adding tests for further modification to the new reflectometer ip
This commit is contained in:
otroubi
@@ -1,75 +0,0 @@
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TOPLEVEL_LANG = verilog
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SIM ?= verilator
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PWD := $(shell pwd)
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WRAP_DIR = $(PWD)/../src
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RTL_CTRL_DIR = $(PWD)/../../controller_new/src
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RTL_ACCUM_DIR = $(PWD)/../../accum/src
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RTL_GENERATOR_DIR = $(PWD)/../../generator/src
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RTL_SAMPLER_DIR = $(PWD)/../../sampler/src
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RTL_ADC_DAC_MODELS_DIR = $(PWD)/../reflectometer_base
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LIBS_DIR = $(PWD)/../../../external/rtl_libs
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#axi primitives
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VERILOG_SOURCES += $(LIBS_DIR)/axi/rtl/axi_pkg.sv
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VERILOG_SOURCES += $(LIBS_DIR)/axi/rtl/axi_if.sv
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VERILOG_SOURCES += $(LIBS_DIR)/axi/rtl/axis_if.sv
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VERILOG_SOURCES += $(LIBS_DIR)/axi/axi_reg/axi4l_reg_map.sv
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#dma primitives
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VERILOG_SOURCES += $(RTL_CTRL_DIR)/dma_reg_pkg.sv
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VERILOG_SOURCES += $(LIBS_DIR)/external/verilog-axi/rtl/axi_dma_rd.v
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VERILOG_SOURCES += $(LIBS_DIR)/external/verilog-axi/rtl/axi_dma_wr.v
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VERILOG_SOURCES += $(LIBS_DIR)/external/verilog-axi/rtl/axi_dma.v
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VERILOG_SOURCES += $(WRAP_DIR)/axi_dma_wrapper_if.sv
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# controller primitives
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VERILOG_SOURCES += $(RTL_CTRL_DIR)/controller.sv
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VERILOG_SOURCES += $(RTL_CTRL_DIR)/dma_controller.sv
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VERILOG_SOURCES += $(RTL_CTRL_DIR)/shaper_axis_desc.sv
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VERILOG_SOURCES += $(RTL_CTRL_DIR)/shaper_axis_status.sv
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VERILOG_SOURCES += $(RTL_CTRL_DIR)/controller_wrapper_axil.sv
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VERILOG_SOURCES += $(RTL_CTRL_DIR)/axi4l_reg_map_controller_pkg.sv
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VERILOG_SOURCES += $(RTL_CTRL_DIR)/axis_defaults_helper.sv
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VERILOG_SOURCES += $(RTL_CTRL_DIR)/axi4l_reg_map_controller.sv
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# accumulator primitives
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VERILOG_SOURCES += $(RTL_ACCUM_DIR)/adder.sv
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VERILOG_SOURCES += $(RTL_ACCUM_DIR)/accum.sv
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VERILOG_SOURCES += $(RTL_ACCUM_DIR)/out_axis_fifo.sv
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VERILOG_SOURCES += $(RTL_ACCUM_DIR)/accum_top.sv
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# generator primitives
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VERILOG_SOURCES += $(RTL_GENERATOR_DIR)/generator.sv
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#sampler_primitives
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VERILOG_SOURCES += $(RTL_SAMPLER_DIR)/sampler.sv
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# project primitives
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VERILOG_SOURCES += $(WRAP_DIR)/reflectometer_ip.sv
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VERILOG_SOURCES += $(WRAP_DIR)/reflectometer_and_dma_wrapper.sv
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# testbench primitives
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VERILOG_SOURCES += $(RTL_ADC_DAC_MODELS_DIR)/adc_model.sv
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VERILOG_SOURCES += $(RTL_ADC_DAC_MODELS_DIR)/dac_model.sv
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VERILOG_SOURCES += $(PWD)/tb_reflectometer_and_dma_wrapper.sv
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TOPLEVEL = tb_reflectometer_and_dma_wrapper
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MODULE = test_reflectometer_and_dma
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ifeq ($(SIM),verilator)
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EXTRA_ARGS += --trace --trace-structs
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EXTRA_ARGS += -I$(LIBS_DIR)/axi/rtl/
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COMPILE_ARGS += -Wno-fatal
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COMPILE_ARGS += -I$(LIBS_DIR)/axi/rtl/
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EXTRA_ARGS += --trace
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EXTRA_ARGS += --trace-structs
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EXTRA_ARGS += --public-flat-rw
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EXTRA_ARGS += -Wno-fatal
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EXTRA_ARGS += --timing
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endif
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include $(shell cocotb-config --makefiles)/Makefile.sim
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@@ -0,0 +1,60 @@
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# SPDX-License-Identifier: MIT
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#
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# Copyright (c) 2025 FPGA Ninja, LLC
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#
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# Authors:
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# - Alex Forencich
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#
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# FPGA settings
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FPGA_PART = xc7a100tfgg484-2
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FPGA_TOP = reflectometer_top
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FPGA_ARCH = artix7
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SIM_TOP = reflectometer_tb
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RTL_DIR = ../../rtl
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include ../../scripts/vivado.mk
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INC_FILES += interfaces.svh
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TB_FILES += reflectometer_tb.sv
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SYN_FILES += reflectometer.sv
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SYN_FILES += dac_model.sv
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SYN_FILES += adc_model.sv
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SYN_FILES += reflectometer_tb.sv
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SYN_FILES += $(sort $(shell find ../../rtl -type f \( -name '*.v' -o -name '*.sv' \)))
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XCI_FILES = $(sort $(shell find ../../rtl/ethernet-udp/src -type f -name '*.xci'))
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XCI_FILES += $(sort $(shell find ip/ -type f -name '*.xci'))
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XDC_FILES += ../../constraints/ax7102.xdc
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XDC_FILES += debug.xdc
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program: $(PROJECT).bit
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echo "open_hw_manager" > program.tcl
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echo "connect_hw_server" >> program.tcl
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echo "open_hw_target" >> program.tcl
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echo "current_hw_device [lindex [get_hw_devices] 0]" >> program.tcl
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echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> program.tcl
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echo "set_property PROGRAM.FILE {$(PROJECT).bit} [current_hw_device]" >> program.tcl
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echo "program_hw_devices [current_hw_device]" >> program.tcl
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echo "exit" >> program.tcl
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vivado -nojournal -nolog -mode batch -source program.tcl
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$(PROJECT).mcs $(PROJECT).prm: $(PROJECT).bit
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echo "write_cfgmem -force -format mcs -size 16 -interface SPIx4 -loadbit {up 0x0000000 $*.bit} -checksum -file $*.mcs" > generate_mcs.tcl
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echo "exit" >> generate_mcs.tcl
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vivado -nojournal -nolog -mode batch -source generate_mcs.tcl
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mkdir -p rev
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COUNT=100; \
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while [ -e rev/$*_rev$$COUNT.bit ]; \
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do COUNT=$$((COUNT+1)); done; \
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COUNT=$$((COUNT-1)); \
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for x in .mcs .prm; \
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do cp $*$$x rev/$*_rev$$COUNT$$x; \
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echo "Output: rev/$*_rev$$COUNT$$x"; done;
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@@ -0,0 +1,59 @@
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// AN9238 virtual ADC model (1 port)
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module virtual_adc_model #(
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parameter int unsigned ADC_DATA_WIDTH = 12,
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// Bipolar input range: +/- VOLTAGE_RANGE
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parameter real VOLTAGE_RANGE = 1.0,
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// Analog input correction
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parameter real VOLTAGE_GAIN = 0.2,
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parameter real GROUND_BIAS = 0.0,
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// ADC timing parameters
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parameter time CONVERSION_DELAY = 250ps
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)(
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input logic clk_i,
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input real voltage_i,
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output logic otr_o,
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output logic [ADC_DATA_WIDTH-1:0] data_o
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);
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localparam int unsigned ZERO_CODE = (1 << (ADC_DATA_WIDTH - 1));
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localparam real VOLTAGE_STEP = (2 * VOLTAGE_RANGE) / real'((1 << ADC_DATA_WIDTH) - 1);
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real voltage_corrected;
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//------------------------------------------------------------
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// Convert analog voltage to ADC code
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//------------------------------------------------------------
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function automatic logic [ADC_DATA_WIDTH-1:0] voltage_to_code( input real voltage );
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if (voltage <= -VOLTAGE_RANGE) return '0;
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if (voltage >= VOLTAGE_RANGE) return {ADC_DATA_WIDTH{1'b1}};
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return $rtoi(voltage / VOLTAGE_STEP + real'((ZERO_CODE)) + 0.5);
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endfunction
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function automatic logic range_check( input real voltage );
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real v_abs = (voltage < 0.0) ? -voltage : voltage;
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return v_abs >= VOLTAGE_RANGE;
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endfunction
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//------------------------------------------------------------
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// Initial state
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//------------------------------------------------------------
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initial begin
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data_o = ZERO_CODE; // 0V
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otr_o = 0;
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end
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//------------------------------------------------------------
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// Update analog output
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//------------------------------------------------------------
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always @(posedge clk_i) begin
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voltage_corrected = (voltage_i - GROUND_BIAS) * VOLTAGE_GAIN;
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data_o <= #(CONVERSION_DELAY) voltage_to_code(voltage_corrected);
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otr_o <= #(CONVERSION_DELAY) range_check(voltage_corrected);
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end
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endmodule
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@@ -0,0 +1,58 @@
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// AN9767 model (1 port)
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module virtual_dac_model #(
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parameter int unsigned DAC_DATA_WIDTH = 14,
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// Bipolar output range: +/- VOLTAGE_RANGE
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parameter real VOLTAGE_RANGE = 5.0,
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// Analog output correction
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parameter real VOLTAGE_GAIN = 1.0,
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parameter real GROUND_BIAS = 0.0,
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// DAC timing parameters
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parameter time TRANSMISSION_DELAY = 150ps,
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parameter time CONVERSION_DELAY = 150ps
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)(
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input logic clk_i,
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input logic wrt_i,
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input logic [DAC_DATA_WIDTH-1:0] data_i,
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output real voltage_o
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);
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localparam int unsigned ZERO_CODE = (1 << (DAC_DATA_WIDTH - 1));
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localparam real VOLTAGE_STEP = (2 * VOLTAGE_RANGE) / real'((1 << DAC_DATA_WIDTH) - 1);
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logic [DAC_DATA_WIDTH-1:0] dac_code;
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//------------------------------------------------------------
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// Convert DAC code to analog voltage
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//------------------------------------------------------------
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function automatic real code_to_voltage( input logic [DAC_DATA_WIDTH-1:0] code);
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return (int'(code) - int'(ZERO_CODE)) * VOLTAGE_STEP;
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endfunction
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//------------------------------------------------------------
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// Initial state
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//------------------------------------------------------------
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initial begin
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dac_code = '0;
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voltage_o = code_to_voltage('0) * VOLTAGE_GAIN + GROUND_BIAS;
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end
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//------------------------------------------------------------
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// Latch new DAC code
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//------------------------------------------------------------
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always @(posedge wrt_i) begin
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dac_code <= #(TRANSMISSION_DELAY) data_i;
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end
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//------------------------------------------------------------
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// Update analog output
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//------------------------------------------------------------
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always @(posedge clk_i) begin
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voltage_o <= #(CONVERSION_DELAY) code_to_voltage(dac_code) * VOLTAGE_GAIN + GROUND_BIAS;
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end
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endmodule
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+4
-2
@@ -1,7 +1,9 @@
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# Primary clocks
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create_clock -name ref_clock -period 5.000 [get_ports ctrl_clk]
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create_clock -name ref_clock -period 5.000 [get_ports clk_in]
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create_clock -name phy_rx_clock -period 8.000 [get_ports clk_m_axis]
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create_clock -name phy_tx_clock -period 8.000 [get_ports clk_s_axis]
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set clk_125_name [get_clocks -of_objects [get_pins generator_inst/clk_dac_125]]
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set clk_65_name [get_clocks -of_objects [get_pins accumulator_top_inst/clk_adc_65]]
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set clk_65_name [get_clocks -of_objects [get_pins accumulator_top_dut/clk_adc_65]]
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set_clock_groups -asynchronous -group $clk_125_name -group $clk_65_name
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@@ -0,0 +1,130 @@
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`ifndef AXIS_INTERFACE_SVH
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`define AXIS_INTERFACE_SVH
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interface axis_if #(
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parameter int DATA_WIDTH = 8
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)(
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input logic clk,
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input logic rst_n
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);
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// Сигналы шины AXI-Stream
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logic [DATA_WIDTH-1:0] tdata;
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logic tvalid;
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logic tlast;
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logic tready;
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initial begin // Default values
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tdata = 'x;
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tvalid = 1'b0;
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tlast = 1'b0;
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tready = 1'b0;
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end
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// Master Clocking Block (для отправки данных из TB)
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clocking drv_cb @(posedge clk);
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default input #1step output #100ps;
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output tdata, tvalid, tlast;
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input tready;
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endclocking
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// Slave Clocking Block (для приема данных в TB с генерацией tready)
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clocking slv_cb @(posedge clk);
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default input #1step output #100ps;
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input tdata, tvalid, tlast;
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output tready;
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endclocking
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// Passive Monitor Clocking Block
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clocking mon_cb @(posedge clk);
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default input #1step;
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input tdata, tvalid, tlast, tready;
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endclocking
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modport master (output tdata, tvalid, tlast, input tready);
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modport slave (input tdata, tvalid, tlast, output tready);
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// Модпорт для тестбенча с тасками
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modport tb (
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clocking drv_cb,
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clocking slv_cb,
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clocking mon_cb,
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import master_send,
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import slave_recv,
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import monitor_recv
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);
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// Отправка пакета (Тестбенч выступает как Master)
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task automatic master_send(input logic [DATA_WIDTH-1:0] payload[]);
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if (payload.size() == 0) return;
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@(drv_cb);
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for (int i = 0; i < payload.size(); i++) begin
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drv_cb.tdata <= payload[i];
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drv_cb.tvalid <= 1'b1;
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drv_cb.tlast <= (i == payload.size() - 1);
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forever begin // Ждем подтверждение от слейва пока не получим
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@(drv_cb);
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if (drv_cb.tready === 1'b1) begin
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break;
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end
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end
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end
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// Сбрасываем сигналы после отправки пакета
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drv_cb.tvalid <= 1'b0;
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drv_cb.tlast <= 1'b0;
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drv_cb.tdata <= 'x;
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endtask
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// Прием пакета (Тестбенч выступает как Slave и управляет tready). Не применять если есть реальный Slave (его tready опустится насильно)
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task automatic slave_recv(output logic [DATA_WIDTH-1:0] payload[]);
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logic [DATA_WIDTH-1:0] local_queue[$]; // Внутри таски очередь использовать можно
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slv_cb.tready <= 1'b1; // Показываем, что готовы принимать
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forever begin
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@(slv_cb);
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if (slv_cb.tvalid === 1'b1) begin
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local_queue.push_back(slv_cb.tdata);
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if (slv_cb.tlast === 1'b1) begin
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break; // Пакет закончился
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end
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end
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end
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slv_cb.tready <= 1'b0; // Снимаем готовность
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// Перекладываем из очереди в динамический массив
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payload = new[local_queue.size()](local_queue);
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endtask
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// Прием пакета (Тестбенч выступает как пассивный наблюдатель без tready)
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task automatic monitor_recv(output logic [DATA_WIDTH-1:0] payload[]);
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logic [DATA_WIDTH-1:0] local_queue[$]; // Внутри таски очередь использовать можно
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forever begin
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if (mon_cb.tready === 1'b1) begin
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break; // Дождались слейва
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end
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@(slv_cb);
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end
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forever begin
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@(mon_cb);
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if (mon_cb.tvalid === 1'b1) begin
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local_queue.push_back(mon_cb.tdata);
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if (mon_cb.tlast === 1'b1) begin
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break; // Пакет закончился
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end
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end
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end
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// Перекладываем из очереди в динамический массив
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payload = new[local_queue.size()](local_queue);
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endtask
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endinterface
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`endif // AXIS_INTERFACE_SVH`
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@@ -0,0 +1,373 @@
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`timescale 1ns / 1ps
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`include "interfaces.svh"
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module reflectometer_tb;
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//------------------------------------------------------------
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// Параметры
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//------------------------------------------------------------
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localparam int unsigned DAC_DATA_WIDTH = 14;
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localparam int unsigned ADC_DATA_WIDTH = 12;
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localparam LOGIC_ZERO_LEVEL = 0; // DAC -5V for logic zero
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localparam VOLTAGE_ZERO_LEVEL = 2**(DAC_DATA_WIDTH-1); // DAC 0V for logic zero
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localparam PACK_FACTOR = 1; // not used in TB
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localparam PROCESS_MODE = 0; // 0 - uint, 1 - int. Current accumulator don't support signed sum
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localparam ACCUM_WIDTH = 32; // accumulator number bit witdth
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localparam N_MAX = 4096; // max value of windows to average by experiments
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localparam PACKET_SIZE = 1024; // bytes per UDP packet
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localparam int REQUEST_TIMEOUT = 3 * PACKET_SIZE; // timeout for packet receiving from accumulator
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localparam ZERO_LEVEL = LOGIC_ZERO_LEVEL; // "logic" VS "voltage"
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localparam CLK_ETH_PHY_PERIOD = 8.000; // 125 MHz
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localparam CLK_REF_PERIOD = 5.000; // 200 MHz
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||||
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||||
//------------------------------------------------------------
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// Глобальные перменные
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||||
//------------------------------------------------------------
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||||
int unsigned WINDOW_SIZE = 65; // fixed subwindow size to average by time
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||||
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||||
//------------------------------------------------------------
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||||
// Тактовые сигналы и сброс
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||||
//------------------------------------------------------------
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||||
logic clk_ref = 1'b0; // 200 MHz
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||||
logic clk_eth_phy = 1'b0; // common for RX & TX
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logic rst_n = 1'b0;
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||||
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||||
//------------------------------------------------------------
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||||
// Управление и конфиг DUT
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||||
//------------------------------------------------------------
|
||||
logic [31:0] window_size;
|
||||
// AXI-S интерфейс для управления
|
||||
axis_if axis_control_if (
|
||||
.clk(clk_eth_phy),
|
||||
.rst_n(rst_n)
|
||||
);
|
||||
|
||||
//------------------------------------------------------------
|
||||
// Входы DUT
|
||||
//------------------------------------------------------------
|
||||
// ADC интерфейс
|
||||
wire clk_adc;
|
||||
wire adc_otr;
|
||||
wire [ADC_DATA_WIDTH-1:0] adc_data;
|
||||
|
||||
//------------------------------------------------------------
|
||||
// Выходы
|
||||
//------------------------------------------------------------
|
||||
// Статусы
|
||||
wire mmcm_locked;
|
||||
wire workflow_done;
|
||||
wire processing_done;
|
||||
// DAC интерфейс
|
||||
wire clk_dac;
|
||||
wire dac_wrt;
|
||||
wire [DAC_DATA_WIDTH-1:0] dac_data;
|
||||
// AXI-S интерфейс для данных
|
||||
axis_if axis_accumulator_if (
|
||||
.clk(clk_eth_phy),
|
||||
.rst_n(rst_n)
|
||||
);
|
||||
//------------------------------------------------------------
|
||||
// Внутренние сигналы тестбенча
|
||||
//------------------------------------------------------------
|
||||
// Интерфейс хендшейка с MAC-PHY
|
||||
wire send_request;
|
||||
logic request_ready;
|
||||
// Сигнал между ЦАП и АЦП
|
||||
real signal_voltage;
|
||||
|
||||
//------------------------------------------------------------
|
||||
// Virtual DAC
|
||||
//------------------------------------------------------------
|
||||
virtual_dac_model #( // default voltage range is +/- 5V
|
||||
.DAC_DATA_WIDTH(DAC_DATA_WIDTH)
|
||||
// ,.VOLTAGE_GAIN(2)
|
||||
) virtual_dac (
|
||||
.clk_i(clk_dac),
|
||||
.wrt_i(dac_wrt),
|
||||
.data_i(dac_data),
|
||||
.voltage_o(signal_voltage)
|
||||
);
|
||||
|
||||
//------------------------------------------------------------
|
||||
// Virtual ADC
|
||||
//------------------------------------------------------------
|
||||
virtual_adc_model #( // default voltage range is +/- 5V
|
||||
.ADC_DATA_WIDTH(ADC_DATA_WIDTH)
|
||||
) virtual_adc (
|
||||
.clk_i(clk_adc),
|
||||
.voltage_i(signal_voltage),
|
||||
.otr_o(adc_otr),
|
||||
.data_o(adc_data)
|
||||
);
|
||||
|
||||
//------------------------------------------------------------
|
||||
// Statistics processing
|
||||
//------------------------------------------------------------
|
||||
|
||||
//------------------------------------------------------------
|
||||
// Config handler
|
||||
//------------------------------------------------------------
|
||||
|
||||
//------------------------------------------------------------
|
||||
// DUT
|
||||
//------------------------------------------------------------
|
||||
reflectometer_top #(
|
||||
.DAC_DATA_WIDTH(DAC_DATA_WIDTH),
|
||||
.ADC_DATA_WIDTH(ADC_DATA_WIDTH),
|
||||
.PACK_FACTOR(PACK_FACTOR),
|
||||
.PROCESS_MODE(PROCESS_MODE),
|
||||
.ZERO_LEVEL(ZERO_LEVEL),
|
||||
.ACCUM_WIDTH(ACCUM_WIDTH),
|
||||
.N_MAX(N_MAX),
|
||||
.PACKET_SIZE(PACKET_SIZE)
|
||||
) DUT (
|
||||
.clk_in(clk_ref),
|
||||
.rst_n(rst_n),
|
||||
|
||||
// Status
|
||||
.locked(mmcm_locked),
|
||||
.workflow_done(workflow_done),
|
||||
.processing_done(processing_done),
|
||||
|
||||
// Accumulator AXI-S bus
|
||||
.clk_axis_accumulator(clk_eth_phy), // GMII PHY RX clock
|
||||
.axis_accumulator(axis_accumulator_if.master),
|
||||
|
||||
// Control AXI-S bus
|
||||
.clk_axis_control(clk_eth_phy), // GMII PHY TX clock
|
||||
.axis_control(axis_control_if.slave),
|
||||
.window_size(window_size), // direct signal crutch (old controller)
|
||||
|
||||
// RTL-MAC handshake
|
||||
.request_ready(request_ready),
|
||||
.send_request(send_request),
|
||||
|
||||
// DAC
|
||||
.dac_clk_o(clk_dac),
|
||||
.dac_data(dac_data),
|
||||
.dac_wrt(dac_wrt),
|
||||
|
||||
// ADC
|
||||
.adc_clk_o(clk_adc),
|
||||
.adc_data(adc_data),
|
||||
.adc_otr(adc_otr)
|
||||
);
|
||||
assign window_size = WINDOW_SIZE;
|
||||
|
||||
//------------------------------------------------------------
|
||||
// Тактовые сигналы
|
||||
//------------------------------------------------------------
|
||||
initial begin
|
||||
forever #(CLK_REF_PERIOD/2) clk_ref = ~clk_ref;
|
||||
end
|
||||
initial begin
|
||||
forever #(CLK_ETH_PHY_PERIOD/2) clk_eth_phy = ~clk_eth_phy;
|
||||
end
|
||||
|
||||
//------------------------------------------------------------
|
||||
// Таски для тестирования
|
||||
//------------------------------------------------------------
|
||||
// Таски работы с AXI-Stream
|
||||
task automatic dut_soft_reset(virtual axis_if#(8).tb vif);
|
||||
logic [7:0] tx_packet[];
|
||||
tx_packet = '{8'h0f};
|
||||
vif.master_send(tx_packet);
|
||||
endtask
|
||||
|
||||
task automatic dut_start(virtual axis_if#(8).tb vif);
|
||||
logic [7:0] tx_packet[];
|
||||
tx_packet = '{8'hf0};
|
||||
vif.master_send(tx_packet);
|
||||
endtask
|
||||
|
||||
task automatic dut_send_system_config(
|
||||
virtual axis_if#(8).tb vif,
|
||||
input logic [31:0] pulse_width,
|
||||
input logic [31:0] pulse_period,
|
||||
input logic [15:0] pulse_num,
|
||||
input logic [13:0] pulse_height, // achtung! p_height strictly must have 14 bits of width
|
||||
input logic [31:0] pulse_period_adc,
|
||||
input logic [31:0] window_size
|
||||
);
|
||||
// Создаем временный фиксированный массив и упаковываем всё одной строкой
|
||||
logic [7:0] tx_packet[];
|
||||
|
||||
// Ахтунг, 14-битный ЦАП захардкожен
|
||||
if (DAC_DATA_WIDTH != 14)
|
||||
$display("[WARNING] -dut_send_system_config- Default pulse height (DAC bitwidth) is equal to 14. Be aware, controller packet structure is coded for 14 bits");
|
||||
|
||||
tx_packet = '{
|
||||
8'h88, // Команда
|
||||
pulse_width[7:0], pulse_width[15:8], pulse_width[23:16], pulse_width[31:24],
|
||||
pulse_period[7:0], pulse_period[15:8], pulse_period[23:16], pulse_period[31:24],
|
||||
pulse_num[7:0], pulse_num[15:8], pulse_height[7:0], 8'({2'b00, pulse_height[13:8]}),
|
||||
pulse_period_adc[7:0], pulse_period_adc[15:8], pulse_period_adc[23:16], pulse_period_adc[31:24]
|
||||
};
|
||||
|
||||
vif.master_send(tx_packet);
|
||||
|
||||
// TODO remove for new controller
|
||||
WINDOW_SIZE = window_size;
|
||||
endtask
|
||||
|
||||
// Таски сбора статистики
|
||||
task automatic dut_read_output(
|
||||
virtual axis_if#(8).tb vif,
|
||||
input int sample_num,
|
||||
input bit randomize_recv_delays,
|
||||
output int output_data[]
|
||||
);
|
||||
logic [7:0] rx_packet[];
|
||||
logic [ACCUM_WIDTH-1:0] data_packet[];
|
||||
int numbers_per_packet = PACKET_SIZE/(ACCUM_WIDTH/8);
|
||||
int packet_num = $ceil(real'(sample_num / WINDOW_SIZE) / real'(numbers_per_packet));
|
||||
int timeout_flag = 0;
|
||||
int packet_counter = 0;
|
||||
|
||||
if (sample_num % WINDOW_SIZE) begin
|
||||
$display("[ERROR] -dut_read_output- Sample_num must be multiple of WINDOW_SIZE: %0d %% %0d = %0d", sample_num, WINDOW_SIZE, sample_num % WINDOW_SIZE);
|
||||
$finish;
|
||||
end
|
||||
|
||||
data_packet = new[numbers_per_packet];
|
||||
output_data = new[numbers_per_packet * packet_num];
|
||||
|
||||
// count send_request pulses (equal to number of packets)
|
||||
fork
|
||||
begin : packet_counter_proc
|
||||
forever begin
|
||||
@(posedge clk_eth_phy);
|
||||
if(send_request === 1)
|
||||
packet_counter++;
|
||||
end
|
||||
end
|
||||
join_none
|
||||
|
||||
// Wait until reflectometer done sampling and averaging
|
||||
wait(processing_done == 1);
|
||||
|
||||
// recv loop
|
||||
// если число пакетов превышает заложенное предрассчитанное значение -- ошибка
|
||||
fork : recv_loop_proc
|
||||
begin
|
||||
// packet recv loop
|
||||
forever begin
|
||||
if (packet_counter > packet_num) begin
|
||||
$display("[ERROR] -dut_read_output- Packet overflow detected. Number of data packets exceeds expected amount of packets");
|
||||
$finish;
|
||||
end
|
||||
|
||||
if (randomize_recv_delays)
|
||||
repeat($urandom_range(0, 500)) @(posedge clk_eth_phy);
|
||||
|
||||
timeout_flag = 0;
|
||||
fork : receive_packet_timeout
|
||||
begin
|
||||
request_ready = 1;
|
||||
vif.slave_recv(rx_packet);
|
||||
request_ready = 0;
|
||||
end
|
||||
begin
|
||||
repeat(REQUEST_TIMEOUT) @(posedge clk_eth_phy);
|
||||
timeout_flag = 1;
|
||||
end
|
||||
join_any
|
||||
|
||||
disable receive_packet_timeout;
|
||||
if (timeout_flag) begin
|
||||
$display("[ERROR] -dut_read_output- Timeout detected when receiving packet");
|
||||
$finish;
|
||||
end
|
||||
|
||||
if (rx_packet.size() != PACKET_SIZE) begin
|
||||
$display("[ERROR] -dut_read_output- Wrong packet size received: %0d bytes received, %0d bytes expected", rx_packet.size(), PACKET_SIZE);
|
||||
$finish;
|
||||
end
|
||||
|
||||
// unpack values
|
||||
data_packet = {<< byte {rx_packet}};
|
||||
data_packet = {<< ACCUM_WIDTH {data_packet}};
|
||||
|
||||
// copy and convert values
|
||||
for (int j = 0; j < data_packet.size(); j++) begin
|
||||
output_data[(packet_counter-1) * data_packet.size() + j] = int'(data_packet[j]);
|
||||
end
|
||||
|
||||
end
|
||||
end
|
||||
begin
|
||||
// IP workflow completion event
|
||||
wait(workflow_done == 1);
|
||||
end
|
||||
join_any
|
||||
|
||||
disable recv_loop_proc;
|
||||
disable packet_counter_proc;
|
||||
|
||||
if (packet_counter != packet_num) begin
|
||||
$display("[ERROR] -dut_read_output- Wrong number of packets received: %0d received, %0d expected", packet_counter, packet_num);
|
||||
$finish;
|
||||
end
|
||||
|
||||
endtask
|
||||
|
||||
// Основная таска типового теста
|
||||
// todo
|
||||
|
||||
//------------------------------------------------------------
|
||||
// ОСНОВНОЙ ПРОЦЕСС ТЕСТИРОВАНИЯ
|
||||
//------------------------------------------------------------
|
||||
initial begin
|
||||
int output_data[];
|
||||
|
||||
automatic virtual axis_if.tb control_vif = axis_control_if.tb;
|
||||
automatic virtual axis_if.tb accumulator_vif = axis_accumulator_if.tb;
|
||||
|
||||
$display("[TB] DUT initializaton");
|
||||
// Инициализация
|
||||
request_ready = 0;
|
||||
rst_n = 0;
|
||||
#100;
|
||||
rst_n = 1;
|
||||
wait(mmcm_locked === 1'b1);
|
||||
#150;
|
||||
$display("[TB] MMCM locked");
|
||||
|
||||
dut_soft_reset(control_vif);
|
||||
#100;
|
||||
|
||||
// Тесты
|
||||
$display("[TB] Tests start");
|
||||
dut_send_system_config(
|
||||
.vif(control_vif),
|
||||
.pulse_width(32'd123),
|
||||
.pulse_period(32'd5000),
|
||||
.pulse_num(16'd1),
|
||||
.pulse_height(14'd15000), // 0V
|
||||
.pulse_period_adc(32'd2600),
|
||||
.window_size(1)
|
||||
);
|
||||
#100;
|
||||
dut_start(control_vif);
|
||||
|
||||
dut_read_output(
|
||||
.vif(accumulator_vif),
|
||||
.sample_num(2600),
|
||||
.randomize_recv_delays(0),
|
||||
.output_data(output_data)
|
||||
);
|
||||
#1000;
|
||||
|
||||
$display("Received %0d numbers", output_data.size());
|
||||
for (int i = 0; i < output_data.size(); i++) begin
|
||||
$write("%0d ", output_data[i]);
|
||||
end
|
||||
$display("");
|
||||
|
||||
$display("[TB] ALL PASSED");
|
||||
$finish;
|
||||
end
|
||||
endmodule
|
||||
@@ -0,0 +1,117 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<wave_config>
|
||||
<wave_state>
|
||||
</wave_state>
|
||||
<db_ref_list>
|
||||
<db_ref path="reflectometer_tb_behav.wdb" id="1">
|
||||
<top_modules>
|
||||
<top_module name="glbl" />
|
||||
<top_module name="reflectometer_tb" />
|
||||
</top_modules>
|
||||
</db_ref>
|
||||
</db_ref_list>
|
||||
<zoom_setting>
|
||||
<ZoomStartTime time="0.000 ns"></ZoomStartTime>
|
||||
<ZoomEndTime time="1,506.001 ns"></ZoomEndTime>
|
||||
<Cursor1Time time="1,000.000 ns"></Cursor1Time>
|
||||
</zoom_setting>
|
||||
<column_width_setting>
|
||||
<NameColumnWidth column_width="196"></NameColumnWidth>
|
||||
<ValueColumnWidth column_width="76"></ValueColumnWidth>
|
||||
</column_width_setting>
|
||||
<WVObjectSize size="7" />
|
||||
<wvobject type="logic" fp_name="/reflectometer_tb/rst_n">
|
||||
<obj_property name="ElementShortName">rst_n</obj_property>
|
||||
<obj_property name="ObjectShortName">rst_n</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/reflectometer_tb/mmcm_locked">
|
||||
<obj_property name="ElementShortName">mmcm_locked</obj_property>
|
||||
<obj_property name="ObjectShortName">mmcm_locked</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="group" fp_name="group28">
|
||||
<obj_property name="label">Signal</obj_property>
|
||||
<obj_property name="DisplayName">label</obj_property>
|
||||
<wvobject type="array" fp_name="/reflectometer_tb/dac_data">
|
||||
<obj_property name="ElementShortName">dac_data[13:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">dac_data[13:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="other" fp_name="/reflectometer_tb/signal_voltage">
|
||||
<obj_property name="ElementShortName">signal_voltage</obj_property>
|
||||
<obj_property name="ObjectShortName">signal_voltage</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/reflectometer_tb/adc_data">
|
||||
<obj_property name="ElementShortName">adc_data[11:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">adc_data[11:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/reflectometer_tb/adc_otr">
|
||||
<obj_property name="ElementShortName">adc_otr</obj_property>
|
||||
<obj_property name="ObjectShortName">adc_otr</obj_property>
|
||||
</wvobject>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/reflectometer_tb/send_request">
|
||||
<obj_property name="ElementShortName">send_request</obj_property>
|
||||
<obj_property name="ObjectShortName">send_request</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/reflectometer_tb/request_ready">
|
||||
<obj_property name="ElementShortName">request_ready</obj_property>
|
||||
<obj_property name="ObjectShortName">request_ready</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="group" fp_name="group51">
|
||||
<obj_property name="label">Controller</obj_property>
|
||||
<obj_property name="DisplayName">label</obj_property>
|
||||
<obj_property name="isExpanded"></obj_property>
|
||||
<wvobject type="logic" fp_name="/reflectometer_tb/axis_control_if/clk">
|
||||
<obj_property name="ElementShortName">clk</obj_property>
|
||||
<obj_property name="ObjectShortName">clk</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/reflectometer_tb/axis_control_if/rst_n">
|
||||
<obj_property name="ElementShortName">rst_n</obj_property>
|
||||
<obj_property name="ObjectShortName">rst_n</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/reflectometer_tb/axis_control_if/tdata">
|
||||
<obj_property name="ElementShortName">tdata[7:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">tdata[7:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/reflectometer_tb/axis_control_if/tvalid">
|
||||
<obj_property name="ElementShortName">tvalid</obj_property>
|
||||
<obj_property name="ObjectShortName">tvalid</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/reflectometer_tb/axis_control_if/tlast">
|
||||
<obj_property name="ElementShortName">tlast</obj_property>
|
||||
<obj_property name="ObjectShortName">tlast</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/reflectometer_tb/axis_control_if/tready">
|
||||
<obj_property name="ElementShortName">tready</obj_property>
|
||||
<obj_property name="ObjectShortName">tready</obj_property>
|
||||
</wvobject>
|
||||
</wvobject>
|
||||
<wvobject type="group" fp_name="group52">
|
||||
<obj_property name="label">Accumulator</obj_property>
|
||||
<obj_property name="DisplayName">label</obj_property>
|
||||
<obj_property name="isExpanded"></obj_property>
|
||||
<wvobject type="logic" fp_name="/reflectometer_tb/axis_accumulator_if/clk">
|
||||
<obj_property name="ElementShortName">clk</obj_property>
|
||||
<obj_property name="ObjectShortName">clk</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/reflectometer_tb/axis_accumulator_if/rst_n">
|
||||
<obj_property name="ElementShortName">rst_n</obj_property>
|
||||
<obj_property name="ObjectShortName">rst_n</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/reflectometer_tb/axis_accumulator_if/tdata">
|
||||
<obj_property name="ElementShortName">tdata[7:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">tdata[7:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/reflectometer_tb/axis_accumulator_if/tvalid">
|
||||
<obj_property name="ElementShortName">tvalid</obj_property>
|
||||
<obj_property name="ObjectShortName">tvalid</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/reflectometer_tb/axis_accumulator_if/tlast">
|
||||
<obj_property name="ElementShortName">tlast</obj_property>
|
||||
<obj_property name="ObjectShortName">tlast</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/reflectometer_tb/axis_accumulator_if/tready">
|
||||
<obj_property name="ElementShortName">tready</obj_property>
|
||||
<obj_property name="ObjectShortName">tready</obj_property>
|
||||
</wvobject>
|
||||
</wvobject>
|
||||
</wave_config>
|
||||
@@ -1,282 +0,0 @@
|
||||
import dma_reg_pkg::*;
|
||||
`timescale 1 ns / 1 ns
|
||||
|
||||
module tb_reflectometer_and_dma_wrapper
|
||||
#(
|
||||
// parameters for base reflectometer works
|
||||
parameter int unsigned DAC_DATA_WIDTH = 14,
|
||||
parameter int unsigned ADC_DATA_WIDTH = 12,
|
||||
parameter int unsigned PACK_FACTOR = 1,
|
||||
parameter int unsigned PROCESS_MODE = 0,
|
||||
parameter int unsigned ZERO_LEVEL = 8192,
|
||||
parameter int unsigned ACCUM_WIDTH = 32,
|
||||
parameter int unsigned N_MAX = 4096,
|
||||
parameter int unsigned PACKET_SIZE = 1024,
|
||||
parameter int unsigned RD_FIFO_WIDTH = 32,
|
||||
|
||||
// parameters for DMA and interfaces
|
||||
parameter int unsigned ADDR_W = 16,
|
||||
parameter int unsigned DATA_W = 32,
|
||||
parameter int unsigned USER_W = 1,
|
||||
|
||||
parameter int unsigned DAC_DATA_WIDTH = 12,
|
||||
|
||||
parameter int unsigned AXI_DATA_WIDTH = 32,
|
||||
|
||||
parameter int unsigned AXI_STRB_WIDTH = AXI_DATA_WIDTH / 8,
|
||||
parameter int unsigned AXI_ID_WIDTH = 8,
|
||||
parameter int unsigned AXI_USER_WIDTH = 1,
|
||||
parameter int unsigned AXI_MAX_BURST_LEN = 16,
|
||||
|
||||
parameter int unsigned AXIS_DATA_WIDTH = AXI_DATA_WIDTH,
|
||||
parameter int unsigned AXIS_KEEP_ENABLE = AXIS_DATA_WIDTH > 8,
|
||||
parameter int unsigned AXIS_KEEP_WIDTH = AXIS_DATA_WIDTH / 8,
|
||||
parameter int unsigned AXIS_LAST_ENABLE = 1,
|
||||
parameter int unsigned AXIS_ID_ENABLE = 1,
|
||||
parameter int unsigned AXIS_DEST_ENABLE = 0,
|
||||
parameter int unsigned AXIS_USER_ENABLE = 1,
|
||||
|
||||
parameter int unsigned ENABLE_SG = 0,
|
||||
parameter int unsigned ENABLE_UNALIGNED = 0,
|
||||
|
||||
parameter int unsigned PIPELINE_OUTPUT = 0
|
||||
)
|
||||
(
|
||||
input logic ctrl_clk,
|
||||
input logic rst_n,
|
||||
output wire locked,
|
||||
|
||||
input logic [ADDR_W-1:0] s_axil_awaddr,
|
||||
input logic [2:0] s_axil_awprot,
|
||||
input logic s_axil_awvalid,
|
||||
output logic s_axil_awready,
|
||||
|
||||
input logic [DATA_W-1:0] s_axil_wdata,
|
||||
input logic [DATA_W/8-1:0] s_axil_wstrb,
|
||||
input logic s_axil_wvalid,
|
||||
output logic s_axil_wready,
|
||||
|
||||
output logic [1:0] s_axil_bresp,
|
||||
output logic s_axil_bvalid,
|
||||
input logic s_axil_bready,
|
||||
|
||||
input logic [ADDR_W-1:0] s_axil_araddr,
|
||||
input logic [2:0] s_axil_arprot,
|
||||
input logic s_axil_arvalid,
|
||||
output logic s_axil_arready,
|
||||
|
||||
output logic [DATA_W-1:0] s_axil_rdata,
|
||||
output logic [1:0] s_axil_rresp,
|
||||
output logic s_axil_rvalid,
|
||||
input logic s_axil_rready,
|
||||
|
||||
output wire [AXIS_DATA_WIDTH-1:0] m_axis_read_data_tdata,
|
||||
output wire [AXIS_KEEP_WIDTH-1:0] m_axis_read_data_tkeep,
|
||||
output wire m_axis_read_data_tvalid,
|
||||
input wire m_axis_read_data_tready,
|
||||
output wire m_axis_read_data_tlast,
|
||||
output wire [AXIS_ID_WIDTH-1:0] m_axis_read_data_tid,
|
||||
output wire [AXIS_DEST_WIDTH-1:0] m_axis_read_data_tdest,
|
||||
output wire [AXIS_USER_WIDTH-1:0] m_axis_read_data_tuser,
|
||||
|
||||
output wire [AXI_ID_WIDTH-1:0] m_axi_awid,
|
||||
output wire [AXI_ADDR_WIDTH-1:0] m_axi_awaddr,
|
||||
output wire [7:0] m_axi_awlen,
|
||||
output wire [2:0] m_axi_awsize,
|
||||
output wire [1:0] m_axi_awburst,
|
||||
output wire m_axi_awlock,
|
||||
output wire [3:0] m_axi_awcache,
|
||||
output wire [2:0] m_axi_awprot,
|
||||
output wire m_axi_awvalid,
|
||||
input wire m_axi_awready,
|
||||
output wire [AXI_DATA_WIDTH-1:0] m_axi_wdata,
|
||||
output wire [AXI_STRB_WIDTH-1:0] m_axi_wstrb,
|
||||
output wire m_axi_wlast,
|
||||
output wire m_axi_wvalid,
|
||||
input wire m_axi_wready,
|
||||
input wire [AXI_ID_WIDTH-1:0] m_axi_bid,
|
||||
input wire [1:0] m_axi_bresp,
|
||||
input wire m_axi_bvalid,
|
||||
output wire m_axi_bready,
|
||||
output wire [AXI_ID_WIDTH-1:0] m_axi_arid,
|
||||
output wire [AXI_ADDR_WIDTH-1:0] m_axi_araddr,
|
||||
output wire [7:0] m_axi_arlen,
|
||||
output wire [2:0] m_axi_arsize,
|
||||
output wire [1:0] m_axi_arburst,
|
||||
output wire m_axi_arlock,
|
||||
output wire [3:0] m_axi_arcache,
|
||||
output wire [2:0] m_axi_arprot,
|
||||
output wire m_axi_arvalid,
|
||||
input wire m_axi_arready,
|
||||
input wire [AXI_ID_WIDTH-1:0] m_axi_rid,
|
||||
input wire [AXI_DATA_WIDTH-1:0] m_axi_rdata,
|
||||
input wire [1:0] m_axi_rresp,
|
||||
input wire m_axi_rlast,
|
||||
input wire m_axi_rvalid,
|
||||
output wire m_axi_rready
|
||||
|
||||
);
|
||||
|
||||
logic rst_n;
|
||||
assign rst_n = ~rst;
|
||||
|
||||
// ---------------------------------------------------------------------------
|
||||
// AXI-Lite flat -> axi4l_if
|
||||
// ---------------------------------------------------------------------------
|
||||
|
||||
axi4l_if #(
|
||||
.ADDR_W(ADDR_W),
|
||||
.DATA_W(DATA_W),
|
||||
.USER_W(USER_W)
|
||||
) axil_bus (
|
||||
.aclk(ctrl_clk),
|
||||
.aresetn(rst_n)
|
||||
);
|
||||
|
||||
axi4l_flat_to_if #(
|
||||
.ADDR_W(ADDR_W),
|
||||
.DATA_W(DATA_W),
|
||||
.USER_W(USER_W)
|
||||
) u_axil_flat_to_if (
|
||||
.s_axil_awaddr (s_axil_awaddr),
|
||||
.s_axil_awprot (s_axil_awprot),
|
||||
.s_axil_awvalid(s_axil_awvalid),
|
||||
.s_axil_awready(s_axil_awready),
|
||||
|
||||
.s_axil_wdata (s_axil_wdata),
|
||||
.s_axil_wstrb (s_axil_wstrb),
|
||||
.s_axil_wvalid (s_axil_wvalid),
|
||||
.s_axil_wready (s_axil_wready),
|
||||
|
||||
.s_axil_bresp (s_axil_bresp),
|
||||
.s_axil_bvalid (s_axil_bvalid),
|
||||
.s_axil_bready (s_axil_bready),
|
||||
|
||||
.s_axil_araddr (s_axil_araddr),
|
||||
.s_axil_arprot (s_axil_arprot),
|
||||
.s_axil_arvalid(s_axil_arvalid),
|
||||
.s_axil_arready(s_axil_arready),
|
||||
|
||||
.s_axil_rdata (s_axil_rdata),
|
||||
.s_axil_rresp (s_axil_rresp),
|
||||
.s_axil_rvalid (s_axil_rvalid),
|
||||
.s_axil_rready (s_axil_rready),
|
||||
|
||||
.m_axil(axil_bus)
|
||||
);
|
||||
|
||||
// ---------------------------------------------------------------------------
|
||||
// AXIS interfaces for the updated controller_wrapper_axil
|
||||
// ---------------------------------------------------------------------------
|
||||
|
||||
// AXIS READ DATA DMA MASTER output
|
||||
axis_if #(
|
||||
.DATA_W (AXIS_DATA_WIDTH),
|
||||
.KEEP_W (AXIS_KEEP_WIDTH),
|
||||
.ID_W (AXIS_ID_WIDTH),
|
||||
.DEST_W (AXIS_DEST_WIDTH),
|
||||
.USER_W (AXIS_USER_WIDTH)
|
||||
) read_data (
|
||||
.aclk(ctrl_clk),
|
||||
.aresetn(rst_n)
|
||||
);
|
||||
|
||||
logic [AXIS_KEEP_WIDTH-1:0] unused_read_tstrb;
|
||||
|
||||
axis_if_to_flat #(
|
||||
.DATA_W (AXIS_DATA_WIDTH),
|
||||
.KEEP_W (AXIS_KEEP_WIDTH),
|
||||
.ID_W (AXIS_ID_WIDTH),
|
||||
.DEST_W (AXIS_DEST_WIDTH),
|
||||
.USER_W (AXIS_USER_WIDTH)
|
||||
) u_read_data_if_to_flat (
|
||||
.s_axis(read_data),
|
||||
|
||||
.m_axis_tdata (m_axis_read_data_tdata),
|
||||
.m_axis_tkeep (m_axis_read_data_tkeep),
|
||||
.m_axis_tstrb (unused_read_tstrb),
|
||||
.m_axis_tlast (m_axis_read_data_tlast),
|
||||
.m_axis_tid (m_axis_read_data_tid),
|
||||
.m_axis_tdest (m_axis_read_data_tdest),
|
||||
.m_axis_tuser (m_axis_read_data_tuser),
|
||||
.m_axis_tvalid(m_axis_read_data_tvalid),
|
||||
.m_axis_tready(m_axis_read_data_tready)
|
||||
);
|
||||
|
||||
// Интерфейс хендшейка с MAC-PHY
|
||||
wire send_request;
|
||||
logic request_ready;
|
||||
// Сигнал между ЦАП и АЦП
|
||||
real signal_voltage;
|
||||
|
||||
// ADC интерфейс
|
||||
wire clk_adc;
|
||||
wire adc_otr;
|
||||
wire [ADC_DATA_WIDTH-1:0] adc_data;
|
||||
|
||||
virtual_adc_model #( // default voltage range is +/- 5V
|
||||
.ADC_DATA_WIDTH(ADC_DATA_WIDTH)
|
||||
) virtual_adc (
|
||||
.clk_i(clk_adc),
|
||||
.voltage_i(signal_voltage),
|
||||
.otr_o(adc_otr),
|
||||
.data_o(adc_data)
|
||||
);
|
||||
|
||||
// DAC интерфейс
|
||||
wire clk_dac;
|
||||
wire dac_wrt;
|
||||
wire [DAC_DATA_WIDTH-1:0] dac_data;
|
||||
|
||||
virtual_dac_model #( // default voltage range is +/- 5V
|
||||
.DAC_DATA_WIDTH(DAC_DATA_WIDTH)
|
||||
// ,.VOLTAGE_GAIN(2)
|
||||
) virtual_dac (
|
||||
.clk_i(clk_dac),
|
||||
.wrt_i(dac_wrt),
|
||||
.data_i(dac_data),
|
||||
.voltage_o(signal_voltage)
|
||||
);
|
||||
|
||||
reflectometer_and_dma_wrapper #(
|
||||
.DAC_DATA_WIDTH(DAC_DATA_WIDTH),
|
||||
.ADC_DATA_WIDTH(ADC_DATA_WIDTH),
|
||||
.ADC_DATA_WIDTH(ADC_DATA_WIDTH),
|
||||
.PACK_FACTOR(PACK_FACTOR),
|
||||
.PROCESS_MODE(PROCESS_MODE),
|
||||
.ZERO_LEVEL(ZERO_LEVEL),
|
||||
.ACCUM_WIDTH(ACCUM_WIDTH),
|
||||
.N_MAX(N_MAX),
|
||||
.PACKET_SIZE(PACKET_SIZE),
|
||||
.RD_FIFO_WIDTH(RD_FIFO_WIDTH),
|
||||
|
||||
.AXI_DATA_WIDTH(AXI_DATA_WIDTH),
|
||||
.AXI_STRB_WIDTH(AXI_STRB_WIDTH),
|
||||
.AXI_USER_WIDTH(AXI_USER_WIDTH),
|
||||
.AXI_MAX_BURST_LEN(AXI_MAX_BURST_LEN),
|
||||
.AXIS_DATA_WIDTH(AXIS_DATA_WIDTH),
|
||||
.AXIS_KEEP_ENABLE(AXIS_KEEP_ENABLE),
|
||||
.AXIS_KEEP_WIDTH(AXIS_KEEP_WIDTH),
|
||||
.AXIS_LAST_ENABLE(AXIS_LAST_ENABLE),
|
||||
.AXIS_ID_ENABLE(AXIS_ID_ENABLE),
|
||||
.AXIS_DEST_ENABLE(AXIS_DEST_ENABLE),
|
||||
.AXIS_USER_ENABLE(AXIS_USER_ENABLE),
|
||||
.ENABLE_SG(ENABLE_SG),
|
||||
.ENABLE_UNALIGNED(ENABLE_UNALIGNED)
|
||||
) reflectometer_and_dma_wrapper_dut (
|
||||
.ctrl_clk(ctrl_clk),
|
||||
.rst_n(rst_n),
|
||||
.locked(locked),
|
||||
.s_axil(axil_bus),
|
||||
.m_axi(m_axi),
|
||||
.m_axis_read_data(read_data),
|
||||
|
||||
.dac_clk_o(clk_dac),
|
||||
.dac_data(dac_data),
|
||||
.dac_wrt(dac_wrt),
|
||||
.adc_clk_o(clk_adc),
|
||||
.adc_data(adc_data),
|
||||
.adc_otr(adc_otr)
|
||||
);
|
||||
|
||||
endmodule
|
||||
Reference in New Issue
Block a user