rtl: update accum_top to use dynamic window_size

This commit is contained in:
Phil
2026-07-02 11:33:40 +03:00
parent f0542845b0
commit 5010c42ae3

View File

@ -5,7 +5,6 @@ module accumulator_top
parameter DATA_WIDTH = 12, parameter DATA_WIDTH = 12,
parameter ACCUM_WIDTH = 32, parameter ACCUM_WIDTH = 32,
parameter N_MAX = 4096, parameter N_MAX = 4096,
parameter WINDOW_SIZE = 65,
parameter PACKET_SIZE = 1024, parameter PACKET_SIZE = 1024,
parameter READ_BATCH_SIZE =(PACKET_SIZE*8)/(ACCUM_WIDTH) parameter READ_BATCH_SIZE =(PACKET_SIZE*8)/(ACCUM_WIDTH)
) )
@ -22,6 +21,7 @@ module accumulator_top
input start, input start,
input [31:0] smp_num, input [31:0] smp_num,
input [15:0] seq_num, input [15:0] seq_num,
input [31:0] window_size,
// eth signals // eth signals
input eth_clk_in, input eth_clk_in,
@ -42,36 +42,66 @@ module accumulator_top
wire readout_begin; wire readout_begin;
wire batch_req; wire batch_req;
logic finish_int;
logic finish_int_d;
logic finish_pulse;
logic calc_active;
logic start_accept;
logic [31:0] window_size_reg;
wire [31:0] window_size_safe = (window_size == 32'd0) ? 32'd1 : window_size;
assign finish_pulse = finish_int && !finish_int_d;
assign start_accept = start && !calc_active;
assign finish = finish_int;
// Keep the top copy stable for blocks that start later than the accum itself
always_ff @(posedge clk_in) begin
if (rst) begin
calc_active <= 1'b0;
finish_int_d <= 1'b0;
window_size_reg <= 32'd1;
end else begin
finish_int_d <= finish_int;
if (start_accept) begin
calc_active <= 1'b1;
end else if (finish_pulse) begin
calc_active <= 1'b0;
end
end
end
accumulator #( accumulator #(
.DATA_WIDTH(DATA_WIDTH), .DATA_WIDTH(DATA_WIDTH),
.ACCUM_WIDTH(ACCUM_WIDTH), .ACCUM_WIDTH(ACCUM_WIDTH),
.N_MAX(N_MAX), .N_MAX(N_MAX),
.WINDOW_SIZE(WINDOW_SIZE),
.PACKET_SIZE(PACKET_SIZE) .PACKET_SIZE(PACKET_SIZE)
) accum_main ( ) accum_main (
.clk_in(clk_in), .clk_in(clk_in),
.rst(rst), .rst(rst),
.s_axis_tdata(s_axis_tdata), .s_axis_tdata(s_axis_tdata),
.s_axis_tvalid(s_axis_tvalid), .s_axis_tvalid(s_axis_tvalid),
.start(start), .start(start_accept),
.smp_num(smp_num), .smp_num(smp_num),
.seq_num(seq_num), .seq_num(seq_num),
.window_size(window_size),
.out_data(out_data), .out_data(out_data),
.out_valid(out_valid), .out_valid(out_valid),
.readout_begin(readout_begin), .readout_begin(readout_begin),
.batch_req(batch_req), .batch_req(batch_req),
.finish(finish) .finish(finish_int)
); );
out_axis_fifo #( out_axis_fifo #(
.ACCUM_WIDTH(ACCUM_WIDTH), .ACCUM_WIDTH(ACCUM_WIDTH),
.WINDOW_SIZE(WINDOW_SIZE),
.PACKET_SIZE(PACKET_SIZE) .PACKET_SIZE(PACKET_SIZE)
) output_async_fifo ( ) output_async_fifo (
.eth_clk_in (eth_clk_in), .eth_clk_in (eth_clk_in),
.acc_clk_in (clk_in), .acc_clk_in (clk_in),
.rst (rst), .rst (rst),
.smp_num (smp_num), .smp_num (smp_num),
.window_size (window_size_reg),
.m_axis_tdata (m_axis_tdata), .m_axis_tdata (m_axis_tdata),
.m_axis_tvalid (m_axis_tvalid), .m_axis_tvalid (m_axis_tvalid),
@ -87,6 +117,6 @@ module accumulator_top
.send_req (send_req), .send_req (send_req),
.batch_req (batch_req), .batch_req (batch_req),
.finish (finish) .finish (finish_int)
); );
endmodule endmodule