baulin.fa/reflectometer_fpga_project
2
0
Fork 0
Code Issues 4 Pull Requests Actions Packages Projects Releases Wiki Activity

upd: sync design log verbosity + optimal delay latency

Browse Source
This commit is contained in:
Zer0Nu11
2026-06-19 20:49:17 +03:00
parent d71aaf1650
commit 4fbecd5e30
3 changed files with 25 additions and 21 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
designs/adc_dac_synchoronizer/sync_top.sv
View File

@ -42,7 +42,7 @@ module sync_top
endgenerate endgenerate
generate generate
if (USE_DELAY_LINE) begin if (USE_DELAY_LINE) begin
localparam int DELAY_LENGTH = 0; localparam int DELAY_LENGTH = USE_DELAY_LINE;
logic [DELAY_LENGTH:0][ADC_DATA_WIDTH-1:0] signal_delay_line; logic [DELAY_LENGTH:0][ADC_DATA_WIDTH-1:0] signal_delay_line;
always_ff @(posedge clk_dac) begin always_ff @(posedge clk_dac) begin
signal_delay_line[0] <= internal_wire_singnal; signal_delay_line[0] <= internal_wire_singnal;

34
designs/adc_dac_synchoronizer/tb_sync_top.sv
View File

@ -6,6 +6,7 @@ module tb_top;
// Параметры // Параметры
//------------------------------------------------------------ //------------------------------------------------------------
parameter string ZERO_LEVEL_PARAM = "logic"; // "logic" VS "true" parameter string ZERO_LEVEL_PARAM = "logic"; // "logic" VS "true"
parameter VERBOSE = 1;
localparam DAC_DATA_WIDTH = 14; localparam DAC_DATA_WIDTH = 14;
localparam ADC_DATA_WIDTH = 12; localparam ADC_DATA_WIDTH = 12;
@ -13,7 +14,7 @@ module tb_top;
localparam PROCESS_MODE = 0; localparam PROCESS_MODE = 0;
localparam CLK_DAC_PERIOD = 8; localparam CLK_DAC_PERIOD = 8;
localparam CLK_ADC_PERIOD = 15.385; localparam CLK_ADC_PERIOD = 15.385;
localparam USE_DELAY_LINE = 1; localparam USE_DELAY_LINE = 0;
localparam LOGIC_ZERO_LEVEL = 0; // DAC -5V for logic zero localparam LOGIC_ZERO_LEVEL = 0; // DAC -5V for logic zero
localparam VOLTAGE_ZERO_LEVEL = 2**(DAC_DATA_WIDTH-1); // DAC 0V for logic zero localparam VOLTAGE_ZERO_LEVEL = 2**(DAC_DATA_WIDTH-1); // DAC 0V for logic zero
localparam ZERO_LEVEL = (ZERO_LEVEL_PARAM == "logic") ? LOGIC_ZERO_LEVEL : VOLTAGE_ZERO_LEVEL; localparam ZERO_LEVEL = (ZERO_LEVEL_PARAM == "logic") ? LOGIC_ZERO_LEVEL : VOLTAGE_ZERO_LEVEL;
@ -262,7 +263,9 @@ module tb_top;
average_sync_time += sync_time_stats[i]; average_sync_time += sync_time_stats[i];
average_sync_time /= pulse_num; average_sync_time /= pulse_num;
if (VERBOSE >= 1) begin
$display("[TB] -run_test_case- Pulse test stats:\n\tavearge_pulse_delay: %0.3f\n\taverage_pulse_width: %0.3f\n\taverage_pulse_period: %0.3f\n\taverage_sync_time: %0.3f", avearge_pulse_delay, average_pulse_width, average_pulse_period, average_sync_time); $display("[TB] -run_test_case- Pulse test stats:\n\tavearge_pulse_delay: %0.3f\n\taverage_pulse_width: %0.3f\n\taverage_pulse_period: %0.3f\n\taverage_sync_time: %0.3f", avearge_pulse_delay, average_pulse_width, average_pulse_period, average_sync_time);
end
if (avearge_pulse_delay > CLOCK_DEVIATION * CLK_ADC_PERIOD) begin if (avearge_pulse_delay > CLOCK_DEVIATION * CLK_ADC_PERIOD) begin
$display("[ERROR] -run_test_case- avearge_pulse_delay too big: %0.3f", avearge_pulse_delay); $display("[ERROR] -run_test_case- avearge_pulse_delay too big: %0.3f", avearge_pulse_delay);
@ -296,24 +299,25 @@ module tb_top;
rst_adc = 0; rst_adc = 0;
rst_dac = 0; rst_dac = 0;
$display("[TB] Test 1. Simple test"); $display("[TB] Test 1. Simple test. (1/2)");
// run_test_case( run_test_case(
// .pulse_width(50), .pulse_width(50),
// .pulse_period(125), .pulse_period(125),
// .pulse_height(2**(ADC_DATA_WIDTH-1)), .pulse_height(2**(ADC_DATA_WIDTH-1)),
// .pulse_num(5), .pulse_num(5),
// .sample_num(65), .sample_num(65),
// .skip_reset(0), .skip_reset(0),
// .randomize_start_timing(0), .randomize_start_timing(0),
// .out_of_range_val(0), .out_of_range_val(0),
// .randomize_out_of_range(0) .randomize_out_of_range(0)
// ); );
$display("[TB] Test 1. Simple test. (2/2)");
run_test_case( run_test_case(
.pulse_width(25), .pulse_width(25),
.pulse_period(110), .pulse_period(125),
.pulse_height(2**(ADC_DATA_WIDTH-1)), .pulse_height(2**(ADC_DATA_WIDTH-1)),
.pulse_num(10), .pulse_num(10),
.sample_num(50), .sample_num(65),
.skip_reset(0), .skip_reset(0),
.randomize_start_timing(0), .randomize_start_timing(0),
.out_of_range_val(0), .out_of_range_val(0),

4
rtl/sampler/src/sampler.sv
View File

@ -5,8 +5,7 @@ module sampler
parameter DATA_WIDTH = 12, parameter DATA_WIDTH = 12,
parameter PACK_FACTOR = 1, parameter PACK_FACTOR = 1,
parameter PROCESS_MODE = 0 parameter PROCESS_MODE = 0
) ) (
(
input clk_in, input clk_in,
input rst, input rst,
input [DATA_WIDTH-1:0] data_in, input [DATA_WIDTH-1:0] data_in,
@ -18,6 +17,7 @@ module sampler
output logic m_axis_tvalid, output logic m_axis_tvalid,
output logic done output logic done
); );
logic [DATA_WIDTH-1:0] data_converted; logic [DATA_WIDTH-1:0] data_converted;
logic out_of_range_reg; logic out_of_range_reg;
logic [31:0] smp_num_reg, cnt_smp_num; logic [31:0] smp_num_reg, cnt_smp_num;