upd: sync design log verbosity + optimal delay latency

rtl/sampler/src/sampler.sv

@@ -5,8 +5,7 @@ module sampler
     parameter DATA_WIDTH = 12,
     parameter PACK_FACTOR = 1,
     parameter PROCESS_MODE = 0
-    )
-(
+) (
     input clk_in,
     input rst,
     input [DATA_WIDTH-1:0] data_in,
@@ -17,7 +16,8 @@ module sampler
     output logic [DATA_WIDTH*PACK_FACTOR-1:0]  m_axis_tdata,
     output logic                              m_axis_tvalid,
     output logic done
-    );
+);
+
     logic [DATA_WIDTH-1:0] data_converted;
     logic out_of_range_reg;
     logic [31:0] smp_num_reg, cnt_smp_num;