upd: sync design log verbosity + optimal delay latency

designs/adc_dac_synchoronizer/sync_top.sv

@@ -42,7 +42,7 @@ module sync_top
     endgenerate
     generate
         if (USE_DELAY_LINE) begin
-            localparam int DELAY_LENGTH = 0;
+            localparam int DELAY_LENGTH = USE_DELAY_LINE;
             logic [DELAY_LENGTH:0][ADC_DATA_WIDTH-1:0] signal_delay_line;
             always_ff @(posedge clk_dac) begin
                 signal_delay_line[0] <= internal_wire_singnal;