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upd: TB automation,

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DA->AD delay line for signal integrity
This commit is contained in:
Zer0Nu11
2026-06-19 08:00:00 +03:00
parent fd9280737d
commit 4923f01322
2 changed files with 205 additions and 169 deletions
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25
designs/adc_dac_synchoronizer/sync_top.sv
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@ -6,7 +6,8 @@ module sync_top
parameter int unsigned ADC_DATA_WIDTH = 12, // ADC bit-width
parameter int unsigned PACK_FACTOR = 1, // number of ADC readings per transaction
parameter int unsigned PROCESS_MODE = 0, // representation format of ADC readings (0 - direct code, 1 - 2's completment)
parameter int unsigned ZERO_LEVEL = 0
parameter int unsigned ZERO_LEVEL = 0,
parameter int unsigned USE_DELAY_LINE = 0
)
(
input clk_adc,
@ -16,9 +17,9 @@ module sync_top
input start,
input out_of_range,
input [31:0] pulse_width,
input [31:0] pulse_period,
input [31:0] pulse_period, // DAC counter limit
input [DAC_DATA_WIDTH-1:0] pulse_height,
input [15:0] pulse_num, // DAC counter limit
input [15:0] pulse_num,
input [31:0] smp_num, // ADC counter limit
output [ADC_DATA_WIDTH*PACK_FACTOR-1:0] m_axis_tdata,
output m_axis_tvalid
@ -29,15 +30,29 @@ module sync_top
//------------------------------------------------------------
wire dac_done, dac_request, adc_done, adc_request;
wire [DAC_DATA_WIDTH-1:0] dac_signal;
wire [ADC_DATA_WIDTH-1:0] internal_wire_singnal;
wire [ADC_DATA_WIDTH-1:0] adc_singnal;
generate
if (ADC_DATA_WIDTH > DAC_DATA_WIDTH) begin : g_pad_zeros
assign adc_singnal = { {(ADC_DATA_WIDTH - DAC_DATA_WIDTH){1'b0}}, dac_signal };
assign internal_wire_singnal = { {(ADC_DATA_WIDTH - DAC_DATA_WIDTH){1'b0}}, dac_signal };
end
else begin : g_truncate
assign adc_singnal = dac_signal[ADC_DATA_WIDTH-1:0];
assign internal_wire_singnal = dac_signal[ADC_DATA_WIDTH-1:0];
end
endgenerate
generate
if (USE_DELAY_LINE) begin
localparam int DELAY_LENGTH = 0;
logic [DELAY_LENGTH:0][ADC_DATA_WIDTH-1:0] signal_delay_line;
always_ff @(posedge clk_dac) begin
signal_delay_line[0] <= internal_wire_singnal;
for (int i = 0; i < DELAY_LENGTH; i++)
signal_delay_line[i+1] <= signal_delay_line[i];
end
assign adc_singnal = signal_delay_line[DELAY_LENGTH];
end else
assign adc_singnal = internal_wire_singnal;
endgenerate
//------------------------------------------------------------
// DAC -> ADC CDC