rtl: rework adder for dynamic window_size

rtl/accum/src/adder.sv

@@ -4,12 +4,13 @@
 module adder
 #(
     parameter DATA_WIDTH = 12,
-    parameter WINDOW_SIZE = 4,
     parameter ACCUM_WIDTH = 32
     )
 (
     input clk_in,
     input rst,
+    input start,
+    input [31:0] window_size,
     input [DATA_WIDTH-1:0] s_axis_tdata,
     input s_axis_tvalid,
     
@@ -20,7 +21,10 @@ module adder
     logic [ACCUM_WIDTH-1:0] accum, res;
     logic [DATA_WIDTH-1:0] axis_data;
     logic res_valid, axis_valid;
- (* MARK_DEBUG = "TRUE" *)   logic [15:0] cnt;
+    (* MARK_DEBUG = "TRUE" *) logic [31:0] cnt;
+    logic [31:0] window_size_reg;
+
+    wire [31:0] window_size_safe = (window_size == 32'd0) ? 32'd1 : window_size;
     
     always @(posedge clk_in) begin
         if (rst) begin
@@ -28,12 +32,24 @@ module adder
             cnt <= '0;
             res <= '0;
             res_valid <= 0;
+            axis_data <= '0;
+            axis_valid <= 0;
+            window_size_reg <= 32'd1;
         end else begin
             res_valid <= 0;
+
+            if (start) begin
+                accum <= '0;
+                cnt <= '0;
+                res <= '0;
+                axis_data <= '0;
+                axis_valid <= 0;
+                window_size_reg <= window_size_safe;
+            end else begin
                 axis_data <= s_axis_tdata;
                 axis_valid <= s_axis_tvalid;
-            if ( axis_valid) begin
+                if (axis_valid) begin
-                if (cnt == WINDOW_SIZE-1) begin
+                    if (cnt == window_size_reg - 1) begin
                         res <= accum + axis_data;
                         res_valid <= 1;
                         accum <= '0;
@@ -45,6 +61,7 @@ module adder
                 end
             end
         end
+    end 
    
     assign sum_valid = res_valid;
     assign sum_data = res;