diff --git a/rtl/accum/src/accum.sv b/rtl/accum/src/accum.sv index a1d5af1..df3073b 100644 --- a/rtl/accum/src/accum.sv +++ b/rtl/accum/src/accum.sv @@ -5,7 +5,7 @@ module accumulator parameter DATA_WIDTH = 12, parameter ACCUM_WIDTH = 32, parameter N_MAX = 4096, - parameter PACKET_SIZE = 8, + parameter PACKET_SIZE = 256, parameter READ_BATCH_SIZE =(PACKET_SIZE*8)/(ACCUM_WIDTH) ) ( @@ -23,7 +23,6 @@ module accumulator output readout_begin, input batch_req, input finish, - output logic accum_done ); @@ -186,6 +185,7 @@ module accumulator if (seq_num_reg <= 16'd1) begin cnt_seq_num <= '0; addrb <= '0; + accum_done <= 1; wr_state <= READOUT_START; end else begin // start further accumulation diff --git a/rtl/accum/src/accum_top.sv b/rtl/accum/src/accum_top.sv index 7f4a6af..22e0cea 100644 --- a/rtl/accum/src/accum_top.sv +++ b/rtl/accum/src/accum_top.sv @@ -4,8 +4,9 @@ module accumulator_top #( parameter DATA_WIDTH = 12, parameter ACCUM_WIDTH = 32, + parameter RW_WIDTH = 32, parameter N_MAX = 4096, - parameter PACKET_SIZE = 1024, + parameter PACKET_SIZE = 256, parameter READ_BATCH_SIZE =(PACKET_SIZE*8)/(ACCUM_WIDTH) ) ( @@ -24,12 +25,16 @@ module accumulator_top input [31:0] window_size, // eth signals - input dma_clk_in, + input eth_clk_in, input req_ready, output send_req, // output axis - axis_if.master m_axis_accum, + output logic [RW_WIDTH-1:0] m_axis_tdata, + output logic m_axis_tvalid, + input logic m_axis_tready, + output logic m_axis_tlast, + output logic finish, output logic accum_done ); @@ -94,18 +99,19 @@ module accumulator_top out_axis_fifo #( .ACCUM_WIDTH(ACCUM_WIDTH), - .PACKET_SIZE(PACKET_SIZE) + .PACKET_SIZE(PACKET_SIZE), + .RW_WIDTH(RW_WIDTH) ) output_async_fifo ( - .dma_clk_in (dma_clk_in), + .eth_clk_in (eth_clk_in), .acc_clk_in (clk_in), .rst (rst), .smp_num (smp_num), .window_size (window_size_reg), - .m_axis_tdata (m_axis_accum.req.t.data), - .m_axis_tvalid (m_axis_accum.req.t.valid), - .m_axis_tready (m_axis_accum.resp.ready), - .m_axis_tlast (m_axis_accum.req.t.last), + .m_axis_tdata (m_axis_tdata), + .m_axis_tvalid (m_axis_tvalid), + .m_axis_tready (m_axis_tready), + .m_axis_tlast (m_axis_tlast), .acc_din (out_data), .din_valid (out_valid), diff --git a/rtl/accum/src/out_axis_fifo.sv b/rtl/accum/src/out_axis_fifo.sv index ce9d2e1..2b53b1a 100644 --- a/rtl/accum/src/out_axis_fifo.sv +++ b/rtl/accum/src/out_axis_fifo.sv @@ -1,16 +1,16 @@ module out_axis_fifo #( parameter ACCUM_WIDTH = 32, parameter RW_WIDTH = 32, - parameter PACKET_SIZE = 1024 + parameter PACKET_SIZE = 256 ) ( - input logic dma_clk_in, + input logic eth_clk_in, input logic acc_clk_in, input logic rst, input logic [31:0] smp_num, input logic [31:0] window_size, - // AXI stream master for output, dma_clk_in domain - output logic [RW_WIDTH:0] m_axis_tdata, + // AXI stream master for output, eth_clk_in domain + output logic [RW_WIDTH-1:0] m_axis_tdata, output logic m_axis_tvalid, input logic m_axis_tready, output logic m_axis_tlast, @@ -67,6 +67,12 @@ module out_axis_fifo #( localparam int FIFO_RDEPTH = FIFO_WDEPTH * ACCUM_WIDTH / RW_WIDTH; localparam int RDEPTH_BITS = $clog2(FIFO_RDEPTH) + 1; + + localparam int WR_WORD_BYTES = ACCUM_WIDTH/8; + localparam int RD_WORD_BYTES = RW_WIDTH/8; + + localparam int PACKET_WR_WORDS = PACKET_SIZE / WR_WORD_BYTES; + localparam int PACKET_RD_WORDS = PACKET_SIZE / RD_WORD_BYTES; wire wr_unavail; wire wr_rst_busy; @@ -128,7 +134,7 @@ module out_axis_fifo #( // wait until we can request a word // depends on prog_full signal WR_CHECK: begin - if ((wr_data_count < (FIFO_WDEPTH - (PACKET_SIZE / (ACCUM_WIDTH / 8)))) && ~wr_rst_busy) begin + if ((wr_data_count < (FIFO_WDEPTH - PACKET_WR_WORDS)) && ~wr_rst_busy) begin batch_req <= 1; // should give us exactly PACKET_SIZE * 8 bits // multiplied by window_size, because we count @@ -195,7 +201,7 @@ module out_axis_fifo #( wire rd_valid; wire [RDEPTH_BITS-1:0] rd_data_count; - always_ff @(posedge dma_clk_in) begin + always_ff @(posedge eth_clk_in) begin if (rst_eth) begin rd_state <= RD_IDLE; send_req <= 1'b0; @@ -209,7 +215,7 @@ module out_axis_fifo #( case (rd_state) // wait until fifo has enough data to send RD_IDLE: begin - if (rd_data_count == PACKET_SIZE) begin + if (rd_data_count >= PACKET_RD_WORDS) begin // enough data to send packet, begin rd_state <= RD_CHECK; end @@ -237,7 +243,7 @@ module out_axis_fifo #( m_axis_tvalid <= 1'b1; sent_cnt <= sent_cnt + 1; // final packet of the batch - if (sent_cnt == PACKET_SIZE - 1) begin + if (sent_cnt == PACKET_RD_WORDS-1) begin rd_state <= RD_IDLE; m_axis_tlast <= 1'b1; end @@ -280,10 +286,10 @@ module out_axis_fifo #( .FIFO_READ_LATENCY(1), // DECIMAL .FIFO_WRITE_DEPTH(FIFO_WDEPTH), .FULL_RESET_VALUE(0), - .PROG_EMPTY_THRESH(PACKET_SIZE), - .PROG_FULL_THRESH(PACKET_SIZE / (ACCUM_WIDTH / 8)), + .PROG_EMPTY_THRESH(PACKET_RD_WORDS), + .PROG_FULL_THRESH(PACKET_WR_WORDS), .RD_DATA_COUNT_WIDTH(RDEPTH_BITS), - .READ_DATA_WIDTH(8), // always 8 bit for eth + .READ_DATA_WIDTH(RW_WIDTH), // always 8 bit for eth .READ_MODE("fwft"), .SIM_ASSERT_CHK(1), // DECIMAL; 0=disable simulation messages, 1=enable simulation messages .USE_ADV_FEATURES("1616"), // String @@ -312,7 +318,7 @@ module out_axis_fifo #( - .rd_clk(dma_clk_in), // 1-bit input: Read clock: Used for read operation. rd_clk must be a free running clock. + .rd_clk(eth_clk_in), // 1-bit input: Read clock: Used for read operation. rd_clk must be a free running clock. .rd_en(rd_en), // 1-bit input: Read Enable: If the FIFO is not empty, asserting this signal causes data (on dout) to be read // from the FIFO. Must be held active-low when rd_rst_busy is active high.