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sampler version with debugged OTR and debugged testbench

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otroubi
2026-07-17 13:38:47 +03:00
parent ef65dd1a97
commit 4240604f26
2 changed files with 132 additions and 176 deletions
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180
rtl/sampler/src/sampler.sv
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@ -13,136 +13,78 @@ module sampler
input [31:0] smp_num,
input request,
output logic [DATA_WIDTH*PACK_FACTOR-1:0] m_axis_tdata,
output logic m_axis_tvalid,
output logic [DATA_WIDTH*PACK_FACTOR-1:0] m_axis_tdata,
output logic m_axis_tvalid,
output logic done
);
logic [DATA_WIDTH-1:0] data_converted;
logic out_of_range_reg;
logic [31:0] smp_num_reg, cnt_smp_num;
logic enable;
logic synced;
logic [$clog2(PACK_FACTOR):0] pack_cnt;
generate
if (PROCESS_MODE) begin
always @(posedge clk_in) begin
if (rst) begin
data_converted <= '0;
out_of_range_reg <= 0;
end
else begin
out_of_range_reg <= out_of_range;
if (data_in == {1'b1, {(DATA_WIDTH-1){1'b0}}})
data_converted <= data_in;
else
data_converted <= data_in[DATA_WIDTH-1] ?{1'b1, (~data_in[DATA_WIDTH-2:0] + 1'b1)}:data_in;
end
end
end else begin
always @(posedge clk_in) begin
if (rst) begin
data_converted <= '0;
out_of_range_reg <= 0;
end
else begin
out_of_range_reg <= out_of_range;
data_converted <= data_in;
end
end
end
endgenerate
logic [DATA_WIDTH*PACK_FACTOR-1:0] buffer;
logic buffer_ready;
logic [$clog2(PACK_FACTOR):0] cnt;
generate
if (PACK_FACTOR == 1) begin
always @(posedge clk_in) begin
if (rst) begin
buffer <= '0;
buffer_ready <= 0;
cnt_smp_num <= '0;
smp_num_reg <= '0;
enable <= 0;
done <= 0;
end
else begin
buffer_ready <= 0;
if (!enable) begin
if (done && request) begin
enable <= 1;
done <= 0;
cnt_smp_num <= 0;
smp_num_reg <= smp_num;
end else begin
done <= 1;
end
end else begin
if (cnt_smp_num != smp_num_reg) begin
cnt_smp_num <= cnt_smp_num +1;
buffer_ready <= 1;
// if (!out_of_range_reg) begin
buffer <= data_converted;
// end
end else begin
cnt_smp_num <= '0;
buffer_ready <= 0;
enable <= 0;
buffer <= '0;
end
end
end
end
end else begin
always @(posedge clk_in) begin
if (rst) begin
buffer <= '0;
cnt <= '0;
buffer_ready <= 0;
cnt_smp_num <= '0;
smp_num_reg <= '0;
enable <= 0;
done <= 0;
always_comb begin
data_converted = '0;
if (PROCESS_MODE) begin
if (out_of_range) begin
if (data_in[DATA_WIDTH-1]==1'b1) data_converted = {1'b1, {(DATA_WIDTH-2){1'b0}}};
else if (data_in[DATA_WIDTH-1]==1'b0) data_converted = {1'b0, {(DATA_WIDTH-2){1'b1}}};
end else begin
buffer_ready <= 0;
if (!enable) begin
if (done && request) begin
enable <= 1;
done <= 0;
cnt_smp_num <= 0;
smp_num_reg <= smp_num;
end else begin
done <= 1;
end
if (data_in == {1'b1, {(DATA_WIDTH-1){1'b0}}})
data_converted = data_in;
else
data_converted = data_in[DATA_WIDTH-1] ?{1'b1, (~data_in[DATA_WIDTH-2:0] + 1'b1)}:data_in;
end
end else begin
if (out_of_range) begin
if (data_in[DATA_WIDTH-1]==1'b1) data_converted = '1;
else if (data_in[DATA_WIDTH-1]==1'b0) data_converted = '0;
end else begin
data_converted = data_in;
end
end
end
always_ff @(posedge clk_in) begin
if (rst) begin
m_axis_tdata <= '0;
m_axis_tvalid <= 0;
cnt_smp_num <= '0;
smp_num_reg <= '0;
pack_cnt <= '0;
synced <= 0;
done <= 0;
end else begin
m_axis_tvalid <= 0;
if (!synced) begin
if (done && request) begin
synced <= 1;
done <= 0;
cnt_smp_num <= 0;
smp_num_reg <= smp_num;
end else begin
done <= 1;
end
end else begin
if (cnt_smp_num != smp_num_reg) begin
cnt_smp_num <= cnt_smp_num +1;
m_axis_tdata[pack_cnt*DATA_WIDTH +: DATA_WIDTH] <= data_converted;
if (pack_cnt == PACK_FACTOR-1) begin
pack_cnt <= 0;
m_axis_tvalid <= 1;
end else begin
if (cnt_smp_num != smp_num_reg) begin
cnt_smp_num <= cnt_smp_num +1;
buffer_ready <= 1;
// if (!out_of_range_reg) begin
buffer <= {buffer[DATA_WIDTH*(PACK_FACTOR-1)-1:0], data_converted};
if (cnt == PACK_FACTOR-1) begin
cnt <= 0;
buffer <= {buffer[DATA_WIDTH*(PACK_FACTOR-1)-1:0], data_converted};
end
else begin
cnt <= cnt + 1;
end
// end
end else begin
cnt_smp_num <= '0;
buffer_ready <= 0;
enable <= 0;
cnt <= 0;
end
pack_cnt <= pack_cnt + 1;
end
end else begin
cnt_smp_num <= '0;
pack_cnt <= '0;
synced <= 0;
done <= 1;
m_axis_tdata <= '0;
end
end
end
endgenerate
assign m_axis_tdata = buffer;
assign m_axis_tvalid = buffer_ready;
end
endmodule