fix: better sync for accum fifo

rtl/accum/src/out_axis_fifo.sv

@@ -243,6 +243,27 @@ module out_axis_fifo #(
         end
     end
 
+    logic [ACCUM_WIDTH-1:0] fifo_din_r, acc_din_reg, din_valid_reg;
+    logic                   fifo_wr_en_r;
+
+    always_ff @(posedge acc_clk_in) begin
+        if (rst_acc) begin
+            fifo_din_r   <= '0;
+            fifo_wr_en_r <= 1'b0;
+   
+            din_valid_reg <= 1'b0;
+        end else begin
+            fifo_wr_en_r  <= 1'b0;
+            acc_din_reg <= acc_din;
+            
+            if (!wr_rst_busy && din_valid_reg) begin
+                fifo_din_r   <= acc_din_reg;
+                fifo_wr_en_r  <= 1'b1;
+            end
+
+            din_valid_reg <= din_valid;
+        end
+    end
 
     // xpm_fifo_async: Asynchronous FIFO
     // Xilinx Parameterized Macro, version 2025.1
@@ -290,9 +311,9 @@ module out_axis_fifo #(
 
         .rst(rst),
         
-        .din(acc_din),                     // WRITE_DATA_WIDTH-bit input: Write Data: The input data bus used when writing the FIFO.
+        .din(fifo_din_r),                     // WRITE_DATA_WIDTH-bit input: Write Data: The input data bus used when writing the FIFO.
         .wr_clk(acc_clk_in),               // 1-bit input: Write clock: Used for write operation. wr_clk must be a free running clock.
-        .wr_en(din_valid),
+        .wr_en(fifo_wr_en_r),
 
         .wr_rst_busy(wr_rst_busy)