From 3a2d8eda2b8713be44078b8cd3367063810a48cf Mon Sep 17 00:00:00 2001 From: otroubi Date: Fri, 8 May 2026 19:03:24 +0300 Subject: [PATCH] rtl: reorganised top without eth --- designs/reflectometer_without_eth/Makefile | 0 designs/reflectometer_without_eth/debug.xdc | 153 +++++++++ .../reflectometer.sv | 293 ++++++++++++++++++ 3 files changed, 446 insertions(+) create mode 100644 designs/reflectometer_without_eth/Makefile create mode 100644 designs/reflectometer_without_eth/debug.xdc create mode 100644 designs/reflectometer_without_eth/reflectometer.sv diff --git a/designs/reflectometer_without_eth/Makefile b/designs/reflectometer_without_eth/Makefile new file mode 100644 index 0000000..e69de29 diff --git a/designs/reflectometer_without_eth/debug.xdc b/designs/reflectometer_without_eth/debug.xdc new file mode 100644 index 0000000..8307e09 --- /dev/null +++ b/designs/reflectometer_without_eth/debug.xdc @@ -0,0 +1,153 @@ +set_clock_groups -name ASYNC_UDP_CTRL -asynchronous -group [get_clocks rgmii_rxc] -group [get_clocks clk_out1_clk_wiz_ctrl_inst] -group [get_clocks clk_out2_clk_wiz_ctrl_inst] + + +create_debug_core u_ila_0 ila +set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0] +set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_0] +set_property C_ADV_TRIGGER false [get_debug_cores u_ila_0] +set_property C_DATA_DEPTH 1024 [get_debug_cores u_ila_0] +set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_0] +set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_0] +set_property C_TRIGIN_EN false [get_debug_cores u_ila_0] +set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0] +set_property port_width 1 [get_debug_ports u_ila_0/clk] +connect_debug_port u_ila_0/clk [get_nets [list clk_wiz_ctrl_inst/inst/clk_out2]] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0] +set_property port_width 16 [get_debug_ports u_ila_0/probe0] +connect_debug_port u_ila_0/probe0 [get_nets [list {accumulator_top_dut/accum_main/adder_dut/cnt[0]} {accumulator_top_dut/accum_main/adder_dut/cnt[1]} {accumulator_top_dut/accum_main/adder_dut/cnt[2]} {accumulator_top_dut/accum_main/adder_dut/cnt[3]} {accumulator_top_dut/accum_main/adder_dut/cnt[4]} {accumulator_top_dut/accum_main/adder_dut/cnt[5]} {accumulator_top_dut/accum_main/adder_dut/cnt[6]} {accumulator_top_dut/accum_main/adder_dut/cnt[7]} {accumulator_top_dut/accum_main/adder_dut/cnt[8]} {accumulator_top_dut/accum_main/adder_dut/cnt[9]} {accumulator_top_dut/accum_main/adder_dut/cnt[10]} {accumulator_top_dut/accum_main/adder_dut/cnt[11]} {accumulator_top_dut/accum_main/adder_dut/cnt[12]} {accumulator_top_dut/accum_main/adder_dut/cnt[13]} {accumulator_top_dut/accum_main/adder_dut/cnt[14]} {accumulator_top_dut/accum_main/adder_dut/cnt[15]}]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe1] +set_property port_width 4 [get_debug_ports u_ila_0/probe1] +connect_debug_port u_ila_0/probe1 [get_nets [list {accumulator_top_dut/accum_main/wr_state[0]} {accumulator_top_dut/accum_main/wr_state[1]} {accumulator_top_dut/accum_main/wr_state[2]} {accumulator_top_dut/accum_main/wr_state[3]}]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe2] +set_property port_width 3 [get_debug_ports u_ila_0/probe2] +connect_debug_port u_ila_0/probe2 [get_nets [list {accumulator_top_dut/output_async_fifo/wr_state[0]} {accumulator_top_dut/output_async_fifo/wr_state[1]} {accumulator_top_dut/output_async_fifo/wr_state[2]}]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe3] +set_property port_width 32 [get_debug_ports u_ila_0/probe3] +connect_debug_port u_ila_0/probe3 [get_nets [list {adc_pulse_period[0]} {adc_pulse_period[1]} {adc_pulse_period[2]} {adc_pulse_period[3]} {adc_pulse_period[4]} {adc_pulse_period[5]} {adc_pulse_period[6]} {adc_pulse_period[7]} {adc_pulse_period[8]} {adc_pulse_period[9]} {adc_pulse_period[10]} {adc_pulse_period[11]} {adc_pulse_period[12]} {adc_pulse_period[13]} {adc_pulse_period[14]} {adc_pulse_period[15]} {adc_pulse_period[16]} {adc_pulse_period[17]} {adc_pulse_period[18]} {adc_pulse_period[19]} {adc_pulse_period[20]} {adc_pulse_period[21]} {adc_pulse_period[22]} {adc_pulse_period[23]} {adc_pulse_period[24]} {adc_pulse_period[25]} {adc_pulse_period[26]} {adc_pulse_period[27]} {adc_pulse_period[28]} {adc_pulse_period[29]} {adc_pulse_period[30]} {adc_pulse_period[31]}]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe4] +set_property port_width 12 [get_debug_ports u_ila_0/probe4] +connect_debug_port u_ila_0/probe4 [get_nets [list {ch2_data_IBUF[0]} {ch2_data_IBUF[1]} {ch2_data_IBUF[2]} {ch2_data_IBUF[3]} {ch2_data_IBUF[4]} {ch2_data_IBUF[5]} {ch2_data_IBUF[6]} {ch2_data_IBUF[7]} {ch2_data_IBUF[8]} {ch2_data_IBUF[9]} {ch2_data_IBUF[10]} {ch2_data_IBUF[11]}]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe5] +set_property port_width 16 [get_debug_ports u_ila_0/probe5] +connect_debug_port u_ila_0/probe5 [get_nets [list {adc_pulse_num[0]} {adc_pulse_num[1]} {adc_pulse_num[2]} {adc_pulse_num[3]} {adc_pulse_num[4]} {adc_pulse_num[5]} {adc_pulse_num[6]} {adc_pulse_num[7]} {adc_pulse_num[8]} {adc_pulse_num[9]} {adc_pulse_num[10]} {adc_pulse_num[11]} {adc_pulse_num[12]} {adc_pulse_num[13]} {adc_pulse_num[14]} {adc_pulse_num[15]}]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe6] +set_property port_width 12 [get_debug_ports u_ila_0/probe6] +connect_debug_port u_ila_0/probe6 [get_nets [list {accum_m_axis_tdata[0]} {accum_m_axis_tdata[1]} {accum_m_axis_tdata[2]} {accum_m_axis_tdata[3]} {accum_m_axis_tdata[4]} {accum_m_axis_tdata[5]} {accum_m_axis_tdata[6]} {accum_m_axis_tdata[7]} {accum_m_axis_tdata[8]} {accum_m_axis_tdata[9]} {accum_m_axis_tdata[10]} {accum_m_axis_tdata[11]}]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe7] +set_property port_width 1 [get_debug_ports u_ila_0/probe7] +connect_debug_port u_ila_0/probe7 [get_nets [list acum_m_axis_tvalid]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe8] +set_property port_width 1 [get_debug_ports u_ila_0/probe8] +connect_debug_port u_ila_0/probe8 [get_nets [list adc_rst]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe9] +set_property port_width 1 [get_debug_ports u_ila_0/probe9] +connect_debug_port u_ila_0/probe9 [get_nets [list adc_start]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe10] +set_property port_width 1 [get_debug_ports u_ila_0/probe10] +connect_debug_port u_ila_0/probe10 [get_nets [list finish]] +create_debug_core u_ila_1 ila +set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_1] +set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_1] +set_property C_ADV_TRIGGER false [get_debug_cores u_ila_1] +set_property C_DATA_DEPTH 1024 [get_debug_cores u_ila_1] +set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_1] +set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_1] +set_property C_TRIGIN_EN false [get_debug_cores u_ila_1] +set_property C_TRIGOUT_EN false [get_debug_cores u_ila_1] +set_property port_width 1 [get_debug_ports u_ila_1/clk] +connect_debug_port u_ila_1/clk [get_nets [list clk_wiz_ctrl_inst/inst/clk_out1]] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe0] +set_property port_width 14 [get_debug_ports u_ila_1/probe0] +connect_debug_port u_ila_1/probe0 [get_nets [list {dac_pulse_height[0]} {dac_pulse_height[1]} {dac_pulse_height[2]} {dac_pulse_height[3]} {dac_pulse_height[4]} {dac_pulse_height[5]} {dac_pulse_height[6]} {dac_pulse_height[7]} {dac_pulse_height[8]} {dac_pulse_height[9]} {dac_pulse_height[10]} {dac_pulse_height[11]} {dac_pulse_height[12]} {dac_pulse_height[13]}]] +create_debug_port u_ila_1 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe1] +set_property port_width 1 [get_debug_ports u_ila_1/probe1] +connect_debug_port u_ila_1/probe1 [get_nets [list dac_rst]] +create_debug_port u_ila_1 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe2] +set_property port_width 1 [get_debug_ports u_ila_1/probe2] +connect_debug_port u_ila_1/probe2 [get_nets [list dac_start]] +create_debug_port u_ila_1 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe3] +set_property port_width 1 [get_debug_ports u_ila_1/probe3] +connect_debug_port u_ila_1/probe3 [get_nets [list debug_dac_OBUF]] +create_debug_core u_ila_2 ila +set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_2] +set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_2] +set_property C_ADV_TRIGGER false [get_debug_cores u_ila_2] +set_property C_DATA_DEPTH 1024 [get_debug_cores u_ila_2] +set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_2] +set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_2] +set_property C_TRIGIN_EN false [get_debug_cores u_ila_2] +set_property C_TRIGOUT_EN false [get_debug_cores u_ila_2] +set_property port_width 1 [get_debug_ports u_ila_2/clk] +connect_debug_port u_ila_2/clk [get_nets [list rgmii_rxc_IBUF_BUFG]] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_2/probe0] +set_property port_width 3 [get_debug_ports u_ila_2/probe0] +connect_debug_port u_ila_2/probe0 [get_nets [list {accumulator_top_dut/output_async_fifo/rd_state[0]} {accumulator_top_dut/output_async_fifo/rd_state[1]} {accumulator_top_dut/output_async_fifo/rd_state[2]}]] +create_debug_port u_ila_2 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_2/probe1] +set_property port_width 8 [get_debug_ports u_ila_2/probe1] +connect_debug_port u_ila_2/probe1 [get_nets [list {m_axis_rx_tdata[0]} {m_axis_rx_tdata[1]} {m_axis_rx_tdata[2]} {m_axis_rx_tdata[3]} {m_axis_rx_tdata[4]} {m_axis_rx_tdata[5]} {m_axis_rx_tdata[6]} {m_axis_rx_tdata[7]}]] +create_debug_port u_ila_2 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_2/probe2] +set_property port_width 8 [get_debug_ports u_ila_2/probe2] +connect_debug_port u_ila_2/probe2 [get_nets [list {s_axis_tx_tdata[0]} {s_axis_tx_tdata[1]} {s_axis_tx_tdata[2]} {s_axis_tx_tdata[3]} {s_axis_tx_tdata[4]} {s_axis_tx_tdata[5]} {s_axis_tx_tdata[6]} {s_axis_tx_tdata[7]}]] +create_debug_port u_ila_2 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_2/probe3] +set_property port_width 3 [get_debug_ports u_ila_2/probe3] +connect_debug_port u_ila_2/probe3 [get_nets [list {udp_ctrl_inst/eth_state[0]} {udp_ctrl_inst/eth_state[1]} {udp_ctrl_inst/eth_state[2]}]] +create_debug_port u_ila_2 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_2/probe4] +set_property port_width 1 [get_debug_ports u_ila_2/probe4] +connect_debug_port u_ila_2/probe4 [get_nets [list udp_ctrl_inst/axis_hs]] +create_debug_port u_ila_2 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_2/probe5] +set_property port_width 1 [get_debug_ports u_ila_2/probe5] +connect_debug_port u_ila_2/probe5 [get_nets [list udp_ctrl_inst/busy_flag_eth]] +create_debug_port u_ila_2 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_2/probe6] +set_property port_width 1 [get_debug_ports u_ila_2/probe6] +connect_debug_port u_ila_2/probe6 [get_nets [list m_axis_rx_tlast]] +create_debug_port u_ila_2 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_2/probe7] +set_property port_width 1 [get_debug_ports u_ila_2/probe7] +connect_debug_port u_ila_2/probe7 [get_nets [list m_axis_rx_tready]] +create_debug_port u_ila_2 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_2/probe8] +set_property port_width 1 [get_debug_ports u_ila_2/probe8] +connect_debug_port u_ila_2/probe8 [get_nets [list m_axis_rx_tvalid]] +create_debug_port u_ila_2 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_2/probe9] +set_property port_width 1 [get_debug_ports u_ila_2/probe9] +connect_debug_port u_ila_2/probe9 [get_nets [list req_ready]] +create_debug_port u_ila_2 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_2/probe10] +set_property port_width 1 [get_debug_ports u_ila_2/probe10] +connect_debug_port u_ila_2/probe10 [get_nets [list s_axis_tx_tlast]] +create_debug_port u_ila_2 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_2/probe11] +set_property port_width 1 [get_debug_ports u_ila_2/probe11] +connect_debug_port u_ila_2/probe11 [get_nets [list s_axis_tx_tready]] +create_debug_port u_ila_2 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_2/probe12] +set_property port_width 1 [get_debug_ports u_ila_2/probe12] +connect_debug_port u_ila_2/probe12 [get_nets [list s_axis_tx_tvalid]] +create_debug_port u_ila_2 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_2/probe13] +set_property port_width 1 [get_debug_ports u_ila_2/probe13] +connect_debug_port u_ila_2/probe13 [get_nets [list send_req]] +set_property C_CLK_INPUT_FREQ_HZ 300000000 [get_debug_cores dbg_hub] +set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub] +set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub] +connect_debug_port dbg_hub/clk [get_nets rgmii_rxc_IBUF_BUFG] diff --git a/designs/reflectometer_without_eth/reflectometer.sv b/designs/reflectometer_without_eth/reflectometer.sv new file mode 100644 index 0000000..2659afa --- /dev/null +++ b/designs/reflectometer_without_eth/reflectometer.sv @@ -0,0 +1,293 @@ +`timescale 1 ns / 1 ns + +module reflectometer_top #( + parameter int unsigned DAC_DATA_WIDTH = 14, + parameter int unsigned ADC_DATA_WIDTH = 12, + parameter PACK_FACTOR = 1, + parameter PROCESS_MODE = 0, + parameter ACCUM_WIDTH = 32, + parameter N_MAX = 4096, + parameter WINDOW_SIZE = 65, + parameter PACKET_SIZE = 1024 +)( + input sys_clk_p, + input sys_clk_n, + input rst_n, + + output [3:0] led, + + input gmii_rx_clk, + input gmii_tx_clk, + + (* MARK_DEBUG="true" *) output logic [7:0] s_axis_tx_tdata, + (* MARK_DEBUG="true" *) output logic s_axis_tx_tvalid, + (* MARK_DEBUG="true" *) input logic s_axis_tx_tready, + (* MARK_DEBUG="true" *) output logic s_axis_tx_tlast, + + (* MARK_DEBUG="true" *) input wire [7:0] m_axis_rx_tdata, + (* MARK_DEBUG="true" *) input wire m_axis_rx_tvalid, + (* MARK_DEBUG="true" *) input wire m_axis_rx_tlast, + (* MARK_DEBUG="true" *) output wire m_axis_rx_tready, + + // axis_mac + + (* MARK_DEBUG="true" *) input logic req_ready, + (* MARK_DEBUG="true" *) output logic send_req, + + // DAC + + (* MARK_DEBUG="true" *) output wire [DAC_DATA_WIDTH-1:0] p2_data, + (* MARK_DEBUG="true" *) output wire p2_wrt, + + // ADC + output ch2_clk, + (* MARK_DEBUG="true" *) input [ADC_DATA_WIDTH-1:0] ch2_data, + input ch2_otr + +); + // temp + + wire p2_wrt; + wire [13:0] p2_data; + + + // ------------------------------------------------------------------------- + // System clock buffer (200 MHz differential input) + // ------------------------------------------------------------------------- + IBUFDS sys_clk_ibufgds ( + .O (sys_clk), + .I (sys_clk_p), + .IB (sys_clk_n) + ); + + // ------------------------------------------------------------------------- + // IDELAYCTRL + // ------------------------------------------------------------------------- + (* IODELAY_GROUP = "rgmii_idelay_group" *) + IDELAYCTRL IDELAYCTRL_inst ( + .RDY (), + .REFCLK (sys_clk), + .RST (1'b0) + ); + + // ------------------------------------------------------------------------- + // Generated clocks for controller + // Need to create this IP in Vivado: + // input : 200 MHz + // output0: 130 MHz + // output1: 65 MHz + // ------------------------------------------------------------------------- + wire dac_clk; + wire adc_clk; + wire clk_wiz_locked; + + clk_wiz_ctrl_inst clk_wiz_ctrl_inst ( + .clk_in1 (sys_clk), + .reset (~rst_n), + .clk_out1 (dac_clk), // 130 MHz + .clk_out2 (adc_clk), // 65 MHz + .locked (clk_wiz_locked) + ); + + // ------------------------------------------------------------------------- + // axis_mac interface + // RX stream from Ethernet goes into controller + // TX stream is unused for now + // ------------------------------------------------------------------------- + (* MARK_DEBUG="true" *) logic req_ready; + (* MARK_DEBUG="true" *) logic send_req; + + + + // ------------------------------------------------------------------------- + // Controller reset + // Use both external reset and clk_wiz lock + // ------------------------------------------------------------------------- + wire ctrl_rst_n = rst_n & clk_wiz_locked; + + + (* MARK_DEBUG="true" *) logic finish; + + // Controller outputs to debug + (* MARK_DEBUG="true" *) wire [31:0] dac_pulse_width; + (* MARK_DEBUG="true" *) wire [31:0] dac_pulse_period; + (* MARK_DEBUG="true" *) wire [DAC_DATA_WIDTH-1:0] dac_pulse_height; + (* MARK_DEBUG="true" *) wire [15:0] dac_pulse_num; + + (* MARK_DEBUG="true" *) wire [31:0] adc_pulse_period; + (* MARK_DEBUG="true" *) wire [15:0] adc_pulse_num; + + (* MARK_DEBUG="true" *) wire dac_start; + (* MARK_DEBUG="true" *) wire adc_start; + (* MARK_DEBUG="true" *) wire dac_rst; + (* MARK_DEBUG="true" *) wire adc_rst; + + + // ------------------------------------------------------------------------- + // Controller + // ETH domain = gmii_rx_clk, because RX AXI master comes from axis_mac RX side + // ------------------------------------------------------------------------- + control #( + .DAC_DATA_WIDTH(DAC_DATA_WIDTH) + ) udp_ctrl_inst ( + .eth_clk_in (gmii_rx_clk), + .dac_clk_in (dac_clk), + .adc_clk_in (adc_clk), + .rst_n (ctrl_rst_n), + + .s_axis_tdata (m_axis_rx_tdata), + .s_axis_tvalid (m_axis_rx_tvalid), + .s_axis_tready (m_axis_rx_tready), + .s_axis_tlast (m_axis_rx_tlast), + + .finish (finish), + + .dac_pulse_width (dac_pulse_width), + .dac_pulse_period (dac_pulse_period), + .dac_pulse_height (dac_pulse_height), + .dac_pulse_num (dac_pulse_num), + + .adc_pulse_period (adc_pulse_period), + .adc_pulse_num (adc_pulse_num), + + .dac_start (dac_start), + .adc_start (adc_start), + + .dac_rst (dac_rst), + .adc_rst (adc_rst) + ); + + // ------------------------------------------------------------------------- + // DAC + // ------------------------------------------------------------------------- + + (* MARK_DEBUG="true" *) logic sample_req; + (* MARK_DEBUG="true" *) logic sample_req_sync1; + (* MARK_DEBUG="true" *) logic sample_req_sync2; + (* MARK_DEBUG="true" *) logic sample_req_sync3; + + (* MARK_DEBUG="true" *) logic sample_done; + (* MARK_DEBUG="true" *) logic sample_done_sync1; + (* MARK_DEBUG="true" *) logic sample_done_sync2; + (* MARK_DEBUG="true" *) logic sample_done_sync3; + + //------------------------------------------------------------ + // DAC -> ADC CDC + //------------------------------------------------------------ + always_ff @(posedge adc_clk or posedge adc_rst) begin + if (adc_rst) begin + sample_req <= 1'b0; + sample_req_sync2 <= 1'b0; + sample_req_sync3 <= 1'b0; + end + else begin + sample_req_sync2 <= sample_req_sync1; + sample_req_sync3 <= sample_req_sync2; + sample_req <= sample_req_sync3; + end + end + + //------------------------------------------------------------ + // ADC -> DAC CDC + //------------------------------------------------------------ + always_ff @(posedge dac_clk or posedge dac_rst) begin + if (dac_rst) begin + sample_done <= 1'b0; + sample_done_sync2 <= 1'b0; + sample_done_sync3 <= 1'b0; + end + else begin + sample_done_sync2 <= sample_done_sync1; + sample_done_sync3 <= sample_done_sync2; + sample_done <= sample_done_sync3; + end + end + + //------------------------------------------------------------ + // Generator + //------------------------------------------------------------ + + generator #( + .DATA_WIDTH(DAC_DATA_WIDTH) + ) generator_inst ( + .clk_in(dac_clk), + .rst(dac_rst), + .start(dac_start), + .pulse_width(dac_pulse_width), + .pulse_period(dac_pulse_period), + .pulse_height(dac_pulse_height), + .pulse_num(dac_pulse_num), + .pulse(p2_wrt), + .pulse_height_out(p2_data), + .sample_done(sample_done), + .sample_req(sample_req_sync1) + ); + +// ------------------------------------------------------------------------- + // ADC + // ------------------------------------------------------------------------- + + (* MARK_DEBUG="true" *) logic [ADC_DATA_WIDTH*PACK_FACTOR-1:0] accum_m_axis_tdata; + (* MARK_DEBUG="true" *) logic acum_m_axis_tvalid; + + sampler + #( + .DATA_WIDTH(ADC_DATA_WIDTH), + .PACK_FACTOR(PACK_FACTOR), + .PROCESS_MODE(PROCESS_MODE) + ) + sampler_dut + ( + .clk_in(adc_clk), + .rst(adc_rst), + .data_in(ch2_data), + .out_of_range(ch2_otr), + .m_axis_tdata(accum_m_axis_tdata), + .m_axis_tvalid(acum_m_axis_tvalid), + .smp_num(adc_pulse_period), + .sample_req(sample_req), + .sample_done(sample_done_sync1) + ); + + // ------------------------------------------------------------------------- + // Accumulator + // ------------------------------------------------------------------------- + + accumulator_top + #( + .DATA_WIDTH(ADC_DATA_WIDTH), + .ACCUM_WIDTH(ACCUM_WIDTH), + .N_MAX(N_MAX), + .WINDOW_SIZE(WINDOW_SIZE), + .PACKET_SIZE(PACKET_SIZE) + ) + accumulator_top_dut + ( + .clk_in(adc_clk), + .rst(adc_rst), + .s_axis_tdata(accum_m_axis_tdata), + .s_axis_tvalid(acum_m_axis_tvalid), + .start(adc_start), + .smp_num(adc_pulse_period), + .seq_num(adc_pulse_num), + + .eth_clk_in(gmii_tx_clk), + .req_ready(req_ready), + .send_req(send_req), + .m_axis_tdata(s_axis_tx_tdata), + .m_axis_tvalid(s_axis_tx_tvalid), + .m_axis_tready(s_axis_tx_tready), + .m_axis_tlast(s_axis_tx_tlast), + + .finish(finish) + ); + + + // ------------------------------------------------------------------------- + // Simple LED status + // ------------------------------------------------------------------------- + assign led[0] = clk_wiz_locked; + assign led[1] = m_axis_rx_tvalid; + assign led[2] = dac_start; + +endmodule \ No newline at end of file