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improved readability

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otroubi
2026-07-31 14:05:07 +03:00
parent ed38e377a6
commit 345344e8e2
1 changed files with 2 additions and 2 deletions
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designs/controller_dma_connective/tests/tb_controller_dma_wrapper_axil.sv
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@@ -53,7 +53,7 @@ module tb_controller_wrapper_axil #(
output logic s_axil_rvalid, output logic s_axil_rvalid,
input logic s_axil_rready, input logic s_axil_rready,
input wire [AXIS_DATA_WIDTH-1:0] s_axis_write_data_tdata, input wire [AXIS_DATA_WIDTH-1:0] s_axis_write_data_tdata,
input wire [AXIS_KEEP_WIDTH-1:0] s_axis_write_data_tkeep, input wire [AXIS_KEEP_WIDTH-1:0] s_axis_write_data_tkeep,
input wire s_axis_write_data_tvalid, input wire s_axis_write_data_tvalid,
output wire s_axis_write_data_tready, output wire s_axis_write_data_tready,
@@ -71,7 +71,7 @@ module tb_controller_wrapper_axil #(
output wire [AXIS_DEST_WIDTH-1:0] m_axis_read_data_tdest, output wire [AXIS_DEST_WIDTH-1:0] m_axis_read_data_tdest,
output wire [AXIS_USER_WIDTH-1:0] m_axis_read_data_tuser, output wire [AXIS_USER_WIDTH-1:0] m_axis_read_data_tuser,
output wire [AXI_ID_WIDTH-1:0] m_axi_awid, output wire [AXI_ID_WIDTH-1:0] m_axi_awid,
output wire [AXI_ADDR_WIDTH-1:0] m_axi_awaddr, output wire [AXI_ADDR_WIDTH-1:0] m_axi_awaddr,
output wire [7:0] m_axi_awlen, output wire [7:0] m_axi_awlen,
output wire [2:0] m_axi_awsize, output wire [2:0] m_axi_awsize,