improved readability

designs/controller_dma_connective/tests/tb_controller_dma_wrapper_axil.sv

@@ -53,7 +53,7 @@ module tb_controller_wrapper_axil #(
   output logic                s_axil_rvalid,
   input  logic                s_axil_rready,
 
-  input  wire [AXIS_DATA_WIDTH-1:0] s_axis_write_data_tdata,
+  input  wire [AXIS_DATA_WIDTH-1:0]   s_axis_write_data_tdata,
     input  wire [AXIS_KEEP_WIDTH-1:0] s_axis_write_data_tkeep,
     input  wire                       s_axis_write_data_tvalid,
     output wire                       s_axis_write_data_tready,
@@ -71,7 +71,7 @@ module tb_controller_wrapper_axil #(
     output wire [AXIS_DEST_WIDTH-1:0] m_axis_read_data_tdest,
     output wire [AXIS_USER_WIDTH-1:0] m_axis_read_data_tuser,
 
-     output wire [AXI_ID_WIDTH-1:0]    m_axi_awid,
+     output wire [AXI_ID_WIDTH-1:0]   m_axi_awid,
     output wire [AXI_ADDR_WIDTH-1:0]  m_axi_awaddr,
     output wire [7:0]                 m_axi_awlen,
     output wire [2:0]                 m_axi_awsize,