transferring new controller design

2026-07-28 12:51:05 +03:00
parent c21c9d2ab5
commit 32076b19f7
10 changed files with 1132 additions and 0 deletions
@@ -0,0 +1,42 @@
+package dma_reg_pkg;
+    parameter int unsigned AXI_ADDR_WIDTH  = 16;
+    parameter int unsigned LEN_WIDTH       = 20;
+    parameter int unsigned TAG_WIDTH       = 8;
+    parameter int unsigned AXIS_ID_WIDTH   = 8;
+    parameter int unsigned AXIS_DEST_WIDTH = 8;
+    parameter int unsigned AXIS_USER_WIDTH = 1;
+
+    typedef struct packed {
+    logic [AXIS_USER_WIDTH-1:0] user;
+    logic [AXIS_DEST_WIDTH-1:0] dest;
+    logic [AXIS_ID_WIDTH-1:0]   id;
+    logic [TAG_WIDTH-1:0]       tag;
+    logic [LEN_WIDTH-1:0]       len;
+    logic [AXI_ADDR_WIDTH-1:0]  addr;
+    
+  } dma_read_desc_t;
+
+  typedef struct packed {
+    logic [TAG_WIDTH-1:0]       tag;
+    logic [LEN_WIDTH-1:0]       len;
+    logic [AXI_ADDR_WIDTH-1:0]  addr;
+    
+  } dma_write_desc_t;
+
+  typedef struct packed {
+    logic [3:0]                 error;
+    logic [TAG_WIDTH-1:0]       tag;
+    
+  } dma_read_status_t;
+
+typedef struct packed {
+    logic [3:0]                 error;
+    logic [AXIS_USER_WIDTH-1:0] user;
+    logic [AXIS_DEST_WIDTH-1:0] dest;
+    logic [AXIS_ID_WIDTH-1:0]   id;
+    logic [TAG_WIDTH-1:0]       tag;
+    logic [LEN_WIDTH-1:0]       len;
+    
+  } dma_write_status_t;
+
+endpackage