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rtl: update accum - change window size to signal

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Phil
2026-07-01 14:57:23 +03:00
parent 425c922690
commit 2a3796a60f
1 changed files with 14 additions and 7 deletions
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21
rtl/accum/src/accum.sv
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@ -5,7 +5,6 @@ module accumulator
parameter DATA_WIDTH = 12,
parameter ACCUM_WIDTH = 32,
parameter N_MAX = 4096,
parameter WINDOW_SIZE = 4,
parameter PACKET_SIZE = 8,
parameter READ_BATCH_SIZE =(PACKET_SIZE*8)/(ACCUM_WIDTH)
)
@ -17,6 +16,7 @@ module accumulator
input start,
input [31:0] smp_num,
input [15:0] seq_num,
input [31:0] window_size,
output [ACCUM_WIDTH-1:0] out_data,
output out_valid,
@ -26,6 +26,7 @@ module accumulator
);
logic [31:0] smp_num_reg, cnt_smp_num;
logic [31:0] window_size_reg;
logic [15:0] seq_num_reg, cnt_seq_num;
logic [15:0] cnt_addr, addra, addrb;
@ -61,7 +62,7 @@ module accumulator
logic [15:0] accum_pipe_addr;
logic [ACCUM_WIDTH-1:0] accum_pipe_data;
// case smp_num // WINDOW_SIZE == 1
// case smp_num // window_size == 1
// Then the next sequence can read the same address it is written
logic accum_pipe_bypass_valid;
logic [ACCUM_WIDTH-1:0] accum_pipe_bypass_data;
@ -72,7 +73,10 @@ module accumulator
logic [ACCUM_WIDTH-1:0] accum_write_base;
logic [ACCUM_WIDTH-1:0] accum_write_value;
assign accum_accept_last = (cnt_smp_num + WINDOW_SIZE >= smp_num_reg);
wire [31:0] window_size_safe = (window_size == 32'd0) ? 32'd1 : window_size;
wire start_accept = start && (wr_state == IDLE);
assign accum_accept_last = (cnt_smp_num + window_size_reg >= smp_num_reg);
assign accum_accept_last_all = accum_accept_last && (cnt_seq_num == seq_num_reg - 1);
assign accum_write_base = accum_pipe_bypass_valid ? accum_pipe_bypass_data : data_bram_out;
assign accum_write_value = accum_pipe_data + accum_write_base;
@ -109,6 +113,7 @@ module accumulator
if (rst) begin
smp_num_reg <= '0;
cnt_smp_num <= '0;
window_size_reg <= 32'd1;
seq_num_reg <= '0;
cnt_seq_num <= '0;
cnt_addr <= '0;
@ -152,6 +157,7 @@ module accumulator
if (start) begin
smp_num_reg <= smp_num;
seq_num_reg <= seq_num;
window_size_reg <= window_size_safe;
wr_state <= INIT_MEM;
end
@ -172,7 +178,7 @@ module accumulator
addra <= cnt_addr;
wea <= 1;
if (cnt_smp_num + WINDOW_SIZE >= smp_num_reg) begin
if (cnt_smp_num + window_size_reg >= smp_num_reg) begin
cnt_smp_num <= '0;
cnt_addr <= '0;
@ -186,7 +192,7 @@ module accumulator
wr_state <= ACCUM;
end
end else begin
cnt_smp_num <= cnt_smp_num + WINDOW_SIZE;
cnt_smp_num <= cnt_smp_num + window_size_reg;
cnt_addr <= cnt_addr + 1;
end
end
@ -253,7 +259,7 @@ module accumulator
cnt_seq_num <= cnt_seq_num + 1;
end
end else begin
cnt_smp_num <= cnt_smp_num + WINDOW_SIZE;
cnt_smp_num <= cnt_smp_num + window_size_reg;
cnt_addr <= cnt_addr + 1;
end
end else begin
@ -326,12 +332,13 @@ module accumulator
adder
#(
.DATA_WIDTH(DATA_WIDTH),
.WINDOW_SIZE(WINDOW_SIZE),
.ACCUM_WIDTH(ACCUM_WIDTH)
) adder_dut
(
.clk_in(clk_in),
.rst(rst),
.start(start_accept),
.window_size(window_size),
.s_axis_tdata(s_axis_tdata),
.s_axis_tvalid(s_axis_tvalid),
.sum_data(data),