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rtl: update sampler

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otroubi
2026-04-28 13:10:22 +03:00
parent fc0e710b3e
commit 264c9ecb8e
2 changed files with 206 additions and 34 deletions
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119
rtl/sampler/src/sampler.sv
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@ -5,8 +5,8 @@
module sampler
#(
parameter DATA_WIDTH = 12,
parameter PACK_FACTOR = 3,
parameter PROCESS_MODE = 1
parameter PACK_FACTOR = 1,
parameter PROCESS_MODE = 0
)
(
input clk_in,
@ -19,52 +19,103 @@ module sampler
);
logic [DATA_WIDTH-1:0] data_converted;
logic out_of_range_reg;
generate
if (PROCESS_MODE) begin
always @( posedge clk_in) begin
if (rst) begin
data_converted <= '0;
end else begin
out_of_range_reg <= out_of_range;
if (PROCESS_MODE) begin
if (data_in == 12'b100000000000) begin
always @(posedge clk_in) begin
if (rst) begin
data_converted <= '0;
out_of_range_reg <= 0;
end
else begin
out_of_range_reg <= out_of_range;
if (data_in == {1'b1, {(DATA_WIDTH-1){1'b0}}})
data_converted <= data_in;
end else begin
data_converted <= data_in[DATA_WIDTH-1] ? {1'b1, (~data_in[DATA_WIDTH-2:0] + 1'b1)} : data_in;
end
end else begin
data_converted <= data_in;
else
data_converted <= data_in[DATA_WIDTH-1] ?{1'b1, (~data_in[DATA_WIDTH-2:0] + 1'b1)}:data_in;
end
end
end
end else begin
always @(posedge clk_in) begin
if (rst) begin
data_converted <= '0;
out_of_range_reg <= 0;
end
else begin
out_of_range_reg <= out_of_range;
data_converted <= data_in;
end
end
end
endgenerate
logic [DATA_WIDTH*PACK_FACTOR-1:0] buffer;
logic buffer_ready;
logic [$clog2(PACK_FACTOR):0] cnt;
always @(posedge clk_in) begin
if (rst) begin
buffer <= '0;
cnt <= -1; //
buffer_ready <= 0;
end
else begin
buffer_ready <= 0;
if (!out_of_range_reg) begin
buffer <= {buffer[DATA_WIDTH*(PACK_FACTOR-1)-1:0], data_converted};
if (cnt == PACK_FACTOR-1) begin
cnt <= 0;
generate
if (PACK_FACTOR == 1) begin
always @(posedge clk_in) begin
if (rst) begin
buffer <= '0;
buffer_ready <= 0;
end
else begin
buffer_ready <= 0;
if (!out_of_range_reg) begin
buffer <= data_converted;
buffer_ready <= 1;
buffer <= {buffer[DATA_WIDTH*(PACK_FACTOR-1)-1:0], data_converted};
end
else begin
cnt <= cnt + 1;
end
end
end
end
end else begin
always @(posedge clk_in) begin
if (rst) begin
buffer <= '0;
cnt <= '0; //
buffer_ready <= 0;
end
else begin
buffer_ready <= 0;
if (!out_of_range_reg) begin
buffer <= {buffer[DATA_WIDTH*(PACK_FACTOR-1)-1:0], data_converted};
if (cnt == PACK_FACTOR-1) begin
cnt <= 0;
buffer_ready <= 1;
buffer <= {buffer[DATA_WIDTH*(PACK_FACTOR-1)-1:0], data_converted};
end
else begin
cnt <= cnt + 1;
end
end
end
end
end
endgenerate
// always @(posedge clk_in) begin
// if (rst) begin
// buffer <= '0;
// cnt <= '0; //
// buffer_ready <= 0;
// end
// else begin
// buffer_ready <= 0;
// if (!out_of_range_reg) begin
// buffer <= {buffer[DATA_WIDTH*(PACK_FACTOR-1)-1:0], data_converted};
// if (cnt == PACK_FACTOR-1) begin
// cnt <= 0;
// buffer_ready <= 1;
// buffer <= {buffer[DATA_WIDTH*(PACK_FACTOR-1)-1:0], data_converted};
// end
// else begin
// cnt <= cnt + 1;
// end
// end
// end
// end
assign m_axis_tdata = buffer;
assign m_axis_tvalid = buffer_ready;