From 4923f0132269302a69fc0083f5a441053d616992 Mon Sep 17 00:00:00 2001 From: Zer0Nu11 Date: Fri, 19 Jun 2026 08:00:00 +0300 Subject: [PATCH 1/9] upd: TB automation, DA->AD delay line for signal integrity --- designs/adc_dac_synchoronizer/sync_top.sv | 25 +- designs/adc_dac_synchoronizer/tb_sync_top.sv | 349 ++++++++++--------- 2 files changed, 205 insertions(+), 169 deletions(-) diff --git a/designs/adc_dac_synchoronizer/sync_top.sv b/designs/adc_dac_synchoronizer/sync_top.sv index ea5f28a..1fa1cf6 100644 --- a/designs/adc_dac_synchoronizer/sync_top.sv +++ b/designs/adc_dac_synchoronizer/sync_top.sv @@ -6,7 +6,8 @@ module sync_top parameter int unsigned ADC_DATA_WIDTH = 12, // ADC bit-width parameter int unsigned PACK_FACTOR = 1, // number of ADC readings per transaction parameter int unsigned PROCESS_MODE = 0, // representation format of ADC readings (0 - direct code, 1 - 2's completment) - parameter int unsigned ZERO_LEVEL = 0 + parameter int unsigned ZERO_LEVEL = 0, + parameter int unsigned USE_DELAY_LINE = 0 ) ( input clk_adc, @@ -16,9 +17,9 @@ module sync_top input start, input out_of_range, input [31:0] pulse_width, - input [31:0] pulse_period, + input [31:0] pulse_period, // DAC counter limit input [DAC_DATA_WIDTH-1:0] pulse_height, - input [15:0] pulse_num, // DAC counter limit + input [15:0] pulse_num, input [31:0] smp_num, // ADC counter limit output [ADC_DATA_WIDTH*PACK_FACTOR-1:0] m_axis_tdata, output m_axis_tvalid @@ -29,15 +30,29 @@ module sync_top //------------------------------------------------------------ wire dac_done, dac_request, adc_done, adc_request; wire [DAC_DATA_WIDTH-1:0] dac_signal; + wire [ADC_DATA_WIDTH-1:0] internal_wire_singnal; wire [ADC_DATA_WIDTH-1:0] adc_singnal; generate if (ADC_DATA_WIDTH > DAC_DATA_WIDTH) begin : g_pad_zeros - assign adc_singnal = { {(ADC_DATA_WIDTH - DAC_DATA_WIDTH){1'b0}}, dac_signal }; + assign internal_wire_singnal = { {(ADC_DATA_WIDTH - DAC_DATA_WIDTH){1'b0}}, dac_signal }; end else begin : g_truncate - assign adc_singnal = dac_signal[ADC_DATA_WIDTH-1:0]; + assign internal_wire_singnal = dac_signal[ADC_DATA_WIDTH-1:0]; end endgenerate + generate + if (USE_DELAY_LINE) begin + localparam int DELAY_LENGTH = 0; + logic [DELAY_LENGTH:0][ADC_DATA_WIDTH-1:0] signal_delay_line; + always_ff @(posedge clk_dac) begin + signal_delay_line[0] <= internal_wire_singnal; + for (int i = 0; i < DELAY_LENGTH; i++) + signal_delay_line[i+1] <= signal_delay_line[i]; + end + assign adc_singnal = signal_delay_line[DELAY_LENGTH]; + end else + assign adc_singnal = internal_wire_singnal; + endgenerate //------------------------------------------------------------ // DAC -> ADC CDC diff --git a/designs/adc_dac_synchoronizer/tb_sync_top.sv b/designs/adc_dac_synchoronizer/tb_sync_top.sv index 7737d93..526ea79 100644 --- a/designs/adc_dac_synchoronizer/tb_sync_top.sv +++ b/designs/adc_dac_synchoronizer/tb_sync_top.sv @@ -5,16 +5,20 @@ module tb_top; //------------------------------------------------------------ // Параметры //------------------------------------------------------------ + parameter string ZERO_LEVEL_PARAM = "logic"; // "logic" VS "true" + localparam DAC_DATA_WIDTH = 14; localparam ADC_DATA_WIDTH = 12; localparam PACK_FACTOR = 1; localparam PROCESS_MODE = 0; - localparam LOGIC_ZERO_LEVEL = 0; // DAC -5V for logic zero - localparam VOLTAGE_ZERO_LEVEL = 2**(DAC_DATA_WIDTH-1); // DAC 0V for logic zero localparam CLK_DAC_PERIOD = 8; localparam CLK_ADC_PERIOD = 15.385; + localparam USE_DELAY_LINE = 1; + localparam LOGIC_ZERO_LEVEL = 0; // DAC -5V for logic zero + localparam VOLTAGE_ZERO_LEVEL = 2**(DAC_DATA_WIDTH-1); // DAC 0V for logic zero + localparam ZERO_LEVEL = (ZERO_LEVEL_PARAM == "logic") ? LOGIC_ZERO_LEVEL : VOLTAGE_ZERO_LEVEL; - localparam ZERO_LEVEL = LOGIC_ZERO_LEVEL; // "logic" VS "true" + localparam CLOCK_DEVIATION = 1; // Maximum clock deviation of pulse stats //------------------------------------------------------------ // Тактовые сигналы и сброс @@ -49,7 +53,8 @@ module tb_top; .ADC_DATA_WIDTH(ADC_DATA_WIDTH), .PACK_FACTOR(PACK_FACTOR), .PROCESS_MODE(PROCESS_MODE), - .ZERO_LEVEL(ZERO_LEVEL) + .ZERO_LEVEL(ZERO_LEVEL), + .USE_DELAY_LINE(USE_DELAY_LINE) ) dut ( .clk_adc(clk_adc), .clk_dac(clk_dac), @@ -77,6 +82,11 @@ module tb_top; end // === Таски для тестирования === + // Функция модуля + function automatic real fabs(real val); + return (val < 0.0) ? -val : val; + endfunction + // Таска сброса DAC DUT task automatic reset_dut_dac( input int rst_duration // сколько тактов держать сброс @@ -113,194 +123,205 @@ module tb_top; input logic [31:0] sn // число сэмплов ); // Задаем конфигурационные регистры - @(posedge clk_dac); pulse_width <= w; pulse_period <= p; pulse_num <= n; pulse_height <= h; smp_num <= sn; endtask + + // Основная таска проверки DUT + task automatic run_test_case( + input int pulse_width, + input int pulse_period, + input int pulse_height, + input int pulse_num, + input int sample_num, + input bit skip_reset, + input bit randomize_start_timing, + input bit out_of_range_val, + input bit randomize_out_of_range + ); + int error_flag = 0; + int start_hold_time = 1; + realtime sync_start_time, pulse_start_time, pulse_update_val_time; + realtime sync_time_stats[$], pulse_width_time_stats[$], pulse_period_time_stats[$], pulse_delay_time_stats[$]; + realtime avearge_pulse_delay, average_pulse_width, average_pulse_period, average_sync_time; - // // Таска проверки устойчивости к долгим управляющим импульсам - // task automatic check_impulses; - // // Локальные переменные для хранения случайных параметров - // int rand_start_duration; - // int rand_delay; - // int rand_ack; - // bit rand_first; - // int total_impulse_cycles = 0; + out_of_range = out_of_range_val; - // int pulse_w = 11; - // int pulse_p = 31; - // int pulse_n = 5; - // int pulse_h = 1024; + if (randomize_out_of_range) + fork + begin : randomize_out_of_range_proc + forever begin + @(posedge clk_adc); + out_of_range = $urandom_range(0, 1); + end + end + join_none - // $display("[TB] -check_impulses- Check system stability under random latencies"); + if (!skip_reset) + fork + reset_dut_adc(1); + reset_dut_dac(1); + join - // // Установка конфигурации - // set_config( - // .w(pulse_w), - // .p(pulse_p), - // .n(pulse_n), - // .h(pulse_h) - // ); + set_config( + .w(pulse_width), + .p(pulse_period), + .n(pulse_num), + .h(pulse_height), + .sn(sample_num) + ); - // reset_dut(5); - // repeat(2) @(posedge clk); + if (randomize_start_timing) + start_hold_time = $urandom_range(1, 15); + fork // warning: check not forever + start_dut(start_hold_time); + begin + @(posedge clk_dac); + // старт первой синхронизации + sync_start_time = $realtime; + end + join_none - // // Старт норме 1 такт. Сделаем случайным от 5 до 25 тактов. - // rand_start_duration = $urandom_range(5, 25); - // $display("[TB] Long start: %0d clocks", rand_start_duration); + for (int i = 0; i < pulse_num; i++) begin + @(posedge m_axis_tvalid); + // Старт цикла. Завершение синхронизации + sync_time_stats.push_back($realtime - sync_start_time); + pulse_start_time = $realtime; + + // Начало импульса + if (pulse_height != ZERO_LEVEL) begin + wait(m_axis_tdata != ZERO_LEVEL); + if (m_axis_tdata != pulse_height) begin + $display("[ERROR] -run_test_case- Wrong pulse height: %d. Must be: %d", m_axis_tdata, pulse_height); + $finish; + end + // Фактическое начало импульса. Поступление высокого уровня + pulse_update_val_time = $realtime; + pulse_delay_time_stats.push_back(pulse_update_val_time - pulse_start_time); + wait(m_axis_tdata == ZERO_LEVEL); + pulse_width_time_stats.push_back($realtime - pulse_update_val_time); + end + // Конец импульса + + @(negedge m_axis_tvalid); + // Завершение цикла. Старт синхронизации + pulse_period_time_stats.push_back($realtime - pulse_start_time); + sync_start_time = $realtime; + end - // // Фоновый процесс подсчета тактов импульса - // fork - // begin : counter_proc - // forever begin - // @(negedge clk); // 180 deg. phase shift for "DAC strobing signal" - // if (dac_out == pulse_h) begin - // total_impulse_cycles++; - // end - // end - // end - // join_none + fork // Проверка с таймаутом на лишние циклы + @(posedge m_axis_tvalid); + repeat(20) @(posedge clk_adc); + join_any + if (m_axis_tvalid == 1) begin + $display("[ERROR] -run_test_case- Extra pulse cycle num. More than must be."); + $finish; + end + + if (randomize_out_of_range) + disable randomize_out_of_range_proc; + + // Проверка по статистике. Подсчет средних значений + if (pulse_delay_time_stats.size() != pulse_num) begin + $display("[ERROR] -run_test_case- Size of pulse_delay_time_stats samples not equal to pulse_num"); + $finish; + end + if (pulse_width_time_stats.size() != pulse_num) begin + $display("[ERROR] -run_test_case- Size of pulse_width_time_stats samples not equal to pulse_num"); + $finish; + end + if (pulse_period_time_stats.size() != pulse_num) begin + $display("[ERROR] -run_test_case- Size of pulse_period_time_stats samples not equal to pulse_num"); + $finish; + end + if (sync_time_stats.size() != pulse_num) begin + $display("[ERROR] -run_test_case- Size of sync_time_stats samples not equal to pulse_num"); + $finish; + end + + avearge_pulse_delay = 0; + foreach (pulse_delay_time_stats[i]) + avearge_pulse_delay += pulse_delay_time_stats[i]; + avearge_pulse_delay /= pulse_num; + + average_pulse_width = 0; + foreach (pulse_width_time_stats[i]) + average_pulse_width += pulse_width_time_stats[i]; + average_pulse_width /= pulse_num; + + average_pulse_period = 0; + foreach (pulse_period_time_stats[i]) + average_pulse_period += pulse_period_time_stats[i]; + average_pulse_period /= pulse_num; + + average_sync_time = 0; + foreach (sync_time_stats[i]) + average_sync_time += sync_time_stats[i]; + average_sync_time /= pulse_num; - // // Параллельный запуск длинного старта и обработки синхронизации - // fork - // // Поток 1: Удерживаем старт аномально долго - // begin - // start_dut(rand_start_duration); - // end - // // Поток 2: Обслуживаем n=4 циклов синхронизации со случайными задержками - // begin - // repeat(pulse_n) begin - // // Рандомизируем параметры для каждого из 4-х рукопожатий - // rand_first = $urandom; // Случайно: Самплер первый (1) или Генератор первый (0) - // rand_delay = $urandom_range(1, 8); // Случайная задержка ожидания (1..8 тактов) - // rand_ack = $urandom_range(5, 10); // Аномально долгий удерживаемый импульс sampler_done (10..30 тактов) - - // synchronize( - // .sampler_first(rand_first), - // .delay_before_ack(rand_delay), - // .ack_duration(rand_ack) - // ); - // end - // end - // join - // repeat(pulse_p+5) @(posedge clk); - // disable counter_proc; - // // Ожидание завершения переходных процессов - // repeat(10) @(posedge clk); - // if (total_impulse_cycles == pulse_w*pulse_n) - // $display("[TB] -check_impulses- Pulse generation CORRECT"); - // else begin - // $display("[ERROR] -check_impulses- Pulse generation INCORRECT. Total number of pulses: %d, must be: %d", total_impulse_cycles, pulse_w*pulse_n); - // $finish; - // end - // $display("[TB] -check_impulses- Done"); - // endtask - - // task automatic run_test_case( - // input int pulse_w, - // input int pulse_p, - // input int pulse_n, - // input int pulse_h, - // input bit skip_reset, // skip reset sequence on demand - // input bit count_level // count ticks of amplitude == pulse_h or amplitude != pulse_h - // ); - // int total_impulse_cycles = 0; - - // if (!skip_reset) begin - // reset_dut(1); - // @(posedge clk); - // end - - // set_config( - // .w(pulse_w), - // .p(pulse_p), - // .n(pulse_n), - // .h(pulse_h) - // ); - // @(posedge clk); - - // start_dut(1); + $display("[TB] -run_test_case- Pulse test stats:\n\tavearge_pulse_delay: %0.3f\n\taverage_pulse_width: %0.3f\n\taverage_pulse_period: %0.3f\n\taverage_sync_time: %0.3f", avearge_pulse_delay, average_pulse_width, average_pulse_period, average_sync_time); - // // Фоновый процесс подсчета тактов импульса - // fork - // begin : counter_proc - // forever begin - // @(negedge clk); // 180 deg. phase shift for "DAC strobing signal" - // if (count_level) begin - // if (dac_out == pulse_h) begin - // total_impulse_cycles++; - // end - // end - // else begin - // if (dac_out != current_zero_level) begin - // total_impulse_cycles++; - // end - // end - // end - // end - // join_none - - // repeat(pulse_n) begin - // synchronize( - // .sampler_first(0), - // .delay_before_ack(1), - // .ack_duration(2) - // ); - // end - // repeat(pulse_p+5) @(posedge clk); - // disable counter_proc; - // repeat(10) @(posedge clk); - - // if (count_level) begin - // if (total_impulse_cycles == pulse_w*pulse_n) - // $display("[TB] -run_test_case- Pulse generation CORRECT"); - // else begin - // $display("[ERROR] -run_test_case- Pulse generation INCORRECT. Total number of pulses: %d, must be: %d", total_impulse_cycles, pulse_w*pulse_n); - // $finish; - // end - // end - // else begin - // if (total_impulse_cycles == 0) - // $display("[TB] -run_test_case- Pulse generation CORRECT"); - // else begin - // $display("[ERROR] -run_test_case- Pulse generation INCORRECT. Total number of pulses: %d, must be: %d", total_impulse_cycles, 0); - // $finish; - // end - // end - // endtask + if (avearge_pulse_delay > CLOCK_DEVIATION * CLK_ADC_PERIOD) begin + $display("[ERROR] -run_test_case- avearge_pulse_delay too big: %0.3f", avearge_pulse_delay); + error_flag = 1; + end + if (fabs(average_pulse_width - pulse_width * CLK_DAC_PERIOD) > CLOCK_DEVIATION * CLK_ADC_PERIOD) begin + $display("[ERROR] -run_test_case- average_pulse_width deviates from choosen pulse_width. Deviation: %0.3f > %0.3f ns", fabs(average_pulse_width - pulse_width * CLK_DAC_PERIOD), CLOCK_DEVIATION * CLK_ADC_PERIOD); + error_flag = 1; + end + if (fabs(average_pulse_period - sample_num * CLK_ADC_PERIOD) > CLOCK_DEVIATION * CLK_ADC_PERIOD) begin + $display("[ERROR] -run_test_case- average_pulse_period deviates from choosen pulse_width. Deviation: %0.3f > %0.3f ns", fabs(average_pulse_period - sample_num * CLK_ADC_PERIOD), CLOCK_DEVIATION * CLK_ADC_PERIOD); + error_flag = 1; + end + if (error_flag) + $finish; + endtask + // Таска // --- ОСНОВНОЙ ПРОЦЕСС ТЕСТИРОВАНИЯ --- initial begin $display("[TB] Tests start"); // Инициализация - dac_start = 0; + dac_start = 0; pulse_width = 0; pulse_period = 0; pulse_height = 0; pulse_num = 0; smp_num = 0; out_of_range = 0; - fork - reset_dut_adc(3); - reset_dut_dac(6); - join - @(posedge clk_dac); - @(posedge clk_adc); - set_config( - .w(50), - .p(125), - .n(5), - .h(1024), - .sn(65) + rst_adc = 0; + rst_dac = 0; + + $display("[TB] Test 1. Simple test"); + // run_test_case( + // .pulse_width(50), + // .pulse_period(125), + // .pulse_height(2**(ADC_DATA_WIDTH-1)), + // .pulse_num(5), + // .sample_num(65), + // .skip_reset(0), + // .randomize_start_timing(0), + // .out_of_range_val(0), + // .randomize_out_of_range(0) + // ); + run_test_case( + .pulse_width(25), + .pulse_period(110), + .pulse_height(2**(ADC_DATA_WIDTH-1)), + .pulse_num(10), + .sample_num(50), + .skip_reset(0), + .randomize_start_timing(0), + .out_of_range_val(0), + .randomize_out_of_range(0) ); - start_dut(1); - - repeat(1000) @(posedge clk_adc); - + $display("[TB] Test 1 complete"); + + $display("[TB] ALL PASSED"); $finish; end From d71aaf1650f38d466dc7f3ab27cbb037351f88da Mon Sep 17 00:00:00 2001 From: Zer0Nu11 Date: Fri, 19 Jun 2026 08:05:03 +0300 Subject: [PATCH 2/9] fix: request/done protocol --- rtl/sampler/src/sampler.sv | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/rtl/sampler/src/sampler.sv b/rtl/sampler/src/sampler.sv index 0b3172b..b67da01 100644 --- a/rtl/sampler/src/sampler.sv +++ b/rtl/sampler/src/sampler.sv @@ -12,11 +12,11 @@ module sampler input [DATA_WIDTH-1:0] data_in, input out_of_range, input [31:0] smp_num, - input done, + input request, output logic [DATA_WIDTH*PACK_FACTOR-1:0] m_axis_tdata, output logic m_axis_tvalid, - output logic request + output logic done ); logic [DATA_WIDTH-1:0] data_converted; logic out_of_range_reg; @@ -66,18 +66,18 @@ module sampler cnt_smp_num <= '0; smp_num_reg <= '0; enable <= 0; - request <= 0; + done <= 0; end else begin buffer_ready <= 0; if (!enable) begin - if (request && done) begin + if (done && request) begin enable <= 1; - request <= 0; + done <= 0; cnt_smp_num <= 0; smp_num_reg <= smp_num; end else begin - request <= 1; + done <= 1; end end else begin if (cnt_smp_num != smp_num_reg) begin @@ -104,17 +104,17 @@ module sampler cnt_smp_num <= '0; smp_num_reg <= '0; enable <= 0; - request <= 0; + done <= 0; end else begin buffer_ready <= 0; if (!enable) begin - if (request && done) begin + if (done && request) begin enable <= 1; - request <= 0; + done <= 0; cnt_smp_num <= 0; smp_num_reg <= smp_num; end else begin - request <= 1; + done <= 1; end end else begin if (cnt_smp_num != smp_num_reg) begin From 4fbecd5e30944a0450eb4f4bc5d4516b6610a202 Mon Sep 17 00:00:00 2001 From: Zer0Nu11 Date: Fri, 19 Jun 2026 20:49:17 +0300 Subject: [PATCH 3/9] upd: sync design log verbosity + optimal delay latency --- designs/adc_dac_synchoronizer/sync_top.sv | 2 +- designs/adc_dac_synchoronizer/tb_sync_top.sv | 38 +++++++++++--------- rtl/sampler/src/sampler.sv | 6 ++-- 3 files changed, 25 insertions(+), 21 deletions(-) diff --git a/designs/adc_dac_synchoronizer/sync_top.sv b/designs/adc_dac_synchoronizer/sync_top.sv index 1fa1cf6..af3115f 100644 --- a/designs/adc_dac_synchoronizer/sync_top.sv +++ b/designs/adc_dac_synchoronizer/sync_top.sv @@ -42,7 +42,7 @@ module sync_top endgenerate generate if (USE_DELAY_LINE) begin - localparam int DELAY_LENGTH = 0; + localparam int DELAY_LENGTH = USE_DELAY_LINE; logic [DELAY_LENGTH:0][ADC_DATA_WIDTH-1:0] signal_delay_line; always_ff @(posedge clk_dac) begin signal_delay_line[0] <= internal_wire_singnal; diff --git a/designs/adc_dac_synchoronizer/tb_sync_top.sv b/designs/adc_dac_synchoronizer/tb_sync_top.sv index 526ea79..68c3cf8 100644 --- a/designs/adc_dac_synchoronizer/tb_sync_top.sv +++ b/designs/adc_dac_synchoronizer/tb_sync_top.sv @@ -6,6 +6,7 @@ module tb_top; // Параметры //------------------------------------------------------------ parameter string ZERO_LEVEL_PARAM = "logic"; // "logic" VS "true" + parameter VERBOSE = 1; localparam DAC_DATA_WIDTH = 14; localparam ADC_DATA_WIDTH = 12; @@ -13,7 +14,7 @@ module tb_top; localparam PROCESS_MODE = 0; localparam CLK_DAC_PERIOD = 8; localparam CLK_ADC_PERIOD = 15.385; - localparam USE_DELAY_LINE = 1; + localparam USE_DELAY_LINE = 0; localparam LOGIC_ZERO_LEVEL = 0; // DAC -5V for logic zero localparam VOLTAGE_ZERO_LEVEL = 2**(DAC_DATA_WIDTH-1); // DAC 0V for logic zero localparam ZERO_LEVEL = (ZERO_LEVEL_PARAM == "logic") ? LOGIC_ZERO_LEVEL : VOLTAGE_ZERO_LEVEL; @@ -262,8 +263,10 @@ module tb_top; average_sync_time += sync_time_stats[i]; average_sync_time /= pulse_num; - $display("[TB] -run_test_case- Pulse test stats:\n\tavearge_pulse_delay: %0.3f\n\taverage_pulse_width: %0.3f\n\taverage_pulse_period: %0.3f\n\taverage_sync_time: %0.3f", avearge_pulse_delay, average_pulse_width, average_pulse_period, average_sync_time); - + if (VERBOSE >= 1) begin + $display("[TB] -run_test_case- Pulse test stats:\n\tavearge_pulse_delay: %0.3f\n\taverage_pulse_width: %0.3f\n\taverage_pulse_period: %0.3f\n\taverage_sync_time: %0.3f", avearge_pulse_delay, average_pulse_width, average_pulse_period, average_sync_time); + end + if (avearge_pulse_delay > CLOCK_DEVIATION * CLK_ADC_PERIOD) begin $display("[ERROR] -run_test_case- avearge_pulse_delay too big: %0.3f", avearge_pulse_delay); error_flag = 1; @@ -296,24 +299,25 @@ module tb_top; rst_adc = 0; rst_dac = 0; - $display("[TB] Test 1. Simple test"); - // run_test_case( - // .pulse_width(50), - // .pulse_period(125), - // .pulse_height(2**(ADC_DATA_WIDTH-1)), - // .pulse_num(5), - // .sample_num(65), - // .skip_reset(0), - // .randomize_start_timing(0), - // .out_of_range_val(0), - // .randomize_out_of_range(0) - // ); + $display("[TB] Test 1. Simple test. (1/2)"); + run_test_case( + .pulse_width(50), + .pulse_period(125), + .pulse_height(2**(ADC_DATA_WIDTH-1)), + .pulse_num(5), + .sample_num(65), + .skip_reset(0), + .randomize_start_timing(0), + .out_of_range_val(0), + .randomize_out_of_range(0) + ); + $display("[TB] Test 1. Simple test. (2/2)"); run_test_case( .pulse_width(25), - .pulse_period(110), + .pulse_period(125), .pulse_height(2**(ADC_DATA_WIDTH-1)), .pulse_num(10), - .sample_num(50), + .sample_num(65), .skip_reset(0), .randomize_start_timing(0), .out_of_range_val(0), diff --git a/rtl/sampler/src/sampler.sv b/rtl/sampler/src/sampler.sv index b67da01..94d5c38 100644 --- a/rtl/sampler/src/sampler.sv +++ b/rtl/sampler/src/sampler.sv @@ -5,8 +5,7 @@ module sampler parameter DATA_WIDTH = 12, parameter PACK_FACTOR = 1, parameter PROCESS_MODE = 0 - ) -( +) ( input clk_in, input rst, input [DATA_WIDTH-1:0] data_in, @@ -17,7 +16,8 @@ module sampler output logic [DATA_WIDTH*PACK_FACTOR-1:0] m_axis_tdata, output logic m_axis_tvalid, output logic done - ); +); + logic [DATA_WIDTH-1:0] data_converted; logic out_of_range_reg; logic [31:0] smp_num_reg, cnt_smp_num; From efcd6ef5d0fd72a8baf97b9465976689a432f813 Mon Sep 17 00:00:00 2001 From: Zer0Nu11 Date: Sat, 20 Jun 2026 03:07:05 +0300 Subject: [PATCH 4/9] upd: fast fix of sampler OTR. fix debug.xdc Major add of full automated testing for TB. --- designs/adc_dac_synchoronizer/debug.xdc | 4 +- designs/adc_dac_synchoronizer/tb_sync_top.sv | 263 +++++++++++++++++-- rtl/sampler/src/sampler.sv | 14 +- 3 files changed, 244 insertions(+), 37 deletions(-) diff --git a/designs/adc_dac_synchoronizer/debug.xdc b/designs/adc_dac_synchoronizer/debug.xdc index 9df31b6..2a50dfc 100644 --- a/designs/adc_dac_synchoronizer/debug.xdc +++ b/designs/adc_dac_synchoronizer/debug.xdc @@ -1,3 +1,3 @@ # Primary clocks -create_clock -name eth_clk -period 8.000 [get_ports dac_clk_in] -create_clock -name acc_clk -period 15.385 [get_ports adc_clk_in] \ No newline at end of file +create_clock -name geneartor_clk -period 8.000 [get_ports clk_dac] +create_clock -name sampler_clk -period 15.385 [get_ports clk_adc] \ No newline at end of file diff --git a/designs/adc_dac_synchoronizer/tb_sync_top.sv b/designs/adc_dac_synchoronizer/tb_sync_top.sv index 68c3cf8..851c266 100644 --- a/designs/adc_dac_synchoronizer/tb_sync_top.sv +++ b/designs/adc_dac_synchoronizer/tb_sync_top.sv @@ -19,7 +19,7 @@ module tb_top; localparam VOLTAGE_ZERO_LEVEL = 2**(DAC_DATA_WIDTH-1); // DAC 0V for logic zero localparam ZERO_LEVEL = (ZERO_LEVEL_PARAM == "logic") ? LOGIC_ZERO_LEVEL : VOLTAGE_ZERO_LEVEL; - localparam CLOCK_DEVIATION = 1; // Maximum clock deviation of pulse stats + localparam CLOCK_DEVIATION = 2; // Maximum clock deviation of pulse stats //------------------------------------------------------------ // Тактовые сигналы и сброс @@ -88,6 +88,8 @@ module tb_top; return (val < 0.0) ? -val : val; endfunction + `define MIN(x, y) (((x) < (y)) ? (x) : (y)) + // Таска сброса DAC DUT task automatic reset_dut_dac( input int rst_duration // сколько тактов держать сброс @@ -151,6 +153,10 @@ module tb_top; out_of_range = out_of_range_val; + if (VERBOSE >= 2) begin + $display("[TB] -run_test_case- Starting test case"); + end + if (randomize_out_of_range) fork begin : randomize_out_of_range_proc @@ -186,60 +192,96 @@ module tb_top; end join_none + if (VERBOSE >= 2) begin + $display("[TB] -run_test_case- Starting pulse generation"); + end + for (int i = 0; i < pulse_num; i++) begin + if (VERBOSE >= 3) begin + $display("[TB] -run_test_case- Start sync for pulse #%d", i); + end @(posedge m_axis_tvalid); + if (VERBOSE >= 3) begin + $display("[TB] -run_test_case- Found valid pulse response data positive front"); + end // Старт цикла. Завершение синхронизации sync_time_stats.push_back($realtime - sync_start_time); pulse_start_time = $realtime; - // Начало импульса - if (pulse_height != ZERO_LEVEL) begin - wait(m_axis_tdata != ZERO_LEVEL); - if (m_axis_tdata != pulse_height) begin - $display("[ERROR] -run_test_case- Wrong pulse height: %d. Must be: %d", m_axis_tdata, pulse_height); - $finish; + fork + // Поток будет запущен для ненулевых импульсов и гарантированно завершится как только зафиксирует статистику импульса + // Начало импульса + if (pulse_height != ZERO_LEVEL && pulse_width != 0) begin + if (VERBOSE >= 4) begin + $display("[TB] -run_test_case- Wait until pulse become high"); + end + wait(m_axis_tdata != ZERO_LEVEL); + // Проверим что высота импульса совпала с заданной. Т.к. OTR != 0 влияет на выходные данные сэмплера, то не будем проверять такие случаи. + // Будем считать что из-за OTR данные изменились (по условию OTR + MSB), проверка пропускается, т.к. сложно понять точное значение OTR в момент обработки данных от tdata + if (m_axis_tdata != pulse_height && (randomize_out_of_range || out_of_range_val)) begin + $display("[ERROR] -run_test_case- Wrong pulse height: %d. Must be: %d", m_axis_tdata, pulse_height); + $finish; + end + // Фактическое начало импульса. Поступление высокого уровня + pulse_update_val_time = $realtime; + pulse_delay_time_stats.push_back(pulse_update_val_time - pulse_start_time); + if (VERBOSE >= 4) begin + $display("[TB] -run_test_case- Wait until pulse become low"); + end + wait(m_axis_tdata == ZERO_LEVEL); + pulse_width_time_stats.push_back($realtime - pulse_update_val_time); end - // Фактическое начало импульса. Поступление высокого уровня - pulse_update_val_time = $realtime; - pulse_delay_time_stats.push_back(pulse_update_val_time - pulse_start_time); - wait(m_axis_tdata == ZERO_LEVEL); - pulse_width_time_stats.push_back($realtime - pulse_update_val_time); - end - // Конец импульса + // Конец импульса + join_none @(negedge m_axis_tvalid); + if (VERBOSE >= 3) begin + $display("[TB] -run_test_case- Found valid pulse response data negative front"); + end // Завершение цикла. Старт синхронизации pulse_period_time_stats.push_back($realtime - pulse_start_time); sync_start_time = $realtime; end + if (VERBOSE >= 2) begin + $display("[TB] -run_test_case- Stop pulse generation"); + end + fork // Проверка с таймаутом на лишние циклы @(posedge m_axis_tvalid); - repeat(20) @(posedge clk_adc); + repeat(30) @(posedge clk_adc); join_any if (m_axis_tvalid == 1) begin $display("[ERROR] -run_test_case- Extra pulse cycle num. More than must be."); $finish; end - if (randomize_out_of_range) + if (VERBOSE >= 2) begin + $display("[TB] -run_test_case- Exit waiting via timeout"); + end + + if (randomize_out_of_range) begin disable randomize_out_of_range_proc; + if (VERBOSE >= 2) begin + $display("[TB] -run_test_case- Stop randomize_out_of_range_proc"); + end + end // Проверка по статистике. Подсчет средних значений - if (pulse_delay_time_stats.size() != pulse_num) begin - $display("[ERROR] -run_test_case- Size of pulse_delay_time_stats samples not equal to pulse_num"); + if (pulse_delay_time_stats.size() != pulse_num && pulse_height != ZERO_LEVEL && pulse_width != 0) begin // Detected with pulse level. Skip if pulse level undetectable + $display("[ERROR] -run_test_case- Size of pulse_delay_time_stats samples not equal to pulse_num: %d VS %d", pulse_delay_time_stats.size(), pulse_num); $finish; end - if (pulse_width_time_stats.size() != pulse_num) begin - $display("[ERROR] -run_test_case- Size of pulse_width_time_stats samples not equal to pulse_num"); + if (pulse_width_time_stats.size() != pulse_num && pulse_height != ZERO_LEVEL && pulse_width != 0) begin // Detected with pulse level. Skip if pulse level undetectable + $display("[ERROR] -run_test_case- Size of pulse_width_time_stats samples not equal to pulse_num: %d VS %d", pulse_width_time_stats.size(), pulse_num); $finish; end if (pulse_period_time_stats.size() != pulse_num) begin - $display("[ERROR] -run_test_case- Size of pulse_period_time_stats samples not equal to pulse_num"); + $display("[ERROR] -run_test_case- Size of pulse_period_time_stats samples not equal to pulse_num: %d VS %d", pulse_period_time_stats.size(), pulse_num); $finish; end if (sync_time_stats.size() != pulse_num) begin - $display("[ERROR] -run_test_case- Size of sync_time_stats samples not equal to pulse_num"); + $display("[ERROR] -run_test_case- Size of sync_time_stats samples not equal to pulse_num: %d VS %d", sync_time_stats.size(), pulse_num); $finish; end @@ -271,7 +313,7 @@ module tb_top; $display("[ERROR] -run_test_case- avearge_pulse_delay too big: %0.3f", avearge_pulse_delay); error_flag = 1; end - if (fabs(average_pulse_width - pulse_width * CLK_DAC_PERIOD) > CLOCK_DEVIATION * CLK_ADC_PERIOD) begin + if (fabs(average_pulse_width - pulse_width * CLK_DAC_PERIOD * (pulse_height != ZERO_LEVEL)) > CLOCK_DEVIATION * CLK_ADC_PERIOD && sample_num * CLK_ADC_PERIOD >= pulse_width * CLK_DAC_PERIOD) begin $display("[ERROR] -run_test_case- average_pulse_width deviates from choosen pulse_width. Deviation: %0.3f > %0.3f ns", fabs(average_pulse_width - pulse_width * CLK_DAC_PERIOD), CLOCK_DEVIATION * CLK_ADC_PERIOD); error_flag = 1; end @@ -279,8 +321,17 @@ module tb_top; $display("[ERROR] -run_test_case- average_pulse_period deviates from choosen pulse_width. Deviation: %0.3f > %0.3f ns", fabs(average_pulse_period - sample_num * CLK_ADC_PERIOD), CLOCK_DEVIATION * CLK_ADC_PERIOD); error_flag = 1; end + + if (VERBOSE >= 2) begin + $display("[TB] -run_test_case- Pass error processing"); + end + if (error_flag) $finish; + + if (VERBOSE >= 2) begin + $display("[TB] -run_test_case- Passed checks"); + end endtask // Таска @@ -299,7 +350,7 @@ module tb_top; rst_adc = 0; rst_dac = 0; - $display("[TB] Test 1. Simple test. (1/2)"); + $display("[TB] Test 1. Simple test. (1/3)"); run_test_case( .pulse_width(50), .pulse_period(125), @@ -307,26 +358,182 @@ module tb_top; .pulse_num(5), .sample_num(65), .skip_reset(0), - .randomize_start_timing(0), + .randomize_start_timing(1), .out_of_range_val(0), .randomize_out_of_range(0) ); - $display("[TB] Test 1. Simple test. (2/2)"); + $display("[TB] Test 1. Simple test. (2/3)"); run_test_case( .pulse_width(25), .pulse_period(125), .pulse_height(2**(ADC_DATA_WIDTH-1)), .pulse_num(10), .sample_num(65), - .skip_reset(0), - .randomize_start_timing(0), + .skip_reset(1), + .randomize_start_timing(1), + .out_of_range_val(0), + .randomize_out_of_range(0) + ); + $display("[TB] Test 1. Simple test. (3/3)"); + run_test_case( + .pulse_width(10), + .pulse_period(50), + .pulse_height(ZERO_LEVEL), + .pulse_num(4), + .sample_num(25), + .skip_reset(1), + .randomize_start_timing(1), .out_of_range_val(0), .randomize_out_of_range(0) ); $display("[TB] Test 1 complete"); + $display("[TB] Test 2. Edge cases. Pulse width 0%%. (1/7)"); + run_test_case( + .pulse_width(0), + .pulse_period(125), + .pulse_height(2**(ADC_DATA_WIDTH-1)), + .pulse_num(5), + .sample_num(65), + .skip_reset(1), + .randomize_start_timing(1), + .out_of_range_val(0), + .randomize_out_of_range(0) + ); + $display("[TB] Test 2. Edge cases. Pulse width 100%%. (2/7)"); + run_test_case( + .pulse_width(10), + .pulse_period(10), + .pulse_height(2**(ADC_DATA_WIDTH-1)), + .pulse_num(5), + .sample_num(65), + .skip_reset(1), + .randomize_start_timing(1), + .out_of_range_val(0), + .randomize_out_of_range(0) + ); + $display("[TB] Test 2. Edge cases. Pulse height == ZERO_LEVEL. (3/7)"); + run_test_case( + .pulse_width(10), + .pulse_period(125), + .pulse_height(ZERO_LEVEL), + .pulse_num(5), + .sample_num(65), + .skip_reset(1), + .randomize_start_timing(1), + .out_of_range_val(0), + .randomize_out_of_range(0) + ); + $display("[TB] Test 2. Edge cases. Pulse num == 0. (4/7)"); + run_test_case( + .pulse_width(10), + .pulse_period(125), + .pulse_height(2**(ADC_DATA_WIDTH-3)), + .pulse_num(0), + .sample_num(65), + .skip_reset(1), + .randomize_start_timing(1), + .out_of_range_val(0), + .randomize_out_of_range(0) + ); + + $display("[TB] Test 2. Edge cases. Sample num time << Pulse width time. (5/7)"); + run_test_case( + .pulse_width(10), + .pulse_period(125), + .pulse_height(2**(ADC_DATA_WIDTH-1)), + .pulse_num(5), + .sample_num(2), + .skip_reset(1), + .randomize_start_timing(1), + .out_of_range_val(0), + .randomize_out_of_range(0) + ); + + // Ожидание окончания работы генератора. Т.к. конец работы определяется по tvalid сэмплера, а он завершается сильно раньше. Чтобы не пропустить start следующей таски, ждем + wait(dut.generator_inst.enable == 0); + #50; + + $display("[TB] Test 2. Edge cases. Sample num == 0. (6/7)"); + // Запустим в работу вручную, т.к. run_test_case обязательно ждет pulse num циклов. Детекция цикла производится по активности сэплера. Ее не должно быть при sample num = 0 + set_config( + .w(10), + .p(125), + .h(2**(ADC_DATA_WIDTH-1)), + .n(5), + .sn(0) + ); + start_dut(3); + fork + begin : wait_sampler_active_proc + @(posedge m_axis_tvalid); + $display("[ERROR] Sampler active with sample num == 0"); + $finish; + end + begin + @(negedge dut.generator_inst.enable); + end + join_any + disable wait_sampler_active_proc; + repeat(30) @(posedge clk_adc); + + // Данный тест должен приводить к тому, что сэмплер будет давать крайние значения вместо заданного pulse height из-за OTR=1 + // TODO известно что при таких настройках OTR = 1 постоянно. Легко предсказать уровень + // Дописать авто тест + $display("[TB] Test 2. Edge cases. OTR == 1. (7/7)"); + run_test_case( + .pulse_width(10), + .pulse_period(125), + .pulse_height(10), + .pulse_num(5), + .sample_num(65), + .skip_reset(1), + .randomize_start_timing(1), + .out_of_range_val(1), + .randomize_out_of_range(0) + ); + $display("[TB] Test 2 complete"); + + // $finish; // TODO remove + + $display("[TB] Test 3. Random tests"); + for (int i = 0; i < 100; i++) begin + int r_w, r_p, r_n, r_h, r_sn; + bit r_skip, r_otr, r_otr_rand; + + // Генерируем параметры + r_p = $urandom_range(50, 150); // Период от 5 до 50 + r_w = $urandom_range(10, r_p); // Ширина не больше периода + r_n = $urandom_range(1, 10); // Количество импульсов + r_h = $urandom_range(0, 2**(`MIN(ADC_DATA_WIDTH, DAC_DATA_WIDTH))-1); // Высота импульса + r_sn = $urandom_range(1, 40); // Число сэмплов + r_skip = $urandom_range(0, 1); // Случайный сброс (0 - сброс, 1 - пропуск) + r_otr = $urandom_range(0, 1); // Out Of Range стартовое значение + r_otr_rand = $urandom_range(0, 1); // Сделать OTR случайным + + if (VERBOSE >= 1) + $display("[TB] --- Test #%0d (Config: W=%0d, P=%0d, N=%0d, H=%0d, SN=%0d, SkipReset=%0b) ---", + i+1, r_w, r_p, r_n, r_h, r_sn, r_skip); + + run_test_case( + .pulse_width(r_w), + .pulse_period(r_p), + .pulse_height(r_h), + .pulse_num(r_n), + .sample_num(r_sn), + .skip_reset(r_skip), + .randomize_start_timing(0), + .out_of_range_val(r_otr), + .randomize_out_of_range(r_otr_rand) + ); + + wait(dut.generator_inst.enable == 0); // Проверка на завершение работы + #50; + end + $display("[TB] Test 3 complete"); $display("[TB] ALL PASSED"); + $display("[TB] Maximum clock deviation of stats %0.2f", CLOCK_DEVIATION); $finish; end diff --git a/rtl/sampler/src/sampler.sv b/rtl/sampler/src/sampler.sv index 94d5c38..ccc36b7 100644 --- a/rtl/sampler/src/sampler.sv +++ b/rtl/sampler/src/sampler.sv @@ -83,9 +83,9 @@ module sampler if (cnt_smp_num != smp_num_reg) begin cnt_smp_num <= cnt_smp_num +1; buffer_ready <= 1; - if (!out_of_range_reg) begin + // if (!out_of_range_reg) begin buffer <= data_converted; - end + // end end else begin cnt_smp_num <= '0; buffer_ready <= 0; @@ -120,16 +120,16 @@ module sampler if (cnt_smp_num != smp_num_reg) begin cnt_smp_num <= cnt_smp_num +1; buffer_ready <= 1; - if (!out_of_range_reg) begin + // if (!out_of_range_reg) begin buffer <= {buffer[DATA_WIDTH*(PACK_FACTOR-1)-1:0], data_converted}; if (cnt == PACK_FACTOR-1) begin cnt <= 0; buffer <= {buffer[DATA_WIDTH*(PACK_FACTOR-1)-1:0], data_converted}; end - else begin - cnt <= cnt + 1; - end - end + else begin + cnt <= cnt + 1; + end + // end end else begin cnt_smp_num <= '0; buffer_ready <= 0; From 789255fa045423db4a75bad9ae1dc4432c33e718 Mon Sep 17 00:00:00 2001 From: Zer0Nu11 Date: Sat, 20 Jun 2026 04:05:37 +0300 Subject: [PATCH 5/9] fix: add timing sim tricks --- designs/adc_dac_synchoronizer/tb_sync_top.sv | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/designs/adc_dac_synchoronizer/tb_sync_top.sv b/designs/adc_dac_synchoronizer/tb_sync_top.sv index 851c266..09cde9c 100644 --- a/designs/adc_dac_synchoronizer/tb_sync_top.sv +++ b/designs/adc_dac_synchoronizer/tb_sync_top.sv @@ -94,6 +94,7 @@ module tb_top; task automatic reset_dut_dac( input int rst_duration // сколько тактов держать сброс ); + @(posedge clk_dac); rst_dac <= 1; repeat(rst_duration) @(posedge clk_dac); rst_dac <= 0; @@ -103,6 +104,7 @@ module tb_top; task automatic reset_dut_adc( input int rst_duration // сколько тактов держать сброс ); + @(posedge clk_adc); rst_adc <= 1; repeat(rst_duration) @(posedge clk_adc); rst_adc <= 0; @@ -180,6 +182,7 @@ module tb_top; .h(pulse_height), .sn(sample_num) ); + @(posedge clk_dac); if (randomize_start_timing) start_hold_time = $urandom_range(1, 15); @@ -266,6 +269,7 @@ module tb_top; $display("[TB] -run_test_case- Stop randomize_out_of_range_proc"); end end + out_of_range = 0; // Проверка по статистике. Подсчет средних значений if (pulse_delay_time_stats.size() != pulse_num && pulse_height != ZERO_LEVEL && pulse_width != 0) begin // Detected with pulse level. Skip if pulse level undetectable @@ -350,6 +354,8 @@ module tb_top; rst_adc = 0; rst_dac = 0; + #100; // init + $display("[TB] Test 1. Simple test. (1/3)"); run_test_case( .pulse_width(50), From b38a6936763baf2dfda0f0a569ae760940f3a666 Mon Sep 17 00:00:00 2001 From: Zer0Nu11 Date: Sat, 20 Jun 2026 09:33:33 +0300 Subject: [PATCH 6/9] fix: timing. New DAC-ADC line code --- designs/adc_dac_synchoronizer/Makefile | 2 +- designs/adc_dac_synchoronizer/debug.xdc | 11 ++++- designs/adc_dac_synchoronizer/sync_top.sv | 46 ++++++++++++++------ designs/adc_dac_synchoronizer/tb_sync_top.sv | 30 +++++++++---- 4 files changed, 64 insertions(+), 25 deletions(-) diff --git a/designs/adc_dac_synchoronizer/Makefile b/designs/adc_dac_synchoronizer/Makefile index f331cc4..1f62d02 100644 --- a/designs/adc_dac_synchoronizer/Makefile +++ b/designs/adc_dac_synchoronizer/Makefile @@ -23,7 +23,7 @@ SYN_FILES += sync_top.sv XCI_FILES += $(sort $(shell find ip/ -type f -name '*.xci')) -XDC_FILES += ../../constraints/ax7102.xdc +# XDC_FILES += ../../constraints/ax7102.xdc # useless for pure RTL design XDC_FILES += debug.xdc SYN_FILES += tb_sync_top.sv diff --git a/designs/adc_dac_synchoronizer/debug.xdc b/designs/adc_dac_synchoronizer/debug.xdc index 2a50dfc..600e406 100644 --- a/designs/adc_dac_synchoronizer/debug.xdc +++ b/designs/adc_dac_synchoronizer/debug.xdc @@ -1,3 +1,12 @@ # Primary clocks create_clock -name geneartor_clk -period 8.000 [get_ports clk_dac] -create_clock -name sampler_clk -period 15.385 [get_ports clk_adc] \ No newline at end of file +create_clock -name sampler_clk -period 15.385 [get_ports clk_adc] +set_clock_groups -asynchronous -group [get_clocks geneartor_clk] -group [get_clocks sampler_clk] + +# set_false_path -through [get_nets -hierarchical {*dac_signal* *internal_wire_singnal* *adc_singnal*}] +# set_false_path -through [get_nets {dac_done dac_done_stretched dac_request adc_done adc_request}] + +# set_property DONT_TOUCH true [get_cells -hierarchical -filter {NAME =~ *generator_inst*pulse_height_reg*}] +# set_property DONT_TOUCH true [get_cells -hierarchical -filter {NAME =~ *generator_inst*dac_out_reg*}] +# Применяем к самому проводу сигнала CE, чтобы Vivado не дробила его +# set_property DONT_TOUCH true [get_nets -of_objects [get_pins -hierarchical -filter {PIN_NAME =~ *CE} -of_objects [get_cells *pulse_height_reg*]]] \ No newline at end of file diff --git a/designs/adc_dac_synchoronizer/sync_top.sv b/designs/adc_dac_synchoronizer/sync_top.sv index af3115f..6de29c5 100644 --- a/designs/adc_dac_synchoronizer/sync_top.sv +++ b/designs/adc_dac_synchoronizer/sync_top.sv @@ -30,28 +30,46 @@ module sync_top //------------------------------------------------------------ wire dac_done, dac_request, adc_done, adc_request; wire [DAC_DATA_WIDTH-1:0] dac_signal; - wire [ADC_DATA_WIDTH-1:0] internal_wire_singnal; - wire [ADC_DATA_WIDTH-1:0] adc_singnal; + wire [ADC_DATA_WIDTH-1:0] internal_wire_signal; + wire [ADC_DATA_WIDTH-1:0] adc_signal; + + // 1. Адаптация разрядности и «заземление» лишних бит generate if (ADC_DATA_WIDTH > DAC_DATA_WIDTH) begin : g_pad_zeros - assign internal_wire_singnal = { {(ADC_DATA_WIDTH - DAC_DATA_WIDTH){1'b0}}, dac_signal }; - end - else begin : g_truncate - assign internal_wire_singnal = dac_signal[ADC_DATA_WIDTH-1:0]; + // АЦП шире ЦАП: добиваем нулями старшие биты + assign internal_wire_signal = { {(ADC_DATA_WIDTH - DAC_DATA_WIDTH){1'b0}}, dac_signal }; + end + else if (ADC_DATA_WIDTH < DAC_DATA_WIDTH) begin : g_truncate + // ЦАП шире АЦП (например, 14 -> 12): забираем младшие биты + assign internal_wire_signal = dac_signal[DAC_DATA_WIDTH-1:DAC_DATA_WIDTH-ADC_DATA_WIDTH]; + (* dont_touch = "true" *) wire dummy; + assign dummy = ^dac_signal; + end + else begin : g_match + // Разрядности равны + assign internal_wire_signal = dac_signal; end endgenerate + generate - if (USE_DELAY_LINE) begin + if (USE_DELAY_LINE > 0) begin : g_delay_line localparam int DELAY_LENGTH = USE_DELAY_LINE; - logic [DELAY_LENGTH:0][ADC_DATA_WIDTH-1:0] signal_delay_line; + // Двумерный массив для линии задержки + logic [DELAY_LENGTH-1:0][ADC_DATA_WIDTH-1:0] signal_delay_line; + always_ff @(posedge clk_dac) begin - signal_delay_line[0] <= internal_wire_singnal; - for (int i = 0; i < DELAY_LENGTH; i++) + signal_delay_line[0] <= internal_wire_signal; + for (int i = 0; i < DELAY_LENGTH-1; i++) begin signal_delay_line[i+1] <= signal_delay_line[i]; + end end - assign adc_singnal = signal_delay_line[DELAY_LENGTH]; - end else - assign adc_singnal = internal_wire_singnal; + + // ИСПРАВЛЕНО: читаем из последнего элемента массива + assign adc_signal = signal_delay_line[DELAY_LENGTH-1]; + end + else begin : g_no_delay + assign adc_signal = internal_wire_signal; + end endgenerate //------------------------------------------------------------ @@ -127,7 +145,7 @@ module sync_top ) sampler_inst ( .clk_in(clk_adc), .rst(rst_adc), - .data_in(adc_singnal), + .data_in(adc_signal), .out_of_range(out_of_range), .smp_num(smp_num), .m_axis_tdata(m_axis_tdata), diff --git a/designs/adc_dac_synchoronizer/tb_sync_top.sv b/designs/adc_dac_synchoronizer/tb_sync_top.sv index 09cde9c..63999d5 100644 --- a/designs/adc_dac_synchoronizer/tb_sync_top.sv +++ b/designs/adc_dac_synchoronizer/tb_sync_top.sv @@ -19,7 +19,7 @@ module tb_top; localparam VOLTAGE_ZERO_LEVEL = 2**(DAC_DATA_WIDTH-1); // DAC 0V for logic zero localparam ZERO_LEVEL = (ZERO_LEVEL_PARAM == "logic") ? LOGIC_ZERO_LEVEL : VOLTAGE_ZERO_LEVEL; - localparam CLOCK_DEVIATION = 2; // Maximum clock deviation of pulse stats + localparam CLOCK_DEVIATION = 3; // Maximum clock deviation of pulse stats //------------------------------------------------------------ // Тактовые сигналы и сброс @@ -183,6 +183,7 @@ module tb_top; .sn(sample_num) ); @(posedge clk_dac); + @(posedge clk_dac); if (randomize_start_timing) start_hold_time = $urandom_range(1, 15); @@ -221,8 +222,8 @@ module tb_top; wait(m_axis_tdata != ZERO_LEVEL); // Проверим что высота импульса совпала с заданной. Т.к. OTR != 0 влияет на выходные данные сэмплера, то не будем проверять такие случаи. // Будем считать что из-за OTR данные изменились (по условию OTR + MSB), проверка пропускается, т.к. сложно понять точное значение OTR в момент обработки данных от tdata - if (m_axis_tdata != pulse_height && (randomize_out_of_range || out_of_range_val)) begin - $display("[ERROR] -run_test_case- Wrong pulse height: %d. Must be: %d", m_axis_tdata, pulse_height); + if (m_axis_tdata != (pulse_height >> 2) && (randomize_out_of_range || out_of_range_val)) begin + $display("[ERROR] -run_test_case- Wrong pulse height: %d. Must be: %d", m_axis_tdata, pulse_height >> 2); $finish; end // Фактическое начало импульса. Поступление высокого уровня @@ -356,11 +357,11 @@ module tb_top; #100; // init - $display("[TB] Test 1. Simple test. (1/3)"); + $display("[TB] Test 1. Simple test. (1/4)"); run_test_case( .pulse_width(50), .pulse_period(125), - .pulse_height(2**(ADC_DATA_WIDTH-1)), + .pulse_height(2**DAC_DATA_WIDTH-1), .pulse_num(5), .sample_num(65), .skip_reset(0), @@ -368,7 +369,7 @@ module tb_top; .out_of_range_val(0), .randomize_out_of_range(0) ); - $display("[TB] Test 1. Simple test. (2/3)"); + $display("[TB] Test 1. Simple test. (2/4)"); run_test_case( .pulse_width(25), .pulse_period(125), @@ -380,7 +381,7 @@ module tb_top; .out_of_range_val(0), .randomize_out_of_range(0) ); - $display("[TB] Test 1. Simple test. (3/3)"); + $display("[TB] Test 1. Simple test. (3/4)"); run_test_case( .pulse_width(10), .pulse_period(50), @@ -392,6 +393,19 @@ module tb_top; .out_of_range_val(0), .randomize_out_of_range(0) ); + + $display("[TB] Test 1. Simple test. (4/4)"); + run_test_case( + .pulse_width(25), + .pulse_period(125), + .pulse_height(2**(DAC_DATA_WIDTH-1)), + .pulse_num(10), + .sample_num(65), + .skip_reset(1), + .randomize_start_timing(1), + .out_of_range_val(0), + .randomize_out_of_range(0) + ); $display("[TB] Test 1 complete"); $display("[TB] Test 2. Edge cases. Pulse width 0%%. (1/7)"); @@ -500,8 +514,6 @@ module tb_top; ); $display("[TB] Test 2 complete"); - // $finish; // TODO remove - $display("[TB] Test 3. Random tests"); for (int i = 0; i < 100; i++) begin int r_w, r_p, r_n, r_h, r_sn; From 771225cd77951c7e774e84d058b51b67ccf74f8f Mon Sep 17 00:00:00 2001 From: "babintsev.lv" Date: Tue, 23 Jun 2026 17:27:20 +0300 Subject: [PATCH 7/9] fix: post-implementation timing sim TB passed --- designs/adc_dac_synchoronizer/debug.xdc | 4 ++-- designs/adc_dac_synchoronizer/sync_top.sv | 4 ++-- designs/adc_dac_synchoronizer/tb_sync_top.sv | 23 ++++++++++++-------- 3 files changed, 18 insertions(+), 13 deletions(-) diff --git a/designs/adc_dac_synchoronizer/debug.xdc b/designs/adc_dac_synchoronizer/debug.xdc index 600e406..a3cf907 100644 --- a/designs/adc_dac_synchoronizer/debug.xdc +++ b/designs/adc_dac_synchoronizer/debug.xdc @@ -6,7 +6,7 @@ set_clock_groups -asynchronous -group [get_clocks geneartor_clk] -group [get_clo # set_false_path -through [get_nets -hierarchical {*dac_signal* *internal_wire_singnal* *adc_singnal*}] # set_false_path -through [get_nets {dac_done dac_done_stretched dac_request adc_done adc_request}] -# set_property DONT_TOUCH true [get_cells -hierarchical -filter {NAME =~ *generator_inst*pulse_height_reg*}] -# set_property DONT_TOUCH true [get_cells -hierarchical -filter {NAME =~ *generator_inst*dac_out_reg*}] + set_property DONT_TOUCH true [get_cells -hierarchical -filter {NAME =~ *generator_inst*pulse_height_reg*}] + set_property DONT_TOUCH true [get_cells -hierarchical -filter {NAME =~ *generator_inst*dac_out_reg*}] # Применяем к самому проводу сигнала CE, чтобы Vivado не дробила его # set_property DONT_TOUCH true [get_nets -of_objects [get_pins -hierarchical -filter {PIN_NAME =~ *CE} -of_objects [get_cells *pulse_height_reg*]]] \ No newline at end of file diff --git a/designs/adc_dac_synchoronizer/sync_top.sv b/designs/adc_dac_synchoronizer/sync_top.sv index 6de29c5..13588ab 100644 --- a/designs/adc_dac_synchoronizer/sync_top.sv +++ b/designs/adc_dac_synchoronizer/sync_top.sv @@ -42,8 +42,8 @@ module sync_top else if (ADC_DATA_WIDTH < DAC_DATA_WIDTH) begin : g_truncate // ЦАП шире АЦП (например, 14 -> 12): забираем младшие биты assign internal_wire_signal = dac_signal[DAC_DATA_WIDTH-1:DAC_DATA_WIDTH-ADC_DATA_WIDTH]; - (* dont_touch = "true" *) wire dummy; - assign dummy = ^dac_signal; +// (* mark_debug = "true" *) wire dummy; +// assign dummy = ^dac_signal; end else begin : g_match // Разрядности равны diff --git a/designs/adc_dac_synchoronizer/tb_sync_top.sv b/designs/adc_dac_synchoronizer/tb_sync_top.sv index 63999d5..a722e7e 100644 --- a/designs/adc_dac_synchoronizer/tb_sync_top.sv +++ b/designs/adc_dac_synchoronizer/tb_sync_top.sv @@ -94,9 +94,9 @@ module tb_top; task automatic reset_dut_dac( input int rst_duration // сколько тактов держать сброс ); - @(posedge clk_dac); + @(negedge clk_dac); rst_dac <= 1; - repeat(rst_duration) @(posedge clk_dac); + repeat(rst_duration) @(negedge clk_dac); rst_dac <= 0; endtask @@ -104,9 +104,9 @@ module tb_top; task automatic reset_dut_adc( input int rst_duration // сколько тактов держать сброс ); - @(posedge clk_adc); + @(negedge clk_adc); rst_adc <= 1; - repeat(rst_duration) @(posedge clk_adc); + repeat(rst_duration) @(negedge clk_adc); rst_adc <= 0; endtask @@ -114,8 +114,9 @@ module tb_top; task automatic start_dut( input int start_duration // сколько тактов держать импульс ); + @(negedge clk_dac); // to make signal stable dac_start <= 1; - repeat(start_duration) @(posedge clk_dac); + repeat(start_duration) @(negedge clk_dac); dac_start <= 0; endtask @@ -220,15 +221,19 @@ module tb_top; $display("[TB] -run_test_case- Wait until pulse become high"); end wait(m_axis_tdata != ZERO_LEVEL); + // Фактическое начало импульса. Поступление высокого уровня + pulse_update_val_time = $realtime; + pulse_delay_time_stats.push_back(pulse_update_val_time - pulse_start_time); + // Проверим что высота импульса совпала с заданной. Т.к. OTR != 0 влияет на выходные данные сэмплера, то не будем проверять такие случаи. + @(posedge clk_adc); + #1.5; // Ожидание завершения переходных процессов // Будем считать что из-за OTR данные изменились (по условию OTR + MSB), проверка пропускается, т.к. сложно понять точное значение OTR в момент обработки данных от tdata if (m_axis_tdata != (pulse_height >> 2) && (randomize_out_of_range || out_of_range_val)) begin $display("[ERROR] -run_test_case- Wrong pulse height: %d. Must be: %d", m_axis_tdata, pulse_height >> 2); $finish; end - // Фактическое начало импульса. Поступление высокого уровня - pulse_update_val_time = $realtime; - pulse_delay_time_stats.push_back(pulse_update_val_time - pulse_start_time); + if (VERBOSE >= 4) begin $display("[TB] -run_test_case- Wait until pulse become low"); end @@ -524,7 +529,7 @@ module tb_top; r_w = $urandom_range(10, r_p); // Ширина не больше периода r_n = $urandom_range(1, 10); // Количество импульсов r_h = $urandom_range(0, 2**(`MIN(ADC_DATA_WIDTH, DAC_DATA_WIDTH))-1); // Высота импульса - r_sn = $urandom_range(1, 40); // Число сэмплов + r_sn = $urandom_range(2, 40); // Число сэмплов r_skip = $urandom_range(0, 1); // Случайный сброс (0 - сброс, 1 - пропуск) r_otr = $urandom_range(0, 1); // Out Of Range стартовое значение r_otr_rand = $urandom_range(0, 1); // Сделать OTR случайным From d878bac42aab689a76f98f5784d617c5049aee20 Mon Sep 17 00:00:00 2001 From: "babintsev.lv" Date: Tue, 30 Jun 2026 17:21:49 +0300 Subject: [PATCH 8/9] upd: new top design WIP --- .../ip/clk_wiz_ctrl_inst.xci | 303 ++++++++++-------- designs/reflectometer_base/reflectometer.sv | 149 +++++---- 2 files changed, 243 insertions(+), 209 deletions(-) diff --git a/designs/reflectometer_base/ip/clk_wiz_ctrl_inst.xci b/designs/reflectometer_base/ip/clk_wiz_ctrl_inst.xci index 3b43b73..7db99ba 100644 --- a/designs/reflectometer_base/ip/clk_wiz_ctrl_inst.xci +++ b/designs/reflectometer_base/ip/clk_wiz_ctrl_inst.xci @@ -3,8 +3,8 @@ "ip_inst": { "xci_name": "clk_wiz_ctrl_inst", "component_reference": "xilinx.com:ip:clk_wiz:6.0", - "ip_revision": "16", - "gen_directory": "../../../../eth_generator_top.gen/sources_1/ip/clk_wiz_ctrl_inst", + "ip_revision": "17", + "gen_directory": "../../../../reflectometer_top.gen/sources_1/ip/clk_wiz_ctrl_inst", "parameters": { "component_parameters": { "Component_Name": [ { "value": "clk_wiz_ctrl_inst", "resolve_type": "user", "usage": "all" } ], @@ -22,7 +22,7 @@ "Enable_PLL1": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], "REF_CLK_FREQ": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ], "PRECISION": [ { "value": "1", "resolve_type": "user", "format": "float", "usage": "all" } ], - "PRIMITIVE": [ { "value": "MMCM", "resolve_type": "user", "usage": "all" } ], + "PRIMITIVE": [ { "value": "MMCM", "value_src": "user", "resolve_type": "user", "usage": "all" } ], "PRIMTYPE_SEL": [ { "value": "mmcm_adv", "resolve_type": "user", "usage": "all" } ], "CLOCK_MGR_TYPE": [ { "value": "auto", "resolve_type": "user", "usage": "all" } ], "USE_FREQ_SYNTH": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ], @@ -31,7 +31,7 @@ "USE_MIN_POWER": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], "USE_DYN_PHASE_SHIFT": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], "USE_DYN_RECONFIG": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], - "JITTER_SEL": [ { "value": "No_Jitter", "resolve_type": "user", "usage": "all" } ], + "JITTER_SEL": [ { "value": "Min_O_Jitter", "value_src": "user", "resolve_type": "user", "usage": "all" } ], "PRIM_IN_FREQ": [ { "value": "200.000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], "PRIM_IN_TIMEPERIOD": [ { "value": "10.000", "resolve_type": "user", "format": "float", "usage": "all" } ], "IN_FREQ_UNITS": [ { "value": "Units_MHz", "resolve_type": "user", "usage": "all" } ], @@ -52,12 +52,12 @@ "CLKIN2_JITTER_PS": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ], "CLKOUT1_USED": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ], "CLKOUT2_USED": [ { "value": "true", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ], - "CLKOUT3_USED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], - "CLKOUT4_USED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLKOUT3_USED": [ { "value": "true", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLKOUT4_USED": [ { "value": "true", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ], "CLKOUT5_USED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], "CLKOUT6_USED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], "CLKOUT7_USED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], - "NUM_OUT_CLKS": [ { "value": "2", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "NUM_OUT_CLKS": [ { "value": "4", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], "CLK_OUT1_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], "CLK_OUT2_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], "CLK_OUT3_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], @@ -65,11 +65,11 @@ "CLK_OUT5_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], "CLK_OUT6_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], "CLK_OUT7_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], - "PRIMARY_PORT": [ { "value": "clk_in1", "resolve_type": "user", "usage": "all" } ], - "CLK_OUT1_PORT": [ { "value": "clk_out1", "resolve_type": "user", "usage": "all" } ], - "CLK_OUT2_PORT": [ { "value": "clk_out2", "resolve_type": "user", "usage": "all" } ], - "CLK_OUT3_PORT": [ { "value": "clk_out3", "resolve_type": "user", "usage": "all" } ], - "CLK_OUT4_PORT": [ { "value": "clk_out4", "resolve_type": "user", "usage": "all" } ], + "PRIMARY_PORT": [ { "value": "clk_sys", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "CLK_OUT1_PORT": [ { "value": "clk_adc_65", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "CLK_OUT2_PORT": [ { "value": "clk_adc_65_180", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "CLK_OUT3_PORT": [ { "value": "clk_dac_125", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "CLK_OUT4_PORT": [ { "value": "clk_dac_125_180", "value_src": "user", "resolve_type": "user", "usage": "all" } ], "CLK_OUT5_PORT": [ { "value": "clk_out5", "resolve_type": "user", "usage": "all" } ], "CLK_OUT6_PORT": [ { "value": "clk_out6", "resolve_type": "user", "usage": "all" } ], "CLK_OUT7_PORT": [ { "value": "clk_out7", "resolve_type": "user", "usage": "all" } ], @@ -84,17 +84,17 @@ "PSEN_PORT": [ { "value": "psen", "resolve_type": "user", "usage": "all" } ], "PSINCDEC_PORT": [ { "value": "psincdec", "resolve_type": "user", "usage": "all" } ], "PSDONE_PORT": [ { "value": "psdone", "resolve_type": "user", "usage": "all" } ], - "CLKOUT1_REQUESTED_OUT_FREQ": [ { "value": "125", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT1_REQUESTED_OUT_FREQ": [ { "value": "65.000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], "CLKOUT1_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], "CLKOUT1_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ], - "CLKOUT2_REQUESTED_OUT_FREQ": [ { "value": "65.000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], - "CLKOUT2_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT2_REQUESTED_OUT_FREQ": [ { "value": "125", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT2_REQUESTED_PHASE": [ { "value": "0.000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], "CLKOUT2_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ], - "CLKOUT3_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ], - "CLKOUT3_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT3_REQUESTED_OUT_FREQ": [ { "value": "125", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT3_REQUESTED_PHASE": [ { "value": "180", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], "CLKOUT3_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ], - "CLKOUT4_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ], - "CLKOUT4_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT4_REQUESTED_OUT_FREQ": [ { "value": "100.000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT4_REQUESTED_PHASE": [ { "value": "0.000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], "CLKOUT4_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ], "CLKOUT5_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ], "CLKOUT5_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], @@ -114,15 +114,15 @@ "CLKOUT5_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], "CLKOUT6_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], "CLKOUT7_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], - "PRIM_SOURCE": [ { "value": "Single_ended_clock_capable_pin", "resolve_type": "user", "usage": "all" } ], - "CLKOUT1_DRIVES": [ { "value": "BUFG", "resolve_type": "user", "usage": "all" } ], - "CLKOUT2_DRIVES": [ { "value": "BUFG", "resolve_type": "user", "usage": "all" } ], - "CLKOUT3_DRIVES": [ { "value": "BUFG", "resolve_type": "user", "usage": "all" } ], - "CLKOUT4_DRIVES": [ { "value": "BUFG", "resolve_type": "user", "usage": "all" } ], - "CLKOUT5_DRIVES": [ { "value": "BUFG", "resolve_type": "user", "usage": "all" } ], - "CLKOUT6_DRIVES": [ { "value": "BUFG", "resolve_type": "user", "usage": "all" } ], - "CLKOUT7_DRIVES": [ { "value": "BUFG", "resolve_type": "user", "usage": "all" } ], - "FEEDBACK_SOURCE": [ { "value": "FDBK_AUTO", "resolve_type": "user", "usage": "all" } ], + "PRIM_SOURCE": [ { "value": "Single_ended_clock_capable_pin", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "CLKOUT1_DRIVES": [ { "value": "BUFGCE", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "CLKOUT2_DRIVES": [ { "value": "BUFGCE", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "CLKOUT3_DRIVES": [ { "value": "BUFGCE", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "CLKOUT4_DRIVES": [ { "value": "BUFGCE", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "CLKOUT5_DRIVES": [ { "value": "BUFGCE", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "CLKOUT6_DRIVES": [ { "value": "BUFGCE", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "CLKOUT7_DRIVES": [ { "value": "BUFGCE", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "FEEDBACK_SOURCE": [ { "value": "FDBK_AUTO", "value_src": "user", "resolve_type": "user", "usage": "all" } ], "CLKFB_IN_SIGNALING": [ { "value": "SINGLE", "resolve_type": "user", "usage": "all" } ], "CLKFB_IN_PORT": [ { "value": "clkfb_in", "resolve_type": "user", "usage": "all" } ], "CLKFB_IN_P_PORT": [ { "value": "clkfb_in_p", "resolve_type": "user", "usage": "all" } ], @@ -141,7 +141,7 @@ "USE_CLK_VALID": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], "USE_INCLK_STOPPED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], "USE_CLKFB_STOPPED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], - "RESET_PORT": [ { "value": "reset", "resolve_type": "user", "usage": "all" } ], + "RESET_PORT": [ { "value": "resetn", "value_src": "user", "resolve_type": "user", "usage": "all" } ], "LOCKED_PORT": [ { "value": "locked", "resolve_type": "user", "usage": "all" } ], "POWER_DOWN_PORT": [ { "value": "power_down", "resolve_type": "user", "usage": "all" } ], "CLK_VALID_PORT": [ { "value": "CLK_VALID", "resolve_type": "user", "usage": "all" } ], @@ -152,36 +152,36 @@ "SS_MODE": [ { "value": "CENTER_HIGH", "resolve_type": "user", "usage": "all" } ], "SS_MOD_FREQ": [ { "value": "250", "resolve_type": "user", "format": "float", "usage": "all" } ], "SS_MOD_TIME": [ { "value": "0.004", "resolve_type": "user", "format": "float", "usage": "all" } ], - "OVERRIDE_MMCM": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "OVERRIDE_MMCM": [ { "value": "false", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ], "MMCM_NOTES": [ { "value": "None", "resolve_type": "user", "usage": "all" } ], "MMCM_DIVCLK_DIVIDE": [ { "value": "4", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], - "MMCM_BANDWIDTH": [ { "value": "OPTIMIZED", "resolve_type": "user", "usage": "all" } ], - "MMCM_CLKFBOUT_MULT_F": [ { "value": "16.875", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_BANDWIDTH": [ { "value": "HIGH", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "MMCM_CLKFBOUT_MULT_F": [ { "value": "27.625", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], "MMCM_CLKFBOUT_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], "MMCM_CLKFBOUT_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], "MMCM_CLKIN1_PERIOD": [ { "value": "5.000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], - "MMCM_CLKIN2_PERIOD": [ { "value": "10.0", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKIN2_PERIOD": [ { "value": "10.000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], "MMCM_CLKOUT4_CASCADE": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], "MMCM_CLOCK_HOLD": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], - "MMCM_COMPENSATION": [ { "value": "ZHOLD", "resolve_type": "user", "usage": "all" } ], + "MMCM_COMPENSATION": [ { "value": "ZHOLD", "value_src": "user", "resolve_type": "user", "usage": "all" } ], "MMCM_REF_JITTER1": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ], "MMCM_REF_JITTER2": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ], "MMCM_STARTUP_WAIT": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], - "MMCM_CLKOUT0_DIVIDE_F": [ { "value": "6.750", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT0_DIVIDE_F": [ { "value": "21.250", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], "MMCM_CLKOUT0_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ], "MMCM_CLKOUT0_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], "MMCM_CLKOUT0_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], - "MMCM_CLKOUT1_DIVIDE": [ { "value": "13", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "MMCM_CLKOUT1_DIVIDE": [ { "value": "11", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], "MMCM_CLKOUT1_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ], - "MMCM_CLKOUT1_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT1_PHASE": [ { "value": "180.000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], "MMCM_CLKOUT1_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], - "MMCM_CLKOUT2_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "MMCM_CLKOUT2_DIVIDE": [ { "value": "11", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], "MMCM_CLKOUT2_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ], - "MMCM_CLKOUT2_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT2_PHASE": [ { "value": "0.000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], "MMCM_CLKOUT2_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], - "MMCM_CLKOUT3_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "MMCM_CLKOUT3_DIVIDE": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], "MMCM_CLKOUT3_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ], - "MMCM_CLKOUT3_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT3_PHASE": [ { "value": "180.000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], "MMCM_CLKOUT3_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], "MMCM_CLKOUT4_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], "MMCM_CLKOUT4_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ], @@ -223,8 +223,8 @@ "PLL_CLKOUT5_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], "PLL_CLKOUT5_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ], "PLL_CLKOUT5_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], - "RESET_TYPE": [ { "value": "ACTIVE_HIGH", "resolve_type": "user", "usage": "all" } ], - "USE_SAFE_CLOCK_STARTUP": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "RESET_TYPE": [ { "value": "ACTIVE_LOW", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "USE_SAFE_CLOCK_STARTUP": [ { "value": "true", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ], "USE_CLOCK_SEQUENCING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], "CLKOUT1_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], "CLKOUT2_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], @@ -245,14 +245,14 @@ "CDDCREQ_PORT": [ { "value": "cddcreq", "resolve_type": "user", "usage": "all" } ], "ENABLE_CLKOUTPHY": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], "CLKOUTPHY_REQUESTED_FREQ": [ { "value": "600.000", "resolve_type": "user", "format": "float", "usage": "all" } ], - "CLKOUT1_JITTER": [ { "value": "162.582", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], - "CLKOUT1_PHASE_ERROR": [ { "value": "137.238", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], - "CLKOUT2_JITTER": [ { "value": "185.296", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], - "CLKOUT2_PHASE_ERROR": [ { "value": "137.238", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], - "CLKOUT3_JITTER": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ], - "CLKOUT3_PHASE_ERROR": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ], - "CLKOUT4_JITTER": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ], - "CLKOUT4_PHASE_ERROR": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT1_JITTER": [ { "value": "137.256", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT1_PHASE_ERROR": [ { "value": "148.044", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT2_JITTER": [ { "value": "137.256", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT2_PHASE_ERROR": [ { "value": "148.044", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT3_JITTER": [ { "value": "123.850", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT3_PHASE_ERROR": [ { "value": "148.044", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT4_JITTER": [ { "value": "123.850", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT4_PHASE_ERROR": [ { "value": "148.044", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], "CLKOUT5_JITTER": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ], "CLKOUT5_PHASE_ERROR": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ], "CLKOUT6_JITTER": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ], @@ -280,8 +280,8 @@ "C_Enable_PLL1": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_REF_CLK_FREQ": [ { "value": "100.0", "resolve_type": "generated", "format": "float", "usage": "all" } ], "C_PRECISION": [ { "value": "1", "resolve_type": "generated", "format": "float", "usage": "all" } ], - "C_CLKOUT3_USED": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], - "C_CLKOUT4_USED": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_CLKOUT3_USED": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_CLKOUT4_USED": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_CLKOUT5_USED": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_CLKOUT6_USED": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_CLKOUT7_USED": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], @@ -295,9 +295,9 @@ "C_USE_PHASE_ALIGNMENT": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_PRIM_IN_JITTER": [ { "value": "0.010", "resolve_type": "generated", "format": "float", "usage": "all" } ], "C_SECONDARY_IN_JITTER": [ { "value": "0.010", "resolve_type": "generated", "format": "float", "usage": "all" } ], - "C_JITTER_SEL": [ { "value": "No_Jitter", "resolve_type": "generated", "usage": "all" } ], + "C_JITTER_SEL": [ { "value": "Min_O_Jitter", "resolve_type": "generated", "usage": "all" } ], "C_USE_MIN_POWER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], - "C_USE_MIN_O_JITTER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_USE_MIN_O_JITTER": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_USE_MAX_I_JITTER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_USE_DYN_PHASE_SHIFT": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_OPTIMIZE_CLOCKING_STRUCTURE_EN": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], @@ -318,43 +318,43 @@ "C_SECONDARY_SOURCE": [ { "value": "Single_ended_clock_capable_pin", "resolve_type": "generated", "usage": "all" } ], "C_CLKFB_IN_SIGNALING": [ { "value": "SINGLE", "resolve_type": "generated", "usage": "all" } ], "C_USE_RESET": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], - "C_RESET_LOW": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_RESET_LOW": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_USE_LOCKED": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_USE_INCLK_STOPPED": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_USE_CLKFB_STOPPED": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_USE_POWER_DOWN": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_USE_STATUS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_USE_FREEZE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], - "C_NUM_OUT_CLKS": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ], - "C_CLKOUT1_DRIVES": [ { "value": "BUFG", "resolve_type": "generated", "usage": "all" } ], - "C_CLKOUT2_DRIVES": [ { "value": "BUFG", "resolve_type": "generated", "usage": "all" } ], - "C_CLKOUT3_DRIVES": [ { "value": "BUFG", "resolve_type": "generated", "usage": "all" } ], - "C_CLKOUT4_DRIVES": [ { "value": "BUFG", "resolve_type": "generated", "usage": "all" } ], - "C_CLKOUT5_DRIVES": [ { "value": "BUFG", "resolve_type": "generated", "usage": "all" } ], - "C_CLKOUT6_DRIVES": [ { "value": "BUFG", "resolve_type": "generated", "usage": "all" } ], - "C_CLKOUT7_DRIVES": [ { "value": "BUFG", "resolve_type": "generated", "usage": "all" } ], + "C_NUM_OUT_CLKS": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_CLKOUT1_DRIVES": [ { "value": "BUFGCE", "resolve_type": "generated", "usage": "all" } ], + "C_CLKOUT2_DRIVES": [ { "value": "BUFGCE", "resolve_type": "generated", "usage": "all" } ], + "C_CLKOUT3_DRIVES": [ { "value": "BUFGCE", "resolve_type": "generated", "usage": "all" } ], + "C_CLKOUT4_DRIVES": [ { "value": "BUFGCE", "resolve_type": "generated", "usage": "all" } ], + "C_CLKOUT5_DRIVES": [ { "value": "BUFGCE", "resolve_type": "generated", "usage": "all" } ], + "C_CLKOUT6_DRIVES": [ { "value": "BUFGCE", "resolve_type": "generated", "usage": "all" } ], + "C_CLKOUT7_DRIVES": [ { "value": "BUFGCE", "resolve_type": "generated", "usage": "all" } ], "C_INCLK_SUM_ROW0": [ { "value": "Input Clock Freq (MHz) Input Jitter (UI)", "resolve_type": "generated", "usage": "all" } ], "C_INCLK_SUM_ROW1": [ { "value": "__primary_________200.000____________0.010", "resolve_type": "generated", "usage": "all" } ], "C_INCLK_SUM_ROW2": [ { "value": "no_secondary_input_clock ", "resolve_type": "generated", "usage": "all" } ], "C_OUTCLK_SUM_ROW0A": [ { "value": " Output Output Phase Duty Cycle Pk-to-Pk Phase", "resolve_type": "generated", "usage": "all" } ], "C_OUTCLK_SUM_ROW0B": [ { "value": " Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)", "resolve_type": "generated", "usage": "all" } ], - "C_OUTCLK_SUM_ROW1": [ { "value": "clk_out1__125.00000______0.000______50.0______162.582____137.238", "resolve_type": "generated", "usage": "all" } ], - "C_OUTCLK_SUM_ROW2": [ { "value": "clk_out2__64.90385______0.000______50.0______185.296____137.238", "resolve_type": "generated", "usage": "all" } ], - "C_OUTCLK_SUM_ROW3": [ { "value": "no_CLK_OUT3_output", "resolve_type": "generated", "usage": "all" } ], - "C_OUTCLK_SUM_ROW4": [ { "value": "no_CLK_OUT4_output", "resolve_type": "generated", "usage": "all" } ], + "C_OUTCLK_SUM_ROW1": [ { "value": "clk_adc_65__65.00000______0.000______50.0______126.994____139.124", "resolve_type": "generated", "usage": "all" } ], + "C_OUTCLK_SUM_ROW2": [ { "value": "clk_adc_65_180__125.56818____180.000______50.0______113.769____139.124", "resolve_type": "generated", "usage": "all" } ], + "C_OUTCLK_SUM_ROW3": [ { "value": "clk_dac_125__125.56818______0.000______50.0______113.769____139.124", "resolve_type": "generated", "usage": "all" } ], + "C_OUTCLK_SUM_ROW4": [ { "value": "clk_dac_125_180__1381.25000____180.000______50.0_______76.736____139.124", "resolve_type": "generated", "usage": "all" } ], "C_OUTCLK_SUM_ROW5": [ { "value": "no_CLK_OUT5_output", "resolve_type": "generated", "usage": "all" } ], "C_OUTCLK_SUM_ROW6": [ { "value": "no_CLK_OUT6_output", "resolve_type": "generated", "usage": "all" } ], "C_OUTCLK_SUM_ROW7": [ { "value": "no_CLK_OUT7_output", "resolve_type": "generated", "usage": "all" } ], - "C_CLKOUT1_REQUESTED_OUT_FREQ": [ { "value": "125", "resolve_type": "generated", "format": "float", "usage": "all" } ], - "C_CLKOUT2_REQUESTED_OUT_FREQ": [ { "value": "65.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], - "C_CLKOUT3_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_CLKOUT1_REQUESTED_OUT_FREQ": [ { "value": "65.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_CLKOUT2_REQUESTED_OUT_FREQ": [ { "value": "125", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_CLKOUT3_REQUESTED_OUT_FREQ": [ { "value": "125", "resolve_type": "generated", "format": "float", "usage": "all" } ], "C_CLKOUT4_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], "C_CLKOUT5_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], "C_CLKOUT6_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], "C_CLKOUT7_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], "C_CLKOUT1_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], "C_CLKOUT2_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], - "C_CLKOUT3_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_CLKOUT3_REQUESTED_PHASE": [ { "value": "180", "resolve_type": "generated", "format": "float", "usage": "all" } ], "C_CLKOUT4_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], "C_CLKOUT5_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], "C_CLKOUT6_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], @@ -366,28 +366,28 @@ "C_CLKOUT5_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], "C_CLKOUT6_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], "C_CLKOUT7_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], - "C_CLKOUT1_OUT_FREQ": [ { "value": "125.00000", "resolve_type": "generated", "format": "float", "usage": "all" } ], - "C_CLKOUT2_OUT_FREQ": [ { "value": "64.90385", "resolve_type": "generated", "format": "float", "usage": "all" } ], - "C_CLKOUT3_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], - "C_CLKOUT4_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_CLKOUT1_OUT_FREQ": [ { "value": "65.00000", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_CLKOUT2_OUT_FREQ": [ { "value": "125.56818", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_CLKOUT3_OUT_FREQ": [ { "value": "125.56818", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_CLKOUT4_OUT_FREQ": [ { "value": "1381.25000", "resolve_type": "generated", "format": "float", "usage": "all" } ], "C_CLKOUT5_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], "C_CLKOUT6_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], "C_CLKOUT7_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], "C_CLKOUT1_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], - "C_CLKOUT2_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_CLKOUT2_PHASE": [ { "value": "180.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], "C_CLKOUT3_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], - "C_CLKOUT4_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_CLKOUT4_PHASE": [ { "value": "180.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], "C_CLKOUT5_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], "C_CLKOUT6_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], "C_CLKOUT7_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], "C_CLKOUT1_DUTY_CYCLE": [ { "value": "50.0", "resolve_type": "generated", "format": "float", "usage": "all" } ], "C_CLKOUT2_DUTY_CYCLE": [ { "value": "50.0", "resolve_type": "generated", "format": "float", "usage": "all" } ], - "C_CLKOUT3_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], - "C_CLKOUT4_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_CLKOUT3_DUTY_CYCLE": [ { "value": "50.0", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_CLKOUT4_DUTY_CYCLE": [ { "value": "50.0", "resolve_type": "generated", "format": "float", "usage": "all" } ], "C_CLKOUT5_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], "C_CLKOUT6_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], "C_CLKOUT7_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], - "C_USE_SAFE_CLOCK_STARTUP": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_USE_SAFE_CLOCK_STARTUP": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_USE_CLOCK_SEQUENCING": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_CLKOUT1_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_CLKOUT2_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], @@ -397,10 +397,10 @@ "C_CLKOUT6_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_CLKOUT7_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_MMCM_NOTES": [ { "value": "None", "resolve_type": "generated", "usage": "all" } ], - "C_MMCM_BANDWIDTH": [ { "value": "OPTIMIZED", "resolve_type": "generated", "usage": "all" } ], - "C_MMCM_CLKFBOUT_MULT_F": [ { "value": "16.875", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_MMCM_BANDWIDTH": [ { "value": "HIGH", "resolve_type": "generated", "usage": "all" } ], + "C_MMCM_CLKFBOUT_MULT_F": [ { "value": "27.625", "resolve_type": "generated", "format": "float", "usage": "all" } ], "C_MMCM_CLKIN1_PERIOD": [ { "value": "5.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], - "C_MMCM_CLKIN2_PERIOD": [ { "value": "10.0", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_MMCM_CLKIN2_PERIOD": [ { "value": "10.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], "C_MMCM_CLKOUT4_CASCADE": [ { "value": "FALSE", "resolve_type": "generated", "format": "bool", "usage": "all" } ], "C_MMCM_CLOCK_HOLD": [ { "value": "FALSE", "resolve_type": "generated", "format": "bool", "usage": "all" } ], "C_MMCM_COMPENSATION": [ { "value": "ZHOLD", "resolve_type": "generated", "usage": "all" } ], @@ -408,9 +408,9 @@ "C_MMCM_REF_JITTER1": [ { "value": "0.010", "resolve_type": "generated", "format": "float", "usage": "all" } ], "C_MMCM_REF_JITTER2": [ { "value": "0.010", "resolve_type": "generated", "format": "float", "usage": "all" } ], "C_MMCM_STARTUP_WAIT": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ], - "C_MMCM_CLKOUT0_DIVIDE_F": [ { "value": "6.750", "resolve_type": "generated", "format": "float", "usage": "all" } ], - "C_MMCM_CLKOUT1_DIVIDE": [ { "value": "13", "resolve_type": "generated", "format": "long", "usage": "all" } ], - "C_MMCM_CLKOUT2_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_MMCM_CLKOUT0_DIVIDE_F": [ { "value": "21.250", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_MMCM_CLKOUT1_DIVIDE": [ { "value": "11", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_MMCM_CLKOUT2_DIVIDE": [ { "value": "11", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_MMCM_CLKOUT3_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_MMCM_CLKOUT4_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_MMCM_CLKOUT5_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], @@ -424,9 +424,9 @@ "C_MMCM_CLKOUT6_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ], "C_MMCM_CLKFBOUT_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], "C_MMCM_CLKOUT0_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], - "C_MMCM_CLKOUT1_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_MMCM_CLKOUT1_PHASE": [ { "value": "180.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], "C_MMCM_CLKOUT2_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], - "C_MMCM_CLKOUT3_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_MMCM_CLKOUT3_PHASE": [ { "value": "180.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], "C_MMCM_CLKOUT4_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], "C_MMCM_CLKOUT5_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], "C_MMCM_CLKOUT6_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], @@ -468,16 +468,16 @@ "C_CLOCK_MGR_TYPE": [ { "value": "NA", "resolve_type": "generated", "usage": "all" } ], "C_OVERRIDE_MMCM": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_OVERRIDE_PLL": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], - "C_PRIMARY_PORT": [ { "value": "clk_in1", "resolve_type": "generated", "usage": "all" } ], + "C_PRIMARY_PORT": [ { "value": "clk_sys", "resolve_type": "generated", "usage": "all" } ], "C_SECONDARY_PORT": [ { "value": "clk_in2", "resolve_type": "generated", "usage": "all" } ], - "C_CLK_OUT1_PORT": [ { "value": "clk_out1", "resolve_type": "generated", "usage": "all" } ], - "C_CLK_OUT2_PORT": [ { "value": "clk_out2", "resolve_type": "generated", "usage": "all" } ], - "C_CLK_OUT3_PORT": [ { "value": "clk_out3", "resolve_type": "generated", "usage": "all" } ], - "C_CLK_OUT4_PORT": [ { "value": "clk_out4", "resolve_type": "generated", "usage": "all" } ], + "C_CLK_OUT1_PORT": [ { "value": "clk_adc_65", "resolve_type": "generated", "usage": "all" } ], + "C_CLK_OUT2_PORT": [ { "value": "clk_adc_65_180", "resolve_type": "generated", "usage": "all" } ], + "C_CLK_OUT3_PORT": [ { "value": "clk_dac_125", "resolve_type": "generated", "usage": "all" } ], + "C_CLK_OUT4_PORT": [ { "value": "clk_dac_125_180", "resolve_type": "generated", "usage": "all" } ], "C_CLK_OUT5_PORT": [ { "value": "clk_out5", "resolve_type": "generated", "usage": "all" } ], "C_CLK_OUT6_PORT": [ { "value": "clk_out6", "resolve_type": "generated", "usage": "all" } ], "C_CLK_OUT7_PORT": [ { "value": "clk_out7", "resolve_type": "generated", "usage": "all" } ], - "C_RESET_PORT": [ { "value": "reset", "resolve_type": "generated", "usage": "all" } ], + "C_RESET_PORT": [ { "value": "resetn", "resolve_type": "generated", "usage": "all" } ], "C_LOCKED_PORT": [ { "value": "locked", "resolve_type": "generated", "usage": "all" } ], "C_CLKFB_IN_PORT": [ { "value": "clkfb_in", "resolve_type": "generated", "usage": "all" } ], "C_CLKFB_IN_P_PORT": [ { "value": "clkfb_in_p", "resolve_type": "generated", "usage": "all" } ], @@ -540,12 +540,12 @@ "C_FILTER_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ], "C_FILTER_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ], "C_DIVIDE1_AUTO": [ { "value": "1", "resolve_type": "generated", "usage": "all" } ], - "C_DIVIDE2_AUTO": [ { "value": "1.9259259259259258", "resolve_type": "generated", "usage": "all" } ], - "C_DIVIDE3_AUTO": [ { "value": "0.14814814814814814", "resolve_type": "generated", "usage": "all" } ], - "C_DIVIDE4_AUTO": [ { "value": "0.14814814814814814", "resolve_type": "generated", "usage": "all" } ], - "C_DIVIDE5_AUTO": [ { "value": "0.14814814814814814", "resolve_type": "generated", "usage": "all" } ], - "C_DIVIDE6_AUTO": [ { "value": "0.14814814814814814", "resolve_type": "generated", "usage": "all" } ], - "C_DIVIDE7_AUTO": [ { "value": "0.14814814814814814", "resolve_type": "generated", "usage": "all" } ], + "C_DIVIDE2_AUTO": [ { "value": "0.5176470588235295", "resolve_type": "generated", "usage": "all" } ], + "C_DIVIDE3_AUTO": [ { "value": "0.5176470588235295", "resolve_type": "generated", "usage": "all" } ], + "C_DIVIDE4_AUTO": [ { "value": "0.047058823529411764", "resolve_type": "generated", "usage": "all" } ], + "C_DIVIDE5_AUTO": [ { "value": "0.047058823529411764", "resolve_type": "generated", "usage": "all" } ], + "C_DIVIDE6_AUTO": [ { "value": "0.047058823529411764", "resolve_type": "generated", "usage": "all" } ], + "C_DIVIDE7_AUTO": [ { "value": "0.047058823529411764", "resolve_type": "generated", "usage": "all" } ], "C_PLLBUFGCEDIV": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ], "C_MMCMBUFGCEDIV": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ], "C_PLLBUFGCEDIV1": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ], @@ -566,66 +566,68 @@ "C_CLKOUT5_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ], "C_CLKOUT6_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ], "C_CLKOUT7_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ], - "C_CLKOUT0_ACTUAL_FREQ": [ { "value": "125.00000", "resolve_type": "generated", "usage": "all" } ], - "C_CLKOUT1_ACTUAL_FREQ": [ { "value": "64.90385", "resolve_type": "generated", "usage": "all" } ], - "C_CLKOUT2_ACTUAL_FREQ": [ { "value": "100.000", "resolve_type": "generated", "usage": "all" } ], - "C_CLKOUT3_ACTUAL_FREQ": [ { "value": "100.000", "resolve_type": "generated", "usage": "all" } ], + "C_CLKOUT0_ACTUAL_FREQ": [ { "value": "65.00000", "resolve_type": "generated", "usage": "all" } ], + "C_CLKOUT1_ACTUAL_FREQ": [ { "value": "125.93750", "resolve_type": "generated", "usage": "all" } ], + "C_CLKOUT2_ACTUAL_FREQ": [ { "value": "125.93750", "resolve_type": "generated", "usage": "all" } ], + "C_CLKOUT3_ACTUAL_FREQ": [ { "value": "100.75000", "resolve_type": "generated", "usage": "all" } ], "C_CLKOUT4_ACTUAL_FREQ": [ { "value": "100.000", "resolve_type": "generated", "usage": "all" } ], "C_CLKOUT5_ACTUAL_FREQ": [ { "value": "100.000", "resolve_type": "generated", "usage": "all" } ], "C_CLKOUT6_ACTUAL_FREQ": [ { "value": "100.000", "resolve_type": "generated", "usage": "all" } ], "C_M_MAX": [ { "value": "64.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], "C_M_MIN": [ { "value": "2.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], - "C_D_MAX": [ { "value": "80.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_D_MAX": [ { "value": "93.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], "C_D_MIN": [ { "value": "1.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], "C_O_MAX": [ { "value": "128.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], "C_O_MIN": [ { "value": "1.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], "C_VCO_MIN": [ { "value": "600.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], - "C_VCO_MAX": [ { "value": "1200.000", "resolve_type": "generated", "format": "float", "usage": "all" } ] + "C_VCO_MAX": [ { "value": "1440.000", "resolve_type": "generated", "format": "float", "usage": "all" } ] }, "project_parameters": { - "ARCHITECTURE": [ { "value": "artix7" } ], - "BASE_BOARD_PART": [ { "value": "" } ], - "BOARD_CONNECTIONS": [ { "value": "" } ], - "DEVICE": [ { "value": "xc7a35t" } ], - "PACKAGE": [ { "value": "fgg484" } ], - "PREFHDL": [ { "value": "VERILOG" } ], - "SILICON_REVISION": [ { "value": "" } ], - "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ], - "SPEEDGRADE": [ { "value": "-1" } ], - "STATIC_POWER": [ { "value": "" } ], - "TEMPERATURE_GRADE": [ { "value": "" } ] + "ARCHITECTURE": [ { "value": "artix7", "resolve_type": "generated", "usage": "all" } ], + "BASE_BOARD_PART": [ { "value": "", "resolve_type": "generated", "usage": "all" } ], + "BOARD_CONNECTIONS": [ { "value": "", "resolve_type": "generated", "usage": "all" } ], + "DEVICE": [ { "value": "xc7a100t", "resolve_type": "generated", "usage": "all" } ], + "PACKAGE": [ { "value": "fgg484", "resolve_type": "generated", "usage": "all" } ], + "PREFHDL": [ { "value": "VERILOG", "resolve_type": "generated", "usage": "all" } ], + "SILICON_REVISION": [ { "value": "", "resolve_type": "generated", "usage": "all" } ], + "SIMULATOR_LANGUAGE": [ { "value": "MIXED", "resolve_type": "generated", "usage": "all" } ], + "SPEEDGRADE": [ { "value": "-2", "resolve_type": "generated", "usage": "all" } ], + "STATIC_POWER": [ { "value": "", "resolve_type": "generated", "usage": "all" } ], + "TEMPERATURE_GRADE": [ { "value": "", "resolve_type": "generated", "usage": "all" } ] }, "runtime_parameters": { "IPCONTEXT": [ { "value": "IP_Flow" } ], - "IPREVISION": [ { "value": "16" } ], + "IPREVISION": [ { "value": "17" } ], "MANAGED": [ { "value": "TRUE" } ], - "OUTPUTDIR": [ { "value": "../../../../eth_generator_top.gen/sources_1/ip/clk_wiz_ctrl_inst" } ], + "OUTPUTDIR": [ { "value": "../../../../reflectometer_top.gen/sources_1/ip/clk_wiz_ctrl_inst" } ], "SELECTEDSIMMODEL": [ { "value": "" } ], "SHAREDDIR": [ { "value": "." } ], - "SWVERSION": [ { "value": "2025.1" } ], + "SWVERSION": [ { "value": "2025.2" } ], "SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ] } }, "boundary": { "ports": { - "reset": [ { "direction": "in", "driver_value": "0" } ], - "clk_in1": [ { "direction": "in" } ], - "clk_out1": [ { "direction": "out" } ], - "clk_out2": [ { "direction": "out" } ], + "resetn": [ { "direction": "in", "driver_value": "0" } ], + "clk_sys": [ { "direction": "in" } ], + "clk_adc_65": [ { "direction": "out" } ], + "clk_adc_65_180": [ { "direction": "out" } ], + "clk_dac_125": [ { "direction": "out" } ], + "clk_dac_125_180": [ { "direction": "out" } ], "locked": [ { "direction": "out" } ] }, "interfaces": { - "reset": { + "resetn": { "vlnv": "xilinx.com:signal:reset:1.0", "abstraction_type": "xilinx.com:signal:reset_rtl:1.0", "mode": "slave", "parameters": { - "POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "usage": "all" } ], + "POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "usage": "all" } ], "BOARD.ASSOCIATED_PARAM": [ { "value": "RESET_BOARD_INTERFACE", "value_src": "constant", "usage": "all" } ], "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ] }, "port_maps": { - "RST": [ { "physical_name": "reset" } ] + "RST": [ { "physical_name": "resetn" } ] } }, "clock_CLK_IN1": { @@ -644,7 +646,7 @@ "BOARD.ASSOCIATED_PARAM": [ { "value": "CLK_IN1_BOARD_INTERFACE", "usage": "all", "is_static_object": false } ] }, "port_maps": { - "CLK_IN1": [ { "physical_name": "clk_in1" } ] + "CLK_IN1": [ { "physical_name": "clk_sys" } ] } }, "clock_CLK_OUT1": { @@ -662,7 +664,7 @@ "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ] }, "port_maps": { - "CLK_OUT1": [ { "physical_name": "clk_out1" } ] + "CLK_OUT1": [ { "physical_name": "clk_adc_65" } ] } }, "clock_CLK_OUT2": { @@ -680,10 +682,47 @@ "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ] }, "port_maps": { - "CLK_OUT2": [ { "physical_name": "clk_out2" } ] + "CLK_OUT2": [ { "physical_name": "clk_adc_65_180" } ] + } + }, + "clock_CLK_OUT3": { + "vlnv": "xilinx.com:signal:clock:1.0", + "abstraction_type": "xilinx.com:signal:clock_rtl:1.0", + "mode": "master", + "parameters": { + "FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ], + "CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "ASSOCIATED_BUSIF": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "ASSOCIATED_RESET": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ] + }, + "port_maps": { + "CLK_OUT3": [ { "physical_name": "clk_dac_125" } ] + } + }, + "clock_CLK_OUT4": { + "vlnv": "xilinx.com:signal:clock:1.0", + "abstraction_type": "xilinx.com:signal:clock_rtl:1.0", + "mode": "master", + "parameters": { + "FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ], + "CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "ASSOCIATED_BUSIF": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "ASSOCIATED_RESET": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ] + }, + "port_maps": { + "CLK_OUT4": [ { "physical_name": "clk_dac_125_180" } ] } } } } - } + }, + "checksum": "5f2160a7" } \ No newline at end of file diff --git a/designs/reflectometer_base/reflectometer.sv b/designs/reflectometer_base/reflectometer.sv index 295004d..fc59256 100644 --- a/designs/reflectometer_base/reflectometer.sv +++ b/designs/reflectometer_base/reflectometer.sv @@ -1,8 +1,8 @@ `timescale 1 ns / 1 ns module reflectometer_top #( - parameter int unsigned DAC_DATA_WIDTH = 14, - parameter int unsigned ADC_DATA_WIDTH = 12, + parameter DAC_DATA_WIDTH = 14, + parameter ADC_DATA_WIDTH = 12, parameter PACK_FACTOR = 1, parameter PROCESS_MODE = 0, parameter ZERO_LEVEL = 8192, @@ -11,69 +11,65 @@ module reflectometer_top #( parameter WINDOW_SIZE = 65, parameter PACKET_SIZE = 1024 )( - input sys_clk, - input rst_n, + input clk_sys, + input rst_n, + + // Output AXI-Stream for Accumulator + input clk_m_axis, + output wire [7:0] m_axis_tx_tdata, + output wire m_axis_tx_tvalid, + input wire m_axis_tx_tready, + output wire m_axis_tx_tlast, - output [3:0] led, + // Input AXI-Stream for Controller + input clk_s_axis, + input wire [7:0] s_axis_rx_tdata, + input wire s_axis_rx_tvalid, + input wire s_axis_rx_tlast, + output wire s_axis_rx_tready, - input gmii_rx_clk, - input gmii_tx_clk, + // Reflectometer status + output wire [3:0] status_leds, // System current status indicators + input wire req_ready, // MAC handshake ready + output wire send_req, // MAC handshake send - (* MARK_DEBUG="true" *) output logic [7:0] s_axis_tx_tdata, - (* MARK_DEBUG="true" *) output logic s_axis_tx_tvalid, - (* MARK_DEBUG="true" *) input logic s_axis_tx_tready, - (* MARK_DEBUG="true" *) output logic s_axis_tx_tlast, - - (* MARK_DEBUG="true" *) input wire [7:0] m_axis_rx_tdata, - (* MARK_DEBUG="true" *) input wire m_axis_rx_tvalid, - (* MARK_DEBUG="true" *) input wire m_axis_rx_tlast, - (* MARK_DEBUG="true" *) output wire m_axis_rx_tready, - - // axis_mac - - (* MARK_DEBUG="true" *) input logic req_ready, - (* MARK_DEBUG="true" *) output logic send_req, - - // DAC - - output wire p2_clk, - (* MARK_DEBUG="true" *) output wire [DAC_DATA_WIDTH-1:0] p2_data, - (* MARK_DEBUG="true" *) output wire p2_wrt, - - // ADC - output ch2_clk, - (* MARK_DEBUG="true" *) input [ADC_DATA_WIDTH-1:0] ch2_data, - input ch2_otr + // Generator (DAC) + output wire dac_clock, + output wire [DAC_DATA_WIDTH-1:0] dac_out, + output wire dac_wrt, + // Sampler (ADC) + output wire adc_clock, + input wire [ADC_DATA_WIDTH-1:0] adc_data, + input wire adc_otr ); - - // ------------------------------------------------------------------------- - // IDELAYCTRL - // ------------------------------------------------------------------------- - (* IODELAY_GROUP = "rgmii_idelay_group" *) - IDELAYCTRL IDELAYCTRL_inst ( - .RDY (), - .REFCLK (sys_clk), - .RST (1'b0) - ); - // ------------------------------------------------------------------------- // Generated clocks for controller // Need to create this IP in Vivado: // input : 200 MHz - // output0: 130 MHz - // output1: 65 MHz + // ADC: + // output0: 65 Mhz 0* phase for logic + // output1: 65 MHz 180* phase for output clocking + // DAC: + // output2: 125 Mhz 0* phase for logic + // output3: 125 MHz 180* phase for output clocking // ------------------------------------------------------------------------- - wire dac_clk; - wire adc_clk; - wire clk_wiz_locked; + wire clk_adc, clk_adc_180; + wire clk_dac, clk_dac_180; + wire locked; - clk_wiz_ctrl_inst clk_wiz_ctrl_inst ( - .clk_in1 (sys_clk), - .reset (~rst_n), - .clk_out1 (dac_clk), // 130 MHz - .clk_out2 (adc_clk), // 65 MHz - .locked (clk_wiz_locked) + clk_wiz_ctrl_inst clk_wiz_inst + ( + // Clock out ports + .clk_adc_65(clk_adc), + .clk_adc_65_180(clk_adc_180), + .clk_dac_125(clk_dac), + .clk_dac_125_180(clk_dac_180), + // Status and control signals + .resetn(rst_n), + .locked(locked), + // Clock in ports + .clk_sys(clk_sys) ); // ------------------------------------------------------------------------- @@ -87,24 +83,23 @@ module reflectometer_top #( // Controller reset // Use both external reset and clk_wiz lock // ------------------------------------------------------------------------- - wire ctrl_rst_n = rst_n & clk_wiz_locked; + wire rst_n_ctrl = rst_n & locked; - - (* MARK_DEBUG="true" *) logic finish; + logic finish; // Controller outputs to debug - (* MARK_DEBUG="true" *) wire [31:0] dac_pulse_width; - (* MARK_DEBUG="true" *) wire [31:0] dac_pulse_period; - (* MARK_DEBUG="true" *) wire [DAC_DATA_WIDTH-1:0] dac_pulse_height; - (* MARK_DEBUG="true" *) wire [15:0] dac_pulse_num; + wire [31:0] dac_pulse_width; + wire [31:0] dac_pulse_period; + wire [DAC_DATA_WIDTH-1:0] dac_pulse_height; + wire [15:0] dac_pulse_num; - (* MARK_DEBUG="true" *) wire [31:0] adc_pulse_period; - (* MARK_DEBUG="true" *) wire [15:0] adc_pulse_num; + wire [31:0] adc_pulse_period; + wire [15:0] adc_pulse_num; - (* MARK_DEBUG="true" *) wire dac_start; - (* MARK_DEBUG="true" *) wire adc_start; - (* MARK_DEBUG="true" *) wire dac_rst; - (* MARK_DEBUG="true" *) wire adc_rst; + wire dac_start; + wire adc_start; + wire dac_rst; + wire adc_rst; // ------------------------------------------------------------------------- @@ -145,15 +140,15 @@ module reflectometer_top #( // DAC // ------------------------------------------------------------------------- - (* MARK_DEBUG="true" *) logic sample_req; - (* MARK_DEBUG="true" *) logic sample_req_sync1; - (* MARK_DEBUG="true" *) logic sample_req_sync2; - (* MARK_DEBUG="true" *) logic sample_req_sync3; + logic sample_req; + logic sample_req_sync1; + logic sample_req_sync2; + logic sample_req_sync3; - (* MARK_DEBUG="true" *) logic sample_done; - (* MARK_DEBUG="true" *) logic sample_done_sync1; - (* MARK_DEBUG="true" *) logic sample_done_sync2; - (* MARK_DEBUG="true" *) logic sample_done_sync3; + logic sample_done; + logic sample_done_sync1; + logic sample_done_sync2; + logic sample_done_sync3; //------------------------------------------------------------ // DAC -> ADC CDC @@ -254,8 +249,8 @@ module reflectometer_top #( // ADC // ------------------------------------------------------------------------- - (* MARK_DEBUG="true" *) logic [ADC_DATA_WIDTH*PACK_FACTOR-1:0] accum_m_axis_tdata; - (* MARK_DEBUG="true" *) logic acum_m_axis_tvalid; + logic [ADC_DATA_WIDTH*PACK_FACTOR-1:0] accum_m_axis_tdata; + logic acum_m_axis_tvalid; sampler #( From 725826b07cb15872d25dd8e2c441e1bbec3d80b3 Mon Sep 17 00:00:00 2001 From: "babintsev.lv" Date: Fri, 3 Jul 2026 16:32:48 +0300 Subject: [PATCH 9/9] add: new reflectometer top design (not ready) --- designs/reflectometer_base/reflectometer.sv | 233 ++++++++------------ 1 file changed, 89 insertions(+), 144 deletions(-) diff --git a/designs/reflectometer_base/reflectometer.sv b/designs/reflectometer_base/reflectometer.sv index fc59256..aade3ce 100644 --- a/designs/reflectometer_base/reflectometer.sv +++ b/designs/reflectometer_base/reflectometer.sv @@ -1,8 +1,8 @@ `timescale 1 ns / 1 ns module reflectometer_top #( - parameter DAC_DATA_WIDTH = 14, - parameter ADC_DATA_WIDTH = 12, + parameter int unsigned DAC_DATA_WIDTH = 14, + parameter int unsigned ADC_DATA_WIDTH = 12, parameter PACK_FACTOR = 1, parameter PROCESS_MODE = 0, parameter ZERO_LEVEL = 8192, @@ -11,79 +11,84 @@ module reflectometer_top #( parameter WINDOW_SIZE = 65, parameter PACKET_SIZE = 1024 )( - input clk_sys, - input rst_n, - - // Output AXI-Stream for Accumulator - input clk_m_axis, - output wire [7:0] m_axis_tx_tdata, - output wire m_axis_tx_tvalid, - input wire m_axis_tx_tready, - output wire m_axis_tx_tlast, + input clk_in, + input rst_n, + output [3:0] status_led, - // Input AXI-Stream for Controller - input clk_s_axis, - input wire [7:0] s_axis_rx_tdata, - input wire s_axis_rx_tvalid, - input wire s_axis_rx_tlast, - output wire s_axis_rx_tready, + // Accumulator AXI-S bus + input wire clk_m_axis, // GMII PHY RX clock + output logic [7:0] m_axis_tdata, + output logic m_axis_tvalid, + input wire m_axis_tready, + output logic m_axis_tlast, - // Reflectometer status - output wire [3:0] status_leds, // System current status indicators - input wire req_ready, // MAC handshake ready - output wire send_req, // MAC handshake send + // Control AXI-S bus + input wire clk_s_axis, // GMII PHY TX clock + input wire [7:0] s_axis__tdata, + input wire s_axis_tvalid, + input wire s_axis_tlast, + output logic s_axis_tready, - // Generator (DAC) - output wire dac_clock, - output wire [DAC_DATA_WIDTH-1:0] dac_out, - output wire dac_wrt, + // RTL-MAC handshake + input wire request_ready, + output logic send_request, + + // DAC + output logic clk_dac, + output logic [DAC_DATA_WIDTH-1:0] dac_data, + output logic dac_wrt, + + // ADC + output logic clk_adc, + input wire [ADC_DATA_WIDTH-1:0] adc_data, + input wire adc_otr - // Sampler (ADC) - output wire adc_clock, - input wire [ADC_DATA_WIDTH-1:0] adc_data, - input wire adc_otr ); + + // // ------------------------------------------------------------------------- + // // IDELAYCTRL + // // ------------------------------------------------------------------------- + // (* IODELAY_GROUP = "rgmii_idelay_group" *) + // IDELAYCTRL IDELAYCTRL_inst ( + // .RDY (), + // .REFCLK (sys_clk), + // .RST (1'b0) + // ); TODO remove + // ------------------------------------------------------------------------- // Generated clocks for controller // Need to create this IP in Vivado: - // input : 200 MHz - // ADC: - // output0: 65 Mhz 0* phase for logic - // output1: 65 MHz 180* phase for output clocking - // DAC: - // output2: 125 Mhz 0* phase for logic - // output3: 125 MHz 180* phase for output clocking + // input resetn + // input clk_200 : 200 MHz : Reference clock + // output clk_adc_65 : 65 MHz : ADC RTL clock + // output clk_adc_65_180 : 65 MHz, phase 180 deg. : ADC PHY clock + // output clk_adc_125 : 125 MHz : DAC RTL clock + // output clk_adc_125_180 : 125 MHz, phase 180 deg. : DAC PHY clock + // output locked // ------------------------------------------------------------------------- - wire clk_adc, clk_adc_180; - wire clk_dac, clk_dac_180; - wire locked; + wire clk_sampler, clk_adc; + wire clk_generator, clk_dac; + wire clk_locked; - clk_wiz_ctrl_inst clk_wiz_inst - ( + clk_wiz_ctrl_inst_clk_wiz inst + ( + // Clock in ports + .clk_200(clk_in) // Clock out ports .clk_adc_65(clk_adc), - .clk_adc_65_180(clk_adc_180), + .clk_adc_65_180(clk_sampler), .clk_dac_125(clk_dac), - .clk_dac_125_180(clk_dac_180), + .clk_dac_125_180(clk_generator), // Status and control signals .resetn(rst_n), - .locked(locked), - // Clock in ports - .clk_sys(clk_sys) + .locked(clk_locked), ); - // ------------------------------------------------------------------------- - // axis_mac interface - // RX stream from Ethernet goes into controller - // TX stream is unused for now - // ------------------------------------------------------------------------- - - // ------------------------------------------------------------------------- // Controller reset // Use both external reset and clk_wiz lock // ------------------------------------------------------------------------- - wire rst_n_ctrl = rst_n & locked; + wire ctrl_rst_n = rst_n & clk_wiz_locked; logic finish; @@ -103,8 +108,7 @@ module reflectometer_top #( // ------------------------------------------------------------------------- - // Controller - // ETH domain = gmii_rx_clk, because RX AXI master comes from axis_mac RX side + // Controller TODO // ------------------------------------------------------------------------- control #( .DAC_DATA_WIDTH(DAC_DATA_WIDTH) @@ -136,23 +140,18 @@ module reflectometer_top #( .adc_rst (adc_rst) ); - // ------------------------------------------------------------------------- - // DAC - // ------------------------------------------------------------------------- - - logic sample_req; - logic sample_req_sync1; - logic sample_req_sync2; - logic sample_req_sync3; - - logic sample_done; - logic sample_done_sync1; - logic sample_done_sync2; - logic sample_done_sync3; - - //------------------------------------------------------------ - // DAC -> ADC CDC //------------------------------------------------------------ + // DAC -> ADC CDC TODO + //------------------------------------------------------------ + logic sample_req; + logic sample_req_sync1; + logic sample_req_sync2; + logic sample_req_sync3; + + logic sample_done; + logic sample_done_sync1; + logic sample_done_sync2; + logic sample_done_sync3; always_ff @(posedge adc_clk or posedge adc_rst) begin if (adc_rst) begin sample_req <= 1'b0; @@ -166,8 +165,8 @@ module reflectometer_top #( end end - //------------------------------------------------------------ - // ADC -> DAC CDC + //------------------------------------------------------------ + // ADC -> DAC CDC TODO //------------------------------------------------------------ always_ff @(posedge dac_clk or posedge dac_rst) begin if (dac_rst) begin @@ -182,10 +181,9 @@ module reflectometer_top #( end end - //------------------------------------------------------------ - // Generator //------------------------------------------------------------ - + // Generator (DAC) TODO + //------------------------------------------------------------ generator #( .DATA_WIDTH(DAC_DATA_WIDTH), .ZERO_LEVEL(ZERO_LEVEL) @@ -203,64 +201,15 @@ module reflectometer_top #( .sample_req(sample_req_sync1) ); - wire ch2_clk_oddr; - - ODDR #( - .DDR_CLK_EDGE("SAME_EDGE"), - .INIT(1'b0), - .SRTYPE("SYNC") - ) ODDR_ch2_clk ( - .Q (ch2_clk_oddr), - .C (adc_clk), - .CE(1'b1), - .D1(1'b1), - .D2(1'b0), - .R (1'b0), - .S (1'b0) - ); - - OBUF OBUF_ch2_clk ( - .I(ch2_clk_oddr), - .O(ch2_clk) - ); - - wire p2_clk_oddr; - - ODDR #( - .DDR_CLK_EDGE("SAME_EDGE"), - .INIT(1'b0), - .SRTYPE("SYNC") - ) ODDR_p2_clk ( - .Q (p2_clk_oddr), - .C (dac_clk), - .CE(1'b1), - .D1(1'b1), - .D2(1'b0), - .R (1'b0), - .S (1'b0) - ); - - OBUF OBUF_p2_clk ( - .I(p2_clk_oddr), - .O(p2_clk) - ); - -// ------------------------------------------------------------------------- - // ADC // ------------------------------------------------------------------------- - - logic [ADC_DATA_WIDTH*PACK_FACTOR-1:0] accum_m_axis_tdata; - logic acum_m_axis_tvalid; - - sampler - #( + // Sampler (ADC) TODO + // ------------------------------------------------------------------------- + sampler #( .DATA_WIDTH(ADC_DATA_WIDTH), .PACK_FACTOR(PACK_FACTOR), .PROCESS_MODE(PROCESS_MODE) - ) - sampler_dut - ( - .clk_in(adc_clk), + ) sampler_dut ( + .clk_in(clk_sampler), .rst(adc_rst), .data_in(ch2_data), .out_of_range(ch2_otr), @@ -272,20 +221,16 @@ module reflectometer_top #( ); // ------------------------------------------------------------------------- - // Accumulator + // Accumulator TODO // ------------------------------------------------------------------------- - - accumulator_top - #( + accumulator_top #( .DATA_WIDTH(ADC_DATA_WIDTH), .ACCUM_WIDTH(ACCUM_WIDTH), .N_MAX(N_MAX), .WINDOW_SIZE(WINDOW_SIZE), .PACKET_SIZE(PACKET_SIZE) - ) - accumulator_top_dut - ( - .clk_in(adc_clk), + ) accumulator_top_dut ( + .clk_in(clk_sampler), .rst(adc_rst), .s_axis_tdata(accum_m_axis_tdata), .s_axis_tvalid(acum_m_axis_tvalid), @@ -304,12 +249,12 @@ module reflectometer_top #( .finish(finish) ); - // ------------------------------------------------------------------------- - // Simple LED status + // LED status TODO // ------------------------------------------------------------------------- - assign led[0] = clk_wiz_locked; - assign led[1] = m_axis_rx_tvalid; - assign led[2] = dac_start; + assign led[0] = clk_locked; + assign led[1] = rst_n; + // assign led[2] = ; + // assign led[3] = ; endmodule \ No newline at end of file