diff --git a/designs/full_new_reflectometer_without_clk_wiz/src/reflectometer_and_dma_wrapper.sv b/designs/full_new_reflectometer_without_clk_wiz/src/reflectometer_and_dma_wrapper.sv
index 6fbbeb6..27ab1b0 100644
--- a/designs/full_new_reflectometer_without_clk_wiz/src/reflectometer_and_dma_wrapper.sv
+++ b/designs/full_new_reflectometer_without_clk_wiz/src/reflectometer_and_dma_wrapper.sv
@@ -50,6 +50,7 @@ module reflectometer_and_dma_wrapper
 
         // DAC
     output  wire [DAC_DATA_WIDTH-1:0]   dac_data,
+    output  wire                        dac_wrt,
 
     // ADC
     input   wire [ADC_DATA_WIDTH-1:0]   adc_data,
@@ -136,6 +137,7 @@ module reflectometer_and_dma_wrapper
         .m_axis_desc_write(m_axis_desc_write),
 
         .dac_data(dac_data),
+        .dac_wrt(dac_wrt),
         .adc_data(adc_data),
         .adc_otr(adc_otr)
     );
diff --git a/designs/full_new_reflectometer_without_clk_wiz/src/reflectometer_ip.sv b/designs/full_new_reflectometer_without_clk_wiz/src/reflectometer_ip.sv
index 82e83ab..4f97af7 100644
--- a/designs/full_new_reflectometer_without_clk_wiz/src/reflectometer_ip.sv
+++ b/designs/full_new_reflectometer_without_clk_wiz/src/reflectometer_ip.sv
@@ -35,13 +35,19 @@ module reflectometer_ip #(
 
     // ADC
     input   wire [ADC_DATA_WIDTH-1:0]   adc_data,
-    input   wire                        adc_otr
+    input   wire                        adc_otr,
+    output  wire                        dac_wrt
 
 
 );
 
     wire workflow_done, processing_done;
 
+     OBUF OBUF_pulse_clk (
+        .I(clk_generator),
+        .O(dac_wrt)
+    );
+
     // -------------------------------------------------------------------------
     // Controller
     // -------------------------------------------------------------------------
diff --git a/designs/full_new_reflectometer_without_clk_wiz/src/reflectometer_top.sv b/designs/full_new_reflectometer_without_clk_wiz/src/reflectometer_top.sv
index a1d4062..a7bcf76 100644
--- a/designs/full_new_reflectometer_without_clk_wiz/src/reflectometer_top.sv
+++ b/designs/full_new_reflectometer_without_clk_wiz/src/reflectometer_top.sv
@@ -91,8 +91,6 @@ module reflectometer_top
     // -------------------------------------------------------------------------
     wire ctrl_rst_n = rst_n & clk_locked;
 
-    assign dac_wrt = dac_clk_o;
-
 
 
     reflectometer_and_dma_wrapper 
@@ -132,6 +130,7 @@ module reflectometer_top
         .m_axis_read_data(m_axis_read_data),
 
         .dac_data(dac_data),
+        .dac_wrt(dac_wrt),
         .adc_data(adc_data),
         .adc_otr(adc_otr)
     );