diff --git a/rtl/controller/src/axi4l_reg_map_controller.sv b/rtl/controller/src/axi4l_reg_map_controller.sv
new file mode 100644
index 0000000..26b87f2
--- /dev/null
+++ b/rtl/controller/src/axi4l_reg_map_controller.sv
@@ -0,0 +1,66 @@
+module axi4l_reg_map_controller #(
+  parameter int unsigned ADDR_W = 16,
+  parameter int unsigned DATA_W = 32,
+  parameter int unsigned USER_W = 1
+)(
+  input  logic clk,
+  input  logic rst_n,
+  axi4l_if.slave s_axil,
+
+  output logic        start_o,
+  output logic [31:0] pulse_width_o,
+  output logic [31:0] pulse_period_o,
+  output logic [31:0] pulse_num_o,
+  output logic [31:0] pulse_height_raw_o,
+  output logic [31:0] pulse_period_ADC_o,
+  
+  output logic        rst_soft_o,
+  input  logic        busy_i,
+  input  logic [7:0]  error_code_i
+);
+  import axi4l_reg_map_example_pkg::*;
+  localparam int unsigned N_REGS = AXI4L_REG_MAP_EXAMPLE_N_REGS;
+
+  logic [N_REGS-1:0][31:0] reg_i;
+  logic [N_REGS-1:0][31:0] reg_o;
+  logic [N_REGS-1:0][31:0] reg_pulse;
+
+  axi4l_reg_map #(
+    .ADDR_W  (ADDR_W),
+    .DATA_W  (DATA_W),
+    .USER_W  (USER_W),
+    .N_REGS  (N_REGS),
+    .REG_MODE (AXI4L_REG_MAP_EXAMPLE_REG_MODE),
+    .REG_RST (AXI4L_REG_MAP_EXAMPLE_REG_RST)
+  ) u_reg_map (
+    .clk      (clk),
+    .rst_n    (rst_n),
+    .s_axil   (s_axil),
+    .reg_i    (reg_i),
+    .reg_o    (reg_o),
+    .reg_pulse(reg_pulse)
+  );
+
+  always_comb begin
+    reg_i = '0;
+
+    // REG1 @ 0x04: status register
+    // bit 0   : busy (RO)
+    reg_i[REG_STATUS][0] = busy_i;
+
+    // REG2 @ 0x08: error register
+    // bits 7:0: error_code (RO)
+    reg_i[REG_ERROR][7:0] = error_code_i;
+
+  end
+
+  assign start_o            = reg_pulse[REG_CONTROL][0];
+  assign rst_soft_o         = reg_pulse[REG_CONTROL][1];
+  assign pulse_width_o      = reg_o[REG_DAC_WIDTH];
+  assign pulse_period_o     = reg_o[REG_DAC_PERIOD];
+  assign pulse_num_o        = reg_o[REG_DAC_PULSE_NUM];
+  assign pulse_height_raw_o = reg_o[REG_DAC_PULSE_HEIGHT]; 
+  assign pulse_period_ADC_o = reg_o[REG_ADC_PERIOD]; 
+
+
+endmodule
diff --git a/rtl/controller/src/axi4l_reg_map_controller_pkg.sv b/rtl/controller/src/axi4l_reg_map_controller_pkg.sv
new file mode 100644
index 0000000..b8e54df
--- /dev/null
+++ b/rtl/controller/src/axi4l_reg_map_controller_pkg.sv
@@ -0,0 +1,67 @@
+package axi4l_reg_map_controller_pkg;
+
+  localparam int unsigned AXI4L_REG_MAP_EXAMPLE_N_REGS = 8;
+
+  localparam logic [31:0] REG_CONTROL          = 32'd0;
+  localparam logic [31:0] REG_STATUS           = 32'd1;
+  localparam logic [31:0] REG_DAC_WIDTH        = 32'd2;
+  localparam logic [31:0] REG_DAC_PERIOD       = 32'd3;
+  localparam logic [31:0] REG_DAC_PULSE_NUM    = 32'd4;
+  localparam logic [31:0] REG_DAC_PULSE_HEIGHT = 32'd5;
+  localparam logic [31:0] REG_ADC_PERIOD       = 32'd6;
+  localparam logic [31:0] REG_ERROR            = 32'd7;
+
+  localparam logic [2:0] REG_BIT_RSVD = 3'd0;
+  localparam logic [2:0] REG_BIT_RO   = 3'd1;
+  localparam logic [2:0] REG_BIT_RW   = 3'd2;
+  localparam logic [2:0] REG_BIT_W1S  = 3'd3;
+
+  localparam logic [AXI4L_REG_MAP_EXAMPLE_N_REGS-1:0][31:0][2:0] AXI4L_REG_MAP_EXAMPLE_REG_MODE = '{
+    // REG_CONTROL
+    '{
+      REG_BIT_W1S,
+      REG_BIT_W1S,
+      default: REG_BIT_RSVD
+    },
+
+    // REG_STATUS
+    '{
+      REG_BIT_RO,
+      default: REG_BIT_RSVD
+    },
+
+    // REG_DAC_WIDTH
+     '{default: REG_BIT_RW},
+
+    // REG_DAC_PERIOD
+     '{default: REG_BIT_RW},
+
+    // REG_DAC_PULSE_NUM
+     '{default: REG_BIT_RW},
+
+    // REG_DAC_PULSE_HEIGHT
+     '{default: REG_BIT_RW},
+
+    // REG_ADC_PERIOD
+     '{default: REG_BIT_RW},
+
+    // REG_ERROR
+    '{
+      REG_BIT_RO, REG_BIT_RO, REG_BIT_RO, REG_BIT_RO,
+      REG_BIT_RO, REG_BIT_RO, REG_BIT_RO, REG_BIT_RO,
+      default: REG_BIT_RSVD
+    }
+  };
+
+  localparam logic [AXI4L_REG_MAP_EXAMPLE_N_REGS-1:0][31:0] AXI4L_REG_MAP_EXAMPLE_REG_RST = '{
+    32'h0000_0000,
+    32'h0000_0000,
+    32'h0000_0000,
+    32'h0000_0000,
+    32'h0000_0000,
+    32'h0000_0000,
+    32'h0000_0000,
+    32'h0000_0000
+  };
+
+endpackage