From 179347659be403a635ee235db33dd211e841ec85 Mon Sep 17 00:00:00 2001 From: Phil Date: Thu, 30 Apr 2026 13:10:41 +0300 Subject: [PATCH] rtl: update reflectometer top design --- designs/reflectometer/reflectometer.sv | 86 ++++++++++---------------- 1 file changed, 33 insertions(+), 53 deletions(-) diff --git a/designs/reflectometer/reflectometer.sv b/designs/reflectometer/reflectometer.sv index 2b7b7d3..b36f39c 100644 --- a/designs/reflectometer/reflectometer.sv +++ b/designs/reflectometer/reflectometer.sv @@ -29,18 +29,18 @@ module reflectometer_top #( // DAC - (* MARK_DEBUG="true" *) output debug_dac + (* MARK_DEBUG="true" *) output debug_dac, // ADC - - input [ADC_DATA_WIDTH-1:0] adc_data_in; - input adc_out_of_range; + output ch2_clk, + (* MARK_DEBUG="true" *) input [ADC_DATA_WIDTH-1:0] ch2_data, + input ch2_otr ); // temp - wire p2_clk; + wire p2_wrt; - (* MARK_DEBUG="true" *) wire [13:0] p2_data; + wire [13:0] p2_data; assign debug_dac = p2_data[13]; // ------------------------------------------------------------------------- // Internal GMII-side signals @@ -158,32 +158,19 @@ module reflectometer_top #( // RX stream from Ethernet goes into controller // TX stream is unused for now // ------------------------------------------------------------------------- - wire req_ready; + (* MARK_DEBUG="true" *) logic req_ready; + (* MARK_DEBUG="true" *) logic send_req; - reg send_req; - reg [15:0] data_length; - - reg [7:0] s_axis_tx_tdata; - reg s_axis_tx_tvalid; - wire s_axis_tx_tready; - reg s_axis_tx_tlast; + (* MARK_DEBUG="true" *) logic [7:0] s_axis_tx_tdata; + (* MARK_DEBUG="true" *) logic s_axis_tx_tvalid; + (* MARK_DEBUG="true" *) logic s_axis_tx_tready; + (* MARK_DEBUG="true" *) logic s_axis_tx_tlast; (* MARK_DEBUG="true" *) wire [7:0] m_axis_rx_tdata; (* MARK_DEBUG="true" *) wire m_axis_rx_tvalid; (* MARK_DEBUG="true" *) wire m_axis_rx_tlast; (* MARK_DEBUG="true" *) wire m_axis_rx_tready; - // Always ready to accept RX payload bytes - assign m_axis_rx_tready = 1'b1; - - // TX disabled - always @(*) begin - send_req = 1'b0; - data_length = 16'd0; - s_axis_tx_tdata = 8'd0; - s_axis_tx_tvalid= 1'b0; - s_axis_tx_tlast = 1'b0; - end axis_mac axis_mac0 ( .gmii_tx_clk (gmii_tx_clk), @@ -196,7 +183,7 @@ module reflectometer_top #( .gmii_txd (gmii_txd), .send_req (send_req), - .data_length (data_length), + .data_length (PACKET_SIZE), .req_ready (req_ready), .s_axis_tx_tdata (s_axis_tx_tdata), @@ -227,14 +214,7 @@ module reflectometer_top #( // ------------------------------------------------------------------------- wire ctrl_rst_n = rst_n & clk_wiz_locked; - // ------------------------------------------------------------------------- - // Debug finish generator (still used here, since generator doesn't have finish signal) - // - // After each adc_start pulse generates one finish pulse after some delay. - // This is just for first bring-up so the controller can leave busy state - // If you don't want this, replace with: - // wire finish_dbg = 1'b0; - // ------------------------------------------------------------------------- + (* MARK_DEBUG="true" *) logic finish; // Controller outputs to debug @@ -266,7 +246,7 @@ module reflectometer_top #( .s_axis_tdata (m_axis_rx_tdata), .s_axis_tvalid (m_axis_rx_tvalid), - .s_axis_tready (), // controller internally always ready in current version + .s_axis_tready (m_axis_rx_tready), .s_axis_tlast (m_axis_rx_tlast), .finish (finish), @@ -299,20 +279,20 @@ module reflectometer_top #( .pulse_period(dac_pulse_period), .pulse_height(dac_pulse_height), .pulse_num(dac_pulse_num), - .pulse(p2_wrt ), + .pulse(p2_wrt), .pulse_height_out(p2_data) ); - // dac clk mgt - wire p2_clk_oddr; + // adc clk mgt + wire ch2_clk_oddr; ODDR #( .DDR_CLK_EDGE("SAME_EDGE"), .INIT(1'b0), .SRTYPE("SYNC") - ) ODDR_p2_clk ( - .Q (p2_clk_oddr), - .C (dac_clk), + ) ODDR_ch2_clk ( + .Q (ch2_clk_oddr), + .C (adc_clk), .CE(1'b1), .D1(1'b1), .D2(1'b0), @@ -320,17 +300,17 @@ module reflectometer_top #( .S (1'b0) ); - OBUF OBUF_p2_clk ( - .I(p2_clk_oddr), - .O(p2_clk) + OBUF OBUF_ch2_clk ( + .I(ch2_clk_oddr), + .O(ch2_clk) ); // ------------------------------------------------------------------------- // ADC // ------------------------------------------------------------------------- - logic [DATA_WIDTH*PACK_FACTOR-1:0] accum_m_axis_tdata; - logic acum_m_axis_tvalid; + (* MARK_DEBUG="true" *) logic [ADC_DATA_WIDTH*PACK_FACTOR-1:0] accum_m_axis_tdata; + (* MARK_DEBUG="true" *) logic acum_m_axis_tvalid; sampler #( @@ -342,8 +322,8 @@ module reflectometer_top #( ( .clk_in(adc_clk), .rst(adc_rst), - .data_in(adc_data_in), - .out_of_range(adc_out_of_range), + .data_in(ch2_data), + .out_of_range(ch2_otr), .m_axis_tdata(accum_m_axis_tdata), .m_axis_tvalid(acum_m_axis_tvalid) ); @@ -370,13 +350,13 @@ module reflectometer_top #( .smp_num(adc_pulse_period), .seq_num(adc_pulse_num), - .eth_clk_in(gmii_rx_clk), + .eth_clk_in(gmii_tx_clk), .req_ready(req_ready), .send_req(send_req), - .m_axis_tdata(m_axis_rx_tdata), - .m_axis_tvalid(m_axis_rx_tvalid), - .m_axis_tready(m_axis_rx_tready), - .m_axis_tlast(m_axis_rx_tlast), + .m_axis_tdata(s_axis_tx_tdata), + .m_axis_tvalid(s_axis_tx_tvalid), + .m_axis_tready(s_axis_tx_tready), + .m_axis_tlast(s_axis_tx_tlast), .finish(finish) );