infra: add libs

2026-05-28 16:59:57 +03:00
parent 0486e16484
commit 17748a71b1
3 changed files with 8 additions and 0 deletions
@@ -0,0 +1,6 @@
 [submodule "libs/rtl_libs"]
 	path = libs/rtl_libs
 	url = https://git.radiophotonics.ru/baulin.fa/rtl_libs.git
 [submodule "libs/verilog-axi"]
 	path = libs/verilog-axi
 	url = https://github.com/alexforencich/verilog-axi.git