infra: add libs

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Phil

2026-05-28 16:59:57 +03:00

parent 0486e16484

commit 17748a71b1

3 changed files with 8 additions and 0 deletions

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libs/rtl_libs

Submodule

+1

Submodule libs/rtl_libs added at 338f30c0d7

libs/verilog-axi

Submodule

+1

Submodule libs/verilog-axi added at 516bd5dadc