baulin.fa/reflectometer_fpga_project
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rtl: add sample reflectometer project mock

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Phil
2026-04-28 17:05:14 +03:00
parent d68c22211d
commit 16cef61a88
5 changed files with 1102 additions and 0 deletions
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designs/reflectometer/debug.xdc Normal file
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set_clock_groups -name ASYNC_UDP_CTRL -asynchronous -group [get_clocks rgmii_rxc] -group [get_clocks clk_out1_clk_wiz_ctrl_inst] -group [get_clocks clk_out2_clk_wiz_ctrl_inst]