diff --git a/rtl/accum/tests/tb_accumulator_top_behav.wcfg b/rtl/accum/tests/tb_accumulator_top_behav.wcfg
index 931e9f1..007c100 100644
--- a/rtl/accum/tests/tb_accumulator_top_behav.wcfg
+++ b/rtl/accum/tests/tb_accumulator_top_behav.wcfg
@@ -11,13 +11,13 @@
-
-
-
+
+
+
-
+
@@ -116,6 +116,10 @@
addrb[15:0]
addrb[15:0]
+
+ wr_state[3:0]
+ wr_state[3:0]
+
fifo
@@ -166,13 +170,13 @@
PROG_FULL_THRESH[31:0]
- wr_data_count[4:0]
- wr_data_count[4:0]
+ wr_data_count[9:0]
+ wr_data_count[9:0]
UNSIGNEDDECRADIX
- rd_data_count[6:0]
- rd_data_count[6:0]
+ rd_data_count[11:0]
+ rd_data_count[11:0]
UNSIGNEDDECRADIX
diff --git a/rtl/controller/tests/tb_control_behav.wcfg b/rtl/controller/tests/tb_control_behav.wcfg
new file mode 100644
index 0000000..6d6625c
--- /dev/null
+++ b/rtl/controller/tests/tb_control_behav.wcfg
@@ -0,0 +1,197 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ eth_clk_in
+ eth_clk_in
+ #008080
+ true
+
+
+ dac_clk_in
+ dac_clk_in
+ #FFA500
+ true
+
+
+ adc_clk_in
+ adc_clk_in
+
+
+ rst_n
+ rst_n
+ #800080
+ true
+
+
+ s_axis_tdata[7:0]
+ s_axis_tdata[7:0]
+ #008080
+ true
+ BINARYRADIX
+
+
+ s_axis_tvalid
+ s_axis_tvalid
+ #008080
+ true
+
+
+ s_axis_tready
+ s_axis_tready
+ #008080
+ true
+
+
+ s_axis_tlast
+ s_axis_tlast
+ #008080
+ true
+
+
+ finish
+ finish
+ #FAAFBE
+ true
+
+
+ dac_pulse_width[31:0]
+ dac_pulse_width[31:0]
+ #FFA500
+ true
+
+
+ dac_pulse_period[31:0]
+ dac_pulse_period[31:0]
+ #FFA500
+ true
+
+
+ dac_pulse_height[11:0]
+ dac_pulse_height[11:0]
+ #FFA500
+ true
+ HEXRADIX
+
+
+ dac_pulse_num[15:0]
+ dac_pulse_num[15:0]
+ #FFA500
+ true
+
+
+ adc_pulse_period[31:0]
+ adc_pulse_period[31:0]
+ #FFA500
+ true
+
+
+ adc_pulse_num[15:0]
+ adc_pulse_num[15:0]
+ #FFA500
+ true
+
+
+ dac_start
+ dac_start
+ #FFA500
+ true
+
+
+ adc_start
+ adc_start
+
+
+ dac_rst
+ dac_rst
+ #FFA500
+ true
+
+
+ adc_rst
+ adc_rst
+
+
+ tb signals
+ label
+
+ dac_rst_count[31:0]
+ dac_rst_count[31:0]
+ #F0E68C
+ true
+
+
+ adc_rst_count[31:0]
+ adc_rst_count[31:0]
+ #F0E68C
+ true
+
+
+ dac_start_count[31:0]
+ dac_start_count[31:0]
+ #F0E68C
+ true
+
+
+ adc_start_count[31:0]
+ adc_start_count[31:0]
+ #F0E68C
+ true
+
+
+ test_pulse_width[31:0]
+ test_pulse_width[31:0]
+ #F0E68C
+ true
+
+
+ test_pulse_period[31:0]
+ test_pulse_period[31:0]
+ #F0E68C
+ true
+
+
+ test_pulse_num[15:0]
+ test_pulse_num[15:0]
+ #F0E68C
+ true
+
+
+ test_pulse_height_raw[15:0]
+ test_pulse_height_raw[15:0]
+ #F0E68C
+ true
+
+
+
+ DAC_DATA_WIDTH[31:0]
+ DAC_DATA_WIDTH[31:0]
+
+
+ cfg_ack_toggle_adc
+ cfg_ack_toggle_adc
+
+
+ cfg_ack_toggle_dac
+ cfg_ack_toggle_dac
+
+