From 14f4a5eb2aff043cb90fe2f45c013286cfa5778b Mon Sep 17 00:00:00 2001 From: otroubi Date: Tue, 30 Jun 2026 17:13:00 +0300 Subject: [PATCH] rtl: register map addition for DMA control --- .../src/axi4l_reg_map_controller.sv | 50 ++++++++---- .../src/axi4l_reg_map_controller_pkg.sv | 81 ++++++++++++++++--- 2 files changed, 105 insertions(+), 26 deletions(-) diff --git a/rtl/controller/src/axi4l_reg_map_controller.sv b/rtl/controller/src/axi4l_reg_map_controller.sv index 26b87f2..5bae2df 100644 --- a/rtl/controller/src/axi4l_reg_map_controller.sv +++ b/rtl/controller/src/axi4l_reg_map_controller.sv @@ -6,16 +6,31 @@ module axi4l_reg_map_controller #( input logic clk, input logic rst_n, axi4l_if.slave s_axil, - +// dac adc registers output logic start_o, output logic [31:0] pulse_width_o, output logic [31:0] pulse_period_o, output logic [31:0] pulse_num_o, output logic [31:0] pulse_height_raw_o, + output logic [31:0] pulse_num_ADC_o, output logic [31:0] pulse_period_ADC_o, + + // DMA read descriptors and status register + output logic [31:0] desc_read_addr_o, + output logic [31:0] desc_read_len_o, + output logic [31:0] desc_read_config_o, + + input logic [31:0] status_read_i, + + // DMA write descriptors and status register + output logic [31:0] desc_write_addr_o, + output logic [31:0] desc_write_len_and_tag_o, + + input logic [31:0] status_write_len_i, + input logic [31:0] status_write_config_i, output logic rst_soft_o, - input logic busy_i, + input logic [7:0] busy_i, input logic [7:0] error_code_i ); import axi4l_reg_map_example_pkg::*; @@ -44,23 +59,28 @@ module axi4l_reg_map_controller #( always_comb begin reg_i = '0; - // REG1 @ 0x04: status register - // bit 0 : busy (RO) - reg_i[REG_STATUS][0] = busy_i; - - // REG2 @ 0x08: error register - // bits 7:0: error_code (RO) + reg_i[REG_STATUS][7:0] = busy_i; reg_i[REG_ERROR][7:0] = error_code_i; + reg_i[REG_READ_STATUS] = status_read_i; + reg_i[REG_STATUS_WRITE_LEN] = status_write_len_i; + reg_i[REG_STATUS_WRITE_CONFIG] = status_write_config_i; + end - assign start_o = reg_pulse[REG_CONTROL][0]; - assign rst_soft_o = reg_pulse[REG_CONTROL][1]; - assign pulse_width_o = reg_o[REG_DAC_WIDTH]; - assign pulse_period_o = reg_o[REG_DAC_PERIOD]; - assign pulse_num_o = reg_o[REG_DAC_PULSE_NUM]; - assign pulse_height_raw_o = reg_o[REG_DAC_PULSE_HEIGHT]; - assign pulse_period_ADC_o = reg_o[REG_ADC_PERIOD]; + assign start_o = reg_pulse[REG_CONTROL][0]; + assign rst_soft_o = reg_pulse[REG_CONTROL][1]; + assign pulse_width_o = reg_o[REG_DAC_WIDTH]; + assign pulse_period_o = reg_o[REG_DAC_PERIOD]; + assign pulse_num_o = reg_o[REG_DAC_PULSE_NUM]; + assign pulse_height_raw_o = reg_o[REG_DAC_PULSE_HEIGHT]; + assign pulse_num_ADC_o = reg_o[REG_ADC_NUM]; + assign pulse_period_ADC_o = reg_o[REG_ADC_PERIOD]; + assign desc_read_addr_o = reg_o[REG_DESC_READ_ADDR]; + assign desc_read_len_o = reg_o[REG_DESC_READ_LEN]; + assign desc_read_config_o = reg_o[REG_DESC_READ_CONFIG]; + assign desc_write_addr_o = reg_o[REG_DESC_WRITE_ADDR]; + assign desc_write_len_and_tag_o = reg_o[REG_DESC_WRITE_LEN_AND_TAG]; endmodule diff --git a/rtl/controller/src/axi4l_reg_map_controller_pkg.sv b/rtl/controller/src/axi4l_reg_map_controller_pkg.sv index b8e54df..83d6950 100644 --- a/rtl/controller/src/axi4l_reg_map_controller_pkg.sv +++ b/rtl/controller/src/axi4l_reg_map_controller_pkg.sv @@ -1,15 +1,38 @@ package axi4l_reg_map_controller_pkg; - localparam int unsigned AXI4L_REG_MAP_EXAMPLE_N_REGS = 8; + localparam int unsigned AXI4L_REG_MAP_EXAMPLE_N_REGS = 17; + +/* +dac adc configuration registers +*/ + localparam logic [31:0] REG_CONTROL = 32'd0; + localparam logic [31:0] REG_STATUS = 32'd1; + localparam logic [31:0] REG_DAC_WIDTH = 32'd2; + localparam logic [31:0] REG_DAC_PERIOD = 32'd3; + localparam logic [31:0] REG_DAC_PULSE_NUM = 32'd4; + localparam logic [31:0] REG_DAC_PULSE_HEIGHT = 32'd5; + localparam logic [31:0] REG_ADC_NUM = 32'd6; + localparam logic [31:0] REG_ADC_PERIOD = 32'd7; + localparam logic [31:0] REG_ERROR = 32'd8; + +/* +AXI read descriptor input and AXI read descriptor status output configuration registers +*/ + localparam logic [31:0] REG_DESC_READ_ADDR = 32'd9; + localparam logic [31:0] REG_DESC_READ_LEN = 32'd10; + localparam logic [31:0] REG_DESC_READ_CONFIG = 32'd11; + + localparam logic [31:0] REG_READ_STATUS = 32'd12; + +/* +AXI write descriptor input and AXI write descriptor status output configuration registers +*/ + localparam logic [31:0] REG_DESC_WRITE_ADDR = 32'd13; + localparam logic [31:0] REG_DESC_WRITE_LEN_AND_TAG = 32'd14; + + localparam logic [31:0] REG_STATUS_WRITE_LEN = 32'd15; + localparam logic [31:0] REG_STATUS_WRITE_CONFIG = 32'd16; - localparam logic [31:0] REG_CONTROL = 32'd0; - localparam logic [31:0] REG_STATUS = 32'd1; - localparam logic [31:0] REG_DAC_WIDTH = 32'd2; - localparam logic [31:0] REG_DAC_PERIOD = 32'd3; - localparam logic [31:0] REG_DAC_PULSE_NUM = 32'd4; - localparam logic [31:0] REG_DAC_PULSE_HEIGHT = 32'd5; - localparam logic [31:0] REG_ADC_PERIOD = 32'd6; - localparam logic [31:0] REG_ERROR = 32'd7; localparam logic [2:0] REG_BIT_RSVD = 3'd0; localparam logic [2:0] REG_BIT_RO = 3'd1; @@ -26,7 +49,8 @@ package axi4l_reg_map_controller_pkg; // REG_STATUS '{ - REG_BIT_RO, + REG_BIT_RO, REG_BIT_RO, REG_BIT_RO, REG_BIT_RO, + REG_BIT_RO, REG_BIT_RO, REG_BIT_RO, REG_BIT_RO, default: REG_BIT_RSVD }, @@ -42,7 +66,10 @@ package axi4l_reg_map_controller_pkg; // REG_DAC_PULSE_HEIGHT '{default: REG_BIT_RW}, - // REG_ADC_PERIOD + // REG_ADC_NUM + '{default: REG_BIT_RW}, + + // REG_ADC_PERIOD '{default: REG_BIT_RW}, // REG_ERROR @@ -51,9 +78,41 @@ package axi4l_reg_map_controller_pkg; REG_BIT_RO, REG_BIT_RO, REG_BIT_RO, REG_BIT_RO, default: REG_BIT_RSVD } + + // REG_DESC_READ_ADDR + '{default: REG_BIT_RW}, + + // REG_DESC_READ_LEN + '{default: REG_BIT_RW}, + + // REG_DESC_READ_CONFIG + '{default: REG_BIT_RW}, + + // REG_READ_STATUS + '{default: REG_BIT_RO}, + + // REG_DESC_WRITE_ADDR + '{default: REG_BIT_RW}, + + // REG_DESC_WRITE_LEN_AND_TAG + '{default: REG_BIT_RW}, + + // REG_STATUS_WRITE_LEN + '{default: REG_BIT_RO}, + + // REG_STATUS_WRITE_CONFIG + '{default: REG_BIT_RO} }; localparam logic [AXI4L_REG_MAP_EXAMPLE_N_REGS-1:0][31:0] AXI4L_REG_MAP_EXAMPLE_REG_RST = '{ + 32'h0000_0000, + 32'h0000_0000, + 32'h0000_0000, + 32'h0000_0000, + 32'h0000_0000, + 32'h0000_0000, + 32'h0000_0000, + 32'h0000_0000, 32'h0000_0000, 32'h0000_0000, 32'h0000_0000,