diff --git a/rtl/controller/src/controller.sv b/rtl/controller/src/controller.sv index 569aa9e..1c540e7 100644 --- a/rtl/controller/src/controller.sv +++ b/rtl/controller/src/controller.sv @@ -1,17 +1,17 @@ module control #( - parameter int unsigned DAC_DATA_WIDTH = 12, - parameter int unsigned ADDR_W = 16 - parameter int unsigned DATA_W = 32 - parameter int unsigned USER_W = 1 + parameter int unsigned DAC_DATA_WIDTH = 12 ) ( input logic ctrl_clk, input logic dac_clk_in, input logic adc_clk_in, + input logic rst_n, - axi4l_if.slave s_axil, + input logic rst_soft, // adc_clk_in domain input logic finish, + input logic [127:0] cfg_bus, + input logic start, // dac_clk_in domain outputs output logic [31:0] dac_pulse_width, @@ -30,46 +30,6 @@ module control #( output logic adc_rst ); - logic start, rst_soft; - logic [31:0] pulse_width, pulse_period, pulse_num, pulse_height_raw, pulse_period_ADC; - logic [7:0] busy, error_code; - logic [31:0] desc_read_addr, desc_read_len, desc_read_config, status_read; - logic [31:0] desc_write_addr, desc_write_len_and_tag, status_write_len, status_write_config; - - axi4l_reg_map_controller #( - .ADDR_W(ADDR_W), - .DATA_W(DATA_W), - .USER_W(USER_W) - ) axi4l_reg_map_controller_inst ( - .clk(ctrl_clk), - .rst_n(rst_n), - .s_axil(s_axil), - - .start_o(start), - .pulse_width_o(pulse_width), - .pulse_period_o(pulse_period), - .pulse_num_o(pulse_num), - .pulse_height_raw_o(pulse_height_raw), - .pulse_period_ADC_o(pulse_period_ADC), - - .desc_read_addr_o(desc_read_addr), - .desc_read_len_o(desc_read_len), - .desc_read_config_o(desc_read_config), - - .status_read_i(status_read), - - .desc_write_addr_o(desc_write_addr), - .desc_write_len_and_tag_o(desc_write_len_and_tag), - - .status_write_len_i(status_write_len), - .status_write_config_i(status_write_config), - - .rst_soft_o(rst_soft), - .busy_i(busy), - .error_code_i(error_code) - ); - - // static checks initial begin if (DAC_DATA_WIDTH > 16) begin @@ -81,7 +41,7 @@ module control #( end // reset synchronizers: async assert, sync deassert in each domain - logic eth_rst_ff1, eth_rst_ff2; + logic rst_ff1, rst_ff2; logic dac_rst_ff1, dac_rst_ff2; logic adc_rst_ff1, adc_rst_ff2; @@ -91,11 +51,11 @@ module control #( always_ff @(posedge ctrl_clk or negedge rst_n) begin if (!rst_n) begin - eth_rst_ff1 <= 1'b1; - eth_rst_ff2 <= 1'b1; + rst_ff1 <= 1'b1; + rst_ff2 <= 1'b1; end else begin - eth_rst_ff1 <= 1'b0; - eth_rst_ff2 <= eth_rst_ff1; + rst_ff1 <= 1'b0; + rst_ff2 <= rst_ff1; end end @@ -124,28 +84,15 @@ module control #( assign adc_rst_int = adc_rst_ff2; - // ------------------------------------------------------------------------- - // Field layout inside cfg_bus_eth: - // [31:0] pulse_width - // [63:32] pulse_period - // [79:64] pulse_num - // [95:80] pulse_height_raw[15:0] - // [127:96] pulse_period_ADC - // - // ------------------------------------------------------------------------- - (* MARK_DEBUG="true" *) logic [127:0] cfg_bus_eth; - assign cfg_bus_eth = {pulse_period_ADC, pulse_height_raw[15:0], pulse_num[15:0], pulse_period, pulse_width}; + // Event toggles cntrl -> DAC/ADC + logic start_toggle; + logic rst_toggle; + // Config request toggles cntrl -> DAC/ADC + logic cfg_req_toggle_dac; + logic cfg_req_toggle_adc; - // Event toggles ETH -> DAC/ADC - logic start_toggle_eth; - logic rst_toggle_eth; - - // Config request toggles ETH -> DAC/ADC - logic cfg_req_toggle_dac_eth; - logic cfg_req_toggle_adc_eth; - - // ACK toggles DAC/ADC -> ETH + // ACK toggles DAC/ADC -> contrl logic cfg_ack_toggle_dac; logic cfg_ack_toggle_adc; @@ -177,9 +124,9 @@ module control #( // finish event: ADC -> ETH via toggle CDC logic finish_toggle_adc; - logic finish_meta_eth, finish_sync_eth, finish_sync_eth_d; + logic finish_meta, finish_sync, finish_sync_d; - wire finish_pulse_eth = finish_sync_eth ^ finish_sync_eth_d; + wire finish_pulse = finish_sync ^ finish_sync_d; always_ff @(posedge adc_clk_in or posedge adc_rst_int) begin if (adc_rst_int) begin @@ -191,13 +138,13 @@ module control #( always_ff @(posedge ctrl_clk or posedge ctrl_rst) begin if (ctrl_rst) begin - finish_meta_eth <= 1'b0; - finish_sync_eth <= 1'b0; - finish_sync_eth_d <= 1'b0; + finish_meta <= 1'b0; + finish_sync <= 1'b0; + finish_sync_d <= 1'b0; end else begin - finish_meta_eth <= finish_toggle_adc; - finish_sync_eth <= finish_meta_eth; - finish_sync_eth_d <= finish_sync_eth; + finish_meta <= finish_toggle_adc; + finish_sync <= finish_meta_eth; + finish_sync_d <= finish_sync_eth; end end @@ -223,11 +170,11 @@ module control #( dac_start <= 1'b0; dac_rst <= 1'b0; end else begin - start_meta_dac <= start_toggle_eth; + start_meta_dac <= start_toggle; start_sync_dac <= start_meta_dac; start_sync_dac_d <= start_sync_dac; - rst_meta_dac <= rst_toggle_eth; + rst_meta_dac <= rst_toggle; rst_sync_dac <= rst_meta_dac; rst_sync_dac_d <= rst_sync_dac; @@ -258,11 +205,11 @@ module control #( adc_start <= 1'b0; adc_rst <= 1'b0; end else begin - start_meta_adc <= start_toggle_eth; + start_meta_adc <= start_toggle; start_sync_adc <= start_meta_adc; start_sync_adc_d <= start_sync_adc; - rst_meta_adc <= rst_toggle_eth; + rst_meta_adc <= rst_toggle; rst_sync_adc <= rst_meta_adc; rst_sync_adc_d <= rst_sync_adc; @@ -271,8 +218,8 @@ module control #( end end - // ETH -> DAC config CDC - // cfg_bus_eth is kept stable in ETH domain until DAC and ADC both ACK. + // contrl -> DAC config CDC + // cfg_bus is kept stable in contrl domain until DAC and ADC both ACK. (* ASYNC_REG = "TRUE" *) logic cfg_req_meta_dac, cfg_req_sync_dac; logic cfg_req_sync_dac_d; wire cfg_req_pulse_dac = cfg_req_sync_dac ^ cfg_req_sync_dac_d; @@ -294,10 +241,10 @@ module control #( cfg_req_sync_dac_d <= cfg_req_sync_dac; if (cfg_req_pulse_dac) begin - dac_pulse_width <= cfg_bus_eth[31:0]; - dac_pulse_period <= cfg_bus_eth[63:32]; - dac_pulse_num <= cfg_bus_eth[79:64]; - dac_pulse_height <= cfg_bus_eth[80 +: DAC_DATA_WIDTH]; + dac_pulse_width <= cfg_bus[31:0]; + dac_pulse_period <= cfg_bus[63:32]; + dac_pulse_num <= cfg_bus[79:64]; + dac_pulse_height <= cfg_bus[80 +: DAC_DATA_WIDTH]; cfg_ack_toggle_dac <= ~cfg_ack_toggle_dac; end @@ -323,8 +270,8 @@ module control #( cfg_req_sync_adc_d <= cfg_req_sync_adc; if (cfg_req_pulse_adc) begin - adc_pulse_period <= cfg_bus_eth[127:96]; - adc_pulse_num <= cfg_bus_eth[79:64]; + adc_pulse_period <= cfg_bus[127:96]; + adc_pulse_num <= cfg_bus[79:64]; cfg_ack_toggle_adc <= ~cfg_ack_toggle_adc; end