diff --git a/designs/reflectometer/reflectometer.sv b/designs/reflectometer/reflectometer.sv
index 9da7bbf..2b7b7d3 100644
--- a/designs/reflectometer/reflectometer.sv
+++ b/designs/reflectometer/reflectometer.sv
@@ -1,7 +1,14 @@
 `timescale 1 ns / 1 ns
 
 module reflectometer_top #(
-    parameter int unsigned DAC_DATA_WIDTH = 14
+    parameter int unsigned DAC_DATA_WIDTH = 14,
+    parameter int unsigned ADC_DATA_WIDTH = 12,
+    parameter PACK_FACTOR = 1,
+    parameter PROCESS_MODE = 0,
+    parameter ACCUM_WIDTH = 32,
+    parameter N_MAX = 4096,
+    parameter WINDOW_SIZE = 65,
+    parameter PACKET_SIZE = 1024
 )(
     input               sys_clk_p,
     input               sys_clk_n,
@@ -23,6 +30,12 @@ module reflectometer_top #(
     // DAC
 
     (* MARK_DEBUG="true" *) output debug_dac
+
+    // ADC
+
+    input [ADC_DATA_WIDTH-1:0] adc_data_in;
+    input adc_out_of_range;
+
 );
     // temp
     wire              p2_clk;
@@ -222,9 +235,7 @@ module reflectometer_top #(
     // If you don't want this, replace with:
     // wire finish_dbg = 1'b0;
     // -------------------------------------------------------------------------
-    (* MARK_DEBUG="true" *) logic        finish_dbg;
-    (* MARK_DEBUG="true" *) logic [7:0]  finish_cnt;
-    (* MARK_DEBUG="true" *) logic        finish_pending;
+    (* MARK_DEBUG="true" *) logic        finish;
 
     // Controller outputs to debug
     (* MARK_DEBUG="true" *) wire [31:0]               dac_pulse_width;
@@ -232,35 +243,14 @@ module reflectometer_top #(
     (* MARK_DEBUG="true" *) wire [DAC_DATA_WIDTH-1:0] dac_pulse_height;
     (* MARK_DEBUG="true" *) wire [15:0]               dac_pulse_num;
 
-    (* MARK_DEBUG="true" *) wire [31:0]               adc_pulse_period_dbg;
-    (* MARK_DEBUG="true" *) wire [15:0]               adc_pulse_num_dbg;
+    (* MARK_DEBUG="true" *) wire [31:0]               adc_pulse_period;
+    (* MARK_DEBUG="true" *) wire [15:0]               adc_pulse_num;
 
     (* MARK_DEBUG="true" *) wire                      dac_start;
-    (* MARK_DEBUG="true" *) wire                      adc_start_dbg;
+    (* MARK_DEBUG="true" *) wire                      adc_start;
     (* MARK_DEBUG="true" *) wire                      dac_rst;
-    (* MARK_DEBUG="true" *) wire                      adc_rst_dbg;
+    (* MARK_DEBUG="true" *) wire                      adc_rst;
 
-    always_ff @(posedge adc_clk or negedge ctrl_rst_n) begin
-        if (!ctrl_rst_n) begin
-            finish_dbg     <= 1'b0;
-            finish_cnt     <= 8'd0;
-            finish_pending <= 1'b0;
-        end else begin
-            finish_dbg <= 1'b0;
-
-            if (adc_start_dbg) begin
-                finish_pending <= 1'b1;
-                finish_cnt     <= 8'd80;
-            end else if (finish_pending) begin
-                if (finish_cnt == 8'd0) begin
-                    finish_dbg     <= 1'b1;
-                    finish_pending <= 1'b0;
-                end else begin
-                    finish_cnt <= finish_cnt - 8'd1;
-                end
-            end
-        end
-    end
 
     // -------------------------------------------------------------------------
     // Controller
@@ -279,21 +269,21 @@ module reflectometer_top #(
         .s_axis_tready     (), // controller internally always ready in current version
         .s_axis_tlast      (m_axis_rx_tlast),
 
-        .finish            (finish_dbg),
+        .finish            (finish),
 
         .dac_pulse_width   (dac_pulse_width),
         .dac_pulse_period  (dac_pulse_period),
         .dac_pulse_height  (dac_pulse_height),
         .dac_pulse_num     (dac_pulse_num),
 
-        .adc_pulse_period  (adc_pulse_period_dbg),
-        .adc_pulse_num     (adc_pulse_num_dbg),
+        .adc_pulse_period  (adc_pulse_period),
+        .adc_pulse_num     (adc_pulse_num),
 
         .dac_start         (dac_start),
-        .adc_start         (adc_start_dbg),
+        .adc_start         (adc_start),
 
         .dac_rst           (dac_rst),
-        .adc_rst           (adc_rst_dbg)
+        .adc_rst           (adc_rst)
     );
 
     // -------------------------------------------------------------------------
@@ -334,8 +324,63 @@ module reflectometer_top #(
         .I(p2_clk_oddr),
         .O(p2_clk)
     );
-    
-    //assign p2_wrt = p2_clk;
+
+// -------------------------------------------------------------------------
+    // ADC
+    // -------------------------------------------------------------------------
+
+    logic [DATA_WIDTH*PACK_FACTOR-1:0]  accum_m_axis_tdata;
+    logic acum_m_axis_tvalid;
+
+    sampler 
+    #(
+        .DATA_WIDTH(ADC_DATA_WIDTH),
+        .PACK_FACTOR(PACK_FACTOR),
+        .PROCESS_MODE(PROCESS_MODE)
+    )
+    sampler_dut
+    (
+       .clk_in(adc_clk),
+       .rst(adc_rst),
+       .data_in(adc_data_in),
+       .out_of_range(adc_out_of_range),
+       .m_axis_tdata(accum_m_axis_tdata),
+       .m_axis_tvalid(acum_m_axis_tvalid)
+    );
+
+    // -------------------------------------------------------------------------
+    // Accumulator
+    // -------------------------------------------------------------------------
+
+    accumulator_top
+    #(
+        .DATA_WIDTH(ADC_DATA_WIDTH),
+        .ACCUM_WIDTH(ACCUM_WIDTH),
+        .N_MAX(N_MAX),
+        .WINDOW_SIZE(WINDOW_SIZE),
+        .PACKET_SIZE(PACKET_SIZE)
+    )
+    accumulator_top_dut
+    (
+        .clk_in(adc_clk),
+        .rst(adc_rst),
+        .s_axis_tdata(accum_m_axis_tdata),
+        .s_axis_tvalid(acum_m_axis_tvalid),
+        .start(adc_start),
+        .smp_num(adc_pulse_period),
+        .seq_num(adc_pulse_num),
+
+        .eth_clk_in(gmii_rx_clk),
+        .req_ready(req_ready),
+        .send_req(send_req),
+        .m_axis_tdata(m_axis_rx_tdata),
+        .m_axis_tvalid(m_axis_rx_tvalid),
+        .m_axis_tready(m_axis_rx_tready),
+        .m_axis_tlast(m_axis_rx_tlast),
+
+        .finish(finish)
+    );
+
 
     // -------------------------------------------------------------------------
     // Simple LED status
@@ -343,6 +388,6 @@ module reflectometer_top #(
     assign led[0] = clk_wiz_locked;
     assign led[1] = m_axis_rx_tvalid;
     assign led[2] = dac_start;
-    assign led[3] = adc_rst_dbg;
+    assign led[3] = debug_dac;
 
 endmodule
\ No newline at end of file