From 136b69dd9faaf78e74107938c99ac472375b4bdd Mon Sep 17 00:00:00 2001 From: otroubi Date: Thu, 3 Sep 2026 15:49:58 +0300 Subject: [PATCH] .sv testbench for new reflectometer --- .../reflectometer_tb.sv | 373 ++++++++++++++++++ 1 file changed, 373 insertions(+) create mode 100644 designs/full_new_reflectometer/tests/full_reflectometer_test/reflectometer_tb.sv diff --git a/designs/full_new_reflectometer/tests/full_reflectometer_test/reflectometer_tb.sv b/designs/full_new_reflectometer/tests/full_reflectometer_test/reflectometer_tb.sv new file mode 100644 index 0000000..1d1cbd9 --- /dev/null +++ b/designs/full_new_reflectometer/tests/full_reflectometer_test/reflectometer_tb.sv @@ -0,0 +1,373 @@ +`timescale 1ns / 1ps + +`include "interfaces.svh" + +module reflectometer_tb; + //------------------------------------------------------------ + // Параметры + //------------------------------------------------------------ + localparam int unsigned DAC_DATA_WIDTH = 14; + localparam int unsigned ADC_DATA_WIDTH = 12; + localparam LOGIC_ZERO_LEVEL = 0; // DAC -5V for logic zero + localparam VOLTAGE_ZERO_LEVEL = 2**(DAC_DATA_WIDTH-1); // DAC 0V for logic zero + localparam PACK_FACTOR = 1; // not used in TB + localparam PROCESS_MODE = 0; // 0 - uint, 1 - int. Current accumulator don't support signed sum + localparam ACCUM_WIDTH = 32; // accumulator number bit witdth + localparam N_MAX = 4096; // max value of windows to average by experiments + localparam PACKET_SIZE = 1024; // bytes per UDP packet + + localparam int REQUEST_TIMEOUT = 3 * PACKET_SIZE; // timeout for packet receiving from accumulator + + localparam ZERO_LEVEL = LOGIC_ZERO_LEVEL; // "logic" VS "voltage" + + localparam CLK_ETH_PHY_PERIOD = 8.000; // 125 MHz + localparam CLK_REF_PERIOD = 5.000; // 200 MHz + + //------------------------------------------------------------ + // Глобальные перменные + //------------------------------------------------------------ + int unsigned WINDOW_SIZE = 65; // fixed subwindow size to average by time + + //------------------------------------------------------------ + // Тактовые сигналы и сброс + //------------------------------------------------------------ + logic clk_ref = 1'b0; // 200 MHz + logic clk_eth_phy = 1'b0; // common for RX & TX + logic rst_n = 1'b0; + + //------------------------------------------------------------ + // Управление и конфиг DUT + //------------------------------------------------------------ + logic [31:0] window_size; + // AXI-S интерфейс для управления + axis_if axis_control_if ( + .clk(clk_eth_phy), + .rst_n(rst_n) + ); + + //------------------------------------------------------------ + // Входы DUT + //------------------------------------------------------------ + // ADC интерфейс + wire clk_adc; + wire adc_otr; + wire [ADC_DATA_WIDTH-1:0] adc_data; + + //------------------------------------------------------------ + // Выходы + //------------------------------------------------------------ + // Статусы + wire mmcm_locked; + wire workflow_done; + wire processing_done; + // DAC интерфейс + wire clk_dac; + wire dac_wrt; + wire [DAC_DATA_WIDTH-1:0] dac_data; + // AXI-S интерфейс для данных + axis_if axis_accumulator_if ( + .clk(clk_eth_phy), + .rst_n(rst_n) + ); + //------------------------------------------------------------ + // Внутренние сигналы тестбенча + //------------------------------------------------------------ + // Интерфейс хендшейка с MAC-PHY + wire send_request; + logic request_ready; + // Сигнал между ЦАП и АЦП + real signal_voltage; + + //------------------------------------------------------------ + // Virtual DAC + //------------------------------------------------------------ + virtual_dac_model #( // default voltage range is +/- 5V + .DAC_DATA_WIDTH(DAC_DATA_WIDTH) + // ,.VOLTAGE_GAIN(2) + ) virtual_dac ( + .clk_i(clk_dac), + .wrt_i(dac_wrt), + .data_i(dac_data), + .voltage_o(signal_voltage) + ); + + //------------------------------------------------------------ + // Virtual ADC + //------------------------------------------------------------ + virtual_adc_model #( // default voltage range is +/- 5V + .ADC_DATA_WIDTH(ADC_DATA_WIDTH) + ) virtual_adc ( + .clk_i(clk_adc), + .voltage_i(signal_voltage), + .otr_o(adc_otr), + .data_o(adc_data) + ); + + //------------------------------------------------------------ + // Statistics processing + //------------------------------------------------------------ + + //------------------------------------------------------------ + // Config handler + //------------------------------------------------------------ + + //------------------------------------------------------------ + // DUT + //------------------------------------------------------------ + reflectometer_top #( + .DAC_DATA_WIDTH(DAC_DATA_WIDTH), + .ADC_DATA_WIDTH(ADC_DATA_WIDTH), + .PACK_FACTOR(PACK_FACTOR), + .PROCESS_MODE(PROCESS_MODE), + .ZERO_LEVEL(ZERO_LEVEL), + .ACCUM_WIDTH(ACCUM_WIDTH), + .N_MAX(N_MAX), + .PACKET_SIZE(PACKET_SIZE) + ) DUT ( + .clk_in(clk_ref), + .rst_n(rst_n), + + // Status + .locked(mmcm_locked), + .workflow_done(workflow_done), + .processing_done(processing_done), + + // Accumulator AXI-S bus + .clk_axis_accumulator(clk_eth_phy), // GMII PHY RX clock + .axis_accumulator(axis_accumulator_if.master), + + // Control AXI-S bus + .clk_axis_control(clk_eth_phy), // GMII PHY TX clock + .axis_control(axis_control_if.slave), + .window_size(window_size), // direct signal crutch (old controller) + + // RTL-MAC handshake + .request_ready(request_ready), + .send_request(send_request), + + // DAC + .dac_clk_o(clk_dac), + .dac_data(dac_data), + .dac_wrt(dac_wrt), + + // ADC + .adc_clk_o(clk_adc), + .adc_data(adc_data), + .adc_otr(adc_otr) + ); + assign window_size = WINDOW_SIZE; + + //------------------------------------------------------------ + // Тактовые сигналы + //------------------------------------------------------------ + initial begin + forever #(CLK_REF_PERIOD/2) clk_ref = ~clk_ref; + end + initial begin + forever #(CLK_ETH_PHY_PERIOD/2) clk_eth_phy = ~clk_eth_phy; + end + + //------------------------------------------------------------ + // Таски для тестирования + //------------------------------------------------------------ + // Таски работы с AXI-Stream + task automatic dut_soft_reset(virtual axis_if#(8).tb vif); + logic [7:0] tx_packet[]; + tx_packet = '{8'h0f}; + vif.master_send(tx_packet); + endtask + + task automatic dut_start(virtual axis_if#(8).tb vif); + logic [7:0] tx_packet[]; + tx_packet = '{8'hf0}; + vif.master_send(tx_packet); + endtask + + task automatic dut_send_system_config( + virtual axis_if#(8).tb vif, + input logic [31:0] pulse_width, + input logic [31:0] pulse_period, + input logic [15:0] pulse_num, + input logic [13:0] pulse_height, // achtung! p_height strictly must have 14 bits of width + input logic [31:0] pulse_period_adc, + input logic [31:0] window_size + ); + // Создаем временный фиксированный массив и упаковываем всё одной строкой + logic [7:0] tx_packet[]; + + // Ахтунг, 14-битный ЦАП захардкожен + if (DAC_DATA_WIDTH != 14) + $display("[WARNING] -dut_send_system_config- Default pulse height (DAC bitwidth) is equal to 14. Be aware, controller packet structure is coded for 14 bits"); + + tx_packet = '{ + 8'h88, // Команда + pulse_width[7:0], pulse_width[15:8], pulse_width[23:16], pulse_width[31:24], + pulse_period[7:0], pulse_period[15:8], pulse_period[23:16], pulse_period[31:24], + pulse_num[7:0], pulse_num[15:8], pulse_height[7:0], 8'({2'b00, pulse_height[13:8]}), + pulse_period_adc[7:0], pulse_period_adc[15:8], pulse_period_adc[23:16], pulse_period_adc[31:24] + }; + + vif.master_send(tx_packet); + + // TODO remove for new controller + WINDOW_SIZE = window_size; + endtask + + // Таски сбора статистики + task automatic dut_read_output( + virtual axis_if#(8).tb vif, + input int sample_num, + input bit randomize_recv_delays, + output int output_data[] + ); + logic [7:0] rx_packet[]; + logic [ACCUM_WIDTH-1:0] data_packet[]; + int numbers_per_packet = PACKET_SIZE/(ACCUM_WIDTH/8); + int packet_num = $ceil(real'(sample_num / WINDOW_SIZE) / real'(numbers_per_packet)); + int timeout_flag = 0; + int packet_counter = 0; + + if (sample_num % WINDOW_SIZE) begin + $display("[ERROR] -dut_read_output- Sample_num must be multiple of WINDOW_SIZE: %0d %% %0d = %0d", sample_num, WINDOW_SIZE, sample_num % WINDOW_SIZE); + $finish; + end + + data_packet = new[numbers_per_packet]; + output_data = new[numbers_per_packet * packet_num]; + + // count send_request pulses (equal to number of packets) + fork + begin : packet_counter_proc + forever begin + @(posedge clk_eth_phy); + if(send_request === 1) + packet_counter++; + end + end + join_none + + // Wait until reflectometer done sampling and averaging + wait(processing_done == 1); + + // recv loop + // если число пакетов превышает заложенное предрассчитанное значение -- ошибка + fork : recv_loop_proc + begin + // packet recv loop + forever begin + if (packet_counter > packet_num) begin + $display("[ERROR] -dut_read_output- Packet overflow detected. Number of data packets exceeds expected amount of packets"); + $finish; + end + + if (randomize_recv_delays) + repeat($urandom_range(0, 500)) @(posedge clk_eth_phy); + + timeout_flag = 0; + fork : receive_packet_timeout + begin + request_ready = 1; + vif.slave_recv(rx_packet); + request_ready = 0; + end + begin + repeat(REQUEST_TIMEOUT) @(posedge clk_eth_phy); + timeout_flag = 1; + end + join_any + + disable receive_packet_timeout; + if (timeout_flag) begin + $display("[ERROR] -dut_read_output- Timeout detected when receiving packet"); + $finish; + end + + if (rx_packet.size() != PACKET_SIZE) begin + $display("[ERROR] -dut_read_output- Wrong packet size received: %0d bytes received, %0d bytes expected", rx_packet.size(), PACKET_SIZE); + $finish; + end + + // unpack values + data_packet = {<< byte {rx_packet}}; + data_packet = {<< ACCUM_WIDTH {data_packet}}; + + // copy and convert values + for (int j = 0; j < data_packet.size(); j++) begin + output_data[(packet_counter-1) * data_packet.size() + j] = int'(data_packet[j]); + end + + end + end + begin + // IP workflow completion event + wait(workflow_done == 1); + end + join_any + + disable recv_loop_proc; + disable packet_counter_proc; + + if (packet_counter != packet_num) begin + $display("[ERROR] -dut_read_output- Wrong number of packets received: %0d received, %0d expected", packet_counter, packet_num); + $finish; + end + + endtask + + // Основная таска типового теста + // todo + + //------------------------------------------------------------ + // ОСНОВНОЙ ПРОЦЕСС ТЕСТИРОВАНИЯ + //------------------------------------------------------------ + initial begin + int output_data[]; + + automatic virtual axis_if.tb control_vif = axis_control_if.tb; + automatic virtual axis_if.tb accumulator_vif = axis_accumulator_if.tb; + + $display("[TB] DUT initializaton"); + // Инициализация + request_ready = 0; + rst_n = 0; + #100; + rst_n = 1; + wait(mmcm_locked === 1'b1); + #150; + $display("[TB] MMCM locked"); + + dut_soft_reset(control_vif); + #100; + + // Тесты + $display("[TB] Tests start"); + dut_send_system_config( + .vif(control_vif), + .pulse_width(32'd123), + .pulse_period(32'd5000), + .pulse_num(16'd1), + .pulse_height(14'd15000), // 0V + .pulse_period_adc(32'd2600), + .window_size(1) + ); + #100; + dut_start(control_vif); + + dut_read_output( + .vif(accumulator_vif), + .sample_num(2600), + .randomize_recv_delays(0), + .output_data(output_data) + ); + #1000; + + $display("Received %0d numbers", output_data.size()); + for (int i = 0; i < output_data.size(); i++) begin + $write("%0d ", output_data[i]); + end + $display(""); + + $display("[TB] ALL PASSED"); + $finish; + end +endmodule