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upd: reflectometer on axis bus iface + TB

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babintsev.lv
2026-07-10 18:46:48 +03:00
parent 0ba25a3541
commit 11a9e97691
5 changed files with 199 additions and 124 deletions
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44
designs/reflectometer_base/reflectometer.sv
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@ -1,5 +1,7 @@
`timescale 1 ns / 1 ns
`include "interfaces.svh"
module reflectometer_top #(
parameter int unsigned DAC_DATA_WIDTH = 14,
parameter int unsigned ADC_DATA_WIDTH = 12,
@ -16,18 +18,12 @@ module reflectometer_top #(
output wire locked,
// Accumulator AXI-S bus
input wire clk_m_axis, // GMII PHY RX clock
output wire [7:0] m_axis_tdata,
output wire m_axis_tvalid,
input wire m_axis_tready,
output wire m_axis_tlast,
input wire clk_axis_accumulator, // GMII PHY RX clock
axis_if.master axis_accumulator,
// Control AXI-S bus
input wire clk_s_axis, // GMII PHY TX clock
input wire [7:0] s_axis__tdata,
input wire s_axis_tvalid,
input wire s_axis_tlast,
output wire s_axis_tready,
input wire clk_axis_control, // GMII PHY TX clock
axis_if.slave axis_control,
// RTL-MAC handshake
input wire request_ready,
@ -101,15 +97,15 @@ module reflectometer_top #(
control #(
.DAC_DATA_WIDTH(DAC_DATA_WIDTH)
) udp_ctrl_inst (
.eth_clk_in (clk_s_axis),
.eth_clk_in (clk_axis_control),
.dac_clk_in (clk_generator),
.adc_clk_in (clk_sampler),
.rst_n (ctrl_rst_n),
.s_axis_tdata (s_axis__tdata),
.s_axis_tvalid (s_axis_tvalid),
.s_axis_tready (s_axis_tready),
.s_axis_tlast (s_axis_tlast),
.s_axis_tdata (axis_control.tdata),
.s_axis_tvalid (axis_control.tvalid),
.s_axis_tready (axis_control.tready),
.s_axis_tlast (axis_control.tlast),
.finish (finish),
@ -131,9 +127,9 @@ module reflectometer_top #(
//------------------------------------------------------------
// DAC -> ADC CDC
//------------------------------------------------------------
logic [2:0] stretch; // 125/65~=2. Чтобы поймать единичный импульс, растянем его во времени
logic [1:0] sync_DA;
wire dac_done_stretched;
(* ASYNC_REG = "TRUE" *) logic [2:0] stretch; // 125/65~=2. Чтобы поймать единичный импульс, растянем его во времени
(* ASYNC_REG = "TRUE" *) logic [1:0] sync_DA;
wire dac_done_stretched;
wire generator_done, generator_request;
wire sampler_done, sampler_request;
@ -163,7 +159,7 @@ module reflectometer_top #(
//------------------------------------------------------------
// ADC -> DAC CDC
//------------------------------------------------------------
logic [1:0] sync_AD;
(* ASYNC_REG = "TRUE" *) logic [1:0] sync_AD;
always_ff @(posedge clk_generator or posedge dac_rst) begin
if (dac_rst)
@ -237,11 +233,11 @@ module reflectometer_top #(
.req_ready(request_ready),
.send_req(send_request),
.eth_clk_in(clk_m_axis),
.m_axis_tdata(m_axis_tdata),
.m_axis_tvalid(m_axis_tvalid),
.m_axis_tready(m_axis_tready),
.m_axis_tlast(m_axis_tlast),
.eth_clk_in(clk_axis_accumulator),
.m_axis_tdata(axis_accumulator.tdata),
.m_axis_tvalid(axis_accumulator.tvalid),
.m_axis_tready(axis_accumulator.tready),
.m_axis_tlast(axis_accumulator.tlast),
.finish(finish)
);