baulin.fa/reflectometer_fpga_project
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upd: reflectometer on axis bus iface + TB

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babintsev.lv
2026-07-10 18:46:48 +03:00
parent 0ba25a3541
commit 11a9e97691
5 changed files with 199 additions and 124 deletions
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8
designs/reflectometer_base/Makefile
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@ -10,16 +10,21 @@
FPGA_PART = xc7a100tfgg484-2
FPGA_TOP = reflectometer_top
FPGA_ARCH = artix7
SIM_TOP = reflectometer_tb
RTL_DIR = ../../rtl
include ../../scripts/vivado.mk
INC_FILES += interfaces.svh
TB_FILES += reflectometer_tb.sv
SYN_FILES += reflectometer.sv
SYN_FILES += dac_model.sv
SYN_FILES += adc_model.sv
SYN_FILES += tb_reflectometer.sv
SYN_FILES += reflectometer_tb.sv
SYN_FILES += $(sort $(shell find ../../rtl -type f \( -name '*.v' -o -name '*.sv' \)))
XCI_FILES = $(sort $(shell find ../../rtl/ethernet-udp/src -type f -name '*.xci'))
@ -28,7 +33,6 @@ XCI_FILES += $(sort $(shell find ip/ -type f -name '*.xci'))
XDC_FILES += ../../constraints/ax7102.xdc
XDC_FILES += debug.xdc
SIM_TOP = tb_reflectometer
program: $(PROJECT).bit