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add: vrtual DAC & ADC subsystem for TB

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fix: makefile
upd: clocking wiz IP
This commit is contained in:
babintsev.lv
2026-07-10 14:15:49 +03:00
parent 64f94a90e6
commit 0ba25a3541
6 changed files with 223 additions and 161 deletions
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8
designs/reflectometer_base/dac_model.sv
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@ -22,7 +22,7 @@ module virtual_dac_model #(
);
localparam int unsigned ZERO_CODE = (1 << (DAC_DATA_WIDTH - 1));
localparam real VOLTAGE_STEP = VOLTAGE_RANGE / real'(ZERO_CODE);
localparam real VOLTAGE_STEP = (2 * VOLTAGE_RANGE) / real'((1 << DAC_DATA_WIDTH) - 1);
logic [DAC_DATA_WIDTH-1:0] dac_code;
@ -45,16 +45,14 @@ module virtual_dac_model #(
// Latch new DAC code
//------------------------------------------------------------
always @(posedge wrt_i) begin
#(TRANSMISSION_DELAY);
dac_code = data_i;
dac_code <= #(TRANSMISSION_DELAY) data_i;
end
//------------------------------------------------------------
// Update analog output
//------------------------------------------------------------
always @(posedge clk_i) begin
#(CONVERSION_DELAY);
voltage_o = code_to_voltage(dac_code) * VOLTAGE_GAIN + GROUND_BIAS;
voltage_o <= #(CONVERSION_DELAY) code_to_voltage(dac_code) * VOLTAGE_GAIN + GROUND_BIAS;
end
endmodule