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add: vrtual DAC & ADC subsystem for TB

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fix: makefile
upd: clocking wiz IP
This commit is contained in:
babintsev.lv
2026-07-10 14:15:49 +03:00
parent 64f94a90e6
commit 0ba25a3541
6 changed files with 223 additions and 161 deletions
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28
designs/reflectometer_base/adc_model.sv
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@ -11,7 +11,7 @@ module virtual_adc_model #(
parameter real GROUND_BIAS = 0.0,
// ADC timing parameters
parameter time CONVERSION_DELAY = 150ps
parameter time CONVERSION_DELAY = 250ps
)(
input logic clk_i,
input real voltage_i,
@ -21,15 +21,22 @@ module virtual_adc_model #(
);
localparam int unsigned ZERO_CODE = (1 << (ADC_DATA_WIDTH - 1));
localparam real VOLTAGE_STEP = VOLTAGE_RANGE / real'(ZERO_CODE);
localparam real VOLTAGE_STEP = (2 * VOLTAGE_RANGE) / real'((1 << ADC_DATA_WIDTH) - 1);
real voltage_corrected;
//------------------------------------------------------------
// Convert analog voltage to ADC code TODO: add OTR check
// Convert analog voltage to ADC code
//------------------------------------------------------------
function automatic real code_to_voltage(
input logic [ADC_DATA_WIDTH-1:0] code
);
return (int'(code) - int'(ZERO_CODE)) * VOLTAGE_STEP;
function automatic logic [ADC_DATA_WIDTH-1:0] voltage_to_code( input real voltage );
if (voltage <= -VOLTAGE_RANGE) return '0;
if (voltage >= VOLTAGE_RANGE) return {ADC_DATA_WIDTH{1'b1}};
return $rtoi(voltage / VOLTAGE_STEP + real'((ZERO_CODE)) + 0.5);
endfunction
function automatic logic range_check( input real voltage );
real v_abs = (voltage < 0.0) ? -voltage : voltage;
return v_abs >= VOLTAGE_RANGE;
endfunction
//------------------------------------------------------------
@ -44,10 +51,9 @@ module virtual_adc_model #(
// Update analog output
//------------------------------------------------------------
always @(posedge clk_i) begin
#(CONVERSION_DELAY);
data_o = ;
otr_o = ;
voltage_corrected = (voltage_i - GROUND_BIAS) * VOLTAGE_GAIN;
data_o <= #(CONVERSION_DELAY) voltage_to_code(voltage_corrected);
otr_o <= #(CONVERSION_DELAY) range_check(voltage_corrected);
end
endmodule