add: vrtual DAC & ADC subsystem for TB

fix: makefile upd: clocking wiz IP
2026-07-10 14:15:49 +03:00
parent 64f94a90e6
commit 0ba25a3541
6 changed files with 223 additions and 161 deletions
--- a/designs/reflectometer_base/Makefile
+++ b/designs/reflectometer_base/Makefile
@ -28,6 +28,7 @@ XCI_FILES += $(sort $(shell find ip/ -type f -name '*.xci'))
 XDC_FILES += ../../constraints/ax7102.xdc
 XDC_FILES += debug.xdc

+SIM_TOP = tb_reflectometer


 program: $(PROJECT).bit