baulin.fa/reflectometer_fpga_project
2
0
Fork 0
Code Issues 4 Pull Requests Actions Packages Projects Releases Wiki Activity

add: vrtual DAC & ADC subsystem for TB

Browse Source 
fix: makefile
upd: clocking wiz IP
This commit is contained in:
babintsev.lv
2026-07-10 14:15:49 +03:00
parent 64f94a90e6
commit 0ba25a3541
6 changed files with 223 additions and 161 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
designs/adc_dac_synchoronizer/Makefile
View File

@ -27,6 +27,7 @@ XDC_FILES += ../../constraints/ax7102.xdc
XDC_FILES += debug.xdc
SYN_FILES += tb_sync_top.sv
SIM_TOP = tb_top