From 0a68a753bef35d02a97e8f6058950a54389e3f56 Mon Sep 17 00:00:00 2001
From: "babintsev.lv" <babintsev.lv@mipt.ru>
Date: Fri, 29 May 2026 18:01:31 +0300
Subject: [PATCH] generator quick fix

---
 rtl/generator/src/generator.sv      |  7 ++-
 rtl/generator/tests/generator_tb.sv | 95 ++++++++++++++++-------------
 2 files changed, 58 insertions(+), 44 deletions(-)

diff --git a/rtl/generator/src/generator.sv b/rtl/generator/src/generator.sv
index 030dfd0..2fa2205 100644
--- a/rtl/generator/src/generator.sv
+++ b/rtl/generator/src/generator.sv
@@ -43,7 +43,8 @@ module generator
             cnt_pulse_num <= '0;
             cnt_period <= '0;
             sample_req <= 0;
-        end else begin
+        end 
+        else begin
             if (start & !enable) begin
                 enable <= 1'b1;
                 cnt_pulse_num <= '0;
@@ -77,12 +78,12 @@ module generator
                 end
                  else begin
                         
-                    if (cnt_period <= pulse_width_reg) begin
+                    if (cnt_period < pulse_width_reg - 1) begin
                         pulse_height_out_reg <= pulse_height_reg;
                     end else begin
                         pulse_height_out_reg <= ZERO_LEVEL;
                     end
-                    if (cnt_period == pulse_period_reg) begin
+                    if (cnt_period == pulse_period_reg - 1) begin
                         cnt_period <= 0;
                     end else begin
                         cnt_period <= cnt_period + 1;
diff --git a/rtl/generator/tests/generator_tb.sv b/rtl/generator/tests/generator_tb.sv
index 2fdeb95..451ffce 100644
--- a/rtl/generator/tests/generator_tb.sv
+++ b/rtl/generator/tests/generator_tb.sv
@@ -3,8 +3,8 @@
 module generator_tb;
 
     parameter DATA_WIDTH = 14;
-    parameter ZERO_LEVEL = 8192;
-    parameter CLK_PERIOD = 16;
+    parameter ZERO_LEVEL = 0;
+    parameter CLK_PERIOD = 8;
 
     logic clk;
     logic rst;
@@ -17,10 +17,12 @@ module generator_tb;
 
     logic pulse;
     logic [DATA_WIDTH-1:0] pulse_height_out;
+    logic sample_done, sample_req;
 
     // DUT
     generator #(
-        .DATA_WIDTH(DATA_WIDTH)
+        .DATA_WIDTH(DATA_WIDTH),
+        .ZERO_LEVEL(ZERO_LEVEL)
     ) dut (
         .clk_in(clk),
         .rst(rst),
@@ -30,7 +32,9 @@ module generator_tb;
         .pulse_height(pulse_height),
         .pulse_num(pulse_num),
         .pulse(pulse),
-        .pulse_height_out(pulse_height_out)
+        .pulse_height_out(pulse_height_out),
+        .sample_done(sample_done),
+        .sample_req(sample_req)
     );
 
     // Clock
@@ -49,6 +53,7 @@ module generator_tb;
         pulse_period = 0;
         pulse_height = 0;
         pulse_num    = 0;
+        sample_done  = 0;
 
         repeat(5) @(posedge clk);
         rst = 0;
@@ -56,59 +61,67 @@ module generator_tb;
         // --- Test 1 ---
         // 3 clk 1, 5 clk 0,  4 pulses
        repeat(2) @(posedge clk);
-        pulse_width  = 3;
-        pulse_period = 8;
+        pulse_width  = 1;
+        pulse_period = 20;
         pulse_num    = 4;
         pulse_height = 14'h3FF;
+        #1;
         start = 1;
 
-       repeat(1) @(posedge clk);
+        repeat(1) @(posedge clk);
         start = 0;
 
-        repeat(50) @(posedge clk);
-
-        // --- Test 2 ---
-        $display("\n--- SECOND RUN ---\n");
-
+        wait(sample_req == 1);
         @(posedge clk);
-        pulse_width  = 2;
-        pulse_period = 5;
-        pulse_num    = 3;
-        pulse_height = 14'h155;
-        start = 1;
+        #1;
+        sample_done = 1;
+        wait(sample_req == 0)
+            sample_done = 0;
 
-        @(posedge clk);
-        start = 0;
+        repeat(pulse_period*pulse_num+10) @(posedge clk);
+    
+    //     // --- Test 2 ---
+    //     $display("\n--- SECOND RUN ---\n");
 
-        repeat(40) @(posedge clk);
+    //     @(posedge clk);
+    //     pulse_width  = 2;
+    //     pulse_period = 5;
+    //     pulse_num    = 3;
+    //     pulse_height = 14'h155;
+    //     start = 1;
+
+    //     @(posedge clk);
+    //     start = 0;
+
+    //     repeat(40) @(posedge clk);
         
-        pulse_width  = 3;
-        pulse_period = 8;
-        pulse_num    = 4;
-        pulse_height = 14'h3FF;
-        start = 1;
+    //     pulse_width  = 3;
+    //     pulse_period = 8;
+    //     pulse_num    = 4;
+    //     pulse_height = 14'h3FF;
+    //     start = 1;
 
-       repeat(1) @(posedge clk);
-        start = 0;
+    //    repeat(1) @(posedge clk);
+    //     start = 0;
         
-        repeat(5) @(posedge clk);
-        start = 1;
-        pulse_height = 14'h155;
+    //     repeat(5) @(posedge clk);
+    //     start = 1;
+    //     pulse_height = 14'h155;
 
-       repeat(1) @(posedge clk);
-        start = 0;
+    //    repeat(1) @(posedge clk);
+    //     start = 0;
         
-        repeat(50) @(posedge clk);
+    //     repeat(50) @(posedge clk);
 
 
-        $display("\n=== TEST FINISHED ===");
-        $finish;
-    end
+    //     $display("\n=== TEST FINISHED ===");
+    //     $finish;
+     end
 
-    // Display
-    always @(posedge clk) begin
-        $display("t=%0t | pulse=%0b | height=%h",
-                  $time, pulse, pulse_height_out);
-    end
+    // // Display
+    // always @(posedge clk) begin
+    //     $display("t=%0t | pulse=%0b | height=%h",
+    //               $time, pulse, pulse_height_out);
+    // end
 
 endmodule
\ No newline at end of file