test: add all controller tests
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@ -1,5 +1,6 @@
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import cocotb
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import cocotb
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from cocotb.clock import Clock
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from cocotb.clock import Clock
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from cocotb.handle import Immediate
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from cocotb.triggers import RisingEdge
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from cocotb.triggers import RisingEdge
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from cocotbext.axi import AxiLiteBus, AxiLiteMaster
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from cocotbext.axi import AxiLiteBus, AxiLiteMaster
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@ -126,20 +127,44 @@ async def simple_controller_start_check(dut):
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@cocotb.test()
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@cocotb.test()
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async def simple_dma_desc_register_write(dut):
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async def simple_dma_desc_status(dut):
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tb = TB(dut)
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tb = TB(dut)
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await tb.reset()
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await tb.reset()
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# mock
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await tb.write_reg(REG_DESC_READ_ADDR, 0xdead)
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await tb.write_reg(REG_DESC_READ_ADDR, 0x0000_1000)
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await tb.write_reg(REG_DESC_READ_LEN, 64)
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await tb.write_reg(REG_DESC_READ_LEN, 64)
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await tb.write_reg(REG_DESC_READ_CONFIG, 0x0000_0001)
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await tb.write_reg(REG_DESC_READ_CONFIG, 0x0000_0001)
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assert await tb.read_reg(REG_DESC_READ_ADDR) == 0x0000_1000
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await tb.write_reg(REG_DESC_WRITE_ADDR, 0xbeef)
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assert await tb.read_reg(REG_DESC_READ_LEN) == 64
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await tb.write_reg(REG_DESC_WRITE_LEN_AND_TAG, 0x0005555)
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# W1S pulse: bit 3 = send_desc_read_o.
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# W1S pulse: bit 3 = send_desc_read_o.
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await tb.write_reg(REG_CONTROL, 1 << CTRL_SEND_DESC_READ)
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await tb.write_reg(REG_CONTROL, 1 << CTRL_SEND_DESC_READ)
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for _ in range(3):
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await tb.write_reg(REG_CONTROL, 1 << CTRL_SEND_DESC_WRITE)
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for _ in range(20):
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await RisingEdge(dut.ctrl_clk)
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await RisingEdge(dut.ctrl_clk)
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assert int(dut.desc_read_cmd_out.value) == 0x000000100040DEAD
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assert int(dut.desc_write_cmd_out.value) == 0x0005555BEEF
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# test status
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dut.status_read_cmd_in.value = Immediate(123)
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dut.status_write_cmd_in.value = Immediate(0xabcd90012345)
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dut.valid_status_read.value = Immediate(1)
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dut.valid_status_write.value = Immediate(1)
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for _ in range(10):
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await RisingEdge(dut.ctrl_clk)
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# read status
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await tb.write_reg(REG_CONTROL, 1 << CTRL_TAKE_STATUS_READ)
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await tb.write_reg(REG_CONTROL, 1 << CTRL_TAKE_STATUS_WRITE)
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for _ in range(10):
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await RisingEdge(dut.ctrl_clk)
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assert await tb.read_reg(REG_READ_STATUS) == 123
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assert await tb.read_reg(REG_STATUS_WRITE_CONFIG) == 0xABCD900
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assert await tb.read_reg(REG_STATUS_WRITE_LEN) == 0x12345
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