test: add all controller tests

This commit is contained in:
Phil
2026-07-14 20:07:52 +03:00
parent e685a6a9fc
commit 076ad542b2

View File

@ -1,5 +1,6 @@
import cocotb
from cocotb.clock import Clock
from cocotb.handle import Immediate
from cocotb.triggers import RisingEdge
from cocotbext.axi import AxiLiteBus, AxiLiteMaster
@ -126,20 +127,44 @@ async def simple_controller_start_check(dut):
@cocotb.test()
async def simple_dma_desc_register_write(dut):
async def simple_dma_desc_status(dut):
tb = TB(dut)
await tb.reset()
# mock
await tb.write_reg(REG_DESC_READ_ADDR, 0x0000_1000)
await tb.write_reg(REG_DESC_READ_ADDR, 0xdead)
await tb.write_reg(REG_DESC_READ_LEN, 64)
await tb.write_reg(REG_DESC_READ_CONFIG, 0x0000_0001)
assert await tb.read_reg(REG_DESC_READ_ADDR) == 0x0000_1000
assert await tb.read_reg(REG_DESC_READ_LEN) == 64
await tb.write_reg(REG_DESC_WRITE_ADDR, 0xbeef)
await tb.write_reg(REG_DESC_WRITE_LEN_AND_TAG, 0x0005555)
# W1S pulse: bit 3 = send_desc_read_o.
await tb.write_reg(REG_CONTROL, 1 << CTRL_SEND_DESC_READ)
for _ in range(3):
await tb.write_reg(REG_CONTROL, 1 << CTRL_SEND_DESC_WRITE)
for _ in range(20):
await RisingEdge(dut.ctrl_clk)
assert int(dut.desc_read_cmd_out.value) == 0x000000100040DEAD
assert int(dut.desc_write_cmd_out.value) == 0x0005555BEEF
# test status
dut.status_read_cmd_in.value = Immediate(123)
dut.status_write_cmd_in.value = Immediate(0xabcd90012345)
dut.valid_status_read.value = Immediate(1)
dut.valid_status_write.value = Immediate(1)
for _ in range(10):
await RisingEdge(dut.ctrl_clk)
# read status
await tb.write_reg(REG_CONTROL, 1 << CTRL_TAKE_STATUS_READ)
await tb.write_reg(REG_CONTROL, 1 << CTRL_TAKE_STATUS_WRITE)
for _ in range(10):
await RisingEdge(dut.ctrl_clk)
assert await tb.read_reg(REG_READ_STATUS) == 123
assert await tb.read_reg(REG_STATUS_WRITE_CONFIG) == 0xABCD900
assert await tb.read_reg(REG_STATUS_WRITE_LEN) == 0x12345