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debugged controller

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This commit is contained in:
otroubi
2026-07-10 13:13:18 +03:00
parent 99a344d534
commit 061f8fe12b
3 changed files with 553 additions and 150 deletions
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5
rtl/controller/src/controller.sv
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@ -90,7 +90,6 @@ module control #(
// Pending ACKs for config delivery
logic cfg_wait_dac_ack;
logic cfg_wait_adc_ack;
wire cfg_busy = cfg_wait_dac_ack || cfg_wait_adc_ack;
// Event toggles cntrl -> DAC/ADC
logic start_toggle;
@ -182,7 +181,7 @@ module control #(
cfg_wait_adc_ack <= 1'b0;
end
if (cfg_bus_valid && !busy && !cfg_busy) begin
if (cfg_bus_valid && !busy && !cfg_wait_dac_ack && !cfg_wait_adc_ack) begin
cfg_bus <= cfg_bus_input;
cfg_req_toggle_dac <= ~cfg_req_toggle_dac;
@ -192,7 +191,7 @@ module control #(
cfg_wait_adc_ack <= 1;
end
if (start && !busy && !cfg_busy) begin
if (start && !busy && !cfg_wait_dac_ack && !cfg_wait_adc_ack) begin
start_toggle <= ~start_toggle;
busy <= 1;
end