rtl: debug synchronizer project testbench

designs/adc_dac_synchoronizer/tb_sync_top.sv

@@ -0,0 +1,169 @@
+`timescale 1ns / 1ps
+
+module tb_top;
+
+    localparam DAC_DATA_WIDTH = 14;
+    localparam ADC_DATA_WIDTH = 12;
+    localparam PACK_FACTOR    = 1;
+    localparam PROCESS_MODE   = 0;
+
+    //------------------------------------------------------------
+    // clocks / reset
+    //------------------------------------------------------------
+    logic adc_clk_in;
+    logic adc_rst;
+
+    logic dac_clk_in;
+    logic dac_rst;
+
+    //------------------------------------------------------------
+    // control
+    //------------------------------------------------------------
+    logic dac_start;
+
+    logic [31:0] pulse_width;
+    logic [31:0] pulse_period;
+    logic [DAC_DATA_WIDTH-1:0] pulse_height;
+    logic [15:0] pulse_num;
+    logic [31:0] smp_num;
+
+    //------------------------------------------------------------
+    // outputs
+    //------------------------------------------------------------
+    logic [ADC_DATA_WIDTH*PACK_FACTOR-1:0] m_axis_tdata;
+    logic                                  m_axis_tvalid;
+
+    integer valid_count;
+
+    //------------------------------------------------------------
+    // DUT
+    //------------------------------------------------------------
+    sync_top #(
+        .DAC_DATA_WIDTH(DAC_DATA_WIDTH),
+        .ADC_DATA_WIDTH(ADC_DATA_WIDTH),
+        .PACK_FACTOR(PACK_FACTOR),
+        .PROCESS_MODE(PROCESS_MODE)
+    ) dut (
+        .adc_clk_in(adc_clk_in),
+        .adc_rst(adc_rst),
+
+        .dac_clk_in(dac_clk_in),
+        .dac_rst(dac_rst),
+
+        .dac_start(dac_start),
+
+        .pulse_width(pulse_width),
+        .pulse_period(pulse_period),
+        .pulse_height(pulse_height),
+        .pulse_num(pulse_num),
+        .smp_num(smp_num),
+
+        .m_axis_tdata(m_axis_tdata),
+        .m_axis_tvalid(m_axis_tvalid)
+    );
+
+    //------------------------------------------------------------
+    // ADC clock
+    //------------------------------------------------------------
+    initial begin
+        adc_clk_in = 1'b0;
+        forever #5 adc_clk_in = ~adc_clk_in;   // 100 MHz
+    end
+
+    //------------------------------------------------------------
+    // DAC clock
+    //------------------------------------------------------------
+    initial begin
+        dac_clk_in = 1'b0;
+        forever #8 dac_clk_in = ~dac_clk_in;   // slower domain
+    end
+
+    //------------------------------------------------------------
+    // monitor output stream
+    //------------------------------------------------------------
+    always @(posedge adc_clk_in) begin
+        if (m_axis_tvalid) begin
+            valid_count = valid_count + 1;
+
+            $display("[%0t] VALID: data=%0d",
+                     $time,
+                     m_axis_tdata);
+        end
+    end
+
+    //------------------------------------------------------------
+    // test
+    //------------------------------------------------------------
+    initial begin
+
+        adc_rst      = 1'b1;
+        dac_rst      = 1'b1;
+
+        dac_start    = 1'b0;
+
+        pulse_width  = 0;
+        pulse_period = 0;
+        pulse_height = 0;
+        pulse_num    = 0;
+        smp_num      = 0;
+
+        valid_count  = 0;
+
+        //--------------------------------------------------------
+        // reset
+        //--------------------------------------------------------
+        repeat (10) @(posedge adc_clk_in);
+        repeat (10) @(posedge dac_clk_in);
+
+        adc_rst = 1'b0;
+        dac_rst = 1'b0;
+
+        repeat (5) @(posedge dac_clk_in);
+
+        //--------------------------------------------------------
+        // config
+        //--------------------------------------------------------
+        pulse_width  = 32'd3;
+        pulse_period = 32'd8;
+        pulse_height = 14'd200;
+        pulse_num    = 16'd4;
+        smp_num      = 32'd8;
+
+        //--------------------------------------------------------
+        // start
+        //--------------------------------------------------------
+        @(posedge dac_clk_in);
+        dac_start = 1'b1;
+
+        @(posedge dac_clk_in);
+        dac_start = 1'b0;
+
+        $display("==================================");
+        $display("TEST START");
+        $display("==================================");
+
+        //--------------------------------------------------------
+        // wait
+        //--------------------------------------------------------
+        repeat (600) @(posedge adc_clk_in);
+
+        //--------------------------------------------------------
+        // check
+        //--------------------------------------------------------
+        if (valid_count > 0) begin
+            $display("==================================");
+            $display("TEST PASSED");
+            $display("valid_count = %0d", valid_count);
+            $display("==================================");
+        end
+        else begin
+            $display("==================================");
+            $display("TEST FAILED");
+            $display("No valid output detected");
+            $display("==================================");
+        end
+
+        $finish;
+    end
+
+endmodule