add processing_done signal for dma

rtl/controller_new/src/axi4l_reg_map_controller.sv

@@ -49,7 +49,8 @@ module axi4l_reg_map_controller #(
   
   output logic        rst_soft_o,
   input  logic        busy_i,
-  input  logic [7:0]  error_code_i
+  input  logic [7:0]  error_code_i,
+  input  logic        processing_done_i
 );
   import axi4l_reg_map_controller_pkg::*;
   localparam int unsigned N_REGS = CTRL_REG_MAP_N_REGS;
@@ -78,16 +79,18 @@ module axi4l_reg_map_controller #(
     reg_i = '0;
 
     reg_i[REG_STATUS][0] = busy_i;
+    reg_i[REG_STATUS][1] = processing_done_i;
 
-    reg_i[REG_STATUS][1] = desc_read_dma_busy_i;
-    reg_i[REG_STATUS][2] = desc_write_dma_busy_i;
-    reg_i[REG_STATUS][3] = status_read_dma_busy_i;
-    reg_i[REG_STATUS][4] = status_write_dma_busy_i;
 
-    reg_i[REG_STATUS][5] = desc_read_dma_hs_i;
+    reg_i[REG_STATUS][2] = desc_read_dma_busy_i;
-    reg_i[REG_STATUS][6] = desc_write_dma_hs_i;
+    reg_i[REG_STATUS][3] = desc_write_dma_busy_i;
-    reg_i[REG_STATUS][7] = status_read_dma_hs_i;
+    reg_i[REG_STATUS][4] = status_read_dma_busy_i;
-    reg_i[REG_STATUS][8] = status_write_dma_hs_i;
+    reg_i[REG_STATUS][5] = status_write_dma_busy_i;
+
+    reg_i[REG_STATUS][6] = desc_read_dma_hs_i;
+    reg_i[REG_STATUS][7] = desc_write_dma_hs_i;
+    reg_i[REG_STATUS][8] = status_read_dma_hs_i;
+    reg_i[REG_STATUS][9] = status_write_dma_hs_i;
 
     reg_i[REG_ERROR][7:0] = error_code_i;
 

rtl/controller_new/src/axi4l_reg_map_controller_pkg.sv

@@ -63,6 +63,7 @@ AXI write descriptor input and AXI write descriptor status output configuration
     6 : REG_BIT_RO,
     7 : REG_BIT_RO,
     8 : REG_BIT_RO,
+    9 : REG_BIT_RO,
     default: REG_BIT_RSVD
   },
 

rtl/controller_new/src/controller.sv

@@ -10,6 +10,10 @@ module control #(
 
     // adc_clk_in domain
     input  logic                       finish,
+
+    input  logic                       accum_done,
+    output logic                       accum_done_out,
+
     input  logic [159:0]               cfg_bus_input,
     input  logic                       cfg_bus_valid,
     input  logic                       start,
@@ -156,6 +160,21 @@ module control #(
         end
     end
 
+            // accum_done event: ADC -> cntrl via CDC
+    logic accum_done_meta, accum_done_sync;
+
+    always_ff @(posedge ctrl_clk or posedge ctrl_rst) begin
+        if (ctrl_rst) begin
+            accum_done_meta   <= 1'b0;
+            accum_done_sync   <= 1'b0;
+            accum_done_sync_d <= 1'b0;
+        end else begin
+            accum_done_meta   <= accum_done;
+            accum_done_sync   <= accum_done_meta;
+            accum_done_out <= accum_done_sync;
+        end
+    end
+
     logic [159:0] cfg_bus;
 
     always_ff @(posedge ctrl_clk or posedge ctrl_rst) begin

rtl/controller_new/src/controller_wrapper_axil.sv

@@ -16,7 +16,9 @@ parameter int unsigned DAC_DATA_WIDTH     = 12
     axi4l_if.slave                     s_axil,
 
     // adc_clk_in domain
-    input  logic                       finish,
+    input  logic                       workflow_done,
+    input  logic                       processing_done,
+
     output logic [31:0]                adc_window_size,
 
     // dac_clk_in domain outputs
@@ -52,6 +54,9 @@ parameter int unsigned DAC_DATA_WIDTH     = 12
     logic desc_read_dma_busy, desc_write_dma_busy, status_read_dma_busy, status_write_dma_busy;
     logic desc_read_dma_hs, desc_write_dma_hs, status_read_dma_hs, status_write_dma_hs;
 
+    logic processing_done_sync;
+
+
     axi4l_reg_map_controller #(
         .ADDR_W(ADDR_W),
         .DATA_W(DATA_W),
@@ -75,6 +80,9 @@ parameter int unsigned DAC_DATA_WIDTH     = 12
         .busy_i(busy),
         .error_code_i(error_code),
 
+    // ACCUMULATOR STATUS
+        .processing_done_i(processing_done_sync)
+
     // CONTROLLER DMA
         .send_desc_read_o(send_desc_read),
         .send_desc_write_o(send_desc_write),
@@ -126,7 +134,9 @@ parameter int unsigned DAC_DATA_WIDTH     = 12
         .adc_clk_in(adc_clk_in),
         .rst_n(rst_n),
         .rst_soft(rst_soft),
-        .finish(finish),
+        .finish(workflow_done),
+        .accum_done(processing_done),
+        .accum_done_out(processing_done_sync),
         .cfg_bus_input(cfg_bus),
         .cfg_bus_valid(cfg_bus_valid),
         .start(start),