add processing_done signal for dma

rtl/controller_new/src/controller.sv

@@ -10,6 +10,10 @@ module control #(
 
     // adc_clk_in domain
     input  logic                       finish,
+
+    input  logic                       accum_done,
+    output logic                       accum_done_out,
+
     input  logic [159:0]               cfg_bus_input,
     input  logic                       cfg_bus_valid,
     input  logic                       start,
@@ -156,6 +160,21 @@ module control #(
         end
     end
 
+            // accum_done event: ADC -> cntrl via CDC
+    logic accum_done_meta, accum_done_sync;
+
+    always_ff @(posedge ctrl_clk or posedge ctrl_rst) begin
+        if (ctrl_rst) begin
+            accum_done_meta   <= 1'b0;
+            accum_done_sync   <= 1'b0;
+            accum_done_sync_d <= 1'b0;
+        end else begin
+            accum_done_meta   <= accum_done;
+            accum_done_sync   <= accum_done_meta;
+            accum_done_out <= accum_done_sync;
+        end
+    end
+
     logic [159:0] cfg_bus;
 
     always_ff @(posedge ctrl_clk or posedge ctrl_rst) begin