debugging sv test for new reflectometer
This commit is contained in:
otroubi
+306
-133
@@ -1,5 +1,7 @@
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`timescale 1ns / 1ps
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import dma_reg_pkg::*;
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`define MEASURE_CLK(clk, period) \
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begin \
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realtime t1, t2; \
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@@ -59,6 +61,76 @@ module reflectometer_tb;
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realtime CLK_ADC_PERIOD;
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realtime CLK_DAC_PERIOD;
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// AXI
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logic [AXI_ID_WIDTH-1:0] s_axi_awid;
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logic [dma_reg_pkg::AXI_ADDR_WIDTH-1:0] s_axi_awaddr;
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logic [7:0] s_axi_awlen;
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logic [2:0] s_axi_awsize;
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logic [1:0] s_axi_awburst;
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logic s_axi_awlock;
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logic [3:0] s_axi_awcache;
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logic [2:0] s_axi_awprot;
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logic [3:0] s_axi_awqos;
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logic [3:0] s_axi_awregion;
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logic [AXI_USER_WIDTH-1:0] s_axi_awuser;
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logic s_axi_awvalid;
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logic s_axi_awready;
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logic [AXI_DATA_WIDTH-1:0] s_axi_wdata;
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logic [AXI_DATA_WIDTH/8-1:0] s_axi_wstrb;
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logic s_axi_wlast;
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logic [AXI_USER_WIDTH-1:0] s_axi_wuser;
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logic s_axi_wvalid;
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logic s_axi_wready;
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logic [AXI_ID_WIDTH-1:0] s_axi_bid;
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logic [1:0] s_axi_bresp;
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logic [AXI_USER_WIDTH-1:0] s_axi_buser;
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logic s_axi_bvalid;
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logic s_axi_bready;
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logic [AXI_ID_WIDTH-1:0] s_axi_arid;
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logic [dma_reg_pkg::AXI_ADDR_WIDTH-1:0] s_axi_araddr;
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logic [7:0] s_axi_arlen;
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logic [2:0] s_axi_arsize;
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logic [1:0] s_axi_arburst;
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logic s_axi_arlock;
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logic [3:0] s_axi_arcache;
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logic [2:0] s_axi_arprot;
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logic [3:0] s_axi_arqos;
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logic [3:0] s_axi_arregion;
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logic [AXI_USER_WIDTH-1:0] s_axi_aruser;
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logic s_axi_arvalid;
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logic s_axi_arready;
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logic [AXI_ID_WIDTH-1:0] s_axi_rid;
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logic [AXI_DATA_WIDTH-1:0] s_axi_rdata;
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logic [1:0] s_axi_rresp;
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logic s_axi_rlast;
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logic [AXI_USER_WIDTH-1:0] s_axi_ruser;
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logic s_axi_rvalid;
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logic s_axi_rready;
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// AXIL
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logic [dma_reg_pkg::AXI_ADDR_WIDTH-1:0] s_axil_awaddr;
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logic [2:0] s_axil_awprot;
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logic s_axil_awvalid;
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logic s_axil_awready;
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logic [AXI_DATA_WIDTH-1:0] s_axil_wdata;
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logic [AXI_DATA_WIDTH/8-1:0] s_axil_wstrb;
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logic s_axil_wvalid;
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logic s_axil_wready;
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logic [1:0] s_axil_bresp;
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logic s_axil_bvalid;
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logic s_axil_bready;
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logic [dma_reg_pkg::AXI_ADDR_WIDTH-1:0] s_axil_araddr;
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logic [2:0] s_axil_arprot;
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logic s_axil_arvalid;
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logic s_axil_arready;
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logic [AXI_DATA_WIDTH-1:0] s_axil_rdata;
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logic [1:0] s_axil_rresp;
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logic s_axil_rvalid;
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logic s_axil_rready;
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//------------------------------------------------------------
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@@ -257,158 +329,259 @@ module reflectometer_tb;
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//------------------------------------------------------------
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// ����� ������ � AXI-Lite, AXI
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localparam int REG_CONTROL = 0;
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localparam int REG_STATUS = 1;
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localparam int REG_DAC_WIDTH = 2;
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localparam int REG_DAC_PERIOD = 3;
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localparam int REG_DAC_PULSE_NUM = 4;
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localparam int REG_DAC_PULSE_HEIGHT = 5;
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localparam int REG_ADC_PERIOD = 6;
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localparam int REG_WINDOW_SIZE = 7;
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localparam int REG_DESC_WRITE_ADDR = 13;
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localparam int REG_DESC_WRITE_LEN_TAG = 14;
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localparam int REG_STATUS_WRITE_LEN = 15;
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localparam int REG_STATUS_WRITE_CONFIG = 16;
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// REG_CONTROL pulse bits
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localparam int CTRL_START = 1 << 0;
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localparam int CTRL_RST_SOFT = 1 << 1;
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localparam int CTRL_CFG_BUS_VALID = 1 << 2;
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localparam int CTRL_SEND_DESC_READ = 1 << 3;
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localparam int CTRL_SEND_DESC_WRITE = 1 << 4;
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localparam int CTRL_TAKE_STATUS_READ = 1 << 5;
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localparam int CTRL_TAKE_STATUS_WRITE = 1 << 6;
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// REG_STATUS bits
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localparam int STATUS_BUSY = 1 << 0;
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localparam int STATUS_PROCESSING_DONE = 1 << 1;
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localparam int STATUS_DESC_READ_BUSY = 1 << 2;
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localparam int STATUS_DESC_WRITE_BUSY = 1 << 3;
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localparam int STATUS_STATUS_READ_BUSY = 1 << 4;
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localparam int STATUS_STATUS_WRITE_BUSY = 1 << 5;
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localparam int STATUS_DESC_READ_HS = 1 << 6;
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localparam int STATUS_DESC_WRITE_HS = 1 << 7;
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localparam int STATUS_STATUS_READ_HS = 1 << 8;
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localparam int STATUS_STATUS_WRITE_HS = 1 << 9;
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function automatic logic [31:0] reg_addr(input int index);
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return index * 4;
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endfunction
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task automatic axil_write(
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input logic [31:0] addr,
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input logic [31:0] data
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);
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begin
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// Write address channel
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@(posedge ctrl_clk);
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s_axil_awaddr <= addr;
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s_axil_awprot <= 3'b000;
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s_axil_awvalid <= 1'b1;
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// Write data channel
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s_axil_wdata <= data;
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s_axil_wstrb <= 4'b1111;
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s_axil_wvalid <= 1'b1;
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// AXI-Lite: address handshake
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while (!s_axil_awready)
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@(posedge ctrl_clk);
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// AXI-Lite: data handshake
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while (!s_axil_wready)
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@(posedge ctrl_clk);
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@(posedge ctrl_clk);
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s_axil_awvalid <= 1'b0;
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s_axil_wvalid <= 1'b0;
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// Write response
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s_axil_bready <= 1'b1;
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while (!s_axil_bvalid)
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@(posedge ctrl_clk);
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if (s_axil_bresp != 2'b00)
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$error( "[AXIL] Write response error: BRESP=%b", s_axil_bresp);
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@(posedge ctrl_clk);
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s_axil_bready <= 1'b0;
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$display( "[AXIL] WRITE addr=0x%08X data=0x%08X", addr, data);
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end
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endtask
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task automatic axil_read(
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input logic [31:0] addr,
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output logic [31:0] data
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);
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begin
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// Read address
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@(posedge ctrl_clk);
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s_axil_araddr <= addr;
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s_axil_arprot <= 3'b000;
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s_axil_arvalid <= 1'b1;
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while (!s_axil_arready)
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@(posedge ctrl_clk);
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@(posedge ctrl_clk);
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s_axil_arvalid <= 1'b0;
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// Read response
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s_axil_rready <= 1'b1;
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while (!s_axil_rvalid)
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@(posedge ctrl_clk);
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data = s_axil_rdata;
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if (s_axil_rresp != 2'b00)
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$error( "[AXIL] Read response error: RRESP=%b", s_axil_rresp );
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@(posedge ctrl_clk);
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s_axil_rready <= 1'b0;
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$display( "[AXIL] READ addr=0x%08X data=0x%08X", addr, data );
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end
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endtask
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task automatic write_reg(
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input int index,
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input logic [31:0] data
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);
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axil_write( reg_addr(index), data );
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endtask
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task automatic read_reg(
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input int index,
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output logic [31:0] data
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);
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axil_read( reg_addr(index), data );
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endtask
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// ����� ����������������
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task automatic configure_reflectometer(
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input int pulse_width,
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input int pulse_period,
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input int pulse_num,
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input int pulse_height,
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input int adc_period,
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input int window_size
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);
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begin
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$display("[TB] Configure reflectometer");
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write_reg( REG_DAC_WIDTH, pulse_width );
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write_reg( REG_DAC_PERIOD, pulse_period);
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write_reg( REG_DAC_PULSE_NUM, pulse_num );
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write_reg( REG_DAC_PULSE_HEIGHT, pulse_height );
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write_reg( REG_ADC_PERIOD, adc_period );
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write_reg( REG_WINDOW_SIZE, window_size );
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// CTRL_CFG_BUS_VALID
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write_reg(REG_CONTROL, CTRL_CFG_BUS_VALID);
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$display("[TB] Configuration sent");
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end
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endtask
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task automatic dut_start();
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begin
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write_reg( REG_CONTROL, CTRL_START);
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$display("[TB] START sent");
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end
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endtask
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task automatic dut_soft_reset();
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begin
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write_reg( REG_CONTROL, CTRL_RST_SOFT );
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$display("[TB] SOFT RESET sent");
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end
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endtask
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// ����� ��� ������ � DMA
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// Òàñêà êîíôèãóðàöèîííàÿ
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task automatic send_desc_write(
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input logic [31:0] addr,
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input logic [31:0] length_tag
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);
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begin
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write_reg( REG_DESC_WRITE_ADDR, addr );
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write_reg( REG_DESC_WRITE_LEN_TAG, length_tag);
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write_reg( REG_CONTROL, CTRL_SEND_DESC_WRITE);
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$display( "[TB] DMA WRITE descriptor: addr=0x%08X len_tag=%0d", addr, length_tag );
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end
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endtask
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task automatic dut_soft_reset(virtual axis_if#(8).tb vif);
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logic [7:0] tx_packet[];
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tx_packet = '{8'h0f};
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vif.master_send(tx_packet);
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endtask
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logic [31:0] dma_received_data[$];
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task automatic dut_start(virtual axis_if#(8).tb vif);
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logic [7:0] tx_packet[];
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tx_packet = '{8'hf0};
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vif.master_send(tx_packet);
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endtask
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task automatic axi_write_slave();
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logic [31:0] addr;
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logic [7:0] len;
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logic [31:0] data;
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task automatic dut_send_system_config(
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virtual axis_if#(8).tb vif,
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input logic [31:0] pulse_width,
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input logic [31:0] pulse_period,
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input logic [15:0] pulse_num,
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input logic [13:0] pulse_height, // achtung! p_height strictly must have 14 bits of width
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input logic [31:0] pulse_period_adc,
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input logic [31:0] window_size
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);
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// Ñîçäàåì âðåìåííûé ôèêñèðîâàííûé ìàññèâ è óïàêîâûâàåì âñ¸ îäíîé ñòðîêîé
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logic [7:0] tx_packet[];
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begin
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forever begin
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// WAIT AW
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@(posedge ctrl_clk);
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// Àõòóíã, 14-áèòíûé ÖÀÏ çàõàðäêîæåí
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if (DAC_DATA_WIDTH != 14)
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$warning("[WARNING] -dut_send_system_config- Default pulse height (DAC bitwidth) is equal to 14. Be aware, controller packet structure is coded for 14 bits");
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if (s_axi_awvalid) begin
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addr = s_axi_awaddr;
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len = s_axi_awlen;
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s_axi_awready <= 1'b1;
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tx_packet = '{
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8'h88, // Êîìàíäà
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pulse_width[7:0], pulse_width[15:8], pulse_width[23:16], pulse_width[31:24],
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pulse_period[7:0], pulse_period[15:8], pulse_period[23:16], pulse_period[31:24],
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pulse_num[7:0], pulse_num[15:8], pulse_height[7:0], 8'({2'b00, pulse_height[13:8]}),
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pulse_period_adc[7:0], pulse_period_adc[15:8], pulse_period_adc[23:16], pulse_period_adc[31:24]
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};
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$display(
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"[AXI] AW: addr=0x%08X len=%0d", addr, len );
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vif.master_send(tx_packet);
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@(posedge ctrl_clk);
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s_axi_awready <= 1'b0;
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// TODO remove for new controller
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window_size_port = window_size;
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endtask
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// RECEIVE W DATA
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for (int i = 0; i <= len; i++) begin
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s_axi_wready <= 1'b1;
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while (!s_axi_wvalid)
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@(posedge ctrl_clk);
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data = s_axi_wdata;
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dma_received_data.push_back(data);
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// Òàñêè ñáîðà ñòàòèñòèêè
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task automatic dut_read_output(
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virtual axis_if#(8).tb vif,
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input int sample_num,
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input int window_size,
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input bit randomize_recv_delays,
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output int output_data[]
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);
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logic [7:0] rx_packet[];
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logic [ACCUM_WIDTH-1:0] data_packet[];
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int numbers_per_packet = PACKET_SIZE/(ACCUM_WIDTH/8);
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int packet_num = $ceil(real'(sample_num / window_size) / real'(numbers_per_packet));
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int timeout_flag = 0;
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int packet_counter = 0;
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$display( "[AXI] W[%0d] = 0x%08X last=%b", i, data, s_axi_wlast );
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if (sample_num % window_size) begin
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$error("-dut_read_output- Sample_num must be multiple of window_size: %0d %% %0d = %0d", sample_num, window_size, sample_num % window_size);
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$finish;
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end
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data_packet = new[numbers_per_packet];
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output_data = new[numbers_per_packet * packet_num];
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// count send_request pulses (equal to number of packets)
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fork
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begin : packet_counter_proc
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forever begin
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@(posedge clk_eth_phy);
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if(send_request === 1)
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packet_counter++;
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end
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end
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join_none
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// Wait until reflectometer done sampling and averaging
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wait(processing_done == 1);
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// recv loop
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// åñëè ÷èñëî ïàêåòîâ ïðåâûøàåò çàëîæåííîå ïðåäðàññ÷èòàííîå çíà÷åíèå -- îøèáêà
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fork : recv_loop_proc
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begin
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// packet recv loop
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forever begin
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if (packet_counter > packet_num) begin
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$error("-dut_read_output- Packet overflow detected. Number of data packets exceeds expected amount of packets");
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$finish;
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end
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if (randomize_recv_delays)
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repeat($urandom_range(0, 500)) @(posedge clk_eth_phy);
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timeout_flag = 0;
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fork : receive_packet_timeout
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begin
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request_ready = 1;
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vif.slave_recv(rx_packet);
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request_ready = 0;
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end
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begin
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repeat(REQUEST_TIMEOUT) @(posedge clk_eth_phy);
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timeout_flag = 1;
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end
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join_any
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disable receive_packet_timeout;
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if (timeout_flag) begin
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$error("-dut_read_output- Timeout detected when receiving packet");
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$finish;
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end
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if (rx_packet.size() != PACKET_SIZE) begin
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$error("-dut_read_output- Wrong packet size received: %0d bytes received, %0d bytes expected", rx_packet.size(), PACKET_SIZE);
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$finish;
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end
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// unpack values
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data_packet = {<< byte {rx_packet}};
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data_packet = {<< ACCUM_WIDTH {data_packet}};
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// copy and convert values
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for (int j = 0; j < data_packet.size(); j++) begin
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output_data[(packet_counter-1) * data_packet.size() + j] = int'(data_packet[j]);
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end
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@(posedge ctrl_clk);
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s_axi_wready <= 1'b0;
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end
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end
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begin
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// IP workflow completion event
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wait(workflow_done == 1);
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end
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join_any
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disable recv_loop_proc;
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disable packet_counter_proc;
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||||
// WRITE RESPONSE
|
||||
s_axi_bresp <= 2'b00;
|
||||
s_axi_bvalid <= 1'b1;
|
||||
|
||||
if (packet_counter != packet_num) begin
|
||||
$error("-dut_read_output- Wrong number of packets received: %0d received, %0d expected", packet_counter, packet_num);
|
||||
$finish;
|
||||
while (!s_axi_bready)
|
||||
@(posedge ctrl_clk);
|
||||
|
||||
@(posedge ctrl_clk);
|
||||
s_axi_bvalid <= 1'b0;
|
||||
|
||||
end
|
||||
end
|
||||
|
||||
wait(processing_done == 0);
|
||||
|
||||
endtask
|
||||
end
|
||||
endtask
|
||||
|
||||
//------------------------------------------------------------
|
||||
// ������� � ����� ��� ����������� ��������
|
||||
|
||||
Reference in New Issue
Block a user