TOPLEVEL_LANG = verilog
SIM ?= questa
WAVES = 1
WLF_FILE := $(SIM_BUILD)/waves.wlf

PWD := $(shell pwd)


RTL_DIR = $(PWD)/../../src
RTL_ACCUM_DIR = $(PWD)/../../src/accum/src
RTL_GENERATOR_DIR = $(PWD)/../../src/generator/src
RTL_SAMPLER_DIR = $(PWD)/../../src/sampler/src
RTL_CLK_DIR = $(PWD)/../../src/clk_ctrl_wiz/clk_wiz_0
LIBS_DIR = $(PWD)/../../../../external/rtl_libs


VERILOG_SOURCES += $(LIBS_DIR)/axi/rtl/axi_pkg.sv
VERILOG_SOURCES += $(RTL_DIR)/dma_reg_pkg.sv
VERILOG_SOURCES += $(LIBS_DIR)/axi/rtl/axi_if.sv
VERILOG_SOURCES += $(LIBS_DIR)/axi/rtl/axis_if.sv
VERILOG_SOURCES += $(LIBS_DIR)/axi/rtl/axis_if_to_flat.sv
VERILOG_SOURCES += $(LIBS_DIR)/axi/rtl/axi4l_flat_to_if.sv
VERILOG_SOURCES += $(LIBS_DIR)/axi/axi_reg/axi4l_reg_map.sv
VERILOG_SOURCES += $(LIBS_DIR)/external/verilog-axi/rtl/axi_dma_rd.v
VERILOG_SOURCES += $(LIBS_DIR)/external/verilog-axi/rtl/axi_dma_wr.v
VERILOG_SOURCES += $(LIBS_DIR)/external/verilog-axi/rtl/axi_dma.v
VERILOG_SOURCES += $(LIBS_DIR)/external/verilog-axi/rtl/axi_ram.v
VERILOG_SOURCES += $(RTL_DIR)/axi_ram_wrapper.sv
VERILOG_SOURCES += $(RTL_DIR)/controller.sv
VERILOG_SOURCES += $(RTL_DIR)/dma_controller.sv
VERILOG_SOURCES += $(RTL_DIR)/shaper_axis_desc.sv
VERILOG_SOURCES += $(RTL_DIR)/shaper_axis_status.sv
VERILOG_SOURCES += $(RTL_DIR)/controller_wrapper_axil.sv
VERILOG_SOURCES += $(RTL_DIR)/axi4l_reg_map_controller_pkg.sv
VERILOG_SOURCES += $(RTL_DIR)/axis_defaults_helper.sv
VERILOG_SOURCES += $(RTL_DIR)/axi4l_reg_map_controller.sv
VERILOG_SOURCES += $(RTL_DIR)/axi_dma_wrapper_if.sv
VERILOG_SOURCES += $(RTL_DIR)/wrapper_controller_dma.sv
VERILOG_SOURCES += $(RTL_ACCUM_DIR)/adder.sv
VERILOG_SOURCES += $(RTL_ACCUM_DIR)/out_axis_fifo.sv
VERILOG_SOURCES += $(RTL_ACCUM_DIR)/accum.sv
VERILOG_SOURCES += $(RTL_ACCUM_DIR)/accum_top.sv
VERILOG_SOURCES += $(RTL_GENERATOR_DIR)/generator.sv
VERILOG_SOURCES += $(RTL_SAMPLER_DIR)/sampler.sv
VERILOG_SOURCES += $(RTL_CLK_DIR)/clk_wiz_0_clk_wiz.v
VERILOG_SOURCES += $(RTL_CLK_DIR)/clk_wiz_0.v

VERILOG_SOURCES += $(PWD)/adc_model.sv
VERILOG_SOURCES += $(PWD)/dac_model.sv
VERILOG_SOURCES += $(PWD)/reflectometer_ip.sv
VERILOG_SOURCES += $(PWD)/reflectometer_and_dma_wrapper.sv
VERILOG_SOURCES += $(PWD)/tb_full_reflectometer.sv
VERILOG_SOURCES += /mnt/c/Xilinx/Vivado/2021.2/data/verilog/src/glbl.v

TOPLEVEL = tb_full_reflectometer
MODULE = full_reflectometer_test


ifeq ($(SIM),questa)
    SIM_ARGS += -L xpm -L unisim
    SIM_ARGS += work.glbl
    SIM_ARGS += -wlf $(WLF_FILE)
    COMPILE_ARGS += +acc
endif


include $(shell cocotb-config --makefiles)/Makefile.sim
