ARM GAS /tmp/ccYgfTud.s page 1 1 .cpu cortex-m7 2 .arch armv7e-m 3 .fpu fpv5-d16 4 .eabi_attribute 28, 1 5 .eabi_attribute 20, 1 6 .eabi_attribute 21, 1 7 .eabi_attribute 23, 3 8 .eabi_attribute 24, 1 9 .eabi_attribute 25, 1 10 .eabi_attribute 26, 1 11 .eabi_attribute 30, 1 12 .eabi_attribute 34, 1 13 .eabi_attribute 18, 4 14 .file "main.c" 15 .text 16 .Ltext0: 17 .cfi_sections .debug_frame 18 .file 1 "Src/main.c" 19 .section .text.NVIC_EncodePriority,"ax",%progbits 20 .align 1 21 .syntax unified 22 .thumb 23 .thumb_func 25 NVIC_EncodePriority: 26 .LVL0: 27 .LFB113: 28 .file 2 "Drivers/CMSIS/Include/core_cm7.h" 1:Drivers/CMSIS/Include/core_cm7.h **** /**************************************************************************//** 2:Drivers/CMSIS/Include/core_cm7.h **** * @file core_cm7.h 3:Drivers/CMSIS/Include/core_cm7.h **** * @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File 4:Drivers/CMSIS/Include/core_cm7.h **** * @version V5.0.8 5:Drivers/CMSIS/Include/core_cm7.h **** * @date 04. June 2018 6:Drivers/CMSIS/Include/core_cm7.h **** ******************************************************************************/ 7:Drivers/CMSIS/Include/core_cm7.h **** /* 8:Drivers/CMSIS/Include/core_cm7.h **** * Copyright (c) 2009-2018 Arm Limited. All rights reserved. 9:Drivers/CMSIS/Include/core_cm7.h **** * 10:Drivers/CMSIS/Include/core_cm7.h **** * SPDX-License-Identifier: Apache-2.0 11:Drivers/CMSIS/Include/core_cm7.h **** * 12:Drivers/CMSIS/Include/core_cm7.h **** * Licensed under the Apache License, Version 2.0 (the License); you may 13:Drivers/CMSIS/Include/core_cm7.h **** * not use this file except in compliance with the License. 14:Drivers/CMSIS/Include/core_cm7.h **** * You may obtain a copy of the License at 15:Drivers/CMSIS/Include/core_cm7.h **** * 16:Drivers/CMSIS/Include/core_cm7.h **** * www.apache.org/licenses/LICENSE-2.0 17:Drivers/CMSIS/Include/core_cm7.h **** * 18:Drivers/CMSIS/Include/core_cm7.h **** * Unless required by applicable law or agreed to in writing, software 19:Drivers/CMSIS/Include/core_cm7.h **** * distributed under the License is distributed on an AS IS BASIS, WITHOUT 20:Drivers/CMSIS/Include/core_cm7.h **** * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 21:Drivers/CMSIS/Include/core_cm7.h **** * See the License for the specific language governing permissions and 22:Drivers/CMSIS/Include/core_cm7.h **** * limitations under the License. 23:Drivers/CMSIS/Include/core_cm7.h **** */ 24:Drivers/CMSIS/Include/core_cm7.h **** 25:Drivers/CMSIS/Include/core_cm7.h **** #if defined ( __ICCARM__ ) 26:Drivers/CMSIS/Include/core_cm7.h **** #pragma system_include /* treat file as system include file for MISRA check */ 27:Drivers/CMSIS/Include/core_cm7.h **** #elif defined (__clang__) 28:Drivers/CMSIS/Include/core_cm7.h **** #pragma clang system_header /* treat file as system include file */ 29:Drivers/CMSIS/Include/core_cm7.h **** #endif 30:Drivers/CMSIS/Include/core_cm7.h **** ARM GAS /tmp/ccYgfTud.s page 2 31:Drivers/CMSIS/Include/core_cm7.h **** #ifndef __CORE_CM7_H_GENERIC 32:Drivers/CMSIS/Include/core_cm7.h **** #define __CORE_CM7_H_GENERIC 33:Drivers/CMSIS/Include/core_cm7.h **** 34:Drivers/CMSIS/Include/core_cm7.h **** #include 35:Drivers/CMSIS/Include/core_cm7.h **** 36:Drivers/CMSIS/Include/core_cm7.h **** #ifdef __cplusplus 37:Drivers/CMSIS/Include/core_cm7.h **** extern "C" { 38:Drivers/CMSIS/Include/core_cm7.h **** #endif 39:Drivers/CMSIS/Include/core_cm7.h **** 40:Drivers/CMSIS/Include/core_cm7.h **** /** 41:Drivers/CMSIS/Include/core_cm7.h **** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions 42:Drivers/CMSIS/Include/core_cm7.h **** CMSIS violates the following MISRA-C:2004 rules: 43:Drivers/CMSIS/Include/core_cm7.h **** 44:Drivers/CMSIS/Include/core_cm7.h **** \li Required Rule 8.5, object/function definition in header file.
45:Drivers/CMSIS/Include/core_cm7.h **** Function definitions in header files are used to allow 'inlining'. 46:Drivers/CMSIS/Include/core_cm7.h **** 47:Drivers/CMSIS/Include/core_cm7.h **** \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
48:Drivers/CMSIS/Include/core_cm7.h **** Unions are used for effective representation of core registers. 49:Drivers/CMSIS/Include/core_cm7.h **** 50:Drivers/CMSIS/Include/core_cm7.h **** \li Advisory Rule 19.7, Function-like macro defined.
51:Drivers/CMSIS/Include/core_cm7.h **** Function-like macros are used to allow more efficient code. 52:Drivers/CMSIS/Include/core_cm7.h **** */ 53:Drivers/CMSIS/Include/core_cm7.h **** 54:Drivers/CMSIS/Include/core_cm7.h **** 55:Drivers/CMSIS/Include/core_cm7.h **** /******************************************************************************* 56:Drivers/CMSIS/Include/core_cm7.h **** * CMSIS definitions 57:Drivers/CMSIS/Include/core_cm7.h **** ******************************************************************************/ 58:Drivers/CMSIS/Include/core_cm7.h **** /** 59:Drivers/CMSIS/Include/core_cm7.h **** \ingroup Cortex_M7 60:Drivers/CMSIS/Include/core_cm7.h **** @{ 61:Drivers/CMSIS/Include/core_cm7.h **** */ 62:Drivers/CMSIS/Include/core_cm7.h **** 63:Drivers/CMSIS/Include/core_cm7.h **** #include "cmsis_version.h" 64:Drivers/CMSIS/Include/core_cm7.h **** 65:Drivers/CMSIS/Include/core_cm7.h **** /* CMSIS CM7 definitions */ 66:Drivers/CMSIS/Include/core_cm7.h **** #define __CM7_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:1 67:Drivers/CMSIS/Include/core_cm7.h **** #define __CM7_CMSIS_VERSION_SUB ( __CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0 68:Drivers/CMSIS/Include/core_cm7.h **** #define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16U) | \ 69:Drivers/CMSIS/Include/core_cm7.h **** __CM7_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS 70:Drivers/CMSIS/Include/core_cm7.h **** 71:Drivers/CMSIS/Include/core_cm7.h **** #define __CORTEX_M (7U) /*!< Cortex-M Core */ 72:Drivers/CMSIS/Include/core_cm7.h **** 73:Drivers/CMSIS/Include/core_cm7.h **** /** __FPU_USED indicates whether an FPU is used or not. 74:Drivers/CMSIS/Include/core_cm7.h **** For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and fun 75:Drivers/CMSIS/Include/core_cm7.h **** */ 76:Drivers/CMSIS/Include/core_cm7.h **** #if defined ( __CC_ARM ) 77:Drivers/CMSIS/Include/core_cm7.h **** #if defined __TARGET_FPU_VFP 78:Drivers/CMSIS/Include/core_cm7.h **** #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) 79:Drivers/CMSIS/Include/core_cm7.h **** #define __FPU_USED 1U 80:Drivers/CMSIS/Include/core_cm7.h **** #else 81:Drivers/CMSIS/Include/core_cm7.h **** #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT) 82:Drivers/CMSIS/Include/core_cm7.h **** #define __FPU_USED 0U 83:Drivers/CMSIS/Include/core_cm7.h **** #endif 84:Drivers/CMSIS/Include/core_cm7.h **** #else 85:Drivers/CMSIS/Include/core_cm7.h **** #define __FPU_USED 0U 86:Drivers/CMSIS/Include/core_cm7.h **** #endif 87:Drivers/CMSIS/Include/core_cm7.h **** ARM GAS /tmp/ccYgfTud.s page 3 88:Drivers/CMSIS/Include/core_cm7.h **** #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) 89:Drivers/CMSIS/Include/core_cm7.h **** #if defined __ARM_PCS_VFP 90:Drivers/CMSIS/Include/core_cm7.h **** #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) 91:Drivers/CMSIS/Include/core_cm7.h **** #define __FPU_USED 1U 92:Drivers/CMSIS/Include/core_cm7.h **** #else 93:Drivers/CMSIS/Include/core_cm7.h **** #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESEN 94:Drivers/CMSIS/Include/core_cm7.h **** #define __FPU_USED 0U 95:Drivers/CMSIS/Include/core_cm7.h **** #endif 96:Drivers/CMSIS/Include/core_cm7.h **** #else 97:Drivers/CMSIS/Include/core_cm7.h **** #define __FPU_USED 0U 98:Drivers/CMSIS/Include/core_cm7.h **** #endif 99:Drivers/CMSIS/Include/core_cm7.h **** 100:Drivers/CMSIS/Include/core_cm7.h **** #elif defined ( __GNUC__ ) 101:Drivers/CMSIS/Include/core_cm7.h **** #if defined (__VFP_FP__) && !defined(__SOFTFP__) 102:Drivers/CMSIS/Include/core_cm7.h **** #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) 103:Drivers/CMSIS/Include/core_cm7.h **** #define __FPU_USED 1U 104:Drivers/CMSIS/Include/core_cm7.h **** #else 105:Drivers/CMSIS/Include/core_cm7.h **** #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT) 106:Drivers/CMSIS/Include/core_cm7.h **** #define __FPU_USED 0U 107:Drivers/CMSIS/Include/core_cm7.h **** #endif 108:Drivers/CMSIS/Include/core_cm7.h **** #else 109:Drivers/CMSIS/Include/core_cm7.h **** #define __FPU_USED 0U 110:Drivers/CMSIS/Include/core_cm7.h **** #endif 111:Drivers/CMSIS/Include/core_cm7.h **** 112:Drivers/CMSIS/Include/core_cm7.h **** #elif defined ( __ICCARM__ ) 113:Drivers/CMSIS/Include/core_cm7.h **** #if defined __ARMVFP__ 114:Drivers/CMSIS/Include/core_cm7.h **** #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) 115:Drivers/CMSIS/Include/core_cm7.h **** #define __FPU_USED 1U 116:Drivers/CMSIS/Include/core_cm7.h **** #else 117:Drivers/CMSIS/Include/core_cm7.h **** #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT) 118:Drivers/CMSIS/Include/core_cm7.h **** #define __FPU_USED 0U 119:Drivers/CMSIS/Include/core_cm7.h **** #endif 120:Drivers/CMSIS/Include/core_cm7.h **** #else 121:Drivers/CMSIS/Include/core_cm7.h **** #define __FPU_USED 0U 122:Drivers/CMSIS/Include/core_cm7.h **** #endif 123:Drivers/CMSIS/Include/core_cm7.h **** 124:Drivers/CMSIS/Include/core_cm7.h **** #elif defined ( __TI_ARM__ ) 125:Drivers/CMSIS/Include/core_cm7.h **** #if defined __TI_VFP_SUPPORT__ 126:Drivers/CMSIS/Include/core_cm7.h **** #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) 127:Drivers/CMSIS/Include/core_cm7.h **** #define __FPU_USED 1U 128:Drivers/CMSIS/Include/core_cm7.h **** #else 129:Drivers/CMSIS/Include/core_cm7.h **** #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT) 130:Drivers/CMSIS/Include/core_cm7.h **** #define __FPU_USED 0U 131:Drivers/CMSIS/Include/core_cm7.h **** #endif 132:Drivers/CMSIS/Include/core_cm7.h **** #else 133:Drivers/CMSIS/Include/core_cm7.h **** #define __FPU_USED 0U 134:Drivers/CMSIS/Include/core_cm7.h **** #endif 135:Drivers/CMSIS/Include/core_cm7.h **** 136:Drivers/CMSIS/Include/core_cm7.h **** #elif defined ( __TASKING__ ) 137:Drivers/CMSIS/Include/core_cm7.h **** #if defined __FPU_VFP__ 138:Drivers/CMSIS/Include/core_cm7.h **** #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) 139:Drivers/CMSIS/Include/core_cm7.h **** #define __FPU_USED 1U 140:Drivers/CMSIS/Include/core_cm7.h **** #else 141:Drivers/CMSIS/Include/core_cm7.h **** #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT) 142:Drivers/CMSIS/Include/core_cm7.h **** #define __FPU_USED 0U 143:Drivers/CMSIS/Include/core_cm7.h **** #endif 144:Drivers/CMSIS/Include/core_cm7.h **** #else ARM GAS /tmp/ccYgfTud.s page 4 145:Drivers/CMSIS/Include/core_cm7.h **** #define __FPU_USED 0U 146:Drivers/CMSIS/Include/core_cm7.h **** #endif 147:Drivers/CMSIS/Include/core_cm7.h **** 148:Drivers/CMSIS/Include/core_cm7.h **** #elif defined ( __CSMC__ ) 149:Drivers/CMSIS/Include/core_cm7.h **** #if ( __CSMC__ & 0x400U) 150:Drivers/CMSIS/Include/core_cm7.h **** #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) 151:Drivers/CMSIS/Include/core_cm7.h **** #define __FPU_USED 1U 152:Drivers/CMSIS/Include/core_cm7.h **** #else 153:Drivers/CMSIS/Include/core_cm7.h **** #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT) 154:Drivers/CMSIS/Include/core_cm7.h **** #define __FPU_USED 0U 155:Drivers/CMSIS/Include/core_cm7.h **** #endif 156:Drivers/CMSIS/Include/core_cm7.h **** #else 157:Drivers/CMSIS/Include/core_cm7.h **** #define __FPU_USED 0U 158:Drivers/CMSIS/Include/core_cm7.h **** #endif 159:Drivers/CMSIS/Include/core_cm7.h **** 160:Drivers/CMSIS/Include/core_cm7.h **** #endif 161:Drivers/CMSIS/Include/core_cm7.h **** 162:Drivers/CMSIS/Include/core_cm7.h **** #include "cmsis_compiler.h" /* CMSIS compiler specific defines */ 163:Drivers/CMSIS/Include/core_cm7.h **** 164:Drivers/CMSIS/Include/core_cm7.h **** 165:Drivers/CMSIS/Include/core_cm7.h **** #ifdef __cplusplus 166:Drivers/CMSIS/Include/core_cm7.h **** } 167:Drivers/CMSIS/Include/core_cm7.h **** #endif 168:Drivers/CMSIS/Include/core_cm7.h **** 169:Drivers/CMSIS/Include/core_cm7.h **** #endif /* __CORE_CM7_H_GENERIC */ 170:Drivers/CMSIS/Include/core_cm7.h **** 171:Drivers/CMSIS/Include/core_cm7.h **** #ifndef __CMSIS_GENERIC 172:Drivers/CMSIS/Include/core_cm7.h **** 173:Drivers/CMSIS/Include/core_cm7.h **** #ifndef __CORE_CM7_H_DEPENDANT 174:Drivers/CMSIS/Include/core_cm7.h **** #define __CORE_CM7_H_DEPENDANT 175:Drivers/CMSIS/Include/core_cm7.h **** 176:Drivers/CMSIS/Include/core_cm7.h **** #ifdef __cplusplus 177:Drivers/CMSIS/Include/core_cm7.h **** extern "C" { 178:Drivers/CMSIS/Include/core_cm7.h **** #endif 179:Drivers/CMSIS/Include/core_cm7.h **** 180:Drivers/CMSIS/Include/core_cm7.h **** /* check device defines and use defaults */ 181:Drivers/CMSIS/Include/core_cm7.h **** #if defined __CHECK_DEVICE_DEFINES 182:Drivers/CMSIS/Include/core_cm7.h **** #ifndef __CM7_REV 183:Drivers/CMSIS/Include/core_cm7.h **** #define __CM7_REV 0x0000U 184:Drivers/CMSIS/Include/core_cm7.h **** #warning "__CM7_REV not defined in device header file; using default!" 185:Drivers/CMSIS/Include/core_cm7.h **** #endif 186:Drivers/CMSIS/Include/core_cm7.h **** 187:Drivers/CMSIS/Include/core_cm7.h **** #ifndef __FPU_PRESENT 188:Drivers/CMSIS/Include/core_cm7.h **** #define __FPU_PRESENT 0U 189:Drivers/CMSIS/Include/core_cm7.h **** #warning "__FPU_PRESENT not defined in device header file; using default!" 190:Drivers/CMSIS/Include/core_cm7.h **** #endif 191:Drivers/CMSIS/Include/core_cm7.h **** 192:Drivers/CMSIS/Include/core_cm7.h **** #ifndef __MPU_PRESENT 193:Drivers/CMSIS/Include/core_cm7.h **** #define __MPU_PRESENT 0U 194:Drivers/CMSIS/Include/core_cm7.h **** #warning "__MPU_PRESENT not defined in device header file; using default!" 195:Drivers/CMSIS/Include/core_cm7.h **** #endif 196:Drivers/CMSIS/Include/core_cm7.h **** 197:Drivers/CMSIS/Include/core_cm7.h **** #ifndef __ICACHE_PRESENT 198:Drivers/CMSIS/Include/core_cm7.h **** #define __ICACHE_PRESENT 0U 199:Drivers/CMSIS/Include/core_cm7.h **** #warning "__ICACHE_PRESENT not defined in device header file; using default!" 200:Drivers/CMSIS/Include/core_cm7.h **** #endif 201:Drivers/CMSIS/Include/core_cm7.h **** ARM GAS /tmp/ccYgfTud.s page 5 202:Drivers/CMSIS/Include/core_cm7.h **** #ifndef __DCACHE_PRESENT 203:Drivers/CMSIS/Include/core_cm7.h **** #define __DCACHE_PRESENT 0U 204:Drivers/CMSIS/Include/core_cm7.h **** #warning "__DCACHE_PRESENT not defined in device header file; using default!" 205:Drivers/CMSIS/Include/core_cm7.h **** #endif 206:Drivers/CMSIS/Include/core_cm7.h **** 207:Drivers/CMSIS/Include/core_cm7.h **** #ifndef __DTCM_PRESENT 208:Drivers/CMSIS/Include/core_cm7.h **** #define __DTCM_PRESENT 0U 209:Drivers/CMSIS/Include/core_cm7.h **** #warning "__DTCM_PRESENT not defined in device header file; using default!" 210:Drivers/CMSIS/Include/core_cm7.h **** #endif 211:Drivers/CMSIS/Include/core_cm7.h **** 212:Drivers/CMSIS/Include/core_cm7.h **** #ifndef __NVIC_PRIO_BITS 213:Drivers/CMSIS/Include/core_cm7.h **** #define __NVIC_PRIO_BITS 3U 214:Drivers/CMSIS/Include/core_cm7.h **** #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" 215:Drivers/CMSIS/Include/core_cm7.h **** #endif 216:Drivers/CMSIS/Include/core_cm7.h **** 217:Drivers/CMSIS/Include/core_cm7.h **** #ifndef __Vendor_SysTickConfig 218:Drivers/CMSIS/Include/core_cm7.h **** #define __Vendor_SysTickConfig 0U 219:Drivers/CMSIS/Include/core_cm7.h **** #warning "__Vendor_SysTickConfig not defined in device header file; using default!" 220:Drivers/CMSIS/Include/core_cm7.h **** #endif 221:Drivers/CMSIS/Include/core_cm7.h **** #endif 222:Drivers/CMSIS/Include/core_cm7.h **** 223:Drivers/CMSIS/Include/core_cm7.h **** /* IO definitions (access restrictions to peripheral registers) */ 224:Drivers/CMSIS/Include/core_cm7.h **** /** 225:Drivers/CMSIS/Include/core_cm7.h **** \defgroup CMSIS_glob_defs CMSIS Global Defines 226:Drivers/CMSIS/Include/core_cm7.h **** 227:Drivers/CMSIS/Include/core_cm7.h **** IO Type Qualifiers are used 228:Drivers/CMSIS/Include/core_cm7.h **** \li to specify the access to peripheral variables. 229:Drivers/CMSIS/Include/core_cm7.h **** \li for automatic generation of peripheral register debug information. 230:Drivers/CMSIS/Include/core_cm7.h **** */ 231:Drivers/CMSIS/Include/core_cm7.h **** #ifdef __cplusplus 232:Drivers/CMSIS/Include/core_cm7.h **** #define __I volatile /*!< Defines 'read only' permissions */ 233:Drivers/CMSIS/Include/core_cm7.h **** #else 234:Drivers/CMSIS/Include/core_cm7.h **** #define __I volatile const /*!< Defines 'read only' permissions */ 235:Drivers/CMSIS/Include/core_cm7.h **** #endif 236:Drivers/CMSIS/Include/core_cm7.h **** #define __O volatile /*!< Defines 'write only' permissions */ 237:Drivers/CMSIS/Include/core_cm7.h **** #define __IO volatile /*!< Defines 'read / write' permissions */ 238:Drivers/CMSIS/Include/core_cm7.h **** 239:Drivers/CMSIS/Include/core_cm7.h **** /* following defines should be used for structure members */ 240:Drivers/CMSIS/Include/core_cm7.h **** #define __IM volatile const /*! Defines 'read only' structure member permissions */ 241:Drivers/CMSIS/Include/core_cm7.h **** #define __OM volatile /*! Defines 'write only' structure member permissions */ 242:Drivers/CMSIS/Include/core_cm7.h **** #define __IOM volatile /*! Defines 'read / write' structure member permissions */ 243:Drivers/CMSIS/Include/core_cm7.h **** 244:Drivers/CMSIS/Include/core_cm7.h **** /*@} end of group Cortex_M7 */ 245:Drivers/CMSIS/Include/core_cm7.h **** 246:Drivers/CMSIS/Include/core_cm7.h **** 247:Drivers/CMSIS/Include/core_cm7.h **** 248:Drivers/CMSIS/Include/core_cm7.h **** /******************************************************************************* 249:Drivers/CMSIS/Include/core_cm7.h **** * Register Abstraction 250:Drivers/CMSIS/Include/core_cm7.h **** Core Register contain: 251:Drivers/CMSIS/Include/core_cm7.h **** - Core Register 252:Drivers/CMSIS/Include/core_cm7.h **** - Core NVIC Register 253:Drivers/CMSIS/Include/core_cm7.h **** - Core SCB Register 254:Drivers/CMSIS/Include/core_cm7.h **** - Core SysTick Register 255:Drivers/CMSIS/Include/core_cm7.h **** - Core Debug Register 256:Drivers/CMSIS/Include/core_cm7.h **** - Core MPU Register 257:Drivers/CMSIS/Include/core_cm7.h **** - Core FPU Register 258:Drivers/CMSIS/Include/core_cm7.h **** ******************************************************************************/ ARM GAS /tmp/ccYgfTud.s page 6 259:Drivers/CMSIS/Include/core_cm7.h **** /** 260:Drivers/CMSIS/Include/core_cm7.h **** \defgroup CMSIS_core_register Defines and Type Definitions 261:Drivers/CMSIS/Include/core_cm7.h **** \brief Type definitions and defines for Cortex-M processor based devices. 262:Drivers/CMSIS/Include/core_cm7.h **** */ 263:Drivers/CMSIS/Include/core_cm7.h **** 264:Drivers/CMSIS/Include/core_cm7.h **** /** 265:Drivers/CMSIS/Include/core_cm7.h **** \ingroup CMSIS_core_register 266:Drivers/CMSIS/Include/core_cm7.h **** \defgroup CMSIS_CORE Status and Control Registers 267:Drivers/CMSIS/Include/core_cm7.h **** \brief Core Register type definitions. 268:Drivers/CMSIS/Include/core_cm7.h **** @{ 269:Drivers/CMSIS/Include/core_cm7.h **** */ 270:Drivers/CMSIS/Include/core_cm7.h **** 271:Drivers/CMSIS/Include/core_cm7.h **** /** 272:Drivers/CMSIS/Include/core_cm7.h **** \brief Union type to access the Application Program Status Register (APSR). 273:Drivers/CMSIS/Include/core_cm7.h **** */ 274:Drivers/CMSIS/Include/core_cm7.h **** typedef union 275:Drivers/CMSIS/Include/core_cm7.h **** { 276:Drivers/CMSIS/Include/core_cm7.h **** struct 277:Drivers/CMSIS/Include/core_cm7.h **** { 278:Drivers/CMSIS/Include/core_cm7.h **** uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ 279:Drivers/CMSIS/Include/core_cm7.h **** uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ 280:Drivers/CMSIS/Include/core_cm7.h **** uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ 281:Drivers/CMSIS/Include/core_cm7.h **** uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ 282:Drivers/CMSIS/Include/core_cm7.h **** uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ 283:Drivers/CMSIS/Include/core_cm7.h **** uint32_t C:1; /*!< bit: 29 Carry condition code flag */ 284:Drivers/CMSIS/Include/core_cm7.h **** uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ 285:Drivers/CMSIS/Include/core_cm7.h **** uint32_t N:1; /*!< bit: 31 Negative condition code flag */ 286:Drivers/CMSIS/Include/core_cm7.h **** } b; /*!< Structure used for bit access */ 287:Drivers/CMSIS/Include/core_cm7.h **** uint32_t w; /*!< Type used for word access */ 288:Drivers/CMSIS/Include/core_cm7.h **** } APSR_Type; 289:Drivers/CMSIS/Include/core_cm7.h **** 290:Drivers/CMSIS/Include/core_cm7.h **** /* APSR Register Definitions */ 291:Drivers/CMSIS/Include/core_cm7.h **** #define APSR_N_Pos 31U /*!< APSR 292:Drivers/CMSIS/Include/core_cm7.h **** #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR 293:Drivers/CMSIS/Include/core_cm7.h **** 294:Drivers/CMSIS/Include/core_cm7.h **** #define APSR_Z_Pos 30U /*!< APSR 295:Drivers/CMSIS/Include/core_cm7.h **** #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR 296:Drivers/CMSIS/Include/core_cm7.h **** 297:Drivers/CMSIS/Include/core_cm7.h **** #define APSR_C_Pos 29U /*!< APSR 298:Drivers/CMSIS/Include/core_cm7.h **** #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR 299:Drivers/CMSIS/Include/core_cm7.h **** 300:Drivers/CMSIS/Include/core_cm7.h **** #define APSR_V_Pos 28U /*!< APSR 301:Drivers/CMSIS/Include/core_cm7.h **** #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR 302:Drivers/CMSIS/Include/core_cm7.h **** 303:Drivers/CMSIS/Include/core_cm7.h **** #define APSR_Q_Pos 27U /*!< APSR 304:Drivers/CMSIS/Include/core_cm7.h **** #define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR 305:Drivers/CMSIS/Include/core_cm7.h **** 306:Drivers/CMSIS/Include/core_cm7.h **** #define APSR_GE_Pos 16U /*!< APSR 307:Drivers/CMSIS/Include/core_cm7.h **** #define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR 308:Drivers/CMSIS/Include/core_cm7.h **** 309:Drivers/CMSIS/Include/core_cm7.h **** 310:Drivers/CMSIS/Include/core_cm7.h **** /** 311:Drivers/CMSIS/Include/core_cm7.h **** \brief Union type to access the Interrupt Program Status Register (IPSR). 312:Drivers/CMSIS/Include/core_cm7.h **** */ 313:Drivers/CMSIS/Include/core_cm7.h **** typedef union 314:Drivers/CMSIS/Include/core_cm7.h **** { 315:Drivers/CMSIS/Include/core_cm7.h **** struct ARM GAS /tmp/ccYgfTud.s page 7 316:Drivers/CMSIS/Include/core_cm7.h **** { 317:Drivers/CMSIS/Include/core_cm7.h **** uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ 318:Drivers/CMSIS/Include/core_cm7.h **** uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ 319:Drivers/CMSIS/Include/core_cm7.h **** } b; /*!< Structure used for bit access */ 320:Drivers/CMSIS/Include/core_cm7.h **** uint32_t w; /*!< Type used for word access */ 321:Drivers/CMSIS/Include/core_cm7.h **** } IPSR_Type; 322:Drivers/CMSIS/Include/core_cm7.h **** 323:Drivers/CMSIS/Include/core_cm7.h **** /* IPSR Register Definitions */ 324:Drivers/CMSIS/Include/core_cm7.h **** #define IPSR_ISR_Pos 0U /*!< IPSR 325:Drivers/CMSIS/Include/core_cm7.h **** #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR 326:Drivers/CMSIS/Include/core_cm7.h **** 327:Drivers/CMSIS/Include/core_cm7.h **** 328:Drivers/CMSIS/Include/core_cm7.h **** /** 329:Drivers/CMSIS/Include/core_cm7.h **** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). 330:Drivers/CMSIS/Include/core_cm7.h **** */ 331:Drivers/CMSIS/Include/core_cm7.h **** typedef union 332:Drivers/CMSIS/Include/core_cm7.h **** { 333:Drivers/CMSIS/Include/core_cm7.h **** struct 334:Drivers/CMSIS/Include/core_cm7.h **** { 335:Drivers/CMSIS/Include/core_cm7.h **** uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ 336:Drivers/CMSIS/Include/core_cm7.h **** uint32_t _reserved0:1; /*!< bit: 9 Reserved */ 337:Drivers/CMSIS/Include/core_cm7.h **** uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ 338:Drivers/CMSIS/Include/core_cm7.h **** uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ 339:Drivers/CMSIS/Include/core_cm7.h **** uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ 340:Drivers/CMSIS/Include/core_cm7.h **** uint32_t T:1; /*!< bit: 24 Thumb bit */ 341:Drivers/CMSIS/Include/core_cm7.h **** uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ 342:Drivers/CMSIS/Include/core_cm7.h **** uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ 343:Drivers/CMSIS/Include/core_cm7.h **** uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ 344:Drivers/CMSIS/Include/core_cm7.h **** uint32_t C:1; /*!< bit: 29 Carry condition code flag */ 345:Drivers/CMSIS/Include/core_cm7.h **** uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ 346:Drivers/CMSIS/Include/core_cm7.h **** uint32_t N:1; /*!< bit: 31 Negative condition code flag */ 347:Drivers/CMSIS/Include/core_cm7.h **** } b; /*!< Structure used for bit access */ 348:Drivers/CMSIS/Include/core_cm7.h **** uint32_t w; /*!< Type used for word access */ 349:Drivers/CMSIS/Include/core_cm7.h **** } xPSR_Type; 350:Drivers/CMSIS/Include/core_cm7.h **** 351:Drivers/CMSIS/Include/core_cm7.h **** /* xPSR Register Definitions */ 352:Drivers/CMSIS/Include/core_cm7.h **** #define xPSR_N_Pos 31U /*!< xPSR 353:Drivers/CMSIS/Include/core_cm7.h **** #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR 354:Drivers/CMSIS/Include/core_cm7.h **** 355:Drivers/CMSIS/Include/core_cm7.h **** #define xPSR_Z_Pos 30U /*!< xPSR 356:Drivers/CMSIS/Include/core_cm7.h **** #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR 357:Drivers/CMSIS/Include/core_cm7.h **** 358:Drivers/CMSIS/Include/core_cm7.h **** #define xPSR_C_Pos 29U /*!< xPSR 359:Drivers/CMSIS/Include/core_cm7.h **** #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR 360:Drivers/CMSIS/Include/core_cm7.h **** 361:Drivers/CMSIS/Include/core_cm7.h **** #define xPSR_V_Pos 28U /*!< xPSR 362:Drivers/CMSIS/Include/core_cm7.h **** #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR 363:Drivers/CMSIS/Include/core_cm7.h **** 364:Drivers/CMSIS/Include/core_cm7.h **** #define xPSR_Q_Pos 27U /*!< xPSR 365:Drivers/CMSIS/Include/core_cm7.h **** #define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR 366:Drivers/CMSIS/Include/core_cm7.h **** 367:Drivers/CMSIS/Include/core_cm7.h **** #define xPSR_ICI_IT_2_Pos 25U /*!< xPSR 368:Drivers/CMSIS/Include/core_cm7.h **** #define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR 369:Drivers/CMSIS/Include/core_cm7.h **** 370:Drivers/CMSIS/Include/core_cm7.h **** #define xPSR_T_Pos 24U /*!< xPSR 371:Drivers/CMSIS/Include/core_cm7.h **** #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR 372:Drivers/CMSIS/Include/core_cm7.h **** ARM GAS /tmp/ccYgfTud.s page 8 373:Drivers/CMSIS/Include/core_cm7.h **** #define xPSR_GE_Pos 16U /*!< xPSR 374:Drivers/CMSIS/Include/core_cm7.h **** #define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR 375:Drivers/CMSIS/Include/core_cm7.h **** 376:Drivers/CMSIS/Include/core_cm7.h **** #define xPSR_ICI_IT_1_Pos 10U /*!< xPSR 377:Drivers/CMSIS/Include/core_cm7.h **** #define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR 378:Drivers/CMSIS/Include/core_cm7.h **** 379:Drivers/CMSIS/Include/core_cm7.h **** #define xPSR_ISR_Pos 0U /*!< xPSR 380:Drivers/CMSIS/Include/core_cm7.h **** #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR 381:Drivers/CMSIS/Include/core_cm7.h **** 382:Drivers/CMSIS/Include/core_cm7.h **** 383:Drivers/CMSIS/Include/core_cm7.h **** /** 384:Drivers/CMSIS/Include/core_cm7.h **** \brief Union type to access the Control Registers (CONTROL). 385:Drivers/CMSIS/Include/core_cm7.h **** */ 386:Drivers/CMSIS/Include/core_cm7.h **** typedef union 387:Drivers/CMSIS/Include/core_cm7.h **** { 388:Drivers/CMSIS/Include/core_cm7.h **** struct 389:Drivers/CMSIS/Include/core_cm7.h **** { 390:Drivers/CMSIS/Include/core_cm7.h **** uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ 391:Drivers/CMSIS/Include/core_cm7.h **** uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ 392:Drivers/CMSIS/Include/core_cm7.h **** uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ 393:Drivers/CMSIS/Include/core_cm7.h **** uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ 394:Drivers/CMSIS/Include/core_cm7.h **** } b; /*!< Structure used for bit access */ 395:Drivers/CMSIS/Include/core_cm7.h **** uint32_t w; /*!< Type used for word access */ 396:Drivers/CMSIS/Include/core_cm7.h **** } CONTROL_Type; 397:Drivers/CMSIS/Include/core_cm7.h **** 398:Drivers/CMSIS/Include/core_cm7.h **** /* CONTROL Register Definitions */ 399:Drivers/CMSIS/Include/core_cm7.h **** #define CONTROL_FPCA_Pos 2U /*!< CONT 400:Drivers/CMSIS/Include/core_cm7.h **** #define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONT 401:Drivers/CMSIS/Include/core_cm7.h **** 402:Drivers/CMSIS/Include/core_cm7.h **** #define CONTROL_SPSEL_Pos 1U /*!< CONT 403:Drivers/CMSIS/Include/core_cm7.h **** #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONT 404:Drivers/CMSIS/Include/core_cm7.h **** 405:Drivers/CMSIS/Include/core_cm7.h **** #define CONTROL_nPRIV_Pos 0U /*!< CONT 406:Drivers/CMSIS/Include/core_cm7.h **** #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONT 407:Drivers/CMSIS/Include/core_cm7.h **** 408:Drivers/CMSIS/Include/core_cm7.h **** /*@} end of group CMSIS_CORE */ 409:Drivers/CMSIS/Include/core_cm7.h **** 410:Drivers/CMSIS/Include/core_cm7.h **** 411:Drivers/CMSIS/Include/core_cm7.h **** /** 412:Drivers/CMSIS/Include/core_cm7.h **** \ingroup CMSIS_core_register 413:Drivers/CMSIS/Include/core_cm7.h **** \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) 414:Drivers/CMSIS/Include/core_cm7.h **** \brief Type definitions for the NVIC Registers 415:Drivers/CMSIS/Include/core_cm7.h **** @{ 416:Drivers/CMSIS/Include/core_cm7.h **** */ 417:Drivers/CMSIS/Include/core_cm7.h **** 418:Drivers/CMSIS/Include/core_cm7.h **** /** 419:Drivers/CMSIS/Include/core_cm7.h **** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). 420:Drivers/CMSIS/Include/core_cm7.h **** */ 421:Drivers/CMSIS/Include/core_cm7.h **** typedef struct 422:Drivers/CMSIS/Include/core_cm7.h **** { 423:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ 424:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED0[24U]; 425:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register 426:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RSERVED1[24U]; 427:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register * 428:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED2[24U]; 429:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register ARM GAS /tmp/ccYgfTud.s page 9 430:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED3[24U]; 431:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ 432:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED4[56U]; 433:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bi 434:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED5[644U]; 435:Drivers/CMSIS/Include/core_cm7.h **** __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Regis 436:Drivers/CMSIS/Include/core_cm7.h **** } NVIC_Type; 437:Drivers/CMSIS/Include/core_cm7.h **** 438:Drivers/CMSIS/Include/core_cm7.h **** /* Software Triggered Interrupt Register Definitions */ 439:Drivers/CMSIS/Include/core_cm7.h **** #define NVIC_STIR_INTID_Pos 0U /*!< STIR: I 440:Drivers/CMSIS/Include/core_cm7.h **** #define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: I 441:Drivers/CMSIS/Include/core_cm7.h **** 442:Drivers/CMSIS/Include/core_cm7.h **** /*@} end of group CMSIS_NVIC */ 443:Drivers/CMSIS/Include/core_cm7.h **** 444:Drivers/CMSIS/Include/core_cm7.h **** 445:Drivers/CMSIS/Include/core_cm7.h **** /** 446:Drivers/CMSIS/Include/core_cm7.h **** \ingroup CMSIS_core_register 447:Drivers/CMSIS/Include/core_cm7.h **** \defgroup CMSIS_SCB System Control Block (SCB) 448:Drivers/CMSIS/Include/core_cm7.h **** \brief Type definitions for the System Control Block Registers 449:Drivers/CMSIS/Include/core_cm7.h **** @{ 450:Drivers/CMSIS/Include/core_cm7.h **** */ 451:Drivers/CMSIS/Include/core_cm7.h **** 452:Drivers/CMSIS/Include/core_cm7.h **** /** 453:Drivers/CMSIS/Include/core_cm7.h **** \brief Structure type to access the System Control Block (SCB). 454:Drivers/CMSIS/Include/core_cm7.h **** */ 455:Drivers/CMSIS/Include/core_cm7.h **** typedef struct 456:Drivers/CMSIS/Include/core_cm7.h **** { 457:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ 458:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Regi 459:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ 460:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset 461:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ 462:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register * 463:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registe 464:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State 465:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Regist 466:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ 467:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ 468:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register 469:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ 470:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register 471:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ 472:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ 473:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ 474:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t ID_MFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ 475:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t ID_ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Regis 476:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED0[1U]; 477:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ 478:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ 479:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ 480:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ 481:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Regis 482:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED3[93U]; 483:Drivers/CMSIS/Include/core_cm7.h **** __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Reg 484:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED4[15U]; 485:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 486:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 ARM GAS /tmp/ccYgfTud.s page 10 487:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 488:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED5[1U]; 489:Drivers/CMSIS/Include/core_cm7.h **** __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ 490:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED6[1U]; 491:Drivers/CMSIS/Include/core_cm7.h **** __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU 492:Drivers/CMSIS/Include/core_cm7.h **** __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC 493:Drivers/CMSIS/Include/core_cm7.h **** __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ 494:Drivers/CMSIS/Include/core_cm7.h **** __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ 495:Drivers/CMSIS/Include/core_cm7.h **** __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ 496:Drivers/CMSIS/Include/core_cm7.h **** __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ 497:Drivers/CMSIS/Include/core_cm7.h **** __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by 498:Drivers/CMSIS/Include/core_cm7.h **** __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by 499:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED7[6U]; 500:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memo 501:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Cont 502:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ 503:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ 504:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ 505:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED8[1U]; 506:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Regis 507:Drivers/CMSIS/Include/core_cm7.h **** } SCB_Type; 508:Drivers/CMSIS/Include/core_cm7.h **** 509:Drivers/CMSIS/Include/core_cm7.h **** /* SCB CPUID Register Definitions */ 510:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB 511:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB 512:Drivers/CMSIS/Include/core_cm7.h **** 513:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB 514:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB 515:Drivers/CMSIS/Include/core_cm7.h **** 516:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB 517:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB 518:Drivers/CMSIS/Include/core_cm7.h **** 519:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB 520:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB 521:Drivers/CMSIS/Include/core_cm7.h **** 522:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CPUID_REVISION_Pos 0U /*!< SCB 523:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB 524:Drivers/CMSIS/Include/core_cm7.h **** 525:Drivers/CMSIS/Include/core_cm7.h **** /* SCB Interrupt Control State Register Definitions */ 526:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB 527:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB 528:Drivers/CMSIS/Include/core_cm7.h **** 529:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB 530:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB 531:Drivers/CMSIS/Include/core_cm7.h **** 532:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB 533:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB 534:Drivers/CMSIS/Include/core_cm7.h **** 535:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB 536:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB 537:Drivers/CMSIS/Include/core_cm7.h **** 538:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB 539:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB 540:Drivers/CMSIS/Include/core_cm7.h **** 541:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB 542:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB 543:Drivers/CMSIS/Include/core_cm7.h **** ARM GAS /tmp/ccYgfTud.s page 11 544:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB 545:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB 546:Drivers/CMSIS/Include/core_cm7.h **** 547:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB 548:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB 549:Drivers/CMSIS/Include/core_cm7.h **** 550:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB 551:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB 552:Drivers/CMSIS/Include/core_cm7.h **** 553:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB 554:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB 555:Drivers/CMSIS/Include/core_cm7.h **** 556:Drivers/CMSIS/Include/core_cm7.h **** /* SCB Vector Table Offset Register Definitions */ 557:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB 558:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB 559:Drivers/CMSIS/Include/core_cm7.h **** 560:Drivers/CMSIS/Include/core_cm7.h **** /* SCB Application Interrupt and Reset Control Register Definitions */ 561:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB 562:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB 563:Drivers/CMSIS/Include/core_cm7.h **** 564:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB 565:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB 566:Drivers/CMSIS/Include/core_cm7.h **** 567:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB 568:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB 569:Drivers/CMSIS/Include/core_cm7.h **** 570:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB 571:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB 572:Drivers/CMSIS/Include/core_cm7.h **** 573:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB 574:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB 575:Drivers/CMSIS/Include/core_cm7.h **** 576:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB 577:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB 578:Drivers/CMSIS/Include/core_cm7.h **** 579:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB 580:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB 581:Drivers/CMSIS/Include/core_cm7.h **** 582:Drivers/CMSIS/Include/core_cm7.h **** /* SCB System Control Register Definitions */ 583:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB 584:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB 585:Drivers/CMSIS/Include/core_cm7.h **** 586:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB 587:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB 588:Drivers/CMSIS/Include/core_cm7.h **** 589:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB 590:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB 591:Drivers/CMSIS/Include/core_cm7.h **** 592:Drivers/CMSIS/Include/core_cm7.h **** /* SCB Configuration Control Register Definitions */ 593:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCR_BP_Pos 18U /*!< SCB 594:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB 595:Drivers/CMSIS/Include/core_cm7.h **** 596:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCR_IC_Pos 17U /*!< SCB 597:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB 598:Drivers/CMSIS/Include/core_cm7.h **** 599:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCR_DC_Pos 16U /*!< SCB 600:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB ARM GAS /tmp/ccYgfTud.s page 12 601:Drivers/CMSIS/Include/core_cm7.h **** 602:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCR_STKALIGN_Pos 9U /*!< SCB 603:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB 604:Drivers/CMSIS/Include/core_cm7.h **** 605:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB 606:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB 607:Drivers/CMSIS/Include/core_cm7.h **** 608:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB 609:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB 610:Drivers/CMSIS/Include/core_cm7.h **** 611:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB 612:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB 613:Drivers/CMSIS/Include/core_cm7.h **** 614:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB 615:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB 616:Drivers/CMSIS/Include/core_cm7.h **** 617:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB 618:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB 619:Drivers/CMSIS/Include/core_cm7.h **** 620:Drivers/CMSIS/Include/core_cm7.h **** /* SCB System Handler Control and State Register Definitions */ 621:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB 622:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB 623:Drivers/CMSIS/Include/core_cm7.h **** 624:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB 625:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB 626:Drivers/CMSIS/Include/core_cm7.h **** 627:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB 628:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB 629:Drivers/CMSIS/Include/core_cm7.h **** 630:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB 631:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB 632:Drivers/CMSIS/Include/core_cm7.h **** 633:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB 634:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB 635:Drivers/CMSIS/Include/core_cm7.h **** 636:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB 637:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB 638:Drivers/CMSIS/Include/core_cm7.h **** 639:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB 640:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB 641:Drivers/CMSIS/Include/core_cm7.h **** 642:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB 643:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB 644:Drivers/CMSIS/Include/core_cm7.h **** 645:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB 646:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB 647:Drivers/CMSIS/Include/core_cm7.h **** 648:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB 649:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB 650:Drivers/CMSIS/Include/core_cm7.h **** 651:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB 652:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB 653:Drivers/CMSIS/Include/core_cm7.h **** 654:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB 655:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB 656:Drivers/CMSIS/Include/core_cm7.h **** 657:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB ARM GAS /tmp/ccYgfTud.s page 13 658:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB 659:Drivers/CMSIS/Include/core_cm7.h **** 660:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB 661:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB 662:Drivers/CMSIS/Include/core_cm7.h **** 663:Drivers/CMSIS/Include/core_cm7.h **** /* SCB Configurable Fault Status Register Definitions */ 664:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB 665:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB 666:Drivers/CMSIS/Include/core_cm7.h **** 667:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB 668:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB 669:Drivers/CMSIS/Include/core_cm7.h **** 670:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB 671:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB 672:Drivers/CMSIS/Include/core_cm7.h **** 673:Drivers/CMSIS/Include/core_cm7.h **** /* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ 674:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB 675:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB 676:Drivers/CMSIS/Include/core_cm7.h **** 677:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB 678:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB 679:Drivers/CMSIS/Include/core_cm7.h **** 680:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB 681:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB 682:Drivers/CMSIS/Include/core_cm7.h **** 683:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB 684:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB 685:Drivers/CMSIS/Include/core_cm7.h **** 686:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB 687:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB 688:Drivers/CMSIS/Include/core_cm7.h **** 689:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB 690:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB 691:Drivers/CMSIS/Include/core_cm7.h **** 692:Drivers/CMSIS/Include/core_cm7.h **** /* BusFault Status Register (part of SCB Configurable Fault Status Register) */ 693:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB 694:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB 695:Drivers/CMSIS/Include/core_cm7.h **** 696:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB 697:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB 698:Drivers/CMSIS/Include/core_cm7.h **** 699:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB 700:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB 701:Drivers/CMSIS/Include/core_cm7.h **** 702:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB 703:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB 704:Drivers/CMSIS/Include/core_cm7.h **** 705:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB 706:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB 707:Drivers/CMSIS/Include/core_cm7.h **** 708:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB 709:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB 710:Drivers/CMSIS/Include/core_cm7.h **** 711:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB 712:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB 713:Drivers/CMSIS/Include/core_cm7.h **** 714:Drivers/CMSIS/Include/core_cm7.h **** /* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ ARM GAS /tmp/ccYgfTud.s page 14 715:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB 716:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB 717:Drivers/CMSIS/Include/core_cm7.h **** 718:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB 719:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB 720:Drivers/CMSIS/Include/core_cm7.h **** 721:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB 722:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB 723:Drivers/CMSIS/Include/core_cm7.h **** 724:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB 725:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB 726:Drivers/CMSIS/Include/core_cm7.h **** 727:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB 728:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB 729:Drivers/CMSIS/Include/core_cm7.h **** 730:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB 731:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB 732:Drivers/CMSIS/Include/core_cm7.h **** 733:Drivers/CMSIS/Include/core_cm7.h **** /* SCB Hard Fault Status Register Definitions */ 734:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB 735:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB 736:Drivers/CMSIS/Include/core_cm7.h **** 737:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_HFSR_FORCED_Pos 30U /*!< SCB 738:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB 739:Drivers/CMSIS/Include/core_cm7.h **** 740:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB 741:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB 742:Drivers/CMSIS/Include/core_cm7.h **** 743:Drivers/CMSIS/Include/core_cm7.h **** /* SCB Debug Fault Status Register Definitions */ 744:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB 745:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB 746:Drivers/CMSIS/Include/core_cm7.h **** 747:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DFSR_VCATCH_Pos 3U /*!< SCB 748:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB 749:Drivers/CMSIS/Include/core_cm7.h **** 750:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB 751:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB 752:Drivers/CMSIS/Include/core_cm7.h **** 753:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DFSR_BKPT_Pos 1U /*!< SCB 754:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB 755:Drivers/CMSIS/Include/core_cm7.h **** 756:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DFSR_HALTED_Pos 0U /*!< SCB 757:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB 758:Drivers/CMSIS/Include/core_cm7.h **** 759:Drivers/CMSIS/Include/core_cm7.h **** /* SCB Cache Level ID Register Definitions */ 760:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CLIDR_LOUU_Pos 27U /*!< SCB 761:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB 762:Drivers/CMSIS/Include/core_cm7.h **** 763:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CLIDR_LOC_Pos 24U /*!< SCB 764:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB 765:Drivers/CMSIS/Include/core_cm7.h **** 766:Drivers/CMSIS/Include/core_cm7.h **** /* SCB Cache Type Register Definitions */ 767:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CTR_FORMAT_Pos 29U /*!< SCB 768:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB 769:Drivers/CMSIS/Include/core_cm7.h **** 770:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CTR_CWG_Pos 24U /*!< SCB 771:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB ARM GAS /tmp/ccYgfTud.s page 15 772:Drivers/CMSIS/Include/core_cm7.h **** 773:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CTR_ERG_Pos 20U /*!< SCB 774:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB 775:Drivers/CMSIS/Include/core_cm7.h **** 776:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CTR_DMINLINE_Pos 16U /*!< SCB 777:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB 778:Drivers/CMSIS/Include/core_cm7.h **** 779:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CTR_IMINLINE_Pos 0U /*!< SCB 780:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB 781:Drivers/CMSIS/Include/core_cm7.h **** 782:Drivers/CMSIS/Include/core_cm7.h **** /* SCB Cache Size ID Register Definitions */ 783:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCSIDR_WT_Pos 31U /*!< SCB 784:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB 785:Drivers/CMSIS/Include/core_cm7.h **** 786:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCSIDR_WB_Pos 30U /*!< SCB 787:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB 788:Drivers/CMSIS/Include/core_cm7.h **** 789:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCSIDR_RA_Pos 29U /*!< SCB 790:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB 791:Drivers/CMSIS/Include/core_cm7.h **** 792:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCSIDR_WA_Pos 28U /*!< SCB 793:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB 794:Drivers/CMSIS/Include/core_cm7.h **** 795:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB 796:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB 797:Drivers/CMSIS/Include/core_cm7.h **** 798:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB 799:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB 800:Drivers/CMSIS/Include/core_cm7.h **** 801:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB 802:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB 803:Drivers/CMSIS/Include/core_cm7.h **** 804:Drivers/CMSIS/Include/core_cm7.h **** /* SCB Cache Size Selection Register Definitions */ 805:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB 806:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB 807:Drivers/CMSIS/Include/core_cm7.h **** 808:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CSSELR_IND_Pos 0U /*!< SCB 809:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB 810:Drivers/CMSIS/Include/core_cm7.h **** 811:Drivers/CMSIS/Include/core_cm7.h **** /* SCB Software Triggered Interrupt Register Definitions */ 812:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_STIR_INTID_Pos 0U /*!< SCB 813:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB 814:Drivers/CMSIS/Include/core_cm7.h **** 815:Drivers/CMSIS/Include/core_cm7.h **** /* SCB D-Cache Invalidate by Set-way Register Definitions */ 816:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DCISW_WAY_Pos 30U /*!< SCB 817:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB 818:Drivers/CMSIS/Include/core_cm7.h **** 819:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DCISW_SET_Pos 5U /*!< SCB 820:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB 821:Drivers/CMSIS/Include/core_cm7.h **** 822:Drivers/CMSIS/Include/core_cm7.h **** /* SCB D-Cache Clean by Set-way Register Definitions */ 823:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DCCSW_WAY_Pos 30U /*!< SCB 824:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB 825:Drivers/CMSIS/Include/core_cm7.h **** 826:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DCCSW_SET_Pos 5U /*!< SCB 827:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB 828:Drivers/CMSIS/Include/core_cm7.h **** ARM GAS /tmp/ccYgfTud.s page 16 829:Drivers/CMSIS/Include/core_cm7.h **** /* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ 830:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DCCISW_WAY_Pos 30U /*!< SCB 831:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB 832:Drivers/CMSIS/Include/core_cm7.h **** 833:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DCCISW_SET_Pos 5U /*!< SCB 834:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB 835:Drivers/CMSIS/Include/core_cm7.h **** 836:Drivers/CMSIS/Include/core_cm7.h **** /* Instruction Tightly-Coupled Memory Control Register Definitions */ 837:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ITCMCR_SZ_Pos 3U /*!< SCB 838:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB 839:Drivers/CMSIS/Include/core_cm7.h **** 840:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB 841:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB 842:Drivers/CMSIS/Include/core_cm7.h **** 843:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ITCMCR_RMW_Pos 1U /*!< SCB 844:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB 845:Drivers/CMSIS/Include/core_cm7.h **** 846:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ITCMCR_EN_Pos 0U /*!< SCB 847:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB 848:Drivers/CMSIS/Include/core_cm7.h **** 849:Drivers/CMSIS/Include/core_cm7.h **** /* Data Tightly-Coupled Memory Control Register Definitions */ 850:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DTCMCR_SZ_Pos 3U /*!< SCB 851:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB 852:Drivers/CMSIS/Include/core_cm7.h **** 853:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB 854:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB 855:Drivers/CMSIS/Include/core_cm7.h **** 856:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DTCMCR_RMW_Pos 1U /*!< SCB 857:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB 858:Drivers/CMSIS/Include/core_cm7.h **** 859:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DTCMCR_EN_Pos 0U /*!< SCB 860:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB 861:Drivers/CMSIS/Include/core_cm7.h **** 862:Drivers/CMSIS/Include/core_cm7.h **** /* AHBP Control Register Definitions */ 863:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AHBPCR_SZ_Pos 1U /*!< SCB 864:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB 865:Drivers/CMSIS/Include/core_cm7.h **** 866:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AHBPCR_EN_Pos 0U /*!< SCB 867:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB 868:Drivers/CMSIS/Include/core_cm7.h **** 869:Drivers/CMSIS/Include/core_cm7.h **** /* L1 Cache Control Register Definitions */ 870:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CACR_FORCEWT_Pos 2U /*!< SCB 871:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB 872:Drivers/CMSIS/Include/core_cm7.h **** 873:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CACR_ECCEN_Pos 1U /*!< SCB 874:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB 875:Drivers/CMSIS/Include/core_cm7.h **** 876:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CACR_SIWT_Pos 0U /*!< SCB 877:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB 878:Drivers/CMSIS/Include/core_cm7.h **** 879:Drivers/CMSIS/Include/core_cm7.h **** /* AHBS Control Register Definitions */ 880:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB 881:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB 882:Drivers/CMSIS/Include/core_cm7.h **** 883:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB 884:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB 885:Drivers/CMSIS/Include/core_cm7.h **** ARM GAS /tmp/ccYgfTud.s page 17 886:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AHBSCR_CTL_Pos 0U /*!< SCB 887:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB 888:Drivers/CMSIS/Include/core_cm7.h **** 889:Drivers/CMSIS/Include/core_cm7.h **** /* Auxiliary Bus Fault Status Register Definitions */ 890:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB 891:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB 892:Drivers/CMSIS/Include/core_cm7.h **** 893:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ABFSR_EPPB_Pos 4U /*!< SCB 894:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB 895:Drivers/CMSIS/Include/core_cm7.h **** 896:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ABFSR_AXIM_Pos 3U /*!< SCB 897:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB 898:Drivers/CMSIS/Include/core_cm7.h **** 899:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ABFSR_AHBP_Pos 2U /*!< SCB 900:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB 901:Drivers/CMSIS/Include/core_cm7.h **** 902:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ABFSR_DTCM_Pos 1U /*!< SCB 903:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB 904:Drivers/CMSIS/Include/core_cm7.h **** 905:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ABFSR_ITCM_Pos 0U /*!< SCB 906:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB 907:Drivers/CMSIS/Include/core_cm7.h **** 908:Drivers/CMSIS/Include/core_cm7.h **** /*@} end of group CMSIS_SCB */ 909:Drivers/CMSIS/Include/core_cm7.h **** 910:Drivers/CMSIS/Include/core_cm7.h **** 911:Drivers/CMSIS/Include/core_cm7.h **** /** 912:Drivers/CMSIS/Include/core_cm7.h **** \ingroup CMSIS_core_register 913:Drivers/CMSIS/Include/core_cm7.h **** \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) 914:Drivers/CMSIS/Include/core_cm7.h **** \brief Type definitions for the System Control and ID Register not in the SCB 915:Drivers/CMSIS/Include/core_cm7.h **** @{ 916:Drivers/CMSIS/Include/core_cm7.h **** */ 917:Drivers/CMSIS/Include/core_cm7.h **** 918:Drivers/CMSIS/Include/core_cm7.h **** /** 919:Drivers/CMSIS/Include/core_cm7.h **** \brief Structure type to access the System Control and ID Register not in the SCB. 920:Drivers/CMSIS/Include/core_cm7.h **** */ 921:Drivers/CMSIS/Include/core_cm7.h **** typedef struct 922:Drivers/CMSIS/Include/core_cm7.h **** { 923:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED0[1U]; 924:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Regist 925:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ 926:Drivers/CMSIS/Include/core_cm7.h **** } SCnSCB_Type; 927:Drivers/CMSIS/Include/core_cm7.h **** 928:Drivers/CMSIS/Include/core_cm7.h **** /* Interrupt Controller Type Register Definitions */ 929:Drivers/CMSIS/Include/core_cm7.h **** #define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: I 930:Drivers/CMSIS/Include/core_cm7.h **** #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: I 931:Drivers/CMSIS/Include/core_cm7.h **** 932:Drivers/CMSIS/Include/core_cm7.h **** /* Auxiliary Control Register Definitions */ 933:Drivers/CMSIS/Include/core_cm7.h **** #define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12U /*!< ACTLR: 934:Drivers/CMSIS/Include/core_cm7.h **** #define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: 935:Drivers/CMSIS/Include/core_cm7.h **** 936:Drivers/CMSIS/Include/core_cm7.h **** #define SCnSCB_ACTLR_DISRAMODE_Pos 11U /*!< ACTLR: 937:Drivers/CMSIS/Include/core_cm7.h **** #define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) /*!< ACTLR: 938:Drivers/CMSIS/Include/core_cm7.h **** 939:Drivers/CMSIS/Include/core_cm7.h **** #define SCnSCB_ACTLR_FPEXCODIS_Pos 10U /*!< ACTLR: 940:Drivers/CMSIS/Include/core_cm7.h **** #define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: 941:Drivers/CMSIS/Include/core_cm7.h **** 942:Drivers/CMSIS/Include/core_cm7.h **** #define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: ARM GAS /tmp/ccYgfTud.s page 18 943:Drivers/CMSIS/Include/core_cm7.h **** #define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: 944:Drivers/CMSIS/Include/core_cm7.h **** 945:Drivers/CMSIS/Include/core_cm7.h **** #define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: 946:Drivers/CMSIS/Include/core_cm7.h **** #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: 947:Drivers/CMSIS/Include/core_cm7.h **** 948:Drivers/CMSIS/Include/core_cm7.h **** /*@} end of group CMSIS_SCnotSCB */ 949:Drivers/CMSIS/Include/core_cm7.h **** 950:Drivers/CMSIS/Include/core_cm7.h **** 951:Drivers/CMSIS/Include/core_cm7.h **** /** 952:Drivers/CMSIS/Include/core_cm7.h **** \ingroup CMSIS_core_register 953:Drivers/CMSIS/Include/core_cm7.h **** \defgroup CMSIS_SysTick System Tick Timer (SysTick) 954:Drivers/CMSIS/Include/core_cm7.h **** \brief Type definitions for the System Timer Registers. 955:Drivers/CMSIS/Include/core_cm7.h **** @{ 956:Drivers/CMSIS/Include/core_cm7.h **** */ 957:Drivers/CMSIS/Include/core_cm7.h **** 958:Drivers/CMSIS/Include/core_cm7.h **** /** 959:Drivers/CMSIS/Include/core_cm7.h **** \brief Structure type to access the System Timer (SysTick). 960:Drivers/CMSIS/Include/core_cm7.h **** */ 961:Drivers/CMSIS/Include/core_cm7.h **** typedef struct 962:Drivers/CMSIS/Include/core_cm7.h **** { 963:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Regis 964:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ 965:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register * 966:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ 967:Drivers/CMSIS/Include/core_cm7.h **** } SysTick_Type; 968:Drivers/CMSIS/Include/core_cm7.h **** 969:Drivers/CMSIS/Include/core_cm7.h **** /* SysTick Control / Status Register Definitions */ 970:Drivers/CMSIS/Include/core_cm7.h **** #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysT 971:Drivers/CMSIS/Include/core_cm7.h **** #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysT 972:Drivers/CMSIS/Include/core_cm7.h **** 973:Drivers/CMSIS/Include/core_cm7.h **** #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysT 974:Drivers/CMSIS/Include/core_cm7.h **** #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysT 975:Drivers/CMSIS/Include/core_cm7.h **** 976:Drivers/CMSIS/Include/core_cm7.h **** #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysT 977:Drivers/CMSIS/Include/core_cm7.h **** #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysT 978:Drivers/CMSIS/Include/core_cm7.h **** 979:Drivers/CMSIS/Include/core_cm7.h **** #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysT 980:Drivers/CMSIS/Include/core_cm7.h **** #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysT 981:Drivers/CMSIS/Include/core_cm7.h **** 982:Drivers/CMSIS/Include/core_cm7.h **** /* SysTick Reload Register Definitions */ 983:Drivers/CMSIS/Include/core_cm7.h **** #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysT 984:Drivers/CMSIS/Include/core_cm7.h **** #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysT 985:Drivers/CMSIS/Include/core_cm7.h **** 986:Drivers/CMSIS/Include/core_cm7.h **** /* SysTick Current Register Definitions */ 987:Drivers/CMSIS/Include/core_cm7.h **** #define SysTick_VAL_CURRENT_Pos 0U /*!< SysT 988:Drivers/CMSIS/Include/core_cm7.h **** #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysT 989:Drivers/CMSIS/Include/core_cm7.h **** 990:Drivers/CMSIS/Include/core_cm7.h **** /* SysTick Calibration Register Definitions */ 991:Drivers/CMSIS/Include/core_cm7.h **** #define SysTick_CALIB_NOREF_Pos 31U /*!< SysT 992:Drivers/CMSIS/Include/core_cm7.h **** #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysT 993:Drivers/CMSIS/Include/core_cm7.h **** 994:Drivers/CMSIS/Include/core_cm7.h **** #define SysTick_CALIB_SKEW_Pos 30U /*!< SysT 995:Drivers/CMSIS/Include/core_cm7.h **** #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysT 996:Drivers/CMSIS/Include/core_cm7.h **** 997:Drivers/CMSIS/Include/core_cm7.h **** #define SysTick_CALIB_TENMS_Pos 0U /*!< SysT 998:Drivers/CMSIS/Include/core_cm7.h **** #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysT 999:Drivers/CMSIS/Include/core_cm7.h **** ARM GAS /tmp/ccYgfTud.s page 19 1000:Drivers/CMSIS/Include/core_cm7.h **** /*@} end of group CMSIS_SysTick */ 1001:Drivers/CMSIS/Include/core_cm7.h **** 1002:Drivers/CMSIS/Include/core_cm7.h **** 1003:Drivers/CMSIS/Include/core_cm7.h **** /** 1004:Drivers/CMSIS/Include/core_cm7.h **** \ingroup CMSIS_core_register 1005:Drivers/CMSIS/Include/core_cm7.h **** \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) 1006:Drivers/CMSIS/Include/core_cm7.h **** \brief Type definitions for the Instrumentation Trace Macrocell (ITM) 1007:Drivers/CMSIS/Include/core_cm7.h **** @{ 1008:Drivers/CMSIS/Include/core_cm7.h **** */ 1009:Drivers/CMSIS/Include/core_cm7.h **** 1010:Drivers/CMSIS/Include/core_cm7.h **** /** 1011:Drivers/CMSIS/Include/core_cm7.h **** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). 1012:Drivers/CMSIS/Include/core_cm7.h **** */ 1013:Drivers/CMSIS/Include/core_cm7.h **** typedef struct 1014:Drivers/CMSIS/Include/core_cm7.h **** { 1015:Drivers/CMSIS/Include/core_cm7.h **** __OM union 1016:Drivers/CMSIS/Include/core_cm7.h **** { 1017:Drivers/CMSIS/Include/core_cm7.h **** __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ 1018:Drivers/CMSIS/Include/core_cm7.h **** __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ 1019:Drivers/CMSIS/Include/core_cm7.h **** __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ 1020:Drivers/CMSIS/Include/core_cm7.h **** } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ 1021:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED0[864U]; 1022:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ 1023:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED1[15U]; 1024:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ 1025:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED2[15U]; 1026:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ 1027:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED3[29U]; 1028:Drivers/CMSIS/Include/core_cm7.h **** __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register * 1029:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ 1030:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Reg 1031:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED4[43U]; 1032:Drivers/CMSIS/Include/core_cm7.h **** __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ 1033:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ 1034:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED5[6U]; 1035:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Re 1036:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Re 1037:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Re 1038:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Re 1039:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Re 1040:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Re 1041:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Re 1042:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Re 1043:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Re 1044:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Re 1045:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Re 1046:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Re 1047:Drivers/CMSIS/Include/core_cm7.h **** } ITM_Type; 1048:Drivers/CMSIS/Include/core_cm7.h **** 1049:Drivers/CMSIS/Include/core_cm7.h **** /* ITM Trace Privilege Register Definitions */ 1050:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM 1051:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM 1052:Drivers/CMSIS/Include/core_cm7.h **** 1053:Drivers/CMSIS/Include/core_cm7.h **** /* ITM Trace Control Register Definitions */ 1054:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TCR_BUSY_Pos 23U /*!< ITM 1055:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM 1056:Drivers/CMSIS/Include/core_cm7.h **** ARM GAS /tmp/ccYgfTud.s page 20 1057:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TCR_TraceBusID_Pos 16U /*!< ITM 1058:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM 1059:Drivers/CMSIS/Include/core_cm7.h **** 1060:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM 1061:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM 1062:Drivers/CMSIS/Include/core_cm7.h **** 1063:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TCR_TSPrescale_Pos 8U /*!< ITM 1064:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM 1065:Drivers/CMSIS/Include/core_cm7.h **** 1066:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TCR_SWOENA_Pos 4U /*!< ITM 1067:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM 1068:Drivers/CMSIS/Include/core_cm7.h **** 1069:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TCR_DWTENA_Pos 3U /*!< ITM 1070:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM 1071:Drivers/CMSIS/Include/core_cm7.h **** 1072:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TCR_SYNCENA_Pos 2U /*!< ITM 1073:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM 1074:Drivers/CMSIS/Include/core_cm7.h **** 1075:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TCR_TSENA_Pos 1U /*!< ITM 1076:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM 1077:Drivers/CMSIS/Include/core_cm7.h **** 1078:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TCR_ITMENA_Pos 0U /*!< ITM 1079:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM 1080:Drivers/CMSIS/Include/core_cm7.h **** 1081:Drivers/CMSIS/Include/core_cm7.h **** /* ITM Integration Write Register Definitions */ 1082:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM 1083:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM 1084:Drivers/CMSIS/Include/core_cm7.h **** 1085:Drivers/CMSIS/Include/core_cm7.h **** /* ITM Integration Read Register Definitions */ 1086:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_IRR_ATREADYM_Pos 0U /*!< ITM 1087:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM 1088:Drivers/CMSIS/Include/core_cm7.h **** 1089:Drivers/CMSIS/Include/core_cm7.h **** /* ITM Integration Mode Control Register Definitions */ 1090:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM 1091:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM 1092:Drivers/CMSIS/Include/core_cm7.h **** 1093:Drivers/CMSIS/Include/core_cm7.h **** /* ITM Lock Status Register Definitions */ 1094:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_LSR_ByteAcc_Pos 2U /*!< ITM 1095:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM 1096:Drivers/CMSIS/Include/core_cm7.h **** 1097:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_LSR_Access_Pos 1U /*!< ITM 1098:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM 1099:Drivers/CMSIS/Include/core_cm7.h **** 1100:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_LSR_Present_Pos 0U /*!< ITM 1101:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM 1102:Drivers/CMSIS/Include/core_cm7.h **** 1103:Drivers/CMSIS/Include/core_cm7.h **** /*@}*/ /* end of group CMSIS_ITM */ 1104:Drivers/CMSIS/Include/core_cm7.h **** 1105:Drivers/CMSIS/Include/core_cm7.h **** 1106:Drivers/CMSIS/Include/core_cm7.h **** /** 1107:Drivers/CMSIS/Include/core_cm7.h **** \ingroup CMSIS_core_register 1108:Drivers/CMSIS/Include/core_cm7.h **** \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) 1109:Drivers/CMSIS/Include/core_cm7.h **** \brief Type definitions for the Data Watchpoint and Trace (DWT) 1110:Drivers/CMSIS/Include/core_cm7.h **** @{ 1111:Drivers/CMSIS/Include/core_cm7.h **** */ 1112:Drivers/CMSIS/Include/core_cm7.h **** 1113:Drivers/CMSIS/Include/core_cm7.h **** /** ARM GAS /tmp/ccYgfTud.s page 21 1114:Drivers/CMSIS/Include/core_cm7.h **** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). 1115:Drivers/CMSIS/Include/core_cm7.h **** */ 1116:Drivers/CMSIS/Include/core_cm7.h **** typedef struct 1117:Drivers/CMSIS/Include/core_cm7.h **** { 1118:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ 1119:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ 1120:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ 1121:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Registe 1122:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ 1123:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ 1124:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Registe 1125:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register 1126:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ 1127:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ 1128:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ 1129:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED0[1U]; 1130:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ 1131:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ 1132:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ 1133:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED1[1U]; 1134:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ 1135:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ 1136:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ 1137:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED2[1U]; 1138:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ 1139:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ 1140:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ 1141:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED3[981U]; 1142:Drivers/CMSIS/Include/core_cm7.h **** __OM uint32_t LAR; /*!< Offset: 0xFB0 ( W) Lock Access Register */ 1143:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ 1144:Drivers/CMSIS/Include/core_cm7.h **** } DWT_Type; 1145:Drivers/CMSIS/Include/core_cm7.h **** 1146:Drivers/CMSIS/Include/core_cm7.h **** /* DWT Control Register Definitions */ 1147:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTR 1148:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTR 1149:Drivers/CMSIS/Include/core_cm7.h **** 1150:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTR 1151:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTR 1152:Drivers/CMSIS/Include/core_cm7.h **** 1153:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTR 1154:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTR 1155:Drivers/CMSIS/Include/core_cm7.h **** 1156:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTR 1157:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTR 1158:Drivers/CMSIS/Include/core_cm7.h **** 1159:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTR 1160:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTR 1161:Drivers/CMSIS/Include/core_cm7.h **** 1162:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTR 1163:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTR 1164:Drivers/CMSIS/Include/core_cm7.h **** 1165:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTR 1166:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTR 1167:Drivers/CMSIS/Include/core_cm7.h **** 1168:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTR 1169:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTR 1170:Drivers/CMSIS/Include/core_cm7.h **** ARM GAS /tmp/ccYgfTud.s page 22 1171:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTR 1172:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTR 1173:Drivers/CMSIS/Include/core_cm7.h **** 1174:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTR 1175:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTR 1176:Drivers/CMSIS/Include/core_cm7.h **** 1177:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTR 1178:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTR 1179:Drivers/CMSIS/Include/core_cm7.h **** 1180:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTR 1181:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTR 1182:Drivers/CMSIS/Include/core_cm7.h **** 1183:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTR 1184:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTR 1185:Drivers/CMSIS/Include/core_cm7.h **** 1186:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTR 1187:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTR 1188:Drivers/CMSIS/Include/core_cm7.h **** 1189:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTR 1190:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTR 1191:Drivers/CMSIS/Include/core_cm7.h **** 1192:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTR 1193:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTR 1194:Drivers/CMSIS/Include/core_cm7.h **** 1195:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTR 1196:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTR 1197:Drivers/CMSIS/Include/core_cm7.h **** 1198:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTR 1199:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTR 1200:Drivers/CMSIS/Include/core_cm7.h **** 1201:Drivers/CMSIS/Include/core_cm7.h **** /* DWT CPI Count Register Definitions */ 1202:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPI 1203:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPI 1204:Drivers/CMSIS/Include/core_cm7.h **** 1205:Drivers/CMSIS/Include/core_cm7.h **** /* DWT Exception Overhead Count Register Definitions */ 1206:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXC 1207:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXC 1208:Drivers/CMSIS/Include/core_cm7.h **** 1209:Drivers/CMSIS/Include/core_cm7.h **** /* DWT Sleep Count Register Definitions */ 1210:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLE 1211:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLE 1212:Drivers/CMSIS/Include/core_cm7.h **** 1213:Drivers/CMSIS/Include/core_cm7.h **** /* DWT LSU Count Register Definitions */ 1214:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSU 1215:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSU 1216:Drivers/CMSIS/Include/core_cm7.h **** 1217:Drivers/CMSIS/Include/core_cm7.h **** /* DWT Folded-instruction Count Register Definitions */ 1218:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOL 1219:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOL 1220:Drivers/CMSIS/Include/core_cm7.h **** 1221:Drivers/CMSIS/Include/core_cm7.h **** /* DWT Comparator Mask Register Definitions */ 1222:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_MASK_MASK_Pos 0U /*!< DWT MAS 1223:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MAS 1224:Drivers/CMSIS/Include/core_cm7.h **** 1225:Drivers/CMSIS/Include/core_cm7.h **** /* DWT Comparator Function Register Definitions */ 1226:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUN 1227:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUN ARM GAS /tmp/ccYgfTud.s page 23 1228:Drivers/CMSIS/Include/core_cm7.h **** 1229:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUN 1230:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUN 1231:Drivers/CMSIS/Include/core_cm7.h **** 1232:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUN 1233:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUN 1234:Drivers/CMSIS/Include/core_cm7.h **** 1235:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUN 1236:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUN 1237:Drivers/CMSIS/Include/core_cm7.h **** 1238:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUN 1239:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUN 1240:Drivers/CMSIS/Include/core_cm7.h **** 1241:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUN 1242:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUN 1243:Drivers/CMSIS/Include/core_cm7.h **** 1244:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUN 1245:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUN 1246:Drivers/CMSIS/Include/core_cm7.h **** 1247:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUN 1248:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUN 1249:Drivers/CMSIS/Include/core_cm7.h **** 1250:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUN 1251:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUN 1252:Drivers/CMSIS/Include/core_cm7.h **** 1253:Drivers/CMSIS/Include/core_cm7.h **** /*@}*/ /* end of group CMSIS_DWT */ 1254:Drivers/CMSIS/Include/core_cm7.h **** 1255:Drivers/CMSIS/Include/core_cm7.h **** 1256:Drivers/CMSIS/Include/core_cm7.h **** /** 1257:Drivers/CMSIS/Include/core_cm7.h **** \ingroup CMSIS_core_register 1258:Drivers/CMSIS/Include/core_cm7.h **** \defgroup CMSIS_TPI Trace Port Interface (TPI) 1259:Drivers/CMSIS/Include/core_cm7.h **** \brief Type definitions for the Trace Port Interface (TPI) 1260:Drivers/CMSIS/Include/core_cm7.h **** @{ 1261:Drivers/CMSIS/Include/core_cm7.h **** */ 1262:Drivers/CMSIS/Include/core_cm7.h **** 1263:Drivers/CMSIS/Include/core_cm7.h **** /** 1264:Drivers/CMSIS/Include/core_cm7.h **** \brief Structure type to access the Trace Port Interface Register (TPI). 1265:Drivers/CMSIS/Include/core_cm7.h **** */ 1266:Drivers/CMSIS/Include/core_cm7.h **** typedef struct 1267:Drivers/CMSIS/Include/core_cm7.h **** { 1268:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Reg 1269:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Regis 1270:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED0[2U]; 1271:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Reg 1272:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED1[55U]; 1273:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register * 1274:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED2[131U]; 1275:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Regis 1276:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Regi 1277:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counte 1278:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED3[759U]; 1279:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ 1280:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ 1281:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ 1282:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED4[1U]; 1283:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ 1284:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ ARM GAS /tmp/ccYgfTud.s page 24 1285:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ 1286:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED5[39U]; 1287:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ 1288:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ 1289:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED7[8U]; 1290:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ 1291:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ 1292:Drivers/CMSIS/Include/core_cm7.h **** } TPI_Type; 1293:Drivers/CMSIS/Include/core_cm7.h **** 1294:Drivers/CMSIS/Include/core_cm7.h **** /* TPI Asynchronous Clock Prescaler Register Definitions */ 1295:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACP 1296:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACP 1297:Drivers/CMSIS/Include/core_cm7.h **** 1298:Drivers/CMSIS/Include/core_cm7.h **** /* TPI Selected Pin Protocol Register Definitions */ 1299:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPP 1300:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPP 1301:Drivers/CMSIS/Include/core_cm7.h **** 1302:Drivers/CMSIS/Include/core_cm7.h **** /* TPI Formatter and Flush Status Register Definitions */ 1303:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFS 1304:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFS 1305:Drivers/CMSIS/Include/core_cm7.h **** 1306:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFS 1307:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFS 1308:Drivers/CMSIS/Include/core_cm7.h **** 1309:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFS 1310:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFS 1311:Drivers/CMSIS/Include/core_cm7.h **** 1312:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFS 1313:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFS 1314:Drivers/CMSIS/Include/core_cm7.h **** 1315:Drivers/CMSIS/Include/core_cm7.h **** /* TPI Formatter and Flush Control Register Definitions */ 1316:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFC 1317:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFC 1318:Drivers/CMSIS/Include/core_cm7.h **** 1319:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFC 1320:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFC 1321:Drivers/CMSIS/Include/core_cm7.h **** 1322:Drivers/CMSIS/Include/core_cm7.h **** /* TPI TRIGGER Register Definitions */ 1323:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRI 1324:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRI 1325:Drivers/CMSIS/Include/core_cm7.h **** 1326:Drivers/CMSIS/Include/core_cm7.h **** /* TPI Integration ETM Data Register Definitions (FIFO0) */ 1327:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIF 1328:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIF 1329:Drivers/CMSIS/Include/core_cm7.h **** 1330:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIF 1331:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIF 1332:Drivers/CMSIS/Include/core_cm7.h **** 1333:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIF 1334:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIF 1335:Drivers/CMSIS/Include/core_cm7.h **** 1336:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIF 1337:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIF 1338:Drivers/CMSIS/Include/core_cm7.h **** 1339:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIF 1340:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIF 1341:Drivers/CMSIS/Include/core_cm7.h **** ARM GAS /tmp/ccYgfTud.s page 25 1342:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIF 1343:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIF 1344:Drivers/CMSIS/Include/core_cm7.h **** 1345:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIF 1346:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIF 1347:Drivers/CMSIS/Include/core_cm7.h **** 1348:Drivers/CMSIS/Include/core_cm7.h **** /* TPI ITATBCTR2 Register Definitions */ 1349:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITA 1350:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITA 1351:Drivers/CMSIS/Include/core_cm7.h **** 1352:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITA 1353:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITA 1354:Drivers/CMSIS/Include/core_cm7.h **** 1355:Drivers/CMSIS/Include/core_cm7.h **** /* TPI Integration ITM Data Register Definitions (FIFO1) */ 1356:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIF 1357:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIF 1358:Drivers/CMSIS/Include/core_cm7.h **** 1359:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIF 1360:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIF 1361:Drivers/CMSIS/Include/core_cm7.h **** 1362:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIF 1363:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIF 1364:Drivers/CMSIS/Include/core_cm7.h **** 1365:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIF 1366:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIF 1367:Drivers/CMSIS/Include/core_cm7.h **** 1368:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIF 1369:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIF 1370:Drivers/CMSIS/Include/core_cm7.h **** 1371:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIF 1372:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIF 1373:Drivers/CMSIS/Include/core_cm7.h **** 1374:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIF 1375:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIF 1376:Drivers/CMSIS/Include/core_cm7.h **** 1377:Drivers/CMSIS/Include/core_cm7.h **** /* TPI ITATBCTR0 Register Definitions */ 1378:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITA 1379:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITA 1380:Drivers/CMSIS/Include/core_cm7.h **** 1381:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITA 1382:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITA 1383:Drivers/CMSIS/Include/core_cm7.h **** 1384:Drivers/CMSIS/Include/core_cm7.h **** /* TPI Integration Mode Control Register Definitions */ 1385:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITC 1386:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITC 1387:Drivers/CMSIS/Include/core_cm7.h **** 1388:Drivers/CMSIS/Include/core_cm7.h **** /* TPI DEVID Register Definitions */ 1389:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEV 1390:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEV 1391:Drivers/CMSIS/Include/core_cm7.h **** 1392:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEV 1393:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEV 1394:Drivers/CMSIS/Include/core_cm7.h **** 1395:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEV 1396:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEV 1397:Drivers/CMSIS/Include/core_cm7.h **** 1398:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEV ARM GAS /tmp/ccYgfTud.s page 26 1399:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEV 1400:Drivers/CMSIS/Include/core_cm7.h **** 1401:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEV 1402:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEV 1403:Drivers/CMSIS/Include/core_cm7.h **** 1404:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEV 1405:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEV 1406:Drivers/CMSIS/Include/core_cm7.h **** 1407:Drivers/CMSIS/Include/core_cm7.h **** /* TPI DEVTYPE Register Definitions */ 1408:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEV 1409:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEV 1410:Drivers/CMSIS/Include/core_cm7.h **** 1411:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEV 1412:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEV 1413:Drivers/CMSIS/Include/core_cm7.h **** 1414:Drivers/CMSIS/Include/core_cm7.h **** /*@}*/ /* end of group CMSIS_TPI */ 1415:Drivers/CMSIS/Include/core_cm7.h **** 1416:Drivers/CMSIS/Include/core_cm7.h **** 1417:Drivers/CMSIS/Include/core_cm7.h **** #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) 1418:Drivers/CMSIS/Include/core_cm7.h **** /** 1419:Drivers/CMSIS/Include/core_cm7.h **** \ingroup CMSIS_core_register 1420:Drivers/CMSIS/Include/core_cm7.h **** \defgroup CMSIS_MPU Memory Protection Unit (MPU) 1421:Drivers/CMSIS/Include/core_cm7.h **** \brief Type definitions for the Memory Protection Unit (MPU) 1422:Drivers/CMSIS/Include/core_cm7.h **** @{ 1423:Drivers/CMSIS/Include/core_cm7.h **** */ 1424:Drivers/CMSIS/Include/core_cm7.h **** 1425:Drivers/CMSIS/Include/core_cm7.h **** /** 1426:Drivers/CMSIS/Include/core_cm7.h **** \brief Structure type to access the Memory Protection Unit (MPU). 1427:Drivers/CMSIS/Include/core_cm7.h **** */ 1428:Drivers/CMSIS/Include/core_cm7.h **** typedef struct 1429:Drivers/CMSIS/Include/core_cm7.h **** { 1430:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ 1431:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ 1432:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ 1433:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register 1434:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Re 1435:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address 1436:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and 1437:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address 1438:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and 1439:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address 1440:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and 1441:Drivers/CMSIS/Include/core_cm7.h **** } MPU_Type; 1442:Drivers/CMSIS/Include/core_cm7.h **** 1443:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_TYPE_RALIASES 4U 1444:Drivers/CMSIS/Include/core_cm7.h **** 1445:Drivers/CMSIS/Include/core_cm7.h **** /* MPU Type Register Definitions */ 1446:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_TYPE_IREGION_Pos 16U /*!< MPU 1447:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU 1448:Drivers/CMSIS/Include/core_cm7.h **** 1449:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_TYPE_DREGION_Pos 8U /*!< MPU 1450:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU 1451:Drivers/CMSIS/Include/core_cm7.h **** 1452:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU 1453:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU 1454:Drivers/CMSIS/Include/core_cm7.h **** 1455:Drivers/CMSIS/Include/core_cm7.h **** /* MPU Control Register Definitions */ ARM GAS /tmp/ccYgfTud.s page 27 1456:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU 1457:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU 1458:Drivers/CMSIS/Include/core_cm7.h **** 1459:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU 1460:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU 1461:Drivers/CMSIS/Include/core_cm7.h **** 1462:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU 1463:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU 1464:Drivers/CMSIS/Include/core_cm7.h **** 1465:Drivers/CMSIS/Include/core_cm7.h **** /* MPU Region Number Register Definitions */ 1466:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RNR_REGION_Pos 0U /*!< MPU 1467:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU 1468:Drivers/CMSIS/Include/core_cm7.h **** 1469:Drivers/CMSIS/Include/core_cm7.h **** /* MPU Region Base Address Register Definitions */ 1470:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RBAR_ADDR_Pos 5U /*!< MPU 1471:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU 1472:Drivers/CMSIS/Include/core_cm7.h **** 1473:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RBAR_VALID_Pos 4U /*!< MPU 1474:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU 1475:Drivers/CMSIS/Include/core_cm7.h **** 1476:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RBAR_REGION_Pos 0U /*!< MPU 1477:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU 1478:Drivers/CMSIS/Include/core_cm7.h **** 1479:Drivers/CMSIS/Include/core_cm7.h **** /* MPU Region Attribute and Size Register Definitions */ 1480:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RASR_ATTRS_Pos 16U /*!< MPU 1481:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU 1482:Drivers/CMSIS/Include/core_cm7.h **** 1483:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RASR_XN_Pos 28U /*!< MPU 1484:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU 1485:Drivers/CMSIS/Include/core_cm7.h **** 1486:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RASR_AP_Pos 24U /*!< MPU 1487:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU 1488:Drivers/CMSIS/Include/core_cm7.h **** 1489:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RASR_TEX_Pos 19U /*!< MPU 1490:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU 1491:Drivers/CMSIS/Include/core_cm7.h **** 1492:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RASR_S_Pos 18U /*!< MPU 1493:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU 1494:Drivers/CMSIS/Include/core_cm7.h **** 1495:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RASR_C_Pos 17U /*!< MPU 1496:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU 1497:Drivers/CMSIS/Include/core_cm7.h **** 1498:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RASR_B_Pos 16U /*!< MPU 1499:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU 1500:Drivers/CMSIS/Include/core_cm7.h **** 1501:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RASR_SRD_Pos 8U /*!< MPU 1502:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU 1503:Drivers/CMSIS/Include/core_cm7.h **** 1504:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RASR_SIZE_Pos 1U /*!< MPU 1505:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU 1506:Drivers/CMSIS/Include/core_cm7.h **** 1507:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RASR_ENABLE_Pos 0U /*!< MPU 1508:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU 1509:Drivers/CMSIS/Include/core_cm7.h **** 1510:Drivers/CMSIS/Include/core_cm7.h **** /*@} end of group CMSIS_MPU */ 1511:Drivers/CMSIS/Include/core_cm7.h **** #endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */ 1512:Drivers/CMSIS/Include/core_cm7.h **** ARM GAS /tmp/ccYgfTud.s page 28 1513:Drivers/CMSIS/Include/core_cm7.h **** 1514:Drivers/CMSIS/Include/core_cm7.h **** /** 1515:Drivers/CMSIS/Include/core_cm7.h **** \ingroup CMSIS_core_register 1516:Drivers/CMSIS/Include/core_cm7.h **** \defgroup CMSIS_FPU Floating Point Unit (FPU) 1517:Drivers/CMSIS/Include/core_cm7.h **** \brief Type definitions for the Floating Point Unit (FPU) 1518:Drivers/CMSIS/Include/core_cm7.h **** @{ 1519:Drivers/CMSIS/Include/core_cm7.h **** */ 1520:Drivers/CMSIS/Include/core_cm7.h **** 1521:Drivers/CMSIS/Include/core_cm7.h **** /** 1522:Drivers/CMSIS/Include/core_cm7.h **** \brief Structure type to access the Floating Point Unit (FPU). 1523:Drivers/CMSIS/Include/core_cm7.h **** */ 1524:Drivers/CMSIS/Include/core_cm7.h **** typedef struct 1525:Drivers/CMSIS/Include/core_cm7.h **** { 1526:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED0[1U]; 1527:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control R 1528:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address R 1529:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Co 1530:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 1531:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 1532:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 1533:Drivers/CMSIS/Include/core_cm7.h **** } FPU_Type; 1534:Drivers/CMSIS/Include/core_cm7.h **** 1535:Drivers/CMSIS/Include/core_cm7.h **** /* Floating-Point Context Control Register Definitions */ 1536:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCC 1537:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCC 1538:Drivers/CMSIS/Include/core_cm7.h **** 1539:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCC 1540:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCC 1541:Drivers/CMSIS/Include/core_cm7.h **** 1542:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCC 1543:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCC 1544:Drivers/CMSIS/Include/core_cm7.h **** 1545:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCC 1546:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCC 1547:Drivers/CMSIS/Include/core_cm7.h **** 1548:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCC 1549:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCC 1550:Drivers/CMSIS/Include/core_cm7.h **** 1551:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCC 1552:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCC 1553:Drivers/CMSIS/Include/core_cm7.h **** 1554:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPCCR_THREAD_Pos 3U /*!< FPCC 1555:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCC 1556:Drivers/CMSIS/Include/core_cm7.h **** 1557:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPCCR_USER_Pos 1U /*!< FPCC 1558:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCC 1559:Drivers/CMSIS/Include/core_cm7.h **** 1560:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCC 1561:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCC 1562:Drivers/CMSIS/Include/core_cm7.h **** 1563:Drivers/CMSIS/Include/core_cm7.h **** /* Floating-Point Context Address Register Definitions */ 1564:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCA 1565:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCA 1566:Drivers/CMSIS/Include/core_cm7.h **** 1567:Drivers/CMSIS/Include/core_cm7.h **** /* Floating-Point Default Status Control Register Definitions */ 1568:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPDSCR_AHP_Pos 26U /*!< FPDS 1569:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDS ARM GAS /tmp/ccYgfTud.s page 29 1570:Drivers/CMSIS/Include/core_cm7.h **** 1571:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPDSCR_DN_Pos 25U /*!< FPDS 1572:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDS 1573:Drivers/CMSIS/Include/core_cm7.h **** 1574:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPDSCR_FZ_Pos 24U /*!< FPDS 1575:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDS 1576:Drivers/CMSIS/Include/core_cm7.h **** 1577:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPDSCR_RMode_Pos 22U /*!< FPDS 1578:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDS 1579:Drivers/CMSIS/Include/core_cm7.h **** 1580:Drivers/CMSIS/Include/core_cm7.h **** /* Media and FP Feature Register 0 Definitions */ 1581:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR 1582:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR 1583:Drivers/CMSIS/Include/core_cm7.h **** 1584:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR 1585:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR 1586:Drivers/CMSIS/Include/core_cm7.h **** 1587:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR 1588:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR 1589:Drivers/CMSIS/Include/core_cm7.h **** 1590:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR0_Divide_Pos 16U /*!< MVFR 1591:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR 1592:Drivers/CMSIS/Include/core_cm7.h **** 1593:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR 1594:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR 1595:Drivers/CMSIS/Include/core_cm7.h **** 1596:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR 1597:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR 1598:Drivers/CMSIS/Include/core_cm7.h **** 1599:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR 1600:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR 1601:Drivers/CMSIS/Include/core_cm7.h **** 1602:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR 1603:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR 1604:Drivers/CMSIS/Include/core_cm7.h **** 1605:Drivers/CMSIS/Include/core_cm7.h **** /* Media and FP Feature Register 1 Definitions */ 1606:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR 1607:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR 1608:Drivers/CMSIS/Include/core_cm7.h **** 1609:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR 1610:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR 1611:Drivers/CMSIS/Include/core_cm7.h **** 1612:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR 1613:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR 1614:Drivers/CMSIS/Include/core_cm7.h **** 1615:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR 1616:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR 1617:Drivers/CMSIS/Include/core_cm7.h **** 1618:Drivers/CMSIS/Include/core_cm7.h **** /* Media and FP Feature Register 2 Definitions */ 1619:Drivers/CMSIS/Include/core_cm7.h **** 1620:Drivers/CMSIS/Include/core_cm7.h **** /*@} end of group CMSIS_FPU */ 1621:Drivers/CMSIS/Include/core_cm7.h **** 1622:Drivers/CMSIS/Include/core_cm7.h **** 1623:Drivers/CMSIS/Include/core_cm7.h **** /** 1624:Drivers/CMSIS/Include/core_cm7.h **** \ingroup CMSIS_core_register 1625:Drivers/CMSIS/Include/core_cm7.h **** \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) 1626:Drivers/CMSIS/Include/core_cm7.h **** \brief Type definitions for the Core Debug Registers ARM GAS /tmp/ccYgfTud.s page 30 1627:Drivers/CMSIS/Include/core_cm7.h **** @{ 1628:Drivers/CMSIS/Include/core_cm7.h **** */ 1629:Drivers/CMSIS/Include/core_cm7.h **** 1630:Drivers/CMSIS/Include/core_cm7.h **** /** 1631:Drivers/CMSIS/Include/core_cm7.h **** \brief Structure type to access the Core Debug Register (CoreDebug). 1632:Drivers/CMSIS/Include/core_cm7.h **** */ 1633:Drivers/CMSIS/Include/core_cm7.h **** typedef struct 1634:Drivers/CMSIS/Include/core_cm7.h **** { 1635:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status 1636:Drivers/CMSIS/Include/core_cm7.h **** __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Reg 1637:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Registe 1638:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Cont 1639:Drivers/CMSIS/Include/core_cm7.h **** } CoreDebug_Type; 1640:Drivers/CMSIS/Include/core_cm7.h **** 1641:Drivers/CMSIS/Include/core_cm7.h **** /* Debug Halting Control and Status Register Definitions */ 1642:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< Core 1643:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< Core 1644:Drivers/CMSIS/Include/core_cm7.h **** 1645:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< Core 1646:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< Core 1647:Drivers/CMSIS/Include/core_cm7.h **** 1648:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< Core 1649:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< Core 1650:Drivers/CMSIS/Include/core_cm7.h **** 1651:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< Core 1652:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< Core 1653:Drivers/CMSIS/Include/core_cm7.h **** 1654:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< Core 1655:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< Core 1656:Drivers/CMSIS/Include/core_cm7.h **** 1657:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< Core 1658:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< Core 1659:Drivers/CMSIS/Include/core_cm7.h **** 1660:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< Core 1661:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< Core 1662:Drivers/CMSIS/Include/core_cm7.h **** 1663:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< Core 1664:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< Core 1665:Drivers/CMSIS/Include/core_cm7.h **** 1666:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< Core 1667:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< Core 1668:Drivers/CMSIS/Include/core_cm7.h **** 1669:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< Core 1670:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< Core 1671:Drivers/CMSIS/Include/core_cm7.h **** 1672:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< Core 1673:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< Core 1674:Drivers/CMSIS/Include/core_cm7.h **** 1675:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< Core 1676:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< Core 1677:Drivers/CMSIS/Include/core_cm7.h **** 1678:Drivers/CMSIS/Include/core_cm7.h **** /* Debug Core Register Selector Register Definitions */ 1679:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< Core 1680:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< Core 1681:Drivers/CMSIS/Include/core_cm7.h **** 1682:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< Core 1683:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< Core ARM GAS /tmp/ccYgfTud.s page 31 1684:Drivers/CMSIS/Include/core_cm7.h **** 1685:Drivers/CMSIS/Include/core_cm7.h **** /* Debug Exception and Monitor Control Register Definitions */ 1686:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< Core 1687:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< Core 1688:Drivers/CMSIS/Include/core_cm7.h **** 1689:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< Core 1690:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< Core 1691:Drivers/CMSIS/Include/core_cm7.h **** 1692:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< Core 1693:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< Core 1694:Drivers/CMSIS/Include/core_cm7.h **** 1695:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< Core 1696:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< Core 1697:Drivers/CMSIS/Include/core_cm7.h **** 1698:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< Core 1699:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< Core 1700:Drivers/CMSIS/Include/core_cm7.h **** 1701:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< Core 1702:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< Core 1703:Drivers/CMSIS/Include/core_cm7.h **** 1704:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< Core 1705:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< Core 1706:Drivers/CMSIS/Include/core_cm7.h **** 1707:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< Core 1708:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< Core 1709:Drivers/CMSIS/Include/core_cm7.h **** 1710:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< Core 1711:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< Core 1712:Drivers/CMSIS/Include/core_cm7.h **** 1713:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< Core 1714:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< Core 1715:Drivers/CMSIS/Include/core_cm7.h **** 1716:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< Core 1717:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< Core 1718:Drivers/CMSIS/Include/core_cm7.h **** 1719:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< Core 1720:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< Core 1721:Drivers/CMSIS/Include/core_cm7.h **** 1722:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< Core 1723:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< Core 1724:Drivers/CMSIS/Include/core_cm7.h **** 1725:Drivers/CMSIS/Include/core_cm7.h **** /*@} end of group CMSIS_CoreDebug */ 1726:Drivers/CMSIS/Include/core_cm7.h **** 1727:Drivers/CMSIS/Include/core_cm7.h **** 1728:Drivers/CMSIS/Include/core_cm7.h **** /** 1729:Drivers/CMSIS/Include/core_cm7.h **** \ingroup CMSIS_core_register 1730:Drivers/CMSIS/Include/core_cm7.h **** \defgroup CMSIS_core_bitfield Core register bit field macros 1731:Drivers/CMSIS/Include/core_cm7.h **** \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). 1732:Drivers/CMSIS/Include/core_cm7.h **** @{ 1733:Drivers/CMSIS/Include/core_cm7.h **** */ 1734:Drivers/CMSIS/Include/core_cm7.h **** 1735:Drivers/CMSIS/Include/core_cm7.h **** /** 1736:Drivers/CMSIS/Include/core_cm7.h **** \brief Mask and shift a bit field value for use in a register bit range. 1737:Drivers/CMSIS/Include/core_cm7.h **** \param[in] field Name of the register bit field. 1738:Drivers/CMSIS/Include/core_cm7.h **** \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. 1739:Drivers/CMSIS/Include/core_cm7.h **** \return Masked and shifted value. 1740:Drivers/CMSIS/Include/core_cm7.h **** */ ARM GAS /tmp/ccYgfTud.s page 32 1741:Drivers/CMSIS/Include/core_cm7.h **** #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) 1742:Drivers/CMSIS/Include/core_cm7.h **** 1743:Drivers/CMSIS/Include/core_cm7.h **** /** 1744:Drivers/CMSIS/Include/core_cm7.h **** \brief Mask and shift a register value to extract a bit filed value. 1745:Drivers/CMSIS/Include/core_cm7.h **** \param[in] field Name of the register bit field. 1746:Drivers/CMSIS/Include/core_cm7.h **** \param[in] value Value of register. This parameter is interpreted as an uint32_t type. 1747:Drivers/CMSIS/Include/core_cm7.h **** \return Masked and shifted bit field value. 1748:Drivers/CMSIS/Include/core_cm7.h **** */ 1749:Drivers/CMSIS/Include/core_cm7.h **** #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) 1750:Drivers/CMSIS/Include/core_cm7.h **** 1751:Drivers/CMSIS/Include/core_cm7.h **** /*@} end of group CMSIS_core_bitfield */ 1752:Drivers/CMSIS/Include/core_cm7.h **** 1753:Drivers/CMSIS/Include/core_cm7.h **** 1754:Drivers/CMSIS/Include/core_cm7.h **** /** 1755:Drivers/CMSIS/Include/core_cm7.h **** \ingroup CMSIS_core_register 1756:Drivers/CMSIS/Include/core_cm7.h **** \defgroup CMSIS_core_base Core Definitions 1757:Drivers/CMSIS/Include/core_cm7.h **** \brief Definitions for base addresses, unions, and structures. 1758:Drivers/CMSIS/Include/core_cm7.h **** @{ 1759:Drivers/CMSIS/Include/core_cm7.h **** */ 1760:Drivers/CMSIS/Include/core_cm7.h **** 1761:Drivers/CMSIS/Include/core_cm7.h **** /* Memory mapping of Core Hardware */ 1762:Drivers/CMSIS/Include/core_cm7.h **** #define SCS_BASE (0xE000E000UL) /*!< System Control Space Bas 1763:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ 1764:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ 1765:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ 1766:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address 1767:Drivers/CMSIS/Include/core_cm7.h **** #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ 1768:Drivers/CMSIS/Include/core_cm7.h **** #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ 1769:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Bas 1770:Drivers/CMSIS/Include/core_cm7.h **** 1771:Drivers/CMSIS/Include/core_cm7.h **** #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register 1772:Drivers/CMSIS/Include/core_cm7.h **** #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct 1773:Drivers/CMSIS/Include/core_cm7.h **** #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration st 1774:Drivers/CMSIS/Include/core_cm7.h **** #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struc 1775:Drivers/CMSIS/Include/core_cm7.h **** #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct 1776:Drivers/CMSIS/Include/core_cm7.h **** #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct 1777:Drivers/CMSIS/Include/core_cm7.h **** #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct 1778:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration 1779:Drivers/CMSIS/Include/core_cm7.h **** 1780:Drivers/CMSIS/Include/core_cm7.h **** #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) 1781:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit * 1782:Drivers/CMSIS/Include/core_cm7.h **** #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit * 1783:Drivers/CMSIS/Include/core_cm7.h **** #endif 1784:Drivers/CMSIS/Include/core_cm7.h **** 1785:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ 1786:Drivers/CMSIS/Include/core_cm7.h **** #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ 1787:Drivers/CMSIS/Include/core_cm7.h **** 1788:Drivers/CMSIS/Include/core_cm7.h **** /*@} */ 1789:Drivers/CMSIS/Include/core_cm7.h **** 1790:Drivers/CMSIS/Include/core_cm7.h **** 1791:Drivers/CMSIS/Include/core_cm7.h **** 1792:Drivers/CMSIS/Include/core_cm7.h **** /******************************************************************************* 1793:Drivers/CMSIS/Include/core_cm7.h **** * Hardware Abstraction Layer 1794:Drivers/CMSIS/Include/core_cm7.h **** Core Function Interface contains: 1795:Drivers/CMSIS/Include/core_cm7.h **** - Core NVIC Functions 1796:Drivers/CMSIS/Include/core_cm7.h **** - Core SysTick Functions 1797:Drivers/CMSIS/Include/core_cm7.h **** - Core Debug Functions ARM GAS /tmp/ccYgfTud.s page 33 1798:Drivers/CMSIS/Include/core_cm7.h **** - Core Register Access Functions 1799:Drivers/CMSIS/Include/core_cm7.h **** ******************************************************************************/ 1800:Drivers/CMSIS/Include/core_cm7.h **** /** 1801:Drivers/CMSIS/Include/core_cm7.h **** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference 1802:Drivers/CMSIS/Include/core_cm7.h **** */ 1803:Drivers/CMSIS/Include/core_cm7.h **** 1804:Drivers/CMSIS/Include/core_cm7.h **** 1805:Drivers/CMSIS/Include/core_cm7.h **** 1806:Drivers/CMSIS/Include/core_cm7.h **** /* ########################## NVIC functions #################################### */ 1807:Drivers/CMSIS/Include/core_cm7.h **** /** 1808:Drivers/CMSIS/Include/core_cm7.h **** \ingroup CMSIS_Core_FunctionInterface 1809:Drivers/CMSIS/Include/core_cm7.h **** \defgroup CMSIS_Core_NVICFunctions NVIC Functions 1810:Drivers/CMSIS/Include/core_cm7.h **** \brief Functions that manage interrupts and exceptions via the NVIC. 1811:Drivers/CMSIS/Include/core_cm7.h **** @{ 1812:Drivers/CMSIS/Include/core_cm7.h **** */ 1813:Drivers/CMSIS/Include/core_cm7.h **** 1814:Drivers/CMSIS/Include/core_cm7.h **** #ifdef CMSIS_NVIC_VIRTUAL 1815:Drivers/CMSIS/Include/core_cm7.h **** #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE 1816:Drivers/CMSIS/Include/core_cm7.h **** #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" 1817:Drivers/CMSIS/Include/core_cm7.h **** #endif 1818:Drivers/CMSIS/Include/core_cm7.h **** #include CMSIS_NVIC_VIRTUAL_HEADER_FILE 1819:Drivers/CMSIS/Include/core_cm7.h **** #else 1820:Drivers/CMSIS/Include/core_cm7.h **** #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping 1821:Drivers/CMSIS/Include/core_cm7.h **** #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping 1822:Drivers/CMSIS/Include/core_cm7.h **** #define NVIC_EnableIRQ __NVIC_EnableIRQ 1823:Drivers/CMSIS/Include/core_cm7.h **** #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ 1824:Drivers/CMSIS/Include/core_cm7.h **** #define NVIC_DisableIRQ __NVIC_DisableIRQ 1825:Drivers/CMSIS/Include/core_cm7.h **** #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ 1826:Drivers/CMSIS/Include/core_cm7.h **** #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ 1827:Drivers/CMSIS/Include/core_cm7.h **** #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ 1828:Drivers/CMSIS/Include/core_cm7.h **** #define NVIC_GetActive __NVIC_GetActive 1829:Drivers/CMSIS/Include/core_cm7.h **** #define NVIC_SetPriority __NVIC_SetPriority 1830:Drivers/CMSIS/Include/core_cm7.h **** #define NVIC_GetPriority __NVIC_GetPriority 1831:Drivers/CMSIS/Include/core_cm7.h **** #define NVIC_SystemReset __NVIC_SystemReset 1832:Drivers/CMSIS/Include/core_cm7.h **** #endif /* CMSIS_NVIC_VIRTUAL */ 1833:Drivers/CMSIS/Include/core_cm7.h **** 1834:Drivers/CMSIS/Include/core_cm7.h **** #ifdef CMSIS_VECTAB_VIRTUAL 1835:Drivers/CMSIS/Include/core_cm7.h **** #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE 1836:Drivers/CMSIS/Include/core_cm7.h **** #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" 1837:Drivers/CMSIS/Include/core_cm7.h **** #endif 1838:Drivers/CMSIS/Include/core_cm7.h **** #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE 1839:Drivers/CMSIS/Include/core_cm7.h **** #else 1840:Drivers/CMSIS/Include/core_cm7.h **** #define NVIC_SetVector __NVIC_SetVector 1841:Drivers/CMSIS/Include/core_cm7.h **** #define NVIC_GetVector __NVIC_GetVector 1842:Drivers/CMSIS/Include/core_cm7.h **** #endif /* (CMSIS_VECTAB_VIRTUAL) */ 1843:Drivers/CMSIS/Include/core_cm7.h **** 1844:Drivers/CMSIS/Include/core_cm7.h **** #define NVIC_USER_IRQ_OFFSET 16 1845:Drivers/CMSIS/Include/core_cm7.h **** 1846:Drivers/CMSIS/Include/core_cm7.h **** 1847:Drivers/CMSIS/Include/core_cm7.h **** /* The following EXC_RETURN values are saved the LR on exception entry */ 1848:Drivers/CMSIS/Include/core_cm7.h **** #define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after ret 1849:Drivers/CMSIS/Include/core_cm7.h **** #define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after retu 1850:Drivers/CMSIS/Include/core_cm7.h **** #define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after retu 1851:Drivers/CMSIS/Include/core_cm7.h **** #define EXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after ret 1852:Drivers/CMSIS/Include/core_cm7.h **** #define EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after retu 1853:Drivers/CMSIS/Include/core_cm7.h **** #define EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after retu 1854:Drivers/CMSIS/Include/core_cm7.h **** ARM GAS /tmp/ccYgfTud.s page 34 1855:Drivers/CMSIS/Include/core_cm7.h **** 1856:Drivers/CMSIS/Include/core_cm7.h **** /** 1857:Drivers/CMSIS/Include/core_cm7.h **** \brief Set Priority Grouping 1858:Drivers/CMSIS/Include/core_cm7.h **** \details Sets the priority grouping field using the required unlock sequence. 1859:Drivers/CMSIS/Include/core_cm7.h **** The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. 1860:Drivers/CMSIS/Include/core_cm7.h **** Only values from 0..7 are used. 1861:Drivers/CMSIS/Include/core_cm7.h **** In case of a conflict between priority grouping and available 1862:Drivers/CMSIS/Include/core_cm7.h **** priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. 1863:Drivers/CMSIS/Include/core_cm7.h **** \param [in] PriorityGroup Priority grouping field. 1864:Drivers/CMSIS/Include/core_cm7.h **** */ 1865:Drivers/CMSIS/Include/core_cm7.h **** __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) 1866:Drivers/CMSIS/Include/core_cm7.h **** { 1867:Drivers/CMSIS/Include/core_cm7.h **** uint32_t reg_value; 1868:Drivers/CMSIS/Include/core_cm7.h **** uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 a 1869:Drivers/CMSIS/Include/core_cm7.h **** 1870:Drivers/CMSIS/Include/core_cm7.h **** reg_value = SCB->AIRCR; /* read old register 1871:Drivers/CMSIS/Include/core_cm7.h **** reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to chan 1872:Drivers/CMSIS/Include/core_cm7.h **** reg_value = (reg_value | 1873:Drivers/CMSIS/Include/core_cm7.h **** ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | 1874:Drivers/CMSIS/Include/core_cm7.h **** (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key a 1875:Drivers/CMSIS/Include/core_cm7.h **** SCB->AIRCR = reg_value; 1876:Drivers/CMSIS/Include/core_cm7.h **** } 1877:Drivers/CMSIS/Include/core_cm7.h **** 1878:Drivers/CMSIS/Include/core_cm7.h **** 1879:Drivers/CMSIS/Include/core_cm7.h **** /** 1880:Drivers/CMSIS/Include/core_cm7.h **** \brief Get Priority Grouping 1881:Drivers/CMSIS/Include/core_cm7.h **** \details Reads the priority grouping field from the NVIC Interrupt Controller. 1882:Drivers/CMSIS/Include/core_cm7.h **** \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). 1883:Drivers/CMSIS/Include/core_cm7.h **** */ 1884:Drivers/CMSIS/Include/core_cm7.h **** __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) 1885:Drivers/CMSIS/Include/core_cm7.h **** { 1886:Drivers/CMSIS/Include/core_cm7.h **** return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); 1887:Drivers/CMSIS/Include/core_cm7.h **** } 1888:Drivers/CMSIS/Include/core_cm7.h **** 1889:Drivers/CMSIS/Include/core_cm7.h **** 1890:Drivers/CMSIS/Include/core_cm7.h **** /** 1891:Drivers/CMSIS/Include/core_cm7.h **** \brief Enable Interrupt 1892:Drivers/CMSIS/Include/core_cm7.h **** \details Enables a device specific interrupt in the NVIC interrupt controller. 1893:Drivers/CMSIS/Include/core_cm7.h **** \param [in] IRQn Device specific interrupt number. 1894:Drivers/CMSIS/Include/core_cm7.h **** \note IRQn must not be negative. 1895:Drivers/CMSIS/Include/core_cm7.h **** */ 1896:Drivers/CMSIS/Include/core_cm7.h **** __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) 1897:Drivers/CMSIS/Include/core_cm7.h **** { 1898:Drivers/CMSIS/Include/core_cm7.h **** if ((int32_t)(IRQn) >= 0) 1899:Drivers/CMSIS/Include/core_cm7.h **** { 1900:Drivers/CMSIS/Include/core_cm7.h **** NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 1901:Drivers/CMSIS/Include/core_cm7.h **** } 1902:Drivers/CMSIS/Include/core_cm7.h **** } 1903:Drivers/CMSIS/Include/core_cm7.h **** 1904:Drivers/CMSIS/Include/core_cm7.h **** 1905:Drivers/CMSIS/Include/core_cm7.h **** /** 1906:Drivers/CMSIS/Include/core_cm7.h **** \brief Get Interrupt Enable status 1907:Drivers/CMSIS/Include/core_cm7.h **** \details Returns a device specific interrupt enable status from the NVIC interrupt controller. 1908:Drivers/CMSIS/Include/core_cm7.h **** \param [in] IRQn Device specific interrupt number. 1909:Drivers/CMSIS/Include/core_cm7.h **** \return 0 Interrupt is not enabled. 1910:Drivers/CMSIS/Include/core_cm7.h **** \return 1 Interrupt is enabled. 1911:Drivers/CMSIS/Include/core_cm7.h **** \note IRQn must not be negative. ARM GAS /tmp/ccYgfTud.s page 35 1912:Drivers/CMSIS/Include/core_cm7.h **** */ 1913:Drivers/CMSIS/Include/core_cm7.h **** __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) 1914:Drivers/CMSIS/Include/core_cm7.h **** { 1915:Drivers/CMSIS/Include/core_cm7.h **** if ((int32_t)(IRQn) >= 0) 1916:Drivers/CMSIS/Include/core_cm7.h **** { 1917:Drivers/CMSIS/Include/core_cm7.h **** return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL) 1918:Drivers/CMSIS/Include/core_cm7.h **** } 1919:Drivers/CMSIS/Include/core_cm7.h **** else 1920:Drivers/CMSIS/Include/core_cm7.h **** { 1921:Drivers/CMSIS/Include/core_cm7.h **** return(0U); 1922:Drivers/CMSIS/Include/core_cm7.h **** } 1923:Drivers/CMSIS/Include/core_cm7.h **** } 1924:Drivers/CMSIS/Include/core_cm7.h **** 1925:Drivers/CMSIS/Include/core_cm7.h **** 1926:Drivers/CMSIS/Include/core_cm7.h **** /** 1927:Drivers/CMSIS/Include/core_cm7.h **** \brief Disable Interrupt 1928:Drivers/CMSIS/Include/core_cm7.h **** \details Disables a device specific interrupt in the NVIC interrupt controller. 1929:Drivers/CMSIS/Include/core_cm7.h **** \param [in] IRQn Device specific interrupt number. 1930:Drivers/CMSIS/Include/core_cm7.h **** \note IRQn must not be negative. 1931:Drivers/CMSIS/Include/core_cm7.h **** */ 1932:Drivers/CMSIS/Include/core_cm7.h **** __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) 1933:Drivers/CMSIS/Include/core_cm7.h **** { 1934:Drivers/CMSIS/Include/core_cm7.h **** if ((int32_t)(IRQn) >= 0) 1935:Drivers/CMSIS/Include/core_cm7.h **** { 1936:Drivers/CMSIS/Include/core_cm7.h **** NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 1937:Drivers/CMSIS/Include/core_cm7.h **** __DSB(); 1938:Drivers/CMSIS/Include/core_cm7.h **** __ISB(); 1939:Drivers/CMSIS/Include/core_cm7.h **** } 1940:Drivers/CMSIS/Include/core_cm7.h **** } 1941:Drivers/CMSIS/Include/core_cm7.h **** 1942:Drivers/CMSIS/Include/core_cm7.h **** 1943:Drivers/CMSIS/Include/core_cm7.h **** /** 1944:Drivers/CMSIS/Include/core_cm7.h **** \brief Get Pending Interrupt 1945:Drivers/CMSIS/Include/core_cm7.h **** \details Reads the NVIC pending register and returns the pending bit for the specified device spe 1946:Drivers/CMSIS/Include/core_cm7.h **** \param [in] IRQn Device specific interrupt number. 1947:Drivers/CMSIS/Include/core_cm7.h **** \return 0 Interrupt status is not pending. 1948:Drivers/CMSIS/Include/core_cm7.h **** \return 1 Interrupt status is pending. 1949:Drivers/CMSIS/Include/core_cm7.h **** \note IRQn must not be negative. 1950:Drivers/CMSIS/Include/core_cm7.h **** */ 1951:Drivers/CMSIS/Include/core_cm7.h **** __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) 1952:Drivers/CMSIS/Include/core_cm7.h **** { 1953:Drivers/CMSIS/Include/core_cm7.h **** if ((int32_t)(IRQn) >= 0) 1954:Drivers/CMSIS/Include/core_cm7.h **** { 1955:Drivers/CMSIS/Include/core_cm7.h **** return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL) 1956:Drivers/CMSIS/Include/core_cm7.h **** } 1957:Drivers/CMSIS/Include/core_cm7.h **** else 1958:Drivers/CMSIS/Include/core_cm7.h **** { 1959:Drivers/CMSIS/Include/core_cm7.h **** return(0U); 1960:Drivers/CMSIS/Include/core_cm7.h **** } 1961:Drivers/CMSIS/Include/core_cm7.h **** } 1962:Drivers/CMSIS/Include/core_cm7.h **** 1963:Drivers/CMSIS/Include/core_cm7.h **** 1964:Drivers/CMSIS/Include/core_cm7.h **** /** 1965:Drivers/CMSIS/Include/core_cm7.h **** \brief Set Pending Interrupt 1966:Drivers/CMSIS/Include/core_cm7.h **** \details Sets the pending bit of a device specific interrupt in the NVIC pending register. 1967:Drivers/CMSIS/Include/core_cm7.h **** \param [in] IRQn Device specific interrupt number. 1968:Drivers/CMSIS/Include/core_cm7.h **** \note IRQn must not be negative. ARM GAS /tmp/ccYgfTud.s page 36 1969:Drivers/CMSIS/Include/core_cm7.h **** */ 1970:Drivers/CMSIS/Include/core_cm7.h **** __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) 1971:Drivers/CMSIS/Include/core_cm7.h **** { 1972:Drivers/CMSIS/Include/core_cm7.h **** if ((int32_t)(IRQn) >= 0) 1973:Drivers/CMSIS/Include/core_cm7.h **** { 1974:Drivers/CMSIS/Include/core_cm7.h **** NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 1975:Drivers/CMSIS/Include/core_cm7.h **** } 1976:Drivers/CMSIS/Include/core_cm7.h **** } 1977:Drivers/CMSIS/Include/core_cm7.h **** 1978:Drivers/CMSIS/Include/core_cm7.h **** 1979:Drivers/CMSIS/Include/core_cm7.h **** /** 1980:Drivers/CMSIS/Include/core_cm7.h **** \brief Clear Pending Interrupt 1981:Drivers/CMSIS/Include/core_cm7.h **** \details Clears the pending bit of a device specific interrupt in the NVIC pending register. 1982:Drivers/CMSIS/Include/core_cm7.h **** \param [in] IRQn Device specific interrupt number. 1983:Drivers/CMSIS/Include/core_cm7.h **** \note IRQn must not be negative. 1984:Drivers/CMSIS/Include/core_cm7.h **** */ 1985:Drivers/CMSIS/Include/core_cm7.h **** __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) 1986:Drivers/CMSIS/Include/core_cm7.h **** { 1987:Drivers/CMSIS/Include/core_cm7.h **** if ((int32_t)(IRQn) >= 0) 1988:Drivers/CMSIS/Include/core_cm7.h **** { 1989:Drivers/CMSIS/Include/core_cm7.h **** NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 1990:Drivers/CMSIS/Include/core_cm7.h **** } 1991:Drivers/CMSIS/Include/core_cm7.h **** } 1992:Drivers/CMSIS/Include/core_cm7.h **** 1993:Drivers/CMSIS/Include/core_cm7.h **** 1994:Drivers/CMSIS/Include/core_cm7.h **** /** 1995:Drivers/CMSIS/Include/core_cm7.h **** \brief Get Active Interrupt 1996:Drivers/CMSIS/Include/core_cm7.h **** \details Reads the active register in the NVIC and returns the active bit for the device specific 1997:Drivers/CMSIS/Include/core_cm7.h **** \param [in] IRQn Device specific interrupt number. 1998:Drivers/CMSIS/Include/core_cm7.h **** \return 0 Interrupt status is not active. 1999:Drivers/CMSIS/Include/core_cm7.h **** \return 1 Interrupt status is active. 2000:Drivers/CMSIS/Include/core_cm7.h **** \note IRQn must not be negative. 2001:Drivers/CMSIS/Include/core_cm7.h **** */ 2002:Drivers/CMSIS/Include/core_cm7.h **** __STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) 2003:Drivers/CMSIS/Include/core_cm7.h **** { 2004:Drivers/CMSIS/Include/core_cm7.h **** if ((int32_t)(IRQn) >= 0) 2005:Drivers/CMSIS/Include/core_cm7.h **** { 2006:Drivers/CMSIS/Include/core_cm7.h **** return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL) 2007:Drivers/CMSIS/Include/core_cm7.h **** } 2008:Drivers/CMSIS/Include/core_cm7.h **** else 2009:Drivers/CMSIS/Include/core_cm7.h **** { 2010:Drivers/CMSIS/Include/core_cm7.h **** return(0U); 2011:Drivers/CMSIS/Include/core_cm7.h **** } 2012:Drivers/CMSIS/Include/core_cm7.h **** } 2013:Drivers/CMSIS/Include/core_cm7.h **** 2014:Drivers/CMSIS/Include/core_cm7.h **** 2015:Drivers/CMSIS/Include/core_cm7.h **** /** 2016:Drivers/CMSIS/Include/core_cm7.h **** \brief Set Interrupt Priority 2017:Drivers/CMSIS/Include/core_cm7.h **** \details Sets the priority of a device specific interrupt or a processor exception. 2018:Drivers/CMSIS/Include/core_cm7.h **** The interrupt number can be positive to specify a device specific interrupt, 2019:Drivers/CMSIS/Include/core_cm7.h **** or negative to specify a processor exception. 2020:Drivers/CMSIS/Include/core_cm7.h **** \param [in] IRQn Interrupt number. 2021:Drivers/CMSIS/Include/core_cm7.h **** \param [in] priority Priority to set. 2022:Drivers/CMSIS/Include/core_cm7.h **** \note The priority cannot be set for every processor exception. 2023:Drivers/CMSIS/Include/core_cm7.h **** */ 2024:Drivers/CMSIS/Include/core_cm7.h **** __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) 2025:Drivers/CMSIS/Include/core_cm7.h **** { ARM GAS /tmp/ccYgfTud.s page 37 2026:Drivers/CMSIS/Include/core_cm7.h **** if ((int32_t)(IRQn) >= 0) 2027:Drivers/CMSIS/Include/core_cm7.h **** { 2028:Drivers/CMSIS/Include/core_cm7.h **** NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & ( 2029:Drivers/CMSIS/Include/core_cm7.h **** } 2030:Drivers/CMSIS/Include/core_cm7.h **** else 2031:Drivers/CMSIS/Include/core_cm7.h **** { 2032:Drivers/CMSIS/Include/core_cm7.h **** SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & ( 2033:Drivers/CMSIS/Include/core_cm7.h **** } 2034:Drivers/CMSIS/Include/core_cm7.h **** } 2035:Drivers/CMSIS/Include/core_cm7.h **** 2036:Drivers/CMSIS/Include/core_cm7.h **** 2037:Drivers/CMSIS/Include/core_cm7.h **** /** 2038:Drivers/CMSIS/Include/core_cm7.h **** \brief Get Interrupt Priority 2039:Drivers/CMSIS/Include/core_cm7.h **** \details Reads the priority of a device specific interrupt or a processor exception. 2040:Drivers/CMSIS/Include/core_cm7.h **** The interrupt number can be positive to specify a device specific interrupt, 2041:Drivers/CMSIS/Include/core_cm7.h **** or negative to specify a processor exception. 2042:Drivers/CMSIS/Include/core_cm7.h **** \param [in] IRQn Interrupt number. 2043:Drivers/CMSIS/Include/core_cm7.h **** \return Interrupt Priority. 2044:Drivers/CMSIS/Include/core_cm7.h **** Value is aligned automatically to the implemented priority bits of the microc 2045:Drivers/CMSIS/Include/core_cm7.h **** */ 2046:Drivers/CMSIS/Include/core_cm7.h **** __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) 2047:Drivers/CMSIS/Include/core_cm7.h **** { 2048:Drivers/CMSIS/Include/core_cm7.h **** 2049:Drivers/CMSIS/Include/core_cm7.h **** if ((int32_t)(IRQn) >= 0) 2050:Drivers/CMSIS/Include/core_cm7.h **** { 2051:Drivers/CMSIS/Include/core_cm7.h **** return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); 2052:Drivers/CMSIS/Include/core_cm7.h **** } 2053:Drivers/CMSIS/Include/core_cm7.h **** else 2054:Drivers/CMSIS/Include/core_cm7.h **** { 2055:Drivers/CMSIS/Include/core_cm7.h **** return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); 2056:Drivers/CMSIS/Include/core_cm7.h **** } 2057:Drivers/CMSIS/Include/core_cm7.h **** } 2058:Drivers/CMSIS/Include/core_cm7.h **** 2059:Drivers/CMSIS/Include/core_cm7.h **** 2060:Drivers/CMSIS/Include/core_cm7.h **** /** 2061:Drivers/CMSIS/Include/core_cm7.h **** \brief Encode Priority 2062:Drivers/CMSIS/Include/core_cm7.h **** \details Encodes the priority for an interrupt with the given priority group, 2063:Drivers/CMSIS/Include/core_cm7.h **** preemptive priority value, and subpriority value. 2064:Drivers/CMSIS/Include/core_cm7.h **** In case of a conflict between priority grouping and available 2065:Drivers/CMSIS/Include/core_cm7.h **** priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. 2066:Drivers/CMSIS/Include/core_cm7.h **** \param [in] PriorityGroup Used priority group. 2067:Drivers/CMSIS/Include/core_cm7.h **** \param [in] PreemptPriority Preemptive priority value (starting from 0). 2068:Drivers/CMSIS/Include/core_cm7.h **** \param [in] SubPriority Subpriority value (starting from 0). 2069:Drivers/CMSIS/Include/core_cm7.h **** \return Encoded priority. Value can be used in the function \ref NVIC_SetP 2070:Drivers/CMSIS/Include/core_cm7.h **** */ 2071:Drivers/CMSIS/Include/core_cm7.h **** __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uin 2072:Drivers/CMSIS/Include/core_cm7.h **** { 29 .loc 2 2072 1 view -0 30 .cfi_startproc 31 @ args = 0, pretend = 0, frame = 0 32 @ frame_needed = 0, uses_anonymous_args = 0 33 .loc 2 2072 1 is_stmt 0 view .LVU1 34 0000 00B5 push {lr} 35 .LCFI0: 36 .cfi_def_cfa_offset 4 37 .cfi_offset 14, -4 2073:Drivers/CMSIS/Include/core_cm7.h **** uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used ARM GAS /tmp/ccYgfTud.s page 38 38 .loc 2 2073 3 is_stmt 1 view .LVU2 39 .loc 2 2073 12 is_stmt 0 view .LVU3 40 0002 00F00700 and r0, r0, #7 41 .LVL1: 2074:Drivers/CMSIS/Include/core_cm7.h **** uint32_t PreemptPriorityBits; 42 .loc 2 2074 3 is_stmt 1 view .LVU4 2075:Drivers/CMSIS/Include/core_cm7.h **** uint32_t SubPriorityBits; 43 .loc 2 2075 3 view .LVU5 2076:Drivers/CMSIS/Include/core_cm7.h **** 2077:Drivers/CMSIS/Include/core_cm7.h **** PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NV 44 .loc 2 2077 3 view .LVU6 45 .loc 2 2077 31 is_stmt 0 view .LVU7 46 0006 C0F1070C rsb ip, r0, #7 47 .loc 2 2077 23 view .LVU8 48 000a BCF1040F cmp ip, #4 49 000e 28BF it cs 50 0010 4FF0040C movcs ip, #4 51 .LVL2: 2078:Drivers/CMSIS/Include/core_cm7.h **** SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint 52 .loc 2 2078 3 is_stmt 1 view .LVU9 53 .loc 2 2078 44 is_stmt 0 view .LVU10 54 0014 031D adds r3, r0, #4 55 .loc 2 2078 109 view .LVU11 56 0016 062B cmp r3, #6 57 0018 0FD9 bls .L3 58 .loc 2 2078 109 discriminator 1 view .LVU12 59 001a C31E subs r3, r0, #3 60 .L2: 61 .LVL3: 2079:Drivers/CMSIS/Include/core_cm7.h **** 2080:Drivers/CMSIS/Include/core_cm7.h **** return ( 62 .loc 2 2080 3 is_stmt 1 view .LVU13 2081:Drivers/CMSIS/Include/core_cm7.h **** ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits 63 .loc 2 2081 30 is_stmt 0 view .LVU14 64 001c 4FF0FF3E mov lr, #-1 65 0020 0EFA0CF0 lsl r0, lr, ip 66 .LVL4: 67 .loc 2 2081 30 view .LVU15 68 0024 21EA0001 bic r1, r1, r0 69 .LVL5: 70 .loc 2 2081 82 view .LVU16 71 0028 9940 lsls r1, r1, r3 2082:Drivers/CMSIS/Include/core_cm7.h **** ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) 72 .loc 2 2082 30 view .LVU17 73 002a 0EFA03FE lsl lr, lr, r3 74 002e 22EA0E02 bic r2, r2, lr 75 .LVL6: 2083:Drivers/CMSIS/Include/core_cm7.h **** ); 2084:Drivers/CMSIS/Include/core_cm7.h **** } 76 .loc 2 2084 1 view .LVU18 77 0032 41EA0200 orr r0, r1, r2 78 0036 5DF804FB ldr pc, [sp], #4 79 .LVL7: 80 .L3: 2078:Drivers/CMSIS/Include/core_cm7.h **** 81 .loc 2 2078 109 discriminator 2 view .LVU19 82 003a 0023 movs r3, #0 ARM GAS /tmp/ccYgfTud.s page 39 83 003c EEE7 b .L2 84 .cfi_endproc 85 .LFE113: 87 .section .text.MX_SDMMC1_SD_Init,"ax",%progbits 88 .align 1 89 .syntax unified 90 .thumb 91 .thumb_func 93 MX_SDMMC1_SD_Init: 94 .LFB1190: 1:Src/main.c **** /* USER CODE BEGIN Header */ 2:Src/main.c **** /** 3:Src/main.c **** ****************************************************************************** 4:Src/main.c **** * @file : main.c 5:Src/main.c **** * @brief : Main program body 6:Src/main.c **** ****************************************************************************** 7:Src/main.c **** * @attention 8:Src/main.c **** * 9:Src/main.c **** * Copyright (c) 2023 STMicroelectronics. 10:Src/main.c **** * All rights reserved. 11:Src/main.c **** * 12:Src/main.c **** * This software is licensed under terms that can be found in the LICENSE file 13:Src/main.c **** * in the root directory of this software component. 14:Src/main.c **** * If no LICENSE file comes with this software, it is provided AS-IS. 15:Src/main.c **** * 16:Src/main.c **** ****************************************************************************** 17:Src/main.c **** */ 18:Src/main.c **** /* USER CODE END Header */ 19:Src/main.c **** /* Includes ------------------------------------------------------------------*/ 20:Src/main.c **** #include "main.h" 21:Src/main.c **** #include "fatfs.h" 22:Src/main.c **** 23:Src/main.c **** /* Private includes ----------------------------------------------------------*/ 24:Src/main.c **** /* USER CODE BEGIN Includes */ 25:Src/main.c **** // #include "math.h" 26:Src/main.c **** #include "File_Handling.h" 27:Src/main.c **** #include 28:Src/main.c **** /* USER CODE END Includes */ 29:Src/main.c **** 30:Src/main.c **** /* Private typedef -----------------------------------------------------------*/ 31:Src/main.c **** /* USER CODE BEGIN PTD */ 32:Src/main.c **** 33:Src/main.c **** /* USER CODE END PTD */ 34:Src/main.c **** 35:Src/main.c **** /* Private define ------------------------------------------------------------*/ 36:Src/main.c **** /* USER CODE BEGIN PD */ 37:Src/main.c **** // AD9102 register addresses and bit fields (see ad9102.pdf) 38:Src/main.c **** #define AD9102_REG_RAMUPDATE 0x001Du 39:Src/main.c **** #define AD9102_REG_PAT_STATUS 0x001Eu 40:Src/main.c **** #define AD9102_REG_PAT_TYPE 0x001Fu 41:Src/main.c **** #define AD9102_REG_SPICONFIG 0x0000u 42:Src/main.c **** #define AD9102_REG_POWERCONFIG 0x0001u 43:Src/main.c **** #define AD9102_REG_CLOCKCONFIG 0x0002u 44:Src/main.c **** #define AD9102_REG_WAV_CONFIG 0x0027u 45:Src/main.c **** #define AD9102_REG_PAT_TIMEBASE 0x0028u 46:Src/main.c **** #define AD9102_REG_PAT_PERIOD 0x0029u 47:Src/main.c **** #define AD9102_REG_SAW_CONFIG 0x0037u ARM GAS /tmp/ccYgfTud.s page 40 48:Src/main.c **** #define AD9102_REG_CFG_ERROR 0x0060u 49:Src/main.c **** 50:Src/main.c **** #define AD9102_PAT_STATUS_RUN (1u << 0) 51:Src/main.c **** 52:Src/main.c **** #define AD9102_WAV_PRESTORE_SEL_SHIFT 4 53:Src/main.c **** #define AD9102_WAV_WAVE_SEL_SHIFT 0 54:Src/main.c **** #define AD9102_WAV_PRESTORE_SAW 1u 55:Src/main.c **** #define AD9102_WAV_WAVE_SEL_PRESTORE 1u 56:Src/main.c **** 57:Src/main.c **** #define AD9102_SAW_STEP_SHIFT 2 58:Src/main.c **** #define AD9102_SAW_TYPE_SHIFT 0 59:Src/main.c **** #define AD9102_SAW_TYPE_UP 0u 60:Src/main.c **** #define AD9102_SAW_TYPE_DOWN 1u 61:Src/main.c **** #define AD9102_SAW_TYPE_TRI 2u 62:Src/main.c **** #define AD9102_SAW_TYPE_ZERO 3u 63:Src/main.c **** 64:Src/main.c **** #define AD9102_REG_COUNT 66u 65:Src/main.c **** 66:Src/main.c **** #define AD9102_EX4_WAV_CONFIG 0x3212u 67:Src/main.c **** #define AD9102_EX4_PAT_TIMEBASE 0x0121u 68:Src/main.c **** #define AD9102_EX4_PAT_PERIOD 0xFFFFu 69:Src/main.c **** #define AD9102_EX4_SAW_CONFIG 0x0606u 70:Src/main.c **** 71:Src/main.c **** #define AD9102_SAW_STEP_DEFAULT 1u 72:Src/main.c **** #define AD9102_PAT_PERIOD_BASE_DEFAULT 0x2u 73:Src/main.c **** #define AD9102_START_DELAY_BASE_DEFAULT 0x1u 74:Src/main.c **** #define AD9102_PAT_TIMEBASE_HOLD_DEFAULT 0x1u 75:Src/main.c **** #define AD9102_PAT_PERIOD_DEFAULT 0xFFFFu 76:Src/main.c **** 77:Src/main.c **** #define AD9102_FLAG_ENABLE 0x0001u 78:Src/main.c **** #define AD9102_FLAG_TRIANGLE 0x0002u 79:Src/main.c **** /* USER CODE END PD */ 80:Src/main.c **** 81:Src/main.c **** /* Private macro -------------------------------------------------------------*/ 82:Src/main.c **** /* USER CODE BEGIN PM */ 83:Src/main.c **** 84:Src/main.c **** /* USER CODE END PM */ 85:Src/main.c **** 86:Src/main.c **** /* Private variables ---------------------------------------------------------*/ 87:Src/main.c **** ADC_HandleTypeDef hadc1; 88:Src/main.c **** ADC_HandleTypeDef hadc3; 89:Src/main.c **** 90:Src/main.c **** SD_HandleTypeDef hsd1; 91:Src/main.c **** 92:Src/main.c **** TIM_HandleTypeDef htim4; 93:Src/main.c **** TIM_HandleTypeDef htim8; 94:Src/main.c **** TIM_HandleTypeDef htim10; 95:Src/main.c **** TIM_HandleTypeDef htim11; 96:Src/main.c **** 97:Src/main.c **** UART_HandleTypeDef huart8; 98:Src/main.c **** 99:Src/main.c **** /* USER CODE BEGIN PV */ 100:Src/main.c **** uint32_t TO6, TO6_before, TO6_stop, TO6_uart, SD_SEEK, SD_SLIDE, temp32, TO7, TO7_before, TO7_PID, 101:Src/main.c **** uint8_t uart_buf, CPU_state, CPU_state_old, UART_transmission_request, State_Data[2], UART_DATA[DL_ 102:Src/main.c **** uint16_t UART_rec_incr, UART_header, CS_result, temp16, Long_Data[DL_16], COMMAND[CL_16];//, SD_mat 103:Src/main.c **** FRESULT fresult; // result 104:Src/main.c **** int test; ARM GAS /tmp/ccYgfTud.s page 41 105:Src/main.c **** unsigned long fgoto, sizeoffile;//file pointer of the file object & size of file FPGA_RECEIVE_DATA_ 106:Src/main.c **** 107:Src/main.c **** LDx_SetupTypeDef LD1_curr_setup, LD2_curr_setup, LD1_def_setup, LD2_def_setup; 108:Src/main.c **** Work_SetupTypeDef Curr_setup, Def_setup; 109:Src/main.c **** LDx_ParamTypeDef LD1_param, LD2_param; 110:Src/main.c **** 111:Src/main.c **** LD_Blinker_StateTypeDef LD_blinker; 112:Src/main.c **** 113:Src/main.c **** task_t task; 114:Src/main.c **** 115:Src/main.c **** static const uint16_t ad9102_reg_addr[AD9102_REG_COUNT] = { 116:Src/main.c **** 0x0000u, 0x0001u, 0x0002u, 0x0003u, 0x0004u, 0x0005u, 0x0006u, 0x0007u, 117:Src/main.c **** 0x0008u, 0x0009u, 0x000au, 0x000bu, 0x000cu, 0x000du, 0x000eu, 0x001fu, 118:Src/main.c **** 0x0020u, 0x0022u, 0x0023u, 0x0024u, 0x0025u, 0x0026u, 0x0027u, 0x0028u, 119:Src/main.c **** 0x0029u, 0x002au, 0x002bu, 0x002cu, 0x002du, 0x002eu, 0x002fu, 0x0030u, 120:Src/main.c **** 0x0031u, 0x0032u, 0x0033u, 0x0034u, 0x0035u, 0x0036u, 0x0037u, 0x003eu, 121:Src/main.c **** 0x003fu, 0x0040u, 0x0041u, 0x0042u, 0x0043u, 0x0044u, 0x0045u, 0x0047u, 122:Src/main.c **** 0x0050u, 0x0051u, 0x0052u, 0x0053u, 0x0054u, 0x0055u, 0x0056u, 0x0057u, 123:Src/main.c **** 0x0058u, 0x0059u, 0x005au, 0x005bu, 0x005cu, 0x005du, 0x005eu, 0x005fu, 124:Src/main.c **** 0x001eu, 0x001du 125:Src/main.c **** }; 126:Src/main.c **** 127:Src/main.c **** static const uint16_t ad9102_example4_regval[AD9102_REG_COUNT] = { 128:Src/main.c **** 0x0000u, 0x0000u, 0x0000u, 0x0000u, 0x0000u, 0x0000u, 0x0000u, 0x4000u, 129:Src/main.c **** 0x0000u, 0x0000u, 0x0000u, 0x0000u, 0x1f00u, 0x0000u, 0x0000u, 0x0000u, 130:Src/main.c **** 0x000eu, 0x0000u, 0x0000u, 0x0000u, 0x0000u, 0x0000u, 0x3212u, 0x0121u, 131:Src/main.c **** 0xffffu, 0x0000u, 0x0101u, 0x0003u, 0x0000u, 0x0000u, 0x0000u, 0x0000u, 132:Src/main.c **** 0x0000u, 0x0000u, 0x0000u, 0x0000u, 0x4000u, 0x0000u, 0x0606u, 0x1999u, 133:Src/main.c **** 0x9a00u, 0x0000u, 0x0000u, 0x0000u, 0x0000u, 0x0000u, 0x0000u, 0x0000u, 134:Src/main.c **** 0x0fa0u, 0x0000u, 0x0000u, 0x0000u, 0x0000u, 0x0000u, 0x0000u, 0x0000u, 135:Src/main.c **** 0x0000u, 0x0000u, 0x0000u, 0x0000u, 0x0000u, 0x0000u, 0x0000u, 0x16ffu, 136:Src/main.c **** 0x0001u, 0x0001u 137:Src/main.c **** }; 138:Src/main.c **** 139:Src/main.c **** 140:Src/main.c **** 141:Src/main.c **** 142:Src/main.c **** /* USER CODE END PV */ 143:Src/main.c **** 144:Src/main.c **** /* Private function prototypes -----------------------------------------------*/ 145:Src/main.c **** void SystemClock_Config(void); 146:Src/main.c **** static void MX_GPIO_Init(void); 147:Src/main.c **** static void MX_DMA_Init(void); 148:Src/main.c **** static void MX_SPI4_Init(void); 149:Src/main.c **** static void MX_TIM2_Init(void); 150:Src/main.c **** static void MX_TIM5_Init(void); 151:Src/main.c **** static void MX_ADC1_Init(void); 152:Src/main.c **** static void MX_ADC3_Init(void); 153:Src/main.c **** static void MX_SPI2_Init(void); 154:Src/main.c **** static void MX_SPI5_Init(void); 155:Src/main.c **** static void MX_SPI6_Init(void); 156:Src/main.c **** static void MX_USART1_UART_Init(void); 157:Src/main.c **** static void MX_SDMMC1_SD_Init(void); 158:Src/main.c **** static void MX_TIM7_Init(void); 159:Src/main.c **** static void MX_TIM6_Init(void); 160:Src/main.c **** static void MX_TIM10_Init(void); 161:Src/main.c **** static void MX_UART8_Init(void); ARM GAS /tmp/ccYgfTud.s page 42 162:Src/main.c **** static void MX_TIM8_Init(void); 163:Src/main.c **** static void MX_TIM11_Init(void); 164:Src/main.c **** static void MX_TIM4_Init(void); 165:Src/main.c **** /* USER CODE BEGIN PFP */ 166:Src/main.c **** static void Init_params(void); 167:Src/main.c **** static void Decode_uart(uint16_t *Command, LDx_SetupTypeDef *LD1_curr_setup, LDx_SetupTypeDef *LD2_ 168:Src/main.c **** static void Decode_task(uint16_t *Command, LDx_SetupTypeDef *LD1_curr_setup, LDx_SetupTypeDef *LD2_ 169:Src/main.c **** void Set_LTEC(uint8_t num, uint16_t DATA); 170:Src/main.c **** static uint16_t MPhD_T(uint8_t num); 171:Src/main.c **** static uint16_t Get_ADC(uint8_t num); 172:Src/main.c **** static uint16_t PID_Controller_Temp(LDx_SetupTypeDef * LDx_curr_setup, LDx_ParamTypeDef * LDx_resul 173:Src/main.c **** static void AD9102_Init(void); 174:Src/main.c **** static void AD9102_WriteReg(uint16_t addr, uint16_t value); 175:Src/main.c **** static uint16_t AD9102_ReadReg(uint16_t addr); 176:Src/main.c **** static void AD9102_WriteRegTable(const uint16_t *values, uint16_t count); 177:Src/main.c **** static uint16_t AD9102_Apply(uint8_t saw_type, uint8_t enable, uint8_t saw_step, uint8_t pat_base, 178:Src/main.c **** static uint8_t AD9102_CheckFlags(uint16_t pat_status, uint8_t expect_run, uint8_t saw_type, uint8_t 179:Src/main.c **** uint8_t CheckChecksum(uint16_t *pbuff); 180:Src/main.c **** uint16_t CalculateChecksum(uint16_t *pbuff, uint16_t len); 181:Src/main.c **** //int SD_Init(void); 182:Src/main.c **** int SD_SAVE(uint16_t *pbuff); 183:Src/main.c **** //uint32_t Get_Length(void); 184:Src/main.c **** int SD_READ(uint16_t *pbuff); 185:Src/main.c **** int SD_REMOVE(void); 186:Src/main.c **** void USART_TX (uint8_t* dt, uint16_t sz); 187:Src/main.c **** void USART_TX_DMA (uint16_t sz); 188:Src/main.c **** static void Stop_TIM10(); 189:Src/main.c **** static void OUT_trigger(uint8_t); 190:Src/main.c **** /* USER CODE END PFP */ 191:Src/main.c **** 192:Src/main.c **** /* Private user code ---------------------------------------------------------*/ 193:Src/main.c **** /* USER CODE BEGIN 0 */ 194:Src/main.c **** 195:Src/main.c **** /* USER CODE END 0 */ 196:Src/main.c **** 197:Src/main.c **** /** 198:Src/main.c **** * @brief The application entry point. 199:Src/main.c **** * @retval int 200:Src/main.c **** */ 201:Src/main.c **** int main(void) 202:Src/main.c **** { 203:Src/main.c **** 204:Src/main.c **** /* USER CODE BEGIN 1 */ 205:Src/main.c **** HAL_StatusTypeDef st; 206:Src/main.c **** /* USER CODE END 1 */ 207:Src/main.c **** 208:Src/main.c **** /* MCU Configuration--------------------------------------------------------*/ 209:Src/main.c **** 210:Src/main.c **** /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ 211:Src/main.c **** HAL_Init(); 212:Src/main.c **** 213:Src/main.c **** /* USER CODE BEGIN Init */ 214:Src/main.c **** /*I hope you don't forget that first - MX_DMA_Init(); and than - MX_USART1_UART_Init();*/ 215:Src/main.c **** /* USER CODE END Init */ 216:Src/main.c **** 217:Src/main.c **** /* Configure the system clock */ 218:Src/main.c **** SystemClock_Config(); ARM GAS /tmp/ccYgfTud.s page 43 219:Src/main.c **** 220:Src/main.c **** /* USER CODE BEGIN SysInit */ 221:Src/main.c **** 222:Src/main.c **** /* USER CODE END SysInit */ 223:Src/main.c **** 224:Src/main.c **** /* Initialize all configured peripherals */ 225:Src/main.c **** MX_GPIO_Init(); 226:Src/main.c **** MX_DMA_Init(); 227:Src/main.c **** MX_SPI4_Init(); 228:Src/main.c **** MX_FATFS_Init(); 229:Src/main.c **** MX_TIM2_Init(); 230:Src/main.c **** MX_TIM5_Init(); 231:Src/main.c **** MX_ADC1_Init(); 232:Src/main.c **** MX_ADC3_Init(); 233:Src/main.c **** MX_SPI2_Init(); 234:Src/main.c **** MX_SPI5_Init(); 235:Src/main.c **** MX_SPI6_Init(); 236:Src/main.c **** MX_USART1_UART_Init(); 237:Src/main.c **** MX_SDMMC1_SD_Init(); 238:Src/main.c **** MX_TIM7_Init(); 239:Src/main.c **** MX_TIM6_Init(); 240:Src/main.c **** MX_TIM10_Init(); 241:Src/main.c **** MX_UART8_Init(); 242:Src/main.c **** MX_TIM8_Init(); 243:Src/main.c **** MX_TIM11_Init(); 244:Src/main.c **** MX_TIM4_Init(); 245:Src/main.c **** /* USER CODE BEGIN 2 */ 246:Src/main.c **** Init_params(); 247:Src/main.c **** //HAL_TIM_Base_Start(&htim11); 248:Src/main.c **** //HAL_TIM_PWM_Start(&htim11, TIM_CHANNEL_1); //start modulating by Mach-Zander modulator 249:Src/main.c **** 250:Src/main.c **** 251:Src/main.c **** //TIM4,11 clocks = 92 MHz 252:Src/main.c **** 253:Src/main.c **** //ADC clock 254:Src/main.c **** //TIM4 -> ARR = 60; // for 1.5 MHz 255:Src/main.c **** //TIM4 -> ARR = 91; // for 1 MHz 256:Src/main.c **** //TIM4 -> ARR = 45; // for 2 MHz 257:Src/main.c **** TIM4 -> ARR = 53; // for 1.735 MHz. It`s the highest frequency for correct ADC work. At higher fre 258:Src/main.c **** 259:Src/main.c **** TIM4 -> CCR3 = (TIM4 -> ARR +1)/2 - 1; 260:Src/main.c **** 261:Src/main.c **** 262:Src/main.c **** //Mach-Zander clock (should be 1/4 of ADC clock freq) 263:Src/main.c **** 264:Src/main.c **** TIM11 -> ARR = (TIM4 -> ARR +1)*4 - 1; 265:Src/main.c **** TIM11 -> CCR1 = (TIM11 -> ARR +1)/2 - 1; 266:Src/main.c **** 267:Src/main.c **** /* 268:Src/main.c **** if (HAL_GPIO_ReadPin(INP_0_GPIO_Port, INP_0_Pin) == 0){ 269:Src/main.c **** 270:Src/main.c **** CPU_state = DECODE_ENABLE; 271:Src/main.c **** } 272:Src/main.c **** */ 273:Src/main.c **** /* USER CODE END 2 */ 274:Src/main.c **** 275:Src/main.c **** /* Infinite loop */ ARM GAS /tmp/ccYgfTud.s page 44 276:Src/main.c **** /* USER CODE BEGIN WHILE */ 277:Src/main.c **** while (1) 278:Src/main.c **** { 279:Src/main.c **** if ((HAL_GPIO_ReadPin(USB_FLAG_GPIO_Port, USB_FLAG_Pin)==GPIO_PIN_SET)&&(u_rx_flg == 0)) 280:Src/main.c **** { 281:Src/main.c **** //NVIC_DisableIRQ(USART1_IRQn); 282:Src/main.c **** LL_USART_EnableIT_PE(USART1); 283:Src/main.c **** LL_USART_EnableIT_RXNE(USART1); 284:Src/main.c **** LL_USART_EnableIT_ERROR(USART1); 285:Src/main.c **** NVIC_SetPriority(USART1_IRQn, 0); 286:Src/main.c **** NVIC_EnableIRQ(USART1_IRQn);//In other case you have FE error flag... 287:Src/main.c **** u_rx_flg = 1; 288:Src/main.c **** } 289:Src/main.c **** // else 290:Src/main.c **** // { 291:Src/main.c **** // //NVIC_DisableIRQ(USART1_IRQn); 292:Src/main.c **** // u_rx_flg = 0; 293:Src/main.c **** // } 294:Src/main.c **** switch (CPU_state) 295:Src/main.c **** { 296:Src/main.c **** case HALT://0 - Default state 297:Src/main.c **** CPU_state_old = HALT;//Save main current cycle 298:Src/main.c **** task.current_param = task.min_param; 299:Src/main.c **** Stop_TIM10(); 300:Src/main.c **** break; 301:Src/main.c **** case DECODE_ENABLE://1 - Decode rec. message 302:Src/main.c **** CS_result = CalculateChecksum(COMMAND, CL_16-2); 303:Src/main.c **** if (CheckChecksum(COMMAND)) 304:Src/main.c **** { 305:Src/main.c **** LL_SPI_Enable(SPI2);//Enable SPI for Laser1 DAC & TEC1 306:Src/main.c **** LL_SPI_Enable(SPI6);//Enable SPI for Laser2 DAC & TEC2 307:Src/main.c **** Decode_uart(COMMAND, &LD1_curr_setup, &LD2_curr_setup, &Curr_setup); 308:Src/main.c **** TO6_before = TO6; 309:Src/main.c **** //LD1_param.LD_TEMP_Before = LD1_param.LD_TEMP; 310:Src/main.c **** //LD2_param.LD_TEMP_Before = LD2_param.LD_TEMP; 311:Src/main.c **** CPU_state = WORK_ENABLE; 312:Src/main.c **** CPU_state_old = WORK_ENABLE;//Save main current cycle 313:Src/main.c **** } 314:Src/main.c **** else 315:Src/main.c **** { 316:Src/main.c **** State_Data[0] |= UART_DECODE_ERR; 317:Src/main.c **** CPU_state = DEFAULT_ENABLE; 318:Src/main.c **** CPU_state_old = HALT;//Save main current cycle 319:Src/main.c **** } 320:Src/main.c **** UART_transmission_request = MESS_01; 321:Src/main.c **** break; 322:Src/main.c **** case DEFAULT_ENABLE://2 - Go to HALT 323:Src/main.c **** //Set current setup to default 324:Src/main.c **** task.current_param = task.min_param; 325:Src/main.c **** Stop_TIM10(); 326:Src/main.c **** Init_params(); 327:Src/main.c **** LL_SPI_Disable(SPI2);//Disable SPI for Laser1 DAC & TEC1 328:Src/main.c **** LL_SPI_Disable(SPI6);//Disable SPI for Laser2 DAC & TEC2 329:Src/main.c **** CPU_state = HALT; 330:Src/main.c **** CPU_state_old = HALT;//Save main current cycle 331:Src/main.c **** UART_transmission_request = MESS_01; 332:Src/main.c **** break; ARM GAS /tmp/ccYgfTud.s page 45 333:Src/main.c **** case TRANS_S_ENABLE://3 - Transmith saved packet Before this operation must to be defaulting! 334:Src/main.c **** temp16 = SD_READ(&Long_Data[0]); 335:Src/main.c **** State_Data[0]|=temp16&0xff; 336:Src/main.c **** if (temp16==0) 337:Src/main.c **** { 338:Src/main.c **** UART_transmission_request = MESS_03; 339:Src/main.c **** } 340:Src/main.c **** else 341:Src/main.c **** { 342:Src/main.c **** UART_transmission_request = MESS_01; 343:Src/main.c **** } 344:Src/main.c **** CPU_state_old = HALT; 345:Src/main.c **** CPU_state = CPU_state_old;//Return to main current cycle 346:Src/main.c **** break; 347:Src/main.c **** case TRANS_ENABLE://4 - Transmith current packet 348:Src/main.c **** UART_transmission_request = MESS_02; 349:Src/main.c **** CPU_state = CPU_state_old;//Return to main current cycle 350:Src/main.c **** break; 351:Src/main.c **** case REMOVE_FILE://5 - Remove file from SD 352:Src/main.c **** State_Data[0]|=SD_REMOVE()&0xff; 353:Src/main.c **** UART_transmission_request = MESS_01; 354:Src/main.c **** CPU_state = CPU_state_old; 355:Src/main.c **** break; 356:Src/main.c **** case STATE://6 - Transmith state message 357:Src/main.c **** UART_transmission_request = MESS_01; 358:Src/main.c **** CPU_state = CPU_state_old;//Return to main current cycle 359:Src/main.c **** break; 360:Src/main.c **** case WORK_ENABLE://7 - Main work cycle 361:Src/main.c **** task.current_param = task.min_param; 362:Src/main.c **** Stop_TIM10(); 363:Src/main.c **** if (TO7>TO7_before)//Main work cycle go with the timer 7 (1000 us or 1 kHz) 364:Src/main.c **** { 365:Src/main.c **** TO7_before = TO7; 366:Src/main.c **** LD1_param.POWER = MPhD_T(1);//Get Data from monitor photodiode of LD1 367:Src/main.c **** LD1_param.POWER = MPhD_T(1);//Get Data from monitor photodiode of LD1 368:Src/main.c **** LD2_param.POWER = MPhD_T(2);//Get Data from monitor photodiode of LD2 369:Src/main.c **** LD2_param.POWER = MPhD_T(2);//Get Data from monitor photodiode of LD2 370:Src/main.c **** 371:Src/main.c **** //Correct temperature in all pulses 372:Src/main.c **** (void) MPhD_T(3); 373:Src/main.c **** LD1_param.LD_CURR_TEMP = MPhD_T(3); 374:Src/main.c **** (void) MPhD_T(4); 375:Src/main.c **** LD2_param.LD_CURR_TEMP = MPhD_T(4); 376:Src/main.c **** temp16=PID_Controller_Temp(&LD1_curr_setup, &LD1_param, 1); 377:Src/main.c **** Set_LTEC(3, temp16);//Drive Laser TEC 1 378:Src/main.c **** temp16=PID_Controller_Temp(&LD2_curr_setup, &LD2_param, 2); 379:Src/main.c **** Set_LTEC(4, temp16);//Drive Laser TEC 2 380:Src/main.c **** 381:Src/main.c **** Long_Data[1] = LD1_param.POWER;//Translate Data from monitor photodiode of LD1 to Long_Data 382:Src/main.c **** Long_Data[2] = LD2_param.POWER;//Translate Data from monitor photodiode of LD2 to Long_Data 383:Src/main.c **** 384:Src/main.c **** Set_LTEC(1,LD1_curr_setup.CURRENT);//Drive Laser diode 1 385:Src/main.c **** Set_LTEC(2,LD2_curr_setup.CURRENT);//Drive Laser diode 2 386:Src/main.c **** 387:Src/main.c **** //Prepare DATA of internals ADCs 388:Src/main.c **** //Put the temperature of LD2 to Long_Data: 389:Src/main.c **** temp16 = Get_ADC(0); ARM GAS /tmp/ccYgfTud.s page 46 390:Src/main.c **** temp16 = Get_ADC(1); 391:Src/main.c **** Long_Data[7] = temp16; // PA2 -- 3V_monitor // PB1 -- U_Rt1_ext_Gain 392:Src/main.c **** 393:Src/main.c **** //Put the temperature of LD2 to Long_Data: 394:Src/main.c **** temp16 = Get_ADC(1); 395:Src/main.c **** Long_Data[8] = temp16; // PB0 -- U_Rt2_ext_Gain // PB0 -- U_Rt2_ext_Gain 396:Src/main.c **** 397:Src/main.c **** //Put the temperature of LD2 to Long_Data: 398:Src/main.c **** temp16 = Get_ADC(1); 399:Src/main.c **** Long_Data[9] = temp16; // PB1 -- U_Rt1_ext_Gain // PA2 -- 3V_monitor 400:Src/main.c **** 401:Src/main.c **** //Put the temperature of LD2 to Long_Data: 402:Src/main.c **** temp16 = Get_ADC(1); 403:Src/main.c **** Long_Data[10] = temp16; // PC0 -- 5V1_monitor // PC0 -- 5V1_monitor 404:Src/main.c **** 405:Src/main.c **** //Put the temperature of LD2 to Long_Data: 406:Src/main.c **** temp16 = Get_ADC(1); 407:Src/main.c **** Long_Data[11] = temp16; // PC1 -- 5V2_monitor // PC1 -- 5V2_monitor 408:Src/main.c **** temp16 = Get_ADC(2); 409:Src/main.c **** 410:Src/main.c **** //Put the temperature of LD2 to Long_Data: 411:Src/main.c **** temp16 = Get_ADC(3); 412:Src/main.c **** temp16 = Get_ADC(4); 413:Src/main.c **** Long_Data[12] = temp16; 414:Src/main.c **** temp16 = Get_ADC(5); 415:Src/main.c **** 416:Src/main.c **** //Put the timer tick to Long_Data: 417:Src/main.c **** TO6_stop = TO6; 418:Src/main.c **** Long_Data[3] = (TO6_stop)&0xffff; 419:Src/main.c **** Long_Data[4] = (TO6_stop>>16)&0xffff; 420:Src/main.c **** 421:Src/main.c **** //Put the average temperature of LD1 to Long_Data: 422:Src/main.c **** Long_Data[5] = LD1_param.LD_CURR_TEMP; 423:Src/main.c **** 424:Src/main.c **** //Put the average temperature of LD2 to Long_Data: 425:Src/main.c **** Long_Data[6] = LD2_param.LD_CURR_TEMP; 426:Src/main.c **** 427:Src/main.c **** if (Curr_setup.SD_EN==1) 428:Src/main.c **** { 429:Src/main.c **** CS_result = CalculateChecksum(&Long_Data[1], DL_16-2); 430:Src/main.c **** Long_Data[DL_16-1] = CS_result; 431:Src/main.c **** temp16 = SD_SAVE(&Long_Data[0]); 432:Src/main.c **** State_Data[0]|=temp16&0xff; 433:Src/main.c **** } 434:Src/main.c **** CPU_state_old = WORK_ENABLE;//Save main current cycle 435:Src/main.c **** } 436:Src/main.c **** break; 437:Src/main.c **** case AD9102_CMD://10 - Configure AD9102 sawtooth output 438:Src/main.c **** if (CalculateChecksum(COMMAND, AD9102_CMD_WORDS - 1) == COMMAND[AD9102_CMD_WORDS - 1]) 439:Src/main.c **** { 440:Src/main.c **** uint16_t flags = COMMAND[0]; 441:Src/main.c **** uint16_t param0 = COMMAND[1]; 442:Src/main.c **** uint16_t param1 = COMMAND[2]; 443:Src/main.c **** uint8_t enable = (flags & AD9102_FLAG_ENABLE) ? 1u : 0u; 444:Src/main.c **** uint8_t triangle = (flags & AD9102_FLAG_TRIANGLE) ? 1u : 0u; 445:Src/main.c **** uint8_t saw_type = triangle ? AD9102_SAW_TYPE_TRI : AD9102_SAW_TYPE_UP; 446:Src/main.c **** uint8_t saw_step = (uint8_t)(param0 & 0x00FFu); ARM GAS /tmp/ccYgfTud.s page 47 447:Src/main.c **** uint8_t pat_base = (uint8_t)((param0 >> 8) & 0x0Fu); 448:Src/main.c **** uint16_t pat_period = param1; 449:Src/main.c **** 450:Src/main.c **** if (param0 == 0u && param1 == 0u) 451:Src/main.c **** { 452:Src/main.c **** saw_step = AD9102_SAW_STEP_DEFAULT; 453:Src/main.c **** pat_base = AD9102_PAT_PERIOD_BASE_DEFAULT; 454:Src/main.c **** pat_period = AD9102_PAT_PERIOD_DEFAULT; 455:Src/main.c **** } 456:Src/main.c **** else 457:Src/main.c **** { 458:Src/main.c **** if (saw_step == 0u) 459:Src/main.c **** { 460:Src/main.c **** saw_step = AD9102_SAW_STEP_DEFAULT; 461:Src/main.c **** } 462:Src/main.c **** else if (saw_step > 63u) 463:Src/main.c **** { 464:Src/main.c **** saw_step = 63u; 465:Src/main.c **** } 466:Src/main.c **** if (pat_period == 0u) 467:Src/main.c **** { 468:Src/main.c **** pat_period = AD9102_PAT_PERIOD_DEFAULT; 469:Src/main.c **** } 470:Src/main.c **** } 471:Src/main.c **** 472:Src/main.c **** uint16_t pat_status = AD9102_Apply(saw_type, enable, saw_step, pat_base, pat_period); 473:Src/main.c **** State_Data[1] = (uint8_t)(pat_status & 0x00FFu); 474:Src/main.c **** if (AD9102_CheckFlags(pat_status, enable, saw_type, saw_step, pat_base, pat_period)) 475:Src/main.c **** { 476:Src/main.c **** State_Data[0] |= AD9102_ERR; 477:Src/main.c **** } 478:Src/main.c **** } 479:Src/main.c **** else 480:Src/main.c **** { 481:Src/main.c **** State_Data[0] |= UART_DECODE_ERR; 482:Src/main.c **** } 483:Src/main.c **** UART_transmission_request = MESS_01; 484:Src/main.c **** CPU_state = CPU_state_old; 485:Src/main.c **** break; 486:Src/main.c **** case DECODE_TASK: 487:Src/main.c **** if (CheckChecksum(COMMAND)) 488:Src/main.c **** { 489:Src/main.c **** Decode_task(COMMAND, &LD1_curr_setup, &LD2_curr_setup, &Curr_setup); 490:Src/main.c **** TO6_before = TO6; 491:Src/main.c **** CPU_state = RUN_TASK; 492:Src/main.c **** CPU_state_old = RUN_TASK;//Save main current cycle 493:Src/main.c **** } 494:Src/main.c **** else 495:Src/main.c **** { 496:Src/main.c **** State_Data[0] |= UART_DECODE_ERR; 497:Src/main.c **** CPU_state = DEFAULT_ENABLE; 498:Src/main.c **** CPU_state_old = HALT;//Save main current cycle 499:Src/main.c **** } 500:Src/main.c **** UART_transmission_request = MESS_01; 501:Src/main.c **** break; 502:Src/main.c **** case RUN_TASK: 503:Src/main.c **** switch (task.task_type) ARM GAS /tmp/ccYgfTud.s page 48 504:Src/main.c **** { 505:Src/main.c **** case TT_CHANGE_CURR_1: 506:Src/main.c **** 507:Src/main.c **** 508:Src/main.c **** //calculating timer periods for ADC clock and Mach-Zander modulator 509:Src/main.c **** //ADC clock 510:Src/main.c **** //TIM4 -> ARR = 60; // for 1.5 MHz 511:Src/main.c **** //TIM4 -> ARR = 91; // for 1 MHz 512:Src/main.c **** //TIM4 -> ARR = 45; // for 2 MHz 513:Src/main.c **** 514:Src/main.c **** //online calculation for debug purposes: 515:Src/main.c **** //manually varying TIM4 -> ARR by debugger while running 516:Src/main.c **** //TIM4 -> CCR3 = (TIM4 -> ARR +1)/2 - 1; 517:Src/main.c **** 518:Src/main.c **** 519:Src/main.c **** //Mach-Zander clock (should be half of ADC clock freq) 520:Src/main.c **** //TIM11 -> ARR = (TIM4 -> ARR +1)*2 - 1; 521:Src/main.c **** //TIM11 -> CCR1 = (TIM11 -> ARR +1)/2 - 1; 522:Src/main.c **** 523:Src/main.c **** 524:Src/main.c **** 525:Src/main.c **** Set_LTEC(TT_CHANGE_CURR_2, task.curr); 526:Src/main.c **** (void) MPhD_T(TT_CHANGE_TEMP_1); 527:Src/main.c **** LD1_param.LD_CURR_TEMP = MPhD_T(TT_CHANGE_TEMP_1); 528:Src/main.c **** (void) MPhD_T(TT_CHANGE_TEMP_2); 529:Src/main.c **** LD2_param.LD_CURR_TEMP = MPhD_T(TT_CHANGE_TEMP_2); 530:Src/main.c **** temp16=PID_Controller_Temp(&LD1_curr_setup, &LD1_param, 1); 531:Src/main.c **** Set_LTEC(TT_CHANGE_TEMP_1, temp16);//Drive Laser TEC 1 532:Src/main.c **** temp16=PID_Controller_Temp(&LD2_curr_setup, &LD2_param, 2); 533:Src/main.c **** Set_LTEC(TT_CHANGE_TEMP_2, temp16);//Drive Laser TEC 2 534:Src/main.c **** 535:Src/main.c **** // Toggle pin for oscilloscope 536:Src/main.c **** HAL_GPIO_WritePin(GPIOD, GPIO_PIN_7, GPIO_PIN_SET); //start of the whole frequency sweep proc 537:Src/main.c **** HAL_GPIO_WritePin(GPIOD, GPIO_PIN_7, GPIO_PIN_RESET); 538:Src/main.c **** 539:Src/main.c **** st = HAL_TIM_Base_Start_IT(&htim10); 540:Src/main.c **** if (st != HAL_OK) 541:Src/main.c **** while(1); 542:Src/main.c **** 543:Src/main.c **** uint16_t step_counter = 0; 544:Src/main.c **** uint16_t trigger_counter = 0; 545:Src/main.c **** uint16_t trigger_step = (uint8_t )((task.max_param - task.current_param)/task.delta_param * 1 546:Src/main.c **** uint16_t task_sheduler = 0; 547:Src/main.c **** 548:Src/main.c **** 549:Src/main.c **** 550:Src/main.c **** HAL_TIM_PWM_Stop(&htim11, TIM_CHANNEL_1); //start modulating by Mach-Zander modulator 551:Src/main.c **** HAL_TIM_PWM_Stop(&htim4, TIM_CHANNEL_3); //start ADC clock 552:Src/main.c **** TIM11 -> CR1 &= ~(1 << 3); //disables one-pulse mode 553:Src/main.c **** TIM4 -> CR1 &= ~(1 << 3); //disables one-pulse mode 554:Src/main.c **** 555:Src/main.c **** 556:Src/main.c **** 557:Src/main.c **** TIM11 -> CNT = 0; 558:Src/main.c **** TIM4 -> CNT = 0; 559:Src/main.c **** 560:Src/main.c **** HAL_TIM_PWM_Start(&htim11, TIM_CHANNEL_1); //start modulating by Mach-Zander modulator ARM GAS /tmp/ccYgfTud.s page 49 561:Src/main.c **** HAL_TIM_PWM_Start(&htim4, TIM_CHANNEL_3); //start ADC clock 562:Src/main.c **** //TIM4 -> CNT = 0; 563:Src/main.c **** 564:Src/main.c **** TIM4 -> CNT = TIM4 -> ARR - 20; // not zero to make phase shift that will be robust to big de 565:Src/main.c **** TIM11 -> CNT = 0; 566:Src/main.c **** 567:Src/main.c **** 568:Src/main.c **** while (task.current_param < task.max_param) 569:Src/main.c **** { 570:Src/main.c **** if (TIM10_coflag) 571:Src/main.c **** { 572:Src/main.c **** Set_LTEC(TT_CHANGE_CURR_1, task.current_param); 573:Src/main.c **** //TIM11 -> CNT = 0; // to link modulator phase 574:Src/main.c **** //TIM4 -> CNT = 0; // to link ADC clock phase 575:Src/main.c **** task.current_param += task.delta_param; 576:Src/main.c **** TO10 = 0; 577:Src/main.c **** TIM10_coflag = 0; 578:Src/main.c **** 579:Src/main.c **** HAL_GPIO_WritePin(GPIOG, GPIO_PIN_9, GPIO_PIN_SET); // set the current step laser current t 580:Src/main.c **** HAL_GPIO_WritePin(GPIOG, GPIO_PIN_9, GPIO_PIN_RESET); 581:Src/main.c **** //* 582:Src/main.c **** if (step_counter % trigger_step == 0){ //trigger at every 60 step 583:Src/main.c **** OUT_trigger(trigger_counter); 584:Src/main.c **** ++trigger_counter; 585:Src/main.c **** } 586:Src/main.c **** ++step_counter; 587:Src/main.c **** //*/ 588:Src/main.c **** /* 589:Src/main.c **** ++task_sheduler; 590:Src/main.c **** if (task_sheduler >= 10){ 591:Src/main.c **** task_sheduler = 0; 592:Src/main.c **** } 593:Src/main.c **** //maintain stable temperature of laser 2 594:Src/main.c **** if (task_sheduler == 0){ 595:Src/main.c **** (void) MPhD_T(TT_CHANGE_TEMP_2); 596:Src/main.c **** LD2_param.LD_CURR_TEMP = MPhD_T(TT_CHANGE_TEMP_2); 597:Src/main.c **** temp16=PID_Controller_Temp(&LD2_curr_setup, &LD2_param, 2); 598:Src/main.c **** Set_LTEC(TT_CHANGE_TEMP_2, temp16);//Drive Laser TEC 2 599:Src/main.c **** } 600:Src/main.c **** //maintain stable temperature of laser 1 601:Src/main.c **** //* 602:Src/main.c **** if (task_sheduler == 5){ 603:Src/main.c **** (void) MPhD_T(TT_CHANGE_TEMP_1); 604:Src/main.c **** LD1_param.LD_CURR_TEMP = MPhD_T(TT_CHANGE_TEMP_1); 605:Src/main.c **** temp16=PID_Controller_Temp(&LD1_curr_setup, &LD1_param, 1); 606:Src/main.c **** Set_LTEC(TT_CHANGE_TEMP_1, temp16);//Drive Laser TEC 1 607:Src/main.c **** } 608:Src/main.c **** //*/ 609:Src/main.c **** } 610:Src/main.c **** } 611:Src/main.c **** TIM11 -> DIER |= 1; //enable update interrupt. In this IRQ handler we will set both tims to o 612:Src/main.c **** //TIM11 -> CR1 |= 1 << 3; //sets timer to one-pulse mode. So it will turn off at the next Upd 613:Src/main.c **** //TIM4 -> CR1 |= 1 << 3; //sets timer to one-pulse mode. So it will turn off at the next Upda 614:Src/main.c **** //but one-pulse mode should be disabled 615:Src/main.c **** 616:Src/main.c **** //HAL_TIM_PWM_Stop(&htim11, TIM_CHANNEL_1); //start modulating by Mach-Zander modulator 617:Src/main.c **** //HAL_TIM_PWM_Stop(&htim4, TIM_CHANNEL_3); //start ADC clock ARM GAS /tmp/ccYgfTud.s page 50 618:Src/main.c **** 619:Src/main.c **** 620:Src/main.c **** 621:Src/main.c **** Stop_TIM10(); 622:Src/main.c **** 623:Src/main.c **** task.current_param = task.min_param; 624:Src/main.c **** Set_LTEC(TT_CHANGE_CURR_1, task.current_param); 625:Src/main.c **** if (task.tau > 3) 626:Src/main.c **** { 627:Src/main.c **** TIM10_period = htim10.Init.Period; 628:Src/main.c **** htim10.Init.Period = 9999; 629:Src/main.c **** TO10_counter = (task.tau - 1) * 100; 630:Src/main.c **** } 631:Src/main.c **** HAL_TIM_Base_Start_IT(&htim10); 632:Src/main.c **** break; 633:Src/main.c **** case TT_CHANGE_CURR_2: 634:Src/main.c **** //Blink laser 2 635:Src/main.c **** //* 636:Src/main.c **** Set_LTEC(TT_CHANGE_CURR_1, task.curr); 637:Src/main.c **** (void) MPhD_T(TT_CHANGE_TEMP_1); 638:Src/main.c **** LD1_param.LD_CURR_TEMP = MPhD_T(TT_CHANGE_TEMP_1); 639:Src/main.c **** (void) MPhD_T(TT_CHANGE_TEMP_2); 640:Src/main.c **** LD2_param.LD_CURR_TEMP = MPhD_T(TT_CHANGE_TEMP_2); 641:Src/main.c **** temp16=PID_Controller_Temp(&LD1_curr_setup, &LD1_param, 1); 642:Src/main.c **** Set_LTEC(TT_CHANGE_TEMP_1, temp16);//Drive Laser TEC 1 643:Src/main.c **** temp16=PID_Controller_Temp(&LD2_curr_setup, &LD2_param, 2); 644:Src/main.c **** Set_LTEC(TT_CHANGE_TEMP_2, temp16);//Drive Laser TEC 2 645:Src/main.c **** 646:Src/main.c **** LD_blinker.task_type = 2; 647:Src/main.c **** LD_blinker.state = 0; // 0 -- disabled (do nothing); 1 -- update LD current; 2 -- blinking, L 648:Src/main.c **** //LD_blinker.param = task.current_param; 649:Src/main.c **** LD_blinker.param = 0; 650:Src/main.c **** LD_blinker.param = 1000; // LD2 current (in unspecified units) 651:Src/main.c **** LD_blinker.signal_port = OUT_9_GPIO_Port; 652:Src/main.c **** LD_blinker.signal_pin = OUT_9_Pin; 653:Src/main.c **** 654:Src/main.c **** TIM8->ARR = 10000; //zero to LD_blinker.param change frequency (also in unspecified units). 655:Src/main.c **** //When it is too low -- Desktop app crashes (there is not so much compute sources on MCU 656:Src/main.c **** st = HAL_TIM_Base_Start_IT(&htim8); 657:Src/main.c **** if (st != HAL_OK) 658:Src/main.c **** while(1); 659:Src/main.c **** // */ 660:Src/main.c **** 661:Src/main.c **** // Toggle pin for oscilloscope 662:Src/main.c **** HAL_GPIO_WritePin(GPIOD, GPIO_PIN_7, GPIO_PIN_SET); 663:Src/main.c **** uint32_t i = 10000; while (--i){} 664:Src/main.c **** HAL_GPIO_WritePin(GPIOD, GPIO_PIN_7, GPIO_PIN_RESET); 665:Src/main.c **** LD_blinker.state = 2; 666:Src/main.c **** 667:Src/main.c **** st = HAL_TIM_Base_Start_IT(&htim10); 668:Src/main.c **** if (st != HAL_OK) 669:Src/main.c **** while(1); 670:Src/main.c **** while (task.current_param < task.max_param) 671:Src/main.c **** { 672:Src/main.c **** if (TIM10_coflag) 673:Src/main.c **** { 674:Src/main.c **** //Set_LTEC(TT_CHANGE_CURR_2, task.current_param); ARM GAS /tmp/ccYgfTud.s page 51 675:Src/main.c **** //LD_blinker.param = task.current_param; 676:Src/main.c **** //++LD_blinker.param; 677:Src/main.c **** task.current_param += task.delta_param; 678:Src/main.c **** TO10 = 0; 679:Src/main.c **** TIM10_coflag = 0; 680:Src/main.c **** 681:Src/main.c **** 682:Src/main.c **** } 683:Src/main.c **** } 684:Src/main.c **** HAL_TIM_Base_Stop(&htim10); 685:Src/main.c **** HAL_GPIO_WritePin(GPIOD, GPIO_PIN_7, GPIO_PIN_SET); 686:Src/main.c **** 687:Src/main.c **** HAL_GPIO_WritePin(GPIOD, GPIO_PIN_7, GPIO_PIN_RESET); 688:Src/main.c **** 689:Src/main.c **** HAL_TIM_Base_Stop_IT(&htim8); 690:Src/main.c **** TIM8->CNT = 0; 691:Src/main.c **** 692:Src/main.c **** Stop_TIM10(); 693:Src/main.c **** task.current_param = task.min_param; 694:Src/main.c **** Set_LTEC(TT_CHANGE_CURR_2, task.current_param); 695:Src/main.c **** if (task.tau > 3) 696:Src/main.c **** { 697:Src/main.c **** TIM10_period = htim10.Init.Period; 698:Src/main.c **** htim10.Init.Period = 9999; 699:Src/main.c **** TO10_counter = (task.tau - 1) * 100; 700:Src/main.c **** } 701:Src/main.c **** HAL_TIM_Base_Start_IT(&htim10); 702:Src/main.c **** 703:Src/main.c **** 704:Src/main.c **** //*/ 705:Src/main.c **** 706:Src/main.c **** /* // Backup 707:Src/main.c **** Set_LTEC(TT_CHANGE_CURR_1, task.curr); 708:Src/main.c **** (void) MPhD_T(TT_CHANGE_TEMP_1); 709:Src/main.c **** LD1_param.LD_CURR_TEMP = MPhD_T(TT_CHANGE_TEMP_1); 710:Src/main.c **** (void) MPhD_T(TT_CHANGE_TEMP_2); 711:Src/main.c **** LD2_param.LD_CURR_TEMP = MPhD_T(TT_CHANGE_TEMP_2); 712:Src/main.c **** temp16=PID_Controller_Temp(&LD1_curr_setup, &LD1_param, 1); 713:Src/main.c **** Set_LTEC(TT_CHANGE_TEMP_1, temp16);//Drive Laser TEC 1 714:Src/main.c **** temp16=PID_Controller_Temp(&LD2_curr_setup, &LD2_param, 2); 715:Src/main.c **** Set_LTEC(TT_CHANGE_TEMP_2, temp16);//Drive Laser TEC 2 716:Src/main.c **** 717:Src/main.c **** // Toggle pin for oscilloscope 718:Src/main.c **** HAL_GPIO_WritePin(GPIOD, GPIO_PIN_7, GPIO_PIN_SET); 719:Src/main.c **** HAL_GPIO_WritePin(GPIOD, GPIO_PIN_7, GPIO_PIN_RESET); 720:Src/main.c **** 721:Src/main.c **** st = HAL_TIM_Base_Start_IT(&htim10); 722:Src/main.c **** if (st != HAL_OK) 723:Src/main.c **** while(1); 724:Src/main.c **** while (task.current_param < task.max_param) 725:Src/main.c **** { 726:Src/main.c **** if (TIM10_coflag) 727:Src/main.c **** { 728:Src/main.c **** Set_LTEC(TT_CHANGE_CURR_2, task.current_param); 729:Src/main.c **** task.current_param += task.delta_param; 730:Src/main.c **** TO10 = 0; 731:Src/main.c **** TIM10_coflag = 0; ARM GAS /tmp/ccYgfTud.s page 52 732:Src/main.c **** 733:Src/main.c **** 734:Src/main.c **** } 735:Src/main.c **** } 736:Src/main.c **** Stop_TIM10(); 737:Src/main.c **** task.current_param = task.min_param; 738:Src/main.c **** Set_LTEC(TT_CHANGE_CURR_2, task.current_param); 739:Src/main.c **** if (task.tau > 3) 740:Src/main.c **** { 741:Src/main.c **** TIM10_period = htim10.Init.Period; 742:Src/main.c **** htim10.Init.Period = 9999; 743:Src/main.c **** TO10_counter = (task.tau - 1) * 100; 744:Src/main.c **** } 745:Src/main.c **** HAL_TIM_Base_Start_IT(&htim10); 746:Src/main.c **** */ 747:Src/main.c **** 748:Src/main.c **** 749:Src/main.c **** break; 750:Src/main.c **** case TT_CHANGE_TEMP_1: 751:Src/main.c **** // isn't implemented 752:Src/main.c **** break; 753:Src/main.c **** case TT_CHANGE_TEMP_2: 754:Src/main.c **** // isn't implemented 755:Src/main.c **** break; 756:Src/main.c **** } 757:Src/main.c **** 758:Src/main.c **** if (TO7>TO7_before) 759:Src/main.c **** { 760:Src/main.c **** TO7_before = TO7; 761:Src/main.c **** 762:Src/main.c **** LD1_param.POWER = MPhD_T(1);//Get Data from monitor photodiode of LD1 763:Src/main.c **** LD1_param.POWER = MPhD_T(1);//Get Data from monitor photodiode of LD1 764:Src/main.c **** LD2_param.POWER = MPhD_T(2);//Get Data from monitor photodiode of LD2 765:Src/main.c **** LD2_param.POWER = MPhD_T(2);//Get Data from monitor photodiode of LD2 766:Src/main.c **** 767:Src/main.c **** Long_Data[1] = LD1_param.POWER;//Translate Data from monitor photodiode of LD1 to Long_Data 768:Src/main.c **** Long_Data[2] = LD2_param.POWER;//Translate Data from monitor photodiode of LD2 to Long_Data 769:Src/main.c **** 770:Src/main.c **** //Prepare DATA of internals ADCs 771:Src/main.c **** //Put the temperature of LD2 to Long_Data: 772:Src/main.c **** temp16 = Get_ADC(0); 773:Src/main.c **** temp16 = Get_ADC(1); 774:Src/main.c **** Long_Data[7] = temp16; 775:Src/main.c **** 776:Src/main.c **** //Put the temperature of LD2 to Long_Data: 777:Src/main.c **** temp16 = Get_ADC(1); 778:Src/main.c **** Long_Data[8] = temp16; 779:Src/main.c **** 780:Src/main.c **** //Put the temperature of LD2 to Long_Data: 781:Src/main.c **** temp16 = Get_ADC(1); 782:Src/main.c **** Long_Data[9] = temp16; 783:Src/main.c **** 784:Src/main.c **** //Put the temperature of LD2 to Long_Data: 785:Src/main.c **** temp16 = Get_ADC(1); 786:Src/main.c **** Long_Data[10] = temp16; 787:Src/main.c **** 788:Src/main.c **** //Put the temperature of LD2 to Long_Data: ARM GAS /tmp/ccYgfTud.s page 53 789:Src/main.c **** temp16 = Get_ADC(1); 790:Src/main.c **** Long_Data[11] = temp16; 791:Src/main.c **** temp16 = Get_ADC(2); 792:Src/main.c **** 793:Src/main.c **** //Put the temperature of LD2 to Long_Data: 794:Src/main.c **** temp16 = Get_ADC(3); 795:Src/main.c **** temp16 = Get_ADC(4); 796:Src/main.c **** Long_Data[12] = temp16; 797:Src/main.c **** temp16 = Get_ADC(5); 798:Src/main.c **** 799:Src/main.c **** //Put the timer tick to Long_Data: 800:Src/main.c **** TO6_stop = TO6; 801:Src/main.c **** Long_Data[3] = (TO6_stop)&0xffff; 802:Src/main.c **** Long_Data[4] = (TO6_stop>>16)&0xffff; 803:Src/main.c **** 804:Src/main.c **** //Put the average temperature of LD1 to Long_Data: 805:Src/main.c **** Long_Data[5] = LD1_param.LD_CURR_TEMP; 806:Src/main.c **** 807:Src/main.c **** //Put the average temperature of LD2 to Long_Data: 808:Src/main.c **** Long_Data[6] = LD2_param.LD_CURR_TEMP; 809:Src/main.c **** } 810:Src/main.c **** while (!TIM10_coflag); 811:Src/main.c **** 812:Src/main.c **** Stop_TIM10(); 813:Src/main.c **** 814:Src/main.c **** if (task.tau > 3) 815:Src/main.c **** { 816:Src/main.c **** htim10.Init.Period = TIM10_period; 817:Src/main.c **** TO10_counter = task.dt / 10; 818:Src/main.c **** } 819:Src/main.c **** 820:Src/main.c **** CPU_state_old = RUN_TASK; 821:Src/main.c **** break; 822:Src/main.c **** } 823:Src/main.c **** 824:Src/main.c **** switch (UART_transmission_request) 825:Src/main.c **** { 826:Src/main.c **** case MESS_01://Default state 827:Src/main.c **** USART_TX(State_Data,2); 828:Src/main.c **** //HAL_UART_Transmit(&huart1, State_Data, 2, 10); 829:Src/main.c **** State_Data[0]=0; 830:Src/main.c **** State_Data[1]=0;//All OK! 831:Src/main.c **** UART_transmission_request = NO_MESS; 832:Src/main.c **** break; 833:Src/main.c **** case MESS_02://Transmith packet 834:Src/main.c **** 835:Src/main.c **** //Find CS and put to Long_Data: 836:Src/main.c **** CS_result = CalculateChecksum(&Long_Data[1], DL_16-2); 837:Src/main.c **** Long_Data[DL_16-1] = CS_result; 838:Src/main.c **** 839:Src/main.c **** for (uint16_t i = 0; i < DL_16; i++) 840:Src/main.c **** { 841:Src/main.c **** UART_DATA[i*2] = (Long_Data[i])&0xff; 842:Src/main.c **** UART_DATA[i*2+1] = (Long_Data[i]>>8)&0xff; 843:Src/main.c **** } 844:Src/main.c **** //HAL_NVIC_SetPriority(DMA2_Stream7_IRQn, 0, 0); 845:Src/main.c **** //HAL_NVIC_EnableIRQ(DMA2_Stream7_IRQn); ARM GAS /tmp/ccYgfTud.s page 54 846:Src/main.c **** //HAL_UART_Transmit_DMA(&huart1, UART_DATA, DL_8); 847:Src/main.c **** //huart1.gState = HAL_UART_STATE_READY; 848:Src/main.c **** //hdma_usart1_tx.State=HAL_DMA_STATE_BUSY; 849:Src/main.c **** USART_TX_DMA (DL_8);//Send data by USART using DMA 850:Src/main.c **** UART_transmission_request = NO_MESS; 851:Src/main.c **** break; 852:Src/main.c **** case MESS_03://Transmith saved packet 853:Src/main.c **** for (uint16_t i = 0; i < DL_16; i++) 854:Src/main.c **** { 855:Src/main.c **** UART_DATA[i*2] = (Long_Data[i])&0xff; 856:Src/main.c **** UART_DATA[i*2+1] = (Long_Data[i]>>8)&0xff; 857:Src/main.c **** } 858:Src/main.c **** //HAL_NVIC_EnableIRQ(DMA2_Stream7_IRQn); 859:Src/main.c **** //HAL_UART_Transmit_DMA(&huart1, UART_DATA, DL_8); 860:Src/main.c **** //huart1.gState = HAL_UART_STATE_READY; 861:Src/main.c **** //hdma_usart1_tx.State=HAL_DMA_STATE_BUSY; 862:Src/main.c **** USART_TX_DMA (DL_8);//Send data by USART using DMA 863:Src/main.c **** UART_transmission_request = NO_MESS; 864:Src/main.c **** break; 865:Src/main.c **** } 866:Src/main.c **** if ((flg_tmt==1)&&((TO6-TO6_uart)>100))//Uart timeout handle. if timeout beetween zero byte of 867:Src/main.c **** { 868:Src/main.c **** UART_rec_incr = 0;//Reset uart command counter 869:Src/main.c **** State_Data[0] |= UART_ERR;//timeout error! 870:Src/main.c **** UART_transmission_request = MESS_01;//Send status 871:Src/main.c **** flg_tmt = 0;//Reset timeout flag 872:Src/main.c **** } 873:Src/main.c **** /* USER CODE END WHILE */ 874:Src/main.c **** 875:Src/main.c **** /* USER CODE BEGIN 3 */ 876:Src/main.c **** } 877:Src/main.c **** /* USER CODE END 3 */ 878:Src/main.c **** } 879:Src/main.c **** 880:Src/main.c **** /** 881:Src/main.c **** * @brief System Clock Configuration 882:Src/main.c **** * @retval None 883:Src/main.c **** */ 884:Src/main.c **** void SystemClock_Config(void) 885:Src/main.c **** { 886:Src/main.c **** RCC_OscInitTypeDef RCC_OscInitStruct = {0}; 887:Src/main.c **** RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; 888:Src/main.c **** 889:Src/main.c **** /** Configure the main internal regulator output voltage 890:Src/main.c **** */ 891:Src/main.c **** __HAL_RCC_PWR_CLK_ENABLE(); 892:Src/main.c **** __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); 893:Src/main.c **** 894:Src/main.c **** /** Initializes the RCC Oscillators according to the specified parameters 895:Src/main.c **** * in the RCC_OscInitTypeDef structure. 896:Src/main.c **** */ 897:Src/main.c **** RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; 898:Src/main.c **** RCC_OscInitStruct.HSEState = RCC_HSE_ON; 899:Src/main.c **** RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; 900:Src/main.c **** RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; 901:Src/main.c **** RCC_OscInitStruct.PLL.PLLM = 25; 902:Src/main.c **** RCC_OscInitStruct.PLL.PLLN = 368; ARM GAS /tmp/ccYgfTud.s page 55 903:Src/main.c **** RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; 904:Src/main.c **** RCC_OscInitStruct.PLL.PLLQ = 8; 905:Src/main.c **** RCC_OscInitStruct.PLL.PLLR = 2; 906:Src/main.c **** if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) 907:Src/main.c **** { 908:Src/main.c **** Error_Handler(); 909:Src/main.c **** } 910:Src/main.c **** 911:Src/main.c **** /** Activate the Over-Drive mode 912:Src/main.c **** */ 913:Src/main.c **** if (HAL_PWREx_EnableOverDrive() != HAL_OK) 914:Src/main.c **** { 915:Src/main.c **** Error_Handler(); 916:Src/main.c **** } 917:Src/main.c **** 918:Src/main.c **** /** Initializes the CPU, AHB and APB buses clocks 919:Src/main.c **** */ 920:Src/main.c **** RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK 921:Src/main.c **** |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; 922:Src/main.c **** RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; 923:Src/main.c **** RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; 924:Src/main.c **** RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4; 925:Src/main.c **** RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; 926:Src/main.c **** 927:Src/main.c **** if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_6) != HAL_OK) 928:Src/main.c **** { 929:Src/main.c **** Error_Handler(); 930:Src/main.c **** } 931:Src/main.c **** } 932:Src/main.c **** 933:Src/main.c **** /** 934:Src/main.c **** * @brief ADC1 Initialization Function 935:Src/main.c **** * @param None 936:Src/main.c **** * @retval None 937:Src/main.c **** */ 938:Src/main.c **** static void MX_ADC1_Init(void) 939:Src/main.c **** { 940:Src/main.c **** 941:Src/main.c **** /* USER CODE BEGIN ADC1_Init 0 */ 942:Src/main.c **** 943:Src/main.c **** /* USER CODE END ADC1_Init 0 */ 944:Src/main.c **** 945:Src/main.c **** ADC_ChannelConfTypeDef sConfig = {0}; 946:Src/main.c **** 947:Src/main.c **** /* USER CODE BEGIN ADC1_Init 1 */ 948:Src/main.c **** 949:Src/main.c **** /* USER CODE END ADC1_Init 1 */ 950:Src/main.c **** 951:Src/main.c **** /** Configure the global features of the ADC (Clock, Resolution, Data Alignment and number of con 952:Src/main.c **** */ 953:Src/main.c **** hadc1.Instance = ADC1; 954:Src/main.c **** hadc1.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV8; 955:Src/main.c **** hadc1.Init.Resolution = ADC_RESOLUTION_12B; 956:Src/main.c **** hadc1.Init.ScanConvMode = ADC_SCAN_ENABLE; 957:Src/main.c **** hadc1.Init.ContinuousConvMode = DISABLE; 958:Src/main.c **** hadc1.Init.DiscontinuousConvMode = DISABLE; 959:Src/main.c **** hadc1.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE; ARM GAS /tmp/ccYgfTud.s page 56 960:Src/main.c **** hadc1.Init.ExternalTrigConv = ADC_SOFTWARE_START; 961:Src/main.c **** hadc1.Init.DataAlign = ADC_DATAALIGN_RIGHT; 962:Src/main.c **** hadc1.Init.NbrOfConversion = 5; 963:Src/main.c **** hadc1.Init.DMAContinuousRequests = DISABLE; 964:Src/main.c **** hadc1.Init.EOCSelection = ADC_EOC_SINGLE_CONV; 965:Src/main.c **** if (HAL_ADC_Init(&hadc1) != HAL_OK) 966:Src/main.c **** { 967:Src/main.c **** Error_Handler(); 968:Src/main.c **** } 969:Src/main.c **** 970:Src/main.c **** /** Configure for the selected ADC regular channel its corresponding rank in the sequencer and it 971:Src/main.c **** */ 972:Src/main.c **** sConfig.Channel = ADC_CHANNEL_9; 973:Src/main.c **** sConfig.Rank = ADC_REGULAR_RANK_1; 974:Src/main.c **** sConfig.SamplingTime = ADC_SAMPLETIME_480CYCLES; 975:Src/main.c **** if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 976:Src/main.c **** { 977:Src/main.c **** Error_Handler(); 978:Src/main.c **** } 979:Src/main.c **** 980:Src/main.c **** /** Configure for the selected ADC regular channel its corresponding rank in the sequencer and it 981:Src/main.c **** */ 982:Src/main.c **** sConfig.Channel = ADC_CHANNEL_8; 983:Src/main.c **** sConfig.Rank = ADC_REGULAR_RANK_2; 984:Src/main.c **** if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 985:Src/main.c **** { 986:Src/main.c **** Error_Handler(); 987:Src/main.c **** } 988:Src/main.c **** 989:Src/main.c **** /** Configure for the selected ADC regular channel its corresponding rank in the sequencer and it 990:Src/main.c **** */ 991:Src/main.c **** sConfig.Channel = ADC_CHANNEL_2; 992:Src/main.c **** sConfig.Rank = ADC_REGULAR_RANK_3; 993:Src/main.c **** if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 994:Src/main.c **** { 995:Src/main.c **** Error_Handler(); 996:Src/main.c **** } 997:Src/main.c **** 998:Src/main.c **** /** Configure for the selected ADC regular channel its corresponding rank in the sequencer and it 999:Src/main.c **** */ 1000:Src/main.c **** sConfig.Channel = ADC_CHANNEL_10; 1001:Src/main.c **** sConfig.Rank = ADC_REGULAR_RANK_4; 1002:Src/main.c **** if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 1003:Src/main.c **** { 1004:Src/main.c **** Error_Handler(); 1005:Src/main.c **** } 1006:Src/main.c **** 1007:Src/main.c **** /** Configure for the selected ADC regular channel its corresponding rank in the sequencer and it 1008:Src/main.c **** */ 1009:Src/main.c **** sConfig.Channel = ADC_CHANNEL_11; 1010:Src/main.c **** sConfig.Rank = ADC_REGULAR_RANK_5; 1011:Src/main.c **** if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 1012:Src/main.c **** { 1013:Src/main.c **** Error_Handler(); 1014:Src/main.c **** } 1015:Src/main.c **** /* USER CODE BEGIN ADC1_Init 2 */ 1016:Src/main.c **** ARM GAS /tmp/ccYgfTud.s page 57 1017:Src/main.c **** /* USER CODE END ADC1_Init 2 */ 1018:Src/main.c **** 1019:Src/main.c **** } 1020:Src/main.c **** 1021:Src/main.c **** /** 1022:Src/main.c **** * @brief ADC3 Initialization Function 1023:Src/main.c **** * @param None 1024:Src/main.c **** * @retval None 1025:Src/main.c **** */ 1026:Src/main.c **** static void MX_ADC3_Init(void) 1027:Src/main.c **** { 1028:Src/main.c **** 1029:Src/main.c **** /* USER CODE BEGIN ADC3_Init 0 */ 1030:Src/main.c **** 1031:Src/main.c **** /* USER CODE END ADC3_Init 0 */ 1032:Src/main.c **** 1033:Src/main.c **** ADC_ChannelConfTypeDef sConfig = {0}; 1034:Src/main.c **** 1035:Src/main.c **** /* USER CODE BEGIN ADC3_Init 1 */ 1036:Src/main.c **** 1037:Src/main.c **** /* USER CODE END ADC3_Init 1 */ 1038:Src/main.c **** 1039:Src/main.c **** /** Configure the global features of the ADC (Clock, Resolution, Data Alignment and number of con 1040:Src/main.c **** */ 1041:Src/main.c **** hadc3.Instance = ADC3; 1042:Src/main.c **** hadc3.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV8; 1043:Src/main.c **** hadc3.Init.Resolution = ADC_RESOLUTION_12B; 1044:Src/main.c **** hadc3.Init.ScanConvMode = ADC_SCAN_DISABLE; 1045:Src/main.c **** hadc3.Init.ContinuousConvMode = DISABLE; 1046:Src/main.c **** hadc3.Init.DiscontinuousConvMode = DISABLE; 1047:Src/main.c **** hadc3.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE; 1048:Src/main.c **** hadc3.Init.ExternalTrigConv = ADC_SOFTWARE_START; 1049:Src/main.c **** hadc3.Init.DataAlign = ADC_DATAALIGN_RIGHT; 1050:Src/main.c **** hadc3.Init.NbrOfConversion = 1; 1051:Src/main.c **** hadc3.Init.DMAContinuousRequests = DISABLE; 1052:Src/main.c **** hadc3.Init.EOCSelection = ADC_EOC_SINGLE_CONV; 1053:Src/main.c **** if (HAL_ADC_Init(&hadc3) != HAL_OK) 1054:Src/main.c **** { 1055:Src/main.c **** Error_Handler(); 1056:Src/main.c **** } 1057:Src/main.c **** 1058:Src/main.c **** /** Configure for the selected ADC regular channel its corresponding rank in the sequencer and it 1059:Src/main.c **** */ 1060:Src/main.c **** sConfig.Channel = ADC_CHANNEL_15; 1061:Src/main.c **** sConfig.Rank = ADC_REGULAR_RANK_1; 1062:Src/main.c **** sConfig.SamplingTime = ADC_SAMPLETIME_480CYCLES; 1063:Src/main.c **** if (HAL_ADC_ConfigChannel(&hadc3, &sConfig) != HAL_OK) 1064:Src/main.c **** { 1065:Src/main.c **** Error_Handler(); 1066:Src/main.c **** } 1067:Src/main.c **** /* USER CODE BEGIN ADC3_Init 2 */ 1068:Src/main.c **** 1069:Src/main.c **** /* USER CODE END ADC3_Init 2 */ 1070:Src/main.c **** 1071:Src/main.c **** } 1072:Src/main.c **** 1073:Src/main.c **** /** ARM GAS /tmp/ccYgfTud.s page 58 1074:Src/main.c **** * @brief SDMMC1 Initialization Function 1075:Src/main.c **** * @param None 1076:Src/main.c **** * @retval None 1077:Src/main.c **** */ 1078:Src/main.c **** static void MX_SDMMC1_SD_Init(void) 1079:Src/main.c **** { 95 .loc 1 1079 1 is_stmt 1 view -0 96 .cfi_startproc 97 @ args = 0, pretend = 0, frame = 0 98 @ frame_needed = 0, uses_anonymous_args = 0 99 @ link register save eliminated. 1080:Src/main.c **** 1081:Src/main.c **** /* USER CODE BEGIN SDMMC1_Init 0 */ 1082:Src/main.c **** 1083:Src/main.c **** /* USER CODE END SDMMC1_Init 0 */ 1084:Src/main.c **** 1085:Src/main.c **** /* USER CODE BEGIN SDMMC1_Init 1 */ 1086:Src/main.c **** 1087:Src/main.c **** /* USER CODE END SDMMC1_Init 1 */ 1088:Src/main.c **** hsd1.Instance = SDMMC1; 100 .loc 1 1088 3 view .LVU21 101 .loc 1 1088 17 is_stmt 0 view .LVU22 102 0000 064B ldr r3, .L6 103 0002 074A ldr r2, .L6+4 104 0004 1A60 str r2, [r3] 1089:Src/main.c **** hsd1.Init.ClockEdge = SDMMC_CLOCK_EDGE_RISING; 105 .loc 1 1089 3 is_stmt 1 view .LVU23 106 .loc 1 1089 23 is_stmt 0 view .LVU24 107 0006 0022 movs r2, #0 108 0008 5A60 str r2, [r3, #4] 1090:Src/main.c **** hsd1.Init.ClockBypass = SDMMC_CLOCK_BYPASS_DISABLE; 109 .loc 1 1090 3 is_stmt 1 view .LVU25 110 .loc 1 1090 25 is_stmt 0 view .LVU26 111 000a 9A60 str r2, [r3, #8] 1091:Src/main.c **** hsd1.Init.ClockPowerSave = SDMMC_CLOCK_POWER_SAVE_DISABLE; 112 .loc 1 1091 3 is_stmt 1 view .LVU27 113 .loc 1 1091 28 is_stmt 0 view .LVU28 114 000c DA60 str r2, [r3, #12] 1092:Src/main.c **** hsd1.Init.BusWide = SDMMC_BUS_WIDE_4B; 115 .loc 1 1092 3 is_stmt 1 view .LVU29 116 .loc 1 1092 21 is_stmt 0 view .LVU30 117 000e 4FF40061 mov r1, #2048 118 0012 1961 str r1, [r3, #16] 1093:Src/main.c **** hsd1.Init.HardwareFlowControl = SDMMC_HARDWARE_FLOW_CONTROL_DISABLE; 119 .loc 1 1093 3 is_stmt 1 view .LVU31 120 .loc 1 1093 33 is_stmt 0 view .LVU32 121 0014 5A61 str r2, [r3, #20] 1094:Src/main.c **** hsd1.Init.ClockDiv = 20; 122 .loc 1 1094 3 is_stmt 1 view .LVU33 123 .loc 1 1094 22 is_stmt 0 view .LVU34 124 0016 1422 movs r2, #20 125 0018 9A61 str r2, [r3, #24] 1095:Src/main.c **** /* USER CODE BEGIN SDMMC1_Init 2 */ 1096:Src/main.c **** 1097:Src/main.c **** /* USER CODE END SDMMC1_Init 2 */ 1098:Src/main.c **** 1099:Src/main.c **** } ARM GAS /tmp/ccYgfTud.s page 59 126 .loc 1 1099 1 view .LVU35 127 001a 7047 bx lr 128 .L7: 129 .align 2 130 .L6: 131 001c 00000000 .word hsd1 132 0020 002C0140 .word 1073818624 133 .cfi_endproc 134 .LFE1190: 136 .section .text.MX_DMA_Init,"ax",%progbits 137 .align 1 138 .syntax unified 139 .thumb 140 .thumb_func 142 MX_DMA_Init: 143 .LFB1205: 1100:Src/main.c **** 1101:Src/main.c **** /** 1102:Src/main.c **** * @brief SPI2 Initialization Function 1103:Src/main.c **** * @param None 1104:Src/main.c **** * @retval None 1105:Src/main.c **** */ 1106:Src/main.c **** static void MX_SPI2_Init(void) 1107:Src/main.c **** { 1108:Src/main.c **** 1109:Src/main.c **** /* USER CODE BEGIN SPI2_Init 0 */ 1110:Src/main.c **** 1111:Src/main.c **** /* USER CODE END SPI2_Init 0 */ 1112:Src/main.c **** 1113:Src/main.c **** LL_SPI_InitTypeDef SPI_InitStruct = {0}; 1114:Src/main.c **** 1115:Src/main.c **** LL_GPIO_InitTypeDef GPIO_InitStruct = {0}; 1116:Src/main.c **** 1117:Src/main.c **** /* Peripheral clock enable */ 1118:Src/main.c **** LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_SPI2); 1119:Src/main.c **** 1120:Src/main.c **** LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_GPIOB); 1121:Src/main.c **** /**SPI2 GPIO Configuration 1122:Src/main.c **** PB13 ------> SPI2_SCK 1123:Src/main.c **** PB14 ------> SPI2_MISO 1124:Src/main.c **** PB15 ------> SPI2_MOSI 1125:Src/main.c **** */ 1126:Src/main.c **** GPIO_InitStruct.Pin = LL_GPIO_PIN_13; 1127:Src/main.c **** GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE; 1128:Src/main.c **** GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH; 1129:Src/main.c **** GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; 1130:Src/main.c **** GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; 1131:Src/main.c **** GPIO_InitStruct.Alternate = LL_GPIO_AF_5; 1132:Src/main.c **** LL_GPIO_Init(GPIOB, &GPIO_InitStruct); 1133:Src/main.c **** 1134:Src/main.c **** GPIO_InitStruct.Pin = LL_GPIO_PIN_14; 1135:Src/main.c **** GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE; 1136:Src/main.c **** GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH; 1137:Src/main.c **** GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; 1138:Src/main.c **** GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; 1139:Src/main.c **** GPIO_InitStruct.Alternate = LL_GPIO_AF_5; 1140:Src/main.c **** LL_GPIO_Init(GPIOB, &GPIO_InitStruct); ARM GAS /tmp/ccYgfTud.s page 60 1141:Src/main.c **** 1142:Src/main.c **** GPIO_InitStruct.Pin = LL_GPIO_PIN_15; 1143:Src/main.c **** GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE; 1144:Src/main.c **** GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH; 1145:Src/main.c **** GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; 1146:Src/main.c **** GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; 1147:Src/main.c **** GPIO_InitStruct.Alternate = LL_GPIO_AF_5; 1148:Src/main.c **** LL_GPIO_Init(GPIOB, &GPIO_InitStruct); 1149:Src/main.c **** 1150:Src/main.c **** /* USER CODE BEGIN SPI2_Init 1 */ 1151:Src/main.c **** 1152:Src/main.c **** /* USER CODE END SPI2_Init 1 */ 1153:Src/main.c **** /* SPI2 parameter configuration*/ 1154:Src/main.c **** SPI_InitStruct.TransferDirection = LL_SPI_FULL_DUPLEX; 1155:Src/main.c **** SPI_InitStruct.Mode = LL_SPI_MODE_MASTER; 1156:Src/main.c **** SPI_InitStruct.DataWidth = LL_SPI_DATAWIDTH_16BIT; 1157:Src/main.c **** SPI_InitStruct.ClockPolarity = LL_SPI_POLARITY_LOW; 1158:Src/main.c **** SPI_InitStruct.ClockPhase = LL_SPI_PHASE_1EDGE; 1159:Src/main.c **** SPI_InitStruct.NSS = LL_SPI_NSS_SOFT; 1160:Src/main.c **** SPI_InitStruct.BaudRate = LL_SPI_BAUDRATEPRESCALER_DIV8; 1161:Src/main.c **** SPI_InitStruct.BitOrder = LL_SPI_MSB_FIRST; 1162:Src/main.c **** SPI_InitStruct.CRCCalculation = LL_SPI_CRCCALCULATION_DISABLE; 1163:Src/main.c **** SPI_InitStruct.CRCPoly = 7; 1164:Src/main.c **** LL_SPI_Init(SPI2, &SPI_InitStruct); 1165:Src/main.c **** LL_SPI_SetStandard(SPI2, LL_SPI_PROTOCOL_MOTOROLA); 1166:Src/main.c **** LL_SPI_DisableNSSPulseMgt(SPI2); 1167:Src/main.c **** /* USER CODE BEGIN SPI2_Init 2 */ 1168:Src/main.c **** 1169:Src/main.c **** /* USER CODE END SPI2_Init 2 */ 1170:Src/main.c **** 1171:Src/main.c **** } 1172:Src/main.c **** 1173:Src/main.c **** /** 1174:Src/main.c **** * @brief SPI4 Initialization Function 1175:Src/main.c **** * @param None 1176:Src/main.c **** * @retval None 1177:Src/main.c **** */ 1178:Src/main.c **** static void MX_SPI4_Init(void) 1179:Src/main.c **** { 1180:Src/main.c **** 1181:Src/main.c **** /* USER CODE BEGIN SPI4_Init 0 */ 1182:Src/main.c **** 1183:Src/main.c **** /* USER CODE END SPI4_Init 0 */ 1184:Src/main.c **** 1185:Src/main.c **** LL_SPI_InitTypeDef SPI_InitStruct = {0}; 1186:Src/main.c **** 1187:Src/main.c **** LL_GPIO_InitTypeDef GPIO_InitStruct = {0}; 1188:Src/main.c **** 1189:Src/main.c **** /* Peripheral clock enable */ 1190:Src/main.c **** LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_SPI4); 1191:Src/main.c **** 1192:Src/main.c **** LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_GPIOE); 1193:Src/main.c **** /**SPI4 GPIO Configuration 1194:Src/main.c **** PE12 ------> SPI4_SCK 1195:Src/main.c **** PE13 ------> SPI4_MISO 1196:Src/main.c **** */ 1197:Src/main.c **** GPIO_InitStruct.Pin = LL_GPIO_PIN_12; ARM GAS /tmp/ccYgfTud.s page 61 1198:Src/main.c **** GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE; 1199:Src/main.c **** GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH; 1200:Src/main.c **** GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; 1201:Src/main.c **** GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; 1202:Src/main.c **** GPIO_InitStruct.Alternate = LL_GPIO_AF_5; 1203:Src/main.c **** LL_GPIO_Init(GPIOE, &GPIO_InitStruct); 1204:Src/main.c **** 1205:Src/main.c **** GPIO_InitStruct.Pin = LL_GPIO_PIN_13; 1206:Src/main.c **** GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE; 1207:Src/main.c **** GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH; 1208:Src/main.c **** GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; 1209:Src/main.c **** GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; 1210:Src/main.c **** GPIO_InitStruct.Alternate = LL_GPIO_AF_5; 1211:Src/main.c **** LL_GPIO_Init(GPIOE, &GPIO_InitStruct); 1212:Src/main.c **** 1213:Src/main.c **** /* USER CODE BEGIN SPI4_Init 1 */ 1214:Src/main.c **** 1215:Src/main.c **** /* USER CODE END SPI4_Init 1 */ 1216:Src/main.c **** /* SPI4 parameter configuration*/ 1217:Src/main.c **** SPI_InitStruct.TransferDirection = LL_SPI_SIMPLEX_RX; 1218:Src/main.c **** SPI_InitStruct.Mode = LL_SPI_MODE_MASTER; 1219:Src/main.c **** SPI_InitStruct.DataWidth = LL_SPI_DATAWIDTH_16BIT; 1220:Src/main.c **** SPI_InitStruct.ClockPolarity = LL_SPI_POLARITY_HIGH; 1221:Src/main.c **** SPI_InitStruct.ClockPhase = LL_SPI_PHASE_1EDGE; 1222:Src/main.c **** SPI_InitStruct.NSS = LL_SPI_NSS_SOFT; 1223:Src/main.c **** SPI_InitStruct.BaudRate = LL_SPI_BAUDRATEPRESCALER_DIV16; 1224:Src/main.c **** SPI_InitStruct.BitOrder = LL_SPI_MSB_FIRST; 1225:Src/main.c **** SPI_InitStruct.CRCCalculation = LL_SPI_CRCCALCULATION_DISABLE; 1226:Src/main.c **** SPI_InitStruct.CRCPoly = 7; 1227:Src/main.c **** LL_SPI_Init(SPI4, &SPI_InitStruct); 1228:Src/main.c **** LL_SPI_SetStandard(SPI4, LL_SPI_PROTOCOL_MOTOROLA); 1229:Src/main.c **** LL_SPI_DisableNSSPulseMgt(SPI4); 1230:Src/main.c **** /* USER CODE BEGIN SPI4_Init 2 */ 1231:Src/main.c **** 1232:Src/main.c **** /* USER CODE END SPI4_Init 2 */ 1233:Src/main.c **** 1234:Src/main.c **** } 1235:Src/main.c **** 1236:Src/main.c **** /** 1237:Src/main.c **** * @brief SPI5 Initialization Function 1238:Src/main.c **** * @param None 1239:Src/main.c **** * @retval None 1240:Src/main.c **** */ 1241:Src/main.c **** static void MX_SPI5_Init(void) 1242:Src/main.c **** { 1243:Src/main.c **** 1244:Src/main.c **** /* USER CODE BEGIN SPI5_Init 0 */ 1245:Src/main.c **** 1246:Src/main.c **** /* USER CODE END SPI5_Init 0 */ 1247:Src/main.c **** 1248:Src/main.c **** LL_SPI_InitTypeDef SPI_InitStruct = {0}; 1249:Src/main.c **** 1250:Src/main.c **** LL_GPIO_InitTypeDef GPIO_InitStruct = {0}; 1251:Src/main.c **** 1252:Src/main.c **** /* Peripheral clock enable */ 1253:Src/main.c **** LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_SPI5); 1254:Src/main.c **** ARM GAS /tmp/ccYgfTud.s page 62 1255:Src/main.c **** LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_GPIOF); 1256:Src/main.c **** /**SPI5 GPIO Configuration 1257:Src/main.c **** PF7 ------> SPI5_SCK 1258:Src/main.c **** PF8 ------> SPI5_MISO 1259:Src/main.c **** */ 1260:Src/main.c **** GPIO_InitStruct.Pin = LL_GPIO_PIN_7; 1261:Src/main.c **** GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE; 1262:Src/main.c **** GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH; 1263:Src/main.c **** GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; 1264:Src/main.c **** GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; 1265:Src/main.c **** GPIO_InitStruct.Alternate = LL_GPIO_AF_5; 1266:Src/main.c **** LL_GPIO_Init(GPIOF, &GPIO_InitStruct); 1267:Src/main.c **** 1268:Src/main.c **** GPIO_InitStruct.Pin = LL_GPIO_PIN_8; 1269:Src/main.c **** GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE; 1270:Src/main.c **** GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH; 1271:Src/main.c **** GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; 1272:Src/main.c **** GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; 1273:Src/main.c **** GPIO_InitStruct.Alternate = LL_GPIO_AF_5; 1274:Src/main.c **** LL_GPIO_Init(GPIOF, &GPIO_InitStruct); 1275:Src/main.c **** 1276:Src/main.c **** /* USER CODE BEGIN SPI5_Init 1 */ 1277:Src/main.c **** 1278:Src/main.c **** /* USER CODE END SPI5_Init 1 */ 1279:Src/main.c **** /* SPI5 parameter configuration*/ 1280:Src/main.c **** SPI_InitStruct.TransferDirection = LL_SPI_SIMPLEX_RX; 1281:Src/main.c **** SPI_InitStruct.Mode = LL_SPI_MODE_MASTER; 1282:Src/main.c **** SPI_InitStruct.DataWidth = LL_SPI_DATAWIDTH_16BIT; 1283:Src/main.c **** SPI_InitStruct.ClockPolarity = LL_SPI_POLARITY_HIGH; 1284:Src/main.c **** SPI_InitStruct.ClockPhase = LL_SPI_PHASE_1EDGE; 1285:Src/main.c **** SPI_InitStruct.NSS = LL_SPI_NSS_SOFT; 1286:Src/main.c **** SPI_InitStruct.BaudRate = LL_SPI_BAUDRATEPRESCALER_DIV16; 1287:Src/main.c **** SPI_InitStruct.BitOrder = LL_SPI_MSB_FIRST; 1288:Src/main.c **** SPI_InitStruct.CRCCalculation = LL_SPI_CRCCALCULATION_DISABLE; 1289:Src/main.c **** SPI_InitStruct.CRCPoly = 7; 1290:Src/main.c **** LL_SPI_Init(SPI5, &SPI_InitStruct); 1291:Src/main.c **** LL_SPI_SetStandard(SPI5, LL_SPI_PROTOCOL_MOTOROLA); 1292:Src/main.c **** LL_SPI_DisableNSSPulseMgt(SPI5); 1293:Src/main.c **** /* USER CODE BEGIN SPI5_Init 2 */ 1294:Src/main.c **** 1295:Src/main.c **** /* USER CODE END SPI5_Init 2 */ 1296:Src/main.c **** 1297:Src/main.c **** } 1298:Src/main.c **** 1299:Src/main.c **** /** 1300:Src/main.c **** * @brief SPI6 Initialization Function 1301:Src/main.c **** * @param None 1302:Src/main.c **** * @retval None 1303:Src/main.c **** */ 1304:Src/main.c **** static void MX_SPI6_Init(void) 1305:Src/main.c **** { 1306:Src/main.c **** 1307:Src/main.c **** /* USER CODE BEGIN SPI6_Init 0 */ 1308:Src/main.c **** 1309:Src/main.c **** /* USER CODE END SPI6_Init 0 */ 1310:Src/main.c **** 1311:Src/main.c **** LL_SPI_InitTypeDef SPI_InitStruct = {0}; ARM GAS /tmp/ccYgfTud.s page 63 1312:Src/main.c **** 1313:Src/main.c **** LL_GPIO_InitTypeDef GPIO_InitStruct = {0}; 1314:Src/main.c **** 1315:Src/main.c **** /* Peripheral clock enable */ 1316:Src/main.c **** LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_SPI6); 1317:Src/main.c **** 1318:Src/main.c **** LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_GPIOA); 1319:Src/main.c **** /**SPI6 GPIO Configuration 1320:Src/main.c **** PA5 ------> SPI6_SCK 1321:Src/main.c **** PA7 ------> SPI6_MOSI 1322:Src/main.c **** */ 1323:Src/main.c **** GPIO_InitStruct.Pin = LL_GPIO_PIN_5; 1324:Src/main.c **** GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE; 1325:Src/main.c **** GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH; 1326:Src/main.c **** GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; 1327:Src/main.c **** GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; 1328:Src/main.c **** GPIO_InitStruct.Alternate = LL_GPIO_AF_8; 1329:Src/main.c **** LL_GPIO_Init(GPIOA, &GPIO_InitStruct); 1330:Src/main.c **** 1331:Src/main.c **** GPIO_InitStruct.Pin = LL_GPIO_PIN_7; 1332:Src/main.c **** GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE; 1333:Src/main.c **** GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH; 1334:Src/main.c **** GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; 1335:Src/main.c **** GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; 1336:Src/main.c **** GPIO_InitStruct.Alternate = LL_GPIO_AF_8; 1337:Src/main.c **** LL_GPIO_Init(GPIOA, &GPIO_InitStruct); 1338:Src/main.c **** 1339:Src/main.c **** /* USER CODE BEGIN SPI6_Init 1 */ 1340:Src/main.c **** 1341:Src/main.c **** /* USER CODE END SPI6_Init 1 */ 1342:Src/main.c **** /* SPI6 parameter configuration*/ 1343:Src/main.c **** SPI_InitStruct.TransferDirection = LL_SPI_FULL_DUPLEX; 1344:Src/main.c **** SPI_InitStruct.Mode = LL_SPI_MODE_MASTER; 1345:Src/main.c **** SPI_InitStruct.DataWidth = LL_SPI_DATAWIDTH_16BIT; 1346:Src/main.c **** SPI_InitStruct.ClockPolarity = LL_SPI_POLARITY_HIGH; 1347:Src/main.c **** SPI_InitStruct.ClockPhase = LL_SPI_PHASE_2EDGE; 1348:Src/main.c **** SPI_InitStruct.NSS = LL_SPI_NSS_SOFT; 1349:Src/main.c **** SPI_InitStruct.BaudRate = LL_SPI_BAUDRATEPRESCALER_DIV16; 1350:Src/main.c **** SPI_InitStruct.BitOrder = LL_SPI_MSB_FIRST; 1351:Src/main.c **** SPI_InitStruct.CRCCalculation = LL_SPI_CRCCALCULATION_DISABLE; 1352:Src/main.c **** SPI_InitStruct.CRCPoly = 7; 1353:Src/main.c **** LL_SPI_Init(SPI6, &SPI_InitStruct); 1354:Src/main.c **** LL_SPI_SetStandard(SPI6, LL_SPI_PROTOCOL_MOTOROLA); 1355:Src/main.c **** LL_SPI_DisableNSSPulseMgt(SPI6); 1356:Src/main.c **** /* USER CODE BEGIN SPI6_Init 2 */ 1357:Src/main.c **** 1358:Src/main.c **** /* USER CODE END SPI6_Init 2 */ 1359:Src/main.c **** 1360:Src/main.c **** } 1361:Src/main.c **** 1362:Src/main.c **** /** 1363:Src/main.c **** * @brief TIM2 Initialization Function 1364:Src/main.c **** * @param None 1365:Src/main.c **** * @retval None 1366:Src/main.c **** */ 1367:Src/main.c **** static void MX_TIM2_Init(void) 1368:Src/main.c **** { ARM GAS /tmp/ccYgfTud.s page 64 1369:Src/main.c **** 1370:Src/main.c **** /* USER CODE BEGIN TIM2_Init 0 */ 1371:Src/main.c **** 1372:Src/main.c **** /* USER CODE END TIM2_Init 0 */ 1373:Src/main.c **** 1374:Src/main.c **** LL_TIM_InitTypeDef TIM_InitStruct = {0}; 1375:Src/main.c **** 1376:Src/main.c **** /* Peripheral clock enable */ 1377:Src/main.c **** LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_TIM2); 1378:Src/main.c **** 1379:Src/main.c **** /* TIM2 interrupt Init */ 1380:Src/main.c **** NVIC_SetPriority(TIM2_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(),0, 0)); 1381:Src/main.c **** NVIC_EnableIRQ(TIM2_IRQn); 1382:Src/main.c **** 1383:Src/main.c **** /* USER CODE BEGIN TIM2_Init 1 */ 1384:Src/main.c **** 1385:Src/main.c **** /* USER CODE END TIM2_Init 1 */ 1386:Src/main.c **** TIM_InitStruct.Prescaler = 1000; 1387:Src/main.c **** TIM_InitStruct.CounterMode = LL_TIM_COUNTERMODE_UP; 1388:Src/main.c **** TIM_InitStruct.Autoreload = 840000; 1389:Src/main.c **** TIM_InitStruct.ClockDivision = LL_TIM_CLOCKDIVISION_DIV1; 1390:Src/main.c **** LL_TIM_Init(TIM2, &TIM_InitStruct); 1391:Src/main.c **** LL_TIM_DisableARRPreload(TIM2); 1392:Src/main.c **** LL_TIM_SetClockSource(TIM2, LL_TIM_CLOCKSOURCE_INTERNAL); 1393:Src/main.c **** LL_TIM_SetTriggerOutput(TIM2, LL_TIM_TRGO_RESET); 1394:Src/main.c **** LL_TIM_DisableMasterSlaveMode(TIM2); 1395:Src/main.c **** /* USER CODE BEGIN TIM2_Init 2 */ 1396:Src/main.c **** 1397:Src/main.c **** /* USER CODE END TIM2_Init 2 */ 1398:Src/main.c **** 1399:Src/main.c **** } 1400:Src/main.c **** 1401:Src/main.c **** /** 1402:Src/main.c **** * @brief TIM4 Initialization Function 1403:Src/main.c **** * @param None 1404:Src/main.c **** * @retval None 1405:Src/main.c **** */ 1406:Src/main.c **** static void MX_TIM4_Init(void) 1407:Src/main.c **** { 1408:Src/main.c **** 1409:Src/main.c **** /* USER CODE BEGIN TIM4_Init 0 */ 1410:Src/main.c **** 1411:Src/main.c **** /* USER CODE END TIM4_Init 0 */ 1412:Src/main.c **** 1413:Src/main.c **** TIM_ClockConfigTypeDef sClockSourceConfig = {0}; 1414:Src/main.c **** TIM_MasterConfigTypeDef sMasterConfig = {0}; 1415:Src/main.c **** TIM_OC_InitTypeDef sConfigOC = {0}; 1416:Src/main.c **** 1417:Src/main.c **** /* USER CODE BEGIN TIM4_Init 1 */ 1418:Src/main.c **** 1419:Src/main.c **** /* USER CODE END TIM4_Init 1 */ 1420:Src/main.c **** htim4.Instance = TIM4; 1421:Src/main.c **** htim4.Init.Prescaler = 0; 1422:Src/main.c **** htim4.Init.CounterMode = TIM_COUNTERMODE_UP; 1423:Src/main.c **** htim4.Init.Period = 45; 1424:Src/main.c **** htim4.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; 1425:Src/main.c **** htim4.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; ARM GAS /tmp/ccYgfTud.s page 65 1426:Src/main.c **** if (HAL_TIM_Base_Init(&htim4) != HAL_OK) 1427:Src/main.c **** { 1428:Src/main.c **** Error_Handler(); 1429:Src/main.c **** } 1430:Src/main.c **** sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL; 1431:Src/main.c **** if (HAL_TIM_ConfigClockSource(&htim4, &sClockSourceConfig) != HAL_OK) 1432:Src/main.c **** { 1433:Src/main.c **** Error_Handler(); 1434:Src/main.c **** } 1435:Src/main.c **** if (HAL_TIM_PWM_Init(&htim4) != HAL_OK) 1436:Src/main.c **** { 1437:Src/main.c **** Error_Handler(); 1438:Src/main.c **** } 1439:Src/main.c **** sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; 1440:Src/main.c **** sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; 1441:Src/main.c **** if (HAL_TIMEx_MasterConfigSynchronization(&htim4, &sMasterConfig) != HAL_OK) 1442:Src/main.c **** { 1443:Src/main.c **** Error_Handler(); 1444:Src/main.c **** } 1445:Src/main.c **** sConfigOC.OCMode = TIM_OCMODE_PWM1; 1446:Src/main.c **** sConfigOC.Pulse = 22; 1447:Src/main.c **** sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH; 1448:Src/main.c **** sConfigOC.OCFastMode = TIM_OCFAST_DISABLE; 1449:Src/main.c **** if (HAL_TIM_PWM_ConfigChannel(&htim4, &sConfigOC, TIM_CHANNEL_3) != HAL_OK) 1450:Src/main.c **** { 1451:Src/main.c **** Error_Handler(); 1452:Src/main.c **** } 1453:Src/main.c **** /* USER CODE BEGIN TIM4_Init 2 */ 1454:Src/main.c **** 1455:Src/main.c **** /* USER CODE END TIM4_Init 2 */ 1456:Src/main.c **** HAL_TIM_MspPostInit(&htim4); 1457:Src/main.c **** 1458:Src/main.c **** } 1459:Src/main.c **** 1460:Src/main.c **** /** 1461:Src/main.c **** * @brief TIM5 Initialization Function 1462:Src/main.c **** * @param None 1463:Src/main.c **** * @retval None 1464:Src/main.c **** */ 1465:Src/main.c **** static void MX_TIM5_Init(void) 1466:Src/main.c **** { 1467:Src/main.c **** 1468:Src/main.c **** /* USER CODE BEGIN TIM5_Init 0 */ 1469:Src/main.c **** 1470:Src/main.c **** /* USER CODE END TIM5_Init 0 */ 1471:Src/main.c **** 1472:Src/main.c **** LL_TIM_InitTypeDef TIM_InitStruct = {0}; 1473:Src/main.c **** 1474:Src/main.c **** /* Peripheral clock enable */ 1475:Src/main.c **** LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_TIM5); 1476:Src/main.c **** 1477:Src/main.c **** /* TIM5 interrupt Init */ 1478:Src/main.c **** NVIC_SetPriority(TIM5_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(),0, 0)); 1479:Src/main.c **** NVIC_EnableIRQ(TIM5_IRQn); 1480:Src/main.c **** 1481:Src/main.c **** /* USER CODE BEGIN TIM5_Init 1 */ 1482:Src/main.c **** ARM GAS /tmp/ccYgfTud.s page 66 1483:Src/main.c **** /* USER CODE END TIM5_Init 1 */ 1484:Src/main.c **** TIM_InitStruct.Prescaler = 10000; 1485:Src/main.c **** TIM_InitStruct.CounterMode = LL_TIM_COUNTERMODE_UP; 1486:Src/main.c **** TIM_InitStruct.Autoreload = 560; 1487:Src/main.c **** TIM_InitStruct.ClockDivision = LL_TIM_CLOCKDIVISION_DIV1; 1488:Src/main.c **** LL_TIM_Init(TIM5, &TIM_InitStruct); 1489:Src/main.c **** LL_TIM_DisableARRPreload(TIM5); 1490:Src/main.c **** LL_TIM_SetClockSource(TIM5, LL_TIM_CLOCKSOURCE_INTERNAL); 1491:Src/main.c **** LL_TIM_SetTriggerOutput(TIM5, LL_TIM_TRGO_RESET); 1492:Src/main.c **** LL_TIM_DisableMasterSlaveMode(TIM5); 1493:Src/main.c **** /* USER CODE BEGIN TIM5_Init 2 */ 1494:Src/main.c **** 1495:Src/main.c **** /* USER CODE END TIM5_Init 2 */ 1496:Src/main.c **** 1497:Src/main.c **** } 1498:Src/main.c **** 1499:Src/main.c **** /** 1500:Src/main.c **** * @brief TIM6 Initialization Function 1501:Src/main.c **** * @param None 1502:Src/main.c **** * @retval None 1503:Src/main.c **** */ 1504:Src/main.c **** static void MX_TIM6_Init(void) 1505:Src/main.c **** { 1506:Src/main.c **** 1507:Src/main.c **** /* USER CODE BEGIN TIM6_Init 0 */ 1508:Src/main.c **** 1509:Src/main.c **** /* USER CODE END TIM6_Init 0 */ 1510:Src/main.c **** 1511:Src/main.c **** LL_TIM_InitTypeDef TIM_InitStruct = {0}; 1512:Src/main.c **** 1513:Src/main.c **** /* Peripheral clock enable */ 1514:Src/main.c **** LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_TIM6); 1515:Src/main.c **** 1516:Src/main.c **** /* TIM6 interrupt Init */ 1517:Src/main.c **** NVIC_SetPriority(TIM6_DAC_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(),0, 0)); 1518:Src/main.c **** NVIC_EnableIRQ(TIM6_DAC_IRQn); 1519:Src/main.c **** 1520:Src/main.c **** /* USER CODE BEGIN TIM6_Init 1 */ 1521:Src/main.c **** 1522:Src/main.c **** /* USER CODE END TIM6_Init 1 */ 1523:Src/main.c **** TIM_InitStruct.Prescaler = 45999; 1524:Src/main.c **** TIM_InitStruct.CounterMode = LL_TIM_COUNTERMODE_UP; 1525:Src/main.c **** TIM_InitStruct.Autoreload = 19; 1526:Src/main.c **** LL_TIM_Init(TIM6, &TIM_InitStruct); 1527:Src/main.c **** LL_TIM_DisableARRPreload(TIM6); 1528:Src/main.c **** LL_TIM_SetTriggerOutput(TIM6, LL_TIM_TRGO_ENABLE); 1529:Src/main.c **** LL_TIM_DisableMasterSlaveMode(TIM6); 1530:Src/main.c **** /* USER CODE BEGIN TIM6_Init 2 */ 1531:Src/main.c **** 1532:Src/main.c **** /* USER CODE END TIM6_Init 2 */ 1533:Src/main.c **** 1534:Src/main.c **** } 1535:Src/main.c **** 1536:Src/main.c **** /** 1537:Src/main.c **** * @brief TIM7 Initialization Function 1538:Src/main.c **** * @param None 1539:Src/main.c **** * @retval None ARM GAS /tmp/ccYgfTud.s page 67 1540:Src/main.c **** */ 1541:Src/main.c **** static void MX_TIM7_Init(void) 1542:Src/main.c **** { 1543:Src/main.c **** 1544:Src/main.c **** /* USER CODE BEGIN TIM7_Init 0 */ 1545:Src/main.c **** 1546:Src/main.c **** /* USER CODE END TIM7_Init 0 */ 1547:Src/main.c **** 1548:Src/main.c **** LL_TIM_InitTypeDef TIM_InitStruct = {0}; 1549:Src/main.c **** 1550:Src/main.c **** /* Peripheral clock enable */ 1551:Src/main.c **** LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_TIM7); 1552:Src/main.c **** 1553:Src/main.c **** /* TIM7 interrupt Init */ 1554:Src/main.c **** NVIC_SetPriority(TIM7_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(),0, 0)); 1555:Src/main.c **** NVIC_EnableIRQ(TIM7_IRQn); 1556:Src/main.c **** 1557:Src/main.c **** /* USER CODE BEGIN TIM7_Init 1 */ 1558:Src/main.c **** 1559:Src/main.c **** /* USER CODE END TIM7_Init 1 */ 1560:Src/main.c **** TIM_InitStruct.Prescaler = 919; 1561:Src/main.c **** TIM_InitStruct.CounterMode = LL_TIM_COUNTERMODE_UP; 1562:Src/main.c **** TIM_InitStruct.Autoreload = 99; 1563:Src/main.c **** LL_TIM_Init(TIM7, &TIM_InitStruct); 1564:Src/main.c **** LL_TIM_DisableARRPreload(TIM7); 1565:Src/main.c **** LL_TIM_SetTriggerOutput(TIM7, LL_TIM_TRGO_ENABLE); 1566:Src/main.c **** LL_TIM_DisableMasterSlaveMode(TIM7); 1567:Src/main.c **** /* USER CODE BEGIN TIM7_Init 2 */ 1568:Src/main.c **** 1569:Src/main.c **** /* USER CODE END TIM7_Init 2 */ 1570:Src/main.c **** 1571:Src/main.c **** } 1572:Src/main.c **** 1573:Src/main.c **** /** 1574:Src/main.c **** * @brief TIM8 Initialization Function 1575:Src/main.c **** * @param None 1576:Src/main.c **** * @retval None 1577:Src/main.c **** */ 1578:Src/main.c **** static void MX_TIM8_Init(void) 1579:Src/main.c **** { 1580:Src/main.c **** 1581:Src/main.c **** /* USER CODE BEGIN TIM8_Init 0 */ 1582:Src/main.c **** 1583:Src/main.c **** /* USER CODE END TIM8_Init 0 */ 1584:Src/main.c **** 1585:Src/main.c **** TIM_ClockConfigTypeDef sClockSourceConfig = {0}; 1586:Src/main.c **** TIM_MasterConfigTypeDef sMasterConfig = {0}; 1587:Src/main.c **** 1588:Src/main.c **** /* USER CODE BEGIN TIM8_Init 1 */ 1589:Src/main.c **** 1590:Src/main.c **** /* USER CODE END TIM8_Init 1 */ 1591:Src/main.c **** htim8.Instance = TIM8; 1592:Src/main.c **** htim8.Init.Prescaler = 0; 1593:Src/main.c **** htim8.Init.CounterMode = TIM_COUNTERMODE_UP; 1594:Src/main.c **** htim8.Init.Period = 91; 1595:Src/main.c **** htim8.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; 1596:Src/main.c **** htim8.Init.RepetitionCounter = 0; ARM GAS /tmp/ccYgfTud.s page 68 1597:Src/main.c **** htim8.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; 1598:Src/main.c **** if (HAL_TIM_Base_Init(&htim8) != HAL_OK) 1599:Src/main.c **** { 1600:Src/main.c **** Error_Handler(); 1601:Src/main.c **** } 1602:Src/main.c **** sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL; 1603:Src/main.c **** if (HAL_TIM_ConfigClockSource(&htim8, &sClockSourceConfig) != HAL_OK) 1604:Src/main.c **** { 1605:Src/main.c **** Error_Handler(); 1606:Src/main.c **** } 1607:Src/main.c **** sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; 1608:Src/main.c **** sMasterConfig.MasterOutputTrigger2 = TIM_TRGO2_RESET; 1609:Src/main.c **** sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; 1610:Src/main.c **** if (HAL_TIMEx_MasterConfigSynchronization(&htim8, &sMasterConfig) != HAL_OK) 1611:Src/main.c **** { 1612:Src/main.c **** Error_Handler(); 1613:Src/main.c **** } 1614:Src/main.c **** /* USER CODE BEGIN TIM8_Init 2 */ 1615:Src/main.c **** 1616:Src/main.c **** /* USER CODE END TIM8_Init 2 */ 1617:Src/main.c **** 1618:Src/main.c **** } 1619:Src/main.c **** 1620:Src/main.c **** /** 1621:Src/main.c **** * @brief TIM10 Initialization Function 1622:Src/main.c **** * @param None 1623:Src/main.c **** * @retval None 1624:Src/main.c **** */ 1625:Src/main.c **** static void MX_TIM10_Init(void) 1626:Src/main.c **** { 1627:Src/main.c **** 1628:Src/main.c **** /* USER CODE BEGIN TIM10_Init 0 */ 1629:Src/main.c **** 1630:Src/main.c **** /* USER CODE END TIM10_Init 0 */ 1631:Src/main.c **** 1632:Src/main.c **** /* USER CODE BEGIN TIM10_Init 1 */ 1633:Src/main.c **** 1634:Src/main.c **** /* USER CODE END TIM10_Init 1 */ 1635:Src/main.c **** htim10.Instance = TIM10; 1636:Src/main.c **** htim10.Init.Prescaler = 183; 1637:Src/main.c **** htim10.Init.CounterMode = TIM_COUNTERMODE_UP; 1638:Src/main.c **** htim10.Init.Period = 9; 1639:Src/main.c **** htim10.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; 1640:Src/main.c **** htim10.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; 1641:Src/main.c **** if (HAL_TIM_Base_Init(&htim10) != HAL_OK) 1642:Src/main.c **** { 1643:Src/main.c **** Error_Handler(); 1644:Src/main.c **** } 1645:Src/main.c **** /* USER CODE BEGIN TIM10_Init 2 */ 1646:Src/main.c **** 1647:Src/main.c **** /* USER CODE END TIM10_Init 2 */ 1648:Src/main.c **** 1649:Src/main.c **** } 1650:Src/main.c **** 1651:Src/main.c **** /** 1652:Src/main.c **** * @brief TIM11 Initialization Function 1653:Src/main.c **** * @param None ARM GAS /tmp/ccYgfTud.s page 69 1654:Src/main.c **** * @retval None 1655:Src/main.c **** */ 1656:Src/main.c **** static void MX_TIM11_Init(void) 1657:Src/main.c **** { 1658:Src/main.c **** 1659:Src/main.c **** /* USER CODE BEGIN TIM11_Init 0 */ 1660:Src/main.c **** 1661:Src/main.c **** /* USER CODE END TIM11_Init 0 */ 1662:Src/main.c **** 1663:Src/main.c **** TIM_OC_InitTypeDef sConfigOC = {0}; 1664:Src/main.c **** 1665:Src/main.c **** /* USER CODE BEGIN TIM11_Init 1 */ 1666:Src/main.c **** 1667:Src/main.c **** /* USER CODE END TIM11_Init 1 */ 1668:Src/main.c **** htim11.Instance = TIM11; 1669:Src/main.c **** htim11.Init.Prescaler = 1; 1670:Src/main.c **** htim11.Init.CounterMode = TIM_COUNTERMODE_UP; 1671:Src/main.c **** htim11.Init.Period = 91; 1672:Src/main.c **** htim11.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; 1673:Src/main.c **** htim11.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_ENABLE; 1674:Src/main.c **** if (HAL_TIM_Base_Init(&htim11) != HAL_OK) 1675:Src/main.c **** { 1676:Src/main.c **** Error_Handler(); 1677:Src/main.c **** } 1678:Src/main.c **** if (HAL_TIM_PWM_Init(&htim11) != HAL_OK) 1679:Src/main.c **** { 1680:Src/main.c **** Error_Handler(); 1681:Src/main.c **** } 1682:Src/main.c **** sConfigOC.OCMode = TIM_OCMODE_PWM1; 1683:Src/main.c **** sConfigOC.Pulse = 91; 1684:Src/main.c **** sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH; 1685:Src/main.c **** sConfigOC.OCFastMode = TIM_OCFAST_DISABLE; 1686:Src/main.c **** if (HAL_TIM_PWM_ConfigChannel(&htim11, &sConfigOC, TIM_CHANNEL_1) != HAL_OK) 1687:Src/main.c **** { 1688:Src/main.c **** Error_Handler(); 1689:Src/main.c **** } 1690:Src/main.c **** /* USER CODE BEGIN TIM11_Init 2 */ 1691:Src/main.c **** 1692:Src/main.c **** /* USER CODE END TIM11_Init 2 */ 1693:Src/main.c **** HAL_TIM_MspPostInit(&htim11); 1694:Src/main.c **** 1695:Src/main.c **** } 1696:Src/main.c **** 1697:Src/main.c **** /** 1698:Src/main.c **** * @brief UART8 Initialization Function 1699:Src/main.c **** * @param None 1700:Src/main.c **** * @retval None 1701:Src/main.c **** */ 1702:Src/main.c **** static void MX_UART8_Init(void) 1703:Src/main.c **** { 1704:Src/main.c **** 1705:Src/main.c **** /* USER CODE BEGIN UART8_Init 0 */ 1706:Src/main.c **** 1707:Src/main.c **** /* USER CODE END UART8_Init 0 */ 1708:Src/main.c **** 1709:Src/main.c **** /* USER CODE BEGIN UART8_Init 1 */ 1710:Src/main.c **** ARM GAS /tmp/ccYgfTud.s page 70 1711:Src/main.c **** /* USER CODE END UART8_Init 1 */ 1712:Src/main.c **** huart8.Instance = UART8; 1713:Src/main.c **** huart8.Init.BaudRate = 115200; 1714:Src/main.c **** huart8.Init.WordLength = UART_WORDLENGTH_8B; 1715:Src/main.c **** huart8.Init.StopBits = UART_STOPBITS_1; 1716:Src/main.c **** huart8.Init.Parity = UART_PARITY_NONE; 1717:Src/main.c **** huart8.Init.Mode = UART_MODE_TX_RX; 1718:Src/main.c **** huart8.Init.HwFlowCtl = UART_HWCONTROL_NONE; 1719:Src/main.c **** huart8.Init.OverSampling = UART_OVERSAMPLING_16; 1720:Src/main.c **** huart8.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE; 1721:Src/main.c **** huart8.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT; 1722:Src/main.c **** if (HAL_UART_Init(&huart8) != HAL_OK) 1723:Src/main.c **** { 1724:Src/main.c **** Error_Handler(); 1725:Src/main.c **** } 1726:Src/main.c **** /* USER CODE BEGIN UART8_Init 2 */ 1727:Src/main.c **** 1728:Src/main.c **** /* USER CODE END UART8_Init 2 */ 1729:Src/main.c **** 1730:Src/main.c **** } 1731:Src/main.c **** 1732:Src/main.c **** /** 1733:Src/main.c **** * @brief USART1 Initialization Function 1734:Src/main.c **** * @param None 1735:Src/main.c **** * @retval None 1736:Src/main.c **** */ 1737:Src/main.c **** static void MX_USART1_UART_Init(void) 1738:Src/main.c **** { 1739:Src/main.c **** 1740:Src/main.c **** /* USER CODE BEGIN USART1_Init 0 */ 1741:Src/main.c **** 1742:Src/main.c **** /* USER CODE END USART1_Init 0 */ 1743:Src/main.c **** 1744:Src/main.c **** LL_USART_InitTypeDef USART_InitStruct = {0}; 1745:Src/main.c **** 1746:Src/main.c **** LL_GPIO_InitTypeDef GPIO_InitStruct = {0}; 1747:Src/main.c **** RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; 1748:Src/main.c **** 1749:Src/main.c **** /** Initializes the peripherals clock 1750:Src/main.c **** */ 1751:Src/main.c **** PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USART1; 1752:Src/main.c **** PeriphClkInitStruct.Usart1ClockSelection = RCC_USART1CLKSOURCE_PCLK2; 1753:Src/main.c **** if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) 1754:Src/main.c **** { 1755:Src/main.c **** Error_Handler(); 1756:Src/main.c **** } 1757:Src/main.c **** 1758:Src/main.c **** /* Peripheral clock enable */ 1759:Src/main.c **** LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_USART1); 1760:Src/main.c **** 1761:Src/main.c **** LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_GPIOA); 1762:Src/main.c **** /**USART1 GPIO Configuration 1763:Src/main.c **** PA9 ------> USART1_TX 1764:Src/main.c **** PA10 ------> USART1_RX 1765:Src/main.c **** */ 1766:Src/main.c **** GPIO_InitStruct.Pin = LL_GPIO_PIN_9; 1767:Src/main.c **** GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE; ARM GAS /tmp/ccYgfTud.s page 71 1768:Src/main.c **** GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH; 1769:Src/main.c **** GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; 1770:Src/main.c **** GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; 1771:Src/main.c **** GPIO_InitStruct.Alternate = LL_GPIO_AF_7; 1772:Src/main.c **** LL_GPIO_Init(GPIOA, &GPIO_InitStruct); 1773:Src/main.c **** 1774:Src/main.c **** GPIO_InitStruct.Pin = LL_GPIO_PIN_10; 1775:Src/main.c **** GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE; 1776:Src/main.c **** GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH; 1777:Src/main.c **** GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; 1778:Src/main.c **** GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; 1779:Src/main.c **** GPIO_InitStruct.Alternate = LL_GPIO_AF_7; 1780:Src/main.c **** LL_GPIO_Init(GPIOA, &GPIO_InitStruct); 1781:Src/main.c **** 1782:Src/main.c **** /* USART1 DMA Init */ 1783:Src/main.c **** 1784:Src/main.c **** /* USART1_TX Init */ 1785:Src/main.c **** LL_DMA_SetChannelSelection(DMA2, LL_DMA_STREAM_7, LL_DMA_CHANNEL_4); 1786:Src/main.c **** 1787:Src/main.c **** LL_DMA_SetDataTransferDirection(DMA2, LL_DMA_STREAM_7, LL_DMA_DIRECTION_MEMORY_TO_PERIPH); 1788:Src/main.c **** 1789:Src/main.c **** LL_DMA_SetStreamPriorityLevel(DMA2, LL_DMA_STREAM_7, LL_DMA_PRIORITY_VERYHIGH); 1790:Src/main.c **** 1791:Src/main.c **** LL_DMA_SetMode(DMA2, LL_DMA_STREAM_7, LL_DMA_MODE_NORMAL); 1792:Src/main.c **** 1793:Src/main.c **** LL_DMA_SetPeriphIncMode(DMA2, LL_DMA_STREAM_7, LL_DMA_PERIPH_NOINCREMENT); 1794:Src/main.c **** 1795:Src/main.c **** LL_DMA_SetMemoryIncMode(DMA2, LL_DMA_STREAM_7, LL_DMA_MEMORY_INCREMENT); 1796:Src/main.c **** 1797:Src/main.c **** LL_DMA_SetPeriphSize(DMA2, LL_DMA_STREAM_7, LL_DMA_PDATAALIGN_BYTE); 1798:Src/main.c **** 1799:Src/main.c **** LL_DMA_SetMemorySize(DMA2, LL_DMA_STREAM_7, LL_DMA_MDATAALIGN_BYTE); 1800:Src/main.c **** 1801:Src/main.c **** LL_DMA_DisableFifoMode(DMA2, LL_DMA_STREAM_7); 1802:Src/main.c **** 1803:Src/main.c **** /* USART1 interrupt Init */ 1804:Src/main.c **** NVIC_SetPriority(USART1_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(),0, 0)); 1805:Src/main.c **** NVIC_EnableIRQ(USART1_IRQn); 1806:Src/main.c **** 1807:Src/main.c **** /* USER CODE BEGIN USART1_Init 1 */ 1808:Src/main.c **** 1809:Src/main.c **** /* USER CODE END USART1_Init 1 */ 1810:Src/main.c **** USART_InitStruct.BaudRate = 115200; 1811:Src/main.c **** USART_InitStruct.DataWidth = LL_USART_DATAWIDTH_8B; 1812:Src/main.c **** USART_InitStruct.StopBits = LL_USART_STOPBITS_1; 1813:Src/main.c **** USART_InitStruct.Parity = LL_USART_PARITY_NONE; 1814:Src/main.c **** USART_InitStruct.TransferDirection = LL_USART_DIRECTION_TX_RX; 1815:Src/main.c **** USART_InitStruct.HardwareFlowControl = LL_USART_HWCONTROL_NONE; 1816:Src/main.c **** USART_InitStruct.OverSampling = LL_USART_OVERSAMPLING_16; 1817:Src/main.c **** LL_USART_Init(USART1, &USART_InitStruct); 1818:Src/main.c **** LL_USART_ConfigAsyncMode(USART1); 1819:Src/main.c **** LL_USART_Enable(USART1); 1820:Src/main.c **** /* USER CODE BEGIN USART1_Init 2 */ 1821:Src/main.c **** 1822:Src/main.c **** /* USER CODE END USART1_Init 2 */ 1823:Src/main.c **** 1824:Src/main.c **** } ARM GAS /tmp/ccYgfTud.s page 72 1825:Src/main.c **** 1826:Src/main.c **** /** 1827:Src/main.c **** * Enable DMA controller clock 1828:Src/main.c **** */ 1829:Src/main.c **** static void MX_DMA_Init(void) 1830:Src/main.c **** { 144 .loc 1 1830 1 is_stmt 1 view -0 145 .cfi_startproc 146 @ args = 0, pretend = 0, frame = 8 147 @ frame_needed = 0, uses_anonymous_args = 0 148 0000 00B5 push {lr} 149 .LCFI1: 150 .cfi_def_cfa_offset 4 151 .cfi_offset 14, -4 152 0002 83B0 sub sp, sp, #12 153 .LCFI2: 154 .cfi_def_cfa_offset 16 1831:Src/main.c **** 1832:Src/main.c **** /* Init with LL driver */ 1833:Src/main.c **** /* DMA controller clock enable */ 1834:Src/main.c **** LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_DMA2); 155 .loc 1 1834 3 view .LVU37 156 .LVL8: 157 .LBB329: 158 .LBI329: 159 .file 3 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h" 1:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** 2:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** ****************************************************************************** 3:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @file stm32f7xx_ll_bus.h 4:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @author MCD Application Team 5:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Header file of BUS LL module. 6:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 7:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** @verbatim 8:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** ##### RCC Limitations ##### 9:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** ============================================================================== 10:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** [..] 11:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** A delay between an RCC peripheral clock enable and the effective peripheral 12:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** enabling should be taken into account in order to manage the peripheral read/write 13:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** from/to registers. 14:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (+) This delay depends on the peripheral mapping. 15:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (++) AHB & APB peripherals, 1 dummy read is necessary 16:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 17:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** [..] 18:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** Workarounds: 19:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (#) For AHB & APB peripherals, a dummy read to the peripheral register has been 20:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** inserted in each LL_{BUS}_GRP{x}_EnableClock() function. 21:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 22:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** @endverbatim 23:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** ****************************************************************************** 24:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @attention 25:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * 26:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * Copyright (c) 2017 STMicroelectronics. 27:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * All rights reserved. 28:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * 29:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * This software is licensed under terms that can be found in the LICENSE file in 30:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * the root directory of this software component. 31:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * If no LICENSE file comes with this software, it is provided AS-IS. ARM GAS /tmp/ccYgfTud.s page 73 32:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** ****************************************************************************** 33:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ 34:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 35:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Define to prevent recursive inclusion -------------------------------------*/ 36:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #ifndef __STM32F7xx_LL_BUS_H 37:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define __STM32F7xx_LL_BUS_H 38:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 39:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #ifdef __cplusplus 40:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** extern "C" { 41:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif 42:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 43:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Includes ------------------------------------------------------------------*/ 44:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #include "stm32f7xx.h" 45:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 46:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** @addtogroup STM32F7xx_LL_Driver 47:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @{ 48:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ 49:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 50:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(RCC) 51:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 52:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** @defgroup BUS_LL BUS 53:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @{ 54:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ 55:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 56:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Private types -------------------------------------------------------------*/ 57:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Private variables ---------------------------------------------------------*/ 58:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Private constants ---------------------------------------------------------*/ 59:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Private macros ------------------------------------------------------------*/ 60:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Exported types ------------------------------------------------------------*/ 61:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Exported constants --------------------------------------------------------*/ 62:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** @defgroup BUS_LL_Exported_Constants BUS Exported Constants 63:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @{ 64:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ 65:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 66:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** @defgroup BUS_LL_EC_AHB1_GRP1_PERIPH AHB1 GRP1 PERIPH 67:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @{ 68:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ 69:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_ALL 0xFFFFFFFFU 70:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_GPIOA RCC_AHB1ENR_GPIOAEN 71:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_GPIOB RCC_AHB1ENR_GPIOBEN 72:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_GPIOC RCC_AHB1ENR_GPIOCEN 73:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_GPIOD RCC_AHB1ENR_GPIODEN 74:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_GPIOE RCC_AHB1ENR_GPIOEEN 75:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_GPIOF RCC_AHB1ENR_GPIOFEN 76:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_GPIOG RCC_AHB1ENR_GPIOGEN 77:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_GPIOH RCC_AHB1ENR_GPIOHEN 78:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_GPIOI RCC_AHB1ENR_GPIOIEN 79:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(GPIOJ) 80:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_GPIOJ RCC_AHB1ENR_GPIOJEN 81:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* GPIOJ */ 82:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(GPIOK) 83:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_GPIOK RCC_AHB1ENR_GPIOKEN 84:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* GPIOK */ 85:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_CRC RCC_AHB1ENR_CRCEN 86:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_BKPSRAM RCC_AHB1ENR_BKPSRAMEN 87:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_DTCMRAM RCC_AHB1ENR_DTCMRAMEN 88:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_DMA1 RCC_AHB1ENR_DMA1EN ARM GAS /tmp/ccYgfTud.s page 74 89:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_DMA2 RCC_AHB1ENR_DMA2EN 90:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(DMA2D) 91:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_DMA2D RCC_AHB1ENR_DMA2DEN 92:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* DMA2D */ 93:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(ETH) 94:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_ETHMAC RCC_AHB1ENR_ETHMACEN 95:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_ETHMACTX RCC_AHB1ENR_ETHMACTXEN 96:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_ETHMACRX RCC_AHB1ENR_ETHMACRXEN 97:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_ETHMACPTP RCC_AHB1ENR_ETHMACPTPEN 98:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* ETH */ 99:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_OTGHS RCC_AHB1ENR_OTGHSEN 100:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_OTGHSULPI RCC_AHB1ENR_OTGHSULPIEN 101:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_AXI RCC_AHB1LPENR_AXILPEN 102:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_FLITF RCC_AHB1LPENR_FLITFLPEN 103:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_SRAM1 RCC_AHB1LPENR_SRAM1LPEN 104:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_SRAM2 RCC_AHB1LPENR_SRAM2LPEN 105:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** 106:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @} 107:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ 108:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 109:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** @defgroup BUS_LL_EC_AHB2_GRP1_PERIPH AHB2 GRP1 PERIPH 110:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @{ 111:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ 112:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB2_GRP1_PERIPH_ALL 0xFFFFFFFFU 113:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(DCMI) 114:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB2_GRP1_PERIPH_DCMI RCC_AHB2ENR_DCMIEN 115:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* DCMI */ 116:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(JPEG) 117:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB2_GRP1_PERIPH_JPEG RCC_AHB2ENR_JPEGEN 118:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* JPEG */ 119:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(CRYP) 120:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB2_GRP1_PERIPH_CRYP RCC_AHB2ENR_CRYPEN 121:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* CRYP */ 122:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(AES) 123:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB2_GRP1_PERIPH_AES RCC_AHB2ENR_AESEN 124:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* AES */ 125:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(HASH) 126:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB2_GRP1_PERIPH_HASH RCC_AHB2ENR_HASHEN 127:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* HASH */ 128:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB2_GRP1_PERIPH_RNG RCC_AHB2ENR_RNGEN 129:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB2_GRP1_PERIPH_OTGFS RCC_AHB2ENR_OTGFSEN 130:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** 131:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @} 132:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ 133:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 134:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** @defgroup BUS_LL_EC_AHB3_GRP1_PERIPH AHB3 GRP1 PERIPH 135:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @{ 136:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ 137:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB3_GRP1_PERIPH_ALL 0xFFFFFFFFU 138:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB3_GRP1_PERIPH_FMC RCC_AHB3ENR_FMCEN 139:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB3_GRP1_PERIPH_QSPI RCC_AHB3ENR_QSPIEN 140:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** 141:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @} 142:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ 143:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 144:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** @defgroup BUS_LL_EC_APB1_GRP1_PERIPH APB1 GRP1 PERIPH 145:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @{ ARM GAS /tmp/ccYgfTud.s page 75 146:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ 147:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_ALL 0xFFFFFFFFU 148:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_TIM2 RCC_APB1ENR_TIM2EN 149:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_TIM3 RCC_APB1ENR_TIM3EN 150:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_TIM4 RCC_APB1ENR_TIM4EN 151:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_TIM5 RCC_APB1ENR_TIM5EN 152:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_TIM6 RCC_APB1ENR_TIM6EN 153:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_TIM7 RCC_APB1ENR_TIM7EN 154:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_TIM12 RCC_APB1ENR_TIM12EN 155:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_TIM13 RCC_APB1ENR_TIM13EN 156:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_TIM14 RCC_APB1ENR_TIM14EN 157:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_LPTIM1 RCC_APB1ENR_LPTIM1EN 158:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_WWDG RCC_APB1ENR_WWDGEN 159:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_SPI2 RCC_APB1ENR_SPI2EN 160:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_SPI3 RCC_APB1ENR_SPI3EN 161:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(SPDIFRX) 162:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_SPDIFRX RCC_APB1ENR_SPDIFRXEN 163:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* SPDIFRX */ 164:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_USART2 RCC_APB1ENR_USART2EN 165:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_USART3 RCC_APB1ENR_USART3EN 166:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_UART4 RCC_APB1ENR_UART4EN 167:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_UART5 RCC_APB1ENR_UART5EN 168:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_I2C1 RCC_APB1ENR_I2C1EN 169:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_I2C2 RCC_APB1ENR_I2C2EN 170:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_I2C3 RCC_APB1ENR_I2C3EN 171:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(I2C4) 172:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_I2C4 RCC_APB1ENR_I2C4EN 173:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* I2C4 */ 174:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_CAN1 RCC_APB1ENR_CAN1EN 175:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(CAN2) 176:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_CAN2 RCC_APB1ENR_CAN2EN 177:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* CAN2 */ 178:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(CAN3) 179:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_CAN3 RCC_APB1ENR_CAN3EN 180:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* CAN3 */ 181:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(CEC) 182:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_CEC RCC_APB1ENR_CECEN 183:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* CEC */ 184:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_PWR RCC_APB1ENR_PWREN 185:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_DAC1 RCC_APB1ENR_DACEN 186:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_UART7 RCC_APB1ENR_UART7EN 187:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_UART8 RCC_APB1ENR_UART8EN 188:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(RCC_APB1ENR_RTCEN) 189:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_RTCAPB RCC_APB1ENR_RTCEN 190:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* RCC_APB1ENR_RTCEN */ 191:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** 192:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @} 193:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ 194:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 195:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** @defgroup BUS_LL_EC_APB2_GRP1_PERIPH APB2 GRP1 PERIPH 196:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @{ 197:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ 198:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_ALL 0xFFFFFFFFU 199:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_TIM1 RCC_APB2ENR_TIM1EN 200:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_TIM8 RCC_APB2ENR_TIM8EN 201:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_USART1 RCC_APB2ENR_USART1EN 202:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_USART6 RCC_APB2ENR_USART6EN ARM GAS /tmp/ccYgfTud.s page 76 203:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_ADC1 RCC_APB2ENR_ADC1EN 204:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_ADC2 RCC_APB2ENR_ADC2EN 205:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_ADC3 RCC_APB2ENR_ADC3EN 206:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_SDMMC1 RCC_APB2ENR_SDMMC1EN 207:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(SDMMC2) 208:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_SDMMC2 RCC_APB2ENR_SDMMC2EN 209:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* SDMMC2 */ 210:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_SPI1 RCC_APB2ENR_SPI1EN 211:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_SPI4 RCC_APB2ENR_SPI4EN 212:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_SYSCFG RCC_APB2ENR_SYSCFGEN 213:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_TIM9 RCC_APB2ENR_TIM9EN 214:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_TIM10 RCC_APB2ENR_TIM10EN 215:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_TIM11 RCC_APB2ENR_TIM11EN 216:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_SPI5 RCC_APB2ENR_SPI5EN 217:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(SPI6) 218:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_SPI6 RCC_APB2ENR_SPI6EN 219:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* SPI6 */ 220:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_SAI1 RCC_APB2ENR_SAI1EN 221:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_SAI2 RCC_APB2ENR_SAI2EN 222:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(LTDC) 223:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_LTDC RCC_APB2ENR_LTDCEN 224:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* LTDC */ 225:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(DSI) 226:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_DSI RCC_APB2ENR_DSIEN 227:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* DSI */ 228:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(DFSDM1_Channel0) 229:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_DFSDM1 RCC_APB2ENR_DFSDM1EN 230:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* DFSDM1_Channel0 */ 231:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(MDIOS) 232:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_MDIO RCC_APB2ENR_MDIOEN 233:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* MDIOS */ 234:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(USB_HS_PHYC) 235:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_OTGPHYC RCC_APB2ENR_OTGPHYCEN 236:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* USB_HS_PHYC */ 237:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_ADC RCC_APB2RSTR_ADCRST 238:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** 239:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @} 240:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ 241:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 242:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** 243:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @} 244:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ 245:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 246:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Exported macro ------------------------------------------------------------*/ 247:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Exported functions --------------------------------------------------------*/ 248:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** @defgroup BUS_LL_Exported_Functions BUS Exported Functions 249:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @{ 250:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ 251:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 252:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** @defgroup BUS_LL_EF_AHB1 AHB1 253:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @{ 254:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ 255:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 256:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** 257:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Enable AHB1 peripherals clock. 258:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll AHB1ENR GPIOAEN LL_AHB1_GRP1_EnableClock\n 259:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOBEN LL_AHB1_GRP1_EnableClock\n ARM GAS /tmp/ccYgfTud.s page 77 260:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOCEN LL_AHB1_GRP1_EnableClock\n 261:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIODEN LL_AHB1_GRP1_EnableClock\n 262:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOEEN LL_AHB1_GRP1_EnableClock\n 263:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOFEN LL_AHB1_GRP1_EnableClock\n 264:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOGEN LL_AHB1_GRP1_EnableClock\n 265:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOHEN LL_AHB1_GRP1_EnableClock\n 266:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOIEN LL_AHB1_GRP1_EnableClock\n 267:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOJEN LL_AHB1_GRP1_EnableClock\n 268:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOKEN LL_AHB1_GRP1_EnableClock\n 269:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR CRCEN LL_AHB1_GRP1_EnableClock\n 270:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR BKPSRAMEN LL_AHB1_GRP1_EnableClock\n 271:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR DTCMRAMEN LL_AHB1_GRP1_EnableClock\n 272:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR DMA1EN LL_AHB1_GRP1_EnableClock\n 273:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR DMA2EN LL_AHB1_GRP1_EnableClock\n 274:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR DMA2DEN LL_AHB1_GRP1_EnableClock\n 275:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR ETHMACEN LL_AHB1_GRP1_EnableClock\n 276:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR ETHMACTXEN LL_AHB1_GRP1_EnableClock\n 277:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR ETHMACRXEN LL_AHB1_GRP1_EnableClock\n 278:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR ETHMACPTPEN LL_AHB1_GRP1_EnableClock\n 279:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR OTGHSEN LL_AHB1_GRP1_EnableClock\n 280:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR OTGHSULPIEN LL_AHB1_GRP1_EnableClock 281:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: 282:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA 283:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB 284:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC 285:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD 286:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE 287:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF 288:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG 289:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH 290:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI 291:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*) 292:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*) 293:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRC 294:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM 295:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DTCMRAM 296:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 298:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*) 299:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*) 300:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*) 301:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*) 302:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACPTP (*) 303:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS 304:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHSULPI 305:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * 306:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. 307:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval None 308:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ 309:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs) 160 .loc 3 309 22 view .LVU38 161 .LBB330: 310:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { 311:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __IO uint32_t tmpreg; 162 .loc 3 311 3 view .LVU39 312:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** SET_BIT(RCC->AHB1ENR, Periphs); 163 .loc 3 312 3 view .LVU40 ARM GAS /tmp/ccYgfTud.s page 78 164 0004 0D4B ldr r3, .L10 165 0006 1A6B ldr r2, [r3, #48] 166 0008 42F48002 orr r2, r2, #4194304 167 000c 1A63 str r2, [r3, #48] 313:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Delay after an RCC peripheral clock enabling */ 314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** tmpreg = READ_BIT(RCC->AHB1ENR, Periphs); 168 .loc 3 314 3 view .LVU41 169 .loc 3 314 12 is_stmt 0 view .LVU42 170 000e 1B6B ldr r3, [r3, #48] 171 0010 03F48003 and r3, r3, #4194304 172 .loc 3 314 10 view .LVU43 173 0014 0193 str r3, [sp, #4] 315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; 174 .loc 3 315 3 is_stmt 1 view .LVU44 175 0016 019B ldr r3, [sp, #4] 176 .LVL9: 177 .loc 3 315 3 is_stmt 0 view .LVU45 178 .LBE330: 179 .LBE329: 1835:Src/main.c **** 1836:Src/main.c **** /* DMA interrupt init */ 1837:Src/main.c **** /* DMA2_Stream7_IRQn interrupt configuration */ 1838:Src/main.c **** NVIC_SetPriority(DMA2_Stream7_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(),0, 0)); 180 .loc 1 1838 3 is_stmt 1 view .LVU46 181 .LBB331: 182 .LBI331: 1884:Drivers/CMSIS/Include/core_cm7.h **** { 183 .loc 2 1884 26 view .LVU47 184 .LBB332: 1886:Drivers/CMSIS/Include/core_cm7.h **** } 185 .loc 2 1886 3 view .LVU48 1886:Drivers/CMSIS/Include/core_cm7.h **** } 186 .loc 2 1886 26 is_stmt 0 view .LVU49 187 0018 094B ldr r3, .L10+4 188 001a D868 ldr r0, [r3, #12] 189 .LBE332: 190 .LBE331: 191 .loc 1 1838 3 discriminator 1 view .LVU50 192 001c 0022 movs r2, #0 193 001e 1146 mov r1, r2 194 0020 C0F30220 ubfx r0, r0, #8, #3 195 0024 FFF7FEFF bl NVIC_EncodePriority 196 .LVL10: 197 .LBB333: 198 .LBI333: 2024:Drivers/CMSIS/Include/core_cm7.h **** { 199 .loc 2 2024 22 is_stmt 1 view .LVU51 200 .LBB334: 2026:Drivers/CMSIS/Include/core_cm7.h **** { 201 .loc 2 2026 3 view .LVU52 2028:Drivers/CMSIS/Include/core_cm7.h **** } 202 .loc 2 2028 5 view .LVU53 2028:Drivers/CMSIS/Include/core_cm7.h **** } 203 .loc 2 2028 49 is_stmt 0 view .LVU54 204 0028 0001 lsls r0, r0, #4 205 .LVL11: 2028:Drivers/CMSIS/Include/core_cm7.h **** } ARM GAS /tmp/ccYgfTud.s page 79 206 .loc 2 2028 49 view .LVU55 207 002a C0B2 uxtb r0, r0 2028:Drivers/CMSIS/Include/core_cm7.h **** } 208 .loc 2 2028 47 view .LVU56 209 002c 054B ldr r3, .L10+8 210 002e 83F84603 strb r0, [r3, #838] 211 .LVL12: 2028:Drivers/CMSIS/Include/core_cm7.h **** } 212 .loc 2 2028 47 view .LVU57 213 .LBE334: 214 .LBE333: 1839:Src/main.c **** NVIC_EnableIRQ(DMA2_Stream7_IRQn); 215 .loc 1 1839 3 is_stmt 1 view .LVU58 216 .LBB335: 217 .LBI335: 1896:Drivers/CMSIS/Include/core_cm7.h **** { 218 .loc 2 1896 22 view .LVU59 219 .LBB336: 1898:Drivers/CMSIS/Include/core_cm7.h **** { 220 .loc 2 1898 3 view .LVU60 1900:Drivers/CMSIS/Include/core_cm7.h **** } 221 .loc 2 1900 5 view .LVU61 1900:Drivers/CMSIS/Include/core_cm7.h **** } 222 .loc 2 1900 43 is_stmt 0 view .LVU62 223 0032 4022 movs r2, #64 224 0034 9A60 str r2, [r3, #8] 225 .LVL13: 1900:Drivers/CMSIS/Include/core_cm7.h **** } 226 .loc 2 1900 43 view .LVU63 227 .LBE336: 228 .LBE335: 1840:Src/main.c **** 1841:Src/main.c **** } 229 .loc 1 1841 1 view .LVU64 230 0036 03B0 add sp, sp, #12 231 .LCFI3: 232 .cfi_def_cfa_offset 4 233 @ sp needed 234 0038 5DF804FB ldr pc, [sp], #4 235 .L11: 236 .align 2 237 .L10: 238 003c 00380240 .word 1073887232 239 0040 00ED00E0 .word -536810240 240 0044 00E100E0 .word -536813312 241 .cfi_endproc 242 .LFE1205: 244 .section .text.Decode_task,"ax",%progbits 245 .align 1 246 .syntax unified 247 .thumb 248 .thumb_func 250 Decode_task: 251 .LVL14: 252 .LFB1209: 1842:Src/main.c **** 1843:Src/main.c **** /** ARM GAS /tmp/ccYgfTud.s page 80 1844:Src/main.c **** * @brief GPIO Initialization Function 1845:Src/main.c **** * @param None 1846:Src/main.c **** * @retval None 1847:Src/main.c **** */ 1848:Src/main.c **** static void MX_GPIO_Init(void) 1849:Src/main.c **** { 1850:Src/main.c **** GPIO_InitTypeDef GPIO_InitStruct = {0}; 1851:Src/main.c **** /* USER CODE BEGIN MX_GPIO_Init_1 */ 1852:Src/main.c **** /* USER CODE END MX_GPIO_Init_1 */ 1853:Src/main.c **** 1854:Src/main.c **** /* GPIO Ports Clock Enable */ 1855:Src/main.c **** __HAL_RCC_GPIOF_CLK_ENABLE(); 1856:Src/main.c **** __HAL_RCC_GPIOH_CLK_ENABLE(); 1857:Src/main.c **** __HAL_RCC_GPIOC_CLK_ENABLE(); 1858:Src/main.c **** __HAL_RCC_GPIOA_CLK_ENABLE(); 1859:Src/main.c **** __HAL_RCC_GPIOB_CLK_ENABLE(); 1860:Src/main.c **** __HAL_RCC_GPIOE_CLK_ENABLE(); 1861:Src/main.c **** __HAL_RCC_GPIOD_CLK_ENABLE(); 1862:Src/main.c **** __HAL_RCC_GPIOG_CLK_ENABLE(); 1863:Src/main.c **** 1864:Src/main.c **** /*Configure GPIO pin Output Level */ 1865:Src/main.c **** HAL_GPIO_WritePin(GPIOF, ADC_MPD2_CS_Pin|SPI5_CNV_Pin|ADC_ThrLD2_CS_Pin, GPIO_PIN_RESET); 1866:Src/main.c **** 1867:Src/main.c **** /*Configure GPIO pin Output Level */ 1868:Src/main.c **** HAL_GPIO_WritePin(GPIOC, EN_5V2_Pin|EN_5V1_Pin|LD2_EN_Pin|TEC2_PD_Pin, GPIO_PIN_RESET); 1869:Src/main.c **** HAL_GPIO_WritePin(AD9102_RESET_GPIO_Port, AD9102_RESET_Pin, GPIO_PIN_SET); 1870:Src/main.c **** 1871:Src/main.c **** /*Configure GPIO pin Output Level */ 1872:Src/main.c **** HAL_GPIO_WritePin(GPIOA, TECEN1_Pin|TECEN2_Pin|REF2_ON_Pin|DAC_LD2_CS_Pin, GPIO_PIN_RESET); 1873:Src/main.c **** 1874:Src/main.c **** /*Configure GPIO pin Output Level */ 1875:Src/main.c **** HAL_GPIO_WritePin(DAC_TEC2_CS_GPIO_Port, DAC_TEC2_CS_Pin, GPIO_PIN_SET); 1876:Src/main.c **** 1877:Src/main.c **** /*Configure GPIO pin Output Level */ 1878:Src/main.c **** HAL_GPIO_WritePin(GPIOE, ADC_MPD1_CS_Pin|ADC_ThrLD1_CS_Pin, GPIO_PIN_RESET); 1879:Src/main.c **** 1880:Src/main.c **** /*Configure GPIO pin Output Level */ 1881:Src/main.c **** HAL_GPIO_WritePin(SPI4_CNV_GPIO_Port, SPI4_CNV_Pin, GPIO_PIN_SET); 1882:Src/main.c **** 1883:Src/main.c **** /*Configure GPIO pin Output Level */ 1884:Src/main.c **** HAL_GPIO_WritePin(GPIOB, REF0_EN_Pin|TEC1_PD_Pin|OUT_6_Pin 1885:Src/main.c **** |OUT_7_Pin|OUT_8_Pin|OUT_9_Pin, GPIO_PIN_RESET); 1886:Src/main.c **** 1887:Src/main.c **** /*Configure GPIO pin Output Level */ 1888:Src/main.c **** HAL_GPIO_WritePin(DAC_TEC1_CS_GPIO_Port, DAC_TEC1_CS_Pin, GPIO_PIN_SET); 1889:Src/main.c **** 1890:Src/main.c **** /*Configure GPIO pin Output Level */ 1891:Src/main.c **** HAL_GPIO_WritePin(GPIOD, LD1_EN_Pin|TEST_01_Pin|GPIO_PIN_7, GPIO_PIN_RESET); 1892:Src/main.c **** HAL_GPIO_WritePin(AD9102_TRIG_GPIO_Port, AD9102_TRIG_Pin, GPIO_PIN_SET); 1893:Src/main.c **** 1894:Src/main.c **** /*Configure GPIO pin Output Level */ 1895:Src/main.c **** HAL_GPIO_WritePin(GPIOG, GPIO_PIN_9|OUT_0_Pin|OUT_1_Pin|OUT_2_Pin 1896:Src/main.c **** |OUT_3_Pin|OUT_4_Pin|OUT_5_Pin, GPIO_PIN_RESET); 1897:Src/main.c **** 1898:Src/main.c **** /*Configure GPIO pins : INP_0_Pin INP_1_Pin */ 1899:Src/main.c **** GPIO_InitStruct.Pin = INP_0_Pin|INP_1_Pin; 1900:Src/main.c **** GPIO_InitStruct.Mode = GPIO_MODE_INPUT; ARM GAS /tmp/ccYgfTud.s page 81 1901:Src/main.c **** GPIO_InitStruct.Pull = GPIO_PULLUP; 1902:Src/main.c **** HAL_GPIO_Init(GPIOF, &GPIO_InitStruct); 1903:Src/main.c **** 1904:Src/main.c **** /*Configure GPIO pins : ADC_MPD2_CS_Pin SPI5_CNV_Pin ADC_ThrLD2_CS_Pin */ 1905:Src/main.c **** GPIO_InitStruct.Pin = ADC_MPD2_CS_Pin|SPI5_CNV_Pin|ADC_ThrLD2_CS_Pin; 1906:Src/main.c **** GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 1907:Src/main.c **** GPIO_InitStruct.Pull = GPIO_NOPULL; 1908:Src/main.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 1909:Src/main.c **** HAL_GPIO_Init(GPIOF, &GPIO_InitStruct); 1910:Src/main.c **** 1911:Src/main.c **** /*Configure GPIO pins : EN_5V2_Pin LD2_EN_Pin TEC2_PD_Pin AD9102_RESET_Pin */ 1912:Src/main.c **** GPIO_InitStruct.Pin = EN_5V2_Pin|LD2_EN_Pin|TEC2_PD_Pin|AD9102_RESET_Pin; 1913:Src/main.c **** GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 1914:Src/main.c **** GPIO_InitStruct.Pull = GPIO_NOPULL; 1915:Src/main.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 1916:Src/main.c **** HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); 1917:Src/main.c **** 1918:Src/main.c **** /*Configure GPIO pin : EN_5V1_Pin */ 1919:Src/main.c **** GPIO_InitStruct.Pin = EN_5V1_Pin; 1920:Src/main.c **** GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 1921:Src/main.c **** GPIO_InitStruct.Pull = GPIO_NOPULL; 1922:Src/main.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; 1923:Src/main.c **** HAL_GPIO_Init(EN_5V1_GPIO_Port, &GPIO_InitStruct); 1924:Src/main.c **** 1925:Src/main.c **** /*Configure GPIO pins : TECEN1_Pin TECEN2_Pin REF2_ON_Pin DAC_TEC2_CS_Pin 1926:Src/main.c **** DAC_LD2_CS_Pin */ 1927:Src/main.c **** GPIO_InitStruct.Pin = TECEN1_Pin|TECEN2_Pin|REF2_ON_Pin|DAC_TEC2_CS_Pin 1928:Src/main.c **** |DAC_LD2_CS_Pin; 1929:Src/main.c **** GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 1930:Src/main.c **** GPIO_InitStruct.Pull = GPIO_NOPULL; 1931:Src/main.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 1932:Src/main.c **** HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 1933:Src/main.c **** 1934:Src/main.c **** /*Configure GPIO pins : TEC2_FLAG1_Pin TEC2_FLAG2_Pin TEC1_FLAG1_Pin TEC1_FLAG2_Pin */ 1935:Src/main.c **** GPIO_InitStruct.Pin = TEC2_FLAG1_Pin|TEC2_FLAG2_Pin|TEC1_FLAG1_Pin|TEC1_FLAG2_Pin; 1936:Src/main.c **** GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 1937:Src/main.c **** GPIO_InitStruct.Pull = GPIO_NOPULL; 1938:Src/main.c **** HAL_GPIO_Init(GPIOF, &GPIO_InitStruct); 1939:Src/main.c **** 1940:Src/main.c **** /*Configure GPIO pins : ADC_MPD1_CS_Pin ADC_ThrLD1_CS_Pin */ 1941:Src/main.c **** GPIO_InitStruct.Pin = ADC_MPD1_CS_Pin|ADC_ThrLD1_CS_Pin; 1942:Src/main.c **** GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 1943:Src/main.c **** GPIO_InitStruct.Pull = GPIO_NOPULL; 1944:Src/main.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 1945:Src/main.c **** HAL_GPIO_Init(GPIOE, &GPIO_InitStruct); 1946:Src/main.c **** 1947:Src/main.c **** /*Configure GPIO pin : SPI4_CNV_Pin */ 1948:Src/main.c **** GPIO_InitStruct.Pin = SPI4_CNV_Pin; 1949:Src/main.c **** GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 1950:Src/main.c **** GPIO_InitStruct.Pull = GPIO_NOPULL; 1951:Src/main.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; 1952:Src/main.c **** HAL_GPIO_Init(SPI4_CNV_GPIO_Port, &GPIO_InitStruct); 1953:Src/main.c **** 1954:Src/main.c **** /*Configure GPIO pins : REF0_EN_Pin TEC1_PD_Pin DAC_TEC1_CS_Pin 1955:Src/main.c **** OUT_6_Pin OUT_7_Pin OUT_8_Pin OUT_9_Pin */ 1956:Src/main.c **** GPIO_InitStruct.Pin = REF0_EN_Pin|TEC1_PD_Pin|DAC_TEC1_CS_Pin 1957:Src/main.c **** |OUT_6_Pin|OUT_7_Pin|OUT_8_Pin|OUT_9_Pin; ARM GAS /tmp/ccYgfTud.s page 82 1958:Src/main.c **** GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 1959:Src/main.c **** GPIO_InitStruct.Pull = GPIO_NOPULL; 1960:Src/main.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 1961:Src/main.c **** HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 1962:Src/main.c **** 1963:Src/main.c **** /*Configure GPIO pins : LD1_EN_Pin TEST_01_Pin PD7 AD9102_TRIG_Pin */ 1964:Src/main.c **** GPIO_InitStruct.Pin = LD1_EN_Pin|TEST_01_Pin|GPIO_PIN_7|AD9102_TRIG_Pin; 1965:Src/main.c **** GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 1966:Src/main.c **** GPIO_InitStruct.Pull = GPIO_NOPULL; 1967:Src/main.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 1968:Src/main.c **** HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); 1969:Src/main.c **** 1970:Src/main.c **** /*Configure GPIO pin : USB_FLAG_Pin */ 1971:Src/main.c **** GPIO_InitStruct.Pin = USB_FLAG_Pin; 1972:Src/main.c **** GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 1973:Src/main.c **** GPIO_InitStruct.Pull = GPIO_NOPULL; 1974:Src/main.c **** HAL_GPIO_Init(USB_FLAG_GPIO_Port, &GPIO_InitStruct); 1975:Src/main.c **** 1976:Src/main.c **** /*Configure GPIO pin : SDMMC1_EN_Pin */ 1977:Src/main.c **** GPIO_InitStruct.Pin = SDMMC1_EN_Pin; 1978:Src/main.c **** GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 1979:Src/main.c **** GPIO_InitStruct.Pull = GPIO_NOPULL; 1980:Src/main.c **** HAL_GPIO_Init(SDMMC1_EN_GPIO_Port, &GPIO_InitStruct); 1981:Src/main.c **** 1982:Src/main.c **** /*Configure GPIO pins : PG9 OUT_0_Pin OUT_1_Pin OUT_2_Pin 1983:Src/main.c **** OUT_3_Pin OUT_4_Pin OUT_5_Pin */ 1984:Src/main.c **** GPIO_InitStruct.Pin = GPIO_PIN_9|OUT_0_Pin|OUT_1_Pin|OUT_2_Pin 1985:Src/main.c **** |OUT_3_Pin|OUT_4_Pin|OUT_5_Pin; 1986:Src/main.c **** GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 1987:Src/main.c **** GPIO_InitStruct.Pull = GPIO_NOPULL; 1988:Src/main.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 1989:Src/main.c **** HAL_GPIO_Init(GPIOG, &GPIO_InitStruct); 1990:Src/main.c **** 1991:Src/main.c **** /* USER CODE BEGIN MX_GPIO_Init_2 */ 1992:Src/main.c **** /* USER CODE END MX_GPIO_Init_2 */ 1993:Src/main.c **** } 1994:Src/main.c **** 1995:Src/main.c **** /* USER CODE BEGIN 4 */ 1996:Src/main.c **** 1997:Src/main.c **** //void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart) { 1998:Src/main.c **** 1999:Src/main.c **** // UART_transmission_request = NO_MESS; 2000:Src/main.c **** 2001:Src/main.c **** //} 2002:Src/main.c **** 2003:Src/main.c **** static void Init_params(void) 2004:Src/main.c **** { 2005:Src/main.c **** TO6 = 0; 2006:Src/main.c **** TO7 = 0; 2007:Src/main.c **** TO7_before = 0; 2008:Src/main.c **** TO6_before = 0; 2009:Src/main.c **** TO6_uart = 0; 2010:Src/main.c **** flg_tmt = 0; 2011:Src/main.c **** UART_rec_incr = 0; 2012:Src/main.c **** fgoto = 0; 2013:Src/main.c **** sizeoffile = 0; 2014:Src/main.c **** u_tx_flg = 0; ARM GAS /tmp/ccYgfTud.s page 83 2015:Src/main.c **** u_rx_flg = 0; 2016:Src/main.c **** //State_Data[0]=0; 2017:Src/main.c **** //State_Data[1]=0;//All OK! 2018:Src/main.c **** for (uint16_t i=0; iWORK_EN = ((uint8_t)((*temp2)>>0))&0x01; 2172:Src/main.c **** Curr_setup->U5V1_EN = ((uint8_t)((*temp2)>>1))&0x01; 2173:Src/main.c **** Curr_setup->U5V2_EN = ((uint8_t)((*temp2)>>2))&0x01; 2174:Src/main.c **** Curr_setup->LD1_EN = ((uint8_t)((*temp2)>>3))&0x01; 2175:Src/main.c **** Curr_setup->LD2_EN = ((uint8_t)((*temp2)>>4))&0x01; 2176:Src/main.c **** Curr_setup->REF1_EN = ((uint8_t)((*temp2)>>5))&0x01; 2177:Src/main.c **** Curr_setup->REF2_EN = ((uint8_t)((*temp2)>>6))&0x01; 2178:Src/main.c **** Curr_setup->TEC1_EN = ((uint8_t)((*temp2)>>7))&0x01; 2179:Src/main.c **** Curr_setup->TEC2_EN = ((uint8_t)((*temp2)>>8))&0x01; 2180:Src/main.c **** Curr_setup->TS1_EN = ((uint8_t)((*temp2)>>9))&0x01; 2181:Src/main.c **** Curr_setup->TS2_EN = ((uint8_t)((*temp2)>>10))&0x01; 2182:Src/main.c **** Curr_setup->SD_EN = ((uint8_t)((*temp2)>>11))&0x01; 2183:Src/main.c **** Curr_setup->PI1_RD = ((uint8_t)((*temp2)>>12))&0x01; 2184:Src/main.c **** Curr_setup->PI2_RD = ((uint8_t)((*temp2)>>13))&0x01; 2185:Src/main.c **** ARM GAS /tmp/ccYgfTud.s page 86 2186:Src/main.c **** temp2++; 2187:Src/main.c **** LD1_curr_setup->LD_TEMP = (uint16_t)(*temp2); 2188:Src/main.c **** temp2++; 2189:Src/main.c **** LD2_curr_setup->LD_TEMP = (uint16_t)(*temp2); 2190:Src/main.c **** temp2++; 2191:Src/main.c **** temp2++; 2192:Src/main.c **** temp2++; 2193:Src/main.c **** Curr_setup->AVERAGES = (uint16_t)(*temp2); 2194:Src/main.c **** temp2++; 2195:Src/main.c **** LD1_curr_setup->P_coef_temp = (float)((uint16_t)(*temp2))/((float)(256));//(float)(1/(float)((uint 2196:Src/main.c **** temp2++; 2197:Src/main.c **** LD1_curr_setup->I_coef_temp = (float)((uint16_t)(*temp2))/((float)(256));//(float)(1/(float)((uint 2198:Src/main.c **** temp2++; 2199:Src/main.c **** LD2_curr_setup->P_coef_temp = (float)((uint16_t)(*temp2))/((float)(256));//(float)(1/(float)((uint 2200:Src/main.c **** temp2++; 2201:Src/main.c **** LD2_curr_setup->I_coef_temp = (float)((uint16_t)(*temp2))/((float)(256));//(float)(1/(float)((uint 2202:Src/main.c **** temp2++; 2203:Src/main.c **** Long_Data[13] = (uint16_t)(*temp2);//Message ID 2204:Src/main.c **** temp2++; 2205:Src/main.c **** LD1_curr_setup->CURRENT = (uint16_t)(*temp2); 2206:Src/main.c **** temp2++; 2207:Src/main.c **** LD2_curr_setup->CURRENT = (uint16_t)(*temp2); 2208:Src/main.c **** temp2++; 2209:Src/main.c **** 2210:Src/main.c **** if (Curr_setup->U5V1_EN) 2211:Src/main.c **** { 2212:Src/main.c **** HAL_GPIO_WritePin(EN_5V1_GPIO_Port, EN_5V1_Pin, GPIO_PIN_SET); 2213:Src/main.c **** } 2214:Src/main.c **** else 2215:Src/main.c **** { 2216:Src/main.c **** HAL_GPIO_WritePin(EN_5V1_GPIO_Port, EN_5V1_Pin, GPIO_PIN_RESET); 2217:Src/main.c **** } 2218:Src/main.c **** 2219:Src/main.c **** if (Curr_setup->U5V2_EN) 2220:Src/main.c **** { 2221:Src/main.c **** HAL_GPIO_WritePin(EN_5V2_GPIO_Port, EN_5V2_Pin, GPIO_PIN_SET); 2222:Src/main.c **** } 2223:Src/main.c **** else 2224:Src/main.c **** { 2225:Src/main.c **** HAL_GPIO_WritePin(EN_5V2_GPIO_Port, EN_5V2_Pin, GPIO_PIN_RESET); 2226:Src/main.c **** } 2227:Src/main.c **** 2228:Src/main.c **** if (Curr_setup->LD1_EN) 2229:Src/main.c **** { 2230:Src/main.c **** HAL_GPIO_WritePin(LD1_EN_GPIO_Port, LD1_EN_Pin, GPIO_PIN_SET); 2231:Src/main.c **** //LL_SPI_Enable(SPI2);//Enable SPI for Laser1 DAC 2232:Src/main.c **** } 2233:Src/main.c **** else 2234:Src/main.c **** { 2235:Src/main.c **** HAL_GPIO_WritePin(LD1_EN_GPIO_Port, LD1_EN_Pin, GPIO_PIN_RESET); 2236:Src/main.c **** //LL_SPI_Disable(SPI2);//Disable SPI for Laser1 DAC 2237:Src/main.c **** } 2238:Src/main.c **** 2239:Src/main.c **** if (Curr_setup->LD2_EN) 2240:Src/main.c **** { 2241:Src/main.c **** HAL_GPIO_WritePin(LD2_EN_GPIO_Port, LD2_EN_Pin, GPIO_PIN_SET); 2242:Src/main.c **** //LL_SPI_Enable(SPI6);//Enable SPI for Laser2 DAC ARM GAS /tmp/ccYgfTud.s page 87 2243:Src/main.c **** } 2244:Src/main.c **** else 2245:Src/main.c **** { 2246:Src/main.c **** HAL_GPIO_WritePin(LD2_EN_GPIO_Port, LD2_EN_Pin, GPIO_PIN_RESET); 2247:Src/main.c **** //LL_SPI_Disable(SPI6);//Disable SPI for Laser2 DAC 2248:Src/main.c **** } 2249:Src/main.c **** 2250:Src/main.c **** if (Curr_setup->REF1_EN) 2251:Src/main.c **** { 2252:Src/main.c **** HAL_GPIO_WritePin(REF0_EN_GPIO_Port, REF0_EN_Pin, GPIO_PIN_SET); 2253:Src/main.c **** } 2254:Src/main.c **** else 2255:Src/main.c **** { 2256:Src/main.c **** HAL_GPIO_WritePin(REF0_EN_GPIO_Port, REF0_EN_Pin, GPIO_PIN_RESET); 2257:Src/main.c **** } 2258:Src/main.c **** 2259:Src/main.c **** if (Curr_setup->REF2_EN) 2260:Src/main.c **** { 2261:Src/main.c **** HAL_GPIO_WritePin(REF2_ON_GPIO_Port, REF2_ON_Pin, GPIO_PIN_SET); 2262:Src/main.c **** } 2263:Src/main.c **** else 2264:Src/main.c **** { 2265:Src/main.c **** HAL_GPIO_WritePin(REF2_ON_GPIO_Port, REF2_ON_Pin, GPIO_PIN_RESET); 2266:Src/main.c **** } 2267:Src/main.c **** 2268:Src/main.c **** if ((Curr_setup->TS1_EN)&&(Curr_setup->TEC1_EN)) 2269:Src/main.c **** { 2270:Src/main.c **** Set_LTEC(3,32767); 2271:Src/main.c **** Set_LTEC(3,32767); 2272:Src/main.c **** HAL_GPIO_WritePin(TEC1_PD_GPIO_Port, TEC1_PD_Pin, GPIO_PIN_SET); 2273:Src/main.c **** HAL_GPIO_WritePin(TECEN1_GPIO_Port, TECEN1_Pin, GPIO_PIN_SET); 2274:Src/main.c **** } 2275:Src/main.c **** else 2276:Src/main.c **** { 2277:Src/main.c **** HAL_GPIO_WritePin(TECEN1_GPIO_Port, TECEN1_Pin, GPIO_PIN_RESET); 2278:Src/main.c **** HAL_GPIO_WritePin(TEC1_PD_GPIO_Port, TEC1_PD_Pin, GPIO_PIN_RESET); 2279:Src/main.c **** } 2280:Src/main.c **** 2281:Src/main.c **** if ((Curr_setup->TS2_EN)&&(Curr_setup->TEC2_EN)) 2282:Src/main.c **** { 2283:Src/main.c **** Set_LTEC(4,32767); 2284:Src/main.c **** Set_LTEC(4,32767); 2285:Src/main.c **** HAL_GPIO_WritePin(TEC2_PD_GPIO_Port, TEC2_PD_Pin, GPIO_PIN_SET); 2286:Src/main.c **** HAL_GPIO_WritePin(TECEN2_GPIO_Port, TECEN2_Pin, GPIO_PIN_SET); 2287:Src/main.c **** } 2288:Src/main.c **** else 2289:Src/main.c **** { 2290:Src/main.c **** HAL_GPIO_WritePin(TECEN2_GPIO_Port, TECEN2_Pin, GPIO_PIN_RESET); 2291:Src/main.c **** HAL_GPIO_WritePin(TEC2_PD_GPIO_Port, TEC2_PD_Pin, GPIO_PIN_RESET); 2292:Src/main.c **** } 2293:Src/main.c **** 2294:Src/main.c **** if (Curr_setup->PI1_RD==0) 2295:Src/main.c **** { 2296:Src/main.c **** LD1_curr_setup->P_coef_temp = 10; 2297:Src/main.c **** LD1_curr_setup->I_coef_temp = 0.01; 2298:Src/main.c **** } 2299:Src/main.c **** ARM GAS /tmp/ccYgfTud.s page 88 2300:Src/main.c **** if (Curr_setup->PI2_RD==0) 2301:Src/main.c **** { 2302:Src/main.c **** LD2_curr_setup->P_coef_temp = 10; 2303:Src/main.c **** LD2_curr_setup->I_coef_temp = 0.01; 2304:Src/main.c **** } 2305:Src/main.c **** } 2306:Src/main.c **** 2307:Src/main.c **** static void Decode_task(uint16_t *Command, LDx_SetupTypeDef *LD1_curr_setup, LDx_SetupTypeDef *LD2_ 2308:Src/main.c **** { 253 .loc 1 2308 1 is_stmt 1 view -0 254 .cfi_startproc 255 @ args = 0, pretend = 0, frame = 8 256 @ frame_needed = 0, uses_anonymous_args = 0 257 @ link register save eliminated. 258 .loc 1 2308 1 is_stmt 0 view .LVU66 259 0000 82B0 sub sp, sp, #8 260 .LCFI4: 261 .cfi_def_cfa_offset 8 2309:Src/main.c **** uint16_t *temp2; 262 .loc 1 2309 2 is_stmt 1 view .LVU67 2310:Src/main.c **** 2311:Src/main.c **** temp2 = (uint16_t *)Command; 263 .loc 1 2311 2 view .LVU68 264 .LVL15: 2312:Src/main.c **** Curr_setup->WORK_EN = ((uint8_t)((*temp2)>>0))&0x01; 265 .loc 1 2312 2 view .LVU69 266 .loc 1 2312 36 is_stmt 0 view .LVU70 267 0002 0288 ldrh r2, [r0] 268 .LVL16: 269 .loc 1 2312 48 view .LVU71 270 0004 02F00102 and r2, r2, #1 271 .loc 1 2312 22 view .LVU72 272 0008 1A70 strb r2, [r3] 2313:Src/main.c **** Curr_setup->U5V1_EN = ((uint8_t)((*temp2)>>1))&0x01; 273 .loc 1 2313 2 is_stmt 1 view .LVU73 274 .loc 1 2313 36 is_stmt 0 view .LVU74 275 000a 0288 ldrh r2, [r0] 276 .loc 1 2313 48 view .LVU75 277 000c C2F34002 ubfx r2, r2, #1, #1 278 .loc 1 2313 22 view .LVU76 279 0010 5A70 strb r2, [r3, #1] 2314:Src/main.c **** Curr_setup->U5V2_EN = ((uint8_t)((*temp2)>>2))&0x01; 280 .loc 1 2314 2 is_stmt 1 view .LVU77 281 .loc 1 2314 36 is_stmt 0 view .LVU78 282 0012 0288 ldrh r2, [r0] 283 .loc 1 2314 48 view .LVU79 284 0014 C2F38002 ubfx r2, r2, #2, #1 285 .loc 1 2314 22 view .LVU80 286 0018 9A70 strb r2, [r3, #2] 2315:Src/main.c **** Curr_setup->LD1_EN = ((uint8_t)((*temp2)>>3))&0x01; 287 .loc 1 2315 2 is_stmt 1 view .LVU81 288 .loc 1 2315 35 is_stmt 0 view .LVU82 289 001a 0288 ldrh r2, [r0] 290 .loc 1 2315 47 view .LVU83 291 001c C2F3C002 ubfx r2, r2, #3, #1 292 .loc 1 2315 21 view .LVU84 293 0020 DA70 strb r2, [r3, #3] ARM GAS /tmp/ccYgfTud.s page 89 2316:Src/main.c **** Curr_setup->LD2_EN = ((uint8_t)((*temp2)>>4))&0x01; 294 .loc 1 2316 2 is_stmt 1 view .LVU85 295 .loc 1 2316 35 is_stmt 0 view .LVU86 296 0022 0288 ldrh r2, [r0] 297 .loc 1 2316 47 view .LVU87 298 0024 C2F30012 ubfx r2, r2, #4, #1 299 .loc 1 2316 21 view .LVU88 300 0028 1A71 strb r2, [r3, #4] 2317:Src/main.c **** Curr_setup->REF1_EN = ((uint8_t)((*temp2)>>5))&0x01; 301 .loc 1 2317 2 is_stmt 1 view .LVU89 302 .loc 1 2317 36 is_stmt 0 view .LVU90 303 002a 0288 ldrh r2, [r0] 304 .loc 1 2317 48 view .LVU91 305 002c C2F34012 ubfx r2, r2, #5, #1 306 .loc 1 2317 22 view .LVU92 307 0030 5A71 strb r2, [r3, #5] 2318:Src/main.c **** Curr_setup->REF2_EN = ((uint8_t)((*temp2)>>6))&0x01; 308 .loc 1 2318 2 is_stmt 1 view .LVU93 309 .loc 1 2318 36 is_stmt 0 view .LVU94 310 0032 0288 ldrh r2, [r0] 311 .loc 1 2318 48 view .LVU95 312 0034 C2F38012 ubfx r2, r2, #6, #1 313 .loc 1 2318 22 view .LVU96 314 0038 9A71 strb r2, [r3, #6] 2319:Src/main.c **** Curr_setup->TEC1_EN = ((uint8_t)((*temp2)>>7))&0x01; 315 .loc 1 2319 2 is_stmt 1 view .LVU97 316 .loc 1 2319 36 is_stmt 0 view .LVU98 317 003a 0288 ldrh r2, [r0] 318 .loc 1 2319 48 view .LVU99 319 003c C2F3C012 ubfx r2, r2, #7, #1 320 .loc 1 2319 22 view .LVU100 321 0040 DA71 strb r2, [r3, #7] 2320:Src/main.c **** Curr_setup->TEC2_EN = ((uint8_t)((*temp2)>>8))&0x01; 322 .loc 1 2320 2 is_stmt 1 view .LVU101 323 .loc 1 2320 36 is_stmt 0 view .LVU102 324 0042 0288 ldrh r2, [r0] 325 .loc 1 2320 48 view .LVU103 326 0044 C2F30022 ubfx r2, r2, #8, #1 327 .loc 1 2320 22 view .LVU104 328 0048 1A72 strb r2, [r3, #8] 2321:Src/main.c **** Curr_setup->TS1_EN = ((uint8_t)((*temp2)>>9))&0x01; 329 .loc 1 2321 2 is_stmt 1 view .LVU105 330 .loc 1 2321 35 is_stmt 0 view .LVU106 331 004a 0288 ldrh r2, [r0] 332 .loc 1 2321 47 view .LVU107 333 004c C2F34022 ubfx r2, r2, #9, #1 334 .loc 1 2321 21 view .LVU108 335 0050 5A72 strb r2, [r3, #9] 2322:Src/main.c **** Curr_setup->TS2_EN = ((uint8_t)((*temp2)>>10))&0x01; 336 .loc 1 2322 2 is_stmt 1 view .LVU109 337 .loc 1 2322 35 is_stmt 0 view .LVU110 338 0052 0288 ldrh r2, [r0] 339 .loc 1 2322 48 view .LVU111 340 0054 C2F38022 ubfx r2, r2, #10, #1 341 .loc 1 2322 21 view .LVU112 342 0058 9A72 strb r2, [r3, #10] 2323:Src/main.c **** Curr_setup->SD_EN = ((uint8_t)((*temp2)>>11))&0x01; ARM GAS /tmp/ccYgfTud.s page 90 343 .loc 1 2323 2 is_stmt 1 view .LVU113 344 .loc 1 2323 34 is_stmt 0 view .LVU114 345 005a 0288 ldrh r2, [r0] 346 .loc 1 2323 47 view .LVU115 347 005c C2F3C022 ubfx r2, r2, #11, #1 348 .loc 1 2323 20 view .LVU116 349 0060 DA72 strb r2, [r3, #11] 2324:Src/main.c **** Curr_setup->PI1_RD = ((uint8_t)((*temp2)>>12))&0x01; 350 .loc 1 2324 2 is_stmt 1 view .LVU117 351 .loc 1 2324 35 is_stmt 0 view .LVU118 352 0062 0288 ldrh r2, [r0] 353 .loc 1 2324 48 view .LVU119 354 0064 C2F30032 ubfx r2, r2, #12, #1 355 .loc 1 2324 21 view .LVU120 356 0068 1A73 strb r2, [r3, #12] 2325:Src/main.c **** Curr_setup->PI2_RD = ((uint8_t)((*temp2)>>13))&0x01; 357 .loc 1 2325 2 is_stmt 1 view .LVU121 358 .loc 1 2325 35 is_stmt 0 view .LVU122 359 006a 0288 ldrh r2, [r0] 360 .loc 1 2325 48 view .LVU123 361 006c C2F34032 ubfx r2, r2, #13, #1 362 .loc 1 2325 21 view .LVU124 363 0070 5A73 strb r2, [r3, #13] 2326:Src/main.c **** 2327:Src/main.c **** temp2++; 364 .loc 1 2327 2 is_stmt 1 view .LVU125 365 .LVL17: 2328:Src/main.c **** task.task_type = (uint8_t)(*temp2); temp2++; 366 .loc 1 2328 2 view .LVU126 367 .loc 1 2328 21 is_stmt 0 view .LVU127 368 0072 8278 ldrb r2, [r0, #2] @ zero_extendqisi2 369 .loc 1 2328 19 view .LVU128 370 0074 384B ldr r3, .L14+8 371 .LVL18: 372 .loc 1 2328 19 view .LVU129 373 0076 1A70 strb r2, [r3] 374 .loc 1 2328 40 is_stmt 1 view .LVU130 375 .LVL19: 2329:Src/main.c **** task.min_param = (float)(*temp2); temp2++; 376 .loc 1 2329 2 view .LVU131 377 .loc 1 2329 29 is_stmt 0 view .LVU132 378 0078 8288 ldrh r2, [r0, #4] 379 007a 07EE902A vmov s15, r2 @ int 380 .loc 1 2329 21 view .LVU133 381 007e F8EE677A vcvt.f32.u32 s15, s15 382 .loc 1 2329 19 view .LVU134 383 0082 C3ED017A vstr.32 s15, [r3, #4] 384 .loc 1 2329 38 is_stmt 1 view .LVU135 385 .LVL20: 2330:Src/main.c **** task.max_param = (float)(*temp2); temp2++; 386 .loc 1 2330 2 view .LVU136 387 .loc 1 2330 29 is_stmt 0 view .LVU137 388 0086 C288 ldrh r2, [r0, #6] 389 0088 07EE902A vmov s15, r2 @ int 390 .loc 1 2330 21 view .LVU138 391 008c F8EE677A vcvt.f32.u32 s15, s15 392 .loc 1 2330 19 view .LVU139 ARM GAS /tmp/ccYgfTud.s page 91 393 0090 C3ED027A vstr.32 s15, [r3, #8] 394 .loc 1 2330 38 is_stmt 1 view .LVU140 395 .LVL21: 2331:Src/main.c **** task.delta_param = (float)(*temp2); temp2++; 396 .loc 1 2331 2 view .LVU141 397 .loc 1 2331 29 is_stmt 0 view .LVU142 398 0094 0289 ldrh r2, [r0, #8] 399 0096 07EE902A vmov s15, r2 @ int 400 .loc 1 2331 21 view .LVU143 401 009a F8EE677A vcvt.f32.u32 s15, s15 402 .loc 1 2331 19 view .LVU144 403 009e C3ED037A vstr.32 s15, [r3, #12] 404 .loc 1 2331 38 is_stmt 1 view .LVU145 405 .LVL22: 2332:Src/main.c **** task.dt = (float)(*temp2) / 100.0; temp2++; 406 .loc 1 2332 2 view .LVU146 407 .loc 1 2332 29 is_stmt 0 view .LVU147 408 00a2 4289 ldrh r2, [r0, #10] 409 00a4 07EE102A vmov s14, r2 @ int 410 .loc 1 2332 21 view .LVU148 411 00a8 B8EE477B vcvt.f64.u32 d7, s14 412 .loc 1 2332 37 view .LVU149 413 00ac 9FED285B vldr.64 d5, .L14 414 00b0 87EE056B vdiv.f64 d6, d7, d5 415 .loc 1 2332 19 view .LVU150 416 00b4 FCEEC67B vcvt.u32.f64 s15, d6 417 00b8 CDED017A vstr.32 s15, [sp, #4] @ int 418 00bc 9DF80420 ldrb r2, [sp, #4] @ zero_extendqisi2 419 00c0 1A75 strb r2, [r3, #20] 420 .loc 1 2332 46 is_stmt 1 view .LVU151 421 .LVL23: 2333:Src/main.c **** task.sec_param = (float)(*temp2); temp2++; 422 .loc 1 2333 2 view .LVU152 423 .loc 1 2333 29 is_stmt 0 view .LVU153 424 00c2 8189 ldrh r1, [r0, #12] 425 .LVL24: 426 .loc 1 2333 29 view .LVU154 427 00c4 07EE901A vmov s15, r1 @ int 428 .loc 1 2333 21 view .LVU155 429 00c8 F8EE677A vcvt.f32.u32 s15, s15 430 .loc 1 2333 19 view .LVU156 431 00cc C3ED067A vstr.32 s15, [r3, #24] 432 .loc 1 2333 38 is_stmt 1 view .LVU157 433 .LVL25: 2334:Src/main.c **** task.curr = (float)(*temp2); temp2++; 434 .loc 1 2334 2 view .LVU158 435 .loc 1 2334 29 is_stmt 0 view .LVU159 436 00d0 C189 ldrh r1, [r0, #14] 437 00d2 07EE901A vmov s15, r1 @ int 438 .loc 1 2334 21 view .LVU160 439 00d6 F8EE677A vcvt.f32.u32 s15, s15 440 .loc 1 2334 19 view .LVU161 441 00da C3ED077A vstr.32 s15, [r3, #28] 442 .loc 1 2334 38 is_stmt 1 view .LVU162 443 .LVL26: 2335:Src/main.c **** task.temp = (float)(*temp2); temp2++; 444 .loc 1 2335 2 view .LVU163 ARM GAS /tmp/ccYgfTud.s page 92 445 .loc 1 2335 29 is_stmt 0 view .LVU164 446 00de 018A ldrh r1, [r0, #16] 447 00e0 07EE901A vmov s15, r1 @ int 448 .loc 1 2335 21 view .LVU165 449 00e4 F8EE677A vcvt.f32.u32 s15, s15 450 .loc 1 2335 19 view .LVU166 451 00e8 C3ED087A vstr.32 s15, [r3, #32] 452 .loc 1 2335 38 is_stmt 1 view .LVU167 453 .LVL27: 2336:Src/main.c **** task.tau = (float)(*temp2); temp2++; 454 .loc 1 2336 2 view .LVU168 455 .loc 1 2336 29 is_stmt 0 view .LVU169 456 00ec 418A ldrh r1, [r0, #18] 457 .loc 1 2336 19 view .LVU170 458 00ee D982 strh r1, [r3, #22] @ movhi 459 .loc 1 2336 38 is_stmt 1 view .LVU171 460 .LVL28: 2337:Src/main.c **** task.p_coef_1 = (float)(*temp2) * 256.0; temp2++; 461 .loc 1 2337 2 view .LVU172 462 .loc 1 2337 29 is_stmt 0 view .LVU173 463 00f0 818A ldrh r1, [r0, #20] 464 00f2 07EE901A vmov s15, r1 @ int 465 .loc 1 2337 21 view .LVU174 466 00f6 F8EE677A vcvt.f32.u32 s15, s15 467 .loc 1 2337 37 view .LVU175 468 00fa 9FED187A vldr.32 s14, .L14+12 469 00fe 67EE877A vmul.f32 s15, s15, s14 470 .loc 1 2337 19 view .LVU176 471 0102 C3ED0A7A vstr.32 s15, [r3, #40] 472 .loc 1 2337 46 is_stmt 1 view .LVU177 473 .LVL29: 2338:Src/main.c **** task.i_coef_1 = (float)(*temp2) * 256.0; temp2++; 474 .loc 1 2338 2 view .LVU178 475 .loc 1 2338 29 is_stmt 0 view .LVU179 476 0106 C18A ldrh r1, [r0, #22] 477 0108 07EE901A vmov s15, r1 @ int 478 .loc 1 2338 21 view .LVU180 479 010c F8EE677A vcvt.f32.u32 s15, s15 480 .loc 1 2338 37 view .LVU181 481 0110 67EE877A vmul.f32 s15, s15, s14 482 .loc 1 2338 19 view .LVU182 483 0114 C3ED097A vstr.32 s15, [r3, #36] 484 .loc 1 2338 46 is_stmt 1 view .LVU183 485 .LVL30: 2339:Src/main.c **** task.p_coef_2 = (float)(*temp2) * 256.0; temp2++; 486 .loc 1 2339 2 view .LVU184 487 .loc 1 2339 29 is_stmt 0 view .LVU185 488 0118 018B ldrh r1, [r0, #24] 489 011a 07EE901A vmov s15, r1 @ int 490 .loc 1 2339 21 view .LVU186 491 011e F8EE677A vcvt.f32.u32 s15, s15 492 .loc 1 2339 37 view .LVU187 493 0122 67EE877A vmul.f32 s15, s15, s14 494 .loc 1 2339 19 view .LVU188 495 0126 C3ED0C7A vstr.32 s15, [r3, #48] 496 .loc 1 2339 46 is_stmt 1 view .LVU189 497 .LVL31: ARM GAS /tmp/ccYgfTud.s page 93 2340:Src/main.c **** task.i_coef_2 = (float)(*temp2) * 256.0; temp2++; 498 .loc 1 2340 2 view .LVU190 499 .loc 1 2340 29 is_stmt 0 view .LVU191 500 012a 418B ldrh r1, [r0, #26] 501 012c 07EE901A vmov s15, r1 @ int 502 .loc 1 2340 21 view .LVU192 503 0130 F8EE677A vcvt.f32.u32 s15, s15 504 .loc 1 2340 37 view .LVU193 505 0134 67EE877A vmul.f32 s15, s15, s14 506 .loc 1 2340 19 view .LVU194 507 0138 C3ED0B7A vstr.32 s15, [r3, #44] 508 .loc 1 2340 46 is_stmt 1 view .LVU195 509 .LVL32: 2341:Src/main.c **** 2342:Src/main.c **** TO10_counter = task.dt / 10; 510 .loc 1 2342 2 view .LVU196 511 .loc 1 2342 25 is_stmt 0 view .LVU197 512 013c 084B ldr r3, .L14+16 513 013e A3FB0232 umull r3, r2, r3, r2 514 0142 D208 lsrs r2, r2, #3 515 .loc 1 2342 15 view .LVU198 516 0144 074B ldr r3, .L14+20 517 0146 1A60 str r2, [r3] 2343:Src/main.c **** } 518 .loc 1 2343 1 view .LVU199 519 0148 02B0 add sp, sp, #8 520 .LCFI5: 521 .cfi_def_cfa_offset 0 522 @ sp needed 523 014a 7047 bx lr 524 .L15: 525 014c AFF30080 .align 3 526 .L14: 527 0150 00000000 .word 0 528 0154 00005940 .word 1079574528 529 0158 00000000 .word task 530 015c 00008043 .word 1132462080 531 0160 CDCCCCCC .word -858993459 532 0164 00000000 .word TO10_counter 533 .cfi_endproc 534 .LFE1209: 536 .section .text.PID_Controller_Temp,"ax",%progbits 537 .align 1 538 .syntax unified 539 .thumb 540 .thumb_func 542 PID_Controller_Temp: 543 .LVL33: 544 .LFB1221: 2344:Src/main.c **** 2345:Src/main.c **** void OUT_trigger(uint8_t out_n) 2346:Src/main.c **** { 2347:Src/main.c **** switch (out_n) 2348:Src/main.c **** { 2349:Src/main.c **** case 0: 2350:Src/main.c **** HAL_GPIO_WritePin(OUT_0_GPIO_Port, OUT_0_Pin, GPIO_PIN_SET); 2351:Src/main.c **** HAL_GPIO_WritePin(OUT_0_GPIO_Port, OUT_0_Pin, GPIO_PIN_RESET); ARM GAS /tmp/ccYgfTud.s page 94 2352:Src/main.c **** break; 2353:Src/main.c **** 2354:Src/main.c **** case 1: 2355:Src/main.c **** HAL_GPIO_WritePin(OUT_1_GPIO_Port, OUT_1_Pin, GPIO_PIN_SET); 2356:Src/main.c **** HAL_GPIO_WritePin(OUT_1_GPIO_Port, OUT_1_Pin, GPIO_PIN_RESET); 2357:Src/main.c **** break; 2358:Src/main.c **** 2359:Src/main.c **** case 2: 2360:Src/main.c **** HAL_GPIO_WritePin(OUT_2_GPIO_Port, OUT_2_Pin, GPIO_PIN_SET); 2361:Src/main.c **** HAL_GPIO_WritePin(OUT_2_GPIO_Port, OUT_2_Pin, GPIO_PIN_RESET); 2362:Src/main.c **** break; 2363:Src/main.c **** 2364:Src/main.c **** case 3: 2365:Src/main.c **** HAL_GPIO_WritePin(OUT_3_GPIO_Port, OUT_3_Pin, GPIO_PIN_SET); 2366:Src/main.c **** HAL_GPIO_WritePin(OUT_3_GPIO_Port, OUT_3_Pin, GPIO_PIN_RESET); 2367:Src/main.c **** break; 2368:Src/main.c **** 2369:Src/main.c **** case 4: 2370:Src/main.c **** HAL_GPIO_WritePin(OUT_4_GPIO_Port, OUT_4_Pin, GPIO_PIN_SET); 2371:Src/main.c **** HAL_GPIO_WritePin(OUT_4_GPIO_Port, OUT_4_Pin, GPIO_PIN_RESET); 2372:Src/main.c **** break; 2373:Src/main.c **** 2374:Src/main.c **** case 5: 2375:Src/main.c **** HAL_GPIO_WritePin(OUT_5_GPIO_Port, OUT_5_Pin, GPIO_PIN_SET); 2376:Src/main.c **** HAL_GPIO_WritePin(OUT_5_GPIO_Port, OUT_5_Pin, GPIO_PIN_RESET); 2377:Src/main.c **** break; 2378:Src/main.c **** 2379:Src/main.c **** case 6: 2380:Src/main.c **** HAL_GPIO_WritePin(OUT_6_GPIO_Port, OUT_6_Pin, GPIO_PIN_SET); 2381:Src/main.c **** HAL_GPIO_WritePin(OUT_6_GPIO_Port, OUT_6_Pin, GPIO_PIN_RESET); 2382:Src/main.c **** break; 2383:Src/main.c **** 2384:Src/main.c **** case 7: 2385:Src/main.c **** HAL_GPIO_WritePin(OUT_7_GPIO_Port, OUT_7_Pin, GPIO_PIN_SET); 2386:Src/main.c **** HAL_GPIO_WritePin(OUT_7_GPIO_Port, OUT_7_Pin, GPIO_PIN_RESET); 2387:Src/main.c **** break; 2388:Src/main.c **** 2389:Src/main.c **** case 8: 2390:Src/main.c **** HAL_GPIO_WritePin(OUT_8_GPIO_Port, OUT_8_Pin, GPIO_PIN_SET); 2391:Src/main.c **** HAL_GPIO_WritePin(OUT_8_GPIO_Port, OUT_8_Pin, GPIO_PIN_RESET); 2392:Src/main.c **** break; 2393:Src/main.c **** 2394:Src/main.c **** case 9: 2395:Src/main.c **** HAL_GPIO_WritePin(OUT_9_GPIO_Port, OUT_9_Pin, GPIO_PIN_SET); 2396:Src/main.c **** HAL_GPIO_WritePin(OUT_9_GPIO_Port, OUT_9_Pin, GPIO_PIN_RESET); 2397:Src/main.c **** break; 2398:Src/main.c **** } 2399:Src/main.c **** } 2400:Src/main.c **** 2401:Src/main.c **** static void AD9102_Init(void) 2402:Src/main.c **** { 2403:Src/main.c **** HAL_GPIO_WritePin(AD9102_CS_GPIO_Port, AD9102_CS_Pin, GPIO_PIN_SET); 2404:Src/main.c **** HAL_GPIO_WritePin(AD9102_RESET_GPIO_Port, AD9102_RESET_Pin, GPIO_PIN_RESET); 2405:Src/main.c **** for (volatile uint32_t d = 0; d < 1000; d++) {} 2406:Src/main.c **** HAL_GPIO_WritePin(AD9102_RESET_GPIO_Port, AD9102_RESET_Pin, GPIO_PIN_SET); 2407:Src/main.c **** 2408:Src/main.c **** AD9102_WriteRegTable(ad9102_example4_regval, AD9102_REG_COUNT); ARM GAS /tmp/ccYgfTud.s page 95 2409:Src/main.c **** AD9102_WriteReg(AD9102_REG_PAT_STATUS, 0x0000u); 2410:Src/main.c **** AD9102_WriteReg(AD9102_REG_RAMUPDATE, 0x0001u); 2411:Src/main.c **** HAL_GPIO_WritePin(AD9102_TRIG_GPIO_Port, AD9102_TRIG_Pin, GPIO_PIN_SET); 2412:Src/main.c **** } 2413:Src/main.c **** 2414:Src/main.c **** static void AD9102_WriteReg(uint16_t addr, uint16_t value) 2415:Src/main.c **** { 2416:Src/main.c **** uint32_t tmp32 = 0; 2417:Src/main.c **** uint16_t cmd = (uint16_t)(addr & 0x7FFFu); // R/W = 0 (write), 15-bit address 2418:Src/main.c **** 2419:Src/main.c **** if (!LL_SPI_IsEnabled(SPI2)) 2420:Src/main.c **** { 2421:Src/main.c **** LL_SPI_Enable(SPI2); 2422:Src/main.c **** } 2423:Src/main.c **** 2424:Src/main.c **** HAL_GPIO_WritePin(AD9102_CS_GPIO_Port, AD9102_CS_Pin, GPIO_PIN_RESET); 2425:Src/main.c **** 2426:Src/main.c **** while((!LL_SPI_IsActiveFlag_TXE(SPI2)) && (tmp32++ < 1000)) {} 2427:Src/main.c **** LL_SPI_TransmitData16(SPI2, cmd); 2428:Src/main.c **** tmp32 = 0; 2429:Src/main.c **** while((!LL_SPI_IsActiveFlag_RXNE(SPI2)) && (tmp32++ < 1000)) {} 2430:Src/main.c **** (void) SPI2->DR; 2431:Src/main.c **** 2432:Src/main.c **** tmp32 = 0; 2433:Src/main.c **** while((!LL_SPI_IsActiveFlag_TXE(SPI2)) && (tmp32++ < 1000)) {} 2434:Src/main.c **** LL_SPI_TransmitData16(SPI2, value); 2435:Src/main.c **** tmp32 = 0; 2436:Src/main.c **** while((!LL_SPI_IsActiveFlag_RXNE(SPI2)) && (tmp32++ < 1000)) {} 2437:Src/main.c **** (void) SPI2->DR; 2438:Src/main.c **** 2439:Src/main.c **** HAL_GPIO_WritePin(AD9102_CS_GPIO_Port, AD9102_CS_Pin, GPIO_PIN_SET); 2440:Src/main.c **** } 2441:Src/main.c **** 2442:Src/main.c **** static uint16_t AD9102_ReadReg(uint16_t addr) 2443:Src/main.c **** { 2444:Src/main.c **** uint32_t tmp32 = 0; 2445:Src/main.c **** uint16_t cmd = (uint16_t)(0x8000u | (addr & 0x7FFFu)); // R/W = 1 (read) 2446:Src/main.c **** uint16_t value; 2447:Src/main.c **** 2448:Src/main.c **** if (!LL_SPI_IsEnabled(SPI2)) 2449:Src/main.c **** { 2450:Src/main.c **** LL_SPI_Enable(SPI2); 2451:Src/main.c **** } 2452:Src/main.c **** 2453:Src/main.c **** HAL_GPIO_WritePin(AD9102_CS_GPIO_Port, AD9102_CS_Pin, GPIO_PIN_RESET); 2454:Src/main.c **** 2455:Src/main.c **** while((!LL_SPI_IsActiveFlag_TXE(SPI2)) && (tmp32++ < 1000)) {} 2456:Src/main.c **** LL_SPI_TransmitData16(SPI2, cmd); 2457:Src/main.c **** tmp32 = 0; 2458:Src/main.c **** while((!LL_SPI_IsActiveFlag_RXNE(SPI2)) && (tmp32++ < 1000)) {} 2459:Src/main.c **** (void) SPI2->DR; 2460:Src/main.c **** 2461:Src/main.c **** tmp32 = 0; 2462:Src/main.c **** while((!LL_SPI_IsActiveFlag_TXE(SPI2)) && (tmp32++ < 1000)) {} 2463:Src/main.c **** LL_SPI_TransmitData16(SPI2, 0x0000u); 2464:Src/main.c **** tmp32 = 0; 2465:Src/main.c **** while((!LL_SPI_IsActiveFlag_RXNE(SPI2)) && (tmp32++ < 1000)) {} ARM GAS /tmp/ccYgfTud.s page 96 2466:Src/main.c **** value = LL_SPI_ReceiveData16(SPI2); 2467:Src/main.c **** 2468:Src/main.c **** HAL_GPIO_WritePin(AD9102_CS_GPIO_Port, AD9102_CS_Pin, GPIO_PIN_SET); 2469:Src/main.c **** return value; 2470:Src/main.c **** } 2471:Src/main.c **** 2472:Src/main.c **** static void AD9102_WriteRegTable(const uint16_t *values, uint16_t count) 2473:Src/main.c **** { 2474:Src/main.c **** for (uint16_t i = 0; i < count; i++) 2475:Src/main.c **** { 2476:Src/main.c **** AD9102_WriteReg(ad9102_reg_addr[i], values[i]); 2477:Src/main.c **** } 2478:Src/main.c **** } 2479:Src/main.c **** 2480:Src/main.c **** static uint16_t AD9102_Apply(uint8_t saw_type, uint8_t enable, uint8_t saw_step, uint8_t pat_base, 2481:Src/main.c **** { 2482:Src/main.c **** if (enable) 2483:Src/main.c **** { 2484:Src/main.c **** uint16_t saw_cfg; 2485:Src/main.c **** uint16_t pat_timebase; 2486:Src/main.c **** 2487:Src/main.c **** if (saw_step == 0u) 2488:Src/main.c **** { 2489:Src/main.c **** saw_step = AD9102_SAW_STEP_DEFAULT; 2490:Src/main.c **** } 2491:Src/main.c **** if (saw_step > 63u) 2492:Src/main.c **** { 2493:Src/main.c **** saw_step = 63u; 2494:Src/main.c **** } 2495:Src/main.c **** saw_cfg = (uint16_t)(((uint16_t)(saw_step & 0x3Fu) << 2) | 2496:Src/main.c **** ((uint16_t)(saw_type & 0x3u))); 2497:Src/main.c **** pat_timebase = (uint16_t)(((AD9102_PAT_TIMEBASE_HOLD_DEFAULT & 0x0Fu) << 8) | 2498:Src/main.c **** ((pat_base & 0x0Fu) << 4) | 2499:Src/main.c **** (AD9102_START_DELAY_BASE_DEFAULT & 0x0Fu)); 2500:Src/main.c **** 2501:Src/main.c **** AD9102_WriteReg(AD9102_REG_WAV_CONFIG, AD9102_EX4_WAV_CONFIG); 2502:Src/main.c **** AD9102_WriteReg(AD9102_REG_SAW_CONFIG, saw_cfg); 2503:Src/main.c **** AD9102_WriteReg(AD9102_REG_PAT_TIMEBASE, pat_timebase); 2504:Src/main.c **** AD9102_WriteReg(AD9102_REG_PAT_PERIOD, pat_period); 2505:Src/main.c **** AD9102_WriteReg(AD9102_REG_PAT_TYPE, 0x0000u); // continuous pattern repeat 2506:Src/main.c **** 2507:Src/main.c **** // Update RUN then RAMUPDATE at the end of the write sequence. 2508:Src/main.c **** // AD9102 output is started by a falling edge of TRIGGER pin when RUN=1. 2509:Src/main.c **** HAL_GPIO_WritePin(AD9102_TRIG_GPIO_Port, AD9102_TRIG_Pin, GPIO_PIN_SET); 2510:Src/main.c **** AD9102_WriteReg(AD9102_REG_PAT_STATUS, AD9102_PAT_STATUS_RUN); 2511:Src/main.c **** AD9102_WriteReg(AD9102_REG_RAMUPDATE, 0x0001u); 2512:Src/main.c **** for (volatile uint32_t d = 0; d < 1000; d++) {} 2513:Src/main.c **** HAL_GPIO_WritePin(AD9102_TRIG_GPIO_Port, AD9102_TRIG_Pin, GPIO_PIN_RESET); 2514:Src/main.c **** } 2515:Src/main.c **** else 2516:Src/main.c **** { 2517:Src/main.c **** AD9102_WriteReg(AD9102_REG_PAT_STATUS, 0x0000u); 2518:Src/main.c **** HAL_GPIO_WritePin(AD9102_TRIG_GPIO_Port, AD9102_TRIG_Pin, GPIO_PIN_SET); 2519:Src/main.c **** } 2520:Src/main.c **** 2521:Src/main.c **** return AD9102_ReadReg(AD9102_REG_PAT_STATUS); 2522:Src/main.c **** } ARM GAS /tmp/ccYgfTud.s page 97 2523:Src/main.c **** 2524:Src/main.c **** static uint8_t AD9102_CheckFlags(uint16_t pat_status, uint8_t expect_run, uint8_t saw_type, uint8_t 2525:Src/main.c **** { 2526:Src/main.c **** uint16_t spiconfig = AD9102_ReadReg(AD9102_REG_SPICONFIG); 2527:Src/main.c **** uint16_t powercfg = AD9102_ReadReg(AD9102_REG_POWERCONFIG); 2528:Src/main.c **** uint16_t clockcfg = AD9102_ReadReg(AD9102_REG_CLOCKCONFIG); 2529:Src/main.c **** uint16_t cfg_err = AD9102_ReadReg(AD9102_REG_CFG_ERROR); 2530:Src/main.c **** uint16_t pat_timebase = (uint16_t)(((AD9102_PAT_TIMEBASE_HOLD_DEFAULT & 0x0Fu) << 8) | 2531:Src/main.c **** ((pat_base & 0x0Fu) << 4) | 2532:Src/main.c **** (AD9102_START_DELAY_BASE_DEFAULT & 0x0Fu)); 2533:Src/main.c **** 2534:Src/main.c **** if (saw_step == 0u) 2535:Src/main.c **** { 2536:Src/main.c **** saw_step = AD9102_SAW_STEP_DEFAULT; 2537:Src/main.c **** } 2538:Src/main.c **** if (saw_step > 63u) 2539:Src/main.c **** { 2540:Src/main.c **** saw_step = 63u; 2541:Src/main.c **** } 2542:Src/main.c **** if (pat_period == 0u) 2543:Src/main.c **** { 2544:Src/main.c **** pat_period = AD9102_PAT_PERIOD_DEFAULT; 2545:Src/main.c **** } 2546:Src/main.c **** uint16_t expect_saw = (uint16_t)(((uint16_t)(saw_step & 0x3Fu) << 2) | 2547:Src/main.c **** ((uint16_t)(saw_type & 0x3u))); 2548:Src/main.c **** 2549:Src/main.c **** uint8_t ok = 1u; 2550:Src/main.c **** 2551:Src/main.c **** // Expect default SPI config: MSB-first, 4-wire, no double SPI, no reset. 2552:Src/main.c **** if (spiconfig != 0x0000u) 2553:Src/main.c **** { 2554:Src/main.c **** ok = 0u; 2555:Src/main.c **** } 2556:Src/main.c **** 2557:Src/main.c **** // Power blocks should not be powered down. 2558:Src/main.c **** if (powercfg & ((1u << 8) | (1u << 7) | (1u << 6) | (1u << 5) | (1u << 3))) 2559:Src/main.c **** { 2560:Src/main.c **** ok = 0u; 2561:Src/main.c **** } 2562:Src/main.c **** 2563:Src/main.c **** // Clock receiver must be enabled (cannot directly detect external clock presence). 2564:Src/main.c **** if (clockcfg & ((1u << 11) | (1u << 7) | (1u << 6) | (1u << 5))) 2565:Src/main.c **** { 2566:Src/main.c **** ok = 0u; 2567:Src/main.c **** } 2568:Src/main.c **** 2569:Src/main.c **** // Any configuration error flags indicate a bad setup. 2570:Src/main.c **** if (cfg_err & 0x003Fu) 2571:Src/main.c **** { 2572:Src/main.c **** ok = 0u; 2573:Src/main.c **** } 2574:Src/main.c **** 2575:Src/main.c **** if (expect_run && ((pat_status & AD9102_PAT_STATUS_RUN) == 0u)) 2576:Src/main.c **** { 2577:Src/main.c **** ok = 0u; 2578:Src/main.c **** } 2579:Src/main.c **** ARM GAS /tmp/ccYgfTud.s page 98 2580:Src/main.c **** if (AD9102_ReadReg(AD9102_REG_WAV_CONFIG) != AD9102_EX4_WAV_CONFIG) 2581:Src/main.c **** { 2582:Src/main.c **** ok = 0u; 2583:Src/main.c **** } 2584:Src/main.c **** if (AD9102_ReadReg(AD9102_REG_PAT_TIMEBASE) != pat_timebase) 2585:Src/main.c **** { 2586:Src/main.c **** ok = 0u; 2587:Src/main.c **** } 2588:Src/main.c **** if (AD9102_ReadReg(AD9102_REG_PAT_PERIOD) != pat_period) 2589:Src/main.c **** { 2590:Src/main.c **** ok = 0u; 2591:Src/main.c **** } 2592:Src/main.c **** if (AD9102_ReadReg(AD9102_REG_PAT_TYPE) != 0x0000u) 2593:Src/main.c **** { 2594:Src/main.c **** ok = 0u; 2595:Src/main.c **** } 2596:Src/main.c **** if (AD9102_ReadReg(AD9102_REG_SAW_CONFIG) != expect_saw) 2597:Src/main.c **** { 2598:Src/main.c **** ok = 0u; 2599:Src/main.c **** } 2600:Src/main.c **** 2601:Src/main.c **** return (ok ? 0u : 1u); 2602:Src/main.c **** } 2603:Src/main.c **** 2604:Src/main.c **** void Set_LTEC(uint8_t num, uint16_t DATA) 2605:Src/main.c **** { 2606:Src/main.c **** uint32_t tmp32; 2607:Src/main.c **** 2608:Src/main.c **** #if AD9102_ON_SPI2 2609:Src/main.c **** // AD9102 occupies SPI2; skip LD1/TEC1 writes to avoid CS conflicts. 2610:Src/main.c **** if (num == 1 || num == 3) 2611:Src/main.c **** { 2612:Src/main.c **** return; 2613:Src/main.c **** } 2614:Src/main.c **** #endif 2615:Src/main.c **** 2616:Src/main.c **** switch (num) 2617:Src/main.c **** { 2618:Src/main.c **** case 1: 2619:Src/main.c **** HAL_GPIO_WritePin(DAC_LD1_CS_GPIO_Port, DAC_LD1_CS_Pin, GPIO_PIN_RESET);//Start operation with L 2620:Src/main.c **** //tmp32=0; 2621:Src/main.c **** //while(tmp32<500){tmp32++;} 2622:Src/main.c **** tmp32 = 0; 2623:Src/main.c **** while((!LL_SPI_IsActiveFlag_TXE(SPI2))&&(tmp32<=500)) {tmp32++;}//When trans. last data cycle wi 2624:Src/main.c **** LL_SPI_TransmitData16(SPI2, DATA);//Transmit word to Laser1 DAC 2625:Src/main.c **** tmp32 = 0; 2626:Src/main.c **** while((!LL_SPI_IsActiveFlag_RXNE(SPI2))&&(tmp32<=500)) {tmp32++;}//When trans. last data cycle w 2627:Src/main.c **** (void) SPI2->DR; 2628:Src/main.c **** break; 2629:Src/main.c **** case 2: 2630:Src/main.c **** //HAL_GPIO_TogglePin(OUT_11_GPIO_Port, OUT_11_Pin); //for debug purposes 2631:Src/main.c **** HAL_GPIO_WritePin(DAC_LD2_CS_GPIO_Port, DAC_LD2_CS_Pin, GPIO_PIN_RESET);//Start operation with L 2632:Src/main.c **** //tmp32=0; 2633:Src/main.c **** //while(tmp32<500){tmp32++;} 2634:Src/main.c **** tmp32 = 0; 2635:Src/main.c **** while((!LL_SPI_IsActiveFlag_TXE(SPI6))&&(tmp32<=500)) {tmp32++;}//When trans. last data cycle wi 2636:Src/main.c **** LL_SPI_TransmitData16(SPI6, DATA);//Transmit word to Laser1 DAC ARM GAS /tmp/ccYgfTud.s page 99 2637:Src/main.c **** tmp32 = 0; 2638:Src/main.c **** while((!LL_SPI_IsActiveFlag_RXNE(SPI6))&&(tmp32<=500)) {tmp32++;}//When trans. last data cycle w 2639:Src/main.c **** (void) SPI6->DR; 2640:Src/main.c **** break; 2641:Src/main.c **** case 3: 2642:Src/main.c **** HAL_GPIO_WritePin(DAC_TEC1_CS_GPIO_Port, DAC_TEC1_CS_Pin, GPIO_PIN_RESET);//Start operation with 2643:Src/main.c **** //tmp32=0; 2644:Src/main.c **** //while(tmp32<500){tmp32++;} 2645:Src/main.c **** tmp32 = 0; 2646:Src/main.c **** while((!LL_SPI_IsActiveFlag_TXE(SPI2))&&(tmp32<=500)) {tmp32++;}//When trans. last data cycle wi 2647:Src/main.c **** LL_SPI_TransmitData16(SPI2, DATA);//Transmit word to Laser1 DAC 2648:Src/main.c **** tmp32 = 0; 2649:Src/main.c **** while((!LL_SPI_IsActiveFlag_RXNE(SPI2))&&(tmp32<=500)) {tmp32++;}//When trans. last data cycle w 2650:Src/main.c **** (void) SPI2->DR; 2651:Src/main.c **** break; 2652:Src/main.c **** case 4: 2653:Src/main.c **** HAL_GPIO_WritePin(DAC_TEC2_CS_GPIO_Port, DAC_TEC2_CS_Pin, GPIO_PIN_RESET);//Start operation with 2654:Src/main.c **** //tmp32=0; 2655:Src/main.c **** //while(tmp32<500){tmp32++;} 2656:Src/main.c **** tmp32 = 0; 2657:Src/main.c **** while((!LL_SPI_IsActiveFlag_TXE(SPI6))&&(tmp32<=500)) {tmp32++;}//When trans. last data cycle wi 2658:Src/main.c **** LL_SPI_TransmitData16(SPI6, DATA);//Transmit word to Laser1 DAC 2659:Src/main.c **** tmp32 = 0; 2660:Src/main.c **** while((!LL_SPI_IsActiveFlag_RXNE(SPI6))&&(tmp32<=500)) {tmp32++;}//When trans. last data cycle w 2661:Src/main.c **** (void) SPI6->DR; 2662:Src/main.c **** break; 2663:Src/main.c **** } 2664:Src/main.c **** HAL_GPIO_WritePin(DAC_LD1_CS_GPIO_Port, DAC_LD1_CS_Pin, GPIO_PIN_SET);//End operation with LDAC1 2665:Src/main.c **** HAL_GPIO_WritePin(DAC_LD2_CS_GPIO_Port, DAC_LD2_CS_Pin, GPIO_PIN_SET);//End operation with LDAC2 2666:Src/main.c **** HAL_GPIO_WritePin(DAC_TEC1_CS_GPIO_Port, DAC_TEC1_CS_Pin, GPIO_PIN_SET);//End operation with TEC1 2667:Src/main.c **** HAL_GPIO_WritePin(DAC_TEC2_CS_GPIO_Port, DAC_TEC2_CS_Pin, GPIO_PIN_SET);//End operation with TEC2 2668:Src/main.c **** } 2669:Src/main.c **** static uint16_t MPhD_T(uint8_t num) 2670:Src/main.c **** { 2671:Src/main.c **** uint16_t P; 2672:Src/main.c **** uint32_t tmp32; 2673:Src/main.c **** HAL_GPIO_WritePin(SPI4_CNV_GPIO_Port, SPI4_CNV_Pin, GPIO_PIN_RESET);//Prepare conversion 2674:Src/main.c **** HAL_GPIO_WritePin(SPI5_CNV_GPIO_Port, SPI5_CNV_Pin, GPIO_PIN_RESET);//Prepare conversion 2675:Src/main.c **** tmp32=0; 2676:Src/main.c **** while(tmp32<500){tmp32++;} 2677:Src/main.c **** HAL_GPIO_WritePin(SPI4_CNV_GPIO_Port, SPI4_CNV_Pin, GPIO_PIN_SET);//Stop acqusition & start conver 2678:Src/main.c **** HAL_GPIO_WritePin(SPI5_CNV_GPIO_Port, SPI5_CNV_Pin, GPIO_PIN_SET);//Stop acqusition & start conver 2679:Src/main.c **** tmp32=0; 2680:Src/main.c **** while(tmp32<500){tmp32++;} 2681:Src/main.c **** if (num==1)//MPD1 2682:Src/main.c **** { 2683:Src/main.c **** HAL_GPIO_WritePin(ADC_ThrLD1_CS_GPIO_Port, ADC_ThrLD1_CS_Pin, GPIO_PIN_SET); 2684:Src/main.c **** HAL_GPIO_WritePin(ADC_MPD1_CS_GPIO_Port, ADC_MPD1_CS_Pin, GPIO_PIN_RESET); 2685:Src/main.c **** tmp32=0; 2686:Src/main.c **** while(tmp32<500){tmp32++;} 2687:Src/main.c **** //LL_SPI_TransmitData16(SPI4, 0xFFFF);//We must to clock the CLK output for collect RX data. We c 2688:Src/main.c **** LL_SPI_Enable(SPI4);//Enable SPI for MPhD1 ADC 2689:Src/main.c **** tmp32 = 0; 2690:Src/main.c **** while(((!LL_SPI_IsActiveFlag_RXNE(SPI4))&&(tmp32<=1000))) {tmp32++;}//When rec. last data cycle w 2691:Src/main.c **** LL_SPI_Disable(SPI4);//Enable SPI for MPhD1 ADC 2692:Src/main.c **** while(tmp32<500){tmp32++;} 2693:Src/main.c **** //HAL_SPI_Receive(&hspi4, &P[0], 1, 100); ARM GAS /tmp/ccYgfTud.s page 100 2694:Src/main.c **** HAL_GPIO_WritePin(ADC_MPD1_CS_GPIO_Port, ADC_MPD1_CS_Pin, GPIO_PIN_SET); 2695:Src/main.c **** P = LL_SPI_ReceiveData16(SPI4); 2696:Src/main.c **** } 2697:Src/main.c **** else if (num==2)//MPD2 2698:Src/main.c **** { 2699:Src/main.c **** HAL_GPIO_WritePin(ADC_ThrLD2_CS_GPIO_Port, ADC_ThrLD2_CS_Pin, GPIO_PIN_SET); 2700:Src/main.c **** HAL_GPIO_WritePin(ADC_MPD2_CS_GPIO_Port, ADC_MPD2_CS_Pin, GPIO_PIN_RESET); 2701:Src/main.c **** tmp32=0; 2702:Src/main.c **** while(tmp32<500){tmp32++;} 2703:Src/main.c **** //LL_SPI_TransmitData16(SPI5, 0xFFFF);//We must to clock the CLK output for collect RX data. We c 2704:Src/main.c **** LL_SPI_Enable(SPI5);//Enable SPI for MPhD2 ADC 2705:Src/main.c **** tmp32 = 0; 2706:Src/main.c **** while(((!LL_SPI_IsActiveFlag_RXNE(SPI5))&&(tmp32<=1000))) {tmp32++;}//When rec. last data cycle w 2707:Src/main.c **** LL_SPI_Disable(SPI5);//Enable SPI for MPhD2 ADC 2708:Src/main.c **** while(tmp32<500){tmp32++;} 2709:Src/main.c **** //HAL_SPI_Receive(&hspi4, &P[0], 1, 100); 2710:Src/main.c **** HAL_GPIO_WritePin(ADC_MPD2_CS_GPIO_Port, ADC_MPD2_CS_Pin, GPIO_PIN_SET); 2711:Src/main.c **** P = LL_SPI_ReceiveData16(SPI5); 2712:Src/main.c **** } 2713:Src/main.c **** else if (num==3)//ThrLD1 2714:Src/main.c **** { 2715:Src/main.c **** HAL_GPIO_WritePin(ADC_MPD1_CS_GPIO_Port, ADC_MPD1_CS_Pin, GPIO_PIN_SET); 2716:Src/main.c **** HAL_GPIO_WritePin(ADC_ThrLD1_CS_GPIO_Port, ADC_ThrLD1_CS_Pin, GPIO_PIN_RESET); 2717:Src/main.c **** tmp32=0; 2718:Src/main.c **** while(tmp32<500){tmp32++;} 2719:Src/main.c **** //LL_SPI_TransmitData16(SPI4, 0xFFFF);//We must to clock the CLK output for collect RX data. We c 2720:Src/main.c **** LL_SPI_Enable(SPI4);//Enable SPI for ThrLD1 ADC 2721:Src/main.c **** tmp32 = 0; 2722:Src/main.c **** while(((!LL_SPI_IsActiveFlag_RXNE(SPI4))&&(tmp32<=1000))) {tmp32++;}//When rec. last data cycle w 2723:Src/main.c **** LL_SPI_Disable(SPI4);//Enable SPI for ThrLD1 ADC 2724:Src/main.c **** while(tmp32<500){tmp32++;} 2725:Src/main.c **** //HAL_SPI_Receive(&hspi4, &P[0], 1, 100); 2726:Src/main.c **** HAL_GPIO_WritePin(ADC_ThrLD1_CS_GPIO_Port, ADC_ThrLD1_CS_Pin, GPIO_PIN_SET); 2727:Src/main.c **** P = LL_SPI_ReceiveData16(SPI4); 2728:Src/main.c **** } 2729:Src/main.c **** else if (num==4)//ThrLD2 2730:Src/main.c **** { 2731:Src/main.c **** HAL_GPIO_WritePin(ADC_MPD2_CS_GPIO_Port, ADC_MPD2_CS_Pin, GPIO_PIN_SET); 2732:Src/main.c **** HAL_GPIO_WritePin(ADC_ThrLD2_CS_GPIO_Port, ADC_ThrLD2_CS_Pin, GPIO_PIN_RESET); 2733:Src/main.c **** tmp32=0; 2734:Src/main.c **** while(tmp32<500){tmp32++;} 2735:Src/main.c **** //LL_SPI_TransmitData16(SPI5, 0xFFFF);//We must to clock the CLK output for collect RX data. We c 2736:Src/main.c **** LL_SPI_Enable(SPI5);//Enable SPI for ThrLD2 ADC 2737:Src/main.c **** tmp32 = 0; 2738:Src/main.c **** while(((!LL_SPI_IsActiveFlag_RXNE(SPI5))&&(tmp32<=1000))) {tmp32++;}//When rec. last data cycle w 2739:Src/main.c **** LL_SPI_Disable(SPI5);//Enable SPI for ThrLD2 ADC 2740:Src/main.c **** while(tmp32<500){tmp32++;} 2741:Src/main.c **** //HAL_SPI_Receive(&hspi4, &P[0], 1, 100); 2742:Src/main.c **** HAL_GPIO_WritePin(ADC_ThrLD2_CS_GPIO_Port, ADC_ThrLD2_CS_Pin, GPIO_PIN_SET); 2743:Src/main.c **** P = LL_SPI_ReceiveData16(SPI5); 2744:Src/main.c **** } 2745:Src/main.c **** /*float I_LD, Ith, I0m, T0m, Inorm, Tnorm1, Tnorm2, P, T_C, A, Pnorm; 2746:Src/main.c **** 2747:Src/main.c **** Inorm = (float) (65535) / (float) (100); 2748:Src/main.c **** Tnorm1 = (float) (65535) / (float) (50); 2749:Src/main.c **** Tnorm2 = 4; 2750:Src/main.c **** Pnorm = (float)(65535) / (float)(20); ARM GAS /tmp/ccYgfTud.s page 101 2751:Src/main.c **** I0m = 8.1568;//@4 C - lowest temperature of system 2752:Src/main.c **** T0m = 48.6282; 2753:Src/main.c **** T_C = (float) (T_LD) / Tnorm1 + Tnorm2; 2754:Src/main.c **** 2755:Src/main.c **** Ith = I0m * expf(T_C/T0m); 2756:Src/main.c **** I_LD = (float) (C_LD) / Inorm; 2757:Src/main.c **** 2758:Src/main.c **** if (I_LD > Ith) 2759:Src/main.c **** { 2760:Src/main.c **** A = (float) (2.24276128270098e-07) * T_C * T_C * T_C - (float) (4.73392579025590e-05) * T_C * T_ 2761:Src/main.c **** P = A * (I_LD - Ith) * Pnorm; 2762:Src/main.c **** } 2763:Src/main.c **** else 2764:Src/main.c **** { 2765:Src/main.c **** P = 0; 2766:Src/main.c **** } */ 2767:Src/main.c **** return P; 2768:Src/main.c **** } 2769:Src/main.c **** /*static uint16_t Temp_LD(uint16_t T_LD_before, uint16_t T_LD, uint32_t Timer_before, uint32_t Time 2770:Src/main.c **** { 2771:Src/main.c **** uint16_t Result; 2772:Src/main.c **** // uint8_t randf; 2773:Src/main.c **** 2774:Src/main.c **** randf = 0; 2775:Src/main.c **** for (uint8_t i = 0; i < 32; i++) 2776:Src/main.c **** { 2777:Src/main.c **** randf = ((Timer>>i)&0x0001)^randf; 2778:Src/main.c **** } 2779:Src/main.c **** 2780:Src/main.c **** Result = ((float)(T_LD - T_LD_before))*((float)(1-expf(((float)(Timer_before)-(float)(Timer))/((fl 2781:Src/main.c **** 2782:Src/main.c **** return (uint16_t)(Result); 2783:Src/main.c **** }*/ 2784:Src/main.c **** static uint16_t Get_ADC(uint8_t num) 2785:Src/main.c **** { 2786:Src/main.c **** uint16_t OUT; 2787:Src/main.c **** switch (num) 2788:Src/main.c **** { 2789:Src/main.c **** case 0: 2790:Src/main.c **** HAL_ADC_Start(&hadc1); // Power on 2791:Src/main.c **** break; 2792:Src/main.c **** case 1: 2793:Src/main.c **** HAL_ADC_PollForConversion(&hadc1, 100); // Waiting for conversion 2794:Src/main.c **** OUT = HAL_ADC_GetValue(&hadc1); // Get value adc 2795:Src/main.c **** break; 2796:Src/main.c **** case 2: 2797:Src/main.c **** HAL_ADC_Stop(&hadc1); // Power off 2798:Src/main.c **** break; 2799:Src/main.c **** case 3: 2800:Src/main.c **** HAL_ADC_Start(&hadc3); // Power on 2801:Src/main.c **** break; 2802:Src/main.c **** case 4: 2803:Src/main.c **** HAL_ADC_PollForConversion(&hadc3, 100); // Waiting for conversion 2804:Src/main.c **** OUT = HAL_ADC_GetValue(&hadc3); // Get value adc 2805:Src/main.c **** break; 2806:Src/main.c **** case 5: 2807:Src/main.c **** HAL_ADC_Stop(&hadc3); // Power off ARM GAS /tmp/ccYgfTud.s page 102 2808:Src/main.c **** break; 2809:Src/main.c **** } 2810:Src/main.c **** return OUT; 2811:Src/main.c **** } 2812:Src/main.c **** 2813:Src/main.c **** uint16_t Advanced_Controller_Temp(LDx_SetupTypeDef * LDx_curr_setup, LDx_ParamTypeDef * LDx_results 2814:Src/main.c **** { 2815:Src/main.c **** // Main idea: 2816:Src/main.c **** // I is responsible to maintaining constant temperature difference between laser and room temperat 2817:Src/main.c **** // As room temperature can be approximated as constant at current-varying time -- I should be kept 2818:Src/main.c **** // As current through laser diode heats it -- we can estimate excessive power on laser diode and t 2819:Src/main.c **** // So, equation should be look like this: 2820:Src/main.c **** // x_output = x_output_original + I(laser)*(a + (t - b)c) 2821:Src/main.c **** // t -- cycle phase 2822:Src/main.c **** // a,b,c -- constants 2823:Src/main.c **** // 2824:Src/main.c **** // How can we control laser diode temperature? 2825:Src/main.c **** // -- We can set laser to fixed current at the time we need to measure. 2826:Src/main.c **** // Then we should measure wavelength. 2827:Src/main.c **** // Calibration sequence: 2828:Src/main.c **** // 1) n 2829:Src/main.c **** 2830:Src/main.c **** 2831:Src/main.c **** 2832:Src/main.c **** int e_pid; 2833:Src/main.c **** float P_coef_current;//, I_coef_current; 2834:Src/main.c **** float e_integral; 2835:Src/main.c **** int x_output; 2836:Src/main.c **** 2837:Src/main.c **** e_pid = (int) LDx_results->LD_CURR_TEMP - (int) LDx_curr_setup->LD_TEMP; 2838:Src/main.c **** 2839:Src/main.c **** e_integral = LDx_results->e_integral; 2840:Src/main.c **** 2841:Src/main.c **** if((e_pid < 3000) && (e_pid > - 3000)){ 2842:Src/main.c **** e_integral += LDx_curr_setup->I_coef_temp * (float)(e_pid) * (float)(TO7 - TO7_PID) / (float) 100 2843:Src/main.c **** } 2844:Src/main.c **** P_coef_current = LDx_curr_setup->P_coef_temp; 2845:Src/main.c **** 2846:Src/main.c **** if (e_integral > 32000){ 2847:Src/main.c **** e_integral = 32000; 2848:Src/main.c **** } 2849:Src/main.c **** else if (e_integral < - 32000){ 2850:Src/main.c **** e_integral = -32000; 2851:Src/main.c **** } 2852:Src/main.c **** LDx_results->e_integral = e_integral; 2853:Src/main.c **** 2854:Src/main.c **** x_output = 32768 + P_coef_current * e_pid + (int)e_integral;//32768 - P_coef_current * e_pid - (in 2855:Src/main.c **** 2856:Src/main.c **** if(x_output < 1000){ 2857:Src/main.c **** x_output = 8800; 2858:Src/main.c **** } 2859:Src/main.c **** else if(x_output > 56800){ 2860:Src/main.c **** x_output = 56800; 2861:Src/main.c **** } 2862:Src/main.c **** 2863:Src/main.c **** if (num==2) 2864:Src/main.c **** TO7_PID = TO7;//Save current time only on 2nd laser ARM GAS /tmp/ccYgfTud.s page 103 2865:Src/main.c **** 2866:Src/main.c **** return (uint16_t)x_output; 2867:Src/main.c **** } 2868:Src/main.c **** 2869:Src/main.c **** 2870:Src/main.c **** uint16_t PID_Controller_Temp(LDx_SetupTypeDef * LDx_curr_setup, LDx_ParamTypeDef * LDx_results, uin 2871:Src/main.c **** { 545 .loc 1 2871 1 is_stmt 1 view -0 546 .cfi_startproc 547 @ args = 0, pretend = 0, frame = 0 548 @ frame_needed = 0, uses_anonymous_args = 0 549 @ link register save eliminated. 550 .loc 1 2871 1 is_stmt 0 view .LVU201 551 0000 30B4 push {r4, r5} 552 .LCFI6: 553 .cfi_def_cfa_offset 8 554 .cfi_offset 4, -8 555 .cfi_offset 5, -4 2872:Src/main.c **** int e_pid; 556 .loc 1 2872 2 is_stmt 1 view .LVU202 2873:Src/main.c **** float P_coef_current;//, I_coef_current; 557 .loc 1 2873 2 view .LVU203 2874:Src/main.c **** float e_integral; 558 .loc 1 2874 2 view .LVU204 2875:Src/main.c **** int x_output; 559 .loc 1 2875 2 view .LVU205 2876:Src/main.c **** 2877:Src/main.c **** e_pid = (int) LDx_results->LD_CURR_TEMP - (int) LDx_curr_setup->LD_TEMP; 560 .loc 1 2877 2 view .LVU206 561 .loc 1 2877 28 is_stmt 0 view .LVU207 562 0002 0B88 ldrh r3, [r1] 563 .loc 1 2877 65 view .LVU208 564 0004 0488 ldrh r4, [r0] 565 .loc 1 2877 8 view .LVU209 566 0006 1B1B subs r3, r3, r4 567 .LVL34: 2878:Src/main.c **** 2879:Src/main.c **** e_integral = LDx_results->e_integral; 568 .loc 1 2879 2 is_stmt 1 view .LVU210 569 .loc 1 2879 13 is_stmt 0 view .LVU211 570 0008 D1ED017A vldr.32 s15, [r1, #4] 571 .LVL35: 2880:Src/main.c **** 2881:Src/main.c **** if((e_pid < 3000) && (e_pid > - 3000)){ 572 .loc 1 2881 2 is_stmt 1 view .LVU212 573 .loc 1 2881 20 is_stmt 0 view .LVU213 574 000c 03F6B73C addw ip, r3, #2999 575 .loc 1 2881 4 view .LVU214 576 0010 41F26E74 movw r4, #5998 577 0014 A445 cmp ip, r4 578 0016 18D8 bhi .L17 2882:Src/main.c **** e_integral += LDx_curr_setup->I_coef_temp * (float)(e_pid) * (float)(TO7 - TO7_PID) / (float) 100 579 .loc 1 2882 3 is_stmt 1 view .LVU215 580 .loc 1 2882 31 is_stmt 0 view .LVU216 581 0018 90ED027A vldr.32 s14, [r0, #8] 582 .loc 1 2882 47 view .LVU217 583 001c 06EE903A vmov s13, r3 @ int ARM GAS /tmp/ccYgfTud.s page 104 584 0020 F8EEE66A vcvt.f32.s32 s13, s13 585 .loc 1 2882 45 view .LVU218 586 0024 27EE267A vmul.f32 s14, s14, s13 587 .loc 1 2882 76 view .LVU219 588 0028 284C ldr r4, .L27 589 002a 2468 ldr r4, [r4] 590 002c 284D ldr r5, .L27+4 591 002e 2D68 ldr r5, [r5] 592 0030 641B subs r4, r4, r5 593 .loc 1 2882 64 view .LVU220 594 0032 06EE904A vmov s13, r4 @ int 595 0036 F8EE666A vcvt.f32.u32 s13, s13 596 .loc 1 2882 62 view .LVU221 597 003a 27EE267A vmul.f32 s14, s14, s13 598 .loc 1 2882 87 view .LVU222 599 003e 9FED256A vldr.32 s12, .L27+8 600 0042 C7EE066A vdiv.f32 s13, s14, s12 601 .loc 1 2882 14 view .LVU223 602 0046 77EEA67A vadd.f32 s15, s15, s13 603 .LVL36: 604 .L17: 2883:Src/main.c **** } 2884:Src/main.c **** P_coef_current = LDx_curr_setup->P_coef_temp; 605 .loc 1 2884 2 is_stmt 1 view .LVU224 606 .loc 1 2884 17 is_stmt 0 view .LVU225 607 004a D0ED016A vldr.32 s13, [r0, #4] 608 .LVL37: 2885:Src/main.c **** 2886:Src/main.c **** if (e_integral > 32000){ 609 .loc 1 2886 2 is_stmt 1 view .LVU226 610 .loc 1 2886 5 is_stmt 0 view .LVU227 611 004e 9FED227A vldr.32 s14, .L27+12 612 0052 F4EEC77A vcmpe.f32 s15, s14 613 0056 F1EE10FA vmrs APSR_nzcv, FPSCR 614 005a 09DC bgt .L21 2887:Src/main.c **** e_integral = 32000; 2888:Src/main.c **** } 2889:Src/main.c **** else if (e_integral < - 32000){ 615 .loc 1 2889 7 is_stmt 1 view .LVU228 616 .loc 1 2889 10 is_stmt 0 view .LVU229 617 005c 9FED1F7A vldr.32 s14, .L27+16 618 0060 F4EEC77A vcmpe.f32 s15, s14 619 0064 F1EE10FA vmrs APSR_nzcv, FPSCR 620 0068 04D5 bpl .L18 2890:Src/main.c **** e_integral = -32000; 621 .loc 1 2890 15 view .LVU230 622 006a DFED1C7A vldr.32 s15, .L27+16 623 .LVL38: 624 .loc 1 2890 15 view .LVU231 625 006e 01E0 b .L18 626 .LVL39: 627 .L21: 2887:Src/main.c **** e_integral = 32000; 628 .loc 1 2887 15 view .LVU232 629 0070 DFED197A vldr.32 s15, .L27+12 630 .LVL40: 631 .L18: ARM GAS /tmp/ccYgfTud.s page 105 2891:Src/main.c **** } 2892:Src/main.c **** LDx_results->e_integral = e_integral; 632 .loc 1 2892 2 is_stmt 1 view .LVU233 633 .loc 1 2892 26 is_stmt 0 view .LVU234 634 0074 C1ED017A vstr.32 s15, [r1, #4] 2893:Src/main.c **** 2894:Src/main.c **** x_output = 32768 + P_coef_current * e_pid + (int)e_integral;//32768 - P_coef_current * e_pid - (in 635 .loc 1 2894 2 is_stmt 1 view .LVU235 636 .loc 1 2894 36 is_stmt 0 view .LVU236 637 0078 07EE103A vmov s14, r3 @ int 638 007c B8EEC77A vcvt.f32.s32 s14, s14 639 0080 27EE267A vmul.f32 s14, s14, s13 640 .loc 1 2894 19 view .LVU237 641 0084 DFED166A vldr.32 s13, .L27+20 642 .LVL41: 643 .loc 1 2894 19 view .LVU238 644 0088 37EE267A vadd.f32 s14, s14, s13 645 .loc 1 2894 46 view .LVU239 646 008c FDEEE77A vcvt.s32.f32 s15, s15 647 .LVL42: 648 .loc 1 2894 44 view .LVU240 649 0090 F8EEE77A vcvt.f32.s32 s15, s15 650 0094 77EE877A vadd.f32 s15, s15, s14 651 .loc 1 2894 11 view .LVU241 652 0098 FDEEE77A vcvt.s32.f32 s15, s15 653 009c 17EE900A vmov r0, s15 @ int 654 .LVL43: 2895:Src/main.c **** 2896:Src/main.c **** if(x_output < 1000){ 655 .loc 1 2896 2 is_stmt 1 view .LVU242 656 .loc 1 2896 4 is_stmt 0 view .LVU243 657 00a0 B0F57A7F cmp r0, #1000 658 00a4 06DB blt .L23 2897:Src/main.c **** x_output = 8800; 2898:Src/main.c **** } 2899:Src/main.c **** else if(x_output > 56800){ 659 .loc 1 2899 7 is_stmt 1 view .LVU244 660 .loc 1 2899 9 is_stmt 0 view .LVU245 661 00a6 4DF6E053 movw r3, #56800 662 .LVL44: 663 .loc 1 2899 9 view .LVU246 664 00aa 9842 cmp r0, r3 665 00ac 04DD ble .L19 2900:Src/main.c **** x_output = 56800; 666 .loc 1 2900 12 view .LVU247 667 00ae 4DF6E050 movw r0, #56800 668 .LVL45: 669 .loc 1 2900 12 view .LVU248 670 00b2 01E0 b .L19 671 .LVL46: 672 .L23: 2897:Src/main.c **** x_output = 8800; 673 .loc 1 2897 12 view .LVU249 674 00b4 42F26020 movw r0, #8800 675 .LVL47: 676 .L19: 2901:Src/main.c **** } ARM GAS /tmp/ccYgfTud.s page 106 2902:Src/main.c **** 2903:Src/main.c **** if (num==2) 677 .loc 1 2903 2 is_stmt 1 view .LVU250 678 .loc 1 2903 5 is_stmt 0 view .LVU251 679 00b8 022A cmp r2, #2 680 00ba 02D0 beq .L26 681 .LVL48: 682 .L20: 2904:Src/main.c **** TO7_PID = TO7;//Save current time only on 2nd laser 2905:Src/main.c **** 2906:Src/main.c **** return (uint16_t)x_output; 683 .loc 1 2906 2 is_stmt 1 view .LVU252 2907:Src/main.c **** } 684 .loc 1 2907 1 is_stmt 0 view .LVU253 685 00bc 80B2 uxth r0, r0 686 .LVL49: 687 .loc 1 2907 1 view .LVU254 688 00be 30BC pop {r4, r5} 689 .LCFI7: 690 .cfi_remember_state 691 .cfi_restore 5 692 .cfi_restore 4 693 .cfi_def_cfa_offset 0 694 00c0 7047 bx lr 695 .LVL50: 696 .L26: 697 .LCFI8: 698 .cfi_restore_state 2904:Src/main.c **** TO7_PID = TO7;//Save current time only on 2nd laser 699 .loc 1 2904 3 is_stmt 1 view .LVU255 2904:Src/main.c **** TO7_PID = TO7;//Save current time only on 2nd laser 700 .loc 1 2904 11 is_stmt 0 view .LVU256 701 00c2 024B ldr r3, .L27 702 00c4 1A68 ldr r2, [r3] 703 .LVL51: 2904:Src/main.c **** TO7_PID = TO7;//Save current time only on 2nd laser 704 .loc 1 2904 11 view .LVU257 705 00c6 024B ldr r3, .L27+4 706 00c8 1A60 str r2, [r3] 707 00ca F7E7 b .L20 708 .L28: 709 .align 2 710 .L27: 711 00cc 00000000 .word TO7 712 00d0 00000000 .word TO7_PID 713 00d4 0000C842 .word 1120403456 714 00d8 0000FA46 .word 1190789120 715 00dc 0000FAC6 .word -956694528 716 00e0 00000047 .word 1191182336 717 .cfi_endproc 718 .LFE1221: 720 .section .text.AD9102_WriteReg,"ax",%progbits 721 .align 1 722 .syntax unified 723 .thumb 724 .thumb_func 726 AD9102_WriteReg: ARM GAS /tmp/ccYgfTud.s page 107 727 .LVL52: 728 .LFB1212: 2415:Src/main.c **** uint32_t tmp32 = 0; 729 .loc 1 2415 1 is_stmt 1 view -0 730 .cfi_startproc 731 @ args = 0, pretend = 0, frame = 0 732 @ frame_needed = 0, uses_anonymous_args = 0 2415:Src/main.c **** uint32_t tmp32 = 0; 733 .loc 1 2415 1 is_stmt 0 view .LVU259 734 0000 38B5 push {r3, r4, r5, lr} 735 .LCFI9: 736 .cfi_def_cfa_offset 16 737 .cfi_offset 3, -16 738 .cfi_offset 4, -12 739 .cfi_offset 5, -8 740 .cfi_offset 14, -4 741 0002 0C46 mov r4, r1 2416:Src/main.c **** uint16_t cmd = (uint16_t)(addr & 0x7FFFu); // R/W = 0 (write), 15-bit address 742 .loc 1 2416 2 is_stmt 1 view .LVU260 743 .LVL53: 2417:Src/main.c **** 744 .loc 1 2417 2 view .LVU261 2417:Src/main.c **** 745 .loc 1 2417 11 is_stmt 0 view .LVU262 746 0004 C0F30E05 ubfx r5, r0, #0, #15 747 .LVL54: 2419:Src/main.c **** { 748 .loc 1 2419 2 is_stmt 1 view .LVU263 749 .LBB337: 750 .LBI337: 751 .file 4 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h" 1:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 2:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** ****************************************************************************** 3:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @file stm32f7xx_ll_spi.h 4:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @author MCD Application Team 5:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Header file of SPI LL module. 6:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** ****************************************************************************** 7:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @attention 8:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * 9:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * Copyright (c) 2017 STMicroelectronics. 10:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * All rights reserved. 11:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * 12:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * This software is licensed under terms that can be found in the LICENSE file 13:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * in the root directory of this software component. 14:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * If no LICENSE file comes with this software, it is provided AS-IS. 15:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * 16:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** ****************************************************************************** 17:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 18:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 19:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /* Define to prevent recursive inclusion -------------------------------------*/ 20:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #ifndef STM32F7xx_LL_SPI_H 21:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define STM32F7xx_LL_SPI_H 22:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 23:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #ifdef __cplusplus 24:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** extern "C" { 25:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #endif 26:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** ARM GAS /tmp/ccYgfTud.s page 108 27:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /* Includes ------------------------------------------------------------------*/ 28:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #include "stm32f7xx.h" 29:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 30:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @addtogroup STM32F7xx_LL_Driver 31:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @{ 32:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 33:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 34:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #if defined (SPI1) || defined (SPI2) || defined (SPI3) || defined (SPI4) || defined (SPI5) || defin 35:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 36:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL SPI 37:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @{ 38:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 39:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 40:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /* Private types -------------------------------------------------------------*/ 41:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /* Private variables ---------------------------------------------------------*/ 42:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /* Private macros ------------------------------------------------------------*/ 43:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 44:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /* Exported types ------------------------------------------------------------*/ 45:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #if defined(USE_FULL_LL_DRIVER) 46:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_ES_INIT SPI Exported Init structure 47:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @{ 48:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 49:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 50:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 51:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief SPI Init structures definition 52:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 53:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** typedef struct 54:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 55:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** uint32_t TransferDirection; /*!< Specifies the SPI unidirectional or bidirectional data mod 56:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** This parameter can be a value of @ref SPI_LL_EC_TRANSFER_M 57:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 58:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** This feature can be modified afterwards using unitary func 59:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 60:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** uint32_t Mode; /*!< Specifies the SPI mode (Master/Slave). 61:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** This parameter can be a value of @ref SPI_LL_EC_MODE. 62:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 63:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** This feature can be modified afterwards using unitary func 64:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 65:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** uint32_t DataWidth; /*!< Specifies the SPI data width. 66:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** This parameter can be a value of @ref SPI_LL_EC_DATAWIDTH. 67:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 68:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** This feature can be modified afterwards using unitary func 69:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 70:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** uint32_t ClockPolarity; /*!< Specifies the serial clock steady state. 71:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** This parameter can be a value of @ref SPI_LL_EC_POLARITY. 72:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 73:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** This feature can be modified afterwards using unitary func 74:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 75:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** uint32_t ClockPhase; /*!< Specifies the clock active edge for the bit capture. 76:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** This parameter can be a value of @ref SPI_LL_EC_PHASE. 77:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 78:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** This feature can be modified afterwards using unitary func 79:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 80:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** uint32_t NSS; /*!< Specifies whether the NSS signal is managed by hardware (N 81:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** This parameter can be a value of @ref SPI_LL_EC_NSS_MODE. 82:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 83:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** This feature can be modified afterwards using unitary func ARM GAS /tmp/ccYgfTud.s page 109 84:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 85:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** uint32_t BaudRate; /*!< Specifies the BaudRate prescaler value which will be used 86:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** This parameter can be a value of @ref SPI_LL_EC_BAUDRATEPR 87:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** @note The communication clock is derived from the master c 88:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 89:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** This feature can be modified afterwards using unitary func 90:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 91:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** uint32_t BitOrder; /*!< Specifies whether data transfers start from MSB or LSB bit 92:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** This parameter can be a value of @ref SPI_LL_EC_BIT_ORDER. 93:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 94:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** This feature can be modified afterwards using unitary func 95:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 96:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** uint32_t CRCCalculation; /*!< Specifies if the CRC calculation is enabled or not. 97:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** This parameter can be a value of @ref SPI_LL_EC_CRC_CALCUL 98:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 99:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** This feature can be modified afterwards using unitary func 100:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 101:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** uint32_t CRCPoly; /*!< Specifies the polynomial used for the CRC calculation. 102:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** This parameter must be a number between Min_Data = 0x00 an 103:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 104:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** This feature can be modified afterwards using unitary func 105:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 106:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } LL_SPI_InitTypeDef; 107:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 108:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 109:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @} 110:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 111:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #endif /* USE_FULL_LL_DRIVER */ 112:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 113:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /* Exported constants --------------------------------------------------------*/ 114:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_Exported_Constants SPI Exported Constants 115:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @{ 116:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 117:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 118:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_EC_GET_FLAG Get Flags Defines 119:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Flags defines which can be used with LL_SPI_ReadReg function 120:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @{ 121:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 122:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_SR_RXNE SPI_SR_RXNE /*!< Rx buffer not empty flag 123:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_SR_TXE SPI_SR_TXE /*!< Tx buffer empty flag 124:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_SR_BSY SPI_SR_BSY /*!< Busy flag 125:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_SR_CRCERR SPI_SR_CRCERR /*!< CRC error flag 126:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_SR_MODF SPI_SR_MODF /*!< Mode fault flag 127:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_SR_OVR SPI_SR_OVR /*!< Overrun flag 128:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_SR_FRE SPI_SR_FRE /*!< TI mode frame format erro 129:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 130:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @} 131:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 132:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 133:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_EC_IT IT Defines 134:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief IT defines which can be used with LL_SPI_ReadReg and LL_SPI_WriteReg functions 135:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @{ 136:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 137:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_CR2_RXNEIE SPI_CR2_RXNEIE /*!< Rx buffer not empty inter 138:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_CR2_TXEIE SPI_CR2_TXEIE /*!< Tx buffer empty interrupt 139:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_CR2_ERRIE SPI_CR2_ERRIE /*!< Error interrupt enable 140:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** ARM GAS /tmp/ccYgfTud.s page 110 141:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @} 142:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 143:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 144:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_EC_MODE Operation Mode 145:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @{ 146:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 147:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_MODE_MASTER (SPI_CR1_MSTR | SPI_CR1_SSI) /*!< Master configuratio 148:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_MODE_SLAVE 0x00000000U /*!< Slave configuration 149:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 150:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @} 151:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 152:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 153:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_EC_PROTOCOL Serial Protocol 154:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @{ 155:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 156:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_PROTOCOL_MOTOROLA 0x00000000U /*!< Motorola mode. Used as de 157:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_PROTOCOL_TI (SPI_CR2_FRF) /*!< TI mode 158:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 159:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @} 160:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 161:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 162:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_EC_PHASE Clock Phase 163:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @{ 164:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 165:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_PHASE_1EDGE 0x00000000U /*!< First clock transition is 166:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_PHASE_2EDGE (SPI_CR1_CPHA) /*!< Second clock transition i 167:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 168:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @} 169:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 170:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 171:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_EC_POLARITY Clock Polarity 172:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @{ 173:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 174:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_POLARITY_LOW 0x00000000U /*!< Clock to 0 when idle */ 175:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_POLARITY_HIGH (SPI_CR1_CPOL) /*!< Clock to 1 when idle */ 176:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 177:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @} 178:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 179:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 180:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_EC_BAUDRATEPRESCALER Baud Rate Prescaler 181:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @{ 182:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 183:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_BAUDRATEPRESCALER_DIV2 0x00000000U /*!< Baud 184:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_BAUDRATEPRESCALER_DIV4 (SPI_CR1_BR_0) /*!< Baud 185:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_BAUDRATEPRESCALER_DIV8 (SPI_CR1_BR_1) /*!< Baud 186:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_BAUDRATEPRESCALER_DIV16 (SPI_CR1_BR_1 | SPI_CR1_BR_0) /*!< Baud 187:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_BAUDRATEPRESCALER_DIV32 (SPI_CR1_BR_2) /*!< Baud 188:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_BAUDRATEPRESCALER_DIV64 (SPI_CR1_BR_2 | SPI_CR1_BR_0) /*!< Baud 189:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_BAUDRATEPRESCALER_DIV128 (SPI_CR1_BR_2 | SPI_CR1_BR_1) /*!< Baud 190:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_BAUDRATEPRESCALER_DIV256 (SPI_CR1_BR_2 | SPI_CR1_BR_1 | SPI_CR1_BR_0) /*!< Baud 191:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 192:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @} 193:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 194:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 195:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_EC_BIT_ORDER Transmission Bit Order 196:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @{ 197:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ ARM GAS /tmp/ccYgfTud.s page 111 198:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_LSB_FIRST (SPI_CR1_LSBFIRST) /*!< Data is transmitted/recei 199:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_MSB_FIRST 0x00000000U /*!< Data is transmitted/recei 200:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 201:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @} 202:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 203:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 204:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_EC_TRANSFER_MODE Transfer Mode 205:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @{ 206:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 207:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_FULL_DUPLEX 0x00000000U /*!< Full-Duplex mo 208:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_SIMPLEX_RX (SPI_CR1_RXONLY) /*!< Simplex Rx mod 209:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_HALF_DUPLEX_RX (SPI_CR1_BIDIMODE) /*!< Half-Duplex Rx 210:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_HALF_DUPLEX_TX (SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE) /*!< Half-Duplex Tx 211:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 212:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @} 213:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 214:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 215:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_EC_NSS_MODE Slave Select Pin Mode 216:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @{ 217:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 218:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_NSS_SOFT (SPI_CR1_SSM) /*!< NSS managed inter 219:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_NSS_HARD_INPUT 0x00000000U /*!< NSS pin used in I 220:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_NSS_HARD_OUTPUT (((uint32_t)SPI_CR2_SSOE << 16U)) /*!< NSS pin used in O 221:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 222:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @} 223:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 224:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 225:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_EC_DATAWIDTH Datawidth 226:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @{ 227:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 228:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_DATAWIDTH_4BIT (SPI_CR2_DS_0 | SPI_CR2_DS_1) 229:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_DATAWIDTH_5BIT (SPI_CR2_DS_2) 230:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_DATAWIDTH_6BIT (SPI_CR2_DS_2 | SPI_CR2_DS_0) 231:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_DATAWIDTH_7BIT (SPI_CR2_DS_2 | SPI_CR2_DS_1) 232:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_DATAWIDTH_8BIT (SPI_CR2_DS_2 | SPI_CR2_DS_1 | SPI_CR2_DS_0) 233:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_DATAWIDTH_9BIT (SPI_CR2_DS_3) 234:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_DATAWIDTH_10BIT (SPI_CR2_DS_3 | SPI_CR2_DS_0) 235:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_DATAWIDTH_11BIT (SPI_CR2_DS_3 | SPI_CR2_DS_1) 236:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_DATAWIDTH_12BIT (SPI_CR2_DS_3 | SPI_CR2_DS_1 | SPI_CR2_DS_0) 237:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_DATAWIDTH_13BIT (SPI_CR2_DS_3 | SPI_CR2_DS_2) 238:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_DATAWIDTH_14BIT (SPI_CR2_DS_3 | SPI_CR2_DS_2 | SPI_CR2_DS_0) 239:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_DATAWIDTH_15BIT (SPI_CR2_DS_3 | SPI_CR2_DS_2 | SPI_CR2_DS_1) 240:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_DATAWIDTH_16BIT (SPI_CR2_DS_3 | SPI_CR2_DS_2 | SPI_CR2_DS_1 | SPI_CR2_DS 241:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 242:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @} 243:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 244:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #if defined(USE_FULL_LL_DRIVER) 245:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 246:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_EC_CRC_CALCULATION CRC Calculation 247:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @{ 248:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 249:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_CRCCALCULATION_DISABLE 0x00000000U /*!< CRC calculation disabled 250:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_CRCCALCULATION_ENABLE (SPI_CR1_CRCEN) /*!< CRC calculation enabled 251:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 252:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @} 253:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 254:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #endif /* USE_FULL_LL_DRIVER */ ARM GAS /tmp/ccYgfTud.s page 112 255:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 256:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_EC_CRC_LENGTH CRC Length 257:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @{ 258:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 259:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_CRC_8BIT 0x00000000U /*!< 8-bit CRC length */ 260:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_CRC_16BIT (SPI_CR1_CRCL) /*!< 16-bit CRC length */ 261:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 262:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @} 263:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 264:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 265:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_EC_RX_FIFO_TH RX FIFO Threshold 266:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @{ 267:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 268:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_RX_FIFO_TH_HALF 0x00000000U /*!< RXNE event is generated i 269:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_RX_FIFO_TH_QUARTER (SPI_CR2_FRXTH) /*!< RXNE event is generated i 270:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 271:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @} 272:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 273:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 274:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_EC_RX_FIFO RX FIFO Level 275:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @{ 276:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 277:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_RX_FIFO_EMPTY 0x00000000U /*!< FIFO reception em 278:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_RX_FIFO_QUARTER_FULL (SPI_SR_FRLVL_0) /*!< FIFO reception 1/ 279:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_RX_FIFO_HALF_FULL (SPI_SR_FRLVL_1) /*!< FIFO reception 1/ 280:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_RX_FIFO_FULL (SPI_SR_FRLVL_1 | SPI_SR_FRLVL_0) /*!< FIFO reception fu 281:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 282:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @} 283:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 284:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 285:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_EC_TX_FIFO TX FIFO Level 286:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @{ 287:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 288:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_TX_FIFO_EMPTY 0x00000000U /*!< FIFO transmission 289:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_TX_FIFO_QUARTER_FULL (SPI_SR_FTLVL_0) /*!< FIFO transmission 290:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_TX_FIFO_HALF_FULL (SPI_SR_FTLVL_1) /*!< FIFO transmission 291:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_TX_FIFO_FULL (SPI_SR_FTLVL_1 | SPI_SR_FTLVL_0) /*!< FIFO transmission 292:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 293:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @} 294:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 295:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 296:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_EC_DMA_PARITY DMA Parity 297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @{ 298:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 299:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_DMA_PARITY_EVEN 0x00000000U /*!< Select DMA parity Even */ 300:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_DMA_PARITY_ODD 0x00000001U /*!< Select DMA parity Odd */ 301:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 302:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 303:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @} 304:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 305:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 306:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 307:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @} 308:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 309:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 310:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /* Exported macro ------------------------------------------------------------*/ 311:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_Exported_Macros SPI Exported Macros ARM GAS /tmp/ccYgfTud.s page 113 312:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @{ 313:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_EM_WRITE_READ Common Write and read registers Macros 316:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @{ 317:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 318:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 319:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 320:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Write a value in SPI register 321:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param __INSTANCE__ SPI Instance 322:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param __REG__ Register to be written 323:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param __VALUE__ Value to be written in the register 324:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None 325:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 326:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE 327:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 328:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 329:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Read a value in SPI register 330:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param __INSTANCE__ SPI Instance 331:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param __REG__ Register to be read 332:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval Register value 333:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 334:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) 335:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 336:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @} 337:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 338:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 339:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 340:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @} 341:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 342:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 343:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /* Exported functions --------------------------------------------------------*/ 344:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_Exported_Functions SPI Exported Functions 345:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @{ 346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 347:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 348:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_EF_Configuration Configuration 349:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @{ 350:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 351:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 352:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 353:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Enable SPI peripheral 354:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR1 SPE LL_SPI_Enable 355:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 356:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None 357:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 358:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_Enable(SPI_TypeDef *SPIx) 359:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** SET_BIT(SPIx->CR1, SPI_CR1_SPE); 361:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 362:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 363:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 364:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Disable SPI peripheral 365:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @note When disabling the SPI, follow the procedure described in the Reference Manual. 366:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR1 SPE LL_SPI_Disable 367:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 368:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None ARM GAS /tmp/ccYgfTud.s page 114 369:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_Disable(SPI_TypeDef *SPIx) 371:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE); 373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 374:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 375:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 376:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Check if SPI peripheral is enabled 377:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR1 SPE LL_SPI_IsEnabled 378:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 379:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval State of bit (1 or 0). 380:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 381:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_IsEnabled(SPI_TypeDef *SPIx) 752 .loc 4 381 26 view .LVU264 753 .LBB338: 382:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 383:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** return ((READ_BIT(SPIx->CR1, SPI_CR1_SPE) == (SPI_CR1_SPE)) ? 1UL : 0UL); 754 .loc 4 383 3 view .LVU265 755 .loc 4 383 12 is_stmt 0 view .LVU266 756 0008 274B ldr r3, .L44 757 000a 1B68 ldr r3, [r3] 758 .loc 4 383 69 view .LVU267 759 000c 13F0400F tst r3, #64 760 0010 04D1 bne .L30 761 .LVL55: 762 .loc 4 383 69 view .LVU268 763 .LBE338: 764 .LBE337: 2421:Src/main.c **** } 765 .loc 1 2421 3 is_stmt 1 view .LVU269 766 .LBB339: 767 .LBI339: 358:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 768 .loc 4 358 22 view .LVU270 769 .LBB340: 360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 770 .loc 4 360 3 view .LVU271 771 0012 254A ldr r2, .L44 772 0014 1368 ldr r3, [r2] 773 0016 43F04003 orr r3, r3, #64 774 001a 1360 str r3, [r2] 775 .LVL56: 776 .L30: 360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 777 .loc 4 360 3 is_stmt 0 view .LVU272 778 .LBE340: 779 .LBE339: 2424:Src/main.c **** 780 .loc 1 2424 2 is_stmt 1 view .LVU273 781 001c 0022 movs r2, #0 782 001e 4FF48051 mov r1, #4096 783 .LVL57: 2424:Src/main.c **** 784 .loc 1 2424 2 is_stmt 0 view .LVU274 785 0022 2248 ldr r0, .L44+4 786 .LVL58: 2424:Src/main.c **** ARM GAS /tmp/ccYgfTud.s page 115 787 .loc 1 2424 2 view .LVU275 788 0024 FFF7FEFF bl HAL_GPIO_WritePin 789 .LVL59: 2426:Src/main.c **** LL_SPI_TransmitData16(SPI2, cmd); 790 .loc 1 2426 2 is_stmt 1 view .LVU276 2416:Src/main.c **** uint16_t cmd = (uint16_t)(addr & 0x7FFFu); // R/W = 0 (write), 15-bit address 791 .loc 1 2416 11 is_stmt 0 view .LVU277 792 0028 0023 movs r3, #0 793 .LVL60: 794 .L32: 2426:Src/main.c **** LL_SPI_TransmitData16(SPI2, cmd); 795 .loc 1 2426 63 is_stmt 1 discriminator 2 view .LVU278 2426:Src/main.c **** LL_SPI_TransmitData16(SPI2, cmd); 796 .loc 1 2426 41 discriminator 2 view .LVU279 797 .LBB341: 798 .LBI341: 384:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 385:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 386:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 387:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Set SPI operation mode to Master or Slave 388:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @note This bit should not be changed when communication is ongoing. 389:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR1 MSTR LL_SPI_SetMode\n 390:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * CR1 SSI LL_SPI_SetMode 391:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 392:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param Mode This parameter can be one of the following values: 393:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_MODE_MASTER 394:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_MODE_SLAVE 395:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None 396:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 397:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_SetMode(SPI_TypeDef *SPIx, uint32_t Mode) 398:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 399:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** MODIFY_REG(SPIx->CR1, SPI_CR1_MSTR | SPI_CR1_SSI, Mode); 400:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 401:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 402:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 403:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Get SPI operation mode (Master or Slave) 404:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR1 MSTR LL_SPI_GetMode\n 405:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * CR1 SSI LL_SPI_GetMode 406:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 407:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval Returned value can be one of the following values: 408:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_MODE_MASTER 409:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_MODE_SLAVE 410:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 411:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_GetMode(SPI_TypeDef *SPIx) 412:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 413:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_MSTR | SPI_CR1_SSI)); 414:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 415:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 416:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 417:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Set serial protocol used 418:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation. 419:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR2 FRF LL_SPI_SetStandard 420:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 421:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param Standard This parameter can be one of the following values: 422:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_PROTOCOL_MOTOROLA 423:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_PROTOCOL_TI 424:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None ARM GAS /tmp/ccYgfTud.s page 116 425:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 426:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_SetStandard(SPI_TypeDef *SPIx, uint32_t Standard) 427:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** MODIFY_REG(SPIx->CR2, SPI_CR2_FRF, Standard); 429:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 430:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 431:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 432:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Get serial protocol used 433:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR2 FRF LL_SPI_GetStandard 434:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 435:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval Returned value can be one of the following values: 436:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_PROTOCOL_MOTOROLA 437:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_PROTOCOL_TI 438:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 439:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_GetStandard(SPI_TypeDef *SPIx) 440:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 441:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_FRF)); 442:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 443:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 444:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 445:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Set clock phase 446:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @note This bit should not be changed when communication is ongoing. 447:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * This bit is not used in SPI TI mode. 448:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR1 CPHA LL_SPI_SetClockPhase 449:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 450:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param ClockPhase This parameter can be one of the following values: 451:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_PHASE_1EDGE 452:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_PHASE_2EDGE 453:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None 454:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 455:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_SetClockPhase(SPI_TypeDef *SPIx, uint32_t ClockPhase) 456:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 457:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** MODIFY_REG(SPIx->CR1, SPI_CR1_CPHA, ClockPhase); 458:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 459:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 460:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 461:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Get clock phase 462:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR1 CPHA LL_SPI_GetClockPhase 463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 464:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval Returned value can be one of the following values: 465:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_PHASE_1EDGE 466:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_PHASE_2EDGE 467:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 468:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_GetClockPhase(SPI_TypeDef *SPIx) 469:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 470:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPHA)); 471:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 472:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 473:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 474:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Set clock polarity 475:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @note This bit should not be changed when communication is ongoing. 476:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * This bit is not used in SPI TI mode. 477:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR1 CPOL LL_SPI_SetClockPolarity 478:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 479:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param ClockPolarity This parameter can be one of the following values: 480:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_POLARITY_LOW 481:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_POLARITY_HIGH ARM GAS /tmp/ccYgfTud.s page 117 482:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None 483:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 484:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPolarity) 485:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 486:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** MODIFY_REG(SPIx->CR1, SPI_CR1_CPOL, ClockPolarity); 487:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 488:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 489:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 490:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Get clock polarity 491:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR1 CPOL LL_SPI_GetClockPolarity 492:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 493:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval Returned value can be one of the following values: 494:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_POLARITY_LOW 495:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_POLARITY_HIGH 496:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 497:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_GetClockPolarity(SPI_TypeDef *SPIx) 498:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 499:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPOL)); 500:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 501:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 502:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 503:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Set baud rate prescaler 504:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @note These bits should not be changed when communication is ongoing. SPI BaudRate = fPCLK/Pr 505:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR1 BR LL_SPI_SetBaudRatePrescaler 506:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 507:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param BaudRate This parameter can be one of the following values: 508:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2 509:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4 510:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8 511:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16 512:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32 513:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64 514:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128 515:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256 516:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None 517:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 518:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_SetBaudRatePrescaler(SPI_TypeDef *SPIx, uint32_t BaudRate) 519:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 520:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** MODIFY_REG(SPIx->CR1, SPI_CR1_BR, BaudRate); 521:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 522:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 523:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 524:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Get baud rate prescaler 525:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR1 BR LL_SPI_GetBaudRatePrescaler 526:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 527:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval Returned value can be one of the following values: 528:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2 529:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4 530:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8 531:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16 532:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32 533:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64 534:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128 535:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256 536:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 537:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_GetBaudRatePrescaler(SPI_TypeDef *SPIx) 538:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { ARM GAS /tmp/ccYgfTud.s page 118 539:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_BR)); 540:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 541:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 542:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 543:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Set transfer bit order 544:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @note This bit should not be changed when communication is ongoing. This bit is not used in S 545:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR1 LSBFIRST LL_SPI_SetTransferBitOrder 546:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 547:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param BitOrder This parameter can be one of the following values: 548:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_LSB_FIRST 549:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_MSB_FIRST 550:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None 551:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 552:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_SetTransferBitOrder(SPI_TypeDef *SPIx, uint32_t BitOrder) 553:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 554:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** MODIFY_REG(SPIx->CR1, SPI_CR1_LSBFIRST, BitOrder); 555:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 556:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 557:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 558:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Get transfer bit order 559:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR1 LSBFIRST LL_SPI_GetTransferBitOrder 560:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 561:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval Returned value can be one of the following values: 562:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_LSB_FIRST 563:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_MSB_FIRST 564:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 565:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_GetTransferBitOrder(SPI_TypeDef *SPIx) 566:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 567:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_LSBFIRST)); 568:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 569:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 570:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 571:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Set transfer direction mode 572:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @note For Half-Duplex mode, Rx Direction is set by default. 573:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * In master mode, the MOSI pin is used and in slave mode, the MISO pin is used for Half-D 574:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR1 RXONLY LL_SPI_SetTransferDirection\n 575:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * CR1 BIDIMODE LL_SPI_SetTransferDirection\n 576:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * CR1 BIDIOE LL_SPI_SetTransferDirection 577:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 578:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param TransferDirection This parameter can be one of the following values: 579:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_FULL_DUPLEX 580:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_SIMPLEX_RX 581:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_HALF_DUPLEX_RX 582:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_HALF_DUPLEX_TX 583:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None 584:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 585:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_SetTransferDirection(SPI_TypeDef *SPIx, uint32_t TransferDirection) 586:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 587:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** MODIFY_REG(SPIx->CR1, SPI_CR1_RXONLY | SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE, TransferDirection); 588:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 589:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 590:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 591:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Get transfer direction mode 592:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR1 RXONLY LL_SPI_GetTransferDirection\n 593:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * CR1 BIDIMODE LL_SPI_GetTransferDirection\n 594:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * CR1 BIDIOE LL_SPI_GetTransferDirection 595:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance ARM GAS /tmp/ccYgfTud.s page 119 596:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval Returned value can be one of the following values: 597:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_FULL_DUPLEX 598:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_SIMPLEX_RX 599:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_HALF_DUPLEX_RX 600:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_HALF_DUPLEX_TX 601:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 602:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_GetTransferDirection(SPI_TypeDef *SPIx) 603:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 604:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_RXONLY | SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE)); 605:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 606:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 607:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 608:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Set frame data width 609:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR2 DS LL_SPI_SetDataWidth 610:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 611:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param DataWidth This parameter can be one of the following values: 612:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_DATAWIDTH_4BIT 613:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_DATAWIDTH_5BIT 614:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_DATAWIDTH_6BIT 615:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_DATAWIDTH_7BIT 616:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_DATAWIDTH_8BIT 617:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_DATAWIDTH_9BIT 618:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_DATAWIDTH_10BIT 619:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_DATAWIDTH_11BIT 620:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_DATAWIDTH_12BIT 621:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_DATAWIDTH_13BIT 622:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_DATAWIDTH_14BIT 623:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_DATAWIDTH_15BIT 624:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_DATAWIDTH_16BIT 625:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None 626:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 627:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_SetDataWidth(SPI_TypeDef *SPIx, uint32_t DataWidth) 628:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 629:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** MODIFY_REG(SPIx->CR2, SPI_CR2_DS, DataWidth); 630:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 631:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 632:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 633:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Get frame data width 634:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR2 DS LL_SPI_GetDataWidth 635:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 636:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval Returned value can be one of the following values: 637:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_DATAWIDTH_4BIT 638:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_DATAWIDTH_5BIT 639:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_DATAWIDTH_6BIT 640:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_DATAWIDTH_7BIT 641:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_DATAWIDTH_8BIT 642:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_DATAWIDTH_9BIT 643:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_DATAWIDTH_10BIT 644:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_DATAWIDTH_11BIT 645:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_DATAWIDTH_12BIT 646:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_DATAWIDTH_13BIT 647:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_DATAWIDTH_14BIT 648:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_DATAWIDTH_15BIT 649:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_DATAWIDTH_16BIT 650:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 651:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_GetDataWidth(SPI_TypeDef *SPIx) 652:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { ARM GAS /tmp/ccYgfTud.s page 120 653:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_DS)); 654:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 655:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 656:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 657:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Set threshold of RXFIFO that triggers an RXNE event 658:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR2 FRXTH LL_SPI_SetRxFIFOThreshold 659:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 660:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param Threshold This parameter can be one of the following values: 661:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_RX_FIFO_TH_HALF 662:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_RX_FIFO_TH_QUARTER 663:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None 664:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 665:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_SetRxFIFOThreshold(SPI_TypeDef *SPIx, uint32_t Threshold) 666:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 667:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** MODIFY_REG(SPIx->CR2, SPI_CR2_FRXTH, Threshold); 668:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 669:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 670:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 671:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Get threshold of RXFIFO that triggers an RXNE event 672:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR2 FRXTH LL_SPI_GetRxFIFOThreshold 673:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 674:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval Returned value can be one of the following values: 675:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_RX_FIFO_TH_HALF 676:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_RX_FIFO_TH_QUARTER 677:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 678:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_GetRxFIFOThreshold(SPI_TypeDef *SPIx) 679:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 680:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_FRXTH)); 681:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 682:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 683:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 684:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @} 685:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 686:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 687:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_EF_CRC_Management CRC Management 688:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @{ 689:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 690:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 691:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 692:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Enable CRC 693:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation. 694:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR1 CRCEN LL_SPI_EnableCRC 695:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 696:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None 697:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 698:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_EnableCRC(SPI_TypeDef *SPIx) 699:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 700:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** SET_BIT(SPIx->CR1, SPI_CR1_CRCEN); 701:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 702:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 703:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 704:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Disable CRC 705:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation. 706:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR1 CRCEN LL_SPI_DisableCRC 707:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 708:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None 709:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ ARM GAS /tmp/ccYgfTud.s page 121 710:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_DisableCRC(SPI_TypeDef *SPIx) 711:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 712:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** CLEAR_BIT(SPIx->CR1, SPI_CR1_CRCEN); 713:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 714:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 715:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 716:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Check if CRC is enabled 717:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation. 718:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR1 CRCEN LL_SPI_IsEnabledCRC 719:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 720:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval State of bit (1 or 0). 721:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 722:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_IsEnabledCRC(SPI_TypeDef *SPIx) 723:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 724:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** return ((READ_BIT(SPIx->CR1, SPI_CR1_CRCEN) == (SPI_CR1_CRCEN)) ? 1UL : 0UL); 725:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 726:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 727:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 728:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Set CRC Length 729:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation. 730:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR1 CRCL LL_SPI_SetCRCWidth 731:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 732:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param CRCLength This parameter can be one of the following values: 733:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_CRC_8BIT 734:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_CRC_16BIT 735:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None 736:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 737:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_SetCRCWidth(SPI_TypeDef *SPIx, uint32_t CRCLength) 738:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 739:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** MODIFY_REG(SPIx->CR1, SPI_CR1_CRCL, CRCLength); 740:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 741:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 742:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 743:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Get CRC Length 744:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR1 CRCL LL_SPI_GetCRCWidth 745:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 746:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval Returned value can be one of the following values: 747:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_CRC_8BIT 748:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_CRC_16BIT 749:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 750:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_GetCRCWidth(SPI_TypeDef *SPIx) 751:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 752:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CRCL)); 753:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 754:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 755:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 756:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Set CRCNext to transfer CRC on the line 757:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @note This bit has to be written as soon as the last data is written in the SPIx_DR register. 758:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR1 CRCNEXT LL_SPI_SetCRCNext 759:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 760:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None 761:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 762:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_SetCRCNext(SPI_TypeDef *SPIx) 763:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 764:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** SET_BIT(SPIx->CR1, SPI_CR1_CRCNEXT); 765:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 766:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** ARM GAS /tmp/ccYgfTud.s page 122 767:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 768:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Set polynomial for CRC calculation 769:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CRCPR CRCPOLY LL_SPI_SetCRCPolynomial 770:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 771:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param CRCPoly This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFF 772:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None 773:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 774:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_SetCRCPolynomial(SPI_TypeDef *SPIx, uint32_t CRCPoly) 775:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 776:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** WRITE_REG(SPIx->CRCPR, (uint16_t)CRCPoly); 777:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 778:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 779:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 780:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Get polynomial for CRC calculation 781:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CRCPR CRCPOLY LL_SPI_GetCRCPolynomial 782:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 783:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF 784:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 785:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_GetCRCPolynomial(SPI_TypeDef *SPIx) 786:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 787:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** return (uint32_t)(READ_REG(SPIx->CRCPR)); 788:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 789:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 790:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 791:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Get Rx CRC 792:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll RXCRCR RXCRC LL_SPI_GetRxCRC 793:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 794:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF 795:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 796:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_GetRxCRC(SPI_TypeDef *SPIx) 797:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 798:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** return (uint32_t)(READ_REG(SPIx->RXCRCR)); 799:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 800:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 801:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 802:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Get Tx CRC 803:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll TXCRCR TXCRC LL_SPI_GetTxCRC 804:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 805:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF 806:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 807:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_GetTxCRC(SPI_TypeDef *SPIx) 808:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 809:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** return (uint32_t)(READ_REG(SPIx->TXCRCR)); 810:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 811:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 812:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 813:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @} 814:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 815:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 816:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_EF_NSS_Management Slave Select Pin Management 817:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @{ 818:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 819:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 820:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 821:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Set NSS mode 822:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @note LL_SPI_NSS_SOFT Mode is not used in SPI TI mode. 823:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR1 SSM LL_SPI_SetNSSMode\n ARM GAS /tmp/ccYgfTud.s page 123 824:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR2 SSOE LL_SPI_SetNSSMode 825:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 826:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param NSS This parameter can be one of the following values: 827:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_NSS_SOFT 828:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_NSS_HARD_INPUT 829:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_NSS_HARD_OUTPUT 830:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None 831:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 832:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_SetNSSMode(SPI_TypeDef *SPIx, uint32_t NSS) 833:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 834:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** MODIFY_REG(SPIx->CR1, SPI_CR1_SSM, NSS); 835:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** MODIFY_REG(SPIx->CR2, SPI_CR2_SSOE, ((uint32_t)(NSS >> 16U))); 836:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 837:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 838:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 839:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Get NSS mode 840:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR1 SSM LL_SPI_GetNSSMode\n 841:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR2 SSOE LL_SPI_GetNSSMode 842:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 843:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval Returned value can be one of the following values: 844:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_NSS_SOFT 845:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_NSS_HARD_INPUT 846:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_NSS_HARD_OUTPUT 847:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 848:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_GetNSSMode(SPI_TypeDef *SPIx) 849:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 850:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** uint32_t Ssm = (READ_BIT(SPIx->CR1, SPI_CR1_SSM)); 851:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** uint32_t Ssoe = (READ_BIT(SPIx->CR2, SPI_CR2_SSOE) << 16U); 852:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** return (Ssm | Ssoe); 853:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 854:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 855:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 856:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Enable NSS pulse management 857:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @note This bit should not be changed when communication is ongoing. This bit is not used in S 858:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR2 NSSP LL_SPI_EnableNSSPulseMgt 859:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 860:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None 861:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 862:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_EnableNSSPulseMgt(SPI_TypeDef *SPIx) 863:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 864:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** SET_BIT(SPIx->CR2, SPI_CR2_NSSP); 865:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 866:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 867:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 868:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Disable NSS pulse management 869:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @note This bit should not be changed when communication is ongoing. This bit is not used in S 870:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR2 NSSP LL_SPI_DisableNSSPulseMgt 871:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 872:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None 873:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 874:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_DisableNSSPulseMgt(SPI_TypeDef *SPIx) 875:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 876:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** CLEAR_BIT(SPIx->CR2, SPI_CR2_NSSP); 877:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 878:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 879:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 880:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Check if NSS pulse is enabled ARM GAS /tmp/ccYgfTud.s page 124 881:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @note This bit should not be changed when communication is ongoing. This bit is not used in S 882:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR2 NSSP LL_SPI_IsEnabledNSSPulse 883:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 884:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval State of bit (1 or 0). 885:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 886:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_IsEnabledNSSPulse(SPI_TypeDef *SPIx) 887:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 888:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** return ((READ_BIT(SPIx->CR2, SPI_CR2_NSSP) == (SPI_CR2_NSSP)) ? 1UL : 0UL); 889:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 890:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 891:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 892:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @} 893:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 894:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 895:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_EF_FLAG_Management FLAG Management 896:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @{ 897:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 898:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 899:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 900:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Check if Rx buffer is not empty 901:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll SR RXNE LL_SPI_IsActiveFlag_RXNE 902:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 903:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval State of bit (1 or 0). 904:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 905:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXNE(SPI_TypeDef *SPIx) 906:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** return ((READ_BIT(SPIx->SR, SPI_SR_RXNE) == (SPI_SR_RXNE)) ? 1UL : 0UL); 908:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 909:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 910:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 911:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Check if Tx buffer is empty 912:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll SR TXE LL_SPI_IsActiveFlag_TXE 913:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 914:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval State of bit (1 or 0). 915:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 916:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXE(SPI_TypeDef *SPIx) 799 .loc 4 916 26 view .LVU280 800 .LBB342: 917:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** return ((READ_BIT(SPIx->SR, SPI_SR_TXE) == (SPI_SR_TXE)) ? 1UL : 0UL); 801 .loc 4 918 3 view .LVU281 802 .loc 4 918 12 is_stmt 0 view .LVU282 803 002a 1F4A ldr r2, .L44 804 002c 9268 ldr r2, [r2, #8] 805 .loc 4 918 66 view .LVU283 806 002e 12F0020F tst r2, #2 807 0032 05D1 bne .L31 808 .LVL61: 809 .loc 4 918 66 view .LVU284 810 .LBE342: 811 .LBE341: 2426:Src/main.c **** LL_SPI_TransmitData16(SPI2, cmd); 812 .loc 1 2426 50 discriminator 1 view .LVU285 813 0034 5A1C adds r2, r3, #1 814 .LVL62: 2426:Src/main.c **** LL_SPI_TransmitData16(SPI2, cmd); 815 .loc 1 2426 41 discriminator 1 view .LVU286 ARM GAS /tmp/ccYgfTud.s page 125 816 0036 B3F57A7F cmp r3, #1000 817 003a 01D2 bcs .L31 2426:Src/main.c **** LL_SPI_TransmitData16(SPI2, cmd); 818 .loc 1 2426 50 discriminator 1 view .LVU287 819 003c 1346 mov r3, r2 820 003e F4E7 b .L32 821 .LVL63: 822 .L31: 2427:Src/main.c **** tmp32 = 0; 823 .loc 1 2427 2 is_stmt 1 view .LVU288 824 .LBB343: 825 .LBI343: 919:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 920:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 921:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 922:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Get CRC error flag 923:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll SR CRCERR LL_SPI_IsActiveFlag_CRCERR 924:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 925:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval State of bit (1 or 0). 926:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 927:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_CRCERR(SPI_TypeDef *SPIx) 928:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 929:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** return ((READ_BIT(SPIx->SR, SPI_SR_CRCERR) == (SPI_SR_CRCERR)) ? 1UL : 0UL); 930:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 931:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 932:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 933:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Get mode fault error flag 934:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll SR MODF LL_SPI_IsActiveFlag_MODF 935:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 936:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval State of bit (1 or 0). 937:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 938:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_MODF(SPI_TypeDef *SPIx) 939:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 940:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** return ((READ_BIT(SPIx->SR, SPI_SR_MODF) == (SPI_SR_MODF)) ? 1UL : 0UL); 941:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 942:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 943:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 944:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Get overrun error flag 945:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll SR OVR LL_SPI_IsActiveFlag_OVR 946:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 947:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval State of bit (1 or 0). 948:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 949:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_OVR(SPI_TypeDef *SPIx) 950:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 951:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** return ((READ_BIT(SPIx->SR, SPI_SR_OVR) == (SPI_SR_OVR)) ? 1UL : 0UL); 952:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 953:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 954:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 955:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Get busy flag 956:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @note The BSY flag is cleared under any one of the following conditions: 957:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * -When the SPI is correctly disabled 958:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * -When a fault is detected in Master mode (MODF bit set to 1) 959:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * -In Master mode, when it finishes a data transmission and no new data is ready to be 960:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * sent 961:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * -In Slave mode, when the BSY flag is set to '0' for at least one SPI clock cycle between 962:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * each data transfer. 963:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll SR BSY LL_SPI_IsActiveFlag_BSY ARM GAS /tmp/ccYgfTud.s page 126 964:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 965:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval State of bit (1 or 0). 966:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 967:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_BSY(SPI_TypeDef *SPIx) 968:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 969:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** return ((READ_BIT(SPIx->SR, SPI_SR_BSY) == (SPI_SR_BSY)) ? 1UL : 0UL); 970:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 971:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 972:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 973:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Get frame format error flag 974:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll SR FRE LL_SPI_IsActiveFlag_FRE 975:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 976:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval State of bit (1 or 0). 977:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 978:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_FRE(SPI_TypeDef *SPIx) 979:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 980:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** return ((READ_BIT(SPIx->SR, SPI_SR_FRE) == (SPI_SR_FRE)) ? 1UL : 0UL); 981:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 982:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 983:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 984:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Get FIFO reception Level 985:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll SR FRLVL LL_SPI_GetRxFIFOLevel 986:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 987:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval Returned value can be one of the following values: 988:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_RX_FIFO_EMPTY 989:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_RX_FIFO_QUARTER_FULL 990:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_RX_FIFO_HALF_FULL 991:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_RX_FIFO_FULL 992:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 993:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_GetRxFIFOLevel(SPI_TypeDef *SPIx) 994:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 995:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** return (uint32_t)(READ_BIT(SPIx->SR, SPI_SR_FRLVL)); 996:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 997:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 998:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 999:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Get FIFO Transmission Level 1000:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll SR FTLVL LL_SPI_GetTxFIFOLevel 1001:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 1002:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval Returned value can be one of the following values: 1003:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_TX_FIFO_EMPTY 1004:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_TX_FIFO_QUARTER_FULL 1005:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_TX_FIFO_HALF_FULL 1006:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_TX_FIFO_FULL 1007:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 1008:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_GetTxFIFOLevel(SPI_TypeDef *SPIx) 1009:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 1010:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** return (uint32_t)(READ_BIT(SPIx->SR, SPI_SR_FTLVL)); 1011:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1012:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 1013:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 1014:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Clear CRC error flag 1015:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll SR CRCERR LL_SPI_ClearFlag_CRCERR 1016:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 1017:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None 1018:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 1019:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_ClearFlag_CRCERR(SPI_TypeDef *SPIx) 1020:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { ARM GAS /tmp/ccYgfTud.s page 127 1021:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** CLEAR_BIT(SPIx->SR, SPI_SR_CRCERR); 1022:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1023:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 1024:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 1025:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Clear mode fault error flag 1026:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @note Clearing this flag is done by a read access to the SPIx_SR 1027:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * register followed by a write access to the SPIx_CR1 register 1028:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll SR MODF LL_SPI_ClearFlag_MODF 1029:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 1030:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None 1031:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 1032:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_ClearFlag_MODF(SPI_TypeDef *SPIx) 1033:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 1034:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __IO uint32_t tmpreg_sr; 1035:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** tmpreg_sr = SPIx->SR; 1036:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** (void) tmpreg_sr; 1037:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE); 1038:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1039:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 1040:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 1041:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Clear overrun error flag 1042:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @note Clearing this flag is done by a read access to the SPIx_DR 1043:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * register followed by a read access to the SPIx_SR register 1044:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll SR OVR LL_SPI_ClearFlag_OVR 1045:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 1046:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None 1047:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 1048:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_ClearFlag_OVR(SPI_TypeDef *SPIx) 1049:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 1050:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __IO uint32_t tmpreg; 1051:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** tmpreg = SPIx->DR; 1052:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** (void) tmpreg; 1053:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** tmpreg = SPIx->SR; 1054:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** (void) tmpreg; 1055:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1056:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 1057:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 1058:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Clear frame format error flag 1059:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @note Clearing this flag is done by reading SPIx_SR register 1060:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll SR FRE LL_SPI_ClearFlag_FRE 1061:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 1062:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None 1063:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 1064:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_ClearFlag_FRE(SPI_TypeDef *SPIx) 1065:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 1066:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __IO uint32_t tmpreg; 1067:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** tmpreg = SPIx->SR; 1068:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** (void) tmpreg; 1069:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1070:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 1071:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 1072:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @} 1073:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 1074:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 1075:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_EF_IT_Management Interrupt Management 1076:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @{ 1077:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ ARM GAS /tmp/ccYgfTud.s page 128 1078:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 1079:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 1080:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Enable error interrupt 1081:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @note This bit controls the generation of an interrupt when an error condition occurs (CRCERR 1082:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR2 ERRIE LL_SPI_EnableIT_ERR 1083:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 1084:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None 1085:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 1086:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_EnableIT_ERR(SPI_TypeDef *SPIx) 1087:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 1088:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** SET_BIT(SPIx->CR2, SPI_CR2_ERRIE); 1089:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1090:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 1091:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 1092:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Enable Rx buffer not empty interrupt 1093:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR2 RXNEIE LL_SPI_EnableIT_RXNE 1094:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 1095:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None 1096:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 1097:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_EnableIT_RXNE(SPI_TypeDef *SPIx) 1098:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 1099:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** SET_BIT(SPIx->CR2, SPI_CR2_RXNEIE); 1100:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1101:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 1102:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 1103:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Enable Tx buffer empty interrupt 1104:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR2 TXEIE LL_SPI_EnableIT_TXE 1105:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 1106:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None 1107:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 1108:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_EnableIT_TXE(SPI_TypeDef *SPIx) 1109:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 1110:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** SET_BIT(SPIx->CR2, SPI_CR2_TXEIE); 1111:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1112:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 1113:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 1114:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Disable error interrupt 1115:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @note This bit controls the generation of an interrupt when an error condition occurs (CRCERR 1116:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR2 ERRIE LL_SPI_DisableIT_ERR 1117:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 1118:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None 1119:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 1120:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_DisableIT_ERR(SPI_TypeDef *SPIx) 1121:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 1122:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** CLEAR_BIT(SPIx->CR2, SPI_CR2_ERRIE); 1123:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1124:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 1125:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 1126:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Disable Rx buffer not empty interrupt 1127:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR2 RXNEIE LL_SPI_DisableIT_RXNE 1128:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 1129:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None 1130:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 1131:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_DisableIT_RXNE(SPI_TypeDef *SPIx) 1132:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 1133:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** CLEAR_BIT(SPIx->CR2, SPI_CR2_RXNEIE); 1134:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } ARM GAS /tmp/ccYgfTud.s page 129 1135:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 1136:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 1137:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Disable Tx buffer empty interrupt 1138:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR2 TXEIE LL_SPI_DisableIT_TXE 1139:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 1140:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None 1141:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 1142:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_DisableIT_TXE(SPI_TypeDef *SPIx) 1143:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 1144:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** CLEAR_BIT(SPIx->CR2, SPI_CR2_TXEIE); 1145:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1146:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 1147:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 1148:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Check if error interrupt is enabled 1149:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR2 ERRIE LL_SPI_IsEnabledIT_ERR 1150:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 1151:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval State of bit (1 or 0). 1152:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 1153:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_ERR(SPI_TypeDef *SPIx) 1154:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 1155:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** return ((READ_BIT(SPIx->CR2, SPI_CR2_ERRIE) == (SPI_CR2_ERRIE)) ? 1UL : 0UL); 1156:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1157:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 1158:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 1159:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Check if Rx buffer not empty interrupt is enabled 1160:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR2 RXNEIE LL_SPI_IsEnabledIT_RXNE 1161:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 1162:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval State of bit (1 or 0). 1163:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 1164:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_RXNE(SPI_TypeDef *SPIx) 1165:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 1166:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** return ((READ_BIT(SPIx->CR2, SPI_CR2_RXNEIE) == (SPI_CR2_RXNEIE)) ? 1UL : 0UL); 1167:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1168:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 1169:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 1170:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Check if Tx buffer empty interrupt 1171:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR2 TXEIE LL_SPI_IsEnabledIT_TXE 1172:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 1173:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval State of bit (1 or 0). 1174:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 1175:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_TXE(SPI_TypeDef *SPIx) 1176:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 1177:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** return ((READ_BIT(SPIx->CR2, SPI_CR2_TXEIE) == (SPI_CR2_TXEIE)) ? 1UL : 0UL); 1178:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1179:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 1180:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 1181:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @} 1182:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 1183:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 1184:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_EF_DMA_Management DMA Management 1185:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @{ 1186:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 1187:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 1188:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 1189:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Enable DMA Rx 1190:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR2 RXDMAEN LL_SPI_EnableDMAReq_RX 1191:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance ARM GAS /tmp/ccYgfTud.s page 130 1192:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None 1193:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 1194:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_EnableDMAReq_RX(SPI_TypeDef *SPIx) 1195:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 1196:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** SET_BIT(SPIx->CR2, SPI_CR2_RXDMAEN); 1197:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1198:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 1199:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 1200:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Disable DMA Rx 1201:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR2 RXDMAEN LL_SPI_DisableDMAReq_RX 1202:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 1203:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None 1204:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 1205:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_DisableDMAReq_RX(SPI_TypeDef *SPIx) 1206:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 1207:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** CLEAR_BIT(SPIx->CR2, SPI_CR2_RXDMAEN); 1208:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1209:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 1210:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 1211:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Check if DMA Rx is enabled 1212:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR2 RXDMAEN LL_SPI_IsEnabledDMAReq_RX 1213:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 1214:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval State of bit (1 or 0). 1215:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 1216:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_RX(SPI_TypeDef *SPIx) 1217:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 1218:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** return ((READ_BIT(SPIx->CR2, SPI_CR2_RXDMAEN) == (SPI_CR2_RXDMAEN)) ? 1UL : 0UL); 1219:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1220:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 1221:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 1222:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Enable DMA Tx 1223:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR2 TXDMAEN LL_SPI_EnableDMAReq_TX 1224:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 1225:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None 1226:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 1227:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_EnableDMAReq_TX(SPI_TypeDef *SPIx) 1228:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 1229:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** SET_BIT(SPIx->CR2, SPI_CR2_TXDMAEN); 1230:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1231:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 1232:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 1233:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Disable DMA Tx 1234:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR2 TXDMAEN LL_SPI_DisableDMAReq_TX 1235:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 1236:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None 1237:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 1238:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_DisableDMAReq_TX(SPI_TypeDef *SPIx) 1239:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 1240:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** CLEAR_BIT(SPIx->CR2, SPI_CR2_TXDMAEN); 1241:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1242:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 1243:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 1244:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Check if DMA Tx is enabled 1245:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR2 TXDMAEN LL_SPI_IsEnabledDMAReq_TX 1246:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 1247:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval State of bit (1 or 0). 1248:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ ARM GAS /tmp/ccYgfTud.s page 131 1249:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx) 1250:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 1251:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** return ((READ_BIT(SPIx->CR2, SPI_CR2_TXDMAEN) == (SPI_CR2_TXDMAEN)) ? 1UL : 0UL); 1252:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1253:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 1254:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 1255:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Set parity of Last DMA reception 1256:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR2 LDMARX LL_SPI_SetDMAParity_RX 1257:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 1258:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param Parity This parameter can be one of the following values: 1259:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_DMA_PARITY_ODD 1260:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_DMA_PARITY_EVEN 1261:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None 1262:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 1263:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_SetDMAParity_RX(SPI_TypeDef *SPIx, uint32_t Parity) 1264:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 1265:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** MODIFY_REG(SPIx->CR2, SPI_CR2_LDMARX, (Parity << SPI_CR2_LDMARX_Pos)); 1266:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1267:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 1268:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 1269:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Get parity configuration for Last DMA reception 1270:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR2 LDMARX LL_SPI_GetDMAParity_RX 1271:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 1272:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval Returned value can be one of the following values: 1273:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_DMA_PARITY_ODD 1274:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_DMA_PARITY_EVEN 1275:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 1276:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_GetDMAParity_RX(SPI_TypeDef *SPIx) 1277:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 1278:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_LDMARX) >> SPI_CR2_LDMARX_Pos); 1279:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1280:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 1281:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 1282:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Set parity of Last DMA transmission 1283:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR2 LDMATX LL_SPI_SetDMAParity_TX 1284:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 1285:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param Parity This parameter can be one of the following values: 1286:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_DMA_PARITY_ODD 1287:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_DMA_PARITY_EVEN 1288:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None 1289:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 1290:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_SetDMAParity_TX(SPI_TypeDef *SPIx, uint32_t Parity) 1291:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 1292:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** MODIFY_REG(SPIx->CR2, SPI_CR2_LDMATX, (Parity << SPI_CR2_LDMATX_Pos)); 1293:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1294:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 1295:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 1296:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Get parity configuration for Last DMA transmission 1297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR2 LDMATX LL_SPI_GetDMAParity_TX 1298:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 1299:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval Returned value can be one of the following values: 1300:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_DMA_PARITY_ODD 1301:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_DMA_PARITY_EVEN 1302:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 1303:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_GetDMAParity_TX(SPI_TypeDef *SPIx) 1304:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 1305:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_LDMATX) >> SPI_CR2_LDMATX_Pos); ARM GAS /tmp/ccYgfTud.s page 132 1306:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1307:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 1308:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 1309:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Get the data register address used for DMA transfer 1310:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll DR DR LL_SPI_DMA_GetRegAddr 1311:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 1312:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval Address of data register 1313:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 1314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_DMA_GetRegAddr(SPI_TypeDef *SPIx) 1315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 1316:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** return (uint32_t) &(SPIx->DR); 1317:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1318:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 1319:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 1320:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @} 1321:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 1322:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 1323:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_EF_DATA_Management DATA Management 1324:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @{ 1325:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 1326:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 1327:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 1328:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Read 8-Bits in the data register 1329:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll DR DR LL_SPI_ReceiveData8 1330:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 1331:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval RxData Value between Min_Data=0x00 and Max_Data=0xFF 1332:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 1333:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint8_t LL_SPI_ReceiveData8(SPI_TypeDef *SPIx) 1334:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 1335:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** return (*((__IO uint8_t *)&SPIx->DR)); 1336:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1337:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 1338:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 1339:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Read 16-Bits in the data register 1340:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll DR DR LL_SPI_ReceiveData16 1341:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 1342:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval RxData Value between Min_Data=0x00 and Max_Data=0xFFFF 1343:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 1344:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint16_t LL_SPI_ReceiveData16(SPI_TypeDef *SPIx) 1345:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 1346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** return (uint16_t)(READ_REG(SPIx->DR)); 1347:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1348:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 1349:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 1350:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Write 8-Bits in the data register 1351:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll DR DR LL_SPI_TransmitData8 1352:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 1353:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param TxData Value between Min_Data=0x00 and Max_Data=0xFF 1354:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None 1355:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 1356:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_TransmitData8(SPI_TypeDef *SPIx, uint8_t TxData) 1357:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 1358:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #if defined (__GNUC__) 1359:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __IO uint8_t *spidr = ((__IO uint8_t *)&SPIx->DR); 1360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** *spidr = TxData; 1361:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #else 1362:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** *((__IO uint8_t *)&SPIx->DR) = TxData; ARM GAS /tmp/ccYgfTud.s page 133 1363:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #endif /* __GNUC__ */ 1364:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1365:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 1366:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 1367:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Write 16-Bits in the data register 1368:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll DR DR LL_SPI_TransmitData16 1369:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 1370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param TxData Value between Min_Data=0x00 and Max_Data=0xFFFF 1371:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None 1372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 1373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData) 826 .loc 4 1373 22 view .LVU289 827 .LBB344: 1374:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 1375:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #if defined (__GNUC__) 1376:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __IO uint16_t *spidr = ((__IO uint16_t *)&SPIx->DR); 828 .loc 4 1376 3 view .LVU290 1377:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** *spidr = TxData; 829 .loc 4 1377 3 view .LVU291 830 .loc 4 1377 10 is_stmt 0 view .LVU292 831 0040 194B ldr r3, .L44 832 0042 9D81 strh r5, [r3, #12] @ movhi 833 .LVL64: 834 .loc 4 1377 10 view .LVU293 835 .LBE344: 836 .LBE343: 2428:Src/main.c **** while((!LL_SPI_IsActiveFlag_RXNE(SPI2)) && (tmp32++ < 1000)) {} 837 .loc 1 2428 2 is_stmt 1 view .LVU294 2429:Src/main.c **** (void) SPI2->DR; 838 .loc 1 2429 2 view .LVU295 2428:Src/main.c **** while((!LL_SPI_IsActiveFlag_RXNE(SPI2)) && (tmp32++ < 1000)) {} 839 .loc 1 2428 8 is_stmt 0 view .LVU296 840 0044 0023 movs r3, #0 841 .LVL65: 842 .L34: 2429:Src/main.c **** (void) SPI2->DR; 843 .loc 1 2429 64 is_stmt 1 discriminator 2 view .LVU297 2429:Src/main.c **** (void) SPI2->DR; 844 .loc 1 2429 42 discriminator 2 view .LVU298 845 .LBB345: 846 .LBI345: 905:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 847 .loc 4 905 26 view .LVU299 848 .LBB346: 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 849 .loc 4 907 3 view .LVU300 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 850 .loc 4 907 12 is_stmt 0 view .LVU301 851 0046 184A ldr r2, .L44 852 0048 9268 ldr r2, [r2, #8] 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 853 .loc 4 907 68 view .LVU302 854 004a 12F0010F tst r2, #1 855 004e 05D1 bne .L33 856 .LVL66: 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 857 .loc 4 907 68 view .LVU303 ARM GAS /tmp/ccYgfTud.s page 134 858 .LBE346: 859 .LBE345: 2429:Src/main.c **** (void) SPI2->DR; 860 .loc 1 2429 51 discriminator 1 view .LVU304 861 0050 5A1C adds r2, r3, #1 862 .LVL67: 2429:Src/main.c **** (void) SPI2->DR; 863 .loc 1 2429 42 discriminator 1 view .LVU305 864 0052 B3F57A7F cmp r3, #1000 865 0056 01D2 bcs .L33 2429:Src/main.c **** (void) SPI2->DR; 866 .loc 1 2429 51 discriminator 1 view .LVU306 867 0058 1346 mov r3, r2 868 005a F4E7 b .L34 869 .LVL68: 870 .L33: 2430:Src/main.c **** 871 .loc 1 2430 2 is_stmt 1 view .LVU307 872 005c 124B ldr r3, .L44 873 005e DB68 ldr r3, [r3, #12] 2432:Src/main.c **** while((!LL_SPI_IsActiveFlag_TXE(SPI2)) && (tmp32++ < 1000)) {} 874 .loc 1 2432 2 view .LVU308 875 .LVL69: 2433:Src/main.c **** LL_SPI_TransmitData16(SPI2, value); 876 .loc 1 2433 2 view .LVU309 2432:Src/main.c **** while((!LL_SPI_IsActiveFlag_TXE(SPI2)) && (tmp32++ < 1000)) {} 877 .loc 1 2432 8 is_stmt 0 view .LVU310 878 0060 0023 movs r3, #0 879 .LVL70: 880 .L36: 2433:Src/main.c **** LL_SPI_TransmitData16(SPI2, value); 881 .loc 1 2433 63 is_stmt 1 discriminator 2 view .LVU311 2433:Src/main.c **** LL_SPI_TransmitData16(SPI2, value); 882 .loc 1 2433 41 discriminator 2 view .LVU312 883 .LBB347: 884 .LBI347: 916:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 885 .loc 4 916 26 view .LVU313 886 .LBB348: 918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 887 .loc 4 918 3 view .LVU314 918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 888 .loc 4 918 12 is_stmt 0 view .LVU315 889 0062 114A ldr r2, .L44 890 0064 9268 ldr r2, [r2, #8] 918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 891 .loc 4 918 66 view .LVU316 892 0066 12F0020F tst r2, #2 893 006a 05D1 bne .L35 894 .LVL71: 918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 895 .loc 4 918 66 view .LVU317 896 .LBE348: 897 .LBE347: 2433:Src/main.c **** LL_SPI_TransmitData16(SPI2, value); 898 .loc 1 2433 50 discriminator 1 view .LVU318 899 006c 5A1C adds r2, r3, #1 ARM GAS /tmp/ccYgfTud.s page 135 900 .LVL72: 2433:Src/main.c **** LL_SPI_TransmitData16(SPI2, value); 901 .loc 1 2433 41 discriminator 1 view .LVU319 902 006e B3F57A7F cmp r3, #1000 903 0072 01D2 bcs .L35 2433:Src/main.c **** LL_SPI_TransmitData16(SPI2, value); 904 .loc 1 2433 50 discriminator 1 view .LVU320 905 0074 1346 mov r3, r2 906 0076 F4E7 b .L36 907 .LVL73: 908 .L35: 2434:Src/main.c **** tmp32 = 0; 909 .loc 1 2434 2 is_stmt 1 view .LVU321 910 .LBB349: 911 .LBI349: 1373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 912 .loc 4 1373 22 view .LVU322 913 .LBB350: 1376:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** *spidr = TxData; 914 .loc 4 1376 3 view .LVU323 915 .loc 4 1377 3 view .LVU324 916 .loc 4 1377 10 is_stmt 0 view .LVU325 917 0078 0B4B ldr r3, .L44 918 007a 9C81 strh r4, [r3, #12] @ movhi 919 .LVL74: 920 .loc 4 1377 10 view .LVU326 921 .LBE350: 922 .LBE349: 2435:Src/main.c **** while((!LL_SPI_IsActiveFlag_RXNE(SPI2)) && (tmp32++ < 1000)) {} 923 .loc 1 2435 2 is_stmt 1 view .LVU327 2436:Src/main.c **** (void) SPI2->DR; 924 .loc 1 2436 2 view .LVU328 2435:Src/main.c **** while((!LL_SPI_IsActiveFlag_RXNE(SPI2)) && (tmp32++ < 1000)) {} 925 .loc 1 2435 8 is_stmt 0 view .LVU329 926 007c 0023 movs r3, #0 927 .LVL75: 928 .L38: 2436:Src/main.c **** (void) SPI2->DR; 929 .loc 1 2436 64 is_stmt 1 discriminator 2 view .LVU330 2436:Src/main.c **** (void) SPI2->DR; 930 .loc 1 2436 42 discriminator 2 view .LVU331 931 .LBB351: 932 .LBI351: 905:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 933 .loc 4 905 26 view .LVU332 934 .LBB352: 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 935 .loc 4 907 3 view .LVU333 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 936 .loc 4 907 12 is_stmt 0 view .LVU334 937 007e 0A4A ldr r2, .L44 938 0080 9268 ldr r2, [r2, #8] 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 939 .loc 4 907 68 view .LVU335 940 0082 12F0010F tst r2, #1 941 0086 05D1 bne .L37 942 .LVL76: ARM GAS /tmp/ccYgfTud.s page 136 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 943 .loc 4 907 68 view .LVU336 944 .LBE352: 945 .LBE351: 2436:Src/main.c **** (void) SPI2->DR; 946 .loc 1 2436 51 discriminator 1 view .LVU337 947 0088 5A1C adds r2, r3, #1 948 .LVL77: 2436:Src/main.c **** (void) SPI2->DR; 949 .loc 1 2436 42 discriminator 1 view .LVU338 950 008a B3F57A7F cmp r3, #1000 951 008e 01D2 bcs .L37 2436:Src/main.c **** (void) SPI2->DR; 952 .loc 1 2436 51 discriminator 1 view .LVU339 953 0090 1346 mov r3, r2 954 0092 F4E7 b .L38 955 .LVL78: 956 .L37: 2437:Src/main.c **** 957 .loc 1 2437 2 is_stmt 1 view .LVU340 958 0094 044B ldr r3, .L44 959 0096 DB68 ldr r3, [r3, #12] 2439:Src/main.c **** } 960 .loc 1 2439 2 view .LVU341 961 0098 0122 movs r2, #1 962 009a 4FF48051 mov r1, #4096 963 009e 0348 ldr r0, .L44+4 964 00a0 FFF7FEFF bl HAL_GPIO_WritePin 965 .LVL79: 2440:Src/main.c **** 966 .loc 1 2440 1 is_stmt 0 view .LVU342 967 00a4 38BD pop {r3, r4, r5, pc} 968 .LVL80: 969 .L45: 2440:Src/main.c **** 970 .loc 1 2440 1 view .LVU343 971 00a6 00BF .align 2 972 .L44: 973 00a8 00380040 .word 1073756160 974 00ac 00040240 .word 1073873920 975 .cfi_endproc 976 .LFE1212: 978 .section .text.AD9102_WriteRegTable,"ax",%progbits 979 .align 1 980 .syntax unified 981 .thumb 982 .thumb_func 984 AD9102_WriteRegTable: 985 .LVL81: 986 .LFB1214: 2473:Src/main.c **** for (uint16_t i = 0; i < count; i++) 987 .loc 1 2473 1 is_stmt 1 view -0 988 .cfi_startproc 989 @ args = 0, pretend = 0, frame = 0 990 @ frame_needed = 0, uses_anonymous_args = 0 2473:Src/main.c **** for (uint16_t i = 0; i < count; i++) 991 .loc 1 2473 1 is_stmt 0 view .LVU345 ARM GAS /tmp/ccYgfTud.s page 137 992 0000 70B5 push {r4, r5, r6, lr} 993 .LCFI10: 994 .cfi_def_cfa_offset 16 995 .cfi_offset 4, -16 996 .cfi_offset 5, -12 997 .cfi_offset 6, -8 998 .cfi_offset 14, -4 999 0002 0646 mov r6, r0 1000 0004 0D46 mov r5, r1 2474:Src/main.c **** { 1001 .loc 1 2474 2 is_stmt 1 view .LVU346 1002 .LBB353: 2474:Src/main.c **** { 1003 .loc 1 2474 7 view .LVU347 1004 .LVL82: 2474:Src/main.c **** { 1005 .loc 1 2474 16 is_stmt 0 view .LVU348 1006 0006 0024 movs r4, #0 2474:Src/main.c **** { 1007 .loc 1 2474 2 view .LVU349 1008 0008 08E0 b .L47 1009 .LVL83: 1010 .L48: 2476:Src/main.c **** } 1011 .loc 1 2476 3 is_stmt 1 view .LVU350 1012 000a 36F81410 ldrh r1, [r6, r4, lsl #1] 1013 000e 054B ldr r3, .L50 1014 0010 33F81400 ldrh r0, [r3, r4, lsl #1] 1015 0014 FFF7FEFF bl AD9102_WriteReg 1016 .LVL84: 2474:Src/main.c **** { 1017 .loc 1 2474 35 discriminator 3 view .LVU351 1018 0018 0134 adds r4, r4, #1 1019 .LVL85: 2474:Src/main.c **** { 1020 .loc 1 2474 35 is_stmt 0 discriminator 3 view .LVU352 1021 001a A4B2 uxth r4, r4 1022 .LVL86: 1023 .L47: 2474:Src/main.c **** { 1024 .loc 1 2474 25 is_stmt 1 discriminator 1 view .LVU353 1025 001c AC42 cmp r4, r5 1026 001e F4D3 bcc .L48 1027 .LBE353: 2478:Src/main.c **** 1028 .loc 1 2478 1 is_stmt 0 view .LVU354 1029 0020 70BD pop {r4, r5, r6, pc} 1030 .LVL87: 1031 .L51: 2478:Src/main.c **** 1032 .loc 1 2478 1 view .LVU355 1033 0022 00BF .align 2 1034 .L50: 1035 0024 00000000 .word ad9102_reg_addr 1036 .cfi_endproc 1037 .LFE1214: 1039 .section .text.AD9102_Init,"ax",%progbits ARM GAS /tmp/ccYgfTud.s page 138 1040 .align 1 1041 .syntax unified 1042 .thumb 1043 .thumb_func 1045 AD9102_Init: 1046 .LFB1211: 2402:Src/main.c **** HAL_GPIO_WritePin(AD9102_CS_GPIO_Port, AD9102_CS_Pin, GPIO_PIN_SET); 1047 .loc 1 2402 1 is_stmt 1 view -0 1048 .cfi_startproc 1049 @ args = 0, pretend = 0, frame = 8 1050 @ frame_needed = 0, uses_anonymous_args = 0 1051 0000 00B5 push {lr} 1052 .LCFI11: 1053 .cfi_def_cfa_offset 4 1054 .cfi_offset 14, -4 1055 0002 83B0 sub sp, sp, #12 1056 .LCFI12: 1057 .cfi_def_cfa_offset 16 2403:Src/main.c **** HAL_GPIO_WritePin(AD9102_RESET_GPIO_Port, AD9102_RESET_Pin, GPIO_PIN_RESET); 1058 .loc 1 2403 2 view .LVU357 1059 0004 0122 movs r2, #1 1060 0006 4FF48051 mov r1, #4096 1061 000a 1648 ldr r0, .L56 1062 000c FFF7FEFF bl HAL_GPIO_WritePin 1063 .LVL88: 2404:Src/main.c **** for (volatile uint32_t d = 0; d < 1000; d++) {} 1064 .loc 1 2404 2 view .LVU358 1065 0010 0022 movs r2, #0 1066 0012 4021 movs r1, #64 1067 0014 1448 ldr r0, .L56+4 1068 0016 FFF7FEFF bl HAL_GPIO_WritePin 1069 .LVL89: 2405:Src/main.c **** HAL_GPIO_WritePin(AD9102_RESET_GPIO_Port, AD9102_RESET_Pin, GPIO_PIN_SET); 1070 .loc 1 2405 2 view .LVU359 1071 .LBB354: 2405:Src/main.c **** HAL_GPIO_WritePin(AD9102_RESET_GPIO_Port, AD9102_RESET_Pin, GPIO_PIN_SET); 1072 .loc 1 2405 7 view .LVU360 2405:Src/main.c **** HAL_GPIO_WritePin(AD9102_RESET_GPIO_Port, AD9102_RESET_Pin, GPIO_PIN_SET); 1073 .loc 1 2405 25 is_stmt 0 view .LVU361 1074 001a 0023 movs r3, #0 1075 001c 0193 str r3, [sp, #4] 2405:Src/main.c **** HAL_GPIO_WritePin(AD9102_RESET_GPIO_Port, AD9102_RESET_Pin, GPIO_PIN_SET); 1076 .loc 1 2405 2 view .LVU362 1077 001e 02E0 b .L53 1078 .L54: 2405:Src/main.c **** HAL_GPIO_WritePin(AD9102_RESET_GPIO_Port, AD9102_RESET_Pin, GPIO_PIN_SET); 1079 .loc 1 2405 48 is_stmt 1 discriminator 3 view .LVU363 2405:Src/main.c **** HAL_GPIO_WritePin(AD9102_RESET_GPIO_Port, AD9102_RESET_Pin, GPIO_PIN_SET); 1080 .loc 1 2405 43 discriminator 3 view .LVU364 1081 0020 019B ldr r3, [sp, #4] 1082 0022 0133 adds r3, r3, #1 1083 0024 0193 str r3, [sp, #4] 1084 .L53: 2405:Src/main.c **** HAL_GPIO_WritePin(AD9102_RESET_GPIO_Port, AD9102_RESET_Pin, GPIO_PIN_SET); 1085 .loc 1 2405 34 discriminator 1 view .LVU365 1086 0026 019B ldr r3, [sp, #4] 1087 0028 B3F57A7F cmp r3, #1000 ARM GAS /tmp/ccYgfTud.s page 139 1088 002c F8D3 bcc .L54 1089 .LBE354: 2406:Src/main.c **** 1090 .loc 1 2406 2 view .LVU366 1091 002e 0122 movs r2, #1 1092 0030 4021 movs r1, #64 1093 0032 0D48 ldr r0, .L56+4 1094 0034 FFF7FEFF bl HAL_GPIO_WritePin 1095 .LVL90: 2408:Src/main.c **** AD9102_WriteReg(AD9102_REG_PAT_STATUS, 0x0000u); 1096 .loc 1 2408 2 view .LVU367 1097 0038 4221 movs r1, #66 1098 003a 0C48 ldr r0, .L56+8 1099 003c FFF7FEFF bl AD9102_WriteRegTable 1100 .LVL91: 2409:Src/main.c **** AD9102_WriteReg(AD9102_REG_RAMUPDATE, 0x0001u); 1101 .loc 1 2409 2 view .LVU368 1102 0040 0021 movs r1, #0 1103 0042 1E20 movs r0, #30 1104 0044 FFF7FEFF bl AD9102_WriteReg 1105 .LVL92: 2410:Src/main.c **** HAL_GPIO_WritePin(AD9102_TRIG_GPIO_Port, AD9102_TRIG_Pin, GPIO_PIN_SET); 1106 .loc 1 2410 2 view .LVU369 1107 0048 0121 movs r1, #1 1108 004a 1D20 movs r0, #29 1109 004c FFF7FEFF bl AD9102_WriteReg 1110 .LVL93: 2411:Src/main.c **** } 1111 .loc 1 2411 2 view .LVU370 1112 0050 0122 movs r2, #1 1113 0052 4FF40061 mov r1, #2048 1114 0056 0648 ldr r0, .L56+12 1115 0058 FFF7FEFF bl HAL_GPIO_WritePin 1116 .LVL94: 2412:Src/main.c **** 1117 .loc 1 2412 1 is_stmt 0 view .LVU371 1118 005c 03B0 add sp, sp, #12 1119 .LCFI13: 1120 .cfi_def_cfa_offset 4 1121 @ sp needed 1122 005e 5DF804FB ldr pc, [sp], #4 1123 .L57: 1124 0062 00BF .align 2 1125 .L56: 1126 0064 00040240 .word 1073873920 1127 0068 00080240 .word 1073874944 1128 006c 00000000 .word ad9102_example4_regval 1129 0070 000C0240 .word 1073875968 1130 .cfi_endproc 1131 .LFE1211: 1133 .section .text.AD9102_ReadReg,"ax",%progbits 1134 .align 1 1135 .syntax unified 1136 .thumb 1137 .thumb_func 1139 AD9102_ReadReg: 1140 .LVL95: ARM GAS /tmp/ccYgfTud.s page 140 1141 .LFB1213: 2443:Src/main.c **** uint32_t tmp32 = 0; 1142 .loc 1 2443 1 is_stmt 1 view -0 1143 .cfi_startproc 1144 @ args = 0, pretend = 0, frame = 0 1145 @ frame_needed = 0, uses_anonymous_args = 0 2443:Src/main.c **** uint32_t tmp32 = 0; 1146 .loc 1 2443 1 is_stmt 0 view .LVU373 1147 0000 10B5 push {r4, lr} 1148 .LCFI14: 1149 .cfi_def_cfa_offset 8 1150 .cfi_offset 4, -8 1151 .cfi_offset 14, -4 2444:Src/main.c **** uint16_t cmd = (uint16_t)(0x8000u | (addr & 0x7FFFu)); // R/W = 1 (read) 1152 .loc 1 2444 2 is_stmt 1 view .LVU374 1153 .LVL96: 2445:Src/main.c **** uint16_t value; 1154 .loc 1 2445 2 view .LVU375 2445:Src/main.c **** uint16_t value; 1155 .loc 1 2445 11 is_stmt 0 view .LVU376 1156 0002 40F40044 orr r4, r0, #32768 1157 .LVL97: 2446:Src/main.c **** 1158 .loc 1 2446 2 is_stmt 1 view .LVU377 2448:Src/main.c **** { 1159 .loc 1 2448 2 view .LVU378 1160 .LBB355: 1161 .LBI355: 381:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 1162 .loc 4 381 26 view .LVU379 1163 .LBB356: 383:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1164 .loc 4 383 3 view .LVU380 383:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1165 .loc 4 383 12 is_stmt 0 view .LVU381 1166 0006 284B ldr r3, .L73 1167 0008 1B68 ldr r3, [r3] 383:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1168 .loc 4 383 69 view .LVU382 1169 000a 13F0400F tst r3, #64 1170 000e 04D1 bne .L59 1171 .LVL98: 383:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1172 .loc 4 383 69 view .LVU383 1173 .LBE356: 1174 .LBE355: 2450:Src/main.c **** } 1175 .loc 1 2450 3 is_stmt 1 view .LVU384 1176 .LBB357: 1177 .LBI357: 358:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 1178 .loc 4 358 22 view .LVU385 1179 .LBB358: 360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1180 .loc 4 360 3 view .LVU386 1181 0010 254A ldr r2, .L73 1182 0012 1368 ldr r3, [r2] ARM GAS /tmp/ccYgfTud.s page 141 1183 0014 43F04003 orr r3, r3, #64 1184 0018 1360 str r3, [r2] 1185 .LVL99: 1186 .L59: 360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1187 .loc 4 360 3 is_stmt 0 view .LVU387 1188 .LBE358: 1189 .LBE357: 2453:Src/main.c **** 1190 .loc 1 2453 2 is_stmt 1 view .LVU388 1191 001a 0022 movs r2, #0 1192 001c 4FF48051 mov r1, #4096 1193 0020 2248 ldr r0, .L73+4 1194 .LVL100: 2453:Src/main.c **** 1195 .loc 1 2453 2 is_stmt 0 view .LVU389 1196 0022 FFF7FEFF bl HAL_GPIO_WritePin 1197 .LVL101: 2455:Src/main.c **** LL_SPI_TransmitData16(SPI2, cmd); 1198 .loc 1 2455 2 is_stmt 1 view .LVU390 2444:Src/main.c **** uint16_t cmd = (uint16_t)(0x8000u | (addr & 0x7FFFu)); // R/W = 1 (read) 1199 .loc 1 2444 11 is_stmt 0 view .LVU391 1200 0026 0023 movs r3, #0 1201 .LVL102: 1202 .L61: 2455:Src/main.c **** LL_SPI_TransmitData16(SPI2, cmd); 1203 .loc 1 2455 63 is_stmt 1 discriminator 2 view .LVU392 2455:Src/main.c **** LL_SPI_TransmitData16(SPI2, cmd); 1204 .loc 1 2455 41 discriminator 2 view .LVU393 1205 .LBB359: 1206 .LBI359: 916:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 1207 .loc 4 916 26 view .LVU394 1208 .LBB360: 918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1209 .loc 4 918 3 view .LVU395 918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1210 .loc 4 918 12 is_stmt 0 view .LVU396 1211 0028 1F4A ldr r2, .L73 1212 002a 9268 ldr r2, [r2, #8] 918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1213 .loc 4 918 66 view .LVU397 1214 002c 12F0020F tst r2, #2 1215 0030 05D1 bne .L60 1216 .LVL103: 918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1217 .loc 4 918 66 view .LVU398 1218 .LBE360: 1219 .LBE359: 2455:Src/main.c **** LL_SPI_TransmitData16(SPI2, cmd); 1220 .loc 1 2455 50 discriminator 1 view .LVU399 1221 0032 5A1C adds r2, r3, #1 1222 .LVL104: 2455:Src/main.c **** LL_SPI_TransmitData16(SPI2, cmd); 1223 .loc 1 2455 41 discriminator 1 view .LVU400 1224 0034 B3F57A7F cmp r3, #1000 1225 0038 01D2 bcs .L60 ARM GAS /tmp/ccYgfTud.s page 142 2455:Src/main.c **** LL_SPI_TransmitData16(SPI2, cmd); 1226 .loc 1 2455 50 discriminator 1 view .LVU401 1227 003a 1346 mov r3, r2 1228 003c F4E7 b .L61 1229 .LVL105: 1230 .L60: 2456:Src/main.c **** tmp32 = 0; 1231 .loc 1 2456 2 is_stmt 1 view .LVU402 1232 .LBB361: 1233 .LBI361: 1373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 1234 .loc 4 1373 22 view .LVU403 1235 .LBB362: 1376:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** *spidr = TxData; 1236 .loc 4 1376 3 view .LVU404 1237 .loc 4 1377 3 view .LVU405 1238 .loc 4 1377 10 is_stmt 0 view .LVU406 1239 003e 1A4B ldr r3, .L73 1240 0040 9C81 strh r4, [r3, #12] @ movhi 1241 .LVL106: 1242 .loc 4 1377 10 view .LVU407 1243 .LBE362: 1244 .LBE361: 2457:Src/main.c **** while((!LL_SPI_IsActiveFlag_RXNE(SPI2)) && (tmp32++ < 1000)) {} 1245 .loc 1 2457 2 is_stmt 1 view .LVU408 2458:Src/main.c **** (void) SPI2->DR; 1246 .loc 1 2458 2 view .LVU409 2457:Src/main.c **** while((!LL_SPI_IsActiveFlag_RXNE(SPI2)) && (tmp32++ < 1000)) {} 1247 .loc 1 2457 8 is_stmt 0 view .LVU410 1248 0042 0023 movs r3, #0 1249 .LVL107: 1250 .L63: 2458:Src/main.c **** (void) SPI2->DR; 1251 .loc 1 2458 64 is_stmt 1 discriminator 2 view .LVU411 2458:Src/main.c **** (void) SPI2->DR; 1252 .loc 1 2458 42 discriminator 2 view .LVU412 1253 .LBB363: 1254 .LBI363: 905:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 1255 .loc 4 905 26 view .LVU413 1256 .LBB364: 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1257 .loc 4 907 3 view .LVU414 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1258 .loc 4 907 12 is_stmt 0 view .LVU415 1259 0044 184A ldr r2, .L73 1260 0046 9268 ldr r2, [r2, #8] 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1261 .loc 4 907 68 view .LVU416 1262 0048 12F0010F tst r2, #1 1263 004c 05D1 bne .L62 1264 .LVL108: 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1265 .loc 4 907 68 view .LVU417 1266 .LBE364: 1267 .LBE363: 2458:Src/main.c **** (void) SPI2->DR; ARM GAS /tmp/ccYgfTud.s page 143 1268 .loc 1 2458 51 discriminator 1 view .LVU418 1269 004e 5A1C adds r2, r3, #1 1270 .LVL109: 2458:Src/main.c **** (void) SPI2->DR; 1271 .loc 1 2458 42 discriminator 1 view .LVU419 1272 0050 B3F57A7F cmp r3, #1000 1273 0054 01D2 bcs .L62 2458:Src/main.c **** (void) SPI2->DR; 1274 .loc 1 2458 51 discriminator 1 view .LVU420 1275 0056 1346 mov r3, r2 1276 0058 F4E7 b .L63 1277 .LVL110: 1278 .L62: 2459:Src/main.c **** 1279 .loc 1 2459 2 is_stmt 1 view .LVU421 1280 005a 134B ldr r3, .L73 1281 005c DB68 ldr r3, [r3, #12] 2461:Src/main.c **** while((!LL_SPI_IsActiveFlag_TXE(SPI2)) && (tmp32++ < 1000)) {} 1282 .loc 1 2461 2 view .LVU422 1283 .LVL111: 2462:Src/main.c **** LL_SPI_TransmitData16(SPI2, 0x0000u); 1284 .loc 1 2462 2 view .LVU423 2461:Src/main.c **** while((!LL_SPI_IsActiveFlag_TXE(SPI2)) && (tmp32++ < 1000)) {} 1285 .loc 1 2461 8 is_stmt 0 view .LVU424 1286 005e 0023 movs r3, #0 1287 .LVL112: 1288 .L65: 2462:Src/main.c **** LL_SPI_TransmitData16(SPI2, 0x0000u); 1289 .loc 1 2462 63 is_stmt 1 discriminator 2 view .LVU425 2462:Src/main.c **** LL_SPI_TransmitData16(SPI2, 0x0000u); 1290 .loc 1 2462 41 discriminator 2 view .LVU426 1291 .LBB365: 1292 .LBI365: 916:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 1293 .loc 4 916 26 view .LVU427 1294 .LBB366: 918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1295 .loc 4 918 3 view .LVU428 918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1296 .loc 4 918 12 is_stmt 0 view .LVU429 1297 0060 114A ldr r2, .L73 1298 0062 9268 ldr r2, [r2, #8] 918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1299 .loc 4 918 66 view .LVU430 1300 0064 12F0020F tst r2, #2 1301 0068 05D1 bne .L64 1302 .LVL113: 918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1303 .loc 4 918 66 view .LVU431 1304 .LBE366: 1305 .LBE365: 2462:Src/main.c **** LL_SPI_TransmitData16(SPI2, 0x0000u); 1306 .loc 1 2462 50 discriminator 1 view .LVU432 1307 006a 5A1C adds r2, r3, #1 1308 .LVL114: 2462:Src/main.c **** LL_SPI_TransmitData16(SPI2, 0x0000u); 1309 .loc 1 2462 41 discriminator 1 view .LVU433 ARM GAS /tmp/ccYgfTud.s page 144 1310 006c B3F57A7F cmp r3, #1000 1311 0070 01D2 bcs .L64 2462:Src/main.c **** LL_SPI_TransmitData16(SPI2, 0x0000u); 1312 .loc 1 2462 50 discriminator 1 view .LVU434 1313 0072 1346 mov r3, r2 1314 0074 F4E7 b .L65 1315 .LVL115: 1316 .L64: 2463:Src/main.c **** tmp32 = 0; 1317 .loc 1 2463 2 is_stmt 1 view .LVU435 1318 .LBB367: 1319 .LBI367: 1373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 1320 .loc 4 1373 22 view .LVU436 1321 .LBB368: 1376:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** *spidr = TxData; 1322 .loc 4 1376 3 view .LVU437 1323 .loc 4 1377 3 view .LVU438 1324 .loc 4 1377 10 is_stmt 0 view .LVU439 1325 0076 0023 movs r3, #0 1326 0078 0B4A ldr r2, .L73 1327 007a 9381 strh r3, [r2, #12] @ movhi 1328 .LVL116: 1329 .loc 4 1377 10 view .LVU440 1330 .LBE368: 1331 .LBE367: 2464:Src/main.c **** while((!LL_SPI_IsActiveFlag_RXNE(SPI2)) && (tmp32++ < 1000)) {} 1332 .loc 1 2464 2 is_stmt 1 view .LVU441 2465:Src/main.c **** value = LL_SPI_ReceiveData16(SPI2); 1333 .loc 1 2465 2 view .LVU442 1334 .L67: 2465:Src/main.c **** value = LL_SPI_ReceiveData16(SPI2); 1335 .loc 1 2465 64 discriminator 2 view .LVU443 2465:Src/main.c **** value = LL_SPI_ReceiveData16(SPI2); 1336 .loc 1 2465 42 discriminator 2 view .LVU444 1337 .LBB369: 1338 .LBI369: 905:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 1339 .loc 4 905 26 view .LVU445 1340 .LBB370: 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1341 .loc 4 907 3 view .LVU446 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1342 .loc 4 907 12 is_stmt 0 view .LVU447 1343 007c 0A4A ldr r2, .L73 1344 007e 9268 ldr r2, [r2, #8] 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1345 .loc 4 907 68 view .LVU448 1346 0080 12F0010F tst r2, #1 1347 0084 05D1 bne .L66 1348 .LVL117: 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1349 .loc 4 907 68 view .LVU449 1350 .LBE370: 1351 .LBE369: 2465:Src/main.c **** value = LL_SPI_ReceiveData16(SPI2); 1352 .loc 1 2465 51 discriminator 1 view .LVU450 ARM GAS /tmp/ccYgfTud.s page 145 1353 0086 5A1C adds r2, r3, #1 1354 .LVL118: 2465:Src/main.c **** value = LL_SPI_ReceiveData16(SPI2); 1355 .loc 1 2465 42 discriminator 1 view .LVU451 1356 0088 B3F57A7F cmp r3, #1000 1357 008c 01D2 bcs .L66 2465:Src/main.c **** value = LL_SPI_ReceiveData16(SPI2); 1358 .loc 1 2465 51 discriminator 1 view .LVU452 1359 008e 1346 mov r3, r2 1360 0090 F4E7 b .L67 1361 .LVL119: 1362 .L66: 2466:Src/main.c **** 1363 .loc 1 2466 2 is_stmt 1 view .LVU453 1364 .LBB371: 1365 .LBI371: 1344:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 1366 .loc 4 1344 26 view .LVU454 1367 .LBB372: 1346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1368 .loc 4 1346 3 view .LVU455 1346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1369 .loc 4 1346 21 is_stmt 0 view .LVU456 1370 0092 054B ldr r3, .L73 1371 0094 DC68 ldr r4, [r3, #12] 1372 .LVL120: 1346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1373 .loc 4 1346 10 view .LVU457 1374 0096 A4B2 uxth r4, r4 1375 .LVL121: 1346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1376 .loc 4 1346 10 view .LVU458 1377 .LBE372: 1378 .LBE371: 2468:Src/main.c **** return value; 1379 .loc 1 2468 2 is_stmt 1 view .LVU459 1380 0098 0122 movs r2, #1 1381 009a 4FF48051 mov r1, #4096 1382 009e 0348 ldr r0, .L73+4 1383 00a0 FFF7FEFF bl HAL_GPIO_WritePin 1384 .LVL122: 2469:Src/main.c **** } 1385 .loc 1 2469 2 view .LVU460 2470:Src/main.c **** 1386 .loc 1 2470 1 is_stmt 0 view .LVU461 1387 00a4 2046 mov r0, r4 1388 00a6 10BD pop {r4, pc} 1389 .LVL123: 1390 .L74: 2470:Src/main.c **** 1391 .loc 1 2470 1 view .LVU462 1392 .align 2 1393 .L73: 1394 00a8 00380040 .word 1073756160 1395 00ac 00040240 .word 1073873920 1396 .cfi_endproc 1397 .LFE1213: ARM GAS /tmp/ccYgfTud.s page 146 1399 .section .text.AD9102_CheckFlags,"ax",%progbits 1400 .align 1 1401 .syntax unified 1402 .thumb 1403 .thumb_func 1405 AD9102_CheckFlags: 1406 .LVL124: 1407 .LFB1216: 2525:Src/main.c **** uint16_t spiconfig = AD9102_ReadReg(AD9102_REG_SPICONFIG); 1408 .loc 1 2525 1 is_stmt 1 view -0 1409 .cfi_startproc 1410 @ args = 8, pretend = 0, frame = 8 1411 @ frame_needed = 0, uses_anonymous_args = 0 2525:Src/main.c **** uint16_t spiconfig = AD9102_ReadReg(AD9102_REG_SPICONFIG); 1412 .loc 1 2525 1 is_stmt 0 view .LVU464 1413 0000 2DE9F04F push {r4, r5, r6, r7, r8, r9, r10, fp, lr} 1414 .LCFI15: 1415 .cfi_def_cfa_offset 36 1416 .cfi_offset 4, -36 1417 .cfi_offset 5, -32 1418 .cfi_offset 6, -28 1419 .cfi_offset 7, -24 1420 .cfi_offset 8, -20 1421 .cfi_offset 9, -16 1422 .cfi_offset 10, -12 1423 .cfi_offset 11, -8 1424 .cfi_offset 14, -4 1425 0004 83B0 sub sp, sp, #12 1426 .LCFI16: 1427 .cfi_def_cfa_offset 48 1428 0006 0190 str r0, [sp, #4] 1429 0008 0F46 mov r7, r1 1430 000a 1546 mov r5, r2 1431 000c 1C46 mov r4, r3 1432 000e BDF834B0 ldrh fp, [sp, #52] 2526:Src/main.c **** uint16_t powercfg = AD9102_ReadReg(AD9102_REG_POWERCONFIG); 1433 .loc 1 2526 2 is_stmt 1 view .LVU465 2526:Src/main.c **** uint16_t powercfg = AD9102_ReadReg(AD9102_REG_POWERCONFIG); 1434 .loc 1 2526 23 is_stmt 0 view .LVU466 1435 0012 0020 movs r0, #0 1436 .LVL125: 2526:Src/main.c **** uint16_t powercfg = AD9102_ReadReg(AD9102_REG_POWERCONFIG); 1437 .loc 1 2526 23 view .LVU467 1438 0014 FFF7FEFF bl AD9102_ReadReg 1439 .LVL126: 2526:Src/main.c **** uint16_t powercfg = AD9102_ReadReg(AD9102_REG_POWERCONFIG); 1440 .loc 1 2526 23 view .LVU468 1441 0018 8246 mov r10, r0 1442 .LVL127: 2527:Src/main.c **** uint16_t clockcfg = AD9102_ReadReg(AD9102_REG_CLOCKCONFIG); 1443 .loc 1 2527 2 is_stmt 1 view .LVU469 2527:Src/main.c **** uint16_t clockcfg = AD9102_ReadReg(AD9102_REG_CLOCKCONFIG); 1444 .loc 1 2527 22 is_stmt 0 view .LVU470 1445 001a 0120 movs r0, #1 1446 001c FFF7FEFF bl AD9102_ReadReg 1447 .LVL128: 1448 0020 8146 mov r9, r0 ARM GAS /tmp/ccYgfTud.s page 147 1449 .LVL129: 2528:Src/main.c **** uint16_t cfg_err = AD9102_ReadReg(AD9102_REG_CFG_ERROR); 1450 .loc 1 2528 2 is_stmt 1 view .LVU471 2528:Src/main.c **** uint16_t cfg_err = AD9102_ReadReg(AD9102_REG_CFG_ERROR); 1451 .loc 1 2528 22 is_stmt 0 view .LVU472 1452 0022 0220 movs r0, #2 1453 0024 FFF7FEFF bl AD9102_ReadReg 1454 .LVL130: 1455 0028 8046 mov r8, r0 1456 .LVL131: 2529:Src/main.c **** uint16_t pat_timebase = (uint16_t)(((AD9102_PAT_TIMEBASE_HOLD_DEFAULT & 0x0Fu) << 8) | 1457 .loc 1 2529 2 is_stmt 1 view .LVU473 2529:Src/main.c **** uint16_t pat_timebase = (uint16_t)(((AD9102_PAT_TIMEBASE_HOLD_DEFAULT & 0x0Fu) << 8) | 1458 .loc 1 2529 21 is_stmt 0 view .LVU474 1459 002a 6020 movs r0, #96 1460 002c FFF7FEFF bl AD9102_ReadReg 1461 .LVL132: 2530:Src/main.c **** ((pat_base & 0x0Fu) << 4) | 1462 .loc 1 2530 2 is_stmt 1 view .LVU475 2531:Src/main.c **** (AD9102_START_DELAY_BASE_DEFAULT & 0x0Fu)); 1463 .loc 1 2531 57 is_stmt 0 view .LVU476 1464 0030 9DF83030 ldrb r3, [sp, #48] @ zero_extendqisi2 1465 0034 1B01 lsls r3, r3, #4 1466 0036 03F0F003 and r3, r3, #240 2530:Src/main.c **** ((pat_base & 0x0Fu) << 4) | 1467 .loc 1 2530 11 view .LVU477 1468 003a 40F20116 movw r6, #257 1469 003e 1E43 orrs r6, r6, r3 1470 .LVL133: 2534:Src/main.c **** { 1471 .loc 1 2534 2 is_stmt 1 view .LVU478 2534:Src/main.c **** { 1472 .loc 1 2534 5 is_stmt 0 view .LVU479 1473 0040 1CB1 cbz r4, .L88 2538:Src/main.c **** { 1474 .loc 1 2538 2 is_stmt 1 view .LVU480 2538:Src/main.c **** { 1475 .loc 1 2538 5 is_stmt 0 view .LVU481 1476 0042 3F2C cmp r4, #63 1477 0044 02D9 bls .L76 2540:Src/main.c **** } 1478 .loc 1 2540 12 view .LVU482 1479 0046 3F24 movs r4, #63 1480 .LVL134: 2540:Src/main.c **** } 1481 .loc 1 2540 12 view .LVU483 1482 0048 00E0 b .L76 1483 .LVL135: 1484 .L88: 2536:Src/main.c **** } 1485 .loc 1 2536 12 view .LVU484 1486 004a 0124 movs r4, #1 1487 .LVL136: 1488 .L76: 2542:Src/main.c **** { 1489 .loc 1 2542 2 is_stmt 1 view .LVU485 2542:Src/main.c **** { ARM GAS /tmp/ccYgfTud.s page 148 1490 .loc 1 2542 5 is_stmt 0 view .LVU486 1491 004c BBF1000F cmp fp, #0 1492 0050 01D1 bne .L77 2544:Src/main.c **** } 1493 .loc 1 2544 14 view .LVU487 1494 0052 4FF6FF7B movw fp, #65535 1495 .L77: 1496 .LVL137: 2546:Src/main.c **** ((uint16_t)(saw_type & 0x3u))); 1497 .loc 1 2546 2 is_stmt 1 view .LVU488 2547:Src/main.c **** 1498 .loc 1 2547 35 is_stmt 0 view .LVU489 1499 0056 05F00305 and r5, r5, #3 1500 .LVL138: 2546:Src/main.c **** ((uint16_t)(saw_type & 0x3u))); 1501 .loc 1 2546 71 view .LVU490 1502 005a A400 lsls r4, r4, #2 1503 .LVL139: 2546:Src/main.c **** ((uint16_t)(saw_type & 0x3u))); 1504 .loc 1 2546 71 view .LVU491 1505 005c E4B2 uxtb r4, r4 2546:Src/main.c **** ((uint16_t)(saw_type & 0x3u))); 1506 .loc 1 2546 11 view .LVU492 1507 005e 2543 orrs r5, r5, r4 1508 .LVL140: 2549:Src/main.c **** 1509 .loc 1 2549 2 is_stmt 1 view .LVU493 2552:Src/main.c **** { 1510 .loc 1 2552 2 view .LVU494 2552:Src/main.c **** { 1511 .loc 1 2552 5 is_stmt 0 view .LVU495 1512 0060 BAF1000F cmp r10, #0 1513 0064 36D1 bne .L91 2549:Src/main.c **** 1514 .loc 1 2549 10 view .LVU496 1515 0066 0124 movs r4, #1 1516 .L78: 1517 .LVL141: 2558:Src/main.c **** { 1518 .loc 1 2558 2 is_stmt 1 view .LVU497 2558:Src/main.c **** { 1519 .loc 1 2558 5 is_stmt 0 view .LVU498 1520 0068 19F4F47F tst r9, #488 1521 006c 00D0 beq .L79 2560:Src/main.c **** } 1522 .loc 1 2560 6 view .LVU499 1523 006e 0024 movs r4, #0 1524 .LVL142: 1525 .L79: 2564:Src/main.c **** { 1526 .loc 1 2564 2 is_stmt 1 view .LVU500 2564:Src/main.c **** { 1527 .loc 1 2564 5 is_stmt 0 view .LVU501 1528 0070 18F40E6F tst r8, #2272 1529 0074 00D0 beq .L80 2566:Src/main.c **** } 1530 .loc 1 2566 6 view .LVU502 ARM GAS /tmp/ccYgfTud.s page 149 1531 0076 0024 movs r4, #0 1532 .LVL143: 1533 .L80: 2570:Src/main.c **** { 1534 .loc 1 2570 2 is_stmt 1 view .LVU503 2570:Src/main.c **** { 1535 .loc 1 2570 5 is_stmt 0 view .LVU504 1536 0078 10F03F0F tst r0, #63 1537 007c 00D0 beq .L81 2572:Src/main.c **** } 1538 .loc 1 2572 6 view .LVU505 1539 007e 0024 movs r4, #0 1540 .LVL144: 1541 .L81: 2575:Src/main.c **** { 1542 .loc 1 2575 2 is_stmt 1 view .LVU506 2575:Src/main.c **** { 1543 .loc 1 2575 5 is_stmt 0 view .LVU507 1544 0080 27B1 cbz r7, .L82 2575:Src/main.c **** { 1545 .loc 1 2575 17 discriminator 1 view .LVU508 1546 0082 019B ldr r3, [sp, #4] 1547 0084 13F0010F tst r3, #1 1548 0088 00D1 bne .L82 2577:Src/main.c **** } 1549 .loc 1 2577 6 view .LVU509 1550 008a 0024 movs r4, #0 1551 .LVL145: 1552 .L82: 2580:Src/main.c **** { 1553 .loc 1 2580 2 is_stmt 1 view .LVU510 2580:Src/main.c **** { 1554 .loc 1 2580 6 is_stmt 0 view .LVU511 1555 008c 2720 movs r0, #39 1556 .LVL146: 2580:Src/main.c **** { 1557 .loc 1 2580 6 view .LVU512 1558 008e FFF7FEFF bl AD9102_ReadReg 1559 .LVL147: 2580:Src/main.c **** { 1560 .loc 1 2580 5 discriminator 1 view .LVU513 1561 0092 43F21223 movw r3, #12818 1562 0096 9842 cmp r0, r3 1563 0098 00D0 beq .L83 2582:Src/main.c **** } 1564 .loc 1 2582 6 view .LVU514 1565 009a 0024 movs r4, #0 1566 .LVL148: 1567 .L83: 2584:Src/main.c **** { 1568 .loc 1 2584 2 is_stmt 1 view .LVU515 2584:Src/main.c **** { 1569 .loc 1 2584 6 is_stmt 0 view .LVU516 1570 009c 2820 movs r0, #40 1571 009e FFF7FEFF bl AD9102_ReadReg 1572 .LVL149: 2584:Src/main.c **** { ARM GAS /tmp/ccYgfTud.s page 150 1573 .loc 1 2584 5 discriminator 1 view .LVU517 1574 00a2 B042 cmp r0, r6 1575 00a4 00D0 beq .L84 2586:Src/main.c **** } 1576 .loc 1 2586 6 view .LVU518 1577 00a6 0024 movs r4, #0 1578 .LVL150: 1579 .L84: 2588:Src/main.c **** { 1580 .loc 1 2588 2 is_stmt 1 view .LVU519 2588:Src/main.c **** { 1581 .loc 1 2588 6 is_stmt 0 view .LVU520 1582 00a8 2920 movs r0, #41 1583 00aa FFF7FEFF bl AD9102_ReadReg 1584 .LVL151: 2588:Src/main.c **** { 1585 .loc 1 2588 5 discriminator 1 view .LVU521 1586 00ae 5845 cmp r0, fp 1587 00b0 00D0 beq .L85 2590:Src/main.c **** } 1588 .loc 1 2590 6 view .LVU522 1589 00b2 0024 movs r4, #0 1590 .LVL152: 1591 .L85: 2592:Src/main.c **** { 1592 .loc 1 2592 2 is_stmt 1 view .LVU523 2592:Src/main.c **** { 1593 .loc 1 2592 6 is_stmt 0 view .LVU524 1594 00b4 1F20 movs r0, #31 1595 00b6 FFF7FEFF bl AD9102_ReadReg 1596 .LVL153: 2592:Src/main.c **** { 1597 .loc 1 2592 5 discriminator 1 view .LVU525 1598 00ba 00B1 cbz r0, .L86 2594:Src/main.c **** } 1599 .loc 1 2594 6 view .LVU526 1600 00bc 0024 movs r4, #0 1601 .LVL154: 1602 .L86: 2596:Src/main.c **** { 1603 .loc 1 2596 2 is_stmt 1 view .LVU527 2596:Src/main.c **** { 1604 .loc 1 2596 6 is_stmt 0 view .LVU528 1605 00be 3720 movs r0, #55 1606 00c0 FFF7FEFF bl AD9102_ReadReg 1607 .LVL155: 2596:Src/main.c **** { 1608 .loc 1 2596 5 discriminator 1 view .LVU529 1609 00c4 A842 cmp r0, r5 1610 00c6 00D0 beq .L87 2598:Src/main.c **** } 1611 .loc 1 2598 6 view .LVU530 1612 00c8 0024 movs r4, #0 1613 .LVL156: 1614 .L87: 2601:Src/main.c **** } 1615 .loc 1 2601 2 is_stmt 1 view .LVU531 ARM GAS /tmp/ccYgfTud.s page 151 2602:Src/main.c **** 1616 .loc 1 2602 1 is_stmt 0 view .LVU532 1617 00ca 84F00100 eor r0, r4, #1 1618 00ce 03B0 add sp, sp, #12 1619 .LCFI17: 1620 .cfi_remember_state 1621 .cfi_def_cfa_offset 36 1622 @ sp needed 1623 00d0 BDE8F08F pop {r4, r5, r6, r7, r8, r9, r10, fp, pc} 1624 .LVL157: 1625 .L91: 1626 .LCFI18: 1627 .cfi_restore_state 2554:Src/main.c **** } 1628 .loc 1 2554 6 view .LVU533 1629 00d4 0024 movs r4, #0 1630 00d6 C7E7 b .L78 1631 .cfi_endproc 1632 .LFE1216: 1634 .section .text.AD9102_Apply,"ax",%progbits 1635 .align 1 1636 .syntax unified 1637 .thumb 1638 .thumb_func 1640 AD9102_Apply: 1641 .LVL158: 1642 .LFB1215: 2481:Src/main.c **** if (enable) 1643 .loc 1 2481 1 is_stmt 1 view -0 1644 .cfi_startproc 1645 @ args = 4, pretend = 0, frame = 8 1646 @ frame_needed = 0, uses_anonymous_args = 0 2481:Src/main.c **** if (enable) 1647 .loc 1 2481 1 is_stmt 0 view .LVU535 1648 0000 30B5 push {r4, r5, lr} 1649 .LCFI19: 1650 .cfi_def_cfa_offset 12 1651 .cfi_offset 4, -12 1652 .cfi_offset 5, -8 1653 .cfi_offset 14, -4 1654 0002 83B0 sub sp, sp, #12 1655 .LCFI20: 1656 .cfi_def_cfa_offset 24 2482:Src/main.c **** { 1657 .loc 1 2482 2 is_stmt 1 view .LVU536 2482:Src/main.c **** { 1658 .loc 1 2482 5 is_stmt 0 view .LVU537 1659 0004 0029 cmp r1, #0 1660 0006 4AD0 beq .L103 1661 .LBB373: 2484:Src/main.c **** uint16_t pat_timebase; 1662 .loc 1 2484 3 is_stmt 1 view .LVU538 2485:Src/main.c **** 1663 .loc 1 2485 3 view .LVU539 2487:Src/main.c **** { 1664 .loc 1 2487 3 view .LVU540 2487:Src/main.c **** { ARM GAS /tmp/ccYgfTud.s page 152 1665 .loc 1 2487 6 is_stmt 0 view .LVU541 1666 0008 1AB1 cbz r2, .L108 2491:Src/main.c **** { 1667 .loc 1 2491 3 is_stmt 1 view .LVU542 2491:Src/main.c **** { 1668 .loc 1 2491 6 is_stmt 0 view .LVU543 1669 000a 3F2A cmp r2, #63 1670 000c 02D9 bls .L104 2493:Src/main.c **** } 1671 .loc 1 2493 13 view .LVU544 1672 000e 3F22 movs r2, #63 1673 .LVL159: 2493:Src/main.c **** } 1674 .loc 1 2493 13 view .LVU545 1675 0010 00E0 b .L104 1676 .LVL160: 1677 .L108: 2489:Src/main.c **** } 1678 .loc 1 2489 13 view .LVU546 1679 0012 0122 movs r2, #1 1680 .LVL161: 1681 .L104: 2495:Src/main.c **** ((uint16_t)(saw_type & 0x3u))); 1682 .loc 1 2495 3 is_stmt 1 view .LVU547 2496:Src/main.c **** pat_timebase = (uint16_t)(((AD9102_PAT_TIMEBASE_HOLD_DEFAULT & 0x0Fu) << 8) | 1683 .loc 1 2496 25 is_stmt 0 view .LVU548 1684 0014 00F00300 and r0, r0, #3 1685 .LVL162: 2495:Src/main.c **** ((uint16_t)(saw_type & 0x3u))); 1686 .loc 1 2495 60 view .LVU549 1687 0018 9200 lsls r2, r2, #2 1688 .LVL163: 2495:Src/main.c **** ((uint16_t)(saw_type & 0x3u))); 1689 .loc 1 2495 60 view .LVU550 1690 001a D2B2 uxtb r2, r2 2495:Src/main.c **** ((uint16_t)(saw_type & 0x3u))); 1691 .loc 1 2495 11 view .LVU551 1692 001c 40EA0204 orr r4, r0, r2 1693 .LVL164: 2497:Src/main.c **** ((pat_base & 0x0Fu) << 4) | 1694 .loc 1 2497 3 is_stmt 1 view .LVU552 2498:Src/main.c **** (AD9102_START_DELAY_BASE_DEFAULT & 0x0Fu)); 1695 .loc 1 2498 49 is_stmt 0 view .LVU553 1696 0020 1B01 lsls r3, r3, #4 1697 .LVL165: 2498:Src/main.c **** (AD9102_START_DELAY_BASE_DEFAULT & 0x0Fu)); 1698 .loc 1 2498 49 view .LVU554 1699 0022 03F0F003 and r3, r3, #240 2497:Src/main.c **** ((pat_base & 0x0Fu) << 4) | 1700 .loc 1 2497 16 view .LVU555 1701 0026 40F20115 movw r5, #257 1702 002a 1D43 orrs r5, r5, r3 1703 .LVL166: 2501:Src/main.c **** AD9102_WriteReg(AD9102_REG_SAW_CONFIG, saw_cfg); 1704 .loc 1 2501 3 is_stmt 1 view .LVU556 1705 002c 43F21221 movw r1, #12818 1706 .LVL167: ARM GAS /tmp/ccYgfTud.s page 153 2501:Src/main.c **** AD9102_WriteReg(AD9102_REG_SAW_CONFIG, saw_cfg); 1707 .loc 1 2501 3 is_stmt 0 view .LVU557 1708 0030 2720 movs r0, #39 1709 0032 FFF7FEFF bl AD9102_WriteReg 1710 .LVL168: 2502:Src/main.c **** AD9102_WriteReg(AD9102_REG_PAT_TIMEBASE, pat_timebase); 1711 .loc 1 2502 3 is_stmt 1 view .LVU558 1712 0036 2146 mov r1, r4 1713 0038 3720 movs r0, #55 1714 003a FFF7FEFF bl AD9102_WriteReg 1715 .LVL169: 2503:Src/main.c **** AD9102_WriteReg(AD9102_REG_PAT_PERIOD, pat_period); 1716 .loc 1 2503 3 view .LVU559 1717 003e 2946 mov r1, r5 1718 0040 2820 movs r0, #40 1719 0042 FFF7FEFF bl AD9102_WriteReg 1720 .LVL170: 2504:Src/main.c **** AD9102_WriteReg(AD9102_REG_PAT_TYPE, 0x0000u); // continuous pattern repeat 1721 .loc 1 2504 3 view .LVU560 1722 0046 BDF81810 ldrh r1, [sp, #24] 1723 004a 2920 movs r0, #41 1724 004c FFF7FEFF bl AD9102_WriteReg 1725 .LVL171: 2505:Src/main.c **** 1726 .loc 1 2505 3 view .LVU561 1727 0050 0021 movs r1, #0 1728 0052 1F20 movs r0, #31 1729 0054 FFF7FEFF bl AD9102_WriteReg 1730 .LVL172: 2509:Src/main.c **** AD9102_WriteReg(AD9102_REG_PAT_STATUS, AD9102_PAT_STATUS_RUN); 1731 .loc 1 2509 3 view .LVU562 1732 0058 0122 movs r2, #1 1733 005a 4FF40061 mov r1, #2048 1734 005e 1548 ldr r0, .L111 1735 0060 FFF7FEFF bl HAL_GPIO_WritePin 1736 .LVL173: 2510:Src/main.c **** AD9102_WriteReg(AD9102_REG_RAMUPDATE, 0x0001u); 1737 .loc 1 2510 3 view .LVU563 1738 0064 0121 movs r1, #1 1739 0066 1E20 movs r0, #30 1740 0068 FFF7FEFF bl AD9102_WriteReg 1741 .LVL174: 2511:Src/main.c **** for (volatile uint32_t d = 0; d < 1000; d++) {} 1742 .loc 1 2511 3 view .LVU564 1743 006c 0121 movs r1, #1 1744 006e 1D20 movs r0, #29 1745 0070 FFF7FEFF bl AD9102_WriteReg 1746 .LVL175: 2512:Src/main.c **** HAL_GPIO_WritePin(AD9102_TRIG_GPIO_Port, AD9102_TRIG_Pin, GPIO_PIN_RESET); 1747 .loc 1 2512 3 view .LVU565 1748 .LBB374: 2512:Src/main.c **** HAL_GPIO_WritePin(AD9102_TRIG_GPIO_Port, AD9102_TRIG_Pin, GPIO_PIN_RESET); 1749 .loc 1 2512 8 view .LVU566 2512:Src/main.c **** HAL_GPIO_WritePin(AD9102_TRIG_GPIO_Port, AD9102_TRIG_Pin, GPIO_PIN_RESET); 1750 .loc 1 2512 26 is_stmt 0 view .LVU567 1751 0074 0023 movs r3, #0 1752 0076 0193 str r3, [sp, #4] ARM GAS /tmp/ccYgfTud.s page 154 2512:Src/main.c **** HAL_GPIO_WritePin(AD9102_TRIG_GPIO_Port, AD9102_TRIG_Pin, GPIO_PIN_RESET); 1753 .loc 1 2512 3 view .LVU568 1754 0078 02E0 b .L105 1755 .L106: 2512:Src/main.c **** HAL_GPIO_WritePin(AD9102_TRIG_GPIO_Port, AD9102_TRIG_Pin, GPIO_PIN_RESET); 1756 .loc 1 2512 49 is_stmt 1 discriminator 3 view .LVU569 2512:Src/main.c **** HAL_GPIO_WritePin(AD9102_TRIG_GPIO_Port, AD9102_TRIG_Pin, GPIO_PIN_RESET); 1757 .loc 1 2512 44 discriminator 3 view .LVU570 1758 007a 019B ldr r3, [sp, #4] 1759 007c 0133 adds r3, r3, #1 1760 007e 0193 str r3, [sp, #4] 1761 .L105: 2512:Src/main.c **** HAL_GPIO_WritePin(AD9102_TRIG_GPIO_Port, AD9102_TRIG_Pin, GPIO_PIN_RESET); 1762 .loc 1 2512 35 discriminator 1 view .LVU571 1763 0080 019B ldr r3, [sp, #4] 1764 0082 B3F57A7F cmp r3, #1000 1765 0086 F8D3 bcc .L106 1766 .LBE374: 2513:Src/main.c **** } 1767 .loc 1 2513 3 view .LVU572 1768 0088 0022 movs r2, #0 1769 008a 4FF40061 mov r1, #2048 1770 008e 0948 ldr r0, .L111 1771 0090 FFF7FEFF bl HAL_GPIO_WritePin 1772 .LVL176: 1773 .L107: 2513:Src/main.c **** } 1774 .loc 1 2513 3 is_stmt 0 view .LVU573 1775 .LBE373: 2521:Src/main.c **** } 1776 .loc 1 2521 2 is_stmt 1 view .LVU574 2521:Src/main.c **** } 1777 .loc 1 2521 9 is_stmt 0 view .LVU575 1778 0094 1E20 movs r0, #30 1779 0096 FFF7FEFF bl AD9102_ReadReg 1780 .LVL177: 2522:Src/main.c **** 1781 .loc 1 2522 1 view .LVU576 1782 009a 03B0 add sp, sp, #12 1783 .LCFI21: 1784 .cfi_remember_state 1785 .cfi_def_cfa_offset 12 1786 @ sp needed 1787 009c 30BD pop {r4, r5, pc} 1788 .LVL178: 1789 .L103: 1790 .LCFI22: 1791 .cfi_restore_state 2517:Src/main.c **** HAL_GPIO_WritePin(AD9102_TRIG_GPIO_Port, AD9102_TRIG_Pin, GPIO_PIN_SET); 1792 .loc 1 2517 3 is_stmt 1 view .LVU577 1793 009e 0021 movs r1, #0 1794 .LVL179: 2517:Src/main.c **** HAL_GPIO_WritePin(AD9102_TRIG_GPIO_Port, AD9102_TRIG_Pin, GPIO_PIN_SET); 1795 .loc 1 2517 3 is_stmt 0 view .LVU578 1796 00a0 1E20 movs r0, #30 1797 .LVL180: 2517:Src/main.c **** HAL_GPIO_WritePin(AD9102_TRIG_GPIO_Port, AD9102_TRIG_Pin, GPIO_PIN_SET); ARM GAS /tmp/ccYgfTud.s page 155 1798 .loc 1 2517 3 view .LVU579 1799 00a2 FFF7FEFF bl AD9102_WriteReg 1800 .LVL181: 2518:Src/main.c **** } 1801 .loc 1 2518 3 is_stmt 1 view .LVU580 1802 00a6 0122 movs r2, #1 1803 00a8 4FF40061 mov r1, #2048 1804 00ac 0148 ldr r0, .L111 1805 00ae FFF7FEFF bl HAL_GPIO_WritePin 1806 .LVL182: 1807 00b2 EFE7 b .L107 1808 .L112: 1809 .align 2 1810 .L111: 1811 00b4 000C0240 .word 1073875968 1812 .cfi_endproc 1813 .LFE1215: 1815 .section .text.OUT_trigger,"ax",%progbits 1816 .align 1 1817 .syntax unified 1818 .thumb 1819 .thumb_func 1821 OUT_trigger: 1822 .LVL183: 1823 .LFB1210: 2346:Src/main.c **** switch (out_n) 1824 .loc 1 2346 1 view -0 1825 .cfi_startproc 1826 @ args = 0, pretend = 0, frame = 0 1827 @ frame_needed = 0, uses_anonymous_args = 0 2346:Src/main.c **** switch (out_n) 1828 .loc 1 2346 1 is_stmt 0 view .LVU582 1829 0000 10B5 push {r4, lr} 1830 .LCFI23: 1831 .cfi_def_cfa_offset 8 1832 .cfi_offset 4, -8 1833 .cfi_offset 14, -4 2347:Src/main.c **** { 1834 .loc 1 2347 2 is_stmt 1 view .LVU583 1835 0002 0928 cmp r0, #9 1836 0004 13D8 bhi .L113 1837 0006 DFE800F0 tbb [pc, r0] 1838 .L116: 1839 000a 05 .byte (.L125-.L116)/2 1840 000b 13 .byte (.L124-.L116)/2 1841 000c 21 .byte (.L123-.L116)/2 1842 000d 2F .byte (.L122-.L116)/2 1843 000e 3D .byte (.L121-.L116)/2 1844 000f 4B .byte (.L120-.L116)/2 1845 0010 59 .byte (.L119-.L116)/2 1846 0011 65 .byte (.L118-.L116)/2 1847 0012 71 .byte (.L117-.L116)/2 1848 0013 7D .byte (.L115-.L116)/2 1849 .p2align 1 1850 .L125: 2350:Src/main.c **** HAL_GPIO_WritePin(OUT_0_GPIO_Port, OUT_0_Pin, GPIO_PIN_RESET); 1851 .loc 1 2350 3 view .LVU584 ARM GAS /tmp/ccYgfTud.s page 156 1852 0014 414C ldr r4, .L128 1853 0016 0122 movs r2, #1 1854 0018 4FF48061 mov r1, #1024 1855 001c 2046 mov r0, r4 1856 .LVL184: 2350:Src/main.c **** HAL_GPIO_WritePin(OUT_0_GPIO_Port, OUT_0_Pin, GPIO_PIN_RESET); 1857 .loc 1 2350 3 is_stmt 0 view .LVU585 1858 001e FFF7FEFF bl HAL_GPIO_WritePin 1859 .LVL185: 2351:Src/main.c **** break; 1860 .loc 1 2351 3 is_stmt 1 view .LVU586 1861 0022 0022 movs r2, #0 1862 0024 4FF48061 mov r1, #1024 1863 0028 2046 mov r0, r4 1864 002a FFF7FEFF bl HAL_GPIO_WritePin 1865 .LVL186: 2352:Src/main.c **** 1866 .loc 1 2352 2 view .LVU587 1867 .L113: 2399:Src/main.c **** 1868 .loc 1 2399 1 is_stmt 0 view .LVU588 1869 002e 10BD pop {r4, pc} 1870 .LVL187: 1871 .L124: 2355:Src/main.c **** HAL_GPIO_WritePin(OUT_1_GPIO_Port, OUT_1_Pin, GPIO_PIN_RESET); 1872 .loc 1 2355 3 is_stmt 1 view .LVU589 1873 0030 3A4C ldr r4, .L128 1874 0032 0122 movs r2, #1 1875 0034 4FF40061 mov r1, #2048 1876 0038 2046 mov r0, r4 1877 .LVL188: 2355:Src/main.c **** HAL_GPIO_WritePin(OUT_1_GPIO_Port, OUT_1_Pin, GPIO_PIN_RESET); 1878 .loc 1 2355 3 is_stmt 0 view .LVU590 1879 003a FFF7FEFF bl HAL_GPIO_WritePin 1880 .LVL189: 2356:Src/main.c **** break; 1881 .loc 1 2356 3 is_stmt 1 view .LVU591 1882 003e 0022 movs r2, #0 1883 0040 4FF40061 mov r1, #2048 1884 0044 2046 mov r0, r4 1885 0046 FFF7FEFF bl HAL_GPIO_WritePin 1886 .LVL190: 2357:Src/main.c **** 1887 .loc 1 2357 2 view .LVU592 1888 004a F0E7 b .L113 1889 .LVL191: 1890 .L123: 2360:Src/main.c **** HAL_GPIO_WritePin(OUT_2_GPIO_Port, OUT_2_Pin, GPIO_PIN_RESET); 1891 .loc 1 2360 3 view .LVU593 1892 004c 334C ldr r4, .L128 1893 004e 0122 movs r2, #1 1894 0050 4FF48051 mov r1, #4096 1895 0054 2046 mov r0, r4 1896 .LVL192: 2360:Src/main.c **** HAL_GPIO_WritePin(OUT_2_GPIO_Port, OUT_2_Pin, GPIO_PIN_RESET); 1897 .loc 1 2360 3 is_stmt 0 view .LVU594 1898 0056 FFF7FEFF bl HAL_GPIO_WritePin ARM GAS /tmp/ccYgfTud.s page 157 1899 .LVL193: 2361:Src/main.c **** break; 1900 .loc 1 2361 3 is_stmt 1 view .LVU595 1901 005a 0022 movs r2, #0 1902 005c 4FF48051 mov r1, #4096 1903 0060 2046 mov r0, r4 1904 0062 FFF7FEFF bl HAL_GPIO_WritePin 1905 .LVL194: 2362:Src/main.c **** 1906 .loc 1 2362 2 view .LVU596 1907 0066 E2E7 b .L113 1908 .LVL195: 1909 .L122: 2365:Src/main.c **** HAL_GPIO_WritePin(OUT_3_GPIO_Port, OUT_3_Pin, GPIO_PIN_RESET); 1910 .loc 1 2365 3 view .LVU597 1911 0068 2C4C ldr r4, .L128 1912 006a 0122 movs r2, #1 1913 006c 4FF40051 mov r1, #8192 1914 0070 2046 mov r0, r4 1915 .LVL196: 2365:Src/main.c **** HAL_GPIO_WritePin(OUT_3_GPIO_Port, OUT_3_Pin, GPIO_PIN_RESET); 1916 .loc 1 2365 3 is_stmt 0 view .LVU598 1917 0072 FFF7FEFF bl HAL_GPIO_WritePin 1918 .LVL197: 2366:Src/main.c **** break; 1919 .loc 1 2366 3 is_stmt 1 view .LVU599 1920 0076 0022 movs r2, #0 1921 0078 4FF40051 mov r1, #8192 1922 007c 2046 mov r0, r4 1923 007e FFF7FEFF bl HAL_GPIO_WritePin 1924 .LVL198: 2367:Src/main.c **** 1925 .loc 1 2367 2 view .LVU600 1926 0082 D4E7 b .L113 1927 .LVL199: 1928 .L121: 2370:Src/main.c **** HAL_GPIO_WritePin(OUT_4_GPIO_Port, OUT_4_Pin, GPIO_PIN_RESET); 1929 .loc 1 2370 3 view .LVU601 1930 0084 254C ldr r4, .L128 1931 0086 0122 movs r2, #1 1932 0088 4FF48041 mov r1, #16384 1933 008c 2046 mov r0, r4 1934 .LVL200: 2370:Src/main.c **** HAL_GPIO_WritePin(OUT_4_GPIO_Port, OUT_4_Pin, GPIO_PIN_RESET); 1935 .loc 1 2370 3 is_stmt 0 view .LVU602 1936 008e FFF7FEFF bl HAL_GPIO_WritePin 1937 .LVL201: 2371:Src/main.c **** break; 1938 .loc 1 2371 3 is_stmt 1 view .LVU603 1939 0092 0022 movs r2, #0 1940 0094 4FF48041 mov r1, #16384 1941 0098 2046 mov r0, r4 1942 009a FFF7FEFF bl HAL_GPIO_WritePin 1943 .LVL202: 2372:Src/main.c **** 1944 .loc 1 2372 2 view .LVU604 1945 009e C6E7 b .L113 ARM GAS /tmp/ccYgfTud.s page 158 1946 .LVL203: 1947 .L120: 2375:Src/main.c **** HAL_GPIO_WritePin(OUT_5_GPIO_Port, OUT_5_Pin, GPIO_PIN_RESET); 1948 .loc 1 2375 3 view .LVU605 1949 00a0 1E4C ldr r4, .L128 1950 00a2 0122 movs r2, #1 1951 00a4 4FF40041 mov r1, #32768 1952 00a8 2046 mov r0, r4 1953 .LVL204: 2375:Src/main.c **** HAL_GPIO_WritePin(OUT_5_GPIO_Port, OUT_5_Pin, GPIO_PIN_RESET); 1954 .loc 1 2375 3 is_stmt 0 view .LVU606 1955 00aa FFF7FEFF bl HAL_GPIO_WritePin 1956 .LVL205: 2376:Src/main.c **** break; 1957 .loc 1 2376 3 is_stmt 1 view .LVU607 1958 00ae 0022 movs r2, #0 1959 00b0 4FF40041 mov r1, #32768 1960 00b4 2046 mov r0, r4 1961 00b6 FFF7FEFF bl HAL_GPIO_WritePin 1962 .LVL206: 2377:Src/main.c **** 1963 .loc 1 2377 2 view .LVU608 1964 00ba B8E7 b .L113 1965 .LVL207: 1966 .L119: 2380:Src/main.c **** HAL_GPIO_WritePin(OUT_6_GPIO_Port, OUT_6_Pin, GPIO_PIN_RESET); 1967 .loc 1 2380 3 view .LVU609 1968 00bc 184C ldr r4, .L128+4 1969 00be 0122 movs r2, #1 1970 00c0 1021 movs r1, #16 1971 00c2 2046 mov r0, r4 1972 .LVL208: 2380:Src/main.c **** HAL_GPIO_WritePin(OUT_6_GPIO_Port, OUT_6_Pin, GPIO_PIN_RESET); 1973 .loc 1 2380 3 is_stmt 0 view .LVU610 1974 00c4 FFF7FEFF bl HAL_GPIO_WritePin 1975 .LVL209: 2381:Src/main.c **** break; 1976 .loc 1 2381 3 is_stmt 1 view .LVU611 1977 00c8 0022 movs r2, #0 1978 00ca 1021 movs r1, #16 1979 00cc 2046 mov r0, r4 1980 00ce FFF7FEFF bl HAL_GPIO_WritePin 1981 .LVL210: 2382:Src/main.c **** 1982 .loc 1 2382 2 view .LVU612 1983 00d2 ACE7 b .L113 1984 .LVL211: 1985 .L118: 2385:Src/main.c **** HAL_GPIO_WritePin(OUT_7_GPIO_Port, OUT_7_Pin, GPIO_PIN_RESET); 1986 .loc 1 2385 3 view .LVU613 1987 00d4 124C ldr r4, .L128+4 1988 00d6 0122 movs r2, #1 1989 00d8 2021 movs r1, #32 1990 00da 2046 mov r0, r4 1991 .LVL212: 2385:Src/main.c **** HAL_GPIO_WritePin(OUT_7_GPIO_Port, OUT_7_Pin, GPIO_PIN_RESET); 1992 .loc 1 2385 3 is_stmt 0 view .LVU614 ARM GAS /tmp/ccYgfTud.s page 159 1993 00dc FFF7FEFF bl HAL_GPIO_WritePin 1994 .LVL213: 2386:Src/main.c **** break; 1995 .loc 1 2386 3 is_stmt 1 view .LVU615 1996 00e0 0022 movs r2, #0 1997 00e2 2021 movs r1, #32 1998 00e4 2046 mov r0, r4 1999 00e6 FFF7FEFF bl HAL_GPIO_WritePin 2000 .LVL214: 2387:Src/main.c **** 2001 .loc 1 2387 2 view .LVU616 2002 00ea A0E7 b .L113 2003 .LVL215: 2004 .L117: 2390:Src/main.c **** HAL_GPIO_WritePin(OUT_8_GPIO_Port, OUT_8_Pin, GPIO_PIN_RESET); 2005 .loc 1 2390 3 view .LVU617 2006 00ec 0C4C ldr r4, .L128+4 2007 00ee 0122 movs r2, #1 2008 00f0 4021 movs r1, #64 2009 00f2 2046 mov r0, r4 2010 .LVL216: 2390:Src/main.c **** HAL_GPIO_WritePin(OUT_8_GPIO_Port, OUT_8_Pin, GPIO_PIN_RESET); 2011 .loc 1 2390 3 is_stmt 0 view .LVU618 2012 00f4 FFF7FEFF bl HAL_GPIO_WritePin 2013 .LVL217: 2391:Src/main.c **** break; 2014 .loc 1 2391 3 is_stmt 1 view .LVU619 2015 00f8 0022 movs r2, #0 2016 00fa 4021 movs r1, #64 2017 00fc 2046 mov r0, r4 2018 00fe FFF7FEFF bl HAL_GPIO_WritePin 2019 .LVL218: 2392:Src/main.c **** 2020 .loc 1 2392 2 view .LVU620 2021 0102 94E7 b .L113 2022 .LVL219: 2023 .L115: 2395:Src/main.c **** HAL_GPIO_WritePin(OUT_9_GPIO_Port, OUT_9_Pin, GPIO_PIN_RESET); 2024 .loc 1 2395 3 view .LVU621 2025 0104 064C ldr r4, .L128+4 2026 0106 0122 movs r2, #1 2027 0108 8021 movs r1, #128 2028 010a 2046 mov r0, r4 2029 .LVL220: 2395:Src/main.c **** HAL_GPIO_WritePin(OUT_9_GPIO_Port, OUT_9_Pin, GPIO_PIN_RESET); 2030 .loc 1 2395 3 is_stmt 0 view .LVU622 2031 010c FFF7FEFF bl HAL_GPIO_WritePin 2032 .LVL221: 2396:Src/main.c **** break; 2033 .loc 1 2396 3 is_stmt 1 view .LVU623 2034 0110 0022 movs r2, #0 2035 0112 8021 movs r1, #128 2036 0114 2046 mov r0, r4 2037 0116 FFF7FEFF bl HAL_GPIO_WritePin 2038 .LVL222: 2397:Src/main.c **** } 2039 .loc 1 2397 2 view .LVU624 ARM GAS /tmp/ccYgfTud.s page 160 2399:Src/main.c **** 2040 .loc 1 2399 1 is_stmt 0 view .LVU625 2041 011a 88E7 b .L113 2042 .L129: 2043 .align 2 2044 .L128: 2045 011c 00180240 .word 1073879040 2046 0120 00040240 .word 1073873920 2047 .cfi_endproc 2048 .LFE1210: 2050 .section .text.MPhD_T,"ax",%progbits 2051 .align 1 2052 .syntax unified 2053 .thumb 2054 .thumb_func 2056 MPhD_T: 2057 .LVL223: 2058 .LFB1218: 2670:Src/main.c **** uint16_t P; 2059 .loc 1 2670 1 is_stmt 1 view -0 2060 .cfi_startproc 2061 @ args = 0, pretend = 0, frame = 0 2062 @ frame_needed = 0, uses_anonymous_args = 0 2670:Src/main.c **** uint16_t P; 2063 .loc 1 2670 1 is_stmt 0 view .LVU627 2064 0000 38B5 push {r3, r4, r5, lr} 2065 .LCFI24: 2066 .cfi_def_cfa_offset 16 2067 .cfi_offset 3, -16 2068 .cfi_offset 4, -12 2069 .cfi_offset 5, -8 2070 .cfi_offset 14, -4 2071 0002 0446 mov r4, r0 2671:Src/main.c **** uint32_t tmp32; 2072 .loc 1 2671 2 is_stmt 1 view .LVU628 2672:Src/main.c **** HAL_GPIO_WritePin(SPI4_CNV_GPIO_Port, SPI4_CNV_Pin, GPIO_PIN_RESET);//Prepare conversion 2073 .loc 1 2672 2 view .LVU629 2673:Src/main.c **** HAL_GPIO_WritePin(SPI5_CNV_GPIO_Port, SPI5_CNV_Pin, GPIO_PIN_RESET);//Prepare conversion 2074 .loc 1 2673 2 view .LVU630 2075 0004 0022 movs r2, #0 2076 0006 4FF48041 mov r1, #16384 2077 000a 8148 ldr r0, .L171 2078 .LVL224: 2673:Src/main.c **** HAL_GPIO_WritePin(SPI5_CNV_GPIO_Port, SPI5_CNV_Pin, GPIO_PIN_RESET);//Prepare conversion 2079 .loc 1 2673 2 is_stmt 0 view .LVU631 2080 000c FFF7FEFF bl HAL_GPIO_WritePin 2081 .LVL225: 2674:Src/main.c **** tmp32=0; 2082 .loc 1 2674 2 is_stmt 1 view .LVU632 2083 0010 0022 movs r2, #0 2084 0012 4FF40071 mov r1, #512 2085 0016 7F48 ldr r0, .L171+4 2086 0018 FFF7FEFF bl HAL_GPIO_WritePin 2087 .LVL226: 2675:Src/main.c **** while(tmp32<500){tmp32++;} 2088 .loc 1 2675 2 view .LVU633 2676:Src/main.c **** HAL_GPIO_WritePin(SPI4_CNV_GPIO_Port, SPI4_CNV_Pin, GPIO_PIN_SET);//Stop acqusition & start conver ARM GAS /tmp/ccYgfTud.s page 161 2089 .loc 1 2676 2 view .LVU634 2675:Src/main.c **** while(tmp32<500){tmp32++;} 2090 .loc 1 2675 7 is_stmt 0 view .LVU635 2091 001c 0023 movs r3, #0 2676:Src/main.c **** HAL_GPIO_WritePin(SPI4_CNV_GPIO_Port, SPI4_CNV_Pin, GPIO_PIN_SET);//Stop acqusition & start conver 2092 .loc 1 2676 7 view .LVU636 2093 001e 00E0 b .L131 2094 .LVL227: 2095 .L132: 2676:Src/main.c **** HAL_GPIO_WritePin(SPI4_CNV_GPIO_Port, SPI4_CNV_Pin, GPIO_PIN_SET);//Stop acqusition & start conver 2096 .loc 1 2676 19 is_stmt 1 discriminator 2 view .LVU637 2676:Src/main.c **** HAL_GPIO_WritePin(SPI4_CNV_GPIO_Port, SPI4_CNV_Pin, GPIO_PIN_SET);//Stop acqusition & start conver 2097 .loc 1 2676 24 is_stmt 0 discriminator 2 view .LVU638 2098 0020 0133 adds r3, r3, #1 2099 .LVL228: 2100 .L131: 2676:Src/main.c **** HAL_GPIO_WritePin(SPI4_CNV_GPIO_Port, SPI4_CNV_Pin, GPIO_PIN_SET);//Stop acqusition & start conver 2101 .loc 1 2676 13 is_stmt 1 discriminator 1 view .LVU639 2102 0022 B3F5FA7F cmp r3, #500 2103 0026 FBD3 bcc .L132 2677:Src/main.c **** HAL_GPIO_WritePin(SPI5_CNV_GPIO_Port, SPI5_CNV_Pin, GPIO_PIN_SET);//Stop acqusition & start conver 2104 .loc 1 2677 2 view .LVU640 2105 0028 0122 movs r2, #1 2106 002a 4FF48041 mov r1, #16384 2107 002e 7848 ldr r0, .L171 2108 0030 FFF7FEFF bl HAL_GPIO_WritePin 2109 .LVL229: 2678:Src/main.c **** tmp32=0; 2110 .loc 1 2678 2 view .LVU641 2111 0034 0122 movs r2, #1 2112 0036 4FF40071 mov r1, #512 2113 003a 7648 ldr r0, .L171+4 2114 003c FFF7FEFF bl HAL_GPIO_WritePin 2115 .LVL230: 2679:Src/main.c **** while(tmp32<500){tmp32++;} 2116 .loc 1 2679 2 view .LVU642 2680:Src/main.c **** if (num==1)//MPD1 2117 .loc 1 2680 2 view .LVU643 2679:Src/main.c **** while(tmp32<500){tmp32++;} 2118 .loc 1 2679 7 is_stmt 0 view .LVU644 2119 0040 0023 movs r3, #0 2680:Src/main.c **** if (num==1)//MPD1 2120 .loc 1 2680 7 view .LVU645 2121 0042 00E0 b .L133 2122 .LVL231: 2123 .L134: 2680:Src/main.c **** if (num==1)//MPD1 2124 .loc 1 2680 19 is_stmt 1 discriminator 2 view .LVU646 2680:Src/main.c **** if (num==1)//MPD1 2125 .loc 1 2680 24 is_stmt 0 discriminator 2 view .LVU647 2126 0044 0133 adds r3, r3, #1 2127 .LVL232: 2128 .L133: 2680:Src/main.c **** if (num==1)//MPD1 2129 .loc 1 2680 13 is_stmt 1 discriminator 1 view .LVU648 2130 0046 B3F5FA7F cmp r3, #500 2131 004a FBD3 bcc .L134 ARM GAS /tmp/ccYgfTud.s page 162 2681:Src/main.c **** { 2132 .loc 1 2681 2 view .LVU649 2133 004c 631E subs r3, r4, #1 2134 .LVL233: 2681:Src/main.c **** { 2135 .loc 1 2681 2 is_stmt 0 view .LVU650 2136 004e 032B cmp r3, #3 2137 0050 39D8 bhi .L135 2138 0052 DFE803F0 tbb [pc, r3] 2139 .L137: 2140 0056 02 .byte (.L140-.L137)/2 2141 0057 3A .byte (.L139-.L137)/2 2142 0058 6F .byte (.L138-.L137)/2 2143 0059 A6 .byte (.L136-.L137)/2 2144 .p2align 1 2145 .L140: 2683:Src/main.c **** HAL_GPIO_WritePin(ADC_MPD1_CS_GPIO_Port, ADC_MPD1_CS_Pin, GPIO_PIN_RESET); 2146 .loc 1 2683 3 is_stmt 1 view .LVU651 2147 005a 6D4C ldr r4, .L171 2148 .LVL234: 2683:Src/main.c **** HAL_GPIO_WritePin(ADC_MPD1_CS_GPIO_Port, ADC_MPD1_CS_Pin, GPIO_PIN_RESET); 2149 .loc 1 2683 3 is_stmt 0 view .LVU652 2150 005c 0122 movs r2, #1 2151 005e 4FF40061 mov r1, #2048 2152 0062 2046 mov r0, r4 2153 0064 FFF7FEFF bl HAL_GPIO_WritePin 2154 .LVL235: 2684:Src/main.c **** tmp32=0; 2155 .loc 1 2684 3 is_stmt 1 view .LVU653 2156 0068 0022 movs r2, #0 2157 006a 4FF48061 mov r1, #1024 2158 006e 2046 mov r0, r4 2159 0070 FFF7FEFF bl HAL_GPIO_WritePin 2160 .LVL236: 2685:Src/main.c **** while(tmp32<500){tmp32++;} 2161 .loc 1 2685 3 view .LVU654 2686:Src/main.c **** //LL_SPI_TransmitData16(SPI4, 0xFFFF);//We must to clock the CLK output for collect RX data. We c 2162 .loc 1 2686 3 view .LVU655 2685:Src/main.c **** while(tmp32<500){tmp32++;} 2163 .loc 1 2685 8 is_stmt 0 view .LVU656 2164 0074 0023 movs r3, #0 2686:Src/main.c **** //LL_SPI_TransmitData16(SPI4, 0xFFFF);//We must to clock the CLK output for collect RX data. We c 2165 .loc 1 2686 8 view .LVU657 2166 0076 00E0 b .L141 2167 .LVL237: 2168 .L142: 2686:Src/main.c **** //LL_SPI_TransmitData16(SPI4, 0xFFFF);//We must to clock the CLK output for collect RX data. We c 2169 .loc 1 2686 20 is_stmt 1 discriminator 2 view .LVU658 2686:Src/main.c **** //LL_SPI_TransmitData16(SPI4, 0xFFFF);//We must to clock the CLK output for collect RX data. We c 2170 .loc 1 2686 25 is_stmt 0 discriminator 2 view .LVU659 2171 0078 0133 adds r3, r3, #1 2172 .LVL238: 2173 .L141: 2686:Src/main.c **** //LL_SPI_TransmitData16(SPI4, 0xFFFF);//We must to clock the CLK output for collect RX data. We c 2174 .loc 1 2686 14 is_stmt 1 discriminator 1 view .LVU660 2175 007a B3F5FA7F cmp r3, #500 2176 007e FBD3 bcc .L142 ARM GAS /tmp/ccYgfTud.s page 163 2688:Src/main.c **** tmp32 = 0; 2177 .loc 1 2688 3 view .LVU661 2178 .LVL239: 2179 .LBB375: 2180 .LBI375: 358:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 2181 .loc 4 358 22 view .LVU662 2182 .LBB376: 360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 2183 .loc 4 360 3 view .LVU663 2184 0080 654A ldr r2, .L171+8 2185 0082 1368 ldr r3, [r2] 2186 .LVL240: 360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 2187 .loc 4 360 3 is_stmt 0 view .LVU664 2188 0084 43F04003 orr r3, r3, #64 2189 0088 1360 str r3, [r2] 2190 .LVL241: 360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 2191 .loc 4 360 3 view .LVU665 2192 .LBE376: 2193 .LBE375: 2689:Src/main.c **** while(((!LL_SPI_IsActiveFlag_RXNE(SPI4))&&(tmp32<=1000))) {tmp32++;}//When rec. last data cycle w 2194 .loc 1 2689 3 is_stmt 1 view .LVU666 2690:Src/main.c **** LL_SPI_Disable(SPI4);//Enable SPI for MPhD1 ADC 2195 .loc 1 2690 3 view .LVU667 2689:Src/main.c **** while(((!LL_SPI_IsActiveFlag_RXNE(SPI4))&&(tmp32<=1000))) {tmp32++;}//When rec. last data cycle w 2196 .loc 1 2689 9 is_stmt 0 view .LVU668 2197 008a 0023 movs r3, #0 2198 .LVL242: 2199 .L143: 2690:Src/main.c **** LL_SPI_Disable(SPI4);//Enable SPI for MPhD1 ADC 2200 .loc 1 2690 43 is_stmt 1 discriminator 1 view .LVU669 2201 .LBB377: 2202 .LBI377: 905:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 2203 .loc 4 905 26 view .LVU670 2204 .LBB378: 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 2205 .loc 4 907 3 view .LVU671 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 2206 .loc 4 907 12 is_stmt 0 view .LVU672 2207 008c 624A ldr r2, .L171+8 2208 008e 9268 ldr r2, [r2, #8] 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 2209 .loc 4 907 68 view .LVU673 2210 0090 12F0010F tst r2, #1 2211 0094 04D1 bne .L144 2212 .LVL243: 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 2213 .loc 4 907 68 view .LVU674 2214 .LBE378: 2215 .LBE377: 2690:Src/main.c **** LL_SPI_Disable(SPI4);//Enable SPI for MPhD1 ADC 2216 .loc 1 2690 43 discriminator 2 view .LVU675 2217 0096 B3F57A7F cmp r3, #1000 2218 009a 01D8 bhi .L144 ARM GAS /tmp/ccYgfTud.s page 164 2690:Src/main.c **** LL_SPI_Disable(SPI4);//Enable SPI for MPhD1 ADC 2219 .loc 1 2690 62 is_stmt 1 discriminator 3 view .LVU676 2690:Src/main.c **** LL_SPI_Disable(SPI4);//Enable SPI for MPhD1 ADC 2220 .loc 1 2690 67 is_stmt 0 discriminator 3 view .LVU677 2221 009c 0133 adds r3, r3, #1 2222 .LVL244: 2690:Src/main.c **** LL_SPI_Disable(SPI4);//Enable SPI for MPhD1 ADC 2223 .loc 1 2690 67 discriminator 3 view .LVU678 2224 009e F5E7 b .L143 2225 .L144: 2691:Src/main.c **** while(tmp32<500){tmp32++;} 2226 .loc 1 2691 3 is_stmt 1 view .LVU679 2227 .LVL245: 2228 .LBB379: 2229 .LBI379: 370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 2230 .loc 4 370 22 view .LVU680 2231 .LBB380: 372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 2232 .loc 4 372 3 view .LVU681 2233 00a0 5D49 ldr r1, .L171+8 2234 00a2 0A68 ldr r2, [r1] 2235 00a4 22F04002 bic r2, r2, #64 2236 00a8 0A60 str r2, [r1] 2237 .LVL246: 372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 2238 .loc 4 372 3 is_stmt 0 view .LVU682 2239 .LBE380: 2240 .LBE379: 2692:Src/main.c **** //HAL_SPI_Receive(&hspi4, &P[0], 1, 100); 2241 .loc 1 2692 3 is_stmt 1 view .LVU683 2242 .LBB382: 2243 .LBB381: 373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 2244 .loc 4 373 1 is_stmt 0 view .LVU684 2245 00aa 00E0 b .L146 2246 .L147: 373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 2247 .loc 4 373 1 view .LVU685 2248 .LBE381: 2249 .LBE382: 2692:Src/main.c **** //HAL_SPI_Receive(&hspi4, &P[0], 1, 100); 2250 .loc 1 2692 20 is_stmt 1 discriminator 2 view .LVU686 2692:Src/main.c **** //HAL_SPI_Receive(&hspi4, &P[0], 1, 100); 2251 .loc 1 2692 25 is_stmt 0 discriminator 2 view .LVU687 2252 00ac 0133 adds r3, r3, #1 2253 .LVL247: 2254 .L146: 2692:Src/main.c **** //HAL_SPI_Receive(&hspi4, &P[0], 1, 100); 2255 .loc 1 2692 14 is_stmt 1 discriminator 1 view .LVU688 2256 00ae B3F5FA7F cmp r3, #500 2257 00b2 FBD3 bcc .L147 2694:Src/main.c **** P = LL_SPI_ReceiveData16(SPI4); 2258 .loc 1 2694 3 view .LVU689 2259 00b4 0122 movs r2, #1 2260 00b6 4FF48061 mov r1, #1024 2261 00ba 5548 ldr r0, .L171 ARM GAS /tmp/ccYgfTud.s page 165 2262 00bc FFF7FEFF bl HAL_GPIO_WritePin 2263 .LVL248: 2695:Src/main.c **** } 2264 .loc 1 2695 3 view .LVU690 2265 .LBB383: 2266 .LBI383: 1344:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 2267 .loc 4 1344 26 view .LVU691 2268 .LBB384: 1346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 2269 .loc 4 1346 3 view .LVU692 1346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 2270 .loc 4 1346 21 is_stmt 0 view .LVU693 2271 00c0 554B ldr r3, .L171+8 2272 00c2 DD68 ldr r5, [r3, #12] 1346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 2273 .loc 4 1346 10 view .LVU694 2274 00c4 ADB2 uxth r5, r5 2275 .LVL249: 2276 .L135: 1346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 2277 .loc 4 1346 10 view .LVU695 2278 .LBE384: 2279 .LBE383: 2767:Src/main.c **** } 2280 .loc 1 2767 2 is_stmt 1 view .LVU696 2768:Src/main.c **** /*static uint16_t Temp_LD(uint16_t T_LD_before, uint16_t T_LD, uint32_t Timer_before, uint32_t Time 2281 .loc 1 2768 1 is_stmt 0 view .LVU697 2282 00c6 2846 mov r0, r5 2283 00c8 38BD pop {r3, r4, r5, pc} 2284 .LVL250: 2285 .L139: 2699:Src/main.c **** HAL_GPIO_WritePin(ADC_MPD2_CS_GPIO_Port, ADC_MPD2_CS_Pin, GPIO_PIN_RESET); 2286 .loc 1 2699 3 is_stmt 1 view .LVU698 2287 00ca 524C ldr r4, .L171+4 2288 00cc 0122 movs r2, #1 2289 00ce 4FF48061 mov r1, #1024 2290 00d2 2046 mov r0, r4 2291 00d4 FFF7FEFF bl HAL_GPIO_WritePin 2292 .LVL251: 2700:Src/main.c **** tmp32=0; 2293 .loc 1 2700 3 view .LVU699 2294 00d8 0022 movs r2, #0 2295 00da 4021 movs r1, #64 2296 00dc 2046 mov r0, r4 2297 00de FFF7FEFF bl HAL_GPIO_WritePin 2298 .LVL252: 2701:Src/main.c **** while(tmp32<500){tmp32++;} 2299 .loc 1 2701 3 view .LVU700 2702:Src/main.c **** //LL_SPI_TransmitData16(SPI5, 0xFFFF);//We must to clock the CLK output for collect RX data. We c 2300 .loc 1 2702 3 view .LVU701 2701:Src/main.c **** while(tmp32<500){tmp32++;} 2301 .loc 1 2701 8 is_stmt 0 view .LVU702 2302 00e2 0023 movs r3, #0 2702:Src/main.c **** //LL_SPI_TransmitData16(SPI5, 0xFFFF);//We must to clock the CLK output for collect RX data. We c 2303 .loc 1 2702 8 view .LVU703 2304 00e4 00E0 b .L148 ARM GAS /tmp/ccYgfTud.s page 166 2305 .LVL253: 2306 .L149: 2702:Src/main.c **** //LL_SPI_TransmitData16(SPI5, 0xFFFF);//We must to clock the CLK output for collect RX data. We c 2307 .loc 1 2702 20 is_stmt 1 discriminator 2 view .LVU704 2702:Src/main.c **** //LL_SPI_TransmitData16(SPI5, 0xFFFF);//We must to clock the CLK output for collect RX data. We c 2308 .loc 1 2702 25 is_stmt 0 discriminator 2 view .LVU705 2309 00e6 0133 adds r3, r3, #1 2310 .LVL254: 2311 .L148: 2702:Src/main.c **** //LL_SPI_TransmitData16(SPI5, 0xFFFF);//We must to clock the CLK output for collect RX data. We c 2312 .loc 1 2702 14 is_stmt 1 discriminator 1 view .LVU706 2313 00e8 B3F5FA7F cmp r3, #500 2314 00ec FBD3 bcc .L149 2704:Src/main.c **** tmp32 = 0; 2315 .loc 1 2704 3 view .LVU707 2316 .LVL255: 2317 .LBB385: 2318 .LBI385: 358:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 2319 .loc 4 358 22 view .LVU708 2320 .LBB386: 360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 2321 .loc 4 360 3 view .LVU709 2322 00ee 4B4A ldr r2, .L171+12 2323 00f0 1368 ldr r3, [r2] 2324 .LVL256: 360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 2325 .loc 4 360 3 is_stmt 0 view .LVU710 2326 00f2 43F04003 orr r3, r3, #64 2327 00f6 1360 str r3, [r2] 2328 .LVL257: 360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 2329 .loc 4 360 3 view .LVU711 2330 .LBE386: 2331 .LBE385: 2705:Src/main.c **** while(((!LL_SPI_IsActiveFlag_RXNE(SPI5))&&(tmp32<=1000))) {tmp32++;}//When rec. last data cycle w 2332 .loc 1 2705 3 is_stmt 1 view .LVU712 2706:Src/main.c **** LL_SPI_Disable(SPI5);//Enable SPI for MPhD2 ADC 2333 .loc 1 2706 3 view .LVU713 2705:Src/main.c **** while(((!LL_SPI_IsActiveFlag_RXNE(SPI5))&&(tmp32<=1000))) {tmp32++;}//When rec. last data cycle w 2334 .loc 1 2705 9 is_stmt 0 view .LVU714 2335 00f8 0023 movs r3, #0 2336 .LVL258: 2337 .L150: 2706:Src/main.c **** LL_SPI_Disable(SPI5);//Enable SPI for MPhD2 ADC 2338 .loc 1 2706 43 is_stmt 1 discriminator 1 view .LVU715 2339 .LBB387: 2340 .LBI387: 905:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 2341 .loc 4 905 26 view .LVU716 2342 .LBB388: 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 2343 .loc 4 907 3 view .LVU717 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 2344 .loc 4 907 12 is_stmt 0 view .LVU718 2345 00fa 484A ldr r2, .L171+12 2346 00fc 9268 ldr r2, [r2, #8] ARM GAS /tmp/ccYgfTud.s page 167 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 2347 .loc 4 907 68 view .LVU719 2348 00fe 12F0010F tst r2, #1 2349 0102 04D1 bne .L151 2350 .LVL259: 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 2351 .loc 4 907 68 view .LVU720 2352 .LBE388: 2353 .LBE387: 2706:Src/main.c **** LL_SPI_Disable(SPI5);//Enable SPI for MPhD2 ADC 2354 .loc 1 2706 43 discriminator 2 view .LVU721 2355 0104 B3F57A7F cmp r3, #1000 2356 0108 01D8 bhi .L151 2706:Src/main.c **** LL_SPI_Disable(SPI5);//Enable SPI for MPhD2 ADC 2357 .loc 1 2706 62 is_stmt 1 discriminator 3 view .LVU722 2706:Src/main.c **** LL_SPI_Disable(SPI5);//Enable SPI for MPhD2 ADC 2358 .loc 1 2706 67 is_stmt 0 discriminator 3 view .LVU723 2359 010a 0133 adds r3, r3, #1 2360 .LVL260: 2706:Src/main.c **** LL_SPI_Disable(SPI5);//Enable SPI for MPhD2 ADC 2361 .loc 1 2706 67 discriminator 3 view .LVU724 2362 010c F5E7 b .L150 2363 .L151: 2707:Src/main.c **** while(tmp32<500){tmp32++;} 2364 .loc 1 2707 3 is_stmt 1 view .LVU725 2365 .LVL261: 2366 .LBB389: 2367 .LBI389: 370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 2368 .loc 4 370 22 view .LVU726 2369 .LBB390: 372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 2370 .loc 4 372 3 view .LVU727 2371 010e 4349 ldr r1, .L171+12 2372 0110 0A68 ldr r2, [r1] 2373 0112 22F04002 bic r2, r2, #64 2374 0116 0A60 str r2, [r1] 2375 .LVL262: 372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 2376 .loc 4 372 3 is_stmt 0 view .LVU728 2377 .LBE390: 2378 .LBE389: 2708:Src/main.c **** //HAL_SPI_Receive(&hspi4, &P[0], 1, 100); 2379 .loc 1 2708 3 is_stmt 1 view .LVU729 2380 .LBB392: 2381 .LBB391: 373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 2382 .loc 4 373 1 is_stmt 0 view .LVU730 2383 0118 00E0 b .L153 2384 .L154: 373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 2385 .loc 4 373 1 view .LVU731 2386 .LBE391: 2387 .LBE392: 2708:Src/main.c **** //HAL_SPI_Receive(&hspi4, &P[0], 1, 100); 2388 .loc 1 2708 20 is_stmt 1 discriminator 2 view .LVU732 2708:Src/main.c **** //HAL_SPI_Receive(&hspi4, &P[0], 1, 100); ARM GAS /tmp/ccYgfTud.s page 168 2389 .loc 1 2708 25 is_stmt 0 discriminator 2 view .LVU733 2390 011a 0133 adds r3, r3, #1 2391 .LVL263: 2392 .L153: 2708:Src/main.c **** //HAL_SPI_Receive(&hspi4, &P[0], 1, 100); 2393 .loc 1 2708 14 is_stmt 1 discriminator 1 view .LVU734 2394 011c B3F5FA7F cmp r3, #500 2395 0120 FBD3 bcc .L154 2710:Src/main.c **** P = LL_SPI_ReceiveData16(SPI5); 2396 .loc 1 2710 3 view .LVU735 2397 0122 0122 movs r2, #1 2398 0124 4021 movs r1, #64 2399 0126 3B48 ldr r0, .L171+4 2400 0128 FFF7FEFF bl HAL_GPIO_WritePin 2401 .LVL264: 2711:Src/main.c **** } 2402 .loc 1 2711 3 view .LVU736 2403 .LBB393: 2404 .LBI393: 1344:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 2405 .loc 4 1344 26 view .LVU737 2406 .LBB394: 1346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 2407 .loc 4 1346 3 view .LVU738 1346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 2408 .loc 4 1346 21 is_stmt 0 view .LVU739 2409 012c 3B4B ldr r3, .L171+12 2410 012e DD68 ldr r5, [r3, #12] 1346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 2411 .loc 4 1346 10 view .LVU740 2412 0130 ADB2 uxth r5, r5 2413 .LVL265: 1346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 2414 .loc 4 1346 10 view .LVU741 2415 .LBE394: 2416 .LBE393: 2417 0132 C8E7 b .L135 2418 .LVL266: 2419 .L138: 2715:Src/main.c **** HAL_GPIO_WritePin(ADC_ThrLD1_CS_GPIO_Port, ADC_ThrLD1_CS_Pin, GPIO_PIN_RESET); 2420 .loc 1 2715 3 is_stmt 1 view .LVU742 2421 0134 364C ldr r4, .L171 2422 0136 0122 movs r2, #1 2423 0138 4FF48061 mov r1, #1024 2424 013c 2046 mov r0, r4 2425 013e FFF7FEFF bl HAL_GPIO_WritePin 2426 .LVL267: 2716:Src/main.c **** tmp32=0; 2427 .loc 1 2716 3 view .LVU743 2428 0142 0022 movs r2, #0 2429 0144 4FF40061 mov r1, #2048 2430 0148 2046 mov r0, r4 2431 014a FFF7FEFF bl HAL_GPIO_WritePin 2432 .LVL268: 2717:Src/main.c **** while(tmp32<500){tmp32++;} 2433 .loc 1 2717 3 view .LVU744 2718:Src/main.c **** //LL_SPI_TransmitData16(SPI4, 0xFFFF);//We must to clock the CLK output for collect RX data. We c ARM GAS /tmp/ccYgfTud.s page 169 2434 .loc 1 2718 3 view .LVU745 2717:Src/main.c **** while(tmp32<500){tmp32++;} 2435 .loc 1 2717 8 is_stmt 0 view .LVU746 2436 014e 0023 movs r3, #0 2718:Src/main.c **** //LL_SPI_TransmitData16(SPI4, 0xFFFF);//We must to clock the CLK output for collect RX data. We c 2437 .loc 1 2718 8 view .LVU747 2438 0150 00E0 b .L155 2439 .LVL269: 2440 .L156: 2718:Src/main.c **** //LL_SPI_TransmitData16(SPI4, 0xFFFF);//We must to clock the CLK output for collect RX data. We c 2441 .loc 1 2718 20 is_stmt 1 discriminator 2 view .LVU748 2718:Src/main.c **** //LL_SPI_TransmitData16(SPI4, 0xFFFF);//We must to clock the CLK output for collect RX data. We c 2442 .loc 1 2718 25 is_stmt 0 discriminator 2 view .LVU749 2443 0152 0133 adds r3, r3, #1 2444 .LVL270: 2445 .L155: 2718:Src/main.c **** //LL_SPI_TransmitData16(SPI4, 0xFFFF);//We must to clock the CLK output for collect RX data. We c 2446 .loc 1 2718 14 is_stmt 1 discriminator 1 view .LVU750 2447 0154 B3F5FA7F cmp r3, #500 2448 0158 FBD3 bcc .L156 2720:Src/main.c **** tmp32 = 0; 2449 .loc 1 2720 3 view .LVU751 2450 .LVL271: 2451 .LBB395: 2452 .LBI395: 358:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 2453 .loc 4 358 22 view .LVU752 2454 .LBB396: 360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 2455 .loc 4 360 3 view .LVU753 2456 015a 2F4A ldr r2, .L171+8 2457 015c 1368 ldr r3, [r2] 2458 .LVL272: 360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 2459 .loc 4 360 3 is_stmt 0 view .LVU754 2460 015e 43F04003 orr r3, r3, #64 2461 0162 1360 str r3, [r2] 2462 .LVL273: 360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 2463 .loc 4 360 3 view .LVU755 2464 .LBE396: 2465 .LBE395: 2721:Src/main.c **** while(((!LL_SPI_IsActiveFlag_RXNE(SPI4))&&(tmp32<=1000))) {tmp32++;}//When rec. last data cycle w 2466 .loc 1 2721 3 is_stmt 1 view .LVU756 2722:Src/main.c **** LL_SPI_Disable(SPI4);//Enable SPI for ThrLD1 ADC 2467 .loc 1 2722 3 view .LVU757 2721:Src/main.c **** while(((!LL_SPI_IsActiveFlag_RXNE(SPI4))&&(tmp32<=1000))) {tmp32++;}//When rec. last data cycle w 2468 .loc 1 2721 9 is_stmt 0 view .LVU758 2469 0164 0023 movs r3, #0 2470 .LVL274: 2471 .L157: 2722:Src/main.c **** LL_SPI_Disable(SPI4);//Enable SPI for ThrLD1 ADC 2472 .loc 1 2722 43 is_stmt 1 discriminator 1 view .LVU759 2473 .LBB397: 2474 .LBI397: 905:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 2475 .loc 4 905 26 view .LVU760 ARM GAS /tmp/ccYgfTud.s page 170 2476 .LBB398: 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 2477 .loc 4 907 3 view .LVU761 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 2478 .loc 4 907 12 is_stmt 0 view .LVU762 2479 0166 2C4A ldr r2, .L171+8 2480 0168 9268 ldr r2, [r2, #8] 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 2481 .loc 4 907 68 view .LVU763 2482 016a 12F0010F tst r2, #1 2483 016e 04D1 bne .L158 2484 .LVL275: 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 2485 .loc 4 907 68 view .LVU764 2486 .LBE398: 2487 .LBE397: 2722:Src/main.c **** LL_SPI_Disable(SPI4);//Enable SPI for ThrLD1 ADC 2488 .loc 1 2722 43 discriminator 2 view .LVU765 2489 0170 B3F57A7F cmp r3, #1000 2490 0174 01D8 bhi .L158 2722:Src/main.c **** LL_SPI_Disable(SPI4);//Enable SPI for ThrLD1 ADC 2491 .loc 1 2722 62 is_stmt 1 discriminator 3 view .LVU766 2722:Src/main.c **** LL_SPI_Disable(SPI4);//Enable SPI for ThrLD1 ADC 2492 .loc 1 2722 67 is_stmt 0 discriminator 3 view .LVU767 2493 0176 0133 adds r3, r3, #1 2494 .LVL276: 2722:Src/main.c **** LL_SPI_Disable(SPI4);//Enable SPI for ThrLD1 ADC 2495 .loc 1 2722 67 discriminator 3 view .LVU768 2496 0178 F5E7 b .L157 2497 .L158: 2723:Src/main.c **** while(tmp32<500){tmp32++;} 2498 .loc 1 2723 3 is_stmt 1 view .LVU769 2499 .LVL277: 2500 .LBB399: 2501 .LBI399: 370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 2502 .loc 4 370 22 view .LVU770 2503 .LBB400: 372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 2504 .loc 4 372 3 view .LVU771 2505 017a 2749 ldr r1, .L171+8 2506 017c 0A68 ldr r2, [r1] 2507 017e 22F04002 bic r2, r2, #64 2508 0182 0A60 str r2, [r1] 2509 .LVL278: 372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 2510 .loc 4 372 3 is_stmt 0 view .LVU772 2511 .LBE400: 2512 .LBE399: 2724:Src/main.c **** //HAL_SPI_Receive(&hspi4, &P[0], 1, 100); 2513 .loc 1 2724 3 is_stmt 1 view .LVU773 2514 .LBB402: 2515 .LBB401: 373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 2516 .loc 4 373 1 is_stmt 0 view .LVU774 2517 0184 00E0 b .L160 2518 .L161: ARM GAS /tmp/ccYgfTud.s page 171 373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 2519 .loc 4 373 1 view .LVU775 2520 .LBE401: 2521 .LBE402: 2724:Src/main.c **** //HAL_SPI_Receive(&hspi4, &P[0], 1, 100); 2522 .loc 1 2724 20 is_stmt 1 discriminator 2 view .LVU776 2724:Src/main.c **** //HAL_SPI_Receive(&hspi4, &P[0], 1, 100); 2523 .loc 1 2724 25 is_stmt 0 discriminator 2 view .LVU777 2524 0186 0133 adds r3, r3, #1 2525 .LVL279: 2526 .L160: 2724:Src/main.c **** //HAL_SPI_Receive(&hspi4, &P[0], 1, 100); 2527 .loc 1 2724 14 is_stmt 1 discriminator 1 view .LVU778 2528 0188 B3F5FA7F cmp r3, #500 2529 018c FBD3 bcc .L161 2726:Src/main.c **** P = LL_SPI_ReceiveData16(SPI4); 2530 .loc 1 2726 3 view .LVU779 2531 018e 0122 movs r2, #1 2532 0190 4FF40061 mov r1, #2048 2533 0194 1E48 ldr r0, .L171 2534 0196 FFF7FEFF bl HAL_GPIO_WritePin 2535 .LVL280: 2727:Src/main.c **** } 2536 .loc 1 2727 3 view .LVU780 2537 .LBB403: 2538 .LBI403: 1344:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 2539 .loc 4 1344 26 view .LVU781 2540 .LBB404: 1346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 2541 .loc 4 1346 3 view .LVU782 1346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 2542 .loc 4 1346 21 is_stmt 0 view .LVU783 2543 019a 1F4B ldr r3, .L171+8 2544 019c DD68 ldr r5, [r3, #12] 1346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 2545 .loc 4 1346 10 view .LVU784 2546 019e ADB2 uxth r5, r5 2547 .LVL281: 1346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 2548 .loc 4 1346 10 view .LVU785 2549 .LBE404: 2550 .LBE403: 2551 01a0 91E7 b .L135 2552 .LVL282: 2553 .L136: 2731:Src/main.c **** HAL_GPIO_WritePin(ADC_ThrLD2_CS_GPIO_Port, ADC_ThrLD2_CS_Pin, GPIO_PIN_RESET); 2554 .loc 1 2731 3 is_stmt 1 view .LVU786 2555 01a2 1C4C ldr r4, .L171+4 2556 01a4 0122 movs r2, #1 2557 01a6 4021 movs r1, #64 2558 01a8 2046 mov r0, r4 2559 01aa FFF7FEFF bl HAL_GPIO_WritePin 2560 .LVL283: 2732:Src/main.c **** tmp32=0; 2561 .loc 1 2732 3 view .LVU787 2562 01ae 0022 movs r2, #0 ARM GAS /tmp/ccYgfTud.s page 172 2563 01b0 4FF48061 mov r1, #1024 2564 01b4 2046 mov r0, r4 2565 01b6 FFF7FEFF bl HAL_GPIO_WritePin 2566 .LVL284: 2733:Src/main.c **** while(tmp32<500){tmp32++;} 2567 .loc 1 2733 3 view .LVU788 2734:Src/main.c **** //LL_SPI_TransmitData16(SPI5, 0xFFFF);//We must to clock the CLK output for collect RX data. We c 2568 .loc 1 2734 3 view .LVU789 2733:Src/main.c **** while(tmp32<500){tmp32++;} 2569 .loc 1 2733 8 is_stmt 0 view .LVU790 2570 01ba 0023 movs r3, #0 2734:Src/main.c **** //LL_SPI_TransmitData16(SPI5, 0xFFFF);//We must to clock the CLK output for collect RX data. We c 2571 .loc 1 2734 8 view .LVU791 2572 01bc 00E0 b .L162 2573 .LVL285: 2574 .L163: 2734:Src/main.c **** //LL_SPI_TransmitData16(SPI5, 0xFFFF);//We must to clock the CLK output for collect RX data. We c 2575 .loc 1 2734 20 is_stmt 1 discriminator 2 view .LVU792 2734:Src/main.c **** //LL_SPI_TransmitData16(SPI5, 0xFFFF);//We must to clock the CLK output for collect RX data. We c 2576 .loc 1 2734 25 is_stmt 0 discriminator 2 view .LVU793 2577 01be 0133 adds r3, r3, #1 2578 .LVL286: 2579 .L162: 2734:Src/main.c **** //LL_SPI_TransmitData16(SPI5, 0xFFFF);//We must to clock the CLK output for collect RX data. We c 2580 .loc 1 2734 14 is_stmt 1 discriminator 1 view .LVU794 2581 01c0 B3F5FA7F cmp r3, #500 2582 01c4 FBD3 bcc .L163 2736:Src/main.c **** tmp32 = 0; 2583 .loc 1 2736 3 view .LVU795 2584 .LVL287: 2585 .LBB405: 2586 .LBI405: 358:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 2587 .loc 4 358 22 view .LVU796 2588 .LBB406: 360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 2589 .loc 4 360 3 view .LVU797 2590 01c6 154A ldr r2, .L171+12 2591 01c8 1368 ldr r3, [r2] 2592 .LVL288: 360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 2593 .loc 4 360 3 is_stmt 0 view .LVU798 2594 01ca 43F04003 orr r3, r3, #64 2595 01ce 1360 str r3, [r2] 2596 .LVL289: 360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 2597 .loc 4 360 3 view .LVU799 2598 .LBE406: 2599 .LBE405: 2737:Src/main.c **** while(((!LL_SPI_IsActiveFlag_RXNE(SPI5))&&(tmp32<=1000))) {tmp32++;}//When rec. last data cycle w 2600 .loc 1 2737 3 is_stmt 1 view .LVU800 2738:Src/main.c **** LL_SPI_Disable(SPI5);//Enable SPI for ThrLD2 ADC 2601 .loc 1 2738 3 view .LVU801 2737:Src/main.c **** while(((!LL_SPI_IsActiveFlag_RXNE(SPI5))&&(tmp32<=1000))) {tmp32++;}//When rec. last data cycle w 2602 .loc 1 2737 9 is_stmt 0 view .LVU802 2603 01d0 0023 movs r3, #0 2604 .LVL290: ARM GAS /tmp/ccYgfTud.s page 173 2605 .L164: 2738:Src/main.c **** LL_SPI_Disable(SPI5);//Enable SPI for ThrLD2 ADC 2606 .loc 1 2738 43 is_stmt 1 discriminator 1 view .LVU803 2607 .LBB407: 2608 .LBI407: 905:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 2609 .loc 4 905 26 view .LVU804 2610 .LBB408: 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 2611 .loc 4 907 3 view .LVU805 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 2612 .loc 4 907 12 is_stmt 0 view .LVU806 2613 01d2 124A ldr r2, .L171+12 2614 01d4 9268 ldr r2, [r2, #8] 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 2615 .loc 4 907 68 view .LVU807 2616 01d6 12F0010F tst r2, #1 2617 01da 04D1 bne .L165 2618 .LVL291: 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 2619 .loc 4 907 68 view .LVU808 2620 .LBE408: 2621 .LBE407: 2738:Src/main.c **** LL_SPI_Disable(SPI5);//Enable SPI for ThrLD2 ADC 2622 .loc 1 2738 43 discriminator 2 view .LVU809 2623 01dc B3F57A7F cmp r3, #1000 2624 01e0 01D8 bhi .L165 2738:Src/main.c **** LL_SPI_Disable(SPI5);//Enable SPI for ThrLD2 ADC 2625 .loc 1 2738 62 is_stmt 1 discriminator 3 view .LVU810 2738:Src/main.c **** LL_SPI_Disable(SPI5);//Enable SPI for ThrLD2 ADC 2626 .loc 1 2738 67 is_stmt 0 discriminator 3 view .LVU811 2627 01e2 0133 adds r3, r3, #1 2628 .LVL292: 2738:Src/main.c **** LL_SPI_Disable(SPI5);//Enable SPI for ThrLD2 ADC 2629 .loc 1 2738 67 discriminator 3 view .LVU812 2630 01e4 F5E7 b .L164 2631 .L165: 2739:Src/main.c **** while(tmp32<500){tmp32++;} 2632 .loc 1 2739 3 is_stmt 1 view .LVU813 2633 .LVL293: 2634 .LBB409: 2635 .LBI409: 370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 2636 .loc 4 370 22 view .LVU814 2637 .LBB410: 372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 2638 .loc 4 372 3 view .LVU815 2639 01e6 0D49 ldr r1, .L171+12 2640 01e8 0A68 ldr r2, [r1] 2641 01ea 22F04002 bic r2, r2, #64 2642 01ee 0A60 str r2, [r1] 2643 .LVL294: 372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 2644 .loc 4 372 3 is_stmt 0 view .LVU816 2645 .LBE410: 2646 .LBE409: 2740:Src/main.c **** //HAL_SPI_Receive(&hspi4, &P[0], 1, 100); ARM GAS /tmp/ccYgfTud.s page 174 2647 .loc 1 2740 3 is_stmt 1 view .LVU817 2648 .LBB412: 2649 .LBB411: 373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 2650 .loc 4 373 1 is_stmt 0 view .LVU818 2651 01f0 00E0 b .L167 2652 .L168: 373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 2653 .loc 4 373 1 view .LVU819 2654 .LBE411: 2655 .LBE412: 2740:Src/main.c **** //HAL_SPI_Receive(&hspi4, &P[0], 1, 100); 2656 .loc 1 2740 20 is_stmt 1 discriminator 2 view .LVU820 2740:Src/main.c **** //HAL_SPI_Receive(&hspi4, &P[0], 1, 100); 2657 .loc 1 2740 25 is_stmt 0 discriminator 2 view .LVU821 2658 01f2 0133 adds r3, r3, #1 2659 .LVL295: 2660 .L167: 2740:Src/main.c **** //HAL_SPI_Receive(&hspi4, &P[0], 1, 100); 2661 .loc 1 2740 14 is_stmt 1 discriminator 1 view .LVU822 2662 01f4 B3F5FA7F cmp r3, #500 2663 01f8 FBD3 bcc .L168 2742:Src/main.c **** P = LL_SPI_ReceiveData16(SPI5); 2664 .loc 1 2742 3 view .LVU823 2665 01fa 0122 movs r2, #1 2666 01fc 4FF48061 mov r1, #1024 2667 0200 0448 ldr r0, .L171+4 2668 0202 FFF7FEFF bl HAL_GPIO_WritePin 2669 .LVL296: 2743:Src/main.c **** } 2670 .loc 1 2743 3 view .LVU824 2671 .LBB413: 2672 .LBI413: 1344:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 2673 .loc 4 1344 26 view .LVU825 2674 .LBB414: 1346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 2675 .loc 4 1346 3 view .LVU826 1346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 2676 .loc 4 1346 21 is_stmt 0 view .LVU827 2677 0206 054B ldr r3, .L171+12 2678 0208 DD68 ldr r5, [r3, #12] 1346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 2679 .loc 4 1346 10 view .LVU828 2680 020a ADB2 uxth r5, r5 2681 .LVL297: 1346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 2682 .loc 4 1346 10 view .LVU829 2683 020c 5BE7 b .L135 2684 .L172: 2685 020e 00BF .align 2 2686 .L171: 2687 0210 00100240 .word 1073876992 2688 0214 00140240 .word 1073878016 2689 0218 00340140 .word 1073820672 2690 021c 00500140 .word 1073827840 2691 .LBE414: ARM GAS /tmp/ccYgfTud.s page 175 2692 .LBE413: 2693 .cfi_endproc 2694 .LFE1218: 2696 .section .text.Stop_TIM10,"ax",%progbits 2697 .align 1 2698 .syntax unified 2699 .thumb 2700 .thumb_func 2702 Stop_TIM10: 2703 .LFB1229: 2908:Src/main.c **** uint8_t CheckChecksum(uint16_t *pbuff) 2909:Src/main.c **** { 2910:Src/main.c **** uint16_t cl_ind; 2911:Src/main.c **** 2912:Src/main.c **** switch (UART_header) 2913:Src/main.c **** { 2914:Src/main.c **** case 0x7777: 2915:Src/main.c **** cl_ind = TSK_16 - 2; 2916:Src/main.c **** break; 2917:Src/main.c **** case 0x1111: 2918:Src/main.c **** cl_ind = CL_16 - 2; 2919:Src/main.c **** break; 2920:Src/main.c **** default: 2921:Src/main.c **** return 0; 2922:Src/main.c **** break; 2923:Src/main.c **** } 2924:Src/main.c **** 2925:Src/main.c **** CS_result = CalculateChecksum(pbuff, cl_ind); 2926:Src/main.c **** 2927:Src/main.c **** return ((CS_result == COMMAND[cl_ind]) ? 1 : 0); 2928:Src/main.c **** } 2929:Src/main.c **** uint16_t CalculateChecksum(uint16_t *pbuff, uint16_t len) 2930:Src/main.c **** { 2931:Src/main.c **** short i; 2932:Src/main.c **** uint16_t cs = *pbuff; 2933:Src/main.c **** 2934:Src/main.c **** for(i = 1; i < len; i++) 2935:Src/main.c **** { 2936:Src/main.c **** cs ^= *(pbuff+i); 2937:Src/main.c **** } 2938:Src/main.c **** return cs; 2939:Src/main.c **** } 2940:Src/main.c **** 2941:Src/main.c **** /*int SD_Init(void) 2942:Src/main.c **** { 2943:Src/main.c **** int test=0; 2944:Src/main.c **** if (HAL_GPIO_ReadPin(SDMMC1_EN_GPIO_Port, SDMMC1_EN_Pin)==GPIO_PIN_RESET) 2945:Src/main.c **** { 2946:Src/main.c **** test = Mount_SD("/"); 2947:Src/main.c **** if (test == 0) //0 - suc 2948:Src/main.c **** { 2949:Src/main.c **** //Format_SD(); 2950:Src/main.c **** test = Create_File("FILE1.TXT"); // 0 -suc 2951:Src/main.c **** //Create_File("FILE2.TXT"); 2952:Src/main.c **** Write_File ("FILE1.TXT", "____OSGG main borad information. Program made by Kazakov Viktor. Part 2953:Src/main.c **** test = Unmount_SD("/"); // 0 - succ 2954:Src/main.c **** return test; ARM GAS /tmp/ccYgfTud.s page 176 2955:Src/main.c **** } 2956:Src/main.c **** else 2957:Src/main.c **** { 2958:Src/main.c **** return 1; 2959:Src/main.c **** } 2960:Src/main.c **** } 2961:Src/main.c **** else 2962:Src/main.c **** { 2963:Src/main.c **** return 1; 2964:Src/main.c **** } 2965:Src/main.c **** }*/ 2966:Src/main.c **** 2967:Src/main.c **** int SD_SAVE(uint16_t *pbuff) 2968:Src/main.c **** { 2969:Src/main.c **** int test=0; 2970:Src/main.c **** if (HAL_GPIO_ReadPin(SDMMC1_EN_GPIO_Port, SDMMC1_EN_Pin)==GPIO_PIN_RESET) 2971:Src/main.c **** { 2972:Src/main.c **** test = Mount_SD("/"); 2973:Src/main.c **** if (test == 0) //0 - suc 2974:Src/main.c **** { 2975:Src/main.c **** //Format_SD(); 2976:Src/main.c **** test = Update_File_byte("FILE1.TXT", (uint8_t *)pbuff, DL_8); 2977:Src/main.c **** test = Unmount_SD("/"); // 0 - succ 2978:Src/main.c **** return test; 2979:Src/main.c **** } 2980:Src/main.c **** else 2981:Src/main.c **** { 2982:Src/main.c **** return 1; 2983:Src/main.c **** } 2984:Src/main.c **** } 2985:Src/main.c **** else 2986:Src/main.c **** { 2987:Src/main.c **** return 1; 2988:Src/main.c **** } 2989:Src/main.c **** } 2990:Src/main.c **** 2991:Src/main.c **** 2992:Src/main.c **** 2993:Src/main.c **** //uint32_t Get_Length(void) 2994:Src/main.c **** //{ 2995:Src/main.c **** // return SD_matr[0][0] + ((uint32_t) (SD_matr[0][1])<<16); 2996:Src/main.c **** //} 2997:Src/main.c **** 2998:Src/main.c **** int SD_READ(uint16_t *pbuff) 2999:Src/main.c **** { 3000:Src/main.c **** int test=0; 3001:Src/main.c **** if (HAL_GPIO_ReadPin(SDMMC1_EN_GPIO_Port, SDMMC1_EN_Pin)==GPIO_PIN_RESET) 3002:Src/main.c **** { 3003:Src/main.c **** test = Mount_SD("/"); 3004:Src/main.c **** if (test == 0) //0 - suc 3005:Src/main.c **** { 3006:Src/main.c **** //Format_SD(); 3007:Src/main.c **** test = Seek_Read_File ("FILE1.TXT", (uint8_t *)pbuff, DL_8, fgoto);//Read next 246 bytes 3008:Src/main.c **** fgoto+=DL_8; 3009:Src/main.c **** test = Unmount_SD("/"); // 0 - succ 3010:Src/main.c **** return test; 3011:Src/main.c **** } ARM GAS /tmp/ccYgfTud.s page 177 3012:Src/main.c **** else 3013:Src/main.c **** { 3014:Src/main.c **** return 1; 3015:Src/main.c **** } 3016:Src/main.c **** } 3017:Src/main.c **** else 3018:Src/main.c **** { 3019:Src/main.c **** return 1; 3020:Src/main.c **** } 3021:Src/main.c **** 3022:Src/main.c **** /* for (uint16_t j = 0; j < DL_16; j++) 3023:Src/main.c **** { 3024:Src/main.c **** *(pbuff+j) = SD_matr[SD_SLIDE][j]; 3025:Src/main.c **** } 3026:Src/main.c **** if (SD_SLIDEAHB1ENR, Periphs) == Periphs); 374:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } 375:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 376:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** 377:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Disable AHB1 peripherals clock. 378:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll AHB1ENR GPIOAEN LL_AHB1_GRP1_DisableClock\n 379:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOBEN LL_AHB1_GRP1_DisableClock\n 380:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOCEN LL_AHB1_GRP1_DisableClock\n 381:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIODEN LL_AHB1_GRP1_DisableClock\n 382:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOEEN LL_AHB1_GRP1_DisableClock\n 383:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOFEN LL_AHB1_GRP1_DisableClock\n 384:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOGEN LL_AHB1_GRP1_DisableClock\n 385:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOHEN LL_AHB1_GRP1_DisableClock\n 386:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOIEN LL_AHB1_GRP1_DisableClock\n 387:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOJEN LL_AHB1_GRP1_DisableClock\n 388:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOKEN LL_AHB1_GRP1_DisableClock\n 389:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR CRCEN LL_AHB1_GRP1_DisableClock\n 390:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR BKPSRAMEN LL_AHB1_GRP1_DisableClock\n 391:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR DTCMRAMEN LL_AHB1_GRP1_DisableClock\n 392:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR DMA1EN LL_AHB1_GRP1_DisableClock\n 393:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR DMA2EN LL_AHB1_GRP1_DisableClock\n 394:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR DMA2DEN LL_AHB1_GRP1_DisableClock\n 395:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR ETHMACEN LL_AHB1_GRP1_DisableClock\n 396:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR ETHMACTXEN LL_AHB1_GRP1_DisableClock\n 397:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR ETHMACRXEN LL_AHB1_GRP1_DisableClock\n 398:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR ETHMACPTPEN LL_AHB1_GRP1_DisableClock\n 399:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR OTGHSEN LL_AHB1_GRP1_DisableClock\n 400:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR OTGHSULPIENDEN LL_AHB1_GRP1_DisableClock 401:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: 402:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA 403:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB 404:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC 405:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD 406:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE 407:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF 408:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG 409:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH 410:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI 411:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*) 412:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*) 413:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRC 414:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM 415:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DTCMRAM 416:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 417:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 418:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*) 419:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*) 420:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*) ARM GAS /tmp/ccYgfTud.s page 193 421:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*) 422:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACPTP (*) 423:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS 424:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHSULPI 425:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * 426:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. 427:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval None 428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ 429:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs) 430:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { 431:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** CLEAR_BIT(RCC->AHB1ENR, Periphs); 432:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } 433:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 434:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** 435:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Force AHB1 peripherals reset. 436:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll AHB1RSTR GPIOARST LL_AHB1_GRP1_ForceReset\n 437:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR GPIOBRST LL_AHB1_GRP1_ForceReset\n 438:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR GPIOCRST LL_AHB1_GRP1_ForceReset\n 439:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR GPIODRST LL_AHB1_GRP1_ForceReset\n 440:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR GPIOERST LL_AHB1_GRP1_ForceReset\n 441:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR GPIOFRST LL_AHB1_GRP1_ForceReset\n 442:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR GPIOGRST LL_AHB1_GRP1_ForceReset\n 443:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR GPIOHRST LL_AHB1_GRP1_ForceReset\n 444:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR GPIOIRST LL_AHB1_GRP1_ForceReset\n 445:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR GPIOJRST LL_AHB1_GRP1_ForceReset\n 446:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR GPIOKRST LL_AHB1_GRP1_ForceReset\n 447:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR CRCRST LL_AHB1_GRP1_ForceReset\n 448:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR DMA1RST LL_AHB1_GRP1_ForceReset\n 449:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR DMA2RST LL_AHB1_GRP1_ForceReset\n 450:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR DMA2DRST LL_AHB1_GRP1_ForceReset\n 451:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR ETHMACRST LL_AHB1_GRP1_ForceReset\n 452:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR OTGHSRST LL_AHB1_GRP1_ForceReset 453:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: 454:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ALL 455:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA 456:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB 457:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC 458:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD 459:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE 460:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF 461:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG 462:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH 463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI 464:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*) 465:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*) 466:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRC 467:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 468:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 469:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*) 470:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*) 471:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS 472:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * 473:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. 474:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval None 475:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ 476:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs) 477:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { ARM GAS /tmp/ccYgfTud.s page 194 478:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** SET_BIT(RCC->AHB1RSTR, Periphs); 479:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } 480:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 481:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** 482:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Release AHB1 peripherals reset. 483:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll AHB1RSTR GPIOARST LL_AHB1_GRP1_ReleaseReset\n 484:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR GPIOBRST LL_AHB1_GRP1_ReleaseReset\n 485:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR GPIOCRST LL_AHB1_GRP1_ReleaseReset\n 486:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR GPIODRST LL_AHB1_GRP1_ReleaseReset\n 487:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR GPIOERST LL_AHB1_GRP1_ReleaseReset\n 488:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR GPIOFRST LL_AHB1_GRP1_ReleaseReset\n 489:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR GPIOGRST LL_AHB1_GRP1_ReleaseReset\n 490:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR GPIOHRST LL_AHB1_GRP1_ReleaseReset\n 491:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR GPIOIRST LL_AHB1_GRP1_ReleaseReset\n 492:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR GPIOJRST LL_AHB1_GRP1_ReleaseReset\n 493:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR GPIOKRST LL_AHB1_GRP1_ReleaseReset\n 494:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR CRCRST LL_AHB1_GRP1_ReleaseReset\n 495:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR DMA1RST LL_AHB1_GRP1_ReleaseReset\n 496:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR DMA2RST LL_AHB1_GRP1_ReleaseReset\n 497:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR DMA2DRST LL_AHB1_GRP1_ReleaseReset\n 498:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR ETHMACRST LL_AHB1_GRP1_ReleaseReset\n 499:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR OTGHSRST LL_AHB1_GRP1_ReleaseReset 500:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: 501:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ALL 502:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA 503:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB 504:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC 505:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD 506:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE 507:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF 508:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG 509:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH 510:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI 511:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*) 512:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*) 513:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRC 514:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 515:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 516:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*) 517:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*) 518:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS 519:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * 520:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. 521:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval None 522:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ 523:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs) 524:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { 525:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** CLEAR_BIT(RCC->AHB1RSTR, Periphs); 526:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } 527:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 528:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** 529:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Enable AHB1 peripheral clocks in low-power mode 530:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll AHB1LPENR GPIOALPEN LL_AHB1_GRP1_EnableClockLowPower\n 531:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR GPIOBLPEN LL_AHB1_GRP1_EnableClockLowPower\n 532:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR GPIOCLPEN LL_AHB1_GRP1_EnableClockLowPower\n 533:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR GPIODLPEN LL_AHB1_GRP1_EnableClockLowPower\n 534:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR GPIOELPEN LL_AHB1_GRP1_EnableClockLowPower\n ARM GAS /tmp/ccYgfTud.s page 195 535:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR GPIOFLPEN LL_AHB1_GRP1_EnableClockLowPower\n 536:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR GPIOGLPEN LL_AHB1_GRP1_EnableClockLowPower\n 537:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR GPIOHLPEN LL_AHB1_GRP1_EnableClockLowPower\n 538:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR GPIOILPEN LL_AHB1_GRP1_EnableClockLowPower\n 539:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR GPIOJLPEN LL_AHB1_GRP1_EnableClockLowPower\n 540:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR GPIOKLPEN LL_AHB1_GRP1_EnableClockLowPower\n 541:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR CRCLPEN LL_AHB1_GRP1_EnableClockLowPower\n 542:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR AXILPEN LL_AHB1_GRP1_EnableClockLowPower\n 543:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR FLITFLPEN LL_AHB1_GRP1_EnableClockLowPower\n 544:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR SRAM1LPEN LL_AHB1_GRP1_EnableClockLowPower\n 545:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR SRAM2LPEN LL_AHB1_GRP1_EnableClockLowPower\n 546:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR BKPSRAMLPEN LL_AHB1_GRP1_EnableClockLowPower\n 547:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR DTCMRAMLPEN LL_AHB1_GRP1_EnableClockLowPower\n 548:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR DMA1LPEN LL_AHB1_GRP1_EnableClockLowPower\n 549:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR DMA2LPEN LL_AHB1_GRP1_EnableClockLowPower\n 550:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR DMA2DLPEN LL_AHB1_GRP1_EnableClockLowPower\n 551:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR ETHMACLPEN LL_AHB1_GRP1_EnableClockLowPower\n 552:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR ETHMACTXLPEN LL_AHB1_GRP1_EnableClockLowPower\n 553:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR ETHMACRXLPEN LL_AHB1_GRP1_EnableClockLowPower\n 554:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR ETHMACPTPLPEN LL_AHB1_GRP1_EnableClockLowPower\n 555:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR OTGHSLPEN LL_AHB1_GRP1_EnableClockLowPower\n 556:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR OTGHSULPILPEN LL_AHB1_GRP1_EnableClockLowPower 557:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: 558:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA 559:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB 560:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC 561:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD 562:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE 563:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF 564:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG 565:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH 566:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI 567:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*) 568:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*) 569:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRC 570:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_AXI 571:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_FLITF 572:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1 573:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM2 574:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM 575:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DTCMRAM 576:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 577:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 578:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*) 579:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*) 580:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*) 581:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*) 582:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACPTP (*) 583:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS 584:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHSULPI 585:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * 586:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. 587:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval None 588:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ 589:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB1_GRP1_EnableClockLowPower(uint32_t Periphs) 590:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { 591:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __IO uint32_t tmpreg; ARM GAS /tmp/ccYgfTud.s page 196 592:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** SET_BIT(RCC->AHB1LPENR, Periphs); 593:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Delay after an RCC peripheral clock enabling */ 594:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** tmpreg = READ_BIT(RCC->AHB1LPENR, Periphs); 595:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; 596:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } 597:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 598:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** 599:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Disable AHB1 peripheral clocks in low-power mode 600:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll AHB1LPENR GPIOALPEN LL_AHB1_GRP1_DisableClockLowPower\n 601:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR GPIOBLPEN LL_AHB1_GRP1_DisableClockLowPower\n 602:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR GPIOCLPEN LL_AHB1_GRP1_DisableClockLowPower\n 603:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR GPIODLPEN LL_AHB1_GRP1_DisableClockLowPower\n 604:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR GPIOELPEN LL_AHB1_GRP1_DisableClockLowPower\n 605:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR GPIOFLPEN LL_AHB1_GRP1_DisableClockLowPower\n 606:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR GPIOGLPEN LL_AHB1_GRP1_DisableClockLowPower\n 607:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR GPIOHLPEN LL_AHB1_GRP1_DisableClockLowPower\n 608:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR GPIOILPEN LL_AHB1_GRP1_DisableClockLowPower\n 609:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR GPIOJLPEN LL_AHB1_GRP1_DisableClockLowPower\n 610:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR GPIOKLPEN LL_AHB1_GRP1_DisableClockLowPower\n 611:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR CRCLPEN LL_AHB1_GRP1_DisableClockLowPower\n 612:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR AXILPEN LL_AHB1_GRP1_DisableClockLowPower\n 613:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR FLITFLPEN LL_AHB1_GRP1_DisableClockLowPower\n 614:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR SRAM1LPEN LL_AHB1_GRP1_DisableClockLowPower\n 615:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR SRAM2LPEN LL_AHB1_GRP1_DisableClockLowPower\n 616:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR BKPSRAMLPEN LL_AHB1_GRP1_DisableClockLowPower\n 617:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR DTCMRAMLPEN LL_AHB1_GRP1_DisableClockLowPower\n 618:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR DMA1LPEN LL_AHB1_GRP1_DisableClockLowPower\n 619:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR DMA2LPEN LL_AHB1_GRP1_DisableClockLowPower\n 620:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR DMA2DLPEN LL_AHB1_GRP1_DisableClockLowPower\n 621:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR ETHMACLPEN LL_AHB1_GRP1_DisableClockLowPower\n 622:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR ETHMACTXLPEN LL_AHB1_GRP1_DisableClockLowPower\n 623:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR ETHMACRXLPEN LL_AHB1_GRP1_DisableClockLowPower\n 624:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR ETHMACPTPLPEN LL_AHB1_GRP1_DisableClockLowPower\n 625:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR OTGHSLPEN LL_AHB1_GRP1_DisableClockLowPower\n 626:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR OTGHSULPILPEN LL_AHB1_GRP1_DisableClockLowPower 627:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: 628:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA 629:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB 630:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC 631:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD 632:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE 633:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF 634:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG 635:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH 636:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI 637:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*) 638:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*) 639:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRC 640:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_AXI 641:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_FLITF 642:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1 643:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM2 644:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM 645:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DTCMRAM 646:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 647:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 648:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*) ARM GAS /tmp/ccYgfTud.s page 197 649:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*) 650:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*) 651:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*) 652:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACPTP (*) 653:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS 654:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHSULPI 655:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * 656:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. 657:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval None 658:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ 659:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB1_GRP1_DisableClockLowPower(uint32_t Periphs) 660:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { 661:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** CLEAR_BIT(RCC->AHB1LPENR, Periphs); 662:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } 663:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 664:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** 665:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @} 666:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ 667:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 668:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** @defgroup BUS_LL_EF_AHB2 AHB2 669:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @{ 670:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ 671:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 672:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** 673:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Enable AHB2 peripherals clock. 674:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll AHB2ENR DCMIEN LL_AHB2_GRP1_EnableClock\n 675:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2ENR JPEGEN LL_AHB2_GRP1_EnableClock\n 676:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2ENR CRYPEN LL_AHB2_GRP1_EnableClock\n 677:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2ENR AESEN LL_AHB2_GRP1_EnableClock\n 678:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2ENR HASHEN LL_AHB2_GRP1_EnableClock\n 679:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2ENR RNGEN LL_AHB2_GRP1_EnableClock\n 680:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2ENR OTGFSEN LL_AHB2_GRP1_EnableClock 681:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: 682:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*) 683:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_JPEG (*) 684:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) 685:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*) 686:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) 687:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_RNG 688:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS 689:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * 690:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. 691:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval None 692:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ 693:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB2_GRP1_EnableClock(uint32_t Periphs) 694:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { 695:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __IO uint32_t tmpreg; 696:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** SET_BIT(RCC->AHB2ENR, Periphs); 697:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Delay after an RCC peripheral clock enabling */ 698:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** tmpreg = READ_BIT(RCC->AHB2ENR, Periphs); 699:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; 700:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } 701:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 702:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** 703:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Check if AHB2 peripheral clock is enabled or not 704:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll AHB2ENR DCMIEN LL_AHB2_GRP1_IsEnabledClock\n 705:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2ENR JPEGEN LL_AHB2_GRP1_IsEnabledClock\n ARM GAS /tmp/ccYgfTud.s page 198 706:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2ENR CRYPEN LL_AHB2_GRP1_IsEnabledClock\n 707:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2ENR AESEN LL_AHB2_GRP1_IsEnabledClock\n 708:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2ENR HASHEN LL_AHB2_GRP1_IsEnabledClock\n 709:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2ENR RNGEN LL_AHB2_GRP1_IsEnabledClock\n 710:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2ENR OTGFSEN LL_AHB2_GRP1_IsEnabledClock 711:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: 712:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*) 713:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_JPEG (*) 714:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) 715:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*) 716:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) 717:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_RNG 718:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS 719:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * 720:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. 721:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval State of Periphs (1 or 0). 722:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ 723:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE uint32_t LL_AHB2_GRP1_IsEnabledClock(uint32_t Periphs) 724:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { 725:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** return (READ_BIT(RCC->AHB2ENR, Periphs) == Periphs); 726:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } 727:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 728:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** 729:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Disable AHB2 peripherals clock. 730:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll AHB2ENR DCMIEN LL_AHB2_GRP1_DisableClock\n 731:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2ENR JPEGEN LL_AHB2_GRP1_DisableClock\n 732:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2ENR CRYPEN LL_AHB2_GRP1_DisableClock\n 733:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2ENR AESEN LL_AHB2_GRP1_DisableClock\n 734:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2ENR HASHEN LL_AHB2_GRP1_DisableClock\n 735:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2ENR RNGEN LL_AHB2_GRP1_DisableClock\n 736:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2ENR OTGFSEN LL_AHB2_GRP1_DisableClock 737:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: 738:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*) 739:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_JPEG (*) 740:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) 741:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*) 742:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) 743:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_RNG 744:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS 745:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * 746:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. 747:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval None 748:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ 749:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB2_GRP1_DisableClock(uint32_t Periphs) 750:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { 751:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** CLEAR_BIT(RCC->AHB2ENR, Periphs); 752:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } 753:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 754:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** 755:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Force AHB2 peripherals reset. 756:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll AHB2RSTR DCMIRST LL_AHB2_GRP1_ForceReset\n 757:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2RSTR JPEGRST LL_AHB2_GRP1_ForceReset\n 758:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2RSTR CRYPRST LL_AHB2_GRP1_ForceReset\n 759:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2RSTR AESRST LL_AHB2_GRP1_ForceReset\n 760:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2RSTR HASHRST LL_AHB2_GRP1_ForceReset\n 761:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2RSTR RNGRST LL_AHB2_GRP1_ForceReset\n 762:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2RSTR OTGFSRST LL_AHB2_GRP1_ForceReset ARM GAS /tmp/ccYgfTud.s page 199 763:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: 764:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_ALL 765:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*) 766:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_JPEG (*) 767:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) 768:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*) 769:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) 770:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_RNG 771:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS 772:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * 773:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. 774:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval None 775:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ 776:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB2_GRP1_ForceReset(uint32_t Periphs) 777:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { 778:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** SET_BIT(RCC->AHB2RSTR, Periphs); 779:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } 780:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 781:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** 782:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Release AHB2 peripherals reset. 783:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll AHB2RSTR DCMIRST LL_AHB2_GRP1_ReleaseReset\n 784:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2RSTR JPEGRST LL_AHB2_GRP1_ReleaseReset\n 785:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2RSTR CRYPRST LL_AHB2_GRP1_ReleaseReset\n 786:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2RSTR AESRST LL_AHB2_GRP1_ReleaseReset\n 787:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2RSTR HASHRST LL_AHB2_GRP1_ReleaseReset\n 788:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2RSTR RNGRST LL_AHB2_GRP1_ReleaseReset\n 789:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2RSTR OTGFSRST LL_AHB2_GRP1_ReleaseReset 790:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: 791:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_ALL 792:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*) 793:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_JPEG (*) 794:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) 795:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*) 796:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) 797:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_RNG 798:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS 799:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * 800:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. 801:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval None 802:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ 803:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB2_GRP1_ReleaseReset(uint32_t Periphs) 804:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { 805:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** CLEAR_BIT(RCC->AHB2RSTR, Periphs); 806:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } 807:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 808:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** 809:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Enable AHB2 peripheral clocks in low-power mode 810:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll AHB2LPENR DCMILPEN LL_AHB2_GRP1_EnableClockLowPower\n 811:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2LPENR JPEGLPEN LL_AHB2_GRP1_EnableClockLowPower\n 812:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2LPENR CRYPLPEN LL_AHB2_GRP1_EnableClockLowPower\n 813:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2LPENR AESLPEN LL_AHB2_GRP1_EnableClockLowPower\n 814:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2LPENR HASHLPEN LL_AHB2_GRP1_EnableClockLowPower\n 815:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2LPENR RNGLPEN LL_AHB2_GRP1_EnableClockLowPower\n 816:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2LPENR OTGFSLPEN LL_AHB2_GRP1_EnableClockLowPower 817:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: 818:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*) 819:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_JPEG (*) ARM GAS /tmp/ccYgfTud.s page 200 820:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) 821:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*) 822:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) 823:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_RNG 824:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS 825:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * 826:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. 827:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval None 828:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ 829:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB2_GRP1_EnableClockLowPower(uint32_t Periphs) 830:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { 831:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __IO uint32_t tmpreg; 832:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** SET_BIT(RCC->AHB2LPENR, Periphs); 833:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Delay after an RCC peripheral clock enabling */ 834:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** tmpreg = READ_BIT(RCC->AHB2LPENR, Periphs); 835:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; 836:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } 837:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 838:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** 839:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Disable AHB2 peripheral clocks in low-power mode 840:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll AHB2LPENR DCMILPEN LL_AHB2_GRP1_DisableClockLowPower\n 841:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2LPENR JPEGLPEN LL_AHB2_GRP1_DisableClockLowPower\n 842:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2LPENR CRYPLPEN LL_AHB2_GRP1_DisableClockLowPower\n 843:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2LPENR AESLPEN LL_AHB2_GRP1_DisableClockLowPower\n 844:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2LPENR HASHLPEN LL_AHB2_GRP1_DisableClockLowPower\n 845:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2LPENR RNGLPEN LL_AHB2_GRP1_DisableClockLowPower\n 846:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2LPENR OTGFSLPEN LL_AHB2_GRP1_DisableClockLowPower 847:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: 848:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*) 849:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_JPEG (*) 850:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) 851:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*) 852:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) 853:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_RNG 854:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS 855:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * 856:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. 857:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval None 858:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ 859:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB2_GRP1_DisableClockLowPower(uint32_t Periphs) 860:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { 861:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** CLEAR_BIT(RCC->AHB2LPENR, Periphs); 862:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } 863:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 864:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** 865:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @} 866:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ 867:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 868:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** @defgroup BUS_LL_EF_AHB3 AHB3 869:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @{ 870:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ 871:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 872:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** 873:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Enable AHB3 peripherals clock. 874:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll AHB3ENR FMCEN LL_AHB3_GRP1_EnableClock\n 875:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB3ENR QSPIEN LL_AHB3_GRP1_EnableClock 876:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: ARM GAS /tmp/ccYgfTud.s page 201 877:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*) 878:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI 879:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * 880:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. 881:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval None 882:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ 883:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB3_GRP1_EnableClock(uint32_t Periphs) 884:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { 885:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __IO uint32_t tmpreg; 886:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** SET_BIT(RCC->AHB3ENR, Periphs); 887:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Delay after an RCC peripheral clock enabling */ 888:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** tmpreg = READ_BIT(RCC->AHB3ENR, Periphs); 889:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; 890:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } 891:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 892:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** 893:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Check if AHB3 peripheral clock is enabled or not 894:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll AHB3ENR FMCEN LL_AHB3_GRP1_IsEnabledClock\n 895:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB3ENR QSPIEN LL_AHB3_GRP1_IsEnabledClock 896:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: 897:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*) 898:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI 899:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * 900:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. 901:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval State of Periphs (1 or 0). 902:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ 903:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE uint32_t LL_AHB3_GRP1_IsEnabledClock(uint32_t Periphs) 904:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { 905:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** return (READ_BIT(RCC->AHB3ENR, Periphs) == Periphs); 906:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 908:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** 909:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Disable AHB3 peripherals clock. 910:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll AHB3ENR FMCEN LL_AHB3_GRP1_DisableClock\n 911:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB3ENR QSPIEN LL_AHB3_GRP1_DisableClock 912:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: 913:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*) 914:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI 915:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * 916:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. 917:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval None 918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ 919:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB3_GRP1_DisableClock(uint32_t Periphs) 920:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { 921:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** CLEAR_BIT(RCC->AHB3ENR, Periphs); 922:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } 923:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 924:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** 925:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Force AHB3 peripherals reset. 926:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll AHB3RSTR FMCRST LL_AHB3_GRP1_ForceReset\n 927:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB3RSTR QSPIRST LL_AHB3_GRP1_ForceReset 928:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: 929:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB3_GRP1_PERIPH_ALL 930:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*) 931:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI 932:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * 933:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. ARM GAS /tmp/ccYgfTud.s page 202 934:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval None 935:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ 936:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB3_GRP1_ForceReset(uint32_t Periphs) 937:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { 938:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** SET_BIT(RCC->AHB3RSTR, Periphs); 939:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } 940:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 941:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** 942:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Release AHB3 peripherals reset. 943:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll AHB3RSTR FMCRST LL_AHB3_GRP1_ReleaseReset\n 944:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB3RSTR QSPIRST LL_AHB3_GRP1_ReleaseReset 945:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: 946:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_ALL 947:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*) 948:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI 949:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * 950:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. 951:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval None 952:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ 953:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB3_GRP1_ReleaseReset(uint32_t Periphs) 954:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { 955:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** CLEAR_BIT(RCC->AHB3RSTR, Periphs); 956:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } 957:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 958:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** 959:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Enable AHB3 peripheral clocks in low-power mode 960:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll AHB3LPENR FMCLPEN LL_AHB3_GRP1_EnableClockLowPower\n 961:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB3LPENR QSPILPEN LL_AHB3_GRP1_EnableClockLowPower 962:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: 963:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*) 964:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI 965:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * 966:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. 967:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval None 968:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ 969:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB3_GRP1_EnableClockLowPower(uint32_t Periphs) 970:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { 971:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __IO uint32_t tmpreg; 972:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** SET_BIT(RCC->AHB3LPENR, Periphs); 973:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Delay after an RCC peripheral clock enabling */ 974:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** tmpreg = READ_BIT(RCC->AHB3LPENR, Periphs); 975:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; 976:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } 977:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 978:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** 979:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Disable AHB3 peripheral clocks in low-power mode 980:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll AHB3LPENR FMCLPEN LL_AHB3_GRP1_DisableClockLowPower\n 981:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB3LPENR QSPILPEN LL_AHB3_GRP1_DisableClockLowPower 982:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: 983:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*) 984:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI 985:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * 986:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. 987:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval None 988:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ 989:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB3_GRP1_DisableClockLowPower(uint32_t Periphs) 990:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { ARM GAS /tmp/ccYgfTud.s page 203 991:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** CLEAR_BIT(RCC->AHB3LPENR, Periphs); 992:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } 993:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 994:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** 995:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @} 996:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ 997:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 998:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** @defgroup BUS_LL_EF_APB1 APB1 999:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @{ 1000:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ 1001:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 1002:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** 1003:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Enable APB1 peripherals clock. 1004:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_EnableClock\n 1005:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR TIM3EN LL_APB1_GRP1_EnableClock\n 1006:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR TIM4EN LL_APB1_GRP1_EnableClock\n 1007:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR TIM5EN LL_APB1_GRP1_EnableClock\n 1008:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR TIM6EN LL_APB1_GRP1_EnableClock\n 1009:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR TIM7EN LL_APB1_GRP1_EnableClock\n 1010:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR TIM12EN LL_APB1_GRP1_EnableClock\n 1011:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR TIM13EN LL_APB1_GRP1_EnableClock\n 1012:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR TIM14EN LL_APB1_GRP1_EnableClock\n 1013:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR LPTIM1EN LL_APB1_GRP1_EnableClock\n 1014:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR WWDGEN LL_APB1_GRP1_EnableClock\n 1015:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR SPI2EN LL_APB1_GRP1_EnableClock\n 1016:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR SPI3EN LL_APB1_GRP1_EnableClock\n 1017:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR SPDIFRXEN LL_APB1_GRP1_EnableClock\n 1018:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR USART2EN LL_APB1_GRP1_EnableClock\n 1019:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR USART3EN LL_APB1_GRP1_EnableClock\n 1020:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR UART4EN LL_APB1_GRP1_EnableClock\n 1021:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR UART5EN LL_APB1_GRP1_EnableClock\n 1022:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR I2C1EN LL_APB1_GRP1_EnableClock\n 1023:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR I2C2EN LL_APB1_GRP1_EnableClock\n 1024:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR I2C3EN LL_APB1_GRP1_EnableClock\n 1025:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR I2C4EN LL_APB1_GRP1_EnableClock\n 1026:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR CAN1EN LL_APB1_GRP1_EnableClock\n 1027:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR CAN2EN LL_APB1_GRP1_EnableClock\n 1028:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR CAN3EN LL_APB1_GRP1_EnableClock\n 1029:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR CECEN LL_APB1_GRP1_EnableClock\n 1030:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR PWREN LL_APB1_GRP1_EnableClock\n 1031:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR DACEN LL_APB1_GRP1_EnableClock\n 1032:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR UART7EN LL_APB1_GRP1_EnableClock\n 1033:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR UART8EN LL_APB1_GRP1_EnableClock\n 1034:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR RTCEN LL_APB1_GRP1_EnableClock 1035:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: 1036:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 1037:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 1038:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 1039:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 1040:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 1041:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 1042:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 1043:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 1044:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 1045:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 1046:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_WWDG 1047:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 ARM GAS /tmp/ccYgfTud.s page 204 1048:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 1049:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*) 1050:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART2 1051:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART3 1052:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART4 1053:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART5 1054:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 1055:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 1056:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 1057:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C4 (*) 1058:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 1059:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*) 1060:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*) 1061:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) 1062:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_PWR 1063:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 1064:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART7 1065:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART8 1066:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*) 1067:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * 1068:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. 1069:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval None 1070:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ 1071:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs) 1072:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { 1073:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __IO uint32_t tmpreg; 1074:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** SET_BIT(RCC->APB1ENR, Periphs); 1075:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Delay after an RCC peripheral clock enabling */ 1076:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** tmpreg = READ_BIT(RCC->APB1ENR, Periphs); 1077:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; 1078:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } 1079:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 1080:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** 1081:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Check if APB1 peripheral clock is enabled or not 1082:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_IsEnabledClock\n 1083:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR TIM3EN LL_APB1_GRP1_IsEnabledClock\n 1084:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR TIM4EN LL_APB1_GRP1_IsEnabledClock\n 1085:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR TIM5EN LL_APB1_GRP1_IsEnabledClock\n 1086:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR TIM6EN LL_APB1_GRP1_IsEnabledClock\n 1087:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR TIM7EN LL_APB1_GRP1_IsEnabledClock\n 1088:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR TIM12EN LL_APB1_GRP1_IsEnabledClock\n 1089:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR TIM13EN LL_APB1_GRP1_IsEnabledClock\n 1090:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR TIM14EN LL_APB1_GRP1_IsEnabledClock\n 1091:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR LPTIM1EN LL_APB1_GRP1_IsEnabledClock\n 1092:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR WWDGEN LL_APB1_GRP1_IsEnabledClock\n 1093:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR SPI2EN LL_APB1_GRP1_IsEnabledClock\n 1094:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR SPI3EN LL_APB1_GRP1_IsEnabledClock\n 1095:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR SPDIFRXEN LL_APB1_GRP1_IsEnabledClock\n 1096:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR USART2EN LL_APB1_GRP1_IsEnabledClock\n 1097:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR USART3EN LL_APB1_GRP1_IsEnabledClock\n 1098:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR UART4EN LL_APB1_GRP1_IsEnabledClock\n 1099:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR UART5EN LL_APB1_GRP1_IsEnabledClock\n 1100:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR I2C1EN LL_APB1_GRP1_IsEnabledClock\n 1101:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR I2C2EN LL_APB1_GRP1_IsEnabledClock\n 1102:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR I2C3EN LL_APB1_GRP1_IsEnabledClock\n 1103:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR I2C4EN LL_APB1_GRP1_IsEnabledClock\n 1104:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR CAN1EN LL_APB1_GRP1_IsEnabledClock\n ARM GAS /tmp/ccYgfTud.s page 205 1105:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR CAN2EN LL_APB1_GRP1_IsEnabledClock\n 1106:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR CAN3EN LL_APB1_GRP1_IsEnabledClock\n 1107:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR CECEN LL_APB1_GRP1_IsEnabledClock\n 1108:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR PWREN LL_APB1_GRP1_IsEnabledClock\n 1109:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR DACEN LL_APB1_GRP1_IsEnabledClock\n 1110:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR UART7EN LL_APB1_GRP1_IsEnabledClock\n 1111:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR UART8EN LL_APB1_GRP1_IsEnabledClock\n 1112:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR RTCEN LL_APB1_GRP1_IsEnabledClock 1113:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: 1114:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 1115:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 1116:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 1117:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 1118:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 1119:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 1120:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 1121:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 1122:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 1123:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 1124:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_WWDG 1125:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 1126:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 1127:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*) 1128:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART2 1129:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART3 1130:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART4 1131:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART5 1132:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 1133:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 1134:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 1135:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C4 (*) 1136:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 1137:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*) 1138:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*) 1139:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) 1140:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_PWR 1141:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 1142:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART7 1143:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART8 1144:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*) 1145:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * 1146:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. 1147:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval State of Periphs (1 or 0). 1148:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ 1149:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs) 1150:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { 1151:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** return (READ_BIT(RCC->APB1ENR, Periphs) == Periphs); 1152:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } 1153:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 1154:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** 1155:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Disable APB1 peripherals clock. 1156:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_DisableClock\n 1157:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR TIM3EN LL_APB1_GRP1_DisableClock\n 1158:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR TIM4EN LL_APB1_GRP1_DisableClock\n 1159:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR TIM5EN LL_APB1_GRP1_DisableClock\n 1160:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR TIM6EN LL_APB1_GRP1_DisableClock\n 1161:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR TIM7EN LL_APB1_GRP1_DisableClock\n ARM GAS /tmp/ccYgfTud.s page 206 1162:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR TIM12EN LL_APB1_GRP1_DisableClock\n 1163:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR TIM13EN LL_APB1_GRP1_DisableClock\n 1164:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR TIM14EN LL_APB1_GRP1_DisableClock\n 1165:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR LPTIM1EN LL_APB1_GRP1_DisableClock\n 1166:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR WWDGEN LL_APB1_GRP1_DisableClock\n 1167:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR SPI2EN LL_APB1_GRP1_DisableClock\n 1168:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR SPI3EN LL_APB1_GRP1_DisableClock\n 1169:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR SPDIFRXEN LL_APB1_GRP1_DisableClock\n 1170:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR USART2EN LL_APB1_GRP1_DisableClock\n 1171:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR USART3EN LL_APB1_GRP1_DisableClock\n 1172:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR UART4EN LL_APB1_GRP1_DisableClock\n 1173:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR UART5EN LL_APB1_GRP1_DisableClock\n 1174:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR I2C1EN LL_APB1_GRP1_DisableClock\n 1175:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR I2C2EN LL_APB1_GRP1_DisableClock\n 1176:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR I2C3EN LL_APB1_GRP1_DisableClock\n 1177:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR I2C4EN LL_APB1_GRP1_DisableClock\n 1178:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR CAN1EN LL_APB1_GRP1_DisableClock\n 1179:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR CAN2EN LL_APB1_GRP1_DisableClock\n 1180:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR CAN3EN LL_APB1_GRP1_DisableClock\n 1181:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR CECEN LL_APB1_GRP1_DisableClock\n 1182:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR PWREN LL_APB1_GRP1_DisableClock\n 1183:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR DACEN LL_APB1_GRP1_DisableClock\n 1184:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR UART7EN LL_APB1_GRP1_DisableClock\n 1185:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR UART8EN LL_APB1_GRP1_DisableClock\n 1186:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR RTCEN LL_APB1_GRP1_DisableClock 1187:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: 1188:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 1189:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 1190:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 1191:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 1192:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 1193:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 1194:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 1195:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 1196:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 1197:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 1198:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_WWDG 1199:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 1200:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 1201:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*) 1202:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART2 1203:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART3 1204:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART4 1205:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART5 1206:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 1207:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 1208:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 1209:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C4 (*) 1210:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 1211:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*) 1212:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*) 1213:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) 1214:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_PWR 1215:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 1216:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART7 1217:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART8 1218:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*) ARM GAS /tmp/ccYgfTud.s page 207 1219:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * 1220:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. 1221:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval None 1222:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ 1223:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_APB1_GRP1_DisableClock(uint32_t Periphs) 1224:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { 1225:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** CLEAR_BIT(RCC->APB1ENR, Periphs); 1226:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } 1227:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 1228:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** 1229:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Force APB1 peripherals reset. 1230:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll APB1RSTR TIM2RST LL_APB1_GRP1_ForceReset\n 1231:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR TIM3RST LL_APB1_GRP1_ForceReset\n 1232:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR TIM4RST LL_APB1_GRP1_ForceReset\n 1233:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR TIM5RST LL_APB1_GRP1_ForceReset\n 1234:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR TIM6RST LL_APB1_GRP1_ForceReset\n 1235:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR TIM7RST LL_APB1_GRP1_ForceReset\n 1236:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR TIM12RST LL_APB1_GRP1_ForceReset\n 1237:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR TIM13RST LL_APB1_GRP1_ForceReset\n 1238:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR TIM14RST LL_APB1_GRP1_ForceReset\n 1239:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR LPTIM1RST LL_APB1_GRP1_ForceReset\n 1240:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR WWDGRST LL_APB1_GRP1_ForceReset\n 1241:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR SPI2RST LL_APB1_GRP1_ForceReset\n 1242:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR SPI3RST LL_APB1_GRP1_ForceReset\n 1243:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR SPDIFRXRST LL_APB1_GRP1_ForceReset\n 1244:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR USART2RST LL_APB1_GRP1_ForceReset\n 1245:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR USART3RST LL_APB1_GRP1_ForceReset\n 1246:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR UART4RST LL_APB1_GRP1_ForceReset\n 1247:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR UART5RST LL_APB1_GRP1_ForceReset\n 1248:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR I2C1RST LL_APB1_GRP1_ForceReset\n 1249:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR I2C2RST LL_APB1_GRP1_ForceReset\n 1250:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR I2C3RST LL_APB1_GRP1_ForceReset\n 1251:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR I2C4RST LL_APB1_GRP1_ForceReset\n 1252:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR CAN1RST LL_APB1_GRP1_ForceReset\n 1253:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR CAN2RST LL_APB1_GRP1_ForceReset\n 1254:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR CAN3RST LL_APB1_GRP1_ForceReset\n 1255:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR CECRST LL_APB1_GRP1_ForceReset\n 1256:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR PWRRST LL_APB1_GRP1_ForceReset\n 1257:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR DACRST LL_APB1_GRP1_ForceReset\n 1258:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR UART7RST LL_APB1_GRP1_ForceReset\n 1259:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR UART8RST LL_APB1_GRP1_ForceReset 1260:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: 1261:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 1262:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 1263:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 1264:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 1265:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 1266:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 1267:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 1268:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 1269:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 1270:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 1271:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_WWDG 1272:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 1273:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 1274:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*) 1275:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART2 ARM GAS /tmp/ccYgfTud.s page 208 1276:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART3 1277:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART4 1278:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART5 1279:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 1280:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 1281:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 1282:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C4 (*) 1283:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 1284:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*) 1285:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*) 1286:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) 1287:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_PWR 1288:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 1289:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART7 1290:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART8 1291:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * 1292:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. 1293:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval None 1294:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ 1295:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_APB1_GRP1_ForceReset(uint32_t Periphs) 1296:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { 1297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** SET_BIT(RCC->APB1RSTR, Periphs); 1298:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } 1299:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 1300:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** 1301:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Release APB1 peripherals reset. 1302:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll APB1RSTR TIM2RST LL_APB1_GRP1_ReleaseReset\n 1303:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR TIM3RST LL_APB1_GRP1_ReleaseReset\n 1304:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR TIM4RST LL_APB1_GRP1_ReleaseReset\n 1305:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR TIM5RST LL_APB1_GRP1_ReleaseReset\n 1306:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR TIM6RST LL_APB1_GRP1_ReleaseReset\n 1307:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR TIM7RST LL_APB1_GRP1_ReleaseReset\n 1308:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR TIM12RST LL_APB1_GRP1_ReleaseReset\n 1309:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR TIM13RST LL_APB1_GRP1_ReleaseReset\n 1310:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR TIM14RST LL_APB1_GRP1_ReleaseReset\n 1311:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR LPTIM1RST LL_APB1_GRP1_ReleaseReset\n 1312:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR WWDGRST LL_APB1_GRP1_ReleaseReset\n 1313:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR SPI2RST LL_APB1_GRP1_ReleaseReset\n 1314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR SPI3RST LL_APB1_GRP1_ReleaseReset\n 1315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR SPDIFRXRST LL_APB1_GRP1_ReleaseReset\n 1316:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR USART2RST LL_APB1_GRP1_ReleaseReset\n 1317:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR USART3RST LL_APB1_GRP1_ReleaseReset\n 1318:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR UART4RST LL_APB1_GRP1_ReleaseReset\n 1319:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR UART5RST LL_APB1_GRP1_ReleaseReset\n 1320:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR I2C1RST LL_APB1_GRP1_ReleaseReset\n 1321:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR I2C2RST LL_APB1_GRP1_ReleaseReset\n 1322:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR I2C3RST LL_APB1_GRP1_ReleaseReset\n 1323:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR I2C4RST LL_APB1_GRP1_ReleaseReset\n 1324:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR CAN1RST LL_APB1_GRP1_ReleaseReset\n 1325:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR CAN2RST LL_APB1_GRP1_ReleaseReset\n 1326:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR CAN3RST LL_APB1_GRP1_ReleaseReset\n 1327:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR CECRST LL_APB1_GRP1_ReleaseReset\n 1328:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR PWRRST LL_APB1_GRP1_ReleaseReset\n 1329:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR DACRST LL_APB1_GRP1_ReleaseReset\n 1330:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR UART7RST LL_APB1_GRP1_ReleaseReset\n 1331:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR UART8RST LL_APB1_GRP1_ReleaseReset 1332:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: ARM GAS /tmp/ccYgfTud.s page 209 1333:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 1334:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 1335:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 1336:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 1337:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 1338:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 1339:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 1340:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 1341:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 1342:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 1343:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_WWDG 1344:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 1345:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 1346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*) 1347:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART2 1348:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART3 1349:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART4 1350:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART5 1351:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 1352:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 1353:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 1354:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C4 (*) 1355:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 1356:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*) 1357:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*) 1358:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) 1359:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_PWR 1360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 1361:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART7 1362:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART8 1363:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * 1364:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. 1365:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval None 1366:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ 1367:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_APB1_GRP1_ReleaseReset(uint32_t Periphs) 1368:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { 1369:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** CLEAR_BIT(RCC->APB1RSTR, Periphs); 1370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } 1371:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 1372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** 1373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Enable APB1 peripheral clocks in low-power mode 1374:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll APB1LPENR TIM2LPEN LL_APB1_GRP1_EnableClockLowPower\n 1375:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR TIM3LPEN LL_APB1_GRP1_EnableClockLowPower\n 1376:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR TIM4LPEN LL_APB1_GRP1_EnableClockLowPower\n 1377:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR TIM5LPEN LL_APB1_GRP1_EnableClockLowPower\n 1378:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR TIM6LPEN LL_APB1_GRP1_EnableClockLowPower\n 1379:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR TIM7LPEN LL_APB1_GRP1_EnableClockLowPower\n 1380:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR TIM12LPEN LL_APB1_GRP1_EnableClockLowPower\n 1381:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR TIM13LPEN LL_APB1_GRP1_EnableClockLowPower\n 1382:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR TIM14LPEN LL_APB1_GRP1_EnableClockLowPower\n 1383:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR LPTIM1LPEN LL_APB1_GRP1_EnableClockLowPower\n 1384:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR WWDGLPEN LL_APB1_GRP1_EnableClockLowPower\n 1385:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR SPI2LPEN LL_APB1_GRP1_EnableClockLowPower\n 1386:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR SPI3LPEN LL_APB1_GRP1_EnableClockLowPower\n 1387:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR SPDIFRXLPEN LL_APB1_GRP1_EnableClockLowPower\n 1388:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR USART2LPEN LL_APB1_GRP1_EnableClockLowPower\n 1389:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR USART3LPEN LL_APB1_GRP1_EnableClockLowPower\n ARM GAS /tmp/ccYgfTud.s page 210 1390:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR UART4LPEN LL_APB1_GRP1_EnableClockLowPower\n 1391:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR UART5LPEN LL_APB1_GRP1_EnableClockLowPower\n 1392:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR I2C1LPEN LL_APB1_GRP1_EnableClockLowPower\n 1393:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR I2C2LPEN LL_APB1_GRP1_EnableClockLowPower\n 1394:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR I2C3LPEN LL_APB1_GRP1_EnableClockLowPower\n 1395:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR I2C4LPEN LL_APB1_GRP1_EnableClockLowPower\n 1396:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR CAN1LPEN LL_APB1_GRP1_EnableClockLowPower\n 1397:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR CAN2LPEN LL_APB1_GRP1_EnableClockLowPower\n 1398:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR CAN3LPEN LL_APB1_GRP1_EnableClockLowPower\n 1399:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR CECLPEN LL_APB1_GRP1_EnableClockLowPower\n 1400:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR PWRLPEN LL_APB1_GRP1_EnableClockLowPower\n 1401:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR DACLPEN LL_APB1_GRP1_EnableClockLowPower\n 1402:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR UART7LPEN LL_APB1_GRP1_EnableClockLowPower\n 1403:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR UART8LPEN LL_APB1_GRP1_EnableClockLowPower\n 1404:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR RTCLPEN LL_APB1_GRP1_EnableClockLowPower 1405:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: 1406:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 1407:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 1408:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 1409:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 1410:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 1411:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 1412:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 1413:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 1414:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 1415:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 1416:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_WWDG 1417:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 1418:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 1419:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*) 1420:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART2 1421:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART3 1422:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART4 1423:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART5 1424:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 1425:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 1426:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 1427:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C4 (*) 1428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 1429:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*) 1430:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*) 1431:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) 1432:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_PWR 1433:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 1434:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART7 1435:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART8 1436:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*) 1437:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * 1438:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. 1439:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval None 1440:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ 1441:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_APB1_GRP1_EnableClockLowPower(uint32_t Periphs) 1442:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { 1443:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __IO uint32_t tmpreg; 1444:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** SET_BIT(RCC->APB1LPENR, Periphs); 1445:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Delay after an RCC peripheral clock enabling */ 1446:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** tmpreg = READ_BIT(RCC->APB1LPENR, Periphs); ARM GAS /tmp/ccYgfTud.s page 211 1447:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; 1448:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } 1449:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 1450:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** 1451:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Disable APB1 peripheral clocks in low-power mode 1452:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll APB1LPENR TIM2LPEN LL_APB1_GRP1_DisableClockLowPower\n 1453:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR TIM3LPEN LL_APB1_GRP1_DisableClockLowPower\n 1454:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR TIM4LPEN LL_APB1_GRP1_DisableClockLowPower\n 1455:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR TIM5LPEN LL_APB1_GRP1_DisableClockLowPower\n 1456:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR TIM6LPEN LL_APB1_GRP1_DisableClockLowPower\n 1457:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR TIM7LPEN LL_APB1_GRP1_DisableClockLowPower\n 1458:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR TIM12LPEN LL_APB1_GRP1_DisableClockLowPower\n 1459:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR TIM13LPEN LL_APB1_GRP1_DisableClockLowPower\n 1460:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR TIM14LPEN LL_APB1_GRP1_DisableClockLowPower\n 1461:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR LPTIM1LPEN LL_APB1_GRP1_DisableClockLowPower\n 1462:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR WWDGLPEN LL_APB1_GRP1_DisableClockLowPower\n 1463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR SPI2LPEN LL_APB1_GRP1_DisableClockLowPower\n 1464:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR SPI3LPEN LL_APB1_GRP1_DisableClockLowPower\n 1465:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR SPDIFRXLPEN LL_APB1_GRP1_DisableClockLowPower\n 1466:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR USART2LPEN LL_APB1_GRP1_DisableClockLowPower\n 1467:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR USART3LPEN LL_APB1_GRP1_DisableClockLowPower\n 1468:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR UART4LPEN LL_APB1_GRP1_DisableClockLowPower\n 1469:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR UART5LPEN LL_APB1_GRP1_DisableClockLowPower\n 1470:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR I2C1LPEN LL_APB1_GRP1_DisableClockLowPower\n 1471:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR I2C2LPEN LL_APB1_GRP1_DisableClockLowPower\n 1472:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR I2C3LPEN LL_APB1_GRP1_DisableClockLowPower\n 1473:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR I2C4LPEN LL_APB1_GRP1_DisableClockLowPower\n 1474:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR CAN1LPEN LL_APB1_GRP1_DisableClockLowPower\n 1475:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR CAN2LPEN LL_APB1_GRP1_DisableClockLowPower\n 1476:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR CAN3LPEN LL_APB1_GRP1_DisableClockLowPower\n 1477:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR CECLPEN LL_APB1_GRP1_DisableClockLowPower\n 1478:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR PWRLPEN LL_APB1_GRP1_DisableClockLowPower\n 1479:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR DACLPEN LL_APB1_GRP1_DisableClockLowPower\n 1480:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR UART7LPEN LL_APB1_GRP1_DisableClockLowPower\n 1481:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR UART8LPEN LL_APB1_GRP1_DisableClockLowPower\n 1482:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR RTCLPEN LL_APB1_GRP1_DisableClockLowPower 1483:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: 1484:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 1485:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 1486:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 1487:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 1488:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 1489:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 1490:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 1491:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 1492:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 1493:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 1494:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_WWDG 1495:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 1496:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 1497:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*) 1498:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART2 1499:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART3 1500:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART4 1501:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART5 1502:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 1503:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 ARM GAS /tmp/ccYgfTud.s page 212 1504:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 1505:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C4 (*) 1506:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 1507:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*) 1508:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*) 1509:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) 1510:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_PWR 1511:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 1512:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART7 1513:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART8 1514:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*) 1515:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * 1516:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. 1517:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval None 1518:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ 1519:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_APB1_GRP1_DisableClockLowPower(uint32_t Periphs) 1520:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { 1521:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** CLEAR_BIT(RCC->APB1LPENR, Periphs); 1522:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } 1523:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 1524:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** 1525:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @} 1526:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ 1527:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 1528:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** @defgroup BUS_LL_EF_APB2 APB2 1529:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @{ 1530:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ 1531:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 1532:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** 1533:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Enable APB2 peripherals clock. 1534:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll APB2ENR TIM1EN LL_APB2_GRP1_EnableClock\n 1535:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR TIM8EN LL_APB2_GRP1_EnableClock\n 1536:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR USART1EN LL_APB2_GRP1_EnableClock\n 1537:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR USART6EN LL_APB2_GRP1_EnableClock\n 1538:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR ADC1EN LL_APB2_GRP1_EnableClock\n 1539:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR ADC2EN LL_APB2_GRP1_EnableClock\n 1540:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR ADC3EN LL_APB2_GRP1_EnableClock\n 1541:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR SDMMC1EN LL_APB2_GRP1_EnableClock\n 1542:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR SDMMC2EN LL_APB2_GRP1_EnableClock\n 1543:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR SPI1EN LL_APB2_GRP1_EnableClock\n 1544:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR SPI4EN LL_APB2_GRP1_EnableClock\n 1545:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR SYSCFGEN LL_APB2_GRP1_EnableClock\n 1546:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR TIM9EN LL_APB2_GRP1_EnableClock\n 1547:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR TIM10EN LL_APB2_GRP1_EnableClock\n 1548:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR TIM11EN LL_APB2_GRP1_EnableClock\n 1549:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR SPI5EN LL_APB2_GRP1_EnableClock\n 1550:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR SPI6EN LL_APB2_GRP1_EnableClock\n 1551:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR SAI1EN LL_APB2_GRP1_EnableClock\n 1552:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR SAI2EN LL_APB2_GRP1_EnableClock\n 1553:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR LTDCEN LL_APB2_GRP1_EnableClock\n 1554:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR DSIEN LL_APB2_GRP1_EnableClock\n 1555:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR DFSDM1EN LL_APB2_GRP1_EnableClock\n 1556:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR MDIOEN LL_APB2_GRP1_EnableClock\n 1557:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR OTGPHYCEN LL_APB2_GRP1_EnableClock 1558:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: 1559:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 1560:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 ARM GAS /tmp/ccYgfTud.s page 213 1561:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_USART1 1562:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_USART6 1563:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_ADC1 1564:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_ADC2 1565:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_ADC3 1566:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1 1567:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC2 (*) 1568:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 1569:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 1570:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG 1571:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_TIM9 1572:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_TIM10 1573:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_TIM11 1574:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 1575:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*) 1576:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 1577:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 1578:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*) 1579:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*) 1580:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*) 1581:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_MDIO (*) 1582:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_OTGPHYC (*) 1583:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * 1584:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. 1585:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval None 1586:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ 1587:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_APB2_GRP1_EnableClock(uint32_t Periphs) 3259 .loc 3 1587 22 view .LVU1016 3260 .LBB424: 1588:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { 1589:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __IO uint32_t tmpreg; 3261 .loc 3 1589 3 view .LVU1017 1590:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** SET_BIT(RCC->APB2ENR, Periphs); 3262 .loc 3 1590 3 view .LVU1018 3263 001e 2A4B ldr r3, .L183 3264 0020 5A6C ldr r2, [r3, #68] 3265 0022 42F40052 orr r2, r2, #8192 3266 0026 5A64 str r2, [r3, #68] 1591:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Delay after an RCC peripheral clock enabling */ 1592:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** tmpreg = READ_BIT(RCC->APB2ENR, Periphs); 3267 .loc 3 1592 3 view .LVU1019 3268 .loc 3 1592 12 is_stmt 0 view .LVU1020 3269 0028 5A6C ldr r2, [r3, #68] 3270 002a 02F40052 and r2, r2, #8192 3271 .loc 3 1592 10 view .LVU1021 3272 002e 0192 str r2, [sp, #4] 1593:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; 3273 .loc 3 1593 3 is_stmt 1 view .LVU1022 3274 0030 019A ldr r2, [sp, #4] 3275 .LVL326: 3276 .loc 3 1593 3 is_stmt 0 view .LVU1023 3277 .LBE424: 3278 .LBE423: 1192:Src/main.c **** /**SPI4 GPIO Configuration 3279 .loc 1 1192 3 is_stmt 1 view .LVU1024 3280 .LBB425: 3281 .LBI425: ARM GAS /tmp/ccYgfTud.s page 214 309:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { 3282 .loc 3 309 22 view .LVU1025 3283 .LBB426: 311:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** SET_BIT(RCC->AHB1ENR, Periphs); 3284 .loc 3 311 3 view .LVU1026 312:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Delay after an RCC peripheral clock enabling */ 3285 .loc 3 312 3 view .LVU1027 3286 0032 1A6B ldr r2, [r3, #48] 3287 0034 42F01002 orr r2, r2, #16 3288 0038 1A63 str r2, [r3, #48] 314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; 3289 .loc 3 314 3 view .LVU1028 314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; 3290 .loc 3 314 12 is_stmt 0 view .LVU1029 3291 003a 1B6B ldr r3, [r3, #48] 3292 003c 03F01003 and r3, r3, #16 314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; 3293 .loc 3 314 10 view .LVU1030 3294 0040 0093 str r3, [sp] 315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } 3295 .loc 3 315 3 is_stmt 1 view .LVU1031 3296 0042 009B ldr r3, [sp] 3297 .LVL327: 315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } 3298 .loc 3 315 3 is_stmt 0 view .LVU1032 3299 .LBE426: 3300 .LBE425: 1197:Src/main.c **** GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE; 3301 .loc 1 1197 3 is_stmt 1 view .LVU1033 1197:Src/main.c **** GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE; 3302 .loc 1 1197 23 is_stmt 0 view .LVU1034 3303 0044 4FF48053 mov r3, #4096 3304 0048 0293 str r3, [sp, #8] 1198:Src/main.c **** GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH; 3305 .loc 1 1198 3 is_stmt 1 view .LVU1035 1198:Src/main.c **** GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH; 3306 .loc 1 1198 24 is_stmt 0 view .LVU1036 3307 004a 0225 movs r5, #2 3308 004c 0395 str r5, [sp, #12] 1199:Src/main.c **** GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; 3309 .loc 1 1199 3 is_stmt 1 view .LVU1037 1199:Src/main.c **** GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; 3310 .loc 1 1199 25 is_stmt 0 view .LVU1038 3311 004e 4FF00308 mov r8, #3 3312 0052 CDF81080 str r8, [sp, #16] 1200:Src/main.c **** GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; 3313 .loc 1 1200 3 is_stmt 1 view .LVU1039 1201:Src/main.c **** GPIO_InitStruct.Alternate = LL_GPIO_AF_5; 3314 .loc 1 1201 3 view .LVU1040 1202:Src/main.c **** LL_GPIO_Init(GPIOE, &GPIO_InitStruct); 3315 .loc 1 1202 3 view .LVU1041 1202:Src/main.c **** LL_GPIO_Init(GPIOE, &GPIO_InitStruct); 3316 .loc 1 1202 29 is_stmt 0 view .LVU1042 3317 0056 0527 movs r7, #5 3318 0058 0797 str r7, [sp, #28] 1203:Src/main.c **** 3319 .loc 1 1203 3 is_stmt 1 view .LVU1043 ARM GAS /tmp/ccYgfTud.s page 215 3320 005a 1C4E ldr r6, .L183+4 3321 005c 02A9 add r1, sp, #8 3322 005e 3046 mov r0, r6 3323 0060 FFF7FEFF bl LL_GPIO_Init 3324 .LVL328: 1205:Src/main.c **** GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE; 3325 .loc 1 1205 3 view .LVU1044 1205:Src/main.c **** GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE; 3326 .loc 1 1205 23 is_stmt 0 view .LVU1045 3327 0064 4FF40053 mov r3, #8192 3328 0068 0293 str r3, [sp, #8] 1206:Src/main.c **** GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH; 3329 .loc 1 1206 3 is_stmt 1 view .LVU1046 1206:Src/main.c **** GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH; 3330 .loc 1 1206 24 is_stmt 0 view .LVU1047 3331 006a 0395 str r5, [sp, #12] 1207:Src/main.c **** GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; 3332 .loc 1 1207 3 is_stmt 1 view .LVU1048 1207:Src/main.c **** GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; 3333 .loc 1 1207 25 is_stmt 0 view .LVU1049 3334 006c CDF81080 str r8, [sp, #16] 1208:Src/main.c **** GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; 3335 .loc 1 1208 3 is_stmt 1 view .LVU1050 1208:Src/main.c **** GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; 3336 .loc 1 1208 30 is_stmt 0 view .LVU1051 3337 0070 0594 str r4, [sp, #20] 1209:Src/main.c **** GPIO_InitStruct.Alternate = LL_GPIO_AF_5; 3338 .loc 1 1209 3 is_stmt 1 view .LVU1052 1209:Src/main.c **** GPIO_InitStruct.Alternate = LL_GPIO_AF_5; 3339 .loc 1 1209 24 is_stmt 0 view .LVU1053 3340 0072 0694 str r4, [sp, #24] 1210:Src/main.c **** LL_GPIO_Init(GPIOE, &GPIO_InitStruct); 3341 .loc 1 1210 3 is_stmt 1 view .LVU1054 1210:Src/main.c **** LL_GPIO_Init(GPIOE, &GPIO_InitStruct); 3342 .loc 1 1210 29 is_stmt 0 view .LVU1055 3343 0074 0797 str r7, [sp, #28] 1211:Src/main.c **** 3344 .loc 1 1211 3 is_stmt 1 view .LVU1056 3345 0076 02A9 add r1, sp, #8 3346 0078 3046 mov r0, r6 3347 007a FFF7FEFF bl LL_GPIO_Init 3348 .LVL329: 1217:Src/main.c **** SPI_InitStruct.Mode = LL_SPI_MODE_MASTER; 3349 .loc 1 1217 3 view .LVU1057 1217:Src/main.c **** SPI_InitStruct.Mode = LL_SPI_MODE_MASTER; 3350 .loc 1 1217 36 is_stmt 0 view .LVU1058 3351 007e 4FF48063 mov r3, #1024 3352 0082 0893 str r3, [sp, #32] 1218:Src/main.c **** SPI_InitStruct.DataWidth = LL_SPI_DATAWIDTH_16BIT; 3353 .loc 1 1218 3 is_stmt 1 view .LVU1059 1218:Src/main.c **** SPI_InitStruct.DataWidth = LL_SPI_DATAWIDTH_16BIT; 3354 .loc 1 1218 23 is_stmt 0 view .LVU1060 3355 0084 4FF48273 mov r3, #260 3356 0088 0993 str r3, [sp, #36] 1219:Src/main.c **** SPI_InitStruct.ClockPolarity = LL_SPI_POLARITY_HIGH; 3357 .loc 1 1219 3 is_stmt 1 view .LVU1061 1219:Src/main.c **** SPI_InitStruct.ClockPolarity = LL_SPI_POLARITY_HIGH; ARM GAS /tmp/ccYgfTud.s page 216 3358 .loc 1 1219 28 is_stmt 0 view .LVU1062 3359 008a 4FF47063 mov r3, #3840 3360 008e 0A93 str r3, [sp, #40] 1220:Src/main.c **** SPI_InitStruct.ClockPhase = LL_SPI_PHASE_1EDGE; 3361 .loc 1 1220 3 is_stmt 1 view .LVU1063 1220:Src/main.c **** SPI_InitStruct.ClockPhase = LL_SPI_PHASE_1EDGE; 3362 .loc 1 1220 32 is_stmt 0 view .LVU1064 3363 0090 0B95 str r5, [sp, #44] 1221:Src/main.c **** SPI_InitStruct.NSS = LL_SPI_NSS_SOFT; 3364 .loc 1 1221 3 is_stmt 1 view .LVU1065 1221:Src/main.c **** SPI_InitStruct.NSS = LL_SPI_NSS_SOFT; 3365 .loc 1 1221 29 is_stmt 0 view .LVU1066 3366 0092 0C94 str r4, [sp, #48] 1222:Src/main.c **** SPI_InitStruct.BaudRate = LL_SPI_BAUDRATEPRESCALER_DIV16; 3367 .loc 1 1222 3 is_stmt 1 view .LVU1067 1222:Src/main.c **** SPI_InitStruct.BaudRate = LL_SPI_BAUDRATEPRESCALER_DIV16; 3368 .loc 1 1222 22 is_stmt 0 view .LVU1068 3369 0094 4FF40073 mov r3, #512 3370 0098 0D93 str r3, [sp, #52] 1223:Src/main.c **** SPI_InitStruct.BitOrder = LL_SPI_MSB_FIRST; 3371 .loc 1 1223 3 is_stmt 1 view .LVU1069 1223:Src/main.c **** SPI_InitStruct.BitOrder = LL_SPI_MSB_FIRST; 3372 .loc 1 1223 27 is_stmt 0 view .LVU1070 3373 009a 1823 movs r3, #24 3374 009c 0E93 str r3, [sp, #56] 1224:Src/main.c **** SPI_InitStruct.CRCCalculation = LL_SPI_CRCCALCULATION_DISABLE; 3375 .loc 1 1224 3 is_stmt 1 view .LVU1071 1224:Src/main.c **** SPI_InitStruct.CRCCalculation = LL_SPI_CRCCALCULATION_DISABLE; 3376 .loc 1 1224 27 is_stmt 0 view .LVU1072 3377 009e 0F94 str r4, [sp, #60] 1225:Src/main.c **** SPI_InitStruct.CRCPoly = 7; 3378 .loc 1 1225 3 is_stmt 1 view .LVU1073 1225:Src/main.c **** SPI_InitStruct.CRCPoly = 7; 3379 .loc 1 1225 33 is_stmt 0 view .LVU1074 3380 00a0 1094 str r4, [sp, #64] 1226:Src/main.c **** LL_SPI_Init(SPI4, &SPI_InitStruct); 3381 .loc 1 1226 3 is_stmt 1 view .LVU1075 1226:Src/main.c **** LL_SPI_Init(SPI4, &SPI_InitStruct); 3382 .loc 1 1226 26 is_stmt 0 view .LVU1076 3383 00a2 0723 movs r3, #7 3384 00a4 1193 str r3, [sp, #68] 1227:Src/main.c **** LL_SPI_SetStandard(SPI4, LL_SPI_PROTOCOL_MOTOROLA); 3385 .loc 1 1227 3 is_stmt 1 view .LVU1077 3386 00a6 0A4C ldr r4, .L183+8 3387 00a8 08A9 add r1, sp, #32 3388 00aa 2046 mov r0, r4 3389 00ac FFF7FEFF bl LL_SPI_Init 3390 .LVL330: 1228:Src/main.c **** LL_SPI_DisableNSSPulseMgt(SPI4); 3391 .loc 1 1228 3 view .LVU1078 3392 .LBB427: 3393 .LBI427: 426:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 3394 .loc 4 426 22 view .LVU1079 3395 .LBB428: 428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 3396 .loc 4 428 3 view .LVU1080 ARM GAS /tmp/ccYgfTud.s page 217 3397 00b0 6368 ldr r3, [r4, #4] 3398 00b2 23F01003 bic r3, r3, #16 3399 00b6 6360 str r3, [r4, #4] 3400 .LVL331: 428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 3401 .loc 4 428 3 is_stmt 0 view .LVU1081 3402 .LBE428: 3403 .LBE427: 1229:Src/main.c **** /* USER CODE BEGIN SPI4_Init 2 */ 3404 .loc 1 1229 3 is_stmt 1 view .LVU1082 3405 .LBB429: 3406 .LBI429: 874:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 3407 .loc 4 874 22 view .LVU1083 3408 .LBB430: 876:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 3409 .loc 4 876 3 view .LVU1084 3410 00b8 6368 ldr r3, [r4, #4] 3411 00ba 23F00803 bic r3, r3, #8 3412 00be 6360 str r3, [r4, #4] 3413 .LVL332: 876:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 3414 .loc 4 876 3 is_stmt 0 view .LVU1085 3415 .LBE430: 3416 .LBE429: 1234:Src/main.c **** 3417 .loc 1 1234 1 view .LVU1086 3418 00c0 12B0 add sp, sp, #72 3419 .LCFI31: 3420 .cfi_def_cfa_offset 24 3421 @ sp needed 3422 00c2 BDE8F081 pop {r4, r5, r6, r7, r8, pc} 3423 .L184: 3424 00c6 00BF .align 2 3425 .L183: 3426 00c8 00380240 .word 1073887232 3427 00cc 00100240 .word 1073876992 3428 00d0 00340140 .word 1073820672 3429 .cfi_endproc 3430 .LFE1192: 3432 .section .text.MX_SPI2_Init,"ax",%progbits 3433 .align 1 3434 .syntax unified 3435 .thumb 3436 .thumb_func 3438 MX_SPI2_Init: 3439 .LFB1191: 1107:Src/main.c **** 3440 .loc 1 1107 1 is_stmt 1 view -0 3441 .cfi_startproc 3442 @ args = 0, pretend = 0, frame = 72 3443 @ frame_needed = 0, uses_anonymous_args = 0 3444 0000 2DE9F041 push {r4, r5, r6, r7, r8, lr} 3445 .LCFI32: 3446 .cfi_def_cfa_offset 24 3447 .cfi_offset 4, -24 3448 .cfi_offset 5, -20 ARM GAS /tmp/ccYgfTud.s page 218 3449 .cfi_offset 6, -16 3450 .cfi_offset 7, -12 3451 .cfi_offset 8, -8 3452 .cfi_offset 14, -4 3453 0004 92B0 sub sp, sp, #72 3454 .LCFI33: 3455 .cfi_def_cfa_offset 96 1113:Src/main.c **** 3456 .loc 1 1113 3 view .LVU1088 1113:Src/main.c **** 3457 .loc 1 1113 22 is_stmt 0 view .LVU1089 3458 0006 2822 movs r2, #40 3459 0008 0021 movs r1, #0 3460 000a 08A8 add r0, sp, #32 3461 000c FFF7FEFF bl memset 3462 .LVL333: 1115:Src/main.c **** 3463 .loc 1 1115 3 is_stmt 1 view .LVU1090 1115:Src/main.c **** 3464 .loc 1 1115 23 is_stmt 0 view .LVU1091 3465 0010 0024 movs r4, #0 3466 0012 0294 str r4, [sp, #8] 3467 0014 0394 str r4, [sp, #12] 3468 0016 0494 str r4, [sp, #16] 3469 0018 0594 str r4, [sp, #20] 3470 001a 0694 str r4, [sp, #24] 3471 001c 0794 str r4, [sp, #28] 1118:Src/main.c **** 3472 .loc 1 1118 3 is_stmt 1 view .LVU1092 3473 .LVL334: 3474 .LBB431: 3475 .LBI431: 1071:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { 3476 .loc 3 1071 22 view .LVU1093 3477 .LBB432: 1073:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** SET_BIT(RCC->APB1ENR, Periphs); 3478 .loc 3 1073 3 view .LVU1094 1074:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Delay after an RCC peripheral clock enabling */ 3479 .loc 3 1074 3 view .LVU1095 3480 001e 2F4B ldr r3, .L187 3481 0020 1A6C ldr r2, [r3, #64] 3482 0022 42F48042 orr r2, r2, #16384 3483 0026 1A64 str r2, [r3, #64] 1076:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; 3484 .loc 3 1076 3 view .LVU1096 1076:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; 3485 .loc 3 1076 12 is_stmt 0 view .LVU1097 3486 0028 1A6C ldr r2, [r3, #64] 3487 002a 02F48042 and r2, r2, #16384 1076:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; 3488 .loc 3 1076 10 view .LVU1098 3489 002e 0192 str r2, [sp, #4] 1077:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } 3490 .loc 3 1077 3 is_stmt 1 view .LVU1099 3491 0030 019A ldr r2, [sp, #4] 3492 .LVL335: 1077:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } ARM GAS /tmp/ccYgfTud.s page 219 3493 .loc 3 1077 3 is_stmt 0 view .LVU1100 3494 .LBE432: 3495 .LBE431: 1120:Src/main.c **** /**SPI2 GPIO Configuration 3496 .loc 1 1120 3 is_stmt 1 view .LVU1101 3497 .LBB433: 3498 .LBI433: 309:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { 3499 .loc 3 309 22 view .LVU1102 3500 .LBB434: 311:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** SET_BIT(RCC->AHB1ENR, Periphs); 3501 .loc 3 311 3 view .LVU1103 312:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Delay after an RCC peripheral clock enabling */ 3502 .loc 3 312 3 view .LVU1104 3503 0032 1A6B ldr r2, [r3, #48] 3504 0034 42F00202 orr r2, r2, #2 3505 0038 1A63 str r2, [r3, #48] 314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; 3506 .loc 3 314 3 view .LVU1105 314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; 3507 .loc 3 314 12 is_stmt 0 view .LVU1106 3508 003a 1B6B ldr r3, [r3, #48] 3509 003c 03F00203 and r3, r3, #2 314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; 3510 .loc 3 314 10 view .LVU1107 3511 0040 0093 str r3, [sp] 315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } 3512 .loc 3 315 3 is_stmt 1 view .LVU1108 3513 0042 009B ldr r3, [sp] 3514 .LVL336: 315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } 3515 .loc 3 315 3 is_stmt 0 view .LVU1109 3516 .LBE434: 3517 .LBE433: 1126:Src/main.c **** GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE; 3518 .loc 1 1126 3 is_stmt 1 view .LVU1110 1126:Src/main.c **** GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE; 3519 .loc 1 1126 23 is_stmt 0 view .LVU1111 3520 0044 4FF40053 mov r3, #8192 3521 0048 0293 str r3, [sp, #8] 1127:Src/main.c **** GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH; 3522 .loc 1 1127 3 is_stmt 1 view .LVU1112 1127:Src/main.c **** GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH; 3523 .loc 1 1127 24 is_stmt 0 view .LVU1113 3524 004a 4FF00208 mov r8, #2 3525 004e CDF80C80 str r8, [sp, #12] 1128:Src/main.c **** GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; 3526 .loc 1 1128 3 is_stmt 1 view .LVU1114 1128:Src/main.c **** GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; 3527 .loc 1 1128 25 is_stmt 0 view .LVU1115 3528 0052 0327 movs r7, #3 3529 0054 0497 str r7, [sp, #16] 1129:Src/main.c **** GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; 3530 .loc 1 1129 3 is_stmt 1 view .LVU1116 1130:Src/main.c **** GPIO_InitStruct.Alternate = LL_GPIO_AF_5; 3531 .loc 1 1130 3 view .LVU1117 1131:Src/main.c **** LL_GPIO_Init(GPIOB, &GPIO_InitStruct); ARM GAS /tmp/ccYgfTud.s page 220 3532 .loc 1 1131 3 view .LVU1118 1131:Src/main.c **** LL_GPIO_Init(GPIOB, &GPIO_InitStruct); 3533 .loc 1 1131 29 is_stmt 0 view .LVU1119 3534 0056 0526 movs r6, #5 3535 0058 0796 str r6, [sp, #28] 1132:Src/main.c **** 3536 .loc 1 1132 3 is_stmt 1 view .LVU1120 3537 005a 214D ldr r5, .L187+4 3538 005c 02A9 add r1, sp, #8 3539 005e 2846 mov r0, r5 3540 0060 FFF7FEFF bl LL_GPIO_Init 3541 .LVL337: 1134:Src/main.c **** GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE; 3542 .loc 1 1134 3 view .LVU1121 1134:Src/main.c **** GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE; 3543 .loc 1 1134 23 is_stmt 0 view .LVU1122 3544 0064 4FF48043 mov r3, #16384 3545 0068 0293 str r3, [sp, #8] 1135:Src/main.c **** GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH; 3546 .loc 1 1135 3 is_stmt 1 view .LVU1123 1135:Src/main.c **** GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH; 3547 .loc 1 1135 24 is_stmt 0 view .LVU1124 3548 006a CDF80C80 str r8, [sp, #12] 1136:Src/main.c **** GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; 3549 .loc 1 1136 3 is_stmt 1 view .LVU1125 1136:Src/main.c **** GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; 3550 .loc 1 1136 25 is_stmt 0 view .LVU1126 3551 006e 0497 str r7, [sp, #16] 1137:Src/main.c **** GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; 3552 .loc 1 1137 3 is_stmt 1 view .LVU1127 1137:Src/main.c **** GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; 3553 .loc 1 1137 30 is_stmt 0 view .LVU1128 3554 0070 0594 str r4, [sp, #20] 1138:Src/main.c **** GPIO_InitStruct.Alternate = LL_GPIO_AF_5; 3555 .loc 1 1138 3 is_stmt 1 view .LVU1129 1138:Src/main.c **** GPIO_InitStruct.Alternate = LL_GPIO_AF_5; 3556 .loc 1 1138 24 is_stmt 0 view .LVU1130 3557 0072 0694 str r4, [sp, #24] 1139:Src/main.c **** LL_GPIO_Init(GPIOB, &GPIO_InitStruct); 3558 .loc 1 1139 3 is_stmt 1 view .LVU1131 1139:Src/main.c **** LL_GPIO_Init(GPIOB, &GPIO_InitStruct); 3559 .loc 1 1139 29 is_stmt 0 view .LVU1132 3560 0074 0796 str r6, [sp, #28] 1140:Src/main.c **** 3561 .loc 1 1140 3 is_stmt 1 view .LVU1133 3562 0076 02A9 add r1, sp, #8 3563 0078 2846 mov r0, r5 3564 007a FFF7FEFF bl LL_GPIO_Init 3565 .LVL338: 1142:Src/main.c **** GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE; 3566 .loc 1 1142 3 view .LVU1134 1142:Src/main.c **** GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE; 3567 .loc 1 1142 23 is_stmt 0 view .LVU1135 3568 007e 4FF40043 mov r3, #32768 3569 0082 0293 str r3, [sp, #8] 1143:Src/main.c **** GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH; 3570 .loc 1 1143 3 is_stmt 1 view .LVU1136 ARM GAS /tmp/ccYgfTud.s page 221 1143:Src/main.c **** GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH; 3571 .loc 1 1143 24 is_stmt 0 view .LVU1137 3572 0084 CDF80C80 str r8, [sp, #12] 1144:Src/main.c **** GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; 3573 .loc 1 1144 3 is_stmt 1 view .LVU1138 1144:Src/main.c **** GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; 3574 .loc 1 1144 25 is_stmt 0 view .LVU1139 3575 0088 0497 str r7, [sp, #16] 1145:Src/main.c **** GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; 3576 .loc 1 1145 3 is_stmt 1 view .LVU1140 1145:Src/main.c **** GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; 3577 .loc 1 1145 30 is_stmt 0 view .LVU1141 3578 008a 0594 str r4, [sp, #20] 1146:Src/main.c **** GPIO_InitStruct.Alternate = LL_GPIO_AF_5; 3579 .loc 1 1146 3 is_stmt 1 view .LVU1142 1146:Src/main.c **** GPIO_InitStruct.Alternate = LL_GPIO_AF_5; 3580 .loc 1 1146 24 is_stmt 0 view .LVU1143 3581 008c 0694 str r4, [sp, #24] 1147:Src/main.c **** LL_GPIO_Init(GPIOB, &GPIO_InitStruct); 3582 .loc 1 1147 3 is_stmt 1 view .LVU1144 1147:Src/main.c **** LL_GPIO_Init(GPIOB, &GPIO_InitStruct); 3583 .loc 1 1147 29 is_stmt 0 view .LVU1145 3584 008e 0796 str r6, [sp, #28] 1148:Src/main.c **** 3585 .loc 1 1148 3 is_stmt 1 view .LVU1146 3586 0090 02A9 add r1, sp, #8 3587 0092 2846 mov r0, r5 3588 0094 FFF7FEFF bl LL_GPIO_Init 3589 .LVL339: 1154:Src/main.c **** SPI_InitStruct.Mode = LL_SPI_MODE_MASTER; 3590 .loc 1 1154 3 view .LVU1147 1154:Src/main.c **** SPI_InitStruct.Mode = LL_SPI_MODE_MASTER; 3591 .loc 1 1154 36 is_stmt 0 view .LVU1148 3592 0098 0894 str r4, [sp, #32] 1155:Src/main.c **** SPI_InitStruct.DataWidth = LL_SPI_DATAWIDTH_16BIT; 3593 .loc 1 1155 3 is_stmt 1 view .LVU1149 1155:Src/main.c **** SPI_InitStruct.DataWidth = LL_SPI_DATAWIDTH_16BIT; 3594 .loc 1 1155 23 is_stmt 0 view .LVU1150 3595 009a 4FF48273 mov r3, #260 3596 009e 0993 str r3, [sp, #36] 1156:Src/main.c **** SPI_InitStruct.ClockPolarity = LL_SPI_POLARITY_LOW; 3597 .loc 1 1156 3 is_stmt 1 view .LVU1151 1156:Src/main.c **** SPI_InitStruct.ClockPolarity = LL_SPI_POLARITY_LOW; 3598 .loc 1 1156 28 is_stmt 0 view .LVU1152 3599 00a0 4FF47063 mov r3, #3840 3600 00a4 0A93 str r3, [sp, #40] 1157:Src/main.c **** SPI_InitStruct.ClockPhase = LL_SPI_PHASE_1EDGE; 3601 .loc 1 1157 3 is_stmt 1 view .LVU1153 1157:Src/main.c **** SPI_InitStruct.ClockPhase = LL_SPI_PHASE_1EDGE; 3602 .loc 1 1157 32 is_stmt 0 view .LVU1154 3603 00a6 0B94 str r4, [sp, #44] 1158:Src/main.c **** SPI_InitStruct.NSS = LL_SPI_NSS_SOFT; 3604 .loc 1 1158 3 is_stmt 1 view .LVU1155 1158:Src/main.c **** SPI_InitStruct.NSS = LL_SPI_NSS_SOFT; 3605 .loc 1 1158 29 is_stmt 0 view .LVU1156 3606 00a8 0C94 str r4, [sp, #48] 1159:Src/main.c **** SPI_InitStruct.BaudRate = LL_SPI_BAUDRATEPRESCALER_DIV8; ARM GAS /tmp/ccYgfTud.s page 222 3607 .loc 1 1159 3 is_stmt 1 view .LVU1157 1159:Src/main.c **** SPI_InitStruct.BaudRate = LL_SPI_BAUDRATEPRESCALER_DIV8; 3608 .loc 1 1159 22 is_stmt 0 view .LVU1158 3609 00aa 4FF40073 mov r3, #512 3610 00ae 0D93 str r3, [sp, #52] 1160:Src/main.c **** SPI_InitStruct.BitOrder = LL_SPI_MSB_FIRST; 3611 .loc 1 1160 3 is_stmt 1 view .LVU1159 1160:Src/main.c **** SPI_InitStruct.BitOrder = LL_SPI_MSB_FIRST; 3612 .loc 1 1160 27 is_stmt 0 view .LVU1160 3613 00b0 1023 movs r3, #16 3614 00b2 0E93 str r3, [sp, #56] 1161:Src/main.c **** SPI_InitStruct.CRCCalculation = LL_SPI_CRCCALCULATION_DISABLE; 3615 .loc 1 1161 3 is_stmt 1 view .LVU1161 1161:Src/main.c **** SPI_InitStruct.CRCCalculation = LL_SPI_CRCCALCULATION_DISABLE; 3616 .loc 1 1161 27 is_stmt 0 view .LVU1162 3617 00b4 0F94 str r4, [sp, #60] 1162:Src/main.c **** SPI_InitStruct.CRCPoly = 7; 3618 .loc 1 1162 3 is_stmt 1 view .LVU1163 1162:Src/main.c **** SPI_InitStruct.CRCPoly = 7; 3619 .loc 1 1162 33 is_stmt 0 view .LVU1164 3620 00b6 1094 str r4, [sp, #64] 1163:Src/main.c **** LL_SPI_Init(SPI2, &SPI_InitStruct); 3621 .loc 1 1163 3 is_stmt 1 view .LVU1165 1163:Src/main.c **** LL_SPI_Init(SPI2, &SPI_InitStruct); 3622 .loc 1 1163 26 is_stmt 0 view .LVU1166 3623 00b8 0723 movs r3, #7 3624 00ba 1193 str r3, [sp, #68] 1164:Src/main.c **** LL_SPI_SetStandard(SPI2, LL_SPI_PROTOCOL_MOTOROLA); 3625 .loc 1 1164 3 is_stmt 1 view .LVU1167 3626 00bc 094C ldr r4, .L187+8 3627 00be 08A9 add r1, sp, #32 3628 00c0 2046 mov r0, r4 3629 00c2 FFF7FEFF bl LL_SPI_Init 3630 .LVL340: 1165:Src/main.c **** LL_SPI_DisableNSSPulseMgt(SPI2); 3631 .loc 1 1165 3 view .LVU1168 3632 .LBB435: 3633 .LBI435: 426:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 3634 .loc 4 426 22 view .LVU1169 3635 .LBB436: 428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 3636 .loc 4 428 3 view .LVU1170 3637 00c6 6368 ldr r3, [r4, #4] 3638 00c8 23F01003 bic r3, r3, #16 3639 00cc 6360 str r3, [r4, #4] 3640 .LVL341: 428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 3641 .loc 4 428 3 is_stmt 0 view .LVU1171 3642 .LBE436: 3643 .LBE435: 1166:Src/main.c **** /* USER CODE BEGIN SPI2_Init 2 */ 3644 .loc 1 1166 3 is_stmt 1 view .LVU1172 3645 .LBB437: 3646 .LBI437: 874:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 3647 .loc 4 874 22 view .LVU1173 ARM GAS /tmp/ccYgfTud.s page 223 3648 .LBB438: 876:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 3649 .loc 4 876 3 view .LVU1174 3650 00ce 6368 ldr r3, [r4, #4] 3651 00d0 23F00803 bic r3, r3, #8 3652 00d4 6360 str r3, [r4, #4] 3653 .LVL342: 876:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 3654 .loc 4 876 3 is_stmt 0 view .LVU1175 3655 .LBE438: 3656 .LBE437: 1171:Src/main.c **** 3657 .loc 1 1171 1 view .LVU1176 3658 00d6 12B0 add sp, sp, #72 3659 .LCFI34: 3660 .cfi_def_cfa_offset 24 3661 @ sp needed 3662 00d8 BDE8F081 pop {r4, r5, r6, r7, r8, pc} 3663 .L188: 3664 .align 2 3665 .L187: 3666 00dc 00380240 .word 1073887232 3667 00e0 00040240 .word 1073873920 3668 00e4 00380040 .word 1073756160 3669 .cfi_endproc 3670 .LFE1191: 3672 .section .text.MX_SPI5_Init,"ax",%progbits 3673 .align 1 3674 .syntax unified 3675 .thumb 3676 .thumb_func 3678 MX_SPI5_Init: 3679 .LFB1193: 1242:Src/main.c **** 3680 .loc 1 1242 1 is_stmt 1 view -0 3681 .cfi_startproc 3682 @ args = 0, pretend = 0, frame = 72 3683 @ frame_needed = 0, uses_anonymous_args = 0 3684 0000 2DE9F041 push {r4, r5, r6, r7, r8, lr} 3685 .LCFI35: 3686 .cfi_def_cfa_offset 24 3687 .cfi_offset 4, -24 3688 .cfi_offset 5, -20 3689 .cfi_offset 6, -16 3690 .cfi_offset 7, -12 3691 .cfi_offset 8, -8 3692 .cfi_offset 14, -4 3693 0004 92B0 sub sp, sp, #72 3694 .LCFI36: 3695 .cfi_def_cfa_offset 96 1248:Src/main.c **** 3696 .loc 1 1248 3 view .LVU1178 1248:Src/main.c **** 3697 .loc 1 1248 22 is_stmt 0 view .LVU1179 3698 0006 2822 movs r2, #40 3699 0008 0021 movs r1, #0 3700 000a 08A8 add r0, sp, #32 ARM GAS /tmp/ccYgfTud.s page 224 3701 000c FFF7FEFF bl memset 3702 .LVL343: 1250:Src/main.c **** 3703 .loc 1 1250 3 is_stmt 1 view .LVU1180 1250:Src/main.c **** 3704 .loc 1 1250 23 is_stmt 0 view .LVU1181 3705 0010 0024 movs r4, #0 3706 0012 0294 str r4, [sp, #8] 3707 0014 0394 str r4, [sp, #12] 3708 0016 0494 str r4, [sp, #16] 3709 0018 0594 str r4, [sp, #20] 3710 001a 0694 str r4, [sp, #24] 3711 001c 0794 str r4, [sp, #28] 1253:Src/main.c **** 3712 .loc 1 1253 3 is_stmt 1 view .LVU1182 3713 .LVL344: 3714 .LBB439: 3715 .LBI439: 1587:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { 3716 .loc 3 1587 22 view .LVU1183 3717 .LBB440: 1589:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** SET_BIT(RCC->APB2ENR, Periphs); 3718 .loc 3 1589 3 view .LVU1184 1590:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Delay after an RCC peripheral clock enabling */ 3719 .loc 3 1590 3 view .LVU1185 3720 001e 294B ldr r3, .L191 3721 0020 5A6C ldr r2, [r3, #68] 3722 0022 42F48012 orr r2, r2, #1048576 3723 0026 5A64 str r2, [r3, #68] 1592:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; 3724 .loc 3 1592 3 view .LVU1186 1592:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; 3725 .loc 3 1592 12 is_stmt 0 view .LVU1187 3726 0028 5A6C ldr r2, [r3, #68] 3727 002a 02F48012 and r2, r2, #1048576 1592:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; 3728 .loc 3 1592 10 view .LVU1188 3729 002e 0192 str r2, [sp, #4] 3730 .loc 3 1593 3 is_stmt 1 view .LVU1189 3731 0030 019A ldr r2, [sp, #4] 3732 .LVL345: 3733 .loc 3 1593 3 is_stmt 0 view .LVU1190 3734 .LBE440: 3735 .LBE439: 1255:Src/main.c **** /**SPI5 GPIO Configuration 3736 .loc 1 1255 3 is_stmt 1 view .LVU1191 3737 .LBB441: 3738 .LBI441: 309:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { 3739 .loc 3 309 22 view .LVU1192 3740 .LBB442: 311:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** SET_BIT(RCC->AHB1ENR, Periphs); 3741 .loc 3 311 3 view .LVU1193 312:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Delay after an RCC peripheral clock enabling */ 3742 .loc 3 312 3 view .LVU1194 3743 0032 1A6B ldr r2, [r3, #48] 3744 0034 42F02002 orr r2, r2, #32 ARM GAS /tmp/ccYgfTud.s page 225 3745 0038 1A63 str r2, [r3, #48] 314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; 3746 .loc 3 314 3 view .LVU1195 314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; 3747 .loc 3 314 12 is_stmt 0 view .LVU1196 3748 003a 1B6B ldr r3, [r3, #48] 3749 003c 03F02003 and r3, r3, #32 314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; 3750 .loc 3 314 10 view .LVU1197 3751 0040 0093 str r3, [sp] 315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } 3752 .loc 3 315 3 is_stmt 1 view .LVU1198 3753 0042 009B ldr r3, [sp] 3754 .LVL346: 315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } 3755 .loc 3 315 3 is_stmt 0 view .LVU1199 3756 .LBE442: 3757 .LBE441: 1260:Src/main.c **** GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE; 3758 .loc 1 1260 3 is_stmt 1 view .LVU1200 1260:Src/main.c **** GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE; 3759 .loc 1 1260 23 is_stmt 0 view .LVU1201 3760 0044 8023 movs r3, #128 3761 0046 0293 str r3, [sp, #8] 1261:Src/main.c **** GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH; 3762 .loc 1 1261 3 is_stmt 1 view .LVU1202 1261:Src/main.c **** GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH; 3763 .loc 1 1261 24 is_stmt 0 view .LVU1203 3764 0048 0225 movs r5, #2 3765 004a 0395 str r5, [sp, #12] 1262:Src/main.c **** GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; 3766 .loc 1 1262 3 is_stmt 1 view .LVU1204 1262:Src/main.c **** GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; 3767 .loc 1 1262 25 is_stmt 0 view .LVU1205 3768 004c 4FF00308 mov r8, #3 3769 0050 CDF81080 str r8, [sp, #16] 1263:Src/main.c **** GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; 3770 .loc 1 1263 3 is_stmt 1 view .LVU1206 1264:Src/main.c **** GPIO_InitStruct.Alternate = LL_GPIO_AF_5; 3771 .loc 1 1264 3 view .LVU1207 1265:Src/main.c **** LL_GPIO_Init(GPIOF, &GPIO_InitStruct); 3772 .loc 1 1265 3 view .LVU1208 1265:Src/main.c **** LL_GPIO_Init(GPIOF, &GPIO_InitStruct); 3773 .loc 1 1265 29 is_stmt 0 view .LVU1209 3774 0054 0527 movs r7, #5 3775 0056 0797 str r7, [sp, #28] 1266:Src/main.c **** 3776 .loc 1 1266 3 is_stmt 1 view .LVU1210 3777 0058 1B4E ldr r6, .L191+4 3778 005a 02A9 add r1, sp, #8 3779 005c 3046 mov r0, r6 3780 005e FFF7FEFF bl LL_GPIO_Init 3781 .LVL347: 1268:Src/main.c **** GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE; 3782 .loc 1 1268 3 view .LVU1211 1268:Src/main.c **** GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE; 3783 .loc 1 1268 23 is_stmt 0 view .LVU1212 ARM GAS /tmp/ccYgfTud.s page 226 3784 0062 4FF48073 mov r3, #256 3785 0066 0293 str r3, [sp, #8] 1269:Src/main.c **** GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH; 3786 .loc 1 1269 3 is_stmt 1 view .LVU1213 1269:Src/main.c **** GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH; 3787 .loc 1 1269 24 is_stmt 0 view .LVU1214 3788 0068 0395 str r5, [sp, #12] 1270:Src/main.c **** GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; 3789 .loc 1 1270 3 is_stmt 1 view .LVU1215 1270:Src/main.c **** GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; 3790 .loc 1 1270 25 is_stmt 0 view .LVU1216 3791 006a CDF81080 str r8, [sp, #16] 1271:Src/main.c **** GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; 3792 .loc 1 1271 3 is_stmt 1 view .LVU1217 1271:Src/main.c **** GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; 3793 .loc 1 1271 30 is_stmt 0 view .LVU1218 3794 006e 0594 str r4, [sp, #20] 1272:Src/main.c **** GPIO_InitStruct.Alternate = LL_GPIO_AF_5; 3795 .loc 1 1272 3 is_stmt 1 view .LVU1219 1272:Src/main.c **** GPIO_InitStruct.Alternate = LL_GPIO_AF_5; 3796 .loc 1 1272 24 is_stmt 0 view .LVU1220 3797 0070 0694 str r4, [sp, #24] 1273:Src/main.c **** LL_GPIO_Init(GPIOF, &GPIO_InitStruct); 3798 .loc 1 1273 3 is_stmt 1 view .LVU1221 1273:Src/main.c **** LL_GPIO_Init(GPIOF, &GPIO_InitStruct); 3799 .loc 1 1273 29 is_stmt 0 view .LVU1222 3800 0072 0797 str r7, [sp, #28] 1274:Src/main.c **** 3801 .loc 1 1274 3 is_stmt 1 view .LVU1223 3802 0074 02A9 add r1, sp, #8 3803 0076 3046 mov r0, r6 3804 0078 FFF7FEFF bl LL_GPIO_Init 3805 .LVL348: 1280:Src/main.c **** SPI_InitStruct.Mode = LL_SPI_MODE_MASTER; 3806 .loc 1 1280 3 view .LVU1224 1280:Src/main.c **** SPI_InitStruct.Mode = LL_SPI_MODE_MASTER; 3807 .loc 1 1280 36 is_stmt 0 view .LVU1225 3808 007c 4FF48063 mov r3, #1024 3809 0080 0893 str r3, [sp, #32] 1281:Src/main.c **** SPI_InitStruct.DataWidth = LL_SPI_DATAWIDTH_16BIT; 3810 .loc 1 1281 3 is_stmt 1 view .LVU1226 1281:Src/main.c **** SPI_InitStruct.DataWidth = LL_SPI_DATAWIDTH_16BIT; 3811 .loc 1 1281 23 is_stmt 0 view .LVU1227 3812 0082 4FF48273 mov r3, #260 3813 0086 0993 str r3, [sp, #36] 1282:Src/main.c **** SPI_InitStruct.ClockPolarity = LL_SPI_POLARITY_HIGH; 3814 .loc 1 1282 3 is_stmt 1 view .LVU1228 1282:Src/main.c **** SPI_InitStruct.ClockPolarity = LL_SPI_POLARITY_HIGH; 3815 .loc 1 1282 28 is_stmt 0 view .LVU1229 3816 0088 4FF47063 mov r3, #3840 3817 008c 0A93 str r3, [sp, #40] 1283:Src/main.c **** SPI_InitStruct.ClockPhase = LL_SPI_PHASE_1EDGE; 3818 .loc 1 1283 3 is_stmt 1 view .LVU1230 1283:Src/main.c **** SPI_InitStruct.ClockPhase = LL_SPI_PHASE_1EDGE; 3819 .loc 1 1283 32 is_stmt 0 view .LVU1231 3820 008e 0B95 str r5, [sp, #44] 1284:Src/main.c **** SPI_InitStruct.NSS = LL_SPI_NSS_SOFT; ARM GAS /tmp/ccYgfTud.s page 227 3821 .loc 1 1284 3 is_stmt 1 view .LVU1232 1284:Src/main.c **** SPI_InitStruct.NSS = LL_SPI_NSS_SOFT; 3822 .loc 1 1284 29 is_stmt 0 view .LVU1233 3823 0090 0C94 str r4, [sp, #48] 1285:Src/main.c **** SPI_InitStruct.BaudRate = LL_SPI_BAUDRATEPRESCALER_DIV16; 3824 .loc 1 1285 3 is_stmt 1 view .LVU1234 1285:Src/main.c **** SPI_InitStruct.BaudRate = LL_SPI_BAUDRATEPRESCALER_DIV16; 3825 .loc 1 1285 22 is_stmt 0 view .LVU1235 3826 0092 4FF40073 mov r3, #512 3827 0096 0D93 str r3, [sp, #52] 1286:Src/main.c **** SPI_InitStruct.BitOrder = LL_SPI_MSB_FIRST; 3828 .loc 1 1286 3 is_stmt 1 view .LVU1236 1286:Src/main.c **** SPI_InitStruct.BitOrder = LL_SPI_MSB_FIRST; 3829 .loc 1 1286 27 is_stmt 0 view .LVU1237 3830 0098 1823 movs r3, #24 3831 009a 0E93 str r3, [sp, #56] 1287:Src/main.c **** SPI_InitStruct.CRCCalculation = LL_SPI_CRCCALCULATION_DISABLE; 3832 .loc 1 1287 3 is_stmt 1 view .LVU1238 1287:Src/main.c **** SPI_InitStruct.CRCCalculation = LL_SPI_CRCCALCULATION_DISABLE; 3833 .loc 1 1287 27 is_stmt 0 view .LVU1239 3834 009c 0F94 str r4, [sp, #60] 1288:Src/main.c **** SPI_InitStruct.CRCPoly = 7; 3835 .loc 1 1288 3 is_stmt 1 view .LVU1240 1288:Src/main.c **** SPI_InitStruct.CRCPoly = 7; 3836 .loc 1 1288 33 is_stmt 0 view .LVU1241 3837 009e 1094 str r4, [sp, #64] 1289:Src/main.c **** LL_SPI_Init(SPI5, &SPI_InitStruct); 3838 .loc 1 1289 3 is_stmt 1 view .LVU1242 1289:Src/main.c **** LL_SPI_Init(SPI5, &SPI_InitStruct); 3839 .loc 1 1289 26 is_stmt 0 view .LVU1243 3840 00a0 0723 movs r3, #7 3841 00a2 1193 str r3, [sp, #68] 1290:Src/main.c **** LL_SPI_SetStandard(SPI5, LL_SPI_PROTOCOL_MOTOROLA); 3842 .loc 1 1290 3 is_stmt 1 view .LVU1244 3843 00a4 094C ldr r4, .L191+8 3844 00a6 08A9 add r1, sp, #32 3845 00a8 2046 mov r0, r4 3846 00aa FFF7FEFF bl LL_SPI_Init 3847 .LVL349: 1291:Src/main.c **** LL_SPI_DisableNSSPulseMgt(SPI5); 3848 .loc 1 1291 3 view .LVU1245 3849 .LBB443: 3850 .LBI443: 426:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 3851 .loc 4 426 22 view .LVU1246 3852 .LBB444: 428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 3853 .loc 4 428 3 view .LVU1247 3854 00ae 6368 ldr r3, [r4, #4] 3855 00b0 23F01003 bic r3, r3, #16 3856 00b4 6360 str r3, [r4, #4] 3857 .LVL350: 428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 3858 .loc 4 428 3 is_stmt 0 view .LVU1248 3859 .LBE444: 3860 .LBE443: 1292:Src/main.c **** /* USER CODE BEGIN SPI5_Init 2 */ ARM GAS /tmp/ccYgfTud.s page 228 3861 .loc 1 1292 3 is_stmt 1 view .LVU1249 3862 .LBB445: 3863 .LBI445: 874:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 3864 .loc 4 874 22 view .LVU1250 3865 .LBB446: 876:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 3866 .loc 4 876 3 view .LVU1251 3867 00b6 6368 ldr r3, [r4, #4] 3868 00b8 23F00803 bic r3, r3, #8 3869 00bc 6360 str r3, [r4, #4] 3870 .LVL351: 876:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 3871 .loc 4 876 3 is_stmt 0 view .LVU1252 3872 .LBE446: 3873 .LBE445: 1297:Src/main.c **** 3874 .loc 1 1297 1 view .LVU1253 3875 00be 12B0 add sp, sp, #72 3876 .LCFI37: 3877 .cfi_def_cfa_offset 24 3878 @ sp needed 3879 00c0 BDE8F081 pop {r4, r5, r6, r7, r8, pc} 3880 .L192: 3881 .align 2 3882 .L191: 3883 00c4 00380240 .word 1073887232 3884 00c8 00140240 .word 1073878016 3885 00cc 00500140 .word 1073827840 3886 .cfi_endproc 3887 .LFE1193: 3889 .section .text.MX_SPI6_Init,"ax",%progbits 3890 .align 1 3891 .syntax unified 3892 .thumb 3893 .thumb_func 3895 MX_SPI6_Init: 3896 .LFB1194: 1305:Src/main.c **** 3897 .loc 1 1305 1 is_stmt 1 view -0 3898 .cfi_startproc 3899 @ args = 0, pretend = 0, frame = 72 3900 @ frame_needed = 0, uses_anonymous_args = 0 3901 0000 2DE9F041 push {r4, r5, r6, r7, r8, lr} 3902 .LCFI38: 3903 .cfi_def_cfa_offset 24 3904 .cfi_offset 4, -24 3905 .cfi_offset 5, -20 3906 .cfi_offset 6, -16 3907 .cfi_offset 7, -12 3908 .cfi_offset 8, -8 3909 .cfi_offset 14, -4 3910 0004 92B0 sub sp, sp, #72 3911 .LCFI39: 3912 .cfi_def_cfa_offset 96 1311:Src/main.c **** 3913 .loc 1 1311 3 view .LVU1255 ARM GAS /tmp/ccYgfTud.s page 229 1311:Src/main.c **** 3914 .loc 1 1311 22 is_stmt 0 view .LVU1256 3915 0006 2822 movs r2, #40 3916 0008 0021 movs r1, #0 3917 000a 08A8 add r0, sp, #32 3918 000c FFF7FEFF bl memset 3919 .LVL352: 1313:Src/main.c **** 3920 .loc 1 1313 3 is_stmt 1 view .LVU1257 1313:Src/main.c **** 3921 .loc 1 1313 23 is_stmt 0 view .LVU1258 3922 0010 0024 movs r4, #0 3923 0012 0294 str r4, [sp, #8] 3924 0014 0394 str r4, [sp, #12] 3925 0016 0494 str r4, [sp, #16] 3926 0018 0594 str r4, [sp, #20] 3927 001a 0694 str r4, [sp, #24] 3928 001c 0794 str r4, [sp, #28] 1316:Src/main.c **** 3929 .loc 1 1316 3 is_stmt 1 view .LVU1259 3930 .LVL353: 3931 .LBB447: 3932 .LBI447: 1587:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { 3933 .loc 3 1587 22 view .LVU1260 3934 .LBB448: 1589:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** SET_BIT(RCC->APB2ENR, Periphs); 3935 .loc 3 1589 3 view .LVU1261 1590:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Delay after an RCC peripheral clock enabling */ 3936 .loc 3 1590 3 view .LVU1262 3937 001e 294B ldr r3, .L195 3938 0020 5A6C ldr r2, [r3, #68] 3939 0022 42F40012 orr r2, r2, #2097152 3940 0026 5A64 str r2, [r3, #68] 1592:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; 3941 .loc 3 1592 3 view .LVU1263 1592:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; 3942 .loc 3 1592 12 is_stmt 0 view .LVU1264 3943 0028 5A6C ldr r2, [r3, #68] 3944 002a 02F40012 and r2, r2, #2097152 1592:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; 3945 .loc 3 1592 10 view .LVU1265 3946 002e 0192 str r2, [sp, #4] 3947 .loc 3 1593 3 is_stmt 1 view .LVU1266 3948 0030 019A ldr r2, [sp, #4] 3949 .LVL354: 3950 .loc 3 1593 3 is_stmt 0 view .LVU1267 3951 .LBE448: 3952 .LBE447: 1318:Src/main.c **** /**SPI6 GPIO Configuration 3953 .loc 1 1318 3 is_stmt 1 view .LVU1268 3954 .LBB449: 3955 .LBI449: 309:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { 3956 .loc 3 309 22 view .LVU1269 3957 .LBB450: 311:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** SET_BIT(RCC->AHB1ENR, Periphs); ARM GAS /tmp/ccYgfTud.s page 230 3958 .loc 3 311 3 view .LVU1270 312:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Delay after an RCC peripheral clock enabling */ 3959 .loc 3 312 3 view .LVU1271 3960 0032 1A6B ldr r2, [r3, #48] 3961 0034 42F00102 orr r2, r2, #1 3962 0038 1A63 str r2, [r3, #48] 314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; 3963 .loc 3 314 3 view .LVU1272 314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; 3964 .loc 3 314 12 is_stmt 0 view .LVU1273 3965 003a 1B6B ldr r3, [r3, #48] 3966 003c 03F00103 and r3, r3, #1 314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; 3967 .loc 3 314 10 view .LVU1274 3968 0040 0093 str r3, [sp] 315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } 3969 .loc 3 315 3 is_stmt 1 view .LVU1275 3970 0042 009B ldr r3, [sp] 3971 .LVL355: 315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } 3972 .loc 3 315 3 is_stmt 0 view .LVU1276 3973 .LBE450: 3974 .LBE449: 1323:Src/main.c **** GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE; 3975 .loc 1 1323 3 is_stmt 1 view .LVU1277 1323:Src/main.c **** GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE; 3976 .loc 1 1323 23 is_stmt 0 view .LVU1278 3977 0044 2023 movs r3, #32 3978 0046 0293 str r3, [sp, #8] 1324:Src/main.c **** GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH; 3979 .loc 1 1324 3 is_stmt 1 view .LVU1279 1324:Src/main.c **** GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH; 3980 .loc 1 1324 24 is_stmt 0 view .LVU1280 3981 0048 0225 movs r5, #2 3982 004a 0395 str r5, [sp, #12] 1325:Src/main.c **** GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; 3983 .loc 1 1325 3 is_stmt 1 view .LVU1281 1325:Src/main.c **** GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; 3984 .loc 1 1325 25 is_stmt 0 view .LVU1282 3985 004c 4FF00308 mov r8, #3 3986 0050 CDF81080 str r8, [sp, #16] 1326:Src/main.c **** GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; 3987 .loc 1 1326 3 is_stmt 1 view .LVU1283 1327:Src/main.c **** GPIO_InitStruct.Alternate = LL_GPIO_AF_8; 3988 .loc 1 1327 3 view .LVU1284 1328:Src/main.c **** LL_GPIO_Init(GPIOA, &GPIO_InitStruct); 3989 .loc 1 1328 3 view .LVU1285 1328:Src/main.c **** LL_GPIO_Init(GPIOA, &GPIO_InitStruct); 3990 .loc 1 1328 29 is_stmt 0 view .LVU1286 3991 0054 0827 movs r7, #8 3992 0056 0797 str r7, [sp, #28] 1329:Src/main.c **** 3993 .loc 1 1329 3 is_stmt 1 view .LVU1287 3994 0058 1B4E ldr r6, .L195+4 3995 005a 0DEB0701 add r1, sp, r7 3996 005e 3046 mov r0, r6 3997 0060 FFF7FEFF bl LL_GPIO_Init ARM GAS /tmp/ccYgfTud.s page 231 3998 .LVL356: 1331:Src/main.c **** GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE; 3999 .loc 1 1331 3 view .LVU1288 1331:Src/main.c **** GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE; 4000 .loc 1 1331 23 is_stmt 0 view .LVU1289 4001 0064 8023 movs r3, #128 4002 0066 0293 str r3, [sp, #8] 1332:Src/main.c **** GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH; 4003 .loc 1 1332 3 is_stmt 1 view .LVU1290 1332:Src/main.c **** GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH; 4004 .loc 1 1332 24 is_stmt 0 view .LVU1291 4005 0068 0395 str r5, [sp, #12] 1333:Src/main.c **** GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; 4006 .loc 1 1333 3 is_stmt 1 view .LVU1292 1333:Src/main.c **** GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; 4007 .loc 1 1333 25 is_stmt 0 view .LVU1293 4008 006a CDF81080 str r8, [sp, #16] 1334:Src/main.c **** GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; 4009 .loc 1 1334 3 is_stmt 1 view .LVU1294 1334:Src/main.c **** GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; 4010 .loc 1 1334 30 is_stmt 0 view .LVU1295 4011 006e 0594 str r4, [sp, #20] 1335:Src/main.c **** GPIO_InitStruct.Alternate = LL_GPIO_AF_8; 4012 .loc 1 1335 3 is_stmt 1 view .LVU1296 1335:Src/main.c **** GPIO_InitStruct.Alternate = LL_GPIO_AF_8; 4013 .loc 1 1335 24 is_stmt 0 view .LVU1297 4014 0070 0694 str r4, [sp, #24] 1336:Src/main.c **** LL_GPIO_Init(GPIOA, &GPIO_InitStruct); 4015 .loc 1 1336 3 is_stmt 1 view .LVU1298 1336:Src/main.c **** LL_GPIO_Init(GPIOA, &GPIO_InitStruct); 4016 .loc 1 1336 29 is_stmt 0 view .LVU1299 4017 0072 0797 str r7, [sp, #28] 1337:Src/main.c **** 4018 .loc 1 1337 3 is_stmt 1 view .LVU1300 4019 0074 0DEB0701 add r1, sp, r7 4020 0078 3046 mov r0, r6 4021 007a FFF7FEFF bl LL_GPIO_Init 4022 .LVL357: 1343:Src/main.c **** SPI_InitStruct.Mode = LL_SPI_MODE_MASTER; 4023 .loc 1 1343 3 view .LVU1301 1343:Src/main.c **** SPI_InitStruct.Mode = LL_SPI_MODE_MASTER; 4024 .loc 1 1343 36 is_stmt 0 view .LVU1302 4025 007e 0894 str r4, [sp, #32] 1344:Src/main.c **** SPI_InitStruct.DataWidth = LL_SPI_DATAWIDTH_16BIT; 4026 .loc 1 1344 3 is_stmt 1 view .LVU1303 1344:Src/main.c **** SPI_InitStruct.DataWidth = LL_SPI_DATAWIDTH_16BIT; 4027 .loc 1 1344 23 is_stmt 0 view .LVU1304 4028 0080 4FF48273 mov r3, #260 4029 0084 0993 str r3, [sp, #36] 1345:Src/main.c **** SPI_InitStruct.ClockPolarity = LL_SPI_POLARITY_HIGH; 4030 .loc 1 1345 3 is_stmt 1 view .LVU1305 1345:Src/main.c **** SPI_InitStruct.ClockPolarity = LL_SPI_POLARITY_HIGH; 4031 .loc 1 1345 28 is_stmt 0 view .LVU1306 4032 0086 4FF47063 mov r3, #3840 4033 008a 0A93 str r3, [sp, #40] 1346:Src/main.c **** SPI_InitStruct.ClockPhase = LL_SPI_PHASE_2EDGE; 4034 .loc 1 1346 3 is_stmt 1 view .LVU1307 ARM GAS /tmp/ccYgfTud.s page 232 1346:Src/main.c **** SPI_InitStruct.ClockPhase = LL_SPI_PHASE_2EDGE; 4035 .loc 1 1346 32 is_stmt 0 view .LVU1308 4036 008c 0B95 str r5, [sp, #44] 1347:Src/main.c **** SPI_InitStruct.NSS = LL_SPI_NSS_SOFT; 4037 .loc 1 1347 3 is_stmt 1 view .LVU1309 1347:Src/main.c **** SPI_InitStruct.NSS = LL_SPI_NSS_SOFT; 4038 .loc 1 1347 29 is_stmt 0 view .LVU1310 4039 008e 0123 movs r3, #1 4040 0090 0C93 str r3, [sp, #48] 1348:Src/main.c **** SPI_InitStruct.BaudRate = LL_SPI_BAUDRATEPRESCALER_DIV16; 4041 .loc 1 1348 3 is_stmt 1 view .LVU1311 1348:Src/main.c **** SPI_InitStruct.BaudRate = LL_SPI_BAUDRATEPRESCALER_DIV16; 4042 .loc 1 1348 22 is_stmt 0 view .LVU1312 4043 0092 4FF40073 mov r3, #512 4044 0096 0D93 str r3, [sp, #52] 1349:Src/main.c **** SPI_InitStruct.BitOrder = LL_SPI_MSB_FIRST; 4045 .loc 1 1349 3 is_stmt 1 view .LVU1313 1349:Src/main.c **** SPI_InitStruct.BitOrder = LL_SPI_MSB_FIRST; 4046 .loc 1 1349 27 is_stmt 0 view .LVU1314 4047 0098 1823 movs r3, #24 4048 009a 0E93 str r3, [sp, #56] 1350:Src/main.c **** SPI_InitStruct.CRCCalculation = LL_SPI_CRCCALCULATION_DISABLE; 4049 .loc 1 1350 3 is_stmt 1 view .LVU1315 1350:Src/main.c **** SPI_InitStruct.CRCCalculation = LL_SPI_CRCCALCULATION_DISABLE; 4050 .loc 1 1350 27 is_stmt 0 view .LVU1316 4051 009c 0F94 str r4, [sp, #60] 1351:Src/main.c **** SPI_InitStruct.CRCPoly = 7; 4052 .loc 1 1351 3 is_stmt 1 view .LVU1317 1351:Src/main.c **** SPI_InitStruct.CRCPoly = 7; 4053 .loc 1 1351 33 is_stmt 0 view .LVU1318 4054 009e 1094 str r4, [sp, #64] 1352:Src/main.c **** LL_SPI_Init(SPI6, &SPI_InitStruct); 4055 .loc 1 1352 3 is_stmt 1 view .LVU1319 1352:Src/main.c **** LL_SPI_Init(SPI6, &SPI_InitStruct); 4056 .loc 1 1352 26 is_stmt 0 view .LVU1320 4057 00a0 0723 movs r3, #7 4058 00a2 1193 str r3, [sp, #68] 1353:Src/main.c **** LL_SPI_SetStandard(SPI6, LL_SPI_PROTOCOL_MOTOROLA); 4059 .loc 1 1353 3 is_stmt 1 view .LVU1321 4060 00a4 094C ldr r4, .L195+8 4061 00a6 08A9 add r1, sp, #32 4062 00a8 2046 mov r0, r4 4063 00aa FFF7FEFF bl LL_SPI_Init 4064 .LVL358: 1354:Src/main.c **** LL_SPI_DisableNSSPulseMgt(SPI6); 4065 .loc 1 1354 3 view .LVU1322 4066 .LBB451: 4067 .LBI451: 426:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 4068 .loc 4 426 22 view .LVU1323 4069 .LBB452: 428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 4070 .loc 4 428 3 view .LVU1324 4071 00ae 6368 ldr r3, [r4, #4] 4072 00b0 23F01003 bic r3, r3, #16 4073 00b4 6360 str r3, [r4, #4] 4074 .LVL359: ARM GAS /tmp/ccYgfTud.s page 233 428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 4075 .loc 4 428 3 is_stmt 0 view .LVU1325 4076 .LBE452: 4077 .LBE451: 1355:Src/main.c **** /* USER CODE BEGIN SPI6_Init 2 */ 4078 .loc 1 1355 3 is_stmt 1 view .LVU1326 4079 .LBB453: 4080 .LBI453: 874:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 4081 .loc 4 874 22 view .LVU1327 4082 .LBB454: 876:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 4083 .loc 4 876 3 view .LVU1328 4084 00b6 6368 ldr r3, [r4, #4] 4085 00b8 23F00803 bic r3, r3, #8 4086 00bc 6360 str r3, [r4, #4] 4087 .LVL360: 876:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 4088 .loc 4 876 3 is_stmt 0 view .LVU1329 4089 .LBE454: 4090 .LBE453: 1360:Src/main.c **** 4091 .loc 1 1360 1 view .LVU1330 4092 00be 12B0 add sp, sp, #72 4093 .LCFI40: 4094 .cfi_def_cfa_offset 24 4095 @ sp needed 4096 00c0 BDE8F081 pop {r4, r5, r6, r7, r8, pc} 4097 .L196: 4098 .align 2 4099 .L195: 4100 00c4 00380240 .word 1073887232 4101 00c8 00000240 .word 1073872896 4102 00cc 00540140 .word 1073828864 4103 .cfi_endproc 4104 .LFE1194: 4106 .section .text.MX_TIM2_Init,"ax",%progbits 4107 .align 1 4108 .syntax unified 4109 .thumb 4110 .thumb_func 4112 MX_TIM2_Init: 4113 .LFB1195: 1368:Src/main.c **** 4114 .loc 1 1368 1 is_stmt 1 view -0 4115 .cfi_startproc 4116 @ args = 0, pretend = 0, frame = 24 4117 @ frame_needed = 0, uses_anonymous_args = 0 4118 0000 10B5 push {r4, lr} 4119 .LCFI41: 4120 .cfi_def_cfa_offset 8 4121 .cfi_offset 4, -8 4122 .cfi_offset 14, -4 4123 0002 86B0 sub sp, sp, #24 4124 .LCFI42: 4125 .cfi_def_cfa_offset 32 1374:Src/main.c **** ARM GAS /tmp/ccYgfTud.s page 234 4126 .loc 1 1374 3 view .LVU1332 1374:Src/main.c **** 4127 .loc 1 1374 22 is_stmt 0 view .LVU1333 4128 0004 0024 movs r4, #0 4129 0006 0194 str r4, [sp, #4] 4130 0008 0294 str r4, [sp, #8] 4131 000a 0394 str r4, [sp, #12] 4132 000c 0494 str r4, [sp, #16] 4133 000e 0594 str r4, [sp, #20] 1377:Src/main.c **** 4134 .loc 1 1377 3 is_stmt 1 view .LVU1334 4135 .LVL361: 4136 .LBB455: 4137 .LBI455: 1071:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { 4138 .loc 3 1071 22 view .LVU1335 4139 .LBB456: 1073:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** SET_BIT(RCC->APB1ENR, Periphs); 4140 .loc 3 1073 3 view .LVU1336 1074:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Delay after an RCC peripheral clock enabling */ 4141 .loc 3 1074 3 view .LVU1337 4142 0010 1D4B ldr r3, .L199 4143 0012 1A6C ldr r2, [r3, #64] 4144 0014 42F00102 orr r2, r2, #1 4145 0018 1A64 str r2, [r3, #64] 1076:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; 4146 .loc 3 1076 3 view .LVU1338 1076:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; 4147 .loc 3 1076 12 is_stmt 0 view .LVU1339 4148 001a 1B6C ldr r3, [r3, #64] 4149 001c 03F00103 and r3, r3, #1 1076:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; 4150 .loc 3 1076 10 view .LVU1340 4151 0020 0093 str r3, [sp] 1077:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } 4152 .loc 3 1077 3 is_stmt 1 view .LVU1341 4153 0022 009B ldr r3, [sp] 4154 .LVL362: 1077:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } 4155 .loc 3 1077 3 is_stmt 0 view .LVU1342 4156 .LBE456: 4157 .LBE455: 1380:Src/main.c **** NVIC_EnableIRQ(TIM2_IRQn); 4158 .loc 1 1380 3 is_stmt 1 view .LVU1343 4159 .LBB457: 4160 .LBI457: 1884:Drivers/CMSIS/Include/core_cm7.h **** { 4161 .loc 2 1884 26 view .LVU1344 4162 .LBB458: 1886:Drivers/CMSIS/Include/core_cm7.h **** } 4163 .loc 2 1886 3 view .LVU1345 1886:Drivers/CMSIS/Include/core_cm7.h **** } 4164 .loc 2 1886 26 is_stmt 0 view .LVU1346 4165 0024 194B ldr r3, .L199+4 4166 0026 D868 ldr r0, [r3, #12] 4167 .LBE458: 4168 .LBE457: ARM GAS /tmp/ccYgfTud.s page 235 1380:Src/main.c **** NVIC_EnableIRQ(TIM2_IRQn); 4169 .loc 1 1380 3 discriminator 1 view .LVU1347 4170 0028 2246 mov r2, r4 4171 002a 2146 mov r1, r4 4172 002c C0F30220 ubfx r0, r0, #8, #3 4173 0030 FFF7FEFF bl NVIC_EncodePriority 4174 .LVL363: 4175 .LBB459: 4176 .LBI459: 2024:Drivers/CMSIS/Include/core_cm7.h **** { 4177 .loc 2 2024 22 is_stmt 1 view .LVU1348 4178 .LBB460: 2026:Drivers/CMSIS/Include/core_cm7.h **** { 4179 .loc 2 2026 3 view .LVU1349 2028:Drivers/CMSIS/Include/core_cm7.h **** } 4180 .loc 2 2028 5 view .LVU1350 2028:Drivers/CMSIS/Include/core_cm7.h **** } 4181 .loc 2 2028 49 is_stmt 0 view .LVU1351 4182 0034 0001 lsls r0, r0, #4 4183 .LVL364: 2028:Drivers/CMSIS/Include/core_cm7.h **** } 4184 .loc 2 2028 49 view .LVU1352 4185 0036 C0B2 uxtb r0, r0 2028:Drivers/CMSIS/Include/core_cm7.h **** } 4186 .loc 2 2028 47 view .LVU1353 4187 0038 154B ldr r3, .L199+8 4188 003a 83F81C03 strb r0, [r3, #796] 4189 .LVL365: 2028:Drivers/CMSIS/Include/core_cm7.h **** } 4190 .loc 2 2028 47 view .LVU1354 4191 .LBE460: 4192 .LBE459: 1381:Src/main.c **** 4193 .loc 1 1381 3 is_stmt 1 view .LVU1355 4194 .LBB461: 4195 .LBI461: 1896:Drivers/CMSIS/Include/core_cm7.h **** { 4196 .loc 2 1896 22 view .LVU1356 4197 .LBB462: 1898:Drivers/CMSIS/Include/core_cm7.h **** { 4198 .loc 2 1898 3 view .LVU1357 1900:Drivers/CMSIS/Include/core_cm7.h **** } 4199 .loc 2 1900 5 view .LVU1358 1900:Drivers/CMSIS/Include/core_cm7.h **** } 4200 .loc 2 1900 43 is_stmt 0 view .LVU1359 4201 003e 4FF08052 mov r2, #268435456 4202 0042 1A60 str r2, [r3] 4203 .LVL366: 1900:Drivers/CMSIS/Include/core_cm7.h **** } 4204 .loc 2 1900 43 view .LVU1360 4205 .LBE462: 4206 .LBE461: 1386:Src/main.c **** TIM_InitStruct.CounterMode = LL_TIM_COUNTERMODE_UP; 4207 .loc 1 1386 3 is_stmt 1 view .LVU1361 1386:Src/main.c **** TIM_InitStruct.CounterMode = LL_TIM_COUNTERMODE_UP; 4208 .loc 1 1386 28 is_stmt 0 view .LVU1362 4209 0044 4FF47A73 mov r3, #1000 ARM GAS /tmp/ccYgfTud.s page 236 4210 0048 ADF80430 strh r3, [sp, #4] @ movhi 1387:Src/main.c **** TIM_InitStruct.Autoreload = 840000; 4211 .loc 1 1387 3 is_stmt 1 view .LVU1363 1387:Src/main.c **** TIM_InitStruct.Autoreload = 840000; 4212 .loc 1 1387 30 is_stmt 0 view .LVU1364 4213 004c 0294 str r4, [sp, #8] 1388:Src/main.c **** TIM_InitStruct.ClockDivision = LL_TIM_CLOCKDIVISION_DIV1; 4214 .loc 1 1388 3 is_stmt 1 view .LVU1365 1388:Src/main.c **** TIM_InitStruct.ClockDivision = LL_TIM_CLOCKDIVISION_DIV1; 4215 .loc 1 1388 29 is_stmt 0 view .LVU1366 4216 004e 114B ldr r3, .L199+12 4217 0050 0393 str r3, [sp, #12] 1389:Src/main.c **** LL_TIM_Init(TIM2, &TIM_InitStruct); 4218 .loc 1 1389 3 is_stmt 1 view .LVU1367 1389:Src/main.c **** LL_TIM_Init(TIM2, &TIM_InitStruct); 4219 .loc 1 1389 32 is_stmt 0 view .LVU1368 4220 0052 0494 str r4, [sp, #16] 1390:Src/main.c **** LL_TIM_DisableARRPreload(TIM2); 4221 .loc 1 1390 3 is_stmt 1 view .LVU1369 4222 0054 01A9 add r1, sp, #4 4223 0056 4FF08040 mov r0, #1073741824 4224 005a FFF7FEFF bl LL_TIM_Init 4225 .LVL367: 1391:Src/main.c **** LL_TIM_SetClockSource(TIM2, LL_TIM_CLOCKSOURCE_INTERNAL); 4226 .loc 1 1391 3 view .LVU1370 4227 .LBB463: 4228 .LBI463: 4229 .file 5 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h" 1:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 2:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** ****************************************************************************** 3:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @file stm32f7xx_ll_tim.h 4:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @author MCD Application Team 5:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Header file of TIM LL module. 6:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** ****************************************************************************** 7:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @attention 8:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * 9:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * Copyright (c) 2017 STMicroelectronics. 10:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * All rights reserved. 11:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * 12:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * This software is licensed under terms that can be found in the LICENSE file 13:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * in the root directory of this software component. 14:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * If no LICENSE file comes with this software, it is provided AS-IS. 15:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * 16:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** ****************************************************************************** 17:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 18:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 19:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /* Define to prevent recursive inclusion -------------------------------------*/ 20:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #ifndef __STM32F7xx_LL_TIM_H 21:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define __STM32F7xx_LL_TIM_H 22:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 23:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #ifdef __cplusplus 24:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** extern "C" { 25:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #endif 26:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 27:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /* Includes ------------------------------------------------------------------*/ 28:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #include "stm32f7xx.h" 29:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** ARM GAS /tmp/ccYgfTud.s page 237 30:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @addtogroup STM32F7xx_LL_Driver 31:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ 32:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 33:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 34:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #if defined (TIM1) || defined (TIM8) || defined (TIM2) || defined (TIM3) || defined (TIM4) || defi 35:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 36:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL TIM 37:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ 38:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 39:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 40:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /* Private types -------------------------------------------------------------*/ 41:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /* Private variables ---------------------------------------------------------*/ 42:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_Private_Variables TIM Private Variables 43:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ 44:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 45:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** static const uint8_t OFFSET_TAB_CCMRx[] = 46:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 47:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 0x00U, /* 0: TIMx_CH1 */ 48:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 0x00U, /* 1: TIMx_CH1N */ 49:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 0x00U, /* 2: TIMx_CH2 */ 50:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 0x00U, /* 3: TIMx_CH2N */ 51:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 0x04U, /* 4: TIMx_CH3 */ 52:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 0x04U, /* 5: TIMx_CH3N */ 53:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 0x04U, /* 6: TIMx_CH4 */ 54:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 0x3CU, /* 7: TIMx_CH5 */ 55:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 0x3CU /* 8: TIMx_CH6 */ 56:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }; 57:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 58:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** static const uint8_t SHIFT_TAB_OCxx[] = 59:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 60:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 0U, /* 0: OC1M, OC1FE, OC1PE */ 61:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 0U, /* 1: - NA */ 62:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 8U, /* 2: OC2M, OC2FE, OC2PE */ 63:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 0U, /* 3: - NA */ 64:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 0U, /* 4: OC3M, OC3FE, OC3PE */ 65:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 0U, /* 5: - NA */ 66:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 8U, /* 6: OC4M, OC4FE, OC4PE */ 67:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 0U, /* 7: OC5M, OC5FE, OC5PE */ 68:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 8U /* 8: OC6M, OC6FE, OC6PE */ 69:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }; 70:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 71:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** static const uint8_t SHIFT_TAB_ICxx[] = 72:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 73:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 0U, /* 0: CC1S, IC1PSC, IC1F */ 74:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 0U, /* 1: - NA */ 75:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 8U, /* 2: CC2S, IC2PSC, IC2F */ 76:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 0U, /* 3: - NA */ 77:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 0U, /* 4: CC3S, IC3PSC, IC3F */ 78:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 0U, /* 5: - NA */ 79:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 8U, /* 6: CC4S, IC4PSC, IC4F */ 80:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 0U, /* 7: - NA */ 81:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 0U /* 8: - NA */ 82:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }; 83:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 84:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** static const uint8_t SHIFT_TAB_CCxP[] = 85:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 86:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 0U, /* 0: CC1P */ ARM GAS /tmp/ccYgfTud.s page 238 87:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 2U, /* 1: CC1NP */ 88:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 4U, /* 2: CC2P */ 89:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 6U, /* 3: CC2NP */ 90:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 8U, /* 4: CC3P */ 91:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 10U, /* 5: CC3NP */ 92:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 12U, /* 6: CC4P */ 93:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 16U, /* 7: CC5P */ 94:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 20U /* 8: CC6P */ 95:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }; 96:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 97:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** static const uint8_t SHIFT_TAB_OISx[] = 98:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 99:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 0U, /* 0: OIS1 */ 100:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1U, /* 1: OIS1N */ 101:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 2U, /* 2: OIS2 */ 102:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3U, /* 3: OIS2N */ 103:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 4U, /* 4: OIS3 */ 104:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 5U, /* 5: OIS3N */ 105:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 6U, /* 6: OIS4 */ 106:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 8U, /* 7: OIS5 */ 107:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 10U /* 8: OIS6 */ 108:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }; 109:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 110:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} 111:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 112:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 113:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /* Private constants ---------------------------------------------------------*/ 114:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_Private_Constants TIM Private Constants 115:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ 116:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 117:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 118:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #if defined(TIM_BREAK_INPUT_SUPPORT) 119:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /* Defines used for the bit position in the register and perform offsets */ 120:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define TIM_POSITION_BRK_SOURCE (POSITION_VAL(Source) & 0x1FUL) 121:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 122:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /* Generic bit definitions for TIMx_AF1 register */ 123:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define TIMx_AF1_BKINP TIM1_AF1_BKINP /*!< BRK BKIN input polarity */ 124:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #endif /* TIM_BREAK_INPUT_SUPPORT */ 125:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 126:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /* Remap mask definitions */ 127:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define TIMx_OR_RMP_SHIFT 16U 128:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define TIMx_OR_RMP_MASK 0x0000FFFFU 129:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define TIM2_OR_RMP_MASK (TIM2_OR_ITR1_RMP << TIMx_OR_RMP_SHIFT) 130:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define TIM5_OR_RMP_MASK (TIM5_OR_TI4_RMP << TIMx_OR_RMP_SHIFT) 131:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define TIM11_OR_RMP_MASK (TIM11_OR_TI1_RMP << TIMx_OR_RMP_SHIFT) 132:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 133:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /* Mask used to set the TDG[x:0] of the DTG bits of the TIMx_BDTR register */ 134:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define DT_DELAY_1 ((uint8_t)0x7F) 135:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define DT_DELAY_2 ((uint8_t)0x3F) 136:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define DT_DELAY_3 ((uint8_t)0x1F) 137:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define DT_DELAY_4 ((uint8_t)0x1F) 138:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 139:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /* Mask used to set the DTG[7:5] bits of the DTG bits of the TIMx_BDTR register */ 140:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define DT_RANGE_1 ((uint8_t)0x00) 141:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define DT_RANGE_2 ((uint8_t)0x80) 142:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define DT_RANGE_3 ((uint8_t)0xC0) 143:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define DT_RANGE_4 ((uint8_t)0xE0) ARM GAS /tmp/ccYgfTud.s page 239 144:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 145:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 146:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 147:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} 148:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 149:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 150:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /* Private macros ------------------------------------------------------------*/ 151:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_Private_Macros TIM Private Macros 152:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ 153:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 154:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @brief Convert channel id into channel index. 155:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param __CHANNEL__ This parameter can be one of the following values: 156:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 157:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1N 158:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 159:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2N 160:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 161:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3N 162:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 163:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH5 164:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH6 165:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval none 166:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 167:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define TIM_GET_CHANNEL_INDEX( __CHANNEL__) \ 168:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** (((__CHANNEL__) == LL_TIM_CHANNEL_CH1) ? 0U :\ 169:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** ((__CHANNEL__) == LL_TIM_CHANNEL_CH1N) ? 1U :\ 170:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** ((__CHANNEL__) == LL_TIM_CHANNEL_CH2) ? 2U :\ 171:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** ((__CHANNEL__) == LL_TIM_CHANNEL_CH2N) ? 3U :\ 172:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** ((__CHANNEL__) == LL_TIM_CHANNEL_CH3) ? 4U :\ 173:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** ((__CHANNEL__) == LL_TIM_CHANNEL_CH3N) ? 5U :\ 174:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** ((__CHANNEL__) == LL_TIM_CHANNEL_CH4) ? 6U :\ 175:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** ((__CHANNEL__) == LL_TIM_CHANNEL_CH5) ? 7U : 8U) 176:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 177:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @brief Calculate the deadtime sampling period(in ps). 178:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param __TIMCLK__ timer input clock frequency (in Hz). 179:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param __CKD__ This parameter can be one of the following values: 180:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CLOCKDIVISION_DIV1 181:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CLOCKDIVISION_DIV2 182:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CLOCKDIVISION_DIV4 183:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval none 184:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 185:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define TIM_CALC_DTS(__TIMCLK__, __CKD__) \ 186:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** (((__CKD__) == LL_TIM_CLOCKDIVISION_DIV1) ? ((uint64_t)1000000000000U/(__TIMCLK__)) : \ 187:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** ((__CKD__) == LL_TIM_CLOCKDIVISION_DIV2) ? ((uint64_t)1000000000000U/((__TIMCLK__) >> 1U)) : \ 188:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** ((uint64_t)1000000000000U/((__TIMCLK__) >> 2U))) 189:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 190:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} 191:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 192:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 193:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 194:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /* Exported types ------------------------------------------------------------*/ 195:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #if defined(USE_FULL_LL_DRIVER) 196:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_ES_INIT TIM Exported Init structure 197:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ 198:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 199:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 200:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** ARM GAS /tmp/ccYgfTud.s page 240 201:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief TIM Time Base configuration structure definition. 202:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 203:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** typedef struct 204:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 205:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint16_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock. 206:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a number between Min_Data=0x0000 and Max_D 207:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 208:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary function 209:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_SetPrescaler().*/ 210:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 211:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t CounterMode; /*!< Specifies the counter mode. 212:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_COUNTERMODE. 213:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 214:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary function 215:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_SetCounterMode().*/ 216:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 217:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t Autoreload; /*!< Specifies the auto reload value to be loaded into the active 218:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** Auto-Reload Register at the next update event. 219:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter must be a number between Min_Data=0x0000 and Max_ 220:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** Some timer instances may support 32 bits counters. In that case 221:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** be a number between 0x0000 and 0xFFFFFFFF. 222:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 223:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary function 224:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_SetAutoReload().*/ 225:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 226:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t ClockDivision; /*!< Specifies the clock division. 227:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_CLOCKDIVISION. 228:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 229:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary function 230:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_SetClockDivision().*/ 231:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 232:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downc 233:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** reaches zero, an update event is generated and counting restarts 234:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** from the RCR value (N). 235:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This means in PWM mode that (N+1) corresponds to: 236:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** - the number of PWM periods in edge-aligned mode 237:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** - the number of half PWM period in center-aligned mode 238:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** GP timers: this parameter must be a number between Min_Data = 0x 239:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** Max_Data = 0xFF. 240:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** Advanced timers: this parameter must be a number between Min_Dat 241:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** Max_Data = 0xFFFF. 242:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 243:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary function 244:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_SetRepetitionCounter().*/ 245:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } LL_TIM_InitTypeDef; 246:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 247:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 248:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief TIM Output Compare configuration structure definition. 249:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 250:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** typedef struct 251:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 252:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t OCMode; /*!< Specifies the output mode. 253:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_OCMODE. 254:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 255:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary function 256:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_OC_SetMode().*/ 257:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** ARM GAS /tmp/ccYgfTud.s page 241 258:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t OCState; /*!< Specifies the TIM Output Compare state. 259:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_OCSTATE. 260:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 261:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary functions 262:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/ 263:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 264:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t OCNState; /*!< Specifies the TIM complementary Output Compare state. 265:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_OCSTATE. 266:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 267:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary functions 268:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/ 269:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 270:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t CompareValue; /*!< Specifies the Compare value to be loaded into the Capture Compare Re 271:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a number between Min_Data=0x0000 and Max_Data= 272:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 273:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary function 274:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** LL_TIM_OC_SetCompareCHx (x=1..6).*/ 275:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 276:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t OCPolarity; /*!< Specifies the output polarity. 277:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY. 278:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 279:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary function 280:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_OC_SetPolarity().*/ 281:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 282:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t OCNPolarity; /*!< Specifies the complementary output polarity. 283:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY. 284:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 285:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary function 286:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_OC_SetPolarity().*/ 287:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 288:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 289:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. 290:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE. 291:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 292:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary function 293:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_OC_SetIdleState().*/ 294:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 295:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. 296:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE. 297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 298:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary function 299:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_OC_SetIdleState().*/ 300:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } LL_TIM_OC_InitTypeDef; 301:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 302:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 303:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief TIM Input Capture configuration structure definition. 304:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 305:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 306:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** typedef struct 307:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 308:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 309:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t ICPolarity; /*!< Specifies the active edge of the input signal. 310:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY. 311:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 312:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary function 313:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_IC_SetPolarity().*/ 314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** ARM GAS /tmp/ccYgfTud.s page 242 315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t ICActiveInput; /*!< Specifies the input. 316:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT. 317:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 318:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary function 319:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_IC_SetActiveInput().*/ 320:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 321:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler. 322:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_ICPSC. 323:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 324:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary function 325:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_IC_SetPrescaler().*/ 326:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 327:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t ICFilter; /*!< Specifies the input capture filter. 328:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_IC_FILTER. 329:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 330:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary function 331:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_IC_SetFilter().*/ 332:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } LL_TIM_IC_InitTypeDef; 333:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 334:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 335:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 336:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief TIM Encoder interface configuration structure definition. 337:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 338:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** typedef struct 339:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 340:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t EncoderMode; /*!< Specifies the encoder resolution (x2 or x4). 341:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_ENCODERMODE. 342:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 343:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary function 344:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_SetEncoderMode().*/ 345:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input. 347:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY. 348:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 349:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary function 350:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_IC_SetPolarity().*/ 351:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 352:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t IC1ActiveInput; /*!< Specifies the TI1 input source 353:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT. 354:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 355:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary function 356:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_IC_SetActiveInput().*/ 357:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 358:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value. 359:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_ICPSC. 360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 361:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary function 362:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_IC_SetPrescaler().*/ 363:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 364:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t IC1Filter; /*!< Specifies the TI1 input filter. 365:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_IC_FILTER. 366:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 367:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary function 368:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_IC_SetFilter().*/ 369:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t IC2Polarity; /*!< Specifies the active edge of TI2 input. 371:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY. ARM GAS /tmp/ccYgfTud.s page 243 372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary function 374:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_IC_SetPolarity().*/ 375:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 376:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t IC2ActiveInput; /*!< Specifies the TI2 input source 377:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT. 378:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 379:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary function 380:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_IC_SetActiveInput().*/ 381:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 382:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t IC2Prescaler; /*!< Specifies the TI2 input prescaler value. 383:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_ICPSC. 384:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 385:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary function 386:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_IC_SetPrescaler().*/ 387:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 388:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t IC2Filter; /*!< Specifies the TI2 input filter. 389:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_IC_FILTER. 390:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 391:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary function 392:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_IC_SetFilter().*/ 393:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 394:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } LL_TIM_ENCODER_InitTypeDef; 395:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 396:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 397:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief TIM Hall sensor interface configuration structure definition. 398:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 399:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** typedef struct 400:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 401:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 402:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input. 403:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY. 404:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 405:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary function 406:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_IC_SetPolarity().*/ 407:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 408:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value. 409:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** Prescaler must be set to get a maximum counter period longer th 410:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** time interval between 2 consecutive changes on the Hall inputs. 411:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_ICPSC. 412:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 413:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary function 414:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_IC_SetPrescaler().*/ 415:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 416:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t IC1Filter; /*!< Specifies the TI1 input filter. 417:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of 418:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref TIM_LL_EC_IC_FILTER. 419:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 420:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary function 421:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_IC_SetFilter().*/ 422:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 423:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t CommutationDelay; /*!< Specifies the compare value to be loaded into the Capture Compa 424:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** A positive pulse (TRGO event) is generated with a programmable 425:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** a change occurs on the Hall inputs. 426:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a number between Min_Data = 0x0000 and Ma 427:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary function ARM GAS /tmp/ccYgfTud.s page 244 429:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_OC_SetCompareCH2().*/ 430:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } LL_TIM_HALLSENSOR_InitTypeDef; 431:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 432:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 433:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief BDTR (Break and Dead Time) structure definition 434:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 435:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** typedef struct 436:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 437:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t OSSRState; /*!< Specifies the Off-State selection used in Run mode. 438:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_OSSR 439:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 440:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary functio 441:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_SetOffStates() 442:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 443:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @note This bit-field cannot be modified as long as LOCK level 444:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** programmed. */ 445:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 446:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t OSSIState; /*!< Specifies the Off-State used in Idle state. 447:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_OSSI 448:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 449:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary functio 450:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_SetOffStates() 451:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 452:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @note This bit-field cannot be modified as long as LOCK level 453:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** programmed. */ 454:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 455:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t LockLevel; /*!< Specifies the LOCK level parameters. 456:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_LOCKLEVEL 457:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 458:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @note The LOCK bits can be written only once after the reset. 459:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** register has been written, their content is frozen until the 460:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 461:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint8_t DeadTime; /*!< Specifies the delay time between the switching-off and the 462:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** switching-on of the outputs. 463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a number between Min_Data = 0x00 and Ma 464:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 465:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary functio 466:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_OC_SetDeadTime() 467:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 468:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @note This bit-field can not be modified as long as LOCK leve 469:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** programmed. */ 470:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 471:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint16_t BreakState; /*!< Specifies whether the TIM Break input is enabled or not. 472:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_BREAK_ENABLE 473:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 474:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary functio 475:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_EnableBRK() or @ref LL_TIM_DisableBRK() 476:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 477:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @note This bit-field can not be modified as long as LOCK leve 478:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** programmed. */ 479:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 480:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t BreakPolarity; /*!< Specifies the TIM Break Input pin polarity. 481:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_BREAK_POLARIT 482:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 483:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary functio 484:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_ConfigBRK() 485:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** ARM GAS /tmp/ccYgfTud.s page 245 486:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @note This bit-field can not be modified as long as LOCK leve 487:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** programmed. */ 488:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 489:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t BreakFilter; /*!< Specifies the TIM Break Filter. 490:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_BREAK_FILTER 491:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 492:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary functio 493:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_ConfigBRK() 494:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 495:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @note This bit-field can not be modified as long as LOCK leve 496:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** programmed. */ 497:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 498:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t Break2State; /*!< Specifies whether the TIM Break2 input is enabled or not. 499:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_BREAK2_ENABLE 500:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 501:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary functio 502:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_EnableBRK2() or @ref LL_TIM_DisableBRK2() 503:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 504:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @note This bit-field can not be modified as long as LOCK leve 505:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** programmed. */ 506:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 507:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t Break2Polarity; /*!< Specifies the TIM Break2 Input pin polarity. 508:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_BREAK2_POLARI 509:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 510:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary functio 511:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_ConfigBRK2() 512:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 513:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @note This bit-field can not be modified as long as LOCK leve 514:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** programmed. */ 515:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 516:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t Break2Filter; /*!< Specifies the TIM Break2 Filter. 517:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_BREAK2_FILTER 518:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 519:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary functio 520:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_ConfigBRK2() 521:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 522:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @note This bit-field can not be modified as long as LOCK leve 523:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** programmed. */ 524:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 525:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t AutomaticOutput; /*!< Specifies whether the TIM Automatic Output feature is enabled 526:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_AUTOMATICOUTP 527:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 528:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary functio 529:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_EnableAutomaticOutput() or @ref LL_TIM_DisableAut 530:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 531:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @note This bit-field can not be modified as long as LOCK leve 532:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** programmed. */ 533:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } LL_TIM_BDTR_InitTypeDef; 534:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 535:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 536:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} 537:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 538:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #endif /* USE_FULL_LL_DRIVER */ 539:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 540:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /* Exported constants --------------------------------------------------------*/ 541:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_Exported_Constants TIM Exported Constants 542:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ ARM GAS /tmp/ccYgfTud.s page 246 543:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 544:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 545:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EC_GET_FLAG Get Flags Defines 546:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Flags defines which can be used with LL_TIM_ReadReg function. 547:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ 548:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 549:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_SR_UIF TIM_SR_UIF /*!< Update interrupt flag */ 550:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_SR_CC1IF TIM_SR_CC1IF /*!< Capture/compare 1 interrup 551:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_SR_CC2IF TIM_SR_CC2IF /*!< Capture/compare 2 interrup 552:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_SR_CC3IF TIM_SR_CC3IF /*!< Capture/compare 3 interrup 553:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_SR_CC4IF TIM_SR_CC4IF /*!< Capture/compare 4 interrup 554:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_SR_CC5IF TIM_SR_CC5IF /*!< Capture/compare 5 interrup 555:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_SR_CC6IF TIM_SR_CC6IF /*!< Capture/compare 6 interrup 556:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_SR_COMIF TIM_SR_COMIF /*!< COM interrupt flag */ 557:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_SR_TIF TIM_SR_TIF /*!< Trigger interrupt flag */ 558:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_SR_BIF TIM_SR_BIF /*!< Break interrupt flag */ 559:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_SR_B2IF TIM_SR_B2IF /*!< Second break interrupt fla 560:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_SR_CC1OF TIM_SR_CC1OF /*!< Capture/Compare 1 overcapt 561:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_SR_CC2OF TIM_SR_CC2OF /*!< Capture/Compare 2 overcapt 562:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_SR_CC3OF TIM_SR_CC3OF /*!< Capture/Compare 3 overcapt 563:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_SR_CC4OF TIM_SR_CC4OF /*!< Capture/Compare 4 overcapt 564:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_SR_SBIF TIM_SR_SBIF /*!< System Break interrupt fla 565:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 566:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} 567:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 568:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 569:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #if defined(USE_FULL_LL_DRIVER) 570:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EC_BREAK_ENABLE Break Enable 571:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ 572:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 573:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_BREAK_DISABLE 0x00000000U /*!< Break function disabled */ 574:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_BREAK_ENABLE TIM_BDTR_BKE /*!< Break function enabled */ 575:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 576:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} 577:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 578:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 579:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EC_BREAK2_ENABLE Break2 Enable 580:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ 581:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 582:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_BREAK2_DISABLE 0x00000000U /*!< Break2 function disabled */ 583:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_BREAK2_ENABLE TIM_BDTR_BK2E /*!< Break2 function enabled */ 584:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 585:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} 586:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 587:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 588:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EC_AUTOMATICOUTPUT_ENABLE Automatic output enable 589:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ 590:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 591:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U /*!< MOE can be set only by 592:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /*!< MOE can be set by softw 593:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 594:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} 595:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 596:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #endif /* USE_FULL_LL_DRIVER */ 597:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 598:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EC_IT IT Defines 599:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief IT defines which can be used with LL_TIM_ReadReg and LL_TIM_WriteReg functions. ARM GAS /tmp/ccYgfTud.s page 247 600:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ 601:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 602:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_DIER_UIE TIM_DIER_UIE /*!< Update interrupt enable */ 603:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_DIER_CC1IE TIM_DIER_CC1IE /*!< Capture/compare 1 interrup 604:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_DIER_CC2IE TIM_DIER_CC2IE /*!< Capture/compare 2 interrup 605:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_DIER_CC3IE TIM_DIER_CC3IE /*!< Capture/compare 3 interrup 606:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_DIER_CC4IE TIM_DIER_CC4IE /*!< Capture/compare 4 interrup 607:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_DIER_COMIE TIM_DIER_COMIE /*!< COM interrupt enable */ 608:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_DIER_TIE TIM_DIER_TIE /*!< Trigger interrupt enable * 609:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_DIER_BIE TIM_DIER_BIE /*!< Break interrupt enable */ 610:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 611:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} 612:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 613:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 614:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EC_UPDATESOURCE Update Source 615:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ 616:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 617:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_UPDATESOURCE_REGULAR 0x00000000U /*!< Counter overflow/underflow 618:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_UPDATESOURCE_COUNTER TIM_CR1_URS /*!< Only counter overflow/unde 619:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 620:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} 621:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 622:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 623:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EC_ONEPULSEMODE One Pulse Mode 624:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ 625:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 626:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_ONEPULSEMODE_SINGLE TIM_CR1_OPM /*!< Counter stops counting at 627:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_ONEPULSEMODE_REPETITIVE 0x00000000U /*!< Counter is not stopped at 628:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 629:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} 630:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 631:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 632:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EC_COUNTERMODE Counter Mode 633:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ 634:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 635:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_COUNTERMODE_UP 0x00000000U /*!< Counter used as upcounter 636:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_COUNTERMODE_DOWN TIM_CR1_DIR /*!< Counter used as downcounte 637:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_COUNTERMODE_CENTER_DOWN TIM_CR1_CMS_0 /*!< The counter counts up and 638:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_COUNTERMODE_CENTER_UP TIM_CR1_CMS_1 /*!< The counter counts up and 639:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_COUNTERMODE_CENTER_UP_DOWN TIM_CR1_CMS /*!< The counter counts up and 640:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 641:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} 642:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 643:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 644:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EC_CLOCKDIVISION Clock Division 645:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ 646:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 647:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_CLOCKDIVISION_DIV1 0x00000000U /*!< tDTS=tCK_INT */ 648:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0 /*!< tDTS=2*tCK_INT */ 649:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1 /*!< tDTS=4*tCK_INT */ 650:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 651:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} 652:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 653:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 654:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EC_COUNTERDIRECTION Counter Direction 655:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ 656:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ ARM GAS /tmp/ccYgfTud.s page 248 657:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_COUNTERDIRECTION_UP 0x00000000U /*!< Timer counter counts up */ 658:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_COUNTERDIRECTION_DOWN TIM_CR1_DIR /*!< Timer counter counts down 659:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 660:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} 661:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 662:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 663:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EC_CCUPDATESOURCE Capture Compare Update Source 664:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ 665:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 666:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_CCUPDATESOURCE_COMG_ONLY 0x00000000U /*!< Capture/compare control bi 667:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI TIM_CR2_CCUS /*!< Capture/compare control bi 668:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 669:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} 670:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 671:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 672:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EC_CCDMAREQUEST Capture Compare DMA Request 673:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ 674:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 675:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_CCDMAREQUEST_CC 0x00000000U /*!< CCx DMA request sent when 676:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_CCDMAREQUEST_UPDATE TIM_CR2_CCDS /*!< CCx DMA requests sent when 677:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 678:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} 679:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 680:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 681:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EC_LOCKLEVEL Lock Level 682:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ 683:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 684:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_LOCKLEVEL_OFF 0x00000000U /*!< LOCK OFF - No bit is write 685:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0 /*!< LOCK Level 1 */ 686:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1 /*!< LOCK Level 2 */ 687:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_LOCKLEVEL_3 TIM_BDTR_LOCK /*!< LOCK Level 3 */ 688:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 689:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} 690:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 691:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 692:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EC_CHANNEL Channel 693:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ 694:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 695:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_CHANNEL_CH1 TIM_CCER_CC1E /*!< Timer input/output channel 1 696:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_CHANNEL_CH1N TIM_CCER_CC1NE /*!< Timer complementary output ch 697:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_CHANNEL_CH2 TIM_CCER_CC2E /*!< Timer input/output channel 2 698:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_CHANNEL_CH2N TIM_CCER_CC2NE /*!< Timer complementary output ch 699:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_CHANNEL_CH3 TIM_CCER_CC3E /*!< Timer input/output channel 3 700:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_CHANNEL_CH3N TIM_CCER_CC3NE /*!< Timer complementary output ch 701:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_CHANNEL_CH4 TIM_CCER_CC4E /*!< Timer input/output channel 4 702:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_CHANNEL_CH5 TIM_CCER_CC5E /*!< Timer output channel 5 */ 703:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_CHANNEL_CH6 TIM_CCER_CC6E /*!< Timer output channel 6 */ 704:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 705:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} 706:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 707:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 708:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #if defined(USE_FULL_LL_DRIVER) 709:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EC_OCSTATE Output Configuration State 710:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ 711:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 712:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_OCSTATE_DISABLE 0x00000000U /*!< OCx is not active */ 713:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_OCSTATE_ENABLE TIM_CCER_CC1E /*!< OCx signal is output on ARM GAS /tmp/ccYgfTud.s page 249 714:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 715:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} 716:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 717:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #endif /* USE_FULL_LL_DRIVER */ 718:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 719:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** Legacy definitions for compatibility purpose 720:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @cond 0 721:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 722:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_OCMODE_ASSYMETRIC_PWM1 LL_TIM_OCMODE_ASYMMETRIC_PWM1 723:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_OCMODE_ASSYMETRIC_PWM2 LL_TIM_OCMODE_ASYMMETRIC_PWM2 724:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 725:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @endcond 726:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 727:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 728:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EC_OCMODE Output Configuration Mode 729:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ 730:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 731:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_OCMODE_FROZEN 0x00000000U 732:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0 733:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1 734:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) 735:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_OCMODE_FORCED_INACTIVE TIM_CCMR1_OC1M_2 736:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0) 737:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1) 738:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1 739:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_OCMODE_RETRIG_OPM1 TIM_CCMR1_OC1M_3 740:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_OCMODE_RETRIG_OPM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0) 741:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_OCMODE_COMBINED_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2) 742:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_OCMODE_COMBINED_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1 743:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_OCMODE_ASYMMETRIC_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1 744:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_OCMODE_ASYMMETRIC_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M) 745:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 746:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} 747:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 748:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 749:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EC_OCPOLARITY Output Configuration Polarity 750:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ 751:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 752:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_OCPOLARITY_HIGH 0x00000000U /*!< OCxactive high*/ 753:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_OCPOLARITY_LOW TIM_CCER_CC1P /*!< OCxactive low*/ 754:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 755:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} 756:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 757:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 758:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EC_OCIDLESTATE Output Configuration Idle State 759:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ 760:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 761:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_OCIDLESTATE_LOW 0x00000000U /*!__REG__, (__VAL 1185:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1186:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 1187:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Read a value in TIM register. 1188:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param __INSTANCE__ TIM Instance 1189:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param __REG__ Register to be read 1190:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval Register value 1191:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1192:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__) 1193:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 1194:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} 1195:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1196:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1197:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 1198:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief HELPER macro retrieving the UIFCPY flag from the counter value. 1199:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note ex: @ref __LL_TIM_GETFLAG_UIFCPY (@ref LL_TIM_GetCounter ()); 1200:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Relevant only if UIF flag remapping has been enabled (UIF status bit is copied 1201:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * to TIMx_CNT register bit 31) 1202:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param __CNT__ Counter value 1203:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval UIF status bit 1204:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1205:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define __LL_TIM_GETFLAG_UIFCPY(__CNT__) \ 1206:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** (READ_BIT((__CNT__), TIM_CNT_UIFCPY) >> TIM_CNT_UIFCPY_Pos) 1207:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1208:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 1209:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief HELPER macro calculating DTG[0:7] in the TIMx_BDTR register to achieve the requested de 1210:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note ex: @ref __LL_TIM_CALC_DEADTIME (80000000, @ref LL_TIM_GetClockDivision (), 120); 1211:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param __TIMCLK__ timer input clock frequency (in Hz) 1212:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param __CKD__ This parameter can be one of the following values: 1213:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CLOCKDIVISION_DIV1 1214:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CLOCKDIVISION_DIV2 1215:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CLOCKDIVISION_DIV4 1216:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param __DT__ deadtime duration (in ns) 1217:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval DTG[0:7] 1218:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1219:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define __LL_TIM_CALC_DEADTIME(__TIMCLK__, __CKD__, __DT__) \ 1220:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** ( (((uint64_t)((__DT__)*1000U)) < ((DT_DELAY_1+1U) * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? 1221:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** (uint8_t)(((uint64_t)((__DT__)*1000U) / TIM_CALC_DTS((__TIMCLK__), (__CKD__))) & DT_DELAY_1) : 1222:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** (((uint64_t)((__DT__)*1000U)) < ((64U + (DT_DELAY_2+1U)) * 2U * TIM_CALC_DTS((__TIMCLK__), (__C 1223:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** (uint8_t)(DT_RANGE_2 | ((uint8_t)((uint8_t)((((uint64_t)((__DT__)*1000U))/ TIM_CALC_DTS((__TIMC 1224:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** (__CKD__))) >> 1U) - (uint8_t) 64) & DT_DELAY_2)) 1225:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_3+1U)) * 8U * TIM_CALC_DTS((__TIMCLK__), (__C 1226:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** (uint8_t)(DT_RANGE_3 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMC ARM GAS /tmp/ccYgfTud.s page 258 1227:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** (__CKD__))) >> 3U) - (uint8_t) 32) & DT_DELAY_3)) 1228:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_4+1U)) * 16U * TIM_CALC_DTS((__TIMCLK__), (__ 1229:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** (uint8_t)(DT_RANGE_4 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMC 1230:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** (__CKD__))) >> 4U) - (uint8_t) 32) & DT_DELAY_4)) 1231:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 0U) 1232:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1233:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 1234:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief HELPER macro calculating the prescaler value to achieve the required counter clock freq 1235:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note ex: @ref __LL_TIM_CALC_PSC (80000000, 1000000); 1236:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param __TIMCLK__ timer input clock frequency (in Hz) 1237:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param __CNTCLK__ counter clock frequency (in Hz) 1238:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval Prescaler value (between Min_Data=0 and Max_Data=65535) 1239:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1240:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define __LL_TIM_CALC_PSC(__TIMCLK__, __CNTCLK__) \ 1241:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** (((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)((((__TIMCLK__) + (__CNTCLK__)/2U)/(__CNTCLK__)) - 1U 1242:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1243:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 1244:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief HELPER macro calculating the auto-reload value to achieve the required output signal fr 1245:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note ex: @ref __LL_TIM_CALC_ARR (1000000, @ref LL_TIM_GetPrescaler (), 10000); 1246:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param __TIMCLK__ timer input clock frequency (in Hz) 1247:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param __PSC__ prescaler 1248:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param __FREQ__ output signal frequency (in Hz) 1249:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535) 1250:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1251:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define __LL_TIM_CALC_ARR(__TIMCLK__, __PSC__, __FREQ__) \ 1252:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** ((((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? (((__TIMCLK__)/((__FREQ__) * ((__PSC__) + 1U)) 1253:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1254:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 1255:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief HELPER macro calculating the compare value required to achieve the required timer outpu 1256:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * active/inactive delay. 1257:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note ex: @ref __LL_TIM_CALC_DELAY (1000000, @ref LL_TIM_GetPrescaler (), 10); 1258:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param __TIMCLK__ timer input clock frequency (in Hz) 1259:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param __PSC__ prescaler 1260:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param __DELAY__ timer output compare active/inactive delay (in us) 1261:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval Compare value (between Min_Data=0 and Max_Data=65535) 1262:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1263:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define __LL_TIM_CALC_DELAY(__TIMCLK__, __PSC__, __DELAY__) \ 1264:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** ((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__)) \ 1265:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** / ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U)))) 1266:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1267:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 1268:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief HELPER macro calculating the auto-reload value to achieve the required pulse duration 1269:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * (when the timer operates in one pulse mode). 1270:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note ex: @ref __LL_TIM_CALC_PULSE (1000000, @ref LL_TIM_GetPrescaler (), 10, 20); 1271:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param __TIMCLK__ timer input clock frequency (in Hz) 1272:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param __PSC__ prescaler 1273:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param __DELAY__ timer output compare active/inactive delay (in us) 1274:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param __PULSE__ pulse duration (in us) 1275:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535) 1276:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1277:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define __LL_TIM_CALC_PULSE(__TIMCLK__, __PSC__, __DELAY__, __PULSE__) \ 1278:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** ((uint32_t)(__LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__PULSE__)) \ 1279:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + __LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__DELAY__)))) 1280:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1281:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 1282:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief HELPER macro retrieving the ratio of the input capture prescaler 1283:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note ex: @ref __LL_TIM_GET_ICPSC_RATIO (@ref LL_TIM_IC_GetPrescaler ()); ARM GAS /tmp/ccYgfTud.s page 259 1284:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param __ICPSC__ This parameter can be one of the following values: 1285:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ICPSC_DIV1 1286:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ICPSC_DIV2 1287:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ICPSC_DIV4 1288:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ICPSC_DIV8 1289:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval Input capture prescaler ratio (1, 2, 4 or 8) 1290:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1291:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define __LL_TIM_GET_ICPSC_RATIO(__ICPSC__) \ 1292:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** ((uint32_t)(0x01U << (((__ICPSC__) >> 16U) >> TIM_CCMR1_IC1PSC_Pos))) 1293:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1294:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1295:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 1296:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} 1297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1298:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1299:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /* Exported functions --------------------------------------------------------*/ 1300:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_Exported_Functions TIM Exported Functions 1301:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ 1302:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1303:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1304:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EF_Time_Base Time Base configuration 1305:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ 1306:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1307:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 1308:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Enable timer counter. 1309:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR1 CEN LL_TIM_EnableCounter 1310:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 1311:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 1312:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1313:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_EnableCounter(TIM_TypeDef *TIMx) 1314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 1315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** SET_BIT(TIMx->CR1, TIM_CR1_CEN); 1316:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 1317:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1318:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 1319:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Disable timer counter. 1320:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR1 CEN LL_TIM_DisableCounter 1321:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 1322:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 1323:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1324:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_DisableCounter(TIM_TypeDef *TIMx) 1325:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 1326:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** CLEAR_BIT(TIMx->CR1, TIM_CR1_CEN); 1327:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 1328:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1329:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 1330:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Indicates whether the timer counter is enabled. 1331:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR1 CEN LL_TIM_IsEnabledCounter 1332:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 1333:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval State of bit (1 or 0). 1334:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1335:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsEnabledCounter(const TIM_TypeDef *TIMx) 1336:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 1337:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return ((READ_BIT(TIMx->CR1, TIM_CR1_CEN) == (TIM_CR1_CEN)) ? 1UL : 0UL); 1338:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 1339:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1340:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** ARM GAS /tmp/ccYgfTud.s page 260 1341:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Enable update event generation. 1342:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR1 UDIS LL_TIM_EnableUpdateEvent 1343:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 1344:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 1345:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_EnableUpdateEvent(TIM_TypeDef *TIMx) 1347:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 1348:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** CLEAR_BIT(TIMx->CR1, TIM_CR1_UDIS); 1349:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 1350:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1351:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 1352:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Disable update event generation. 1353:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR1 UDIS LL_TIM_DisableUpdateEvent 1354:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 1355:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 1356:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1357:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_DisableUpdateEvent(TIM_TypeDef *TIMx) 1358:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 1359:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** SET_BIT(TIMx->CR1, TIM_CR1_UDIS); 1360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 1361:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1362:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 1363:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Indicates whether update event generation is enabled. 1364:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR1 UDIS LL_TIM_IsEnabledUpdateEvent 1365:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 1366:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval Inverted state of bit (0 or 1). 1367:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1368:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsEnabledUpdateEvent(const TIM_TypeDef *TIMx) 1369:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 1370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return ((READ_BIT(TIMx->CR1, TIM_CR1_UDIS) == (uint32_t)RESET) ? 1UL : 0UL); 1371:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 1372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 1374:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Set update event source 1375:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Update event source set to LL_TIM_UPDATESOURCE_REGULAR: any of the following events 1376:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * generate an update interrupt or DMA request if enabled: 1377:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * - Counter overflow/underflow 1378:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * - Setting the UG bit 1379:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * - Update generation through the slave mode controller 1380:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Update event source set to LL_TIM_UPDATESOURCE_COUNTER: only counter 1381:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * overflow/underflow generates an update interrupt or DMA request if enabled. 1382:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR1 URS LL_TIM_SetUpdateSource 1383:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 1384:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param UpdateSource This parameter can be one of the following values: 1385:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_UPDATESOURCE_REGULAR 1386:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_UPDATESOURCE_COUNTER 1387:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 1388:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1389:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_SetUpdateSource(TIM_TypeDef *TIMx, uint32_t UpdateSource) 1390:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 1391:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(TIMx->CR1, TIM_CR1_URS, UpdateSource); 1392:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 1393:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1394:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 1395:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Get actual event update source 1396:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR1 URS LL_TIM_GetUpdateSource 1397:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance ARM GAS /tmp/ccYgfTud.s page 261 1398:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval Returned value can be one of the following values: 1399:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_UPDATESOURCE_REGULAR 1400:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_UPDATESOURCE_COUNTER 1401:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1402:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_GetUpdateSource(const TIM_TypeDef *TIMx) 1403:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 1404:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_URS)); 1405:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 1406:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1407:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 1408:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Set one pulse mode (one shot v.s. repetitive). 1409:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR1 OPM LL_TIM_SetOnePulseMode 1410:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 1411:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param OnePulseMode This parameter can be one of the following values: 1412:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ONEPULSEMODE_SINGLE 1413:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE 1414:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 1415:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1416:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_SetOnePulseMode(TIM_TypeDef *TIMx, uint32_t OnePulseMode) 1417:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 1418:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(TIMx->CR1, TIM_CR1_OPM, OnePulseMode); 1419:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 1420:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1421:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 1422:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Get actual one pulse mode. 1423:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR1 OPM LL_TIM_GetOnePulseMode 1424:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 1425:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval Returned value can be one of the following values: 1426:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ONEPULSEMODE_SINGLE 1427:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE 1428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1429:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_GetOnePulseMode(const TIM_TypeDef *TIMx) 1430:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 1431:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_OPM)); 1432:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 1433:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1434:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 1435:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Set the timer counter counting mode. 1436:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to 1437:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * check whether or not the counter mode selection feature is supported 1438:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * by a timer instance. 1439:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) 1440:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * requires a timer reset to avoid unexpected direction 1441:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * due to DIR bit readonly in center aligned mode. 1442:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR1 DIR LL_TIM_SetCounterMode\n 1443:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CR1 CMS LL_TIM_SetCounterMode 1444:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 1445:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param CounterMode This parameter can be one of the following values: 1446:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_COUNTERMODE_UP 1447:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_COUNTERMODE_DOWN 1448:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP 1449:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN 1450:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN 1451:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 1452:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1453:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_SetCounterMode(TIM_TypeDef *TIMx, uint32_t CounterMode) 1454:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { ARM GAS /tmp/ccYgfTud.s page 262 1455:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(TIMx->CR1, (TIM_CR1_DIR | TIM_CR1_CMS), CounterMode); 1456:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 1457:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1458:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 1459:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Get actual counter mode. 1460:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to 1461:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * check whether or not the counter mode selection feature is supported 1462:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * by a timer instance. 1463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR1 DIR LL_TIM_GetCounterMode\n 1464:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CR1 CMS LL_TIM_GetCounterMode 1465:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 1466:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval Returned value can be one of the following values: 1467:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_COUNTERMODE_UP 1468:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_COUNTERMODE_DOWN 1469:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP 1470:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN 1471:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN 1472:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1473:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_GetCounterMode(const TIM_TypeDef *TIMx) 1474:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 1475:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t counter_mode; 1476:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1477:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** counter_mode = (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CMS)); 1478:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1479:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** if (counter_mode == 0U) 1480:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 1481:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** counter_mode = (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR)); 1482:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 1483:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1484:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return counter_mode; 1485:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 1486:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1487:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 1488:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Enable auto-reload (ARR) preload. 1489:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR1 ARPE LL_TIM_EnableARRPreload 1490:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 1491:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 1492:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1493:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_EnableARRPreload(TIM_TypeDef *TIMx) 1494:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 1495:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** SET_BIT(TIMx->CR1, TIM_CR1_ARPE); 1496:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 1497:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1498:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 1499:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Disable auto-reload (ARR) preload. 1500:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR1 ARPE LL_TIM_DisableARRPreload 1501:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 1502:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 1503:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1504:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_DisableARRPreload(TIM_TypeDef *TIMx) 4230 .loc 5 1504 22 view .LVU1371 4231 .LBB464: 1505:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 1506:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** CLEAR_BIT(TIMx->CR1, TIM_CR1_ARPE); 4232 .loc 5 1506 3 view .LVU1372 4233 005e 4FF08043 mov r3, #1073741824 4234 0062 1A68 ldr r2, [r3] ARM GAS /tmp/ccYgfTud.s page 263 4235 0064 22F08002 bic r2, r2, #128 4236 0068 1A60 str r2, [r3] 4237 .LVL368: 4238 .loc 5 1506 3 is_stmt 0 view .LVU1373 4239 .LBE464: 4240 .LBE463: 1392:Src/main.c **** LL_TIM_SetTriggerOutput(TIM2, LL_TIM_TRGO_RESET); 4241 .loc 1 1392 3 is_stmt 1 view .LVU1374 4242 .LBB465: 4243 .LBI465: 1507:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 1508:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1509:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 1510:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Indicates whether auto-reload (ARR) preload is enabled. 1511:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR1 ARPE LL_TIM_IsEnabledARRPreload 1512:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 1513:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval State of bit (1 or 0). 1514:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1515:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsEnabledARRPreload(const TIM_TypeDef *TIMx) 1516:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 1517:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return ((READ_BIT(TIMx->CR1, TIM_CR1_ARPE) == (TIM_CR1_ARPE)) ? 1UL : 0UL); 1518:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 1519:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1520:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 1521:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Set the division ratio between the timer clock and the sampling clock used by the dead 1522:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * (when supported) and the digital filters. 1523:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check 1524:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * whether or not the clock division feature is supported by the timer 1525:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * instance. 1526:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR1 CKD LL_TIM_SetClockDivision 1527:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 1528:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param ClockDivision This parameter can be one of the following values: 1529:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CLOCKDIVISION_DIV1 1530:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CLOCKDIVISION_DIV2 1531:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CLOCKDIVISION_DIV4 1532:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 1533:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1534:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_SetClockDivision(TIM_TypeDef *TIMx, uint32_t ClockDivision) 1535:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 1536:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(TIMx->CR1, TIM_CR1_CKD, ClockDivision); 1537:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 1538:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1539:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 1540:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Get the actual division ratio between the timer clock and the sampling clock used by t 1541:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * generators (when supported) and the digital filters. 1542:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check 1543:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * whether or not the clock division feature is supported by the timer 1544:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * instance. 1545:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR1 CKD LL_TIM_GetClockDivision 1546:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 1547:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval Returned value can be one of the following values: 1548:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CLOCKDIVISION_DIV1 1549:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CLOCKDIVISION_DIV2 1550:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CLOCKDIVISION_DIV4 1551:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1552:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_GetClockDivision(const TIM_TypeDef *TIMx) 1553:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { ARM GAS /tmp/ccYgfTud.s page 264 1554:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CKD)); 1555:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 1556:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1557:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 1558:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Set the counter value. 1559:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check 1560:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * whether or not a timer instance supports a 32 bits counter. 1561:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CNT CNT LL_TIM_SetCounter 1562:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 1563:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Counter Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF) 1564:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 1565:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1566:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_SetCounter(TIM_TypeDef *TIMx, uint32_t Counter) 1567:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 1568:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** WRITE_REG(TIMx->CNT, Counter); 1569:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 1570:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1571:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 1572:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Get the counter value. 1573:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check 1574:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * whether or not a timer instance supports a 32 bits counter. 1575:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CNT CNT LL_TIM_GetCounter 1576:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 1577:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF) 1578:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1579:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_GetCounter(const TIM_TypeDef *TIMx) 1580:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 1581:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return (uint32_t)(READ_REG(TIMx->CNT)); 1582:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 1583:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1584:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 1585:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Get the current direction of the counter 1586:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR1 DIR LL_TIM_GetDirection 1587:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 1588:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval Returned value can be one of the following values: 1589:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_COUNTERDIRECTION_UP 1590:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_COUNTERDIRECTION_DOWN 1591:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1592:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_GetDirection(const TIM_TypeDef *TIMx) 1593:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 1594:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR)); 1595:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 1596:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1597:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 1598:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Set the prescaler value. 1599:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note The counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1). 1600:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note The prescaler can be changed on the fly as this control register is buffered. The new 1601:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * prescaler ratio is taken into account at the next update event. 1602:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Helper macro @ref __LL_TIM_CALC_PSC can be used to calculate the Prescaler parameter 1603:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll PSC PSC LL_TIM_SetPrescaler 1604:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 1605:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Prescaler between Min_Data=0 and Max_Data=65535 1606:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 1607:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1608:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Prescaler) 1609:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 1610:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** WRITE_REG(TIMx->PSC, Prescaler); ARM GAS /tmp/ccYgfTud.s page 265 1611:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 1612:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1613:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 1614:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Get the prescaler value. 1615:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll PSC PSC LL_TIM_GetPrescaler 1616:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 1617:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval Prescaler value between Min_Data=0 and Max_Data=65535 1618:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1619:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_GetPrescaler(const TIM_TypeDef *TIMx) 1620:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 1621:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return (uint32_t)(READ_REG(TIMx->PSC)); 1622:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 1623:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1624:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 1625:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Set the auto-reload value. 1626:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note The counter is blocked while the auto-reload value is null. 1627:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check 1628:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * whether or not a timer instance supports a 32 bits counter. 1629:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Helper macro @ref __LL_TIM_CALC_ARR can be used to calculate the AutoReload parameter 1630:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll ARR ARR LL_TIM_SetAutoReload 1631:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 1632:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param AutoReload between Min_Data=0 and Max_Data=65535 1633:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 1634:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1635:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_SetAutoReload(TIM_TypeDef *TIMx, uint32_t AutoReload) 1636:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 1637:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** WRITE_REG(TIMx->ARR, AutoReload); 1638:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 1639:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1640:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 1641:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Get the auto-reload value. 1642:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll ARR ARR LL_TIM_GetAutoReload 1643:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check 1644:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * whether or not a timer instance supports a 32 bits counter. 1645:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 1646:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval Auto-reload value 1647:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1648:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_GetAutoReload(const TIM_TypeDef *TIMx) 1649:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 1650:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return (uint32_t)(READ_REG(TIMx->ARR)); 1651:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 1652:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1653:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 1654:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Set the repetition counter value. 1655:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note For advanced timer instances RepetitionCounter can be up to 65535. 1656:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check 1657:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * whether or not a timer instance supports a repetition counter. 1658:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll RCR REP LL_TIM_SetRepetitionCounter 1659:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 1660:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param RepetitionCounter between Min_Data=0 and Max_Data=255 or 65535 for advanced timer. 1661:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 1662:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1663:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_SetRepetitionCounter(TIM_TypeDef *TIMx, uint32_t RepetitionCounter) 1664:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 1665:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** WRITE_REG(TIMx->RCR, RepetitionCounter); 1666:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 1667:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** ARM GAS /tmp/ccYgfTud.s page 266 1668:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 1669:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Get the repetition counter value. 1670:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check 1671:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * whether or not a timer instance supports a repetition counter. 1672:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll RCR REP LL_TIM_GetRepetitionCounter 1673:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 1674:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval Repetition counter value 1675:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1676:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_GetRepetitionCounter(const TIM_TypeDef *TIMx) 1677:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 1678:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return (uint32_t)(READ_REG(TIMx->RCR)); 1679:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 1680:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1681:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 1682:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Force a continuous copy of the update interrupt flag (UIF) into the timer counter regis 1683:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note This allows both the counter value and a potential roll-over condition signalled by the U 1684:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * in an atomic way. 1685:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR1 UIFREMAP LL_TIM_EnableUIFRemap 1686:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 1687:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 1688:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1689:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_EnableUIFRemap(TIM_TypeDef *TIMx) 1690:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 1691:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** SET_BIT(TIMx->CR1, TIM_CR1_UIFREMAP); 1692:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 1693:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1694:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 1695:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Disable update interrupt flag (UIF) remapping. 1696:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR1 UIFREMAP LL_TIM_DisableUIFRemap 1697:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 1698:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 1699:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1700:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_DisableUIFRemap(TIM_TypeDef *TIMx) 1701:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 1702:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** CLEAR_BIT(TIMx->CR1, TIM_CR1_UIFREMAP); 1703:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 1704:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1705:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 1706:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Indicate whether update interrupt flag (UIF) copy is set. 1707:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Counter Counter value 1708:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval State of bit (1 or 0). 1709:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1710:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsActiveUIFCPY(const uint32_t Counter) 1711:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 1712:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return (((Counter & TIM_CNT_UIFCPY) == (TIM_CNT_UIFCPY)) ? 1UL : 0UL); 1713:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 1714:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1715:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 1716:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} 1717:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1718:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1719:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EF_Capture_Compare Capture Compare configuration 1720:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ 1721:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1722:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 1723:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Enable the capture/compare control bits (CCxE, CCxNE and OCxM) preload. 1724:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note CCxE, CCxNE and OCxM bits are preloaded, after having been written, ARM GAS /tmp/ccYgfTud.s page 267 1725:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * they are updated only when a commutation event (COM) occurs. 1726:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Only on channels that have a complementary output. 1727:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check 1728:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * whether or not a timer instance is able to generate a commutation event. 1729:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR2 CCPC LL_TIM_CC_EnablePreload 1730:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 1731:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 1732:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1733:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_CC_EnablePreload(TIM_TypeDef *TIMx) 1734:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 1735:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** SET_BIT(TIMx->CR2, TIM_CR2_CCPC); 1736:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 1737:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1738:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 1739:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Disable the capture/compare control bits (CCxE, CCxNE and OCxM) preload. 1740:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check 1741:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * whether or not a timer instance is able to generate a commutation event. 1742:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR2 CCPC LL_TIM_CC_DisablePreload 1743:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 1744:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 1745:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1746:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_CC_DisablePreload(TIM_TypeDef *TIMx) 1747:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 1748:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** CLEAR_BIT(TIMx->CR2, TIM_CR2_CCPC); 1749:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 1750:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1751:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 1752:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Indicates whether the capture/compare control bits (CCxE, CCxNE and OCxM) preload is en 1753:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR2 CCPC LL_TIM_CC_IsEnabledPreload 1754:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 1755:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval State of bit (1 or 0). 1756:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1757:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledPreload(const TIM_TypeDef *TIMx) 1758:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 1759:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return ((READ_BIT(TIMx->CR2, TIM_CR2_CCPC) == (TIM_CR2_CCPC)) ? 1UL : 0UL); 1760:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 1761:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1762:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 1763:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Set the updated source of the capture/compare control bits (CCxE, CCxNE and OCxM). 1764:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check 1765:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * whether or not a timer instance is able to generate a commutation event. 1766:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR2 CCUS LL_TIM_CC_SetUpdate 1767:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 1768:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param CCUpdateSource This parameter can be one of the following values: 1769:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CCUPDATESOURCE_COMG_ONLY 1770:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI 1771:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 1772:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1773:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_CC_SetUpdate(TIM_TypeDef *TIMx, uint32_t CCUpdateSource) 1774:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 1775:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(TIMx->CR2, TIM_CR2_CCUS, CCUpdateSource); 1776:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 1777:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1778:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 1779:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Set the trigger of the capture/compare DMA request. 1780:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR2 CCDS LL_TIM_CC_SetDMAReqTrigger 1781:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance ARM GAS /tmp/ccYgfTud.s page 268 1782:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param DMAReqTrigger This parameter can be one of the following values: 1783:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CCDMAREQUEST_CC 1784:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CCDMAREQUEST_UPDATE 1785:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 1786:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1787:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_CC_SetDMAReqTrigger(TIM_TypeDef *TIMx, uint32_t DMAReqTrigger) 1788:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 1789:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(TIMx->CR2, TIM_CR2_CCDS, DMAReqTrigger); 1790:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 1791:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1792:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 1793:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Get actual trigger of the capture/compare DMA request. 1794:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR2 CCDS LL_TIM_CC_GetDMAReqTrigger 1795:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 1796:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval Returned value can be one of the following values: 1797:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CCDMAREQUEST_CC 1798:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CCDMAREQUEST_UPDATE 1799:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1800:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_CC_GetDMAReqTrigger(const TIM_TypeDef *TIMx) 1801:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 1802:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return (uint32_t)(READ_BIT(TIMx->CR2, TIM_CR2_CCDS)); 1803:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 1804:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1805:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 1806:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Set the lock level to freeze the 1807:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * configuration of several capture/compare parameters. 1808:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not 1809:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * the lock mechanism is supported by a timer instance. 1810:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll BDTR LOCK LL_TIM_CC_SetLockLevel 1811:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 1812:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param LockLevel This parameter can be one of the following values: 1813:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_LOCKLEVEL_OFF 1814:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_LOCKLEVEL_1 1815:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_LOCKLEVEL_2 1816:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_LOCKLEVEL_3 1817:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 1818:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1819:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_CC_SetLockLevel(TIM_TypeDef *TIMx, uint32_t LockLevel) 1820:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 1821:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(TIMx->BDTR, TIM_BDTR_LOCK, LockLevel); 1822:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 1823:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1824:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 1825:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Enable capture/compare channels. 1826:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCER CC1E LL_TIM_CC_EnableChannel\n 1827:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC1NE LL_TIM_CC_EnableChannel\n 1828:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC2E LL_TIM_CC_EnableChannel\n 1829:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC2NE LL_TIM_CC_EnableChannel\n 1830:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC3E LL_TIM_CC_EnableChannel\n 1831:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC3NE LL_TIM_CC_EnableChannel\n 1832:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC4E LL_TIM_CC_EnableChannel\n 1833:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC5E LL_TIM_CC_EnableChannel\n 1834:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC6E LL_TIM_CC_EnableChannel 1835:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 1836:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Channels This parameter can be a combination of the following values: 1837:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 1838:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1N ARM GAS /tmp/ccYgfTud.s page 269 1839:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 1840:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2N 1841:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 1842:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3N 1843:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 1844:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH5 1845:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH6 1846:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 1847:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1848:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_CC_EnableChannel(TIM_TypeDef *TIMx, uint32_t Channels) 1849:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 1850:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** SET_BIT(TIMx->CCER, Channels); 1851:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 1852:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1853:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 1854:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Disable capture/compare channels. 1855:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCER CC1E LL_TIM_CC_DisableChannel\n 1856:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC1NE LL_TIM_CC_DisableChannel\n 1857:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC2E LL_TIM_CC_DisableChannel\n 1858:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC2NE LL_TIM_CC_DisableChannel\n 1859:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC3E LL_TIM_CC_DisableChannel\n 1860:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC3NE LL_TIM_CC_DisableChannel\n 1861:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC4E LL_TIM_CC_DisableChannel\n 1862:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC5E LL_TIM_CC_DisableChannel\n 1863:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC6E LL_TIM_CC_DisableChannel 1864:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 1865:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Channels This parameter can be a combination of the following values: 1866:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 1867:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1N 1868:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 1869:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2N 1870:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 1871:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3N 1872:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 1873:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH5 1874:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH6 1875:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 1876:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1877:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_CC_DisableChannel(TIM_TypeDef *TIMx, uint32_t Channels) 1878:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 1879:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** CLEAR_BIT(TIMx->CCER, Channels); 1880:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 1881:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1882:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 1883:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Indicate whether channel(s) is(are) enabled. 1884:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCER CC1E LL_TIM_CC_IsEnabledChannel\n 1885:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC1NE LL_TIM_CC_IsEnabledChannel\n 1886:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC2E LL_TIM_CC_IsEnabledChannel\n 1887:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC2NE LL_TIM_CC_IsEnabledChannel\n 1888:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC3E LL_TIM_CC_IsEnabledChannel\n 1889:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC3NE LL_TIM_CC_IsEnabledChannel\n 1890:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC4E LL_TIM_CC_IsEnabledChannel\n 1891:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC5E LL_TIM_CC_IsEnabledChannel\n 1892:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC6E LL_TIM_CC_IsEnabledChannel 1893:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 1894:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Channels This parameter can be a combination of the following values: 1895:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 ARM GAS /tmp/ccYgfTud.s page 270 1896:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1N 1897:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 1898:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2N 1899:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 1900:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3N 1901:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 1902:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH5 1903:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH6 1904:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval State of bit (1 or 0). 1905:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1906:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledChannel(const TIM_TypeDef *TIMx, uint32_t Channels) 1907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 1908:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return ((READ_BIT(TIMx->CCER, Channels) == (Channels)) ? 1UL : 0UL); 1909:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 1910:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1911:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 1912:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} 1913:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1914:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1915:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EF_Output_Channel Output channel configuration 1916:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ 1917:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 1919:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Configure an output channel. 1920:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCMR1 CC1S LL_TIM_OC_ConfigOutput\n 1921:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR1 CC2S LL_TIM_OC_ConfigOutput\n 1922:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 CC3S LL_TIM_OC_ConfigOutput\n 1923:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 CC4S LL_TIM_OC_ConfigOutput\n 1924:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR3 CC5S LL_TIM_OC_ConfigOutput\n 1925:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR3 CC6S LL_TIM_OC_ConfigOutput\n 1926:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC1P LL_TIM_OC_ConfigOutput\n 1927:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC2P LL_TIM_OC_ConfigOutput\n 1928:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC3P LL_TIM_OC_ConfigOutput\n 1929:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC4P LL_TIM_OC_ConfigOutput\n 1930:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC5P LL_TIM_OC_ConfigOutput\n 1931:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC6P LL_TIM_OC_ConfigOutput\n 1932:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CR2 OIS1 LL_TIM_OC_ConfigOutput\n 1933:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CR2 OIS2 LL_TIM_OC_ConfigOutput\n 1934:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CR2 OIS3 LL_TIM_OC_ConfigOutput\n 1935:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CR2 OIS4 LL_TIM_OC_ConfigOutput\n 1936:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CR2 OIS5 LL_TIM_OC_ConfigOutput\n 1937:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CR2 OIS6 LL_TIM_OC_ConfigOutput 1938:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 1939:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Channel This parameter can be one of the following values: 1940:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 1941:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 1942:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 1943:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 1944:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH5 1945:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH6 1946:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Configuration This parameter must be a combination of all the following values: 1947:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCPOLARITY_HIGH or @ref LL_TIM_OCPOLARITY_LOW 1948:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCIDLESTATE_LOW or @ref LL_TIM_OCIDLESTATE_HIGH 1949:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 1950:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1951:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configura 1952:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { ARM GAS /tmp/ccYgfTud.s page 271 1953:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 1954:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iC 1955:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** CLEAR_BIT(*pReg, (TIM_CCMR1_CC1S << SHIFT_TAB_OCxx[iChannel])); 1956:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]), 1957:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** (Configuration & TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]); 1958:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]), 1959:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** (Configuration & TIM_CR2_OIS1) << SHIFT_TAB_OISx[iChannel]); 1960:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 1961:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1962:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 1963:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Define the behavior of the output reference signal OCxREF from which 1964:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * OCx and OCxN (when relevant) are derived. 1965:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCMR1 OC1M LL_TIM_OC_SetMode\n 1966:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR1 OC2M LL_TIM_OC_SetMode\n 1967:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 OC3M LL_TIM_OC_SetMode\n 1968:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 OC4M LL_TIM_OC_SetMode\n 1969:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR3 OC5M LL_TIM_OC_SetMode\n 1970:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR3 OC6M LL_TIM_OC_SetMode 1971:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 1972:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Channel This parameter can be one of the following values: 1973:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 1974:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 1975:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 1976:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 1977:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH5 1978:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH6 1979:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Mode This parameter can be one of the following values: 1980:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_FROZEN 1981:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_ACTIVE 1982:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_INACTIVE 1983:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_TOGGLE 1984:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE 1985:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE 1986:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_PWM1 1987:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_PWM2 1988:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_RETRIG_OPM1 1989:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_RETRIG_OPM2 1990:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_COMBINED_PWM1 1991:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_COMBINED_PWM2 1992:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_ASYMMETRIC_PWM1 1993:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_ASYMMETRIC_PWM2 1994:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 1995:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1996:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Mode) 1997:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 1998:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 1999:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iC 2000:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel]), Mode << SHIFT 2001:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 2002:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 2003:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 2004:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Get the output compare mode of an output channel. 2005:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCMR1 OC1M LL_TIM_OC_GetMode\n 2006:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR1 OC2M LL_TIM_OC_GetMode\n 2007:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 OC3M LL_TIM_OC_GetMode\n 2008:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 OC4M LL_TIM_OC_GetMode\n 2009:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR3 OC5M LL_TIM_OC_GetMode\n ARM GAS /tmp/ccYgfTud.s page 272 2010:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR3 OC6M LL_TIM_OC_GetMode 2011:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 2012:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Channel This parameter can be one of the following values: 2013:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 2014:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 2015:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 2016:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 2017:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH5 2018:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH6 2019:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval Returned value can be one of the following values: 2020:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_FROZEN 2021:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_ACTIVE 2022:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_INACTIVE 2023:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_TOGGLE 2024:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE 2025:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE 2026:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_PWM1 2027:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_PWM2 2028:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_RETRIG_OPM1 2029:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_RETRIG_OPM2 2030:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_COMBINED_PWM1 2031:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_COMBINED_PWM2 2032:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_ASYMMETRIC_PWM1 2033:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_ASYMMETRIC_PWM2 2034:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 2035:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_OC_GetMode(const TIM_TypeDef *TIMx, uint32_t Channel) 2036:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 2037:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 2038:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CC 2039:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return (READ_BIT(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel])) >> SHIFT 2040:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 2041:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 2042:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 2043:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Set the polarity of an output channel. 2044:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCER CC1P LL_TIM_OC_SetPolarity\n 2045:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC1NP LL_TIM_OC_SetPolarity\n 2046:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC2P LL_TIM_OC_SetPolarity\n 2047:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC2NP LL_TIM_OC_SetPolarity\n 2048:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC3P LL_TIM_OC_SetPolarity\n 2049:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC3NP LL_TIM_OC_SetPolarity\n 2050:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC4P LL_TIM_OC_SetPolarity\n 2051:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC5P LL_TIM_OC_SetPolarity\n 2052:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC6P LL_TIM_OC_SetPolarity 2053:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 2054:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Channel This parameter can be one of the following values: 2055:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 2056:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1N 2057:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 2058:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2N 2059:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 2060:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3N 2061:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 2062:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH5 2063:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH6 2064:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Polarity This parameter can be one of the following values: 2065:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCPOLARITY_HIGH 2066:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCPOLARITY_LOW ARM GAS /tmp/ccYgfTud.s page 273 2067:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 2068:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 2069:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_OC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Polarity) 2070:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 2071:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 2072:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]), Polarity << SHIFT_TAB_CCxP[i 2073:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 2074:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 2075:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 2076:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Get the polarity of an output channel. 2077:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCER CC1P LL_TIM_OC_GetPolarity\n 2078:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC1NP LL_TIM_OC_GetPolarity\n 2079:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC2P LL_TIM_OC_GetPolarity\n 2080:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC2NP LL_TIM_OC_GetPolarity\n 2081:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC3P LL_TIM_OC_GetPolarity\n 2082:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC3NP LL_TIM_OC_GetPolarity\n 2083:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC4P LL_TIM_OC_GetPolarity\n 2084:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC5P LL_TIM_OC_GetPolarity\n 2085:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC6P LL_TIM_OC_GetPolarity 2086:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 2087:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Channel This parameter can be one of the following values: 2088:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 2089:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1N 2090:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 2091:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2N 2092:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 2093:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3N 2094:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 2095:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH5 2096:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH6 2097:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval Returned value can be one of the following values: 2098:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCPOLARITY_HIGH 2099:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCPOLARITY_LOW 2100:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 2101:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity(const TIM_TypeDef *TIMx, uint32_t Channel) 2102:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 2103:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 2104:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return (READ_BIT(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel])) >> SHIFT_TAB_CCxP[iChan 2105:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 2106:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 2107:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 2108:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Set the IDLE state of an output channel 2109:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note This function is significant only for the timer instances 2110:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * supporting the break feature. Macro IS_TIM_BREAK_INSTANCE(TIMx) 2111:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * can be used to check whether or not a timer instance provides 2112:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * a break input. 2113:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR2 OIS1 LL_TIM_OC_SetIdleState\n 2114:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CR2 OIS2N LL_TIM_OC_SetIdleState\n 2115:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CR2 OIS2 LL_TIM_OC_SetIdleState\n 2116:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CR2 OIS2N LL_TIM_OC_SetIdleState\n 2117:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CR2 OIS3 LL_TIM_OC_SetIdleState\n 2118:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CR2 OIS3N LL_TIM_OC_SetIdleState\n 2119:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CR2 OIS4 LL_TIM_OC_SetIdleState\n 2120:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CR2 OIS5 LL_TIM_OC_SetIdleState\n 2121:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CR2 OIS6 LL_TIM_OC_SetIdleState 2122:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 2123:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Channel This parameter can be one of the following values: ARM GAS /tmp/ccYgfTud.s page 274 2124:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 2125:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1N 2126:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 2127:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2N 2128:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 2129:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3N 2130:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 2131:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH5 2132:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH6 2133:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param IdleState This parameter can be one of the following values: 2134:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCIDLESTATE_LOW 2135:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCIDLESTATE_HIGH 2136:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 2137:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 2138:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_OC_SetIdleState(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t IdleState 2139:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 2140:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 2141:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]), IdleState << SHIFT_TAB_OISx[iC 2142:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 2143:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 2144:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 2145:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Get the IDLE state of an output channel 2146:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR2 OIS1 LL_TIM_OC_GetIdleState\n 2147:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CR2 OIS2N LL_TIM_OC_GetIdleState\n 2148:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CR2 OIS2 LL_TIM_OC_GetIdleState\n 2149:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CR2 OIS2N LL_TIM_OC_GetIdleState\n 2150:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CR2 OIS3 LL_TIM_OC_GetIdleState\n 2151:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CR2 OIS3N LL_TIM_OC_GetIdleState\n 2152:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CR2 OIS4 LL_TIM_OC_GetIdleState\n 2153:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CR2 OIS5 LL_TIM_OC_GetIdleState\n 2154:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CR2 OIS6 LL_TIM_OC_GetIdleState 2155:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 2156:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Channel This parameter can be one of the following values: 2157:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 2158:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1N 2159:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 2160:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2N 2161:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 2162:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3N 2163:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 2164:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH5 2165:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH6 2166:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval Returned value can be one of the following values: 2167:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCIDLESTATE_LOW 2168:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCIDLESTATE_HIGH 2169:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 2170:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_OC_GetIdleState(const TIM_TypeDef *TIMx, uint32_t Channel) 2171:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 2172:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 2173:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return (READ_BIT(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel])) >> SHIFT_TAB_OISx[iChanne 2174:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 2175:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 2176:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 2177:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Enable fast mode for the output channel. 2178:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Acts only if the channel is configured in PWM1 or PWM2 mode. 2179:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCMR1 OC1FE LL_TIM_OC_EnableFast\n 2180:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR1 OC2FE LL_TIM_OC_EnableFast\n ARM GAS /tmp/ccYgfTud.s page 275 2181:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 OC3FE LL_TIM_OC_EnableFast\n 2182:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 OC4FE LL_TIM_OC_EnableFast\n 2183:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR3 OC5FE LL_TIM_OC_EnableFast\n 2184:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR3 OC6FE LL_TIM_OC_EnableFast 2185:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 2186:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Channel This parameter can be one of the following values: 2187:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 2188:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 2189:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 2190:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 2191:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH5 2192:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH6 2193:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 2194:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 2195:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_OC_EnableFast(TIM_TypeDef *TIMx, uint32_t Channel) 2196:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 2197:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 2198:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iC 2199:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** SET_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel])); 2200:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 2201:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 2202:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 2203:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 2204:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Disable fast mode for the output channel. 2205:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCMR1 OC1FE LL_TIM_OC_DisableFast\n 2206:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR1 OC2FE LL_TIM_OC_DisableFast\n 2207:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 OC3FE LL_TIM_OC_DisableFast\n 2208:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 OC4FE LL_TIM_OC_DisableFast\n 2209:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR3 OC5FE LL_TIM_OC_DisableFast\n 2210:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR3 OC6FE LL_TIM_OC_DisableFast 2211:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 2212:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Channel This parameter can be one of the following values: 2213:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 2214:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 2215:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 2216:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 2217:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH5 2218:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH6 2219:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 2220:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 2221:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_OC_DisableFast(TIM_TypeDef *TIMx, uint32_t Channel) 2222:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 2223:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 2224:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iC 2225:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** CLEAR_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel])); 2226:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 2227:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 2228:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 2229:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 2230:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Indicates whether fast mode is enabled for the output channel. 2231:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCMR1 OC1FE LL_TIM_OC_IsEnabledFast\n 2232:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR1 OC2FE LL_TIM_OC_IsEnabledFast\n 2233:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 OC3FE LL_TIM_OC_IsEnabledFast\n 2234:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 OC4FE LL_TIM_OC_IsEnabledFast\n 2235:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR3 OC5FE LL_TIM_OC_IsEnabledFast\n 2236:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR3 OC6FE LL_TIM_OC_IsEnabledFast 2237:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance ARM GAS /tmp/ccYgfTud.s page 276 2238:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Channel This parameter can be one of the following values: 2239:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 2240:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 2241:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 2242:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 2243:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH5 2244:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH6 2245:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval State of bit (1 or 0). 2246:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 2247:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(const TIM_TypeDef *TIMx, uint32_t Channel) 2248:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 2249:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 2250:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CC 2251:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t bitfield = TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]; 2252:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL); 2253:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 2254:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 2255:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 2256:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Enable compare register (TIMx_CCRx) preload for the output channel. 2257:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCMR1 OC1PE LL_TIM_OC_EnablePreload\n 2258:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR1 OC2PE LL_TIM_OC_EnablePreload\n 2259:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 OC3PE LL_TIM_OC_EnablePreload\n 2260:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 OC4PE LL_TIM_OC_EnablePreload\n 2261:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR3 OC5PE LL_TIM_OC_EnablePreload\n 2262:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR3 OC6PE LL_TIM_OC_EnablePreload 2263:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 2264:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Channel This parameter can be one of the following values: 2265:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 2266:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 2267:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 2268:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 2269:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH5 2270:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH6 2271:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 2272:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 2273:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_OC_EnablePreload(TIM_TypeDef *TIMx, uint32_t Channel) 2274:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 2275:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 2276:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iC 2277:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** SET_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel])); 2278:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 2279:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 2280:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 2281:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Disable compare register (TIMx_CCRx) preload for the output channel. 2282:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCMR1 OC1PE LL_TIM_OC_DisablePreload\n 2283:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR1 OC2PE LL_TIM_OC_DisablePreload\n 2284:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 OC3PE LL_TIM_OC_DisablePreload\n 2285:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 OC4PE LL_TIM_OC_DisablePreload\n 2286:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR3 OC5PE LL_TIM_OC_DisablePreload\n 2287:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR3 OC6PE LL_TIM_OC_DisablePreload 2288:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 2289:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Channel This parameter can be one of the following values: 2290:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 2291:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 2292:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 2293:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 2294:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH5 ARM GAS /tmp/ccYgfTud.s page 277 2295:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH6 2296:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 2297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 2298:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_OC_DisablePreload(TIM_TypeDef *TIMx, uint32_t Channel) 2299:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 2300:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 2301:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iC 2302:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** CLEAR_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel])); 2303:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 2304:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 2305:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 2306:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Indicates whether compare register (TIMx_CCRx) preload is enabled for the output channe 2307:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCMR1 OC1PE LL_TIM_OC_IsEnabledPreload\n 2308:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR1 OC2PE LL_TIM_OC_IsEnabledPreload\n 2309:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 OC3PE LL_TIM_OC_IsEnabledPreload\n 2310:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 OC4PE LL_TIM_OC_IsEnabledPreload\n 2311:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR3 OC5PE LL_TIM_OC_IsEnabledPreload\n 2312:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR3 OC6PE LL_TIM_OC_IsEnabledPreload 2313:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 2314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Channel This parameter can be one of the following values: 2315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 2316:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 2317:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 2318:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 2319:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH5 2320:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH6 2321:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval State of bit (1 or 0). 2322:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 2323:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(const TIM_TypeDef *TIMx, uint32_t Channel) 2324:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 2325:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 2326:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CC 2327:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t bitfield = TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]; 2328:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL); 2329:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 2330:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 2331:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 2332:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Enable clearing the output channel on an external event. 2333:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note This function can only be used in Output compare and PWM modes. It does not work in Force 2334:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether 2335:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * or not a timer instance can clear the OCxREF signal on an external event. 2336:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCMR1 OC1CE LL_TIM_OC_EnableClear\n 2337:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR1 OC2CE LL_TIM_OC_EnableClear\n 2338:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 OC3CE LL_TIM_OC_EnableClear\n 2339:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 OC4CE LL_TIM_OC_EnableClear\n 2340:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR3 OC5CE LL_TIM_OC_EnableClear\n 2341:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR3 OC6CE LL_TIM_OC_EnableClear 2342:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 2343:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Channel This parameter can be one of the following values: 2344:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 2345:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 2346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 2347:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 2348:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH5 2349:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH6 2350:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 2351:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ ARM GAS /tmp/ccYgfTud.s page 278 2352:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_OC_EnableClear(TIM_TypeDef *TIMx, uint32_t Channel) 2353:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 2354:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 2355:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iC 2356:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** SET_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel])); 2357:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 2358:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 2359:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 2360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Disable clearing the output channel on an external event. 2361:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether 2362:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * or not a timer instance can clear the OCxREF signal on an external event. 2363:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCMR1 OC1CE LL_TIM_OC_DisableClear\n 2364:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR1 OC2CE LL_TIM_OC_DisableClear\n 2365:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 OC3CE LL_TIM_OC_DisableClear\n 2366:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 OC4CE LL_TIM_OC_DisableClear\n 2367:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR3 OC5CE LL_TIM_OC_DisableClear\n 2368:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR3 OC6CE LL_TIM_OC_DisableClear 2369:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 2370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Channel This parameter can be one of the following values: 2371:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 2372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 2373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 2374:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 2375:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH5 2376:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH6 2377:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 2378:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 2379:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_OC_DisableClear(TIM_TypeDef *TIMx, uint32_t Channel) 2380:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 2381:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 2382:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iC 2383:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** CLEAR_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel])); 2384:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 2385:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 2386:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 2387:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Indicates clearing the output channel on an external event is enabled for the output ch 2388:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note This function enables clearing the output channel on an external event. 2389:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note This function can only be used in Output compare and PWM modes. It does not work in Force 2390:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether 2391:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * or not a timer instance can clear the OCxREF signal on an external event. 2392:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCMR1 OC1CE LL_TIM_OC_IsEnabledClear\n 2393:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR1 OC2CE LL_TIM_OC_IsEnabledClear\n 2394:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 OC3CE LL_TIM_OC_IsEnabledClear\n 2395:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 OC4CE LL_TIM_OC_IsEnabledClear\n 2396:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR3 OC5CE LL_TIM_OC_IsEnabledClear\n 2397:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR3 OC6CE LL_TIM_OC_IsEnabledClear 2398:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 2399:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Channel This parameter can be one of the following values: 2400:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 2401:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 2402:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 2403:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 2404:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH5 2405:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH6 2406:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval State of bit (1 or 0). 2407:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 2408:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(const TIM_TypeDef *TIMx, uint32_t Channel) ARM GAS /tmp/ccYgfTud.s page 279 2409:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 2410:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 2411:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CC 2412:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t bitfield = TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]; 2413:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL); 2414:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 2415:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 2416:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 2417:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Set the dead-time delay (delay inserted between the rising edge of the OCxREF signal an 2418:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * the Ocx and OCxN signals). 2419:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not 2420:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * dead-time insertion feature is supported by a timer instance. 2421:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Helper macro @ref __LL_TIM_CALC_DEADTIME can be used to calculate the DeadTime parameter 2422:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll BDTR DTG LL_TIM_OC_SetDeadTime 2423:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 2424:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param DeadTime between Min_Data=0 and Max_Data=255 2425:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 2426:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 2427:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_OC_SetDeadTime(TIM_TypeDef *TIMx, uint32_t DeadTime) 2428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 2429:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(TIMx->BDTR, TIM_BDTR_DTG, DeadTime); 2430:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 2431:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 2432:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 2433:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Set compare value for output channel 1 (TIMx_CCR1). 2434:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF. 2435:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check 2436:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * whether or not a timer instance supports a 32 bits counter. 2437:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not 2438:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * output channel 1 is supported by a timer instance. 2439:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCR1 CCR1 LL_TIM_OC_SetCompareCH1 2440:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 2441:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param CompareValue between Min_Data=0 and Max_Data=65535 2442:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 2443:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 2444:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_OC_SetCompareCH1(TIM_TypeDef *TIMx, uint32_t CompareValue) 2445:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 2446:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** WRITE_REG(TIMx->CCR1, CompareValue); 2447:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 2448:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 2449:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 2450:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Set compare value for output channel 2 (TIMx_CCR2). 2451:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF. 2452:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check 2453:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * whether or not a timer instance supports a 32 bits counter. 2454:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not 2455:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * output channel 2 is supported by a timer instance. 2456:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCR2 CCR2 LL_TIM_OC_SetCompareCH2 2457:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 2458:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param CompareValue between Min_Data=0 and Max_Data=65535 2459:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 2460:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 2461:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_OC_SetCompareCH2(TIM_TypeDef *TIMx, uint32_t CompareValue) 2462:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 2463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** WRITE_REG(TIMx->CCR2, CompareValue); 2464:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 2465:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** ARM GAS /tmp/ccYgfTud.s page 280 2466:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 2467:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Set compare value for output channel 3 (TIMx_CCR3). 2468:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF. 2469:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check 2470:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * whether or not a timer instance supports a 32 bits counter. 2471:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not 2472:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * output channel is supported by a timer instance. 2473:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCR3 CCR3 LL_TIM_OC_SetCompareCH3 2474:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 2475:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param CompareValue between Min_Data=0 and Max_Data=65535 2476:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 2477:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 2478:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_OC_SetCompareCH3(TIM_TypeDef *TIMx, uint32_t CompareValue) 2479:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 2480:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** WRITE_REG(TIMx->CCR3, CompareValue); 2481:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 2482:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 2483:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 2484:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Set compare value for output channel 4 (TIMx_CCR4). 2485:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF. 2486:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check 2487:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * whether or not a timer instance supports a 32 bits counter. 2488:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not 2489:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * output channel 4 is supported by a timer instance. 2490:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCR4 CCR4 LL_TIM_OC_SetCompareCH4 2491:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 2492:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param CompareValue between Min_Data=0 and Max_Data=65535 2493:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 2494:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 2495:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_OC_SetCompareCH4(TIM_TypeDef *TIMx, uint32_t CompareValue) 2496:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 2497:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** WRITE_REG(TIMx->CCR4, CompareValue); 2498:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 2499:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 2500:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 2501:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Set compare value for output channel 5 (TIMx_CCR5). 2502:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not 2503:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * output channel 5 is supported by a timer instance. 2504:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCR5 CCR5 LL_TIM_OC_SetCompareCH5 2505:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 2506:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param CompareValue between Min_Data=0 and Max_Data=65535 2507:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 2508:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 2509:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_OC_SetCompareCH5(TIM_TypeDef *TIMx, uint32_t CompareValue) 2510:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 2511:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(TIMx->CCR5, TIM_CCR5_CCR5, CompareValue); 2512:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 2513:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 2514:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 2515:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Set compare value for output channel 6 (TIMx_CCR6). 2516:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not 2517:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * output channel 6 is supported by a timer instance. 2518:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCR6 CCR6 LL_TIM_OC_SetCompareCH6 2519:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 2520:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param CompareValue between Min_Data=0 and Max_Data=65535 2521:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 2522:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ ARM GAS /tmp/ccYgfTud.s page 281 2523:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_OC_SetCompareCH6(TIM_TypeDef *TIMx, uint32_t CompareValue) 2524:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 2525:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** WRITE_REG(TIMx->CCR6, CompareValue); 2526:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 2527:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 2528:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 2529:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Get compare value (TIMx_CCR1) set for output channel 1. 2530:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFF 2531:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check 2532:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * whether or not a timer instance supports a 32 bits counter. 2533:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not 2534:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * output channel 1 is supported by a timer instance. 2535:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCR1 CCR1 LL_TIM_OC_GetCompareCH1 2536:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 2537:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval CompareValue (between Min_Data=0 and Max_Data=65535) 2538:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 2539:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH1(const TIM_TypeDef *TIMx) 2540:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 2541:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return (uint32_t)(READ_REG(TIMx->CCR1)); 2542:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 2543:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 2544:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 2545:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Get compare value (TIMx_CCR2) set for output channel 2. 2546:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFF 2547:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check 2548:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * whether or not a timer instance supports a 32 bits counter. 2549:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not 2550:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * output channel 2 is supported by a timer instance. 2551:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCR2 CCR2 LL_TIM_OC_GetCompareCH2 2552:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 2553:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval CompareValue (between Min_Data=0 and Max_Data=65535) 2554:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 2555:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH2(const TIM_TypeDef *TIMx) 2556:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 2557:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return (uint32_t)(READ_REG(TIMx->CCR2)); 2558:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 2559:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 2560:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 2561:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Get compare value (TIMx_CCR3) set for output channel 3. 2562:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFF 2563:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check 2564:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * whether or not a timer instance supports a 32 bits counter. 2565:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not 2566:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * output channel 3 is supported by a timer instance. 2567:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCR3 CCR3 LL_TIM_OC_GetCompareCH3 2568:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 2569:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval CompareValue (between Min_Data=0 and Max_Data=65535) 2570:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 2571:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH3(const TIM_TypeDef *TIMx) 2572:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 2573:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return (uint32_t)(READ_REG(TIMx->CCR3)); 2574:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 2575:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 2576:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 2577:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Get compare value (TIMx_CCR4) set for output channel 4. 2578:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFF 2579:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check ARM GAS /tmp/ccYgfTud.s page 282 2580:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * whether or not a timer instance supports a 32 bits counter. 2581:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not 2582:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * output channel 4 is supported by a timer instance. 2583:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCR4 CCR4 LL_TIM_OC_GetCompareCH4 2584:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 2585:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval CompareValue (between Min_Data=0 and Max_Data=65535) 2586:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 2587:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH4(const TIM_TypeDef *TIMx) 2588:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 2589:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return (uint32_t)(READ_REG(TIMx->CCR4)); 2590:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 2591:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 2592:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 2593:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Get compare value (TIMx_CCR5) set for output channel 5. 2594:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not 2595:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * output channel 5 is supported by a timer instance. 2596:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCR5 CCR5 LL_TIM_OC_GetCompareCH5 2597:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 2598:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval CompareValue (between Min_Data=0 and Max_Data=65535) 2599:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 2600:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH5(const TIM_TypeDef *TIMx) 2601:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 2602:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return (uint32_t)(READ_BIT(TIMx->CCR5, TIM_CCR5_CCR5)); 2603:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 2604:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 2605:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 2606:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Get compare value (TIMx_CCR6) set for output channel 6. 2607:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not 2608:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * output channel 6 is supported by a timer instance. 2609:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCR6 CCR6 LL_TIM_OC_GetCompareCH6 2610:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 2611:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval CompareValue (between Min_Data=0 and Max_Data=65535) 2612:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 2613:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH6(const TIM_TypeDef *TIMx) 2614:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 2615:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return (uint32_t)(READ_REG(TIMx->CCR6)); 2616:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 2617:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 2618:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 2619:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Select on which reference signal the OC5REF is combined to. 2620:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_COMBINED3PHASEPWM_INSTANCE(TIMx) can be used to check 2621:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * whether or not a timer instance supports the combined 3-phase PWM mode. 2622:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCR5 GC5C3 LL_TIM_SetCH5CombinedChannels\n 2623:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCR5 GC5C2 LL_TIM_SetCH5CombinedChannels\n 2624:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCR5 GC5C1 LL_TIM_SetCH5CombinedChannels 2625:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 2626:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param GroupCH5 This parameter can be a combination of the following values: 2627:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_GROUPCH5_NONE 2628:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_GROUPCH5_OC1REFC 2629:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_GROUPCH5_OC2REFC 2630:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_GROUPCH5_OC3REFC 2631:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 2632:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 2633:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_SetCH5CombinedChannels(TIM_TypeDef *TIMx, uint32_t GroupCH5) 2634:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 2635:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(TIMx->CCR5, (TIM_CCR5_GC5C3 | TIM_CCR5_GC5C2 | TIM_CCR5_GC5C1), GroupCH5); 2636:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } ARM GAS /tmp/ccYgfTud.s page 283 2637:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 2638:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 2639:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} 2640:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 2641:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 2642:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EF_Input_Channel Input channel configuration 2643:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ 2644:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 2645:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 2646:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Configure input channel. 2647:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCMR1 CC1S LL_TIM_IC_Config\n 2648:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR1 IC1PSC LL_TIM_IC_Config\n 2649:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR1 IC1F LL_TIM_IC_Config\n 2650:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR1 CC2S LL_TIM_IC_Config\n 2651:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR1 IC2PSC LL_TIM_IC_Config\n 2652:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR1 IC2F LL_TIM_IC_Config\n 2653:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 CC3S LL_TIM_IC_Config\n 2654:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 IC3PSC LL_TIM_IC_Config\n 2655:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 IC3F LL_TIM_IC_Config\n 2656:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 CC4S LL_TIM_IC_Config\n 2657:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 IC4PSC LL_TIM_IC_Config\n 2658:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 IC4F LL_TIM_IC_Config\n 2659:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC1P LL_TIM_IC_Config\n 2660:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC1NP LL_TIM_IC_Config\n 2661:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC2P LL_TIM_IC_Config\n 2662:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC2NP LL_TIM_IC_Config\n 2663:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC3P LL_TIM_IC_Config\n 2664:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC3NP LL_TIM_IC_Config\n 2665:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC4P LL_TIM_IC_Config\n 2666:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC4NP LL_TIM_IC_Config 2667:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 2668:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Channel This parameter can be one of the following values: 2669:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 2670:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 2671:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 2672:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 2673:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Configuration This parameter must be a combination of all the following values: 2674:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI or @ref LL_TIM_ACTIVEINPUT_INDIRECTTI or @ref LL_ 2675:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ICPSC_DIV1 or ... or @ref LL_TIM_ICPSC_DIV8 2676:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV1 or ... or @ref LL_TIM_IC_FILTER_FDIV32_N8 2677:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_POLARITY_RISING or @ref LL_TIM_IC_POLARITY_FALLING or @ref LL_TIM_I 2678:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 2679:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 2680:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration) 2681:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 2682:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 2683:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iC 2684:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChanne 2685:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** ((Configuration >> 16U) & (TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S)) 2686:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** << SHIFT_TAB_ICxx[iChannel]); 2687:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]), 2688:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** (Configuration & (TIM_CCER_CC1NP | TIM_CCER_CC1P)) << SHIFT_TAB_CCxP[iChannel]); 2689:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 2690:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 2691:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 2692:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Set the active input. 2693:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCMR1 CC1S LL_TIM_IC_SetActiveInput\n ARM GAS /tmp/ccYgfTud.s page 284 2694:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR1 CC2S LL_TIM_IC_SetActiveInput\n 2695:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 CC3S LL_TIM_IC_SetActiveInput\n 2696:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 CC4S LL_TIM_IC_SetActiveInput 2697:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 2698:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Channel This parameter can be one of the following values: 2699:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 2700:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 2701:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 2702:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 2703:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param ICActiveInput This parameter can be one of the following values: 2704:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI 2705:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI 2706:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ACTIVEINPUT_TRC 2707:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 2708:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 2709:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_IC_SetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICActiv 2710:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 2711:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 2712:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iC 2713:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), (ICActiveInput >> 16U) << SHIFT 2714:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 2715:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 2716:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 2717:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Get the current active input. 2718:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCMR1 CC1S LL_TIM_IC_GetActiveInput\n 2719:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR1 CC2S LL_TIM_IC_GetActiveInput\n 2720:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 CC3S LL_TIM_IC_GetActiveInput\n 2721:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 CC4S LL_TIM_IC_GetActiveInput 2722:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 2723:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Channel This parameter can be one of the following values: 2724:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 2725:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 2726:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 2727:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 2728:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval Returned value can be one of the following values: 2729:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI 2730:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI 2731:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ACTIVEINPUT_TRC 2732:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 2733:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(const TIM_TypeDef *TIMx, uint32_t Channel) 2734:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 2735:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 2736:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CC 2737:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return ((READ_BIT(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChann 2738:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 2739:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 2740:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 2741:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Set the prescaler of input channel. 2742:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCMR1 IC1PSC LL_TIM_IC_SetPrescaler\n 2743:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR1 IC2PSC LL_TIM_IC_SetPrescaler\n 2744:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 IC3PSC LL_TIM_IC_SetPrescaler\n 2745:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 IC4PSC LL_TIM_IC_SetPrescaler 2746:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 2747:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Channel This parameter can be one of the following values: 2748:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 2749:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 2750:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 ARM GAS /tmp/ccYgfTud.s page 285 2751:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 2752:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param ICPrescaler This parameter can be one of the following values: 2753:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ICPSC_DIV1 2754:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ICPSC_DIV2 2755:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ICPSC_DIV4 2756:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ICPSC_DIV8 2757:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 2758:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 2759:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_IC_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPrescal 2760:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 2761:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 2762:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iC 2763:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel]), (ICPrescaler >> 16U) << SHIFT 2764:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 2765:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 2766:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 2767:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Get the current prescaler value acting on an input channel. 2768:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCMR1 IC1PSC LL_TIM_IC_GetPrescaler\n 2769:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR1 IC2PSC LL_TIM_IC_GetPrescaler\n 2770:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 IC3PSC LL_TIM_IC_GetPrescaler\n 2771:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 IC4PSC LL_TIM_IC_GetPrescaler 2772:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 2773:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Channel This parameter can be one of the following values: 2774:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 2775:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 2776:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 2777:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 2778:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval Returned value can be one of the following values: 2779:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ICPSC_DIV1 2780:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ICPSC_DIV2 2781:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ICPSC_DIV4 2782:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ICPSC_DIV8 2783:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 2784:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(const TIM_TypeDef *TIMx, uint32_t Channel) 2785:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 2786:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 2787:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CC 2788:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iCha 2789:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 2790:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 2791:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 2792:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Set the input filter duration. 2793:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCMR1 IC1F LL_TIM_IC_SetFilter\n 2794:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR1 IC2F LL_TIM_IC_SetFilter\n 2795:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 IC3F LL_TIM_IC_SetFilter\n 2796:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 IC4F LL_TIM_IC_SetFilter 2797:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 2798:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Channel This parameter can be one of the following values: 2799:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 2800:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 2801:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 2802:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 2803:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param ICFilter This parameter can be one of the following values: 2804:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV1 2805:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV1_N2 2806:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV1_N4 2807:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV1_N8 ARM GAS /tmp/ccYgfTud.s page 286 2808:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV2_N6 2809:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV2_N8 2810:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV4_N6 2811:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV4_N8 2812:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV8_N6 2813:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV8_N8 2814:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV16_N5 2815:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV16_N6 2816:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV16_N8 2817:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV32_N5 2818:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV32_N6 2819:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV32_N8 2820:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 2821:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 2822:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_IC_SetFilter(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICFilter) 2823:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 2824:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 2825:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iC 2826:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel]), (ICFilter >> 16U) << SHIFT_TAB_ 2827:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 2828:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 2829:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 2830:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Get the input filter duration. 2831:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCMR1 IC1F LL_TIM_IC_GetFilter\n 2832:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR1 IC2F LL_TIM_IC_GetFilter\n 2833:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 IC3F LL_TIM_IC_GetFilter\n 2834:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 IC4F LL_TIM_IC_GetFilter 2835:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 2836:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Channel This parameter can be one of the following values: 2837:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 2838:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 2839:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 2840:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 2841:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval Returned value can be one of the following values: 2842:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV1 2843:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV1_N2 2844:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV1_N4 2845:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV1_N8 2846:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV2_N6 2847:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV2_N8 2848:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV4_N6 2849:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV4_N8 2850:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV8_N6 2851:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV8_N8 2852:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV16_N5 2853:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV16_N6 2854:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV16_N8 2855:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV32_N5 2856:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV32_N6 2857:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV32_N8 2858:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 2859:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IC_GetFilter(const TIM_TypeDef *TIMx, uint32_t Channel) 2860:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 2861:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 2862:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CC 2863:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChann 2864:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } ARM GAS /tmp/ccYgfTud.s page 287 2865:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 2866:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 2867:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Set the input channel polarity. 2868:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCER CC1P LL_TIM_IC_SetPolarity\n 2869:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC1NP LL_TIM_IC_SetPolarity\n 2870:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC2P LL_TIM_IC_SetPolarity\n 2871:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC2NP LL_TIM_IC_SetPolarity\n 2872:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC3P LL_TIM_IC_SetPolarity\n 2873:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC3NP LL_TIM_IC_SetPolarity\n 2874:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC4P LL_TIM_IC_SetPolarity\n 2875:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC4NP LL_TIM_IC_SetPolarity 2876:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 2877:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Channel This parameter can be one of the following values: 2878:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 2879:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 2880:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 2881:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 2882:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param ICPolarity This parameter can be one of the following values: 2883:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_POLARITY_RISING 2884:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_POLARITY_FALLING 2885:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE 2886:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 2887:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 2888:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_IC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPolarity 2889:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 2890:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 2891:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]), 2892:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** ICPolarity << SHIFT_TAB_CCxP[iChannel]); 2893:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 2894:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 2895:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 2896:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Get the current input channel polarity. 2897:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCER CC1P LL_TIM_IC_GetPolarity\n 2898:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC1NP LL_TIM_IC_GetPolarity\n 2899:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC2P LL_TIM_IC_GetPolarity\n 2900:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC2NP LL_TIM_IC_GetPolarity\n 2901:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC3P LL_TIM_IC_GetPolarity\n 2902:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC3NP LL_TIM_IC_GetPolarity\n 2903:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC4P LL_TIM_IC_GetPolarity\n 2904:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC4NP LL_TIM_IC_GetPolarity 2905:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 2906:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Channel This parameter can be one of the following values: 2907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 2908:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 2909:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 2910:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 2911:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval Returned value can be one of the following values: 2912:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_POLARITY_RISING 2913:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_POLARITY_FALLING 2914:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE 2915:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 2916:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IC_GetPolarity(const TIM_TypeDef *TIMx, uint32_t Channel) 2917:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 2918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 2919:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return (READ_BIT(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel])) >> 2920:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** SHIFT_TAB_CCxP[iChannel]); 2921:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } ARM GAS /tmp/ccYgfTud.s page 288 2922:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 2923:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 2924:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Connect the TIMx_CH1, CH2 and CH3 pins to the TI1 input (XOR combination). 2925:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not 2926:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * a timer instance provides an XOR input. 2927:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR2 TI1S LL_TIM_IC_EnableXORCombination 2928:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 2929:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 2930:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 2931:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_IC_EnableXORCombination(TIM_TypeDef *TIMx) 2932:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 2933:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** SET_BIT(TIMx->CR2, TIM_CR2_TI1S); 2934:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 2935:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 2936:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 2937:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Disconnect the TIMx_CH1, CH2 and CH3 pins from the TI1 input. 2938:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not 2939:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * a timer instance provides an XOR input. 2940:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR2 TI1S LL_TIM_IC_DisableXORCombination 2941:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 2942:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 2943:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 2944:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_IC_DisableXORCombination(TIM_TypeDef *TIMx) 2945:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 2946:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** CLEAR_BIT(TIMx->CR2, TIM_CR2_TI1S); 2947:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 2948:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 2949:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 2950:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Indicates whether the TIMx_CH1, CH2 and CH3 pins are connectected to the TI1 input. 2951:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not 2952:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * a timer instance provides an XOR input. 2953:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR2 TI1S LL_TIM_IC_IsEnabledXORCombination 2954:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 2955:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval State of bit (1 or 0). 2956:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 2957:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IC_IsEnabledXORCombination(const TIM_TypeDef *TIMx) 2958:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 2959:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return ((READ_BIT(TIMx->CR2, TIM_CR2_TI1S) == (TIM_CR2_TI1S)) ? 1UL : 0UL); 2960:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 2961:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 2962:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 2963:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Get captured value for input channel 1. 2964:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xF 2965:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check 2966:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * whether or not a timer instance supports a 32 bits counter. 2967:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not 2968:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * input channel 1 is supported by a timer instance. 2969:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCR1 CCR1 LL_TIM_IC_GetCaptureCH1 2970:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 2971:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval CapturedValue (between Min_Data=0 and Max_Data=65535) 2972:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 2973:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH1(const TIM_TypeDef *TIMx) 2974:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 2975:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return (uint32_t)(READ_REG(TIMx->CCR1)); 2976:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 2977:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 2978:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** ARM GAS /tmp/ccYgfTud.s page 289 2979:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Get captured value for input channel 2. 2980:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xF 2981:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check 2982:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * whether or not a timer instance supports a 32 bits counter. 2983:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not 2984:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * input channel 2 is supported by a timer instance. 2985:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCR2 CCR2 LL_TIM_IC_GetCaptureCH2 2986:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 2987:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval CapturedValue (between Min_Data=0 and Max_Data=65535) 2988:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 2989:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH2(const TIM_TypeDef *TIMx) 2990:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 2991:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return (uint32_t)(READ_REG(TIMx->CCR2)); 2992:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 2993:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 2994:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 2995:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Get captured value for input channel 3. 2996:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xF 2997:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check 2998:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * whether or not a timer instance supports a 32 bits counter. 2999:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not 3000:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * input channel 3 is supported by a timer instance. 3001:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCR3 CCR3 LL_TIM_IC_GetCaptureCH3 3002:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3003:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval CapturedValue (between Min_Data=0 and Max_Data=65535) 3004:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3005:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH3(const TIM_TypeDef *TIMx) 3006:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3007:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return (uint32_t)(READ_REG(TIMx->CCR3)); 3008:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3009:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3010:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3011:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Get captured value for input channel 4. 3012:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xF 3013:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check 3014:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * whether or not a timer instance supports a 32 bits counter. 3015:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not 3016:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * input channel 4 is supported by a timer instance. 3017:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCR4 CCR4 LL_TIM_IC_GetCaptureCH4 3018:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3019:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval CapturedValue (between Min_Data=0 and Max_Data=65535) 3020:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3021:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH4(const TIM_TypeDef *TIMx) 3022:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3023:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return (uint32_t)(READ_REG(TIMx->CCR4)); 3024:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3025:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3026:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3027:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} 3028:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3029:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3030:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EF_Clock_Selection Counter clock selection 3031:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ 3032:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3033:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3034:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Enable external clock mode 2. 3035:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note When external clock mode 2 is enabled the counter is clocked by any active edge on the ET ARM GAS /tmp/ccYgfTud.s page 290 3036:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check 3037:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * whether or not a timer instance supports external clock mode2. 3038:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SMCR ECE LL_TIM_EnableExternalClock 3039:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3040:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 3041:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3042:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_EnableExternalClock(TIM_TypeDef *TIMx) 3043:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3044:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** SET_BIT(TIMx->SMCR, TIM_SMCR_ECE); 3045:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3046:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3047:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3048:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Disable external clock mode 2. 3049:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check 3050:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * whether or not a timer instance supports external clock mode2. 3051:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SMCR ECE LL_TIM_DisableExternalClock 3052:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3053:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 3054:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3055:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_DisableExternalClock(TIM_TypeDef *TIMx) 3056:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3057:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** CLEAR_BIT(TIMx->SMCR, TIM_SMCR_ECE); 3058:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3059:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3060:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3061:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Indicate whether external clock mode 2 is enabled. 3062:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check 3063:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * whether or not a timer instance supports external clock mode2. 3064:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SMCR ECE LL_TIM_IsEnabledExternalClock 3065:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3066:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval State of bit (1 or 0). 3067:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3068:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsEnabledExternalClock(const TIM_TypeDef *TIMx) 3069:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3070:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return ((READ_BIT(TIMx->SMCR, TIM_SMCR_ECE) == (TIM_SMCR_ECE)) ? 1UL : 0UL); 3071:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3072:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3073:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3074:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Set the clock source of the counter clock. 3075:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note when selected clock source is external clock mode 1, the timer input 3076:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * the external clock is applied is selected by calling the @ref LL_TIM_SetTriggerInput() 3077:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * function. This timer input must be configured by calling 3078:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * the @ref LL_TIM_IC_Config() function. 3079:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(TIMx) can be used to check 3080:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * whether or not a timer instance supports external clock mode1. 3081:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check 3082:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * whether or not a timer instance supports external clock mode2. 3083:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SMCR SMS LL_TIM_SetClockSource\n 3084:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * SMCR ECE LL_TIM_SetClockSource 3085:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3086:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param ClockSource This parameter can be one of the following values: 3087:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CLOCKSOURCE_INTERNAL 3088:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE1 3089:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE2 3090:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 3091:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3092:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_SetClockSource(TIM_TypeDef *TIMx, uint32_t ClockSource) ARM GAS /tmp/ccYgfTud.s page 291 4244 .loc 5 3092 22 view .LVU1375 4245 .LBB466: 3093:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3094:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS | TIM_SMCR_ECE, ClockSource); 4246 .loc 5 3094 3 view .LVU1376 4247 006a 9968 ldr r1, [r3, #8] 4248 006c 0A4A ldr r2, .L199+16 4249 006e 0A40 ands r2, r2, r1 4250 0070 9A60 str r2, [r3, #8] 4251 .LVL369: 4252 .loc 5 3094 3 is_stmt 0 view .LVU1377 4253 .LBE466: 4254 .LBE465: 1393:Src/main.c **** LL_TIM_DisableMasterSlaveMode(TIM2); 4255 .loc 1 1393 3 is_stmt 1 view .LVU1378 4256 .LBB467: 4257 .LBI467: 3095:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3096:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3097:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3098:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Set the encoder interface mode. 3099:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx) can be used to check 3100:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * whether or not a timer instance supports the encoder mode. 3101:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SMCR SMS LL_TIM_SetEncoderMode 3102:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3103:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param EncoderMode This parameter can be one of the following values: 3104:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ENCODERMODE_X2_TI1 3105:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ENCODERMODE_X2_TI2 3106:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ENCODERMODE_X4_TI12 3107:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 3108:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3109:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_SetEncoderMode(TIM_TypeDef *TIMx, uint32_t EncoderMode) 3110:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3111:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, EncoderMode); 3112:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3113:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3114:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3115:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} 3116:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3117:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3118:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EF_Timer_Synchronization Timer synchronisation configuration 3119:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ 3120:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3121:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3122:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Set the trigger output (TRGO) used for timer synchronization . 3123:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_MASTER_INSTANCE(TIMx) can be used to check 3124:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * whether or not a timer instance can operate as a master timer. 3125:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR2 MMS LL_TIM_SetTriggerOutput 3126:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3127:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TimerSynchronization This parameter can be one of the following values: 3128:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TRGO_RESET 3129:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TRGO_ENABLE 3130:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TRGO_UPDATE 3131:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TRGO_CC1IF 3132:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TRGO_OC1REF 3133:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TRGO_OC2REF 3134:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TRGO_OC3REF ARM GAS /tmp/ccYgfTud.s page 292 3135:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TRGO_OC4REF 3136:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 3137:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3138:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_SetTriggerOutput(TIM_TypeDef *TIMx, uint32_t TimerSynchronization) 4258 .loc 5 3138 22 view .LVU1379 4259 .LBB468: 3139:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3140:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(TIMx->CR2, TIM_CR2_MMS, TimerSynchronization); 4260 .loc 5 3140 3 view .LVU1380 4261 0072 5A68 ldr r2, [r3, #4] 4262 0074 22F07002 bic r2, r2, #112 4263 0078 5A60 str r2, [r3, #4] 4264 .LVL370: 4265 .loc 5 3140 3 is_stmt 0 view .LVU1381 4266 .LBE468: 4267 .LBE467: 1394:Src/main.c **** /* USER CODE BEGIN TIM2_Init 2 */ 4268 .loc 1 1394 3 is_stmt 1 view .LVU1382 4269 .LBB469: 4270 .LBI469: 3141:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3142:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3143:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3144:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Set the trigger output 2 (TRGO2) used for ADC synchronization . 3145:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_TRGO2_INSTANCE(TIMx) can be used to check 3146:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * whether or not a timer instance can be used for ADC synchronization. 3147:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR2 MMS2 LL_TIM_SetTriggerOutput2 3148:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer Instance 3149:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param ADCSynchronization This parameter can be one of the following values: 3150:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TRGO2_RESET 3151:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TRGO2_ENABLE 3152:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TRGO2_UPDATE 3153:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TRGO2_CC1F 3154:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TRGO2_OC1 3155:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TRGO2_OC2 3156:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TRGO2_OC3 3157:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TRGO2_OC4 3158:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TRGO2_OC5 3159:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TRGO2_OC6 3160:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TRGO2_OC4_RISINGFALLING 3161:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TRGO2_OC6_RISINGFALLING 3162:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TRGO2_OC4_RISING_OC6_RISING 3163:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TRGO2_OC4_RISING_OC6_FALLING 3164:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TRGO2_OC5_RISING_OC6_RISING 3165:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TRGO2_OC5_RISING_OC6_FALLING 3166:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 3167:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3168:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_SetTriggerOutput2(TIM_TypeDef *TIMx, uint32_t ADCSynchronization) 3169:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3170:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(TIMx->CR2, TIM_CR2_MMS2, ADCSynchronization); 3171:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3172:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3173:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3174:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Set the synchronization mode of a slave timer. 3175:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not 3176:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * a timer instance can operate as a slave timer. 3177:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SMCR SMS LL_TIM_SetSlaveMode ARM GAS /tmp/ccYgfTud.s page 293 3178:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3179:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param SlaveMode This parameter can be one of the following values: 3180:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_SLAVEMODE_DISABLED 3181:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_SLAVEMODE_RESET 3182:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_SLAVEMODE_GATED 3183:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_SLAVEMODE_TRIGGER 3184:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_SLAVEMODE_COMBINED_RESETTRIGGER 3185:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 3186:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3187:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_SetSlaveMode(TIM_TypeDef *TIMx, uint32_t SlaveMode) 3188:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3189:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, SlaveMode); 3190:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3191:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3192:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3193:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Set the selects the trigger input to be used to synchronize the counter. 3194:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not 3195:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * a timer instance can operate as a slave timer. 3196:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SMCR TS LL_TIM_SetTriggerInput 3197:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3198:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TriggerInput This parameter can be one of the following values: 3199:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TS_ITR0 3200:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TS_ITR1 3201:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TS_ITR2 3202:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TS_ITR3 3203:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TS_TI1F_ED 3204:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TS_TI1FP1 3205:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TS_TI2FP2 3206:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TS_ETRF 3207:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 3208:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3209:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_SetTriggerInput(TIM_TypeDef *TIMx, uint32_t TriggerInput) 3210:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3211:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(TIMx->SMCR, TIM_SMCR_TS, TriggerInput); 3212:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3213:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3214:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3215:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Enable the Master/Slave mode. 3216:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not 3217:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * a timer instance can operate as a slave timer. 3218:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SMCR MSM LL_TIM_EnableMasterSlaveMode 3219:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3220:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 3221:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3222:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_EnableMasterSlaveMode(TIM_TypeDef *TIMx) 3223:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3224:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** SET_BIT(TIMx->SMCR, TIM_SMCR_MSM); 3225:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3226:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3227:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3228:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Disable the Master/Slave mode. 3229:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not 3230:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * a timer instance can operate as a slave timer. 3231:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SMCR MSM LL_TIM_DisableMasterSlaveMode 3232:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3233:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 3234:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ ARM GAS /tmp/ccYgfTud.s page 294 3235:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_DisableMasterSlaveMode(TIM_TypeDef *TIMx) 4271 .loc 5 3235 22 view .LVU1383 4272 .LBB470: 3236:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3237:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** CLEAR_BIT(TIMx->SMCR, TIM_SMCR_MSM); 4273 .loc 5 3237 3 view .LVU1384 4274 007a 9A68 ldr r2, [r3, #8] 4275 007c 22F08002 bic r2, r2, #128 4276 0080 9A60 str r2, [r3, #8] 4277 .LVL371: 4278 .loc 5 3237 3 is_stmt 0 view .LVU1385 4279 .LBE470: 4280 .LBE469: 1399:Src/main.c **** 4281 .loc 1 1399 1 view .LVU1386 4282 0082 06B0 add sp, sp, #24 4283 .LCFI43: 4284 .cfi_def_cfa_offset 8 4285 @ sp needed 4286 0084 10BD pop {r4, pc} 4287 .L200: 4288 0086 00BF .align 2 4289 .L199: 4290 0088 00380240 .word 1073887232 4291 008c 00ED00E0 .word -536810240 4292 0090 00E100E0 .word -536813312 4293 0094 40D10C00 .word 840000 4294 0098 F8BFFEFF .word -81928 4295 .cfi_endproc 4296 .LFE1195: 4298 .section .text.MX_TIM5_Init,"ax",%progbits 4299 .align 1 4300 .syntax unified 4301 .thumb 4302 .thumb_func 4304 MX_TIM5_Init: 4305 .LFB1197: 1466:Src/main.c **** 4306 .loc 1 1466 1 is_stmt 1 view -0 4307 .cfi_startproc 4308 @ args = 0, pretend = 0, frame = 24 4309 @ frame_needed = 0, uses_anonymous_args = 0 4310 0000 10B5 push {r4, lr} 4311 .LCFI44: 4312 .cfi_def_cfa_offset 8 4313 .cfi_offset 4, -8 4314 .cfi_offset 14, -4 4315 0002 86B0 sub sp, sp, #24 4316 .LCFI45: 4317 .cfi_def_cfa_offset 32 1472:Src/main.c **** 4318 .loc 1 1472 3 view .LVU1388 1472:Src/main.c **** 4319 .loc 1 1472 22 is_stmt 0 view .LVU1389 4320 0004 0024 movs r4, #0 4321 0006 0194 str r4, [sp, #4] 4322 0008 0294 str r4, [sp, #8] ARM GAS /tmp/ccYgfTud.s page 295 4323 000a 0394 str r4, [sp, #12] 4324 000c 0494 str r4, [sp, #16] 4325 000e 0594 str r4, [sp, #20] 1475:Src/main.c **** 4326 .loc 1 1475 3 is_stmt 1 view .LVU1390 4327 .LVL372: 4328 .LBB471: 4329 .LBI471: 1071:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { 4330 .loc 3 1071 22 view .LVU1391 4331 .LBB472: 1073:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** SET_BIT(RCC->APB1ENR, Periphs); 4332 .loc 3 1073 3 view .LVU1392 1074:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Delay after an RCC peripheral clock enabling */ 4333 .loc 3 1074 3 view .LVU1393 4334 0010 1C4B ldr r3, .L203 4335 0012 1A6C ldr r2, [r3, #64] 4336 0014 42F00802 orr r2, r2, #8 4337 0018 1A64 str r2, [r3, #64] 1076:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; 4338 .loc 3 1076 3 view .LVU1394 1076:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; 4339 .loc 3 1076 12 is_stmt 0 view .LVU1395 4340 001a 1B6C ldr r3, [r3, #64] 4341 001c 03F00803 and r3, r3, #8 1076:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; 4342 .loc 3 1076 10 view .LVU1396 4343 0020 0093 str r3, [sp] 1077:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } 4344 .loc 3 1077 3 is_stmt 1 view .LVU1397 4345 0022 009B ldr r3, [sp] 4346 .LVL373: 1077:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } 4347 .loc 3 1077 3 is_stmt 0 view .LVU1398 4348 .LBE472: 4349 .LBE471: 1478:Src/main.c **** NVIC_EnableIRQ(TIM5_IRQn); 4350 .loc 1 1478 3 is_stmt 1 view .LVU1399 4351 .LBB473: 4352 .LBI473: 1884:Drivers/CMSIS/Include/core_cm7.h **** { 4353 .loc 2 1884 26 view .LVU1400 4354 .LBB474: 1886:Drivers/CMSIS/Include/core_cm7.h **** } 4355 .loc 2 1886 3 view .LVU1401 1886:Drivers/CMSIS/Include/core_cm7.h **** } 4356 .loc 2 1886 26 is_stmt 0 view .LVU1402 4357 0024 184B ldr r3, .L203+4 4358 0026 D868 ldr r0, [r3, #12] 4359 .LBE474: 4360 .LBE473: 1478:Src/main.c **** NVIC_EnableIRQ(TIM5_IRQn); 4361 .loc 1 1478 3 discriminator 1 view .LVU1403 4362 0028 2246 mov r2, r4 4363 002a 2146 mov r1, r4 4364 002c C0F30220 ubfx r0, r0, #8, #3 4365 0030 FFF7FEFF bl NVIC_EncodePriority ARM GAS /tmp/ccYgfTud.s page 296 4366 .LVL374: 4367 .LBB475: 4368 .LBI475: 2024:Drivers/CMSIS/Include/core_cm7.h **** { 4369 .loc 2 2024 22 is_stmt 1 view .LVU1404 4370 .LBB476: 2026:Drivers/CMSIS/Include/core_cm7.h **** { 4371 .loc 2 2026 3 view .LVU1405 2028:Drivers/CMSIS/Include/core_cm7.h **** } 4372 .loc 2 2028 5 view .LVU1406 2028:Drivers/CMSIS/Include/core_cm7.h **** } 4373 .loc 2 2028 49 is_stmt 0 view .LVU1407 4374 0034 0001 lsls r0, r0, #4 4375 .LVL375: 2028:Drivers/CMSIS/Include/core_cm7.h **** } 4376 .loc 2 2028 49 view .LVU1408 4377 0036 C0B2 uxtb r0, r0 2028:Drivers/CMSIS/Include/core_cm7.h **** } 4378 .loc 2 2028 47 view .LVU1409 4379 0038 144B ldr r3, .L203+8 4380 003a 83F83203 strb r0, [r3, #818] 4381 .LVL376: 2028:Drivers/CMSIS/Include/core_cm7.h **** } 4382 .loc 2 2028 47 view .LVU1410 4383 .LBE476: 4384 .LBE475: 1479:Src/main.c **** 4385 .loc 1 1479 3 is_stmt 1 view .LVU1411 4386 .LBB477: 4387 .LBI477: 1896:Drivers/CMSIS/Include/core_cm7.h **** { 4388 .loc 2 1896 22 view .LVU1412 4389 .LBB478: 1898:Drivers/CMSIS/Include/core_cm7.h **** { 4390 .loc 2 1898 3 view .LVU1413 1900:Drivers/CMSIS/Include/core_cm7.h **** } 4391 .loc 2 1900 5 view .LVU1414 1900:Drivers/CMSIS/Include/core_cm7.h **** } 4392 .loc 2 1900 43 is_stmt 0 view .LVU1415 4393 003e 4FF48022 mov r2, #262144 4394 0042 5A60 str r2, [r3, #4] 4395 .LVL377: 1900:Drivers/CMSIS/Include/core_cm7.h **** } 4396 .loc 2 1900 43 view .LVU1416 4397 .LBE478: 4398 .LBE477: 1484:Src/main.c **** TIM_InitStruct.CounterMode = LL_TIM_COUNTERMODE_UP; 4399 .loc 1 1484 3 is_stmt 1 view .LVU1417 1484:Src/main.c **** TIM_InitStruct.CounterMode = LL_TIM_COUNTERMODE_UP; 4400 .loc 1 1484 28 is_stmt 0 view .LVU1418 4401 0044 42F21073 movw r3, #10000 4402 0048 ADF80430 strh r3, [sp, #4] @ movhi 1485:Src/main.c **** TIM_InitStruct.Autoreload = 560; 4403 .loc 1 1485 3 is_stmt 1 view .LVU1419 1485:Src/main.c **** TIM_InitStruct.Autoreload = 560; 4404 .loc 1 1485 30 is_stmt 0 view .LVU1420 4405 004c 0294 str r4, [sp, #8] ARM GAS /tmp/ccYgfTud.s page 297 1486:Src/main.c **** TIM_InitStruct.ClockDivision = LL_TIM_CLOCKDIVISION_DIV1; 4406 .loc 1 1486 3 is_stmt 1 view .LVU1421 1486:Src/main.c **** TIM_InitStruct.ClockDivision = LL_TIM_CLOCKDIVISION_DIV1; 4407 .loc 1 1486 29 is_stmt 0 view .LVU1422 4408 004e 4FF40C73 mov r3, #560 4409 0052 0393 str r3, [sp, #12] 1487:Src/main.c **** LL_TIM_Init(TIM5, &TIM_InitStruct); 4410 .loc 1 1487 3 is_stmt 1 view .LVU1423 1487:Src/main.c **** LL_TIM_Init(TIM5, &TIM_InitStruct); 4411 .loc 1 1487 32 is_stmt 0 view .LVU1424 4412 0054 0494 str r4, [sp, #16] 1488:Src/main.c **** LL_TIM_DisableARRPreload(TIM5); 4413 .loc 1 1488 3 is_stmt 1 view .LVU1425 4414 0056 0E4C ldr r4, .L203+12 4415 0058 01A9 add r1, sp, #4 4416 005a 2046 mov r0, r4 4417 005c FFF7FEFF bl LL_TIM_Init 4418 .LVL378: 1489:Src/main.c **** LL_TIM_SetClockSource(TIM5, LL_TIM_CLOCKSOURCE_INTERNAL); 4419 .loc 1 1489 3 view .LVU1426 4420 .LBB479: 4421 .LBI479: 1504:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 4422 .loc 5 1504 22 view .LVU1427 4423 .LBB480: 1506:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 4424 .loc 5 1506 3 view .LVU1428 4425 0060 2368 ldr r3, [r4] 4426 0062 23F08003 bic r3, r3, #128 4427 0066 2360 str r3, [r4] 4428 .LVL379: 1506:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 4429 .loc 5 1506 3 is_stmt 0 view .LVU1429 4430 .LBE480: 4431 .LBE479: 1490:Src/main.c **** LL_TIM_SetTriggerOutput(TIM5, LL_TIM_TRGO_RESET); 4432 .loc 1 1490 3 is_stmt 1 view .LVU1430 4433 .LBB481: 4434 .LBI481: 3092:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 4435 .loc 5 3092 22 view .LVU1431 4436 .LBB482: 3094:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 4437 .loc 5 3094 3 view .LVU1432 4438 0068 A268 ldr r2, [r4, #8] 4439 006a 0A4B ldr r3, .L203+16 4440 006c 1340 ands r3, r3, r2 4441 006e A360 str r3, [r4, #8] 4442 .LVL380: 3094:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 4443 .loc 5 3094 3 is_stmt 0 view .LVU1433 4444 .LBE482: 4445 .LBE481: 1491:Src/main.c **** LL_TIM_DisableMasterSlaveMode(TIM5); 4446 .loc 1 1491 3 is_stmt 1 view .LVU1434 4447 .LBB483: 4448 .LBI483: ARM GAS /tmp/ccYgfTud.s page 298 3138:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 4449 .loc 5 3138 22 view .LVU1435 4450 .LBB484: 3140:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 4451 .loc 5 3140 3 view .LVU1436 4452 0070 6368 ldr r3, [r4, #4] 4453 0072 23F07003 bic r3, r3, #112 4454 0076 6360 str r3, [r4, #4] 4455 .LVL381: 3140:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 4456 .loc 5 3140 3 is_stmt 0 view .LVU1437 4457 .LBE484: 4458 .LBE483: 1492:Src/main.c **** /* USER CODE BEGIN TIM5_Init 2 */ 4459 .loc 1 1492 3 is_stmt 1 view .LVU1438 4460 .LBB485: 4461 .LBI485: 3235:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 4462 .loc 5 3235 22 view .LVU1439 4463 .LBB486: 4464 .loc 5 3237 3 view .LVU1440 4465 0078 A368 ldr r3, [r4, #8] 4466 007a 23F08003 bic r3, r3, #128 4467 007e A360 str r3, [r4, #8] 4468 .LVL382: 4469 .loc 5 3237 3 is_stmt 0 view .LVU1441 4470 .LBE486: 4471 .LBE485: 1497:Src/main.c **** 4472 .loc 1 1497 1 view .LVU1442 4473 0080 06B0 add sp, sp, #24 4474 .LCFI46: 4475 .cfi_def_cfa_offset 8 4476 @ sp needed 4477 0082 10BD pop {r4, pc} 4478 .L204: 4479 .align 2 4480 .L203: 4481 0084 00380240 .word 1073887232 4482 0088 00ED00E0 .word -536810240 4483 008c 00E100E0 .word -536813312 4484 0090 000C0040 .word 1073744896 4485 0094 F8BFFEFF .word -81928 4486 .cfi_endproc 4487 .LFE1197: 4489 .section .text.MX_TIM7_Init,"ax",%progbits 4490 .align 1 4491 .syntax unified 4492 .thumb 4493 .thumb_func 4495 MX_TIM7_Init: 4496 .LFB1199: 1542:Src/main.c **** 4497 .loc 1 1542 1 is_stmt 1 view -0 4498 .cfi_startproc 4499 @ args = 0, pretend = 0, frame = 24 4500 @ frame_needed = 0, uses_anonymous_args = 0 ARM GAS /tmp/ccYgfTud.s page 299 4501 0000 10B5 push {r4, lr} 4502 .LCFI47: 4503 .cfi_def_cfa_offset 8 4504 .cfi_offset 4, -8 4505 .cfi_offset 14, -4 4506 0002 86B0 sub sp, sp, #24 4507 .LCFI48: 4508 .cfi_def_cfa_offset 32 1548:Src/main.c **** 4509 .loc 1 1548 3 view .LVU1444 1548:Src/main.c **** 4510 .loc 1 1548 22 is_stmt 0 view .LVU1445 4511 0004 0024 movs r4, #0 4512 0006 0194 str r4, [sp, #4] 4513 0008 0294 str r4, [sp, #8] 4514 000a 0394 str r4, [sp, #12] 4515 000c 0494 str r4, [sp, #16] 4516 000e 0594 str r4, [sp, #20] 1551:Src/main.c **** 4517 .loc 1 1551 3 is_stmt 1 view .LVU1446 4518 .LVL383: 4519 .LBB487: 4520 .LBI487: 1071:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { 4521 .loc 3 1071 22 view .LVU1447 4522 .LBB488: 1073:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** SET_BIT(RCC->APB1ENR, Periphs); 4523 .loc 3 1073 3 view .LVU1448 1074:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Delay after an RCC peripheral clock enabling */ 4524 .loc 3 1074 3 view .LVU1449 4525 0010 1A4B ldr r3, .L207 4526 0012 1A6C ldr r2, [r3, #64] 4527 0014 42F02002 orr r2, r2, #32 4528 0018 1A64 str r2, [r3, #64] 1076:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; 4529 .loc 3 1076 3 view .LVU1450 1076:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; 4530 .loc 3 1076 12 is_stmt 0 view .LVU1451 4531 001a 1B6C ldr r3, [r3, #64] 4532 001c 03F02003 and r3, r3, #32 1076:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; 4533 .loc 3 1076 10 view .LVU1452 4534 0020 0093 str r3, [sp] 1077:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } 4535 .loc 3 1077 3 is_stmt 1 view .LVU1453 4536 0022 009B ldr r3, [sp] 4537 .LVL384: 1077:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } 4538 .loc 3 1077 3 is_stmt 0 view .LVU1454 4539 .LBE488: 4540 .LBE487: 1554:Src/main.c **** NVIC_EnableIRQ(TIM7_IRQn); 4541 .loc 1 1554 3 is_stmt 1 view .LVU1455 4542 .LBB489: 4543 .LBI489: 1884:Drivers/CMSIS/Include/core_cm7.h **** { 4544 .loc 2 1884 26 view .LVU1456 ARM GAS /tmp/ccYgfTud.s page 300 4545 .LBB490: 1886:Drivers/CMSIS/Include/core_cm7.h **** } 4546 .loc 2 1886 3 view .LVU1457 1886:Drivers/CMSIS/Include/core_cm7.h **** } 4547 .loc 2 1886 26 is_stmt 0 view .LVU1458 4548 0024 164B ldr r3, .L207+4 4549 0026 D868 ldr r0, [r3, #12] 4550 .LBE490: 4551 .LBE489: 1554:Src/main.c **** NVIC_EnableIRQ(TIM7_IRQn); 4552 .loc 1 1554 3 discriminator 1 view .LVU1459 4553 0028 2246 mov r2, r4 4554 002a 2146 mov r1, r4 4555 002c C0F30220 ubfx r0, r0, #8, #3 4556 0030 FFF7FEFF bl NVIC_EncodePriority 4557 .LVL385: 4558 .LBB491: 4559 .LBI491: 2024:Drivers/CMSIS/Include/core_cm7.h **** { 4560 .loc 2 2024 22 is_stmt 1 view .LVU1460 4561 .LBB492: 2026:Drivers/CMSIS/Include/core_cm7.h **** { 4562 .loc 2 2026 3 view .LVU1461 2028:Drivers/CMSIS/Include/core_cm7.h **** } 4563 .loc 2 2028 5 view .LVU1462 2028:Drivers/CMSIS/Include/core_cm7.h **** } 4564 .loc 2 2028 49 is_stmt 0 view .LVU1463 4565 0034 0001 lsls r0, r0, #4 4566 .LVL386: 2028:Drivers/CMSIS/Include/core_cm7.h **** } 4567 .loc 2 2028 49 view .LVU1464 4568 0036 C0B2 uxtb r0, r0 2028:Drivers/CMSIS/Include/core_cm7.h **** } 4569 .loc 2 2028 47 view .LVU1465 4570 0038 124B ldr r3, .L207+8 4571 003a 83F83703 strb r0, [r3, #823] 4572 .LVL387: 2028:Drivers/CMSIS/Include/core_cm7.h **** } 4573 .loc 2 2028 47 view .LVU1466 4574 .LBE492: 4575 .LBE491: 1555:Src/main.c **** 4576 .loc 1 1555 3 is_stmt 1 view .LVU1467 4577 .LBB493: 4578 .LBI493: 1896:Drivers/CMSIS/Include/core_cm7.h **** { 4579 .loc 2 1896 22 view .LVU1468 4580 .LBB494: 1898:Drivers/CMSIS/Include/core_cm7.h **** { 4581 .loc 2 1898 3 view .LVU1469 1900:Drivers/CMSIS/Include/core_cm7.h **** } 4582 .loc 2 1900 5 view .LVU1470 1900:Drivers/CMSIS/Include/core_cm7.h **** } 4583 .loc 2 1900 43 is_stmt 0 view .LVU1471 4584 003e 4FF40002 mov r2, #8388608 4585 0042 5A60 str r2, [r3, #4] 4586 .LVL388: ARM GAS /tmp/ccYgfTud.s page 301 1900:Drivers/CMSIS/Include/core_cm7.h **** } 4587 .loc 2 1900 43 view .LVU1472 4588 .LBE494: 4589 .LBE493: 1560:Src/main.c **** TIM_InitStruct.CounterMode = LL_TIM_COUNTERMODE_UP; 4590 .loc 1 1560 3 is_stmt 1 view .LVU1473 1560:Src/main.c **** TIM_InitStruct.CounterMode = LL_TIM_COUNTERMODE_UP; 4591 .loc 1 1560 28 is_stmt 0 view .LVU1474 4592 0044 40F29733 movw r3, #919 4593 0048 ADF80430 strh r3, [sp, #4] @ movhi 1561:Src/main.c **** TIM_InitStruct.Autoreload = 99; 4594 .loc 1 1561 3 is_stmt 1 view .LVU1475 1561:Src/main.c **** TIM_InitStruct.Autoreload = 99; 4595 .loc 1 1561 30 is_stmt 0 view .LVU1476 4596 004c 0294 str r4, [sp, #8] 1562:Src/main.c **** LL_TIM_Init(TIM7, &TIM_InitStruct); 4597 .loc 1 1562 3 is_stmt 1 view .LVU1477 1562:Src/main.c **** LL_TIM_Init(TIM7, &TIM_InitStruct); 4598 .loc 1 1562 29 is_stmt 0 view .LVU1478 4599 004e 6323 movs r3, #99 4600 0050 0393 str r3, [sp, #12] 1563:Src/main.c **** LL_TIM_DisableARRPreload(TIM7); 4601 .loc 1 1563 3 is_stmt 1 view .LVU1479 4602 0052 0D4C ldr r4, .L207+12 4603 0054 01A9 add r1, sp, #4 4604 0056 2046 mov r0, r4 4605 0058 FFF7FEFF bl LL_TIM_Init 4606 .LVL389: 1564:Src/main.c **** LL_TIM_SetTriggerOutput(TIM7, LL_TIM_TRGO_ENABLE); 4607 .loc 1 1564 3 view .LVU1480 4608 .LBB495: 4609 .LBI495: 1504:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 4610 .loc 5 1504 22 view .LVU1481 4611 .LBB496: 1506:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 4612 .loc 5 1506 3 view .LVU1482 4613 005c 2368 ldr r3, [r4] 4614 005e 23F08003 bic r3, r3, #128 4615 0062 2360 str r3, [r4] 4616 .LVL390: 1506:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 4617 .loc 5 1506 3 is_stmt 0 view .LVU1483 4618 .LBE496: 4619 .LBE495: 1565:Src/main.c **** LL_TIM_DisableMasterSlaveMode(TIM7); 4620 .loc 1 1565 3 is_stmt 1 view .LVU1484 4621 .LBB497: 4622 .LBI497: 3138:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 4623 .loc 5 3138 22 view .LVU1485 4624 .LBB498: 3140:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 4625 .loc 5 3140 3 view .LVU1486 4626 0064 6368 ldr r3, [r4, #4] 4627 0066 23F07003 bic r3, r3, #112 4628 006a 43F01003 orr r3, r3, #16 ARM GAS /tmp/ccYgfTud.s page 302 4629 006e 6360 str r3, [r4, #4] 4630 .LVL391: 3140:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 4631 .loc 5 3140 3 is_stmt 0 view .LVU1487 4632 .LBE498: 4633 .LBE497: 1566:Src/main.c **** /* USER CODE BEGIN TIM7_Init 2 */ 4634 .loc 1 1566 3 is_stmt 1 view .LVU1488 4635 .LBB499: 4636 .LBI499: 3235:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 4637 .loc 5 3235 22 view .LVU1489 4638 .LBB500: 4639 .loc 5 3237 3 view .LVU1490 4640 0070 A368 ldr r3, [r4, #8] 4641 0072 23F08003 bic r3, r3, #128 4642 0076 A360 str r3, [r4, #8] 4643 .LVL392: 4644 .loc 5 3237 3 is_stmt 0 view .LVU1491 4645 .LBE500: 4646 .LBE499: 1571:Src/main.c **** 4647 .loc 1 1571 1 view .LVU1492 4648 0078 06B0 add sp, sp, #24 4649 .LCFI49: 4650 .cfi_def_cfa_offset 8 4651 @ sp needed 4652 007a 10BD pop {r4, pc} 4653 .L208: 4654 .align 2 4655 .L207: 4656 007c 00380240 .word 1073887232 4657 0080 00ED00E0 .word -536810240 4658 0084 00E100E0 .word -536813312 4659 0088 00140040 .word 1073746944 4660 .cfi_endproc 4661 .LFE1199: 4663 .section .text.MX_TIM6_Init,"ax",%progbits 4664 .align 1 4665 .syntax unified 4666 .thumb 4667 .thumb_func 4669 MX_TIM6_Init: 4670 .LFB1198: 1505:Src/main.c **** 4671 .loc 1 1505 1 is_stmt 1 view -0 4672 .cfi_startproc 4673 @ args = 0, pretend = 0, frame = 24 4674 @ frame_needed = 0, uses_anonymous_args = 0 4675 0000 10B5 push {r4, lr} 4676 .LCFI50: 4677 .cfi_def_cfa_offset 8 4678 .cfi_offset 4, -8 4679 .cfi_offset 14, -4 4680 0002 86B0 sub sp, sp, #24 4681 .LCFI51: 4682 .cfi_def_cfa_offset 32 ARM GAS /tmp/ccYgfTud.s page 303 1511:Src/main.c **** 4683 .loc 1 1511 3 view .LVU1494 1511:Src/main.c **** 4684 .loc 1 1511 22 is_stmt 0 view .LVU1495 4685 0004 0024 movs r4, #0 4686 0006 0194 str r4, [sp, #4] 4687 0008 0294 str r4, [sp, #8] 4688 000a 0394 str r4, [sp, #12] 4689 000c 0494 str r4, [sp, #16] 4690 000e 0594 str r4, [sp, #20] 1514:Src/main.c **** 4691 .loc 1 1514 3 is_stmt 1 view .LVU1496 4692 .LVL393: 4693 .LBB501: 4694 .LBI501: 1071:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { 4695 .loc 3 1071 22 view .LVU1497 4696 .LBB502: 1073:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** SET_BIT(RCC->APB1ENR, Periphs); 4697 .loc 3 1073 3 view .LVU1498 1074:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Delay after an RCC peripheral clock enabling */ 4698 .loc 3 1074 3 view .LVU1499 4699 0010 1A4B ldr r3, .L211 4700 0012 1A6C ldr r2, [r3, #64] 4701 0014 42F01002 orr r2, r2, #16 4702 0018 1A64 str r2, [r3, #64] 1076:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; 4703 .loc 3 1076 3 view .LVU1500 1076:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; 4704 .loc 3 1076 12 is_stmt 0 view .LVU1501 4705 001a 1B6C ldr r3, [r3, #64] 4706 001c 03F01003 and r3, r3, #16 1076:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; 4707 .loc 3 1076 10 view .LVU1502 4708 0020 0093 str r3, [sp] 1077:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } 4709 .loc 3 1077 3 is_stmt 1 view .LVU1503 4710 0022 009B ldr r3, [sp] 4711 .LVL394: 1077:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } 4712 .loc 3 1077 3 is_stmt 0 view .LVU1504 4713 .LBE502: 4714 .LBE501: 1517:Src/main.c **** NVIC_EnableIRQ(TIM6_DAC_IRQn); 4715 .loc 1 1517 3 is_stmt 1 view .LVU1505 4716 .LBB503: 4717 .LBI503: 1884:Drivers/CMSIS/Include/core_cm7.h **** { 4718 .loc 2 1884 26 view .LVU1506 4719 .LBB504: 1886:Drivers/CMSIS/Include/core_cm7.h **** } 4720 .loc 2 1886 3 view .LVU1507 1886:Drivers/CMSIS/Include/core_cm7.h **** } 4721 .loc 2 1886 26 is_stmt 0 view .LVU1508 4722 0024 164B ldr r3, .L211+4 4723 0026 D868 ldr r0, [r3, #12] 4724 .LBE504: ARM GAS /tmp/ccYgfTud.s page 304 4725 .LBE503: 1517:Src/main.c **** NVIC_EnableIRQ(TIM6_DAC_IRQn); 4726 .loc 1 1517 3 discriminator 1 view .LVU1509 4727 0028 2246 mov r2, r4 4728 002a 2146 mov r1, r4 4729 002c C0F30220 ubfx r0, r0, #8, #3 4730 0030 FFF7FEFF bl NVIC_EncodePriority 4731 .LVL395: 4732 .LBB505: 4733 .LBI505: 2024:Drivers/CMSIS/Include/core_cm7.h **** { 4734 .loc 2 2024 22 is_stmt 1 view .LVU1510 4735 .LBB506: 2026:Drivers/CMSIS/Include/core_cm7.h **** { 4736 .loc 2 2026 3 view .LVU1511 2028:Drivers/CMSIS/Include/core_cm7.h **** } 4737 .loc 2 2028 5 view .LVU1512 2028:Drivers/CMSIS/Include/core_cm7.h **** } 4738 .loc 2 2028 49 is_stmt 0 view .LVU1513 4739 0034 0001 lsls r0, r0, #4 4740 .LVL396: 2028:Drivers/CMSIS/Include/core_cm7.h **** } 4741 .loc 2 2028 49 view .LVU1514 4742 0036 C0B2 uxtb r0, r0 2028:Drivers/CMSIS/Include/core_cm7.h **** } 4743 .loc 2 2028 47 view .LVU1515 4744 0038 124B ldr r3, .L211+8 4745 003a 83F83603 strb r0, [r3, #822] 4746 .LVL397: 2028:Drivers/CMSIS/Include/core_cm7.h **** } 4747 .loc 2 2028 47 view .LVU1516 4748 .LBE506: 4749 .LBE505: 1518:Src/main.c **** 4750 .loc 1 1518 3 is_stmt 1 view .LVU1517 4751 .LBB507: 4752 .LBI507: 1896:Drivers/CMSIS/Include/core_cm7.h **** { 4753 .loc 2 1896 22 view .LVU1518 4754 .LBB508: 1898:Drivers/CMSIS/Include/core_cm7.h **** { 4755 .loc 2 1898 3 view .LVU1519 1900:Drivers/CMSIS/Include/core_cm7.h **** } 4756 .loc 2 1900 5 view .LVU1520 1900:Drivers/CMSIS/Include/core_cm7.h **** } 4757 .loc 2 1900 43 is_stmt 0 view .LVU1521 4758 003e 4FF48002 mov r2, #4194304 4759 0042 5A60 str r2, [r3, #4] 4760 .LVL398: 1900:Drivers/CMSIS/Include/core_cm7.h **** } 4761 .loc 2 1900 43 view .LVU1522 4762 .LBE508: 4763 .LBE507: 1523:Src/main.c **** TIM_InitStruct.CounterMode = LL_TIM_COUNTERMODE_UP; 4764 .loc 1 1523 3 is_stmt 1 view .LVU1523 1523:Src/main.c **** TIM_InitStruct.CounterMode = LL_TIM_COUNTERMODE_UP; 4765 .loc 1 1523 28 is_stmt 0 view .LVU1524 ARM GAS /tmp/ccYgfTud.s page 305 4766 0044 4BF2AF33 movw r3, #45999 4767 0048 ADF80430 strh r3, [sp, #4] @ movhi 1524:Src/main.c **** TIM_InitStruct.Autoreload = 19; 4768 .loc 1 1524 3 is_stmt 1 view .LVU1525 1524:Src/main.c **** TIM_InitStruct.Autoreload = 19; 4769 .loc 1 1524 30 is_stmt 0 view .LVU1526 4770 004c 0294 str r4, [sp, #8] 1525:Src/main.c **** LL_TIM_Init(TIM6, &TIM_InitStruct); 4771 .loc 1 1525 3 is_stmt 1 view .LVU1527 1525:Src/main.c **** LL_TIM_Init(TIM6, &TIM_InitStruct); 4772 .loc 1 1525 29 is_stmt 0 view .LVU1528 4773 004e 1323 movs r3, #19 4774 0050 0393 str r3, [sp, #12] 1526:Src/main.c **** LL_TIM_DisableARRPreload(TIM6); 4775 .loc 1 1526 3 is_stmt 1 view .LVU1529 4776 0052 0D4C ldr r4, .L211+12 4777 0054 01A9 add r1, sp, #4 4778 0056 2046 mov r0, r4 4779 0058 FFF7FEFF bl LL_TIM_Init 4780 .LVL399: 1527:Src/main.c **** LL_TIM_SetTriggerOutput(TIM6, LL_TIM_TRGO_ENABLE); 4781 .loc 1 1527 3 view .LVU1530 4782 .LBB509: 4783 .LBI509: 1504:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 4784 .loc 5 1504 22 view .LVU1531 4785 .LBB510: 1506:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 4786 .loc 5 1506 3 view .LVU1532 4787 005c 2368 ldr r3, [r4] 4788 005e 23F08003 bic r3, r3, #128 4789 0062 2360 str r3, [r4] 4790 .LVL400: 1506:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 4791 .loc 5 1506 3 is_stmt 0 view .LVU1533 4792 .LBE510: 4793 .LBE509: 1528:Src/main.c **** LL_TIM_DisableMasterSlaveMode(TIM6); 4794 .loc 1 1528 3 is_stmt 1 view .LVU1534 4795 .LBB511: 4796 .LBI511: 3138:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 4797 .loc 5 3138 22 view .LVU1535 4798 .LBB512: 3140:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 4799 .loc 5 3140 3 view .LVU1536 4800 0064 6368 ldr r3, [r4, #4] 4801 0066 23F07003 bic r3, r3, #112 4802 006a 43F01003 orr r3, r3, #16 4803 006e 6360 str r3, [r4, #4] 4804 .LVL401: 3140:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 4805 .loc 5 3140 3 is_stmt 0 view .LVU1537 4806 .LBE512: 4807 .LBE511: 1529:Src/main.c **** /* USER CODE BEGIN TIM6_Init 2 */ 4808 .loc 1 1529 3 is_stmt 1 view .LVU1538 ARM GAS /tmp/ccYgfTud.s page 306 4809 .LBB513: 4810 .LBI513: 3235:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 4811 .loc 5 3235 22 view .LVU1539 4812 .LBB514: 4813 .loc 5 3237 3 view .LVU1540 4814 0070 A368 ldr r3, [r4, #8] 4815 0072 23F08003 bic r3, r3, #128 4816 0076 A360 str r3, [r4, #8] 4817 .LVL402: 4818 .loc 5 3237 3 is_stmt 0 view .LVU1541 4819 .LBE514: 4820 .LBE513: 1534:Src/main.c **** 4821 .loc 1 1534 1 view .LVU1542 4822 0078 06B0 add sp, sp, #24 4823 .LCFI52: 4824 .cfi_def_cfa_offset 8 4825 @ sp needed 4826 007a 10BD pop {r4, pc} 4827 .L212: 4828 .align 2 4829 .L211: 4830 007c 00380240 .word 1073887232 4831 0080 00ED00E0 .word -536810240 4832 0084 00E100E0 .word -536813312 4833 0088 00100040 .word 1073745920 4834 .cfi_endproc 4835 .LFE1198: 4837 .section .rodata.Init_params.str1.4,"aMS",%progbits,1 4838 .align 2 4839 .LC0: 4840 0000 2F00 .ascii "/\000" 4841 0002 0000 .align 2 4842 .LC1: 4843 0004 434F4D4D .ascii "COMMAND.TXT\000" 4843 414E442E 4843 54585400 4844 .section .text.Init_params,"ax",%progbits 4845 .align 1 4846 .syntax unified 4847 .thumb 4848 .thumb_func 4850 Init_params: 4851 .LFB1207: 2004:Src/main.c **** TO6 = 0; 4852 .loc 1 2004 1 is_stmt 1 view -0 4853 .cfi_startproc 4854 @ args = 0, pretend = 0, frame = 0 4855 @ frame_needed = 0, uses_anonymous_args = 0 4856 0000 2DE9F041 push {r4, r5, r6, r7, r8, lr} 4857 .LCFI53: 4858 .cfi_def_cfa_offset 24 4859 .cfi_offset 4, -24 4860 .cfi_offset 5, -20 4861 .cfi_offset 6, -16 4862 .cfi_offset 7, -12 ARM GAS /tmp/ccYgfTud.s page 307 4863 .cfi_offset 8, -8 4864 .cfi_offset 14, -4 2005:Src/main.c **** TO7 = 0; 4865 .loc 1 2005 2 view .LVU1544 2005:Src/main.c **** TO7 = 0; 4866 .loc 1 2005 6 is_stmt 0 view .LVU1545 4867 0004 0023 movs r3, #0 4868 0006 9F4A ldr r2, .L225 4869 0008 1360 str r3, [r2] 2006:Src/main.c **** TO7_before = 0; 4870 .loc 1 2006 2 is_stmt 1 view .LVU1546 2006:Src/main.c **** TO7_before = 0; 4871 .loc 1 2006 6 is_stmt 0 view .LVU1547 4872 000a 9F4A ldr r2, .L225+4 4873 000c 1360 str r3, [r2] 2007:Src/main.c **** TO6_before = 0; 4874 .loc 1 2007 2 is_stmt 1 view .LVU1548 2007:Src/main.c **** TO6_before = 0; 4875 .loc 1 2007 13 is_stmt 0 view .LVU1549 4876 000e 9F4A ldr r2, .L225+8 4877 0010 1360 str r3, [r2] 2008:Src/main.c **** TO6_uart = 0; 4878 .loc 1 2008 2 is_stmt 1 view .LVU1550 2008:Src/main.c **** TO6_uart = 0; 4879 .loc 1 2008 13 is_stmt 0 view .LVU1551 4880 0012 9F4A ldr r2, .L225+12 4881 0014 1360 str r3, [r2] 2009:Src/main.c **** flg_tmt = 0; 4882 .loc 1 2009 2 is_stmt 1 view .LVU1552 2009:Src/main.c **** flg_tmt = 0; 4883 .loc 1 2009 11 is_stmt 0 view .LVU1553 4884 0016 9F4A ldr r2, .L225+16 4885 0018 1360 str r3, [r2] 2010:Src/main.c **** UART_rec_incr = 0; 4886 .loc 1 2010 2 is_stmt 1 view .LVU1554 2010:Src/main.c **** UART_rec_incr = 0; 4887 .loc 1 2010 10 is_stmt 0 view .LVU1555 4888 001a 9F4A ldr r2, .L225+20 4889 001c 1370 strb r3, [r2] 2011:Src/main.c **** fgoto = 0; 4890 .loc 1 2011 2 is_stmt 1 view .LVU1556 2011:Src/main.c **** fgoto = 0; 4891 .loc 1 2011 16 is_stmt 0 view .LVU1557 4892 001e 9F4A ldr r2, .L225+24 4893 0020 1380 strh r3, [r2] @ movhi 2012:Src/main.c **** sizeoffile = 0; 4894 .loc 1 2012 2 is_stmt 1 view .LVU1558 2012:Src/main.c **** sizeoffile = 0; 4895 .loc 1 2012 8 is_stmt 0 view .LVU1559 4896 0022 9F4A ldr r2, .L225+28 4897 0024 1360 str r3, [r2] 2013:Src/main.c **** u_tx_flg = 0; 4898 .loc 1 2013 2 is_stmt 1 view .LVU1560 2013:Src/main.c **** u_tx_flg = 0; 4899 .loc 1 2013 13 is_stmt 0 view .LVU1561 4900 0026 9F4A ldr r2, .L225+32 4901 0028 1360 str r3, [r2] ARM GAS /tmp/ccYgfTud.s page 308 2014:Src/main.c **** u_rx_flg = 0; 4902 .loc 1 2014 2 is_stmt 1 view .LVU1562 2014:Src/main.c **** u_rx_flg = 0; 4903 .loc 1 2014 11 is_stmt 0 view .LVU1563 4904 002a 9F4A ldr r2, .L225+36 4905 002c 1370 strb r3, [r2] 2015:Src/main.c **** //State_Data[0]=0; 4906 .loc 1 2015 2 is_stmt 1 view .LVU1564 2015:Src/main.c **** //State_Data[0]=0; 4907 .loc 1 2015 11 is_stmt 0 view .LVU1565 4908 002e 9F4A ldr r2, .L225+40 4909 0030 1370 strb r3, [r2] 2018:Src/main.c **** { 4910 .loc 1 2018 2 is_stmt 1 view .LVU1566 4911 .LBB515: 2018:Src/main.c **** { 4912 .loc 1 2018 7 view .LVU1567 4913 .LVL403: 2018:Src/main.c **** { 4914 .loc 1 2018 2 is_stmt 0 view .LVU1568 4915 0032 05E0 b .L214 4916 .LVL404: 4917 .L215: 2020:Src/main.c **** } 4918 .loc 1 2020 3 is_stmt 1 view .LVU1569 2020:Src/main.c **** } 4919 .loc 1 2020 16 is_stmt 0 view .LVU1570 4920 0034 9E4A ldr r2, .L225+44 4921 0036 0021 movs r1, #0 4922 0038 22F81310 strh r1, [r2, r3, lsl #1] @ movhi 2018:Src/main.c **** { 4923 .loc 1 2018 31 is_stmt 1 discriminator 3 view .LVU1571 4924 003c 0133 adds r3, r3, #1 4925 .LVL405: 2018:Src/main.c **** { 4926 .loc 1 2018 31 is_stmt 0 discriminator 3 view .LVU1572 4927 003e 9BB2 uxth r3, r3 4928 .LVL406: 4929 .L214: 2018:Src/main.c **** { 4930 .loc 1 2018 22 is_stmt 1 discriminator 1 view .LVU1573 4931 0040 0E2B cmp r3, #14 4932 0042 F7D9 bls .L215 4933 .LBE515: 2022:Src/main.c **** 4934 .loc 1 2022 2 view .LVU1574 2022:Src/main.c **** 4935 .loc 1 2022 14 is_stmt 0 view .LVU1575 4936 0044 9A4B ldr r3, .L225+44 4937 .LVL407: 2022:Src/main.c **** 4938 .loc 1 2022 14 view .LVU1576 4939 0046 41F21112 movw r2, #4369 4940 004a 1A80 strh r2, [r3] @ movhi 2025:Src/main.c **** Def_setup.LD1_EN = 0; 4941 .loc 1 2025 2 is_stmt 1 view .LVU1577 2025:Src/main.c **** Def_setup.LD1_EN = 0; ARM GAS /tmp/ccYgfTud.s page 309 4942 .loc 1 2025 21 is_stmt 0 view .LVU1578 4943 004c 994B ldr r3, .L225+48 4944 004e 0022 movs r2, #0 4945 0050 DA81 strh r2, [r3, #14] @ movhi 2026:Src/main.c **** Def_setup.LD2_EN = 0; 4946 .loc 1 2026 2 is_stmt 1 view .LVU1579 2026:Src/main.c **** Def_setup.LD2_EN = 0; 4947 .loc 1 2026 19 is_stmt 0 view .LVU1580 4948 0052 DA70 strb r2, [r3, #3] 2027:Src/main.c **** Def_setup.MES_ID = 0; 4949 .loc 1 2027 2 is_stmt 1 view .LVU1581 2027:Src/main.c **** Def_setup.MES_ID = 0; 4950 .loc 1 2027 19 is_stmt 0 view .LVU1582 4951 0054 1A71 strb r2, [r3, #4] 2028:Src/main.c **** Def_setup.PI1_RD = 0; 4952 .loc 1 2028 2 is_stmt 1 view .LVU1583 2028:Src/main.c **** Def_setup.PI1_RD = 0; 4953 .loc 1 2028 19 is_stmt 0 view .LVU1584 4954 0056 1A82 strh r2, [r3, #16] @ movhi 2029:Src/main.c **** Def_setup.PI2_RD = 0; 4955 .loc 1 2029 2 is_stmt 1 view .LVU1585 2029:Src/main.c **** Def_setup.PI2_RD = 0; 4956 .loc 1 2029 19 is_stmt 0 view .LVU1586 4957 0058 1A73 strb r2, [r3, #12] 2030:Src/main.c **** Def_setup.REF1_EN = 0; 4958 .loc 1 2030 2 is_stmt 1 view .LVU1587 2030:Src/main.c **** Def_setup.REF1_EN = 0; 4959 .loc 1 2030 19 is_stmt 0 view .LVU1588 4960 005a 5A73 strb r2, [r3, #13] 2031:Src/main.c **** Def_setup.REF2_EN = 0; 4961 .loc 1 2031 2 is_stmt 1 view .LVU1589 2031:Src/main.c **** Def_setup.REF2_EN = 0; 4962 .loc 1 2031 20 is_stmt 0 view .LVU1590 4963 005c 5A71 strb r2, [r3, #5] 2032:Src/main.c **** Def_setup.SD_EN = 0; 4964 .loc 1 2032 2 is_stmt 1 view .LVU1591 2032:Src/main.c **** Def_setup.SD_EN = 0; 4965 .loc 1 2032 20 is_stmt 0 view .LVU1592 4966 005e 9A71 strb r2, [r3, #6] 2033:Src/main.c **** Def_setup.TEC1_EN = 0; 4967 .loc 1 2033 2 is_stmt 1 view .LVU1593 2033:Src/main.c **** Def_setup.TEC1_EN = 0; 4968 .loc 1 2033 18 is_stmt 0 view .LVU1594 4969 0060 DA72 strb r2, [r3, #11] 2034:Src/main.c **** Def_setup.TEC2_EN = 0; 4970 .loc 1 2034 2 is_stmt 1 view .LVU1595 2034:Src/main.c **** Def_setup.TEC2_EN = 0; 4971 .loc 1 2034 20 is_stmt 0 view .LVU1596 4972 0062 DA71 strb r2, [r3, #7] 2035:Src/main.c **** Def_setup.TS1_EN = 0; 4973 .loc 1 2035 2 is_stmt 1 view .LVU1597 2035:Src/main.c **** Def_setup.TS1_EN = 0; 4974 .loc 1 2035 20 is_stmt 0 view .LVU1598 4975 0064 1A72 strb r2, [r3, #8] 2036:Src/main.c **** Def_setup.TS2_EN = 0; 4976 .loc 1 2036 2 is_stmt 1 view .LVU1599 2036:Src/main.c **** Def_setup.TS2_EN = 0; ARM GAS /tmp/ccYgfTud.s page 310 4977 .loc 1 2036 19 is_stmt 0 view .LVU1600 4978 0066 5A72 strb r2, [r3, #9] 2037:Src/main.c **** Def_setup.U5V1_EN = 0; 4979 .loc 1 2037 2 is_stmt 1 view .LVU1601 2037:Src/main.c **** Def_setup.U5V1_EN = 0; 4980 .loc 1 2037 19 is_stmt 0 view .LVU1602 4981 0068 9A72 strb r2, [r3, #10] 2038:Src/main.c **** Def_setup.U5V2_EN = 0; 4982 .loc 1 2038 2 is_stmt 1 view .LVU1603 2038:Src/main.c **** Def_setup.U5V2_EN = 0; 4983 .loc 1 2038 20 is_stmt 0 view .LVU1604 4984 006a 5A70 strb r2, [r3, #1] 2039:Src/main.c **** Def_setup.WORK_EN = 0; 4985 .loc 1 2039 2 is_stmt 1 view .LVU1605 2039:Src/main.c **** Def_setup.WORK_EN = 0; 4986 .loc 1 2039 20 is_stmt 0 view .LVU1606 4987 006c 9A70 strb r2, [r3, #2] 2040:Src/main.c **** 4988 .loc 1 2040 2 is_stmt 1 view .LVU1607 2040:Src/main.c **** 4989 .loc 1 2040 20 is_stmt 0 view .LVU1608 4990 006e 1A70 strb r2, [r3] 2042:Src/main.c **** LD2_def_setup.LD_TEMP = 0; 4991 .loc 1 2042 2 is_stmt 1 view .LVU1609 2042:Src/main.c **** LD2_def_setup.LD_TEMP = 0; 4992 .loc 1 2042 24 is_stmt 0 view .LVU1610 4993 0070 914D ldr r5, .L225+52 4994 0072 2A80 strh r2, [r5] @ movhi 2043:Src/main.c **** LD1_def_setup.P_coef_temp = 0; 4995 .loc 1 2043 2 is_stmt 1 view .LVU1611 2043:Src/main.c **** LD1_def_setup.P_coef_temp = 0; 4996 .loc 1 2043 24 is_stmt 0 view .LVU1612 4997 0074 914C ldr r4, .L225+56 4998 0076 2280 strh r2, [r4] @ movhi 2044:Src/main.c **** LD2_def_setup.P_coef_temp = 0; 4999 .loc 1 2044 2 is_stmt 1 view .LVU1613 2044:Src/main.c **** LD2_def_setup.P_coef_temp = 0; 5000 .loc 1 2044 28 is_stmt 0 view .LVU1614 5001 0078 0022 movs r2, #0 5002 007a 6A60 str r2, [r5, #4] @ float 2045:Src/main.c **** LD1_def_setup.I_coef_temp = 0; 5003 .loc 1 2045 2 is_stmt 1 view .LVU1615 2045:Src/main.c **** LD1_def_setup.I_coef_temp = 0; 5004 .loc 1 2045 28 is_stmt 0 view .LVU1616 5005 007c 6260 str r2, [r4, #4] @ float 2046:Src/main.c **** LD2_def_setup.I_coef_temp = 0; 5006 .loc 1 2046 2 is_stmt 1 view .LVU1617 2046:Src/main.c **** LD2_def_setup.I_coef_temp = 0; 5007 .loc 1 2046 28 is_stmt 0 view .LVU1618 5008 007e AA60 str r2, [r5, #8] @ float 2047:Src/main.c **** 5009 .loc 1 2047 2 is_stmt 1 view .LVU1619 2047:Src/main.c **** 5010 .loc 1 2047 28 is_stmt 0 view .LVU1620 5011 0080 A260 str r2, [r4, #8] @ float 2050:Src/main.c **** LD1_curr_setup = LD1_def_setup; 5012 .loc 1 2050 2 is_stmt 1 view .LVU1621 ARM GAS /tmp/ccYgfTud.s page 311 2050:Src/main.c **** LD1_curr_setup = LD1_def_setup; 5013 .loc 1 2050 13 is_stmt 0 view .LVU1622 5014 0082 8F4E ldr r6, .L225+60 5015 0084 9C46 mov ip, r3 5016 0086 BCE80F00 ldmia ip!, {r0, r1, r2, r3} 5017 008a 0FC6 stmia r6!, {r0, r1, r2, r3} 5018 008c DCF80030 ldr r3, [ip] 5019 0090 3380 strh r3, [r6] @ movhi 2051:Src/main.c **** LD2_curr_setup = LD2_def_setup; 5020 .loc 1 2051 2 is_stmt 1 view .LVU1623 2051:Src/main.c **** LD2_curr_setup = LD2_def_setup; 5021 .loc 1 2051 17 is_stmt 0 view .LVU1624 5022 0092 8C4E ldr r6, .L225+64 5023 0094 95E80F00 ldm r5, {r0, r1, r2, r3} 5024 0098 86E80F00 stm r6, {r0, r1, r2, r3} 2052:Src/main.c **** 5025 .loc 1 2052 2 is_stmt 1 view .LVU1625 2052:Src/main.c **** 5026 .loc 1 2052 17 is_stmt 0 view .LVU1626 5027 009c 8A4D ldr r5, .L225+68 5028 009e 94E80F00 ldm r4, {r0, r1, r2, r3} 5029 00a2 85E80F00 stm r5, {r0, r1, r2, r3} 2057:Src/main.c **** LL_TIM_EnableCounter(TIM6); 5030 .loc 1 2057 2 is_stmt 1 view .LVU1627 5031 .LVL408: 5032 .LBB516: 5033 .LBI516: 3238:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3239:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3240:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3241:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Indicates whether the Master/Slave mode is enabled. 3242:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not 3243:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * a timer instance can operate as a slave timer. 3244:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SMCR MSM LL_TIM_IsEnabledMasterSlaveMode 3245:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3246:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval State of bit (1 or 0). 3247:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3248:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsEnabledMasterSlaveMode(const TIM_TypeDef *TIMx) 3249:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3250:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return ((READ_BIT(TIMx->SMCR, TIM_SMCR_MSM) == (TIM_SMCR_MSM)) ? 1UL : 0UL); 3251:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3252:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3253:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3254:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Configure the external trigger (ETR) input. 3255:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_ETR_INSTANCE(TIMx) can be used to check whether or not 3256:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * a timer instance provides an external trigger input. 3257:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SMCR ETP LL_TIM_ConfigETR\n 3258:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * SMCR ETPS LL_TIM_ConfigETR\n 3259:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * SMCR ETF LL_TIM_ConfigETR 3260:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3261:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param ETRPolarity This parameter can be one of the following values: 3262:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ETR_POLARITY_NONINVERTED 3263:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ETR_POLARITY_INVERTED 3264:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param ETRPrescaler This parameter can be one of the following values: 3265:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ETR_PRESCALER_DIV1 3266:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ETR_PRESCALER_DIV2 3267:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ETR_PRESCALER_DIV4 ARM GAS /tmp/ccYgfTud.s page 312 3268:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ETR_PRESCALER_DIV8 3269:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param ETRFilter This parameter can be one of the following values: 3270:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ETR_FILTER_FDIV1 3271:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N2 3272:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N4 3273:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N8 3274:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ETR_FILTER_FDIV2_N6 3275:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ETR_FILTER_FDIV2_N8 3276:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ETR_FILTER_FDIV4_N6 3277:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ETR_FILTER_FDIV4_N8 3278:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ETR_FILTER_FDIV8_N6 3279:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ETR_FILTER_FDIV8_N8 3280:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N5 3281:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N6 3282:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N8 3283:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N5 3284:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N6 3285:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N8 3286:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 3287:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3288:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_ConfigETR(TIM_TypeDef *TIMx, uint32_t ETRPolarity, uint32_t ETRPrescale 3289:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t ETRFilter) 3290:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3291:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(TIMx->SMCR, TIM_SMCR_ETP | TIM_SMCR_ETPS | TIM_SMCR_ETF, ETRPolarity | ETRPrescaler | 3292:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3293:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3294:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3295:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} 3296:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3298:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EF_Break_Function Break function configuration 3299:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ 3300:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3301:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3302:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Enable the break function. 3303:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not 3304:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * a timer instance provides a break input. 3305:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll BDTR BKE LL_TIM_EnableBRK 3306:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3307:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 3308:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3309:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_EnableBRK(TIM_TypeDef *TIMx) 3310:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3311:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** SET_BIT(TIMx->BDTR, TIM_BDTR_BKE); 3312:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3313:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Disable the break function. 3316:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll BDTR BKE LL_TIM_DisableBRK 3317:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3318:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not 3319:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * a timer instance provides a break input. 3320:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 3321:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3322:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_DisableBRK(TIM_TypeDef *TIMx) 3323:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3324:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BKE); ARM GAS /tmp/ccYgfTud.s page 313 3325:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3326:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3327:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3328:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Configure the break input. 3329:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not 3330:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * a timer instance provides a break input. 3331:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll BDTR BKP LL_TIM_ConfigBRK\n 3332:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * BDTR BKF LL_TIM_ConfigBRK 3333:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3334:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param BreakPolarity This parameter can be one of the following values: 3335:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK_POLARITY_LOW 3336:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK_POLARITY_HIGH 3337:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param BreakFilter This parameter can be one of the following values: 3338:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK_FILTER_FDIV1 3339:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N2 3340:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N4 3341:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N8 3342:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N6 3343:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N8 3344:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N6 3345:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N8 3346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N6 3347:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N8 3348:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N5 3349:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N6 3350:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N8 3351:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N5 3352:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N6 3353:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N8 3354:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 3355:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3356:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_ConfigBRK(TIM_TypeDef *TIMx, uint32_t BreakPolarity, 3357:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t BreakFilter) 3358:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3359:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(TIMx->BDTR, TIM_BDTR_BKP | TIM_BDTR_BKF, BreakPolarity | BreakFilter); 3360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3361:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3362:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3363:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Enable the break 2 function. 3364:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not 3365:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * a timer instance provides a second break input. 3366:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll BDTR BK2E LL_TIM_EnableBRK2 3367:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3368:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 3369:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_EnableBRK2(TIM_TypeDef *TIMx) 3371:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** SET_BIT(TIMx->BDTR, TIM_BDTR_BK2E); 3373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3374:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3375:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3376:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Disable the break 2 function. 3377:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not 3378:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * a timer instance provides a second break input. 3379:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll BDTR BK2E LL_TIM_DisableBRK2 3380:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3381:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None ARM GAS /tmp/ccYgfTud.s page 314 3382:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3383:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_DisableBRK2(TIM_TypeDef *TIMx) 3384:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3385:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BK2E); 3386:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3387:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3388:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3389:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Configure the break 2 input. 3390:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not 3391:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * a timer instance provides a second break input. 3392:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll BDTR BK2P LL_TIM_ConfigBRK2\n 3393:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * BDTR BK2F LL_TIM_ConfigBRK2 3394:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3395:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Break2Polarity This parameter can be one of the following values: 3396:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK2_POLARITY_LOW 3397:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK2_POLARITY_HIGH 3398:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Break2Filter This parameter can be one of the following values: 3399:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1 3400:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N2 3401:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N4 3402:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N8 3403:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N6 3404:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N8 3405:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N6 3406:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N8 3407:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N6 3408:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N8 3409:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N5 3410:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N6 3411:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N8 3412:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N5 3413:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N6 3414:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N8 3415:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 3416:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3417:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_ConfigBRK2(TIM_TypeDef *TIMx, uint32_t Break2Polarity, uint32_t Break2F 3418:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3419:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(TIMx->BDTR, TIM_BDTR_BK2P | TIM_BDTR_BK2F, Break2Polarity | Break2Filter); 3420:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3421:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3422:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3423:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Select the outputs off state (enabled v.s. disabled) in Idle and Run modes. 3424:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not 3425:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * a timer instance provides a break input. 3426:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll BDTR OSSI LL_TIM_SetOffStates\n 3427:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * BDTR OSSR LL_TIM_SetOffStates 3428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3429:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param OffStateIdle This parameter can be one of the following values: 3430:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OSSI_DISABLE 3431:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OSSI_ENABLE 3432:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param OffStateRun This parameter can be one of the following values: 3433:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OSSR_DISABLE 3434:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OSSR_ENABLE 3435:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 3436:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3437:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_SetOffStates(TIM_TypeDef *TIMx, uint32_t OffStateIdle, uint32_t OffStat 3438:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { ARM GAS /tmp/ccYgfTud.s page 315 3439:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(TIMx->BDTR, TIM_BDTR_OSSI | TIM_BDTR_OSSR, OffStateIdle | OffStateRun); 3440:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3441:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3442:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3443:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Enable automatic output (MOE can be set by software or automatically when a break input 3444:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not 3445:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * a timer instance provides a break input. 3446:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll BDTR AOE LL_TIM_EnableAutomaticOutput 3447:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3448:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 3449:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3450:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_EnableAutomaticOutput(TIM_TypeDef *TIMx) 3451:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3452:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** SET_BIT(TIMx->BDTR, TIM_BDTR_AOE); 3453:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3454:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3455:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3456:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Disable automatic output (MOE can be set only by software). 3457:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not 3458:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * a timer instance provides a break input. 3459:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll BDTR AOE LL_TIM_DisableAutomaticOutput 3460:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3461:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 3462:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_DisableAutomaticOutput(TIM_TypeDef *TIMx) 3464:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3465:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** CLEAR_BIT(TIMx->BDTR, TIM_BDTR_AOE); 3466:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3467:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3468:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3469:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Indicate whether automatic output is enabled. 3470:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not 3471:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * a timer instance provides a break input. 3472:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll BDTR AOE LL_TIM_IsEnabledAutomaticOutput 3473:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3474:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval State of bit (1 or 0). 3475:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3476:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsEnabledAutomaticOutput(const TIM_TypeDef *TIMx) 3477:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3478:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return ((READ_BIT(TIMx->BDTR, TIM_BDTR_AOE) == (TIM_BDTR_AOE)) ? 1UL : 0UL); 3479:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3480:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3481:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3482:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Enable the outputs (set the MOE bit in TIMx_BDTR register). 3483:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by 3484:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * software and is reset in case of break or break2 event 3485:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not 3486:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * a timer instance provides a break input. 3487:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll BDTR MOE LL_TIM_EnableAllOutputs 3488:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3489:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 3490:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3491:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_EnableAllOutputs(TIM_TypeDef *TIMx) 3492:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3493:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** SET_BIT(TIMx->BDTR, TIM_BDTR_MOE); 3494:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3495:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** ARM GAS /tmp/ccYgfTud.s page 316 3496:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3497:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Disable the outputs (reset the MOE bit in TIMx_BDTR register). 3498:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by 3499:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * software and is reset in case of break or break2 event. 3500:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not 3501:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * a timer instance provides a break input. 3502:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll BDTR MOE LL_TIM_DisableAllOutputs 3503:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3504:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 3505:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3506:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_DisableAllOutputs(TIM_TypeDef *TIMx) 3507:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3508:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** CLEAR_BIT(TIMx->BDTR, TIM_BDTR_MOE); 3509:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3510:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3511:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3512:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Indicates whether outputs are enabled. 3513:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not 3514:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * a timer instance provides a break input. 3515:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll BDTR MOE LL_TIM_IsEnabledAllOutputs 3516:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3517:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval State of bit (1 or 0). 3518:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3519:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsEnabledAllOutputs(const TIM_TypeDef *TIMx) 3520:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3521:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return ((READ_BIT(TIMx->BDTR, TIM_BDTR_MOE) == (TIM_BDTR_MOE)) ? 1UL : 0UL); 3522:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3523:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3524:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #if defined(TIM_BREAK_INPUT_SUPPORT) 3525:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3526:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Enable the signals connected to the designated timer break input. 3527:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether 3528:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * or not a timer instance allows for break input selection. 3529:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll AF1 BKINE LL_TIM_EnableBreakInputSource\n 3530:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * AF1 BKDFBKE LL_TIM_EnableBreakInputSource\n 3531:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * AF2 BK2INE LL_TIM_EnableBreakInputSource\n 3532:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * AF2 BK2DFBKE LL_TIM_EnableBreakInputSource 3533:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3534:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param BreakInput This parameter can be one of the following values: 3535:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK_INPUT_BKIN 3536:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK_INPUT_BKIN2 3537:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Source This parameter can be one of the following values: 3538:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BKIN_SOURCE_BKIN 3539:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BKIN_SOURCE_DF1BK 3540:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 3541:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3542:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_EnableBreakInputSource(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t 3543:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3544:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput)); 3545:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** SET_BIT(*pReg, Source); 3546:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3547:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3548:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3549:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Disable the signals connected to the designated timer break input. 3550:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether 3551:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * or not a timer instance allows for break input selection. 3552:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll AF1 BKINE LL_TIM_DisableBreakInputSource\n ARM GAS /tmp/ccYgfTud.s page 317 3553:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * AF1 BKDFBKE LL_TIM_DisableBreakInputSource\n 3554:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * AF2 BK2INE LL_TIM_DisableBreakInputSource\n 3555:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * AF2 BK2DFBKE LL_TIM_DisableBreakInputSource 3556:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3557:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param BreakInput This parameter can be one of the following values: 3558:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK_INPUT_BKIN 3559:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK_INPUT_BKIN2 3560:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Source This parameter can be one of the following values: 3561:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BKIN_SOURCE_BKIN 3562:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BKIN_SOURCE_DF1BK 3563:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 3564:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3565:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_DisableBreakInputSource(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_ 3566:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3567:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput)); 3568:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** CLEAR_BIT(*pReg, Source); 3569:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3570:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3571:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3572:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Set the polarity of the break signal for the timer break input. 3573:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether 3574:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * or not a timer instance allows for break input selection. 3575:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll AF1 BKINP LL_TIM_SetBreakInputSourcePolarity\n 3576:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * AF1 BKDFBKP LL_TIM_SetBreakInputSourcePolarity\n 3577:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * AF2 BK2INP LL_TIM_SetBreakInputSourcePolarity\n 3578:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * AF2 BK2DFBKP LL_TIM_SetBreakInputSourcePolarity 3579:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3580:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param BreakInput This parameter can be one of the following values: 3581:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK_INPUT_BKIN 3582:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK_INPUT_BKIN2 3583:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Source This parameter can be one of the following values: 3584:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BKIN_SOURCE_BKIN 3585:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BKIN_SOURCE_DF1BK 3586:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Polarity This parameter can be one of the following values: 3587:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BKIN_POLARITY_LOW 3588:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BKIN_POLARITY_HIGH 3589:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 3590:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3591:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_SetBreakInputSourcePolarity(TIM_TypeDef *TIMx, uint32_t BreakInput, uin 3592:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t Polarity) 3593:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3594:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput)); 3595:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(*pReg, (TIMx_AF1_BKINP << TIM_POSITION_BRK_SOURCE), (Polarity << TIM_POSITION_BRK_SOUR 3596:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3597:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #endif /* TIM_BREAK_INPUT_SUPPORT */ 3598:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3599:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} 3600:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3601:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3602:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EF_DMA_Burst_Mode DMA burst mode configuration 3603:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ 3604:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3605:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3606:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Configures the timer DMA burst feature. 3607:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_DMABURST_INSTANCE(TIMx) can be used to check whether or 3608:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * not a timer instance supports the DMA burst mode. 3609:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll DCR DBL LL_TIM_ConfigDMABurst\n ARM GAS /tmp/ccYgfTud.s page 318 3610:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * DCR DBA LL_TIM_ConfigDMABurst 3611:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3612:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param DMABurstBaseAddress This parameter can be one of the following values: 3613:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_BASEADDR_CR1 3614:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_BASEADDR_CR2 3615:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_BASEADDR_SMCR 3616:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_BASEADDR_DIER 3617:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_BASEADDR_SR 3618:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_BASEADDR_EGR 3619:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR1 3620:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR2 3621:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_BASEADDR_CCER 3622:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_BASEADDR_CNT 3623:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_BASEADDR_PSC 3624:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_BASEADDR_ARR 3625:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_BASEADDR_RCR 3626:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR1 3627:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR2 3628:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR3 3629:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR4 3630:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_BASEADDR_BDTR 3631:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_BASEADDR_OR 3632:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR3 3633:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR5 3634:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR6 3635:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_BASEADDR_AF1 (*) 3636:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_BASEADDR_AF2 (*) 3637:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * (*) value not defined in all devices 3638:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param DMABurstLength This parameter can be one of the following values: 3639:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_LENGTH_1TRANSFER 3640:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_LENGTH_2TRANSFERS 3641:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_LENGTH_3TRANSFERS 3642:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_LENGTH_4TRANSFERS 3643:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_LENGTH_5TRANSFERS 3644:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_LENGTH_6TRANSFERS 3645:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_LENGTH_7TRANSFERS 3646:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_LENGTH_8TRANSFERS 3647:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_LENGTH_9TRANSFERS 3648:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_LENGTH_10TRANSFERS 3649:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_LENGTH_11TRANSFERS 3650:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_LENGTH_12TRANSFERS 3651:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_LENGTH_13TRANSFERS 3652:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_LENGTH_14TRANSFERS 3653:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_LENGTH_15TRANSFERS 3654:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_LENGTH_16TRANSFERS 3655:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_LENGTH_17TRANSFERS 3656:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_LENGTH_18TRANSFERS 3657:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 3658:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3659:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_ConfigDMABurst(TIM_TypeDef *TIMx, uint32_t DMABurstBaseAddress, uint32_ 3660:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3661:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(TIMx->DCR, (TIM_DCR_DBL | TIM_DCR_DBA), (DMABurstBaseAddress | DMABurstLength)); 3662:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3663:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3664:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3665:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} 3666:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ ARM GAS /tmp/ccYgfTud.s page 319 3667:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3668:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EF_Timer_Inputs_Remapping Timer input remapping 3669:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ 3670:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3671:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3672:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Remap TIM inputs (input channel, internal/external triggers). 3673:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_REMAP_INSTANCE(TIMx) can be used to check whether or not 3674:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * a some timer inputs can be remapped. 3675:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll TIM2_OR ITR1_RMP LL_TIM_SetRemap\n 3676:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * TIM5_OR TI4_RMP LL_TIM_SetRemap\n 3677:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * TIM11_OR TI1_RMP LL_TIM_SetRemap 3678:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3679:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Remap Remap param depends on the TIMx. Description available only 3680:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * in CHM version of the User Manual (not in .pdf). 3681:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * Otherwise see Reference Manual description of OR registers. 3682:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * 3683:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * Below description summarizes "Timer Instance" and "Remap" param combinations: 3684:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * 3685:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * TIM2: one of the following values 3686:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * 3687:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * ITR1_RMP can be one of the following values 3688:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TIM2_ITR1_RMP_TIM8_TRGO 3689:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TIM2_ITR1_RMP_ETH_PTP 3690:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TIM2_ITR1_RMP_OTG_FS_SOF 3691:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TIM2_ITR1_RMP_OTG_HS_SOF 3692:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * 3693:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * TIM5: one of the following values 3694:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * 3695:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TIM5_TI4_RMP_GPIO 3696:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TIM5_TI4_RMP_LSI 3697:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TIM5_TI4_RMP_LSE 3698:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TIM5_TI4_RMP_RTC 3699:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * 3700:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * TIM11: one of the following values 3701:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * 3702:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TIM11_TI1_RMP_GPIO 3703:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TIM11_TI1_RMP_SPDIFRX 3704:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TIM11_TI1_RMP_HSE 3705:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TIM11_TI1_RMP_MCO1 3706:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * 3707:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 3708:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3709:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_SetRemap(TIM_TypeDef *TIMx, uint32_t Remap) 3710:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3711:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(TIMx->OR, (Remap >> TIMx_OR_RMP_SHIFT), (Remap & TIMx_OR_RMP_MASK)); 3712:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3713:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3714:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3715:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} 3716:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3717:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3718:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EF_FLAG_Management FLAG-Management 3719:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ 3720:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3721:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3722:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Clear the update interrupt flag (UIF). 3723:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SR UIF LL_TIM_ClearFlag_UPDATE ARM GAS /tmp/ccYgfTud.s page 320 3724:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3725:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 3726:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3727:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_ClearFlag_UPDATE(TIM_TypeDef *TIMx) 3728:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3729:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** WRITE_REG(TIMx->SR, ~(TIM_SR_UIF)); 3730:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3731:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3732:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3733:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Indicate whether update interrupt flag (UIF) is set (update interrupt is pending). 3734:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SR UIF LL_TIM_IsActiveFlag_UPDATE 3735:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3736:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval State of bit (1 or 0). 3737:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3738:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_UPDATE(const TIM_TypeDef *TIMx) 3739:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3740:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return ((READ_BIT(TIMx->SR, TIM_SR_UIF) == (TIM_SR_UIF)) ? 1UL : 0UL); 3741:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3742:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3743:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3744:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Clear the Capture/Compare 1 interrupt flag (CC1F). 3745:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SR CC1IF LL_TIM_ClearFlag_CC1 3746:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3747:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 3748:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3749:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_ClearFlag_CC1(TIM_TypeDef *TIMx) 3750:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3751:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** WRITE_REG(TIMx->SR, ~(TIM_SR_CC1IF)); 3752:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3753:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3754:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3755:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Indicate whether Capture/Compare 1 interrupt flag (CC1F) is set (Capture/Compare 1 inte 3756:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SR CC1IF LL_TIM_IsActiveFlag_CC1 3757:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3758:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval State of bit (1 or 0). 3759:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3760:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1(const TIM_TypeDef *TIMx) 3761:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3762:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return ((READ_BIT(TIMx->SR, TIM_SR_CC1IF) == (TIM_SR_CC1IF)) ? 1UL : 0UL); 3763:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3764:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3765:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3766:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Clear the Capture/Compare 2 interrupt flag (CC2F). 3767:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SR CC2IF LL_TIM_ClearFlag_CC2 3768:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3769:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 3770:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3771:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_ClearFlag_CC2(TIM_TypeDef *TIMx) 3772:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3773:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** WRITE_REG(TIMx->SR, ~(TIM_SR_CC2IF)); 3774:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3775:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3776:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3777:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Indicate whether Capture/Compare 2 interrupt flag (CC2F) is set (Capture/Compare 2 inte 3778:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SR CC2IF LL_TIM_IsActiveFlag_CC2 3779:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3780:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval State of bit (1 or 0). ARM GAS /tmp/ccYgfTud.s page 321 3781:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3782:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2(const TIM_TypeDef *TIMx) 3783:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3784:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return ((READ_BIT(TIMx->SR, TIM_SR_CC2IF) == (TIM_SR_CC2IF)) ? 1UL : 0UL); 3785:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3786:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3787:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3788:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Clear the Capture/Compare 3 interrupt flag (CC3F). 3789:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SR CC3IF LL_TIM_ClearFlag_CC3 3790:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3791:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 3792:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3793:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_ClearFlag_CC3(TIM_TypeDef *TIMx) 3794:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3795:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** WRITE_REG(TIMx->SR, ~(TIM_SR_CC3IF)); 3796:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3797:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3798:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3799:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Indicate whether Capture/Compare 3 interrupt flag (CC3F) is set (Capture/Compare 3 inte 3800:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SR CC3IF LL_TIM_IsActiveFlag_CC3 3801:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3802:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval State of bit (1 or 0). 3803:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3804:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3(const TIM_TypeDef *TIMx) 3805:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3806:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return ((READ_BIT(TIMx->SR, TIM_SR_CC3IF) == (TIM_SR_CC3IF)) ? 1UL : 0UL); 3807:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3808:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3809:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3810:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Clear the Capture/Compare 4 interrupt flag (CC4F). 3811:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SR CC4IF LL_TIM_ClearFlag_CC4 3812:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3813:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 3814:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3815:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_ClearFlag_CC4(TIM_TypeDef *TIMx) 3816:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3817:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** WRITE_REG(TIMx->SR, ~(TIM_SR_CC4IF)); 3818:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3819:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3820:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3821:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Indicate whether Capture/Compare 4 interrupt flag (CC4F) is set (Capture/Compare 4 inte 3822:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SR CC4IF LL_TIM_IsActiveFlag_CC4 3823:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3824:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval State of bit (1 or 0). 3825:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3826:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4(const TIM_TypeDef *TIMx) 3827:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3828:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return ((READ_BIT(TIMx->SR, TIM_SR_CC4IF) == (TIM_SR_CC4IF)) ? 1UL : 0UL); 3829:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3830:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3831:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3832:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Clear the Capture/Compare 5 interrupt flag (CC5F). 3833:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SR CC5IF LL_TIM_ClearFlag_CC5 3834:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3835:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 3836:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3837:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_ClearFlag_CC5(TIM_TypeDef *TIMx) ARM GAS /tmp/ccYgfTud.s page 322 3838:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3839:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** WRITE_REG(TIMx->SR, ~(TIM_SR_CC5IF)); 3840:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3841:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3842:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3843:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Indicate whether Capture/Compare 5 interrupt flag (CC5F) is set (Capture/Compare 5 inte 3844:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SR CC5IF LL_TIM_IsActiveFlag_CC5 3845:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3846:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval State of bit (1 or 0). 3847:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3848:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC5(const TIM_TypeDef *TIMx) 3849:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3850:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return ((READ_BIT(TIMx->SR, TIM_SR_CC5IF) == (TIM_SR_CC5IF)) ? 1UL : 0UL); 3851:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3852:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3853:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3854:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Clear the Capture/Compare 6 interrupt flag (CC6F). 3855:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SR CC6IF LL_TIM_ClearFlag_CC6 3856:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3857:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 3858:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3859:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_ClearFlag_CC6(TIM_TypeDef *TIMx) 3860:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3861:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** WRITE_REG(TIMx->SR, ~(TIM_SR_CC6IF)); 3862:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3863:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3864:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3865:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Indicate whether Capture/Compare 6 interrupt flag (CC6F) is set (Capture/Compare 6 inte 3866:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SR CC6IF LL_TIM_IsActiveFlag_CC6 3867:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3868:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval State of bit (1 or 0). 3869:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3870:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC6(const TIM_TypeDef *TIMx) 3871:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3872:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return ((READ_BIT(TIMx->SR, TIM_SR_CC6IF) == (TIM_SR_CC6IF)) ? 1UL : 0UL); 3873:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3874:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3875:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3876:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Clear the commutation interrupt flag (COMIF). 3877:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SR COMIF LL_TIM_ClearFlag_COM 3878:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3879:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 3880:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3881:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_ClearFlag_COM(TIM_TypeDef *TIMx) 3882:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3883:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** WRITE_REG(TIMx->SR, ~(TIM_SR_COMIF)); 3884:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3885:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3886:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3887:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Indicate whether commutation interrupt flag (COMIF) is set (commutation interrupt is pe 3888:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SR COMIF LL_TIM_IsActiveFlag_COM 3889:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3890:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval State of bit (1 or 0). 3891:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3892:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_COM(const TIM_TypeDef *TIMx) 3893:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3894:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return ((READ_BIT(TIMx->SR, TIM_SR_COMIF) == (TIM_SR_COMIF)) ? 1UL : 0UL); ARM GAS /tmp/ccYgfTud.s page 323 3895:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3896:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3897:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3898:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Clear the trigger interrupt flag (TIF). 3899:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SR TIF LL_TIM_ClearFlag_TRIG 3900:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3901:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 3902:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3903:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_ClearFlag_TRIG(TIM_TypeDef *TIMx) 3904:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3905:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** WRITE_REG(TIMx->SR, ~(TIM_SR_TIF)); 3906:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3908:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3909:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Indicate whether trigger interrupt flag (TIF) is set (trigger interrupt is pending). 3910:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SR TIF LL_TIM_IsActiveFlag_TRIG 3911:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3912:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval State of bit (1 or 0). 3913:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3914:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_TRIG(const TIM_TypeDef *TIMx) 3915:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3916:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return ((READ_BIT(TIMx->SR, TIM_SR_TIF) == (TIM_SR_TIF)) ? 1UL : 0UL); 3917:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3919:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3920:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Clear the break interrupt flag (BIF). 3921:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SR BIF LL_TIM_ClearFlag_BRK 3922:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3923:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 3924:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3925:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_ClearFlag_BRK(TIM_TypeDef *TIMx) 3926:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3927:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** WRITE_REG(TIMx->SR, ~(TIM_SR_BIF)); 3928:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3929:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3930:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3931:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Indicate whether break interrupt flag (BIF) is set (break interrupt is pending). 3932:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SR BIF LL_TIM_IsActiveFlag_BRK 3933:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3934:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval State of bit (1 or 0). 3935:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3936:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK(const TIM_TypeDef *TIMx) 3937:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3938:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return ((READ_BIT(TIMx->SR, TIM_SR_BIF) == (TIM_SR_BIF)) ? 1UL : 0UL); 3939:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3940:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3941:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3942:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Clear the break 2 interrupt flag (B2IF). 3943:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SR B2IF LL_TIM_ClearFlag_BRK2 3944:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3945:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 3946:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3947:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_ClearFlag_BRK2(TIM_TypeDef *TIMx) 3948:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3949:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** WRITE_REG(TIMx->SR, ~(TIM_SR_B2IF)); 3950:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3951:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** ARM GAS /tmp/ccYgfTud.s page 324 3952:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3953:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Indicate whether break 2 interrupt flag (B2IF) is set (break 2 interrupt is pending). 3954:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SR B2IF LL_TIM_IsActiveFlag_BRK2 3955:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3956:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval State of bit (1 or 0). 3957:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3958:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK2(const TIM_TypeDef *TIMx) 3959:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3960:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return ((READ_BIT(TIMx->SR, TIM_SR_B2IF) == (TIM_SR_B2IF)) ? 1UL : 0UL); 3961:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3962:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3963:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3964:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Clear the Capture/Compare 1 over-capture interrupt flag (CC1OF). 3965:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SR CC1OF LL_TIM_ClearFlag_CC1OVR 3966:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3967:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 3968:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3969:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_ClearFlag_CC1OVR(TIM_TypeDef *TIMx) 3970:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3971:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** WRITE_REG(TIMx->SR, ~(TIM_SR_CC1OF)); 3972:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3973:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3974:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3975:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Indicate whether Capture/Compare 1 over-capture interrupt flag (CC1OF) is set 3976:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * (Capture/Compare 1 interrupt is pending). 3977:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SR CC1OF LL_TIM_IsActiveFlag_CC1OVR 3978:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3979:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval State of bit (1 or 0). 3980:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3981:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1OVR(const TIM_TypeDef *TIMx) 3982:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3983:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return ((READ_BIT(TIMx->SR, TIM_SR_CC1OF) == (TIM_SR_CC1OF)) ? 1UL : 0UL); 3984:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3985:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3986:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3987:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Clear the Capture/Compare 2 over-capture interrupt flag (CC2OF). 3988:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SR CC2OF LL_TIM_ClearFlag_CC2OVR 3989:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3990:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 3991:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3992:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_ClearFlag_CC2OVR(TIM_TypeDef *TIMx) 3993:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3994:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** WRITE_REG(TIMx->SR, ~(TIM_SR_CC2OF)); 3995:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3996:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3997:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3998:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Indicate whether Capture/Compare 2 over-capture interrupt flag (CC2OF) is set 3999:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * (Capture/Compare 2 over-capture interrupt is pending). 4000:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SR CC2OF LL_TIM_IsActiveFlag_CC2OVR 4001:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 4002:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval State of bit (1 or 0). 4003:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 4004:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2OVR(const TIM_TypeDef *TIMx) 4005:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 4006:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return ((READ_BIT(TIMx->SR, TIM_SR_CC2OF) == (TIM_SR_CC2OF)) ? 1UL : 0UL); 4007:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 4008:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** ARM GAS /tmp/ccYgfTud.s page 325 4009:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 4010:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Clear the Capture/Compare 3 over-capture interrupt flag (CC3OF). 4011:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SR CC3OF LL_TIM_ClearFlag_CC3OVR 4012:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 4013:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 4014:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 4015:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_ClearFlag_CC3OVR(TIM_TypeDef *TIMx) 4016:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 4017:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** WRITE_REG(TIMx->SR, ~(TIM_SR_CC3OF)); 4018:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 4019:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 4020:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 4021:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Indicate whether Capture/Compare 3 over-capture interrupt flag (CC3OF) is set 4022:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * (Capture/Compare 3 over-capture interrupt is pending). 4023:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SR CC3OF LL_TIM_IsActiveFlag_CC3OVR 4024:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 4025:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval State of bit (1 or 0). 4026:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 4027:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3OVR(const TIM_TypeDef *TIMx) 4028:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 4029:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return ((READ_BIT(TIMx->SR, TIM_SR_CC3OF) == (TIM_SR_CC3OF)) ? 1UL : 0UL); 4030:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 4031:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 4032:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 4033:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Clear the Capture/Compare 4 over-capture interrupt flag (CC4OF). 4034:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SR CC4OF LL_TIM_ClearFlag_CC4OVR 4035:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 4036:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 4037:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 4038:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_ClearFlag_CC4OVR(TIM_TypeDef *TIMx) 4039:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 4040:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** WRITE_REG(TIMx->SR, ~(TIM_SR_CC4OF)); 4041:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 4042:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 4043:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 4044:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Indicate whether Capture/Compare 4 over-capture interrupt flag (CC4OF) is set 4045:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * (Capture/Compare 4 over-capture interrupt is pending). 4046:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SR CC4OF LL_TIM_IsActiveFlag_CC4OVR 4047:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 4048:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval State of bit (1 or 0). 4049:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 4050:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4OVR(const TIM_TypeDef *TIMx) 4051:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 4052:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return ((READ_BIT(TIMx->SR, TIM_SR_CC4OF) == (TIM_SR_CC4OF)) ? 1UL : 0UL); 4053:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 4054:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 4055:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 4056:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Clear the system break interrupt flag (SBIF). 4057:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SR SBIF LL_TIM_ClearFlag_SYSBRK 4058:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 4059:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 4060:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 4061:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_ClearFlag_SYSBRK(TIM_TypeDef *TIMx) 4062:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 4063:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** WRITE_REG(TIMx->SR, ~(TIM_SR_SBIF)); 4064:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 4065:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** ARM GAS /tmp/ccYgfTud.s page 326 4066:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 4067:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Indicate whether system break interrupt flag (SBIF) is set (system break interrupt is p 4068:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SR SBIF LL_TIM_IsActiveFlag_SYSBRK 4069:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 4070:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval State of bit (1 or 0). 4071:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 4072:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_SYSBRK(const TIM_TypeDef *TIMx) 4073:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 4074:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return ((READ_BIT(TIMx->SR, TIM_SR_SBIF) == (TIM_SR_SBIF)) ? 1UL : 0UL); 4075:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 4076:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 4077:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 4078:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} 4079:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 4080:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 4081:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EF_IT_Management IT-Management 4082:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ 4083:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 4084:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 4085:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Enable update interrupt (UIE). 4086:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll DIER UIE LL_TIM_EnableIT_UPDATE 4087:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 4088:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 4089:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 4090:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_EnableIT_UPDATE(TIM_TypeDef *TIMx) 5034 .loc 5 4090 22 view .LVU1628 5035 .LBB517: 4091:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 4092:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** SET_BIT(TIMx->DIER, TIM_DIER_UIE); 5036 .loc 5 4092 3 view .LVU1629 5037 00a6 894B ldr r3, .L225+72 5038 00a8 DA68 ldr r2, [r3, #12] 5039 00aa 42F00102 orr r2, r2, #1 5040 00ae DA60 str r2, [r3, #12] 5041 .LVL409: 5042 .loc 5 4092 3 is_stmt 0 view .LVU1630 5043 .LBE517: 5044 .LBE516: 2058:Src/main.c **** LL_TIM_EnableIT_UPDATE(TIM7); 5045 .loc 1 2058 2 is_stmt 1 view .LVU1631 5046 .LBB518: 5047 .LBI518: 1313:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 5048 .loc 5 1313 22 view .LVU1632 5049 .LBB519: 1315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 5050 .loc 5 1315 3 view .LVU1633 5051 00b0 1A68 ldr r2, [r3] 5052 00b2 42F00102 orr r2, r2, #1 5053 00b6 1A60 str r2, [r3] 5054 .LVL410: 1315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 5055 .loc 5 1315 3 is_stmt 0 view .LVU1634 5056 .LBE519: 5057 .LBE518: 2059:Src/main.c **** LL_TIM_EnableCounter(TIM7); 5058 .loc 1 2059 2 is_stmt 1 view .LVU1635 ARM GAS /tmp/ccYgfTud.s page 327 5059 .LBB520: 5060 .LBI520: 4090:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 5061 .loc 5 4090 22 view .LVU1636 5062 .LBB521: 5063 .loc 5 4092 3 view .LVU1637 5064 00b8 03F58063 add r3, r3, #1024 5065 00bc DA68 ldr r2, [r3, #12] 5066 00be 42F00102 orr r2, r2, #1 5067 00c2 DA60 str r2, [r3, #12] 5068 .LVL411: 5069 .loc 5 4092 3 is_stmt 0 view .LVU1638 5070 .LBE521: 5071 .LBE520: 2060:Src/main.c **** //HAL_TIM_Base_Start_IT(&htim6); 5072 .loc 1 2060 2 is_stmt 1 view .LVU1639 5073 .LBB522: 5074 .LBI522: 1313:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 5075 .loc 5 1313 22 view .LVU1640 5076 .LBB523: 1315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 5077 .loc 5 1315 3 view .LVU1641 5078 00c4 1A68 ldr r2, [r3] 5079 00c6 42F00102 orr r2, r2, #1 5080 00ca 1A60 str r2, [r3] 5081 .LVL412: 1315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 5082 .loc 5 1315 3 is_stmt 0 view .LVU1642 5083 .LBE523: 5084 .LBE522: 2067:Src/main.c **** LL_DMA_ClearFlag_TC7(DMA2); 5085 .loc 1 2067 3 is_stmt 1 view .LVU1643 5086 .LBB524: 5087 .LBI524: 5088 .file 6 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h" 1:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 2:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** ****************************************************************************** 3:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @file stm32f7xx_ll_dma.h 4:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @author MCD Application Team 5:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Header file of DMA LL module. 6:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** ****************************************************************************** 7:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @attention 8:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * 9:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * Copyright (c) 2017 STMicroelectronics. 10:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * All rights reserved. 11:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * 12:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * This software is licensed under terms that can be found in the LICENSE file in 13:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * the root directory of this software component. 14:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * If no LICENSE file comes with this software, it is provided AS-IS. 15:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * 16:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** ****************************************************************************** 17:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 18:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 19:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /* Define to prevent recursive inclusion -------------------------------------*/ 20:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #ifndef __STM32F7xx_LL_DMA_H 21:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define __STM32F7xx_LL_DMA_H ARM GAS /tmp/ccYgfTud.s page 328 22:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 23:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #ifdef __cplusplus 24:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** extern "C" { 25:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #endif 26:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 27:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /* Includes ------------------------------------------------------------------*/ 28:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #include "stm32f7xx.h" 29:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 30:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @addtogroup STM32F7xx_LL_Driver 31:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @{ 32:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 33:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 34:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #if defined (DMA1) || defined (DMA2) 35:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 36:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL DMA 37:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @{ 38:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 39:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 40:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /* Private types -------------------------------------------------------------*/ 41:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /* Private variables ---------------------------------------------------------*/ 42:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_Private_Variables DMA Private Variables 43:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @{ 44:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 45:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /* Array used to get the DMA stream register offset versus stream index LL_DMA_STREAM_x */ 46:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** static const uint8_t STREAM_OFFSET_TAB[] = 47:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 48:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** (uint8_t)(DMA1_Stream0_BASE - DMA1_BASE), 49:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** (uint8_t)(DMA1_Stream1_BASE - DMA1_BASE), 50:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** (uint8_t)(DMA1_Stream2_BASE - DMA1_BASE), 51:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** (uint8_t)(DMA1_Stream3_BASE - DMA1_BASE), 52:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** (uint8_t)(DMA1_Stream4_BASE - DMA1_BASE), 53:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** (uint8_t)(DMA1_Stream5_BASE - DMA1_BASE), 54:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** (uint8_t)(DMA1_Stream6_BASE - DMA1_BASE), 55:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** (uint8_t)(DMA1_Stream7_BASE - DMA1_BASE) 56:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }; 57:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 58:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 59:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @} 60:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 61:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 62:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /* Private constants ---------------------------------------------------------*/ 63:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_Private_Constants DMA Private Constants 64:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @{ 65:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 66:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #if defined(DMA_SxCR_CHSEL_3) 67:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define DMA_CHANNEL_SELECTION_8_15 68:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #endif /* DMA_SxCR_CHSEL_3 */ 69:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 70:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @} 71:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 72:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 73:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 74:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /* Private macros ------------------------------------------------------------*/ 75:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /* Exported types ------------------------------------------------------------*/ 76:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #if defined(USE_FULL_LL_DRIVER) 77:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_ES_INIT DMA Exported Init structure 78:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @{ ARM GAS /tmp/ccYgfTud.s page 329 79:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 80:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** typedef struct 81:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 82:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** uint32_t PeriphOrM2MSrcAddress; /*!< Specifies the peripheral base address for DMA transfer 83:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** or as Source base address in case of memory to memory trans 84:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 85:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** This parameter must be a value between Min_Data = 0 and Max 86:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 87:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** uint32_t MemoryOrM2MDstAddress; /*!< Specifies the memory base address for DMA transfer 88:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** or as Destination base address in case of memory to memory 89:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 90:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** This parameter must be a value between Min_Data = 0 and Max 91:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 92:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** uint32_t Direction; /*!< Specifies if the data will be transferred from memory to pe 93:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** from memory to memory or from peripheral to memory. 94:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** This parameter can be a value of @ref DMA_LL_EC_DIRECTION 95:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 96:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** This feature can be modified afterwards using unitary funct 97:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 98:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** uint32_t Mode; /*!< Specifies the normal or circular operation mode. 99:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** This parameter can be a value of @ref DMA_LL_EC_MODE 100:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** @note The circular buffer mode cannot be used if the memory 101:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** data transfer direction is configured on the selected 102:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 103:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** This feature can be modified afterwards using unitary funct 104:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 105:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** uint32_t PeriphOrM2MSrcIncMode; /*!< Specifies whether the Peripheral address or Source address 106:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** is incremented or not. 107:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** This parameter can be a value of @ref DMA_LL_EC_PERIPH 108:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 109:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** This feature can be modified afterwards using unitary funct 110:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 111:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** uint32_t MemoryOrM2MDstIncMode; /*!< Specifies whether the Memory address or Destination address 112:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** is incremented or not. 113:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** This parameter can be a value of @ref DMA_LL_EC_MEMORY 114:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 115:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** This feature can be modified afterwards using unitary funct 116:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 117:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** uint32_t PeriphOrM2MSrcDataSize; /*!< Specifies the Peripheral data size alignment or Source data 118:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** in case of memory to memory transfer direction. 119:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** This parameter can be a value of @ref DMA_LL_EC_PDATAALIGN 120:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 121:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** This feature can be modified afterwards using unitary funct 122:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 123:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** uint32_t MemoryOrM2MDstDataSize; /*!< Specifies the Memory data size alignment or Destination dat 124:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** in case of memory to memory transfer direction. 125:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** This parameter can be a value of @ref DMA_LL_EC_MDATAALIGN 126:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 127:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** This feature can be modified afterwards using unitary funct 128:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 129:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** uint32_t NbData; /*!< Specifies the number of data to transfer, in data unit. 130:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** The data unit is equal to the source buffer configuration s 131:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** or MemorySize parameters depending in the transfer directio 132:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** This parameter must be a value between Min_Data = 0 and Max 133:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 134:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** This feature can be modified afterwards using unitary funct 135:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** ARM GAS /tmp/ccYgfTud.s page 330 136:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** uint32_t Channel; /*!< Specifies the peripheral channel. 137:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** This parameter can be a value of @ref DMA_LL_EC_CHANNEL 138:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 139:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** This feature can be modified afterwards using unitary funct 140:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 141:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** uint32_t Priority; /*!< Specifies the channel priority level. 142:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** This parameter can be a value of @ref DMA_LL_EC_PRIORITY 143:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 144:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** This feature can be modified afterwards using unitary funct 145:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 146:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** uint32_t FIFOMode; /*!< Specifies if the FIFO mode or Direct mode will be used for 147:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** This parameter can be a value of @ref DMA_LL_FIFOMODE 148:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** @note The Direct mode (FIFO mode disabled) cannot be used i 149:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** memory-to-memory data transfer is configured on the selecte 150:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 151:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** This feature can be modified afterwards using unitary funct 152:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 153:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** uint32_t FIFOThreshold; /*!< Specifies the FIFO threshold level. 154:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** This parameter can be a value of @ref DMA_LL_EC_FIFOTHRESHO 155:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 156:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** This feature can be modified afterwards using unitary funct 157:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 158:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** uint32_t MemBurst; /*!< Specifies the Burst transfer configuration for the memory t 159:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** It specifies the amount of data to be transferred in a sing 160:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** transaction. 161:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** This parameter can be a value of @ref DMA_LL_EC_MBURST 162:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** @note The burst mode is possible only if the address Increm 163:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 164:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** This feature can be modified afterwards using unitary funct 165:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 166:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** uint32_t PeriphBurst; /*!< Specifies the Burst transfer configuration for the peripher 167:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** It specifies the amount of data to be transferred in a sing 168:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** transaction. 169:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** This parameter can be a value of @ref DMA_LL_EC_PBURST 170:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** @note The burst mode is possible only if the address Increm 171:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 172:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** This feature can be modified afterwards using unitary funct 173:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 174:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } LL_DMA_InitTypeDef; 175:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 176:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @} 177:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 178:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #endif /*USE_FULL_LL_DRIVER*/ 179:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /* Exported constants --------------------------------------------------------*/ 180:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_Exported_Constants DMA Exported Constants 181:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @{ 182:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 183:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 184:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_EC_STREAM STREAM 185:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @{ 186:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 187:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_STREAM_0 0x00000000U 188:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_STREAM_1 0x00000001U 189:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_STREAM_2 0x00000002U 190:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_STREAM_3 0x00000003U 191:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_STREAM_4 0x00000004U 192:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_STREAM_5 0x00000005U ARM GAS /tmp/ccYgfTud.s page 331 193:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_STREAM_6 0x00000006U 194:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_STREAM_7 0x00000007U 195:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_STREAM_ALL 0xFFFF0000U 196:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 197:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @} 198:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 199:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 200:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_EC_DIRECTION DIRECTION 201:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @{ 202:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 203:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_DIRECTION_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direc 204:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_DIRECTION_MEMORY_TO_PERIPH DMA_SxCR_DIR_0 /*!< Memory to peripheral direc 205:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_DIRECTION_MEMORY_TO_MEMORY DMA_SxCR_DIR_1 /*!< Memory to memory direction 206:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 207:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @} 208:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 209:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 210:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_EC_MODE MODE 211:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @{ 212:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 213:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_MODE_NORMAL 0x00000000U /*!< Normal Mode 214:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_MODE_CIRCULAR DMA_SxCR_CIRC /*!< Circular Mode 215:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_MODE_PFCTRL DMA_SxCR_PFCTRL /*!< Peripheral flow control mo 216:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 217:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @} 218:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 219:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 220:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_EC_DOUBLEBUFFER_MODE DOUBLE BUFFER MODE 221:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @{ 222:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 223:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_DOUBLEBUFFER_MODE_DISABLE 0x00000000U /*!< Disable double buffering m 224:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_DOUBLEBUFFER_MODE_ENABLE DMA_SxCR_DBM /*!< Enable double buffering mo 225:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 226:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @} 227:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 228:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 229:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_EC_PERIPH PERIPH 230:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @{ 231:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 232:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_PERIPH_NOINCREMENT 0x00000000U /*!< Peripheral increment mode 233:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_PERIPH_INCREMENT DMA_SxCR_PINC /*!< Peripheral increment mode 234:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 235:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @} 236:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 237:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 238:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_EC_MEMORY MEMORY 239:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @{ 240:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 241:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_MEMORY_NOINCREMENT 0x00000000U /*!< Memory increment mode Disa 242:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_MEMORY_INCREMENT DMA_SxCR_MINC /*!< Memory increment mode Enab 243:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 244:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @} 245:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 246:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 247:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_EC_PDATAALIGN PDATAALIGN 248:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @{ 249:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ ARM GAS /tmp/ccYgfTud.s page 332 250:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_PDATAALIGN_BYTE 0x00000000U /*!< Peripheral data alignment 251:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_PDATAALIGN_HALFWORD DMA_SxCR_PSIZE_0 /*!< Peripheral data alignment 252:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_PDATAALIGN_WORD DMA_SxCR_PSIZE_1 /*!< Peripheral data alignment 253:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 254:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @} 255:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 256:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 257:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_EC_MDATAALIGN MDATAALIGN 258:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @{ 259:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 260:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_MDATAALIGN_BYTE 0x00000000U /*!< Memory data alignment : By 261:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_MDATAALIGN_HALFWORD DMA_SxCR_MSIZE_0 /*!< Memory data alignment : Ha 262:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_MDATAALIGN_WORD DMA_SxCR_MSIZE_1 /*!< Memory data alignment : Wo 263:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 264:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @} 265:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 266:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 267:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_EC_OFFSETSIZE OFFSETSIZE 268:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @{ 269:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 270:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_OFFSETSIZE_PSIZE 0x00000000U /*!< Peripheral increment offse 271:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_OFFSETSIZE_FIXEDTO4 DMA_SxCR_PINCOS /*!< Peripheral increment offse 272:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 273:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @} 274:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 275:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 276:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_EC_PRIORITY PRIORITY 277:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @{ 278:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 279:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_PRIORITY_LOW 0x00000000U /*!< Priority level : Low 280:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_PRIORITY_MEDIUM DMA_SxCR_PL_0 /*!< Priority level : Medium 281:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_PRIORITY_HIGH DMA_SxCR_PL_1 /*!< Priority level : High 282:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_PRIORITY_VERYHIGH DMA_SxCR_PL /*!< Priority level : Very_High 283:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 284:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @} 285:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 286:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 287:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_EC_CHANNEL CHANNEL 288:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @{ 289:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 290:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_CHANNEL_0 0x00000000U 291:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_CHANNEL_1 DMA_SxCR_CHSEL_0 292:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_CHANNEL_2 DMA_SxCR_CHSEL_1 293:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_CHANNEL_3 (DMA_SxCR_CHSEL_0 | DMA_SxCR_CHSEL_1) 294:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_CHANNEL_4 DMA_SxCR_CHSEL_2 295:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_CHANNEL_5 (DMA_SxCR_CHSEL_2 | DMA_SxCR_CHSEL_0) 296:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_CHANNEL_6 (DMA_SxCR_CHSEL_2 | DMA_SxCR_CHSEL_1) 297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_CHANNEL_7 (DMA_SxCR_CHSEL_2 | DMA_SxCR_CHSEL_1 | DMA_SxCR_CHSEL_0) 298:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #if defined(DMA_CHANNEL_SELECTION_8_15) 299:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_CHANNEL_8 DMA_SxCR_CHSEL_3 300:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_CHANNEL_9 (DMA_SxCR_CHSEL_3 | DMA_SxCR_CHSEL_0) 301:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_CHANNEL_10 (DMA_SxCR_CHSEL_3 | DMA_SxCR_CHSEL_1) 302:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_CHANNEL_11 (DMA_SxCR_CHSEL_3 | DMA_SxCR_CHSEL_1 | DMA_SxCR_CHSEL_0) 303:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_CHANNEL_12 (DMA_SxCR_CHSEL_3 | DMA_SxCR_CHSEL_2) 304:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_CHANNEL_13 (DMA_SxCR_CHSEL_3 | DMA_SxCR_CHSEL_2 | DMA_SxCR_CHSEL_0) 305:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_CHANNEL_14 (DMA_SxCR_CHSEL_3 | DMA_SxCR_CHSEL_2 | DMA_SxCR_CHSEL_1) 306:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_CHANNEL_15 DMA_SxCR_CHSEL ARM GAS /tmp/ccYgfTud.s page 333 307:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #endif /* DMA_CHANNEL_SELECTION_8_15 */ 308:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 309:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @} 310:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 311:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 312:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_EC_MBURST MBURST 313:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @{ 314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_MBURST_SINGLE 0x00000000U /*!< Memory burst 316:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_MBURST_INC4 DMA_SxCR_MBURST_0 /*!< Memory burst 317:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_MBURST_INC8 DMA_SxCR_MBURST_1 /*!< Memory burst 318:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_MBURST_INC16 (DMA_SxCR_MBURST_0 | DMA_SxCR_MBURST_1) /*!< Memory burst 319:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 320:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @} 321:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 322:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 323:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_EC_PBURST PBURST 324:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @{ 325:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 326:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_PBURST_SINGLE 0x00000000U /*!< Peripheral b 327:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_PBURST_INC4 DMA_SxCR_PBURST_0 /*!< Peripheral b 328:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_PBURST_INC8 DMA_SxCR_PBURST_1 /*!< Peripheral b 329:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_PBURST_INC16 (DMA_SxCR_PBURST_0 | DMA_SxCR_PBURST_1) /*!< Peripheral b 330:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 331:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @} 332:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 333:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 334:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_FIFOMODE DMA_LL_FIFOMODE 335:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @{ 336:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 337:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_FIFOMODE_DISABLE 0x00000000U /*!< FIFO mode di 338:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_FIFOMODE_ENABLE DMA_SxFCR_DMDIS /*!< FIFO mode en 339:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 340:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @} 341:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 342:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 343:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_EC_FIFOSTATUS_0 FIFOSTATUS 0 344:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @{ 345:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_FIFOSTATUS_0_25 0x00000000U /*!< 0 < fifo_lev 347:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_FIFOSTATUS_25_50 DMA_SxFCR_FS_0 /*!< 1/4 < fifo_l 348:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_FIFOSTATUS_50_75 DMA_SxFCR_FS_1 /*!< 1/2 < fifo_l 349:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_FIFOSTATUS_75_100 (DMA_SxFCR_FS_1 | DMA_SxFCR_FS_0) /*!< 3/4 < fifo_l 350:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_FIFOSTATUS_EMPTY DMA_SxFCR_FS_2 /*!< FIFO is empt 351:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_FIFOSTATUS_FULL (DMA_SxFCR_FS_2 | DMA_SxFCR_FS_0) /*!< FIFO is full 352:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 353:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @} 354:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 355:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 356:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_EC_FIFOTHRESHOLD FIFOTHRESHOLD 357:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @{ 358:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 359:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_FIFOTHRESHOLD_1_4 0x00000000U /*!< FIFO thresho 360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_FIFOTHRESHOLD_1_2 DMA_SxFCR_FTH_0 /*!< FIFO thresho 361:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_FIFOTHRESHOLD_3_4 DMA_SxFCR_FTH_1 /*!< FIFO thresho 362:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_FIFOTHRESHOLD_FULL DMA_SxFCR_FTH /*!< FIFO thresho 363:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** ARM GAS /tmp/ccYgfTud.s page 334 364:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @} 365:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 366:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 367:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_EC_CURRENTTARGETMEM CURRENTTARGETMEM 368:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @{ 369:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_CURRENTTARGETMEM0 0x00000000U /*!< Set CurrentT 371:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_CURRENTTARGETMEM1 DMA_SxCR_CT /*!< Set CurrentT 372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @} 374:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 375:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 376:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 377:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @} 378:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 379:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 380:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /* Exported macro ------------------------------------------------------------*/ 381:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_Exported_Macros DMA Exported Macros 382:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @{ 383:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 384:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 385:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_EM_WRITE_READ Common Write and read registers macros 386:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @{ 387:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 388:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 389:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Write a value in DMA register 390:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param __INSTANCE__ DMA Instance 391:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param __REG__ Register to be written 392:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param __VALUE__ Value to be written in the register 393:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 394:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 395:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE 396:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 397:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 398:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Read a value in DMA register 399:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param __INSTANCE__ DMA Instance 400:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param __REG__ Register to be read 401:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval Register value 402:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 403:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) 404:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 405:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @} 406:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 407:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 408:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_EM_CONVERT_DMAxCHANNELy Convert DMAxStreamy 409:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @{ 410:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 411:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 412:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Convert DMAx_Streamy into DMAx 413:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param __STREAM_INSTANCE__ DMAx_Streamy 414:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval DMAx 415:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 416:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define __LL_DMA_GET_INSTANCE(__STREAM_INSTANCE__) \ 417:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** (((uint32_t)(__STREAM_INSTANCE__) > ((uint32_t)DMA1_Stream7)) ? DMA2 : DMA1) 418:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 419:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 420:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Convert DMAx_Streamy into LL_DMA_STREAM_y ARM GAS /tmp/ccYgfTud.s page 335 421:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param __STREAM_INSTANCE__ DMAx_Streamy 422:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval LL_DMA_CHANNEL_y 423:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 424:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define __LL_DMA_GET_STREAM(__STREAM_INSTANCE__) \ 425:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** (((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream0)) ? LL_DMA_STREAM_0 : \ 426:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream0)) ? LL_DMA_STREAM_0 : \ 427:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream1)) ? LL_DMA_STREAM_1 : \ 428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream1)) ? LL_DMA_STREAM_1 : \ 429:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream2)) ? LL_DMA_STREAM_2 : \ 430:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream2)) ? LL_DMA_STREAM_2 : \ 431:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream3)) ? LL_DMA_STREAM_3 : \ 432:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream3)) ? LL_DMA_STREAM_3 : \ 433:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream4)) ? LL_DMA_STREAM_4 : \ 434:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream4)) ? LL_DMA_STREAM_4 : \ 435:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream5)) ? LL_DMA_STREAM_5 : \ 436:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream5)) ? LL_DMA_STREAM_5 : \ 437:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream6)) ? LL_DMA_STREAM_6 : \ 438:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream6)) ? LL_DMA_STREAM_6 : \ 439:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** LL_DMA_STREAM_7) 440:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 441:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 442:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Convert DMA Instance DMAx and LL_DMA_STREAM_y into DMAx_Streamy 443:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param __DMA_INSTANCE__ DMAx 444:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param __STREAM__ LL_DMA_STREAM_y 445:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval DMAx_Streamy 446:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 447:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define __LL_DMA_GET_STREAM_INSTANCE(__DMA_INSTANCE__, __STREAM__) \ 448:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** ((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DM 449:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DM 450:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DM 451:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DM 452:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DM 453:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DM 454:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DM 455:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DM 456:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DM 457:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DM 458:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DM 459:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DM 460:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DM 461:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DM 462:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DM 463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** DMA2_Stream7) 464:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 465:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 466:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @} 467:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 468:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 469:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 470:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @} 471:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 472:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 473:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 474:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /* Exported functions --------------------------------------------------------*/ 475:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_Exported_Functions DMA Exported Functions 476:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @{ 477:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ ARM GAS /tmp/ccYgfTud.s page 336 478:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 479:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_EF_Configuration Configuration 480:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @{ 481:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 482:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 483:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Enable DMA stream. 484:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR EN LL_DMA_EnableStream 485:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 486:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: 487:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 488:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 489:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 490:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 491:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 492:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 493:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 494:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 495:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 496:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 497:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_EnableStream(DMA_TypeDef *DMAx, uint32_t Stream) 498:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 499:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA 500:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 501:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 502:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 503:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Disable DMA stream. 504:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR EN LL_DMA_DisableStream 505:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 506:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: 507:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 508:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 509:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 510:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 511:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 512:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 513:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 514:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 515:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 516:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 517:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_DisableStream(DMA_TypeDef *DMAx, uint32_t Stream) 5089 .loc 6 517 22 view .LVU1644 5090 .LBB525: 518:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 519:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, D 5091 .loc 6 519 3 view .LVU1645 5092 00cc 03F51433 add r3, r3, #151552 5093 00d0 D3F8B820 ldr r2, [r3, #184] 5094 00d4 22F00102 bic r2, r2, #1 5095 00d8 C3F8B820 str r2, [r3, #184] 5096 .LVL413: 5097 .loc 6 519 3 is_stmt 0 view .LVU1646 5098 .LBE525: 5099 .LBE524: 2068:Src/main.c **** LL_DMA_ClearFlag_TE7(DMA2); 5100 .loc 1 2068 3 is_stmt 1 view .LVU1647 5101 .LBB526: 5102 .LBI526: ARM GAS /tmp/ccYgfTud.s page 337 520:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 521:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 522:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 523:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Check if DMA stream is enabled or disabled. 524:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR EN LL_DMA_IsEnabledStream 525:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 526:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: 527:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 528:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 529:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 530:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 531:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 532:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 533:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 534:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 535:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). 536:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 537:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsEnabledStream(DMA_TypeDef *DMAx, uint32_t Stream) 538:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 539:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))- 540:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 541:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 542:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 543:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Configure all parameters linked to DMA transfer. 544:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR DIR LL_DMA_ConfigTransfer\n 545:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * CR CIRC LL_DMA_ConfigTransfer\n 546:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * CR PINC LL_DMA_ConfigTransfer\n 547:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * CR MINC LL_DMA_ConfigTransfer\n 548:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * CR PSIZE LL_DMA_ConfigTransfer\n 549:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * CR MSIZE LL_DMA_ConfigTransfer\n 550:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * CR PL LL_DMA_ConfigTransfer\n 551:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * CR PFCTRL LL_DMA_ConfigTransfer 552:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 553:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: 554:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 555:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 556:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 557:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 558:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 559:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 560:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 561:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 562:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Configuration This parameter must be a combination of all the following values: 563:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY or @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH o 564:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_MODE_NORMAL or @ref LL_DMA_MODE_CIRCULAR or @ref LL_DMA_MODE_PFCTRL 565:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_PERIPH_INCREMENT or @ref LL_DMA_PERIPH_NOINCREMENT 566:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_MEMORY_INCREMENT or @ref LL_DMA_MEMORY_NOINCREMENT 567:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_PDATAALIGN_BYTE or @ref LL_DMA_PDATAALIGN_HALFWORD or @ref LL_DMA_PDAT 568:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_MDATAALIGN_BYTE or @ref LL_DMA_MDATAALIGN_HALFWORD or @ref LL_DMA_MDAT 569:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_PRIORITY_LOW or @ref LL_DMA_PRIORITY_MEDIUM or @ref LL_DMA_PRIORITY_HI 570:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** *@retval None 571:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 572:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ConfigTransfer(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Configurati 573:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 574:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** MODIFY_REG(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, 575:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** DMA_SxCR_DIR | DMA_SxCR_CIRC | DMA_SxCR_PINC | DMA_SxCR_MINC | DMA_SxCR_PSIZE | DMA_Sx 576:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** Configuration); ARM GAS /tmp/ccYgfTud.s page 338 577:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 578:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 579:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 580:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Set Data transfer direction (read from peripheral or from memory). 581:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR DIR LL_DMA_SetDataTransferDirection 582:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 583:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: 584:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 585:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 586:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 587:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 588:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 589:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 590:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 591:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 592:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Direction This parameter can be one of the following values: 593:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY 594:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH 595:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY 596:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 597:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 598:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_SetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t 599:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 600:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, D 601:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 602:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 603:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 604:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Data transfer direction (read from peripheral or from memory). 605:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR DIR LL_DMA_GetDataTransferDirection 606:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 607:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: 608:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 609:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 610:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 611:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 612:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 613:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 614:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 615:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 616:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval Returned value can be one of the following values: 617:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY 618:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH 619:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY 620:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 621:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Stream) 622:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 623:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))- 624:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 625:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 626:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 627:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Set DMA mode normal, circular or peripheral flow control. 628:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR CIRC LL_DMA_SetMode\n 629:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * CR PFCTRL LL_DMA_SetMode 630:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 631:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: 632:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 633:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 ARM GAS /tmp/ccYgfTud.s page 339 634:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 635:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 636:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 637:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 638:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 639:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 640:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Mode This parameter can be one of the following values: 641:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_MODE_NORMAL 642:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_MODE_CIRCULAR 643:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_MODE_PFCTRL 644:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 645:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 646:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_SetMode(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Mode) 647:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 648:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, D 649:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 650:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 651:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 652:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get DMA mode normal, circular or peripheral flow control. 653:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR CIRC LL_DMA_GetMode\n 654:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * CR PFCTRL LL_DMA_GetMode 655:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 656:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: 657:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 658:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 659:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 660:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 661:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 662:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 663:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 664:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 665:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval Returned value can be one of the following values: 666:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_MODE_NORMAL 667:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_MODE_CIRCULAR 668:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_MODE_PFCTRL 669:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 670:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_GetMode(DMA_TypeDef *DMAx, uint32_t Stream) 671:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 672:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))- 673:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 674:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 675:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 676:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Set Peripheral increment mode. 677:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR PINC LL_DMA_SetPeriphIncMode 678:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 679:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: 680:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 681:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 682:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 683:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 684:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 685:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 686:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 687:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 688:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param IncrementMode This parameter can be one of the following values: 689:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_PERIPH_NOINCREMENT 690:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_PERIPH_INCREMENT ARM GAS /tmp/ccYgfTud.s page 340 691:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 692:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 693:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_SetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Increment 694:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 695:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, D 696:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 697:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 698:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 699:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Peripheral increment mode. 700:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR PINC LL_DMA_GetPeriphIncMode 701:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 702:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: 703:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 704:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 705:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 706:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 707:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 708:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 709:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 710:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 711:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval Returned value can be one of the following values: 712:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_PERIPH_NOINCREMENT 713:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_PERIPH_INCREMENT 714:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 715:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_GetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Stream) 716:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 717:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))- 718:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 719:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 720:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 721:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Set Memory increment mode. 722:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR MINC LL_DMA_SetMemoryIncMode 723:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 724:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: 725:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 726:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 727:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 728:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 729:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 730:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 731:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 732:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 733:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param IncrementMode This parameter can be one of the following values: 734:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_MEMORY_NOINCREMENT 735:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_MEMORY_INCREMENT 736:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 737:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 738:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_SetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Increment 739:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 740:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, D 741:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 742:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 743:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 744:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Memory increment mode. 745:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR MINC LL_DMA_GetMemoryIncMode 746:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 747:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: ARM GAS /tmp/ccYgfTud.s page 341 748:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 749:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 750:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 751:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 752:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 753:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 754:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 755:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 756:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval Returned value can be one of the following values: 757:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_MEMORY_NOINCREMENT 758:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_MEMORY_INCREMENT 759:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 760:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Stream) 761:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 762:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))- 763:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 764:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 765:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 766:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Set Peripheral size. 767:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR PSIZE LL_DMA_SetPeriphSize 768:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 769:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: 770:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 771:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 772:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 773:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 774:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 775:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 776:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 777:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 778:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Size This parameter can be one of the following values: 779:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_PDATAALIGN_BYTE 780:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_PDATAALIGN_HALFWORD 781:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_PDATAALIGN_WORD 782:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 783:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 784:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_SetPeriphSize(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Size) 785:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 786:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, D 787:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 788:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 789:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 790:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Peripheral size. 791:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR PSIZE LL_DMA_GetPeriphSize 792:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 793:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: 794:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 795:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 796:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 797:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 798:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 799:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 800:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 801:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 802:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval Returned value can be one of the following values: 803:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_PDATAALIGN_BYTE 804:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_PDATAALIGN_HALFWORD ARM GAS /tmp/ccYgfTud.s page 342 805:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_PDATAALIGN_WORD 806:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 807:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_GetPeriphSize(DMA_TypeDef *DMAx, uint32_t Stream) 808:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 809:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))- 810:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 811:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 812:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 813:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Set Memory size. 814:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR MSIZE LL_DMA_SetMemorySize 815:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 816:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: 817:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 818:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 819:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 820:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 821:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 822:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 823:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 824:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 825:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Size This parameter can be one of the following values: 826:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_MDATAALIGN_BYTE 827:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_MDATAALIGN_HALFWORD 828:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_MDATAALIGN_WORD 829:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 830:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 831:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_SetMemorySize(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Size) 832:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 833:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, D 834:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 835:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 836:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 837:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Memory size. 838:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR MSIZE LL_DMA_GetMemorySize 839:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 840:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: 841:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 842:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 843:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 844:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 845:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 846:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 847:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 848:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 849:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval Returned value can be one of the following values: 850:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_MDATAALIGN_BYTE 851:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_MDATAALIGN_HALFWORD 852:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_MDATAALIGN_WORD 853:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 854:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_GetMemorySize(DMA_TypeDef *DMAx, uint32_t Stream) 855:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 856:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))- 857:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 858:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 859:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 860:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Set Peripheral increment offset size. 861:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR PINCOS LL_DMA_SetIncOffsetSize ARM GAS /tmp/ccYgfTud.s page 343 862:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 863:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: 864:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 865:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 866:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 867:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 868:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 869:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 870:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 871:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 872:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param OffsetSize This parameter can be one of the following values: 873:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_OFFSETSIZE_PSIZE 874:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_OFFSETSIZE_FIXEDTO4 875:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 876:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 877:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_SetIncOffsetSize(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t OffsetSiz 878:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 879:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, D 880:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 881:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 882:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 883:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Peripheral increment offset size. 884:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR PINCOS LL_DMA_GetIncOffsetSize 885:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 886:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: 887:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 888:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 889:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 890:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 891:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 892:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 893:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 894:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 895:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval Returned value can be one of the following values: 896:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_OFFSETSIZE_PSIZE 897:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_OFFSETSIZE_FIXEDTO4 898:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 899:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_GetIncOffsetSize(DMA_TypeDef *DMAx, uint32_t Stream) 900:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 901:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))- 902:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 903:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 904:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 905:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Set Stream priority level. 906:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR PL LL_DMA_SetStreamPriorityLevel 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 908:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: 909:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 910:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 911:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 912:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 913:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 914:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 915:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 916:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 917:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Priority This parameter can be one of the following values: 918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_PRIORITY_LOW ARM GAS /tmp/ccYgfTud.s page 344 919:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_PRIORITY_MEDIUM 920:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_PRIORITY_HIGH 921:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_PRIORITY_VERYHIGH 922:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 923:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 924:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_SetStreamPriorityLevel(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Pr 925:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 926:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, D 927:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 928:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 929:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 930:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream priority level. 931:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR PL LL_DMA_GetStreamPriorityLevel 932:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 933:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: 934:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 935:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 936:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 937:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 938:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 939:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 940:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 941:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 942:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval Returned value can be one of the following values: 943:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_PRIORITY_LOW 944:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_PRIORITY_MEDIUM 945:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_PRIORITY_HIGH 946:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_PRIORITY_VERYHIGH 947:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 948:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_GetStreamPriorityLevel(DMA_TypeDef *DMAx, uint32_t Stream) 949:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 950:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))- 951:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 952:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 953:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 954:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Set Number of data to transfer. 955:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll NDTR NDT LL_DMA_SetDataLength 956:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @note This action has no effect if 957:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * stream is enabled. 958:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 959:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: 960:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 961:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 962:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 963:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 964:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 965:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 966:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 967:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 968:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param NbData Between 0 to 0xFFFFFFFF 969:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 970:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 971:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_SetDataLength(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t NbData) 972:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 973:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->NDTR, 974:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 975:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** ARM GAS /tmp/ccYgfTud.s page 345 976:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 977:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Number of data to transfer. 978:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll NDTR NDT LL_DMA_GetDataLength 979:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @note Once the stream is enabled, the return value indicate the 980:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * remaining bytes to be transmitted. 981:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 982:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: 983:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 984:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 985:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 986:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 987:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 988:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 989:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 990:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 991:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval Between 0 to 0xFFFFFFFF 992:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 993:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_GetDataLength(DMA_TypeDef* DMAx, uint32_t Stream) 994:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 995:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))- 996:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 997:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 998:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 999:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Select Channel number associated to the Stream. 1000:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR CHSEL LL_DMA_SetChannelSelection 1001:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 1002:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: 1003:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 1004:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 1005:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 1006:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 1007:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 1008:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 1009:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 1010:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 1011:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Channel This parameter can be one of the following values: 1012:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_0 1013:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_1 1014:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_2 1015:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_3 1016:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_4 1017:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_5 1018:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_6 1019:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_7 1020:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_8 (*) 1021:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_9 (*) 1022:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_10 (*) 1023:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_11 (*) 1024:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_12 (*) 1025:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_13 (*) 1026:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_14 (*) 1027:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_15 (*) 1028:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * 1029:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * (*) value not defined in all devices. 1030:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 1031:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1032:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_SetChannelSelection(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Channe ARM GAS /tmp/ccYgfTud.s page 346 1033:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1034:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, D 1035:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1036:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1037:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1038:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get the Channel number associated to the Stream. 1039:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR CHSEL LL_DMA_GetChannelSelection 1040:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 1041:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: 1042:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 1043:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 1044:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 1045:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 1046:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 1047:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 1048:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 1049:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 1050:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval Returned value can be one of the following values: 1051:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_0 1052:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_1 1053:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_2 1054:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_3 1055:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_4 1056:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_5 1057:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_6 1058:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_7 1059:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_8 (*) 1060:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_9 (*) 1061:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_10 (*) 1062:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_11 (*) 1063:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_12 (*) 1064:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_13 (*) 1065:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_14 (*) 1066:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_15 (*) 1067:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * 1068:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * (*) value not defined in all devices. 1069:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1070:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_GetChannelSelection(DMA_TypeDef *DMAx, uint32_t Stream) 1071:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1072:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))- 1073:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1074:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1075:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1076:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Set Memory burst transfer configuration. 1077:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR MBURST LL_DMA_SetMemoryBurstxfer 1078:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 1079:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: 1080:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 1081:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 1082:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 1083:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 1084:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 1085:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 1086:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 1087:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 1088:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Mburst This parameter can be one of the following values: 1089:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_MBURST_SINGLE ARM GAS /tmp/ccYgfTud.s page 347 1090:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_MBURST_INC4 1091:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_MBURST_INC8 1092:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_MBURST_INC16 1093:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 1094:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1095:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_SetMemoryBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Mburst) 1096:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1097:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, D 1098:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1099:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1100:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1101:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Memory burst transfer configuration. 1102:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR MBURST LL_DMA_GetMemoryBurstxfer 1103:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 1104:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: 1105:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 1106:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 1107:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 1108:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 1109:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 1110:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 1111:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 1112:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 1113:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval Returned value can be one of the following values: 1114:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_MBURST_SINGLE 1115:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_MBURST_INC4 1116:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_MBURST_INC8 1117:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_MBURST_INC16 1118:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1119:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_GetMemoryBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream) 1120:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1121:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))- 1122:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1123:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1124:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1125:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Set Peripheral burst transfer configuration. 1126:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR PBURST LL_DMA_SetPeriphBurstxfer 1127:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 1128:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: 1129:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 1130:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 1131:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 1132:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 1133:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 1134:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 1135:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 1136:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 1137:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Pburst This parameter can be one of the following values: 1138:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_PBURST_SINGLE 1139:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_PBURST_INC4 1140:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_PBURST_INC8 1141:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_PBURST_INC16 1142:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 1143:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1144:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_SetPeriphBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Pburst) 1145:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1146:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, D ARM GAS /tmp/ccYgfTud.s page 348 1147:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1148:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1149:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1150:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Peripheral burst transfer configuration. 1151:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR PBURST LL_DMA_GetPeriphBurstxfer 1152:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 1153:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: 1154:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 1155:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 1156:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 1157:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 1158:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 1159:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 1160:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 1161:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 1162:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval Returned value can be one of the following values: 1163:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_PBURST_SINGLE 1164:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_PBURST_INC4 1165:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_PBURST_INC8 1166:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_PBURST_INC16 1167:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1168:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_GetPeriphBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream) 1169:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1170:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))- 1171:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1172:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1173:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1174:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Set Current target (only in double buffer mode) to Memory 1 or Memory 0. 1175:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR CT LL_DMA_SetCurrentTargetMem 1176:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 1177:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: 1178:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 1179:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 1180:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 1181:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 1182:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 1183:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 1184:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 1185:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 1186:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param CurrentMemory This parameter can be one of the following values: 1187:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CURRENTTARGETMEM0 1188:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CURRENTTARGETMEM1 1189:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 1190:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1191:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_SetCurrentTargetMem(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Curren 1192:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1193:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, 1194:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1195:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1196:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1197:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Set Current target (only in double buffer mode) to Memory 1 or Memory 0. 1198:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR CT LL_DMA_GetCurrentTargetMem 1199:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 1200:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: 1201:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 1202:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 1203:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 ARM GAS /tmp/ccYgfTud.s page 349 1204:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 1205:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 1206:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 1207:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 1208:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 1209:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval Returned value can be one of the following values: 1210:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CURRENTTARGETMEM0 1211:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CURRENTTARGETMEM1 1212:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1213:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_GetCurrentTargetMem(DMA_TypeDef *DMAx, uint32_t Stream) 1214:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1215:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))- 1216:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1217:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1218:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1219:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Enable the double buffer mode. 1220:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR DBM LL_DMA_EnableDoubleBufferMode 1221:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 1222:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: 1223:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 1224:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 1225:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 1226:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 1227:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 1228:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 1229:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 1230:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 1231:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 1232:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1233:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_EnableDoubleBufferMode(DMA_TypeDef *DMAx, uint32_t Stream) 1234:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1235:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA 1236:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1237:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1238:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1239:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Disable the double buffer mode. 1240:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR DBM LL_DMA_DisableDoubleBufferMode 1241:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 1242:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: 1243:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 1244:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 1245:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 1246:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 1247:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 1248:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 1249:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 1250:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 1251:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 1252:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1253:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_DisableDoubleBufferMode(DMA_TypeDef *DMAx, uint32_t Stream) 1254:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1255:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, D 1256:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1257:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1258:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1259:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get FIFO status. 1260:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll FCR FS LL_DMA_GetFIFOStatus ARM GAS /tmp/ccYgfTud.s page 350 1261:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 1262:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: 1263:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 1264:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 1265:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 1266:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 1267:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 1268:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 1269:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 1270:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 1271:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval Returned value can be one of the following values: 1272:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_FIFOSTATUS_0_25 1273:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_FIFOSTATUS_25_50 1274:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_FIFOSTATUS_50_75 1275:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_FIFOSTATUS_75_100 1276:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_FIFOSTATUS_EMPTY 1277:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_FIFOSTATUS_FULL 1278:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1279:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_GetFIFOStatus(DMA_TypeDef *DMAx, uint32_t Stream) 1280:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1281:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))- 1282:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1283:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1284:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1285:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Disable Fifo mode. 1286:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll FCR DMDIS LL_DMA_DisableFifoMode 1287:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 1288:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: 1289:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 1290:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 1291:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 1292:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 1293:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 1294:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 1295:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 1296:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 1297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 1298:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1299:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_DisableFifoMode(DMA_TypeDef *DMAx, uint32_t Stream) 1300:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1301:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, 1302:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1303:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1304:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1305:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Enable Fifo mode. 1306:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll FCR DMDIS LL_DMA_EnableFifoMode 1307:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 1308:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: 1309:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 1310:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 1311:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 1312:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 1313:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 1314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 1315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 1316:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 1317:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None ARM GAS /tmp/ccYgfTud.s page 351 1318:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1319:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_EnableFifoMode(DMA_TypeDef *DMAx, uint32_t Stream) 1320:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1321:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DM 1322:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1323:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1324:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1325:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Select FIFO threshold. 1326:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll FCR FTH LL_DMA_SetFIFOThreshold 1327:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 1328:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: 1329:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 1330:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 1331:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 1332:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 1333:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 1334:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 1335:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 1336:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 1337:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Threshold This parameter can be one of the following values: 1338:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_FIFOTHRESHOLD_1_4 1339:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_FIFOTHRESHOLD_1_2 1340:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_FIFOTHRESHOLD_3_4 1341:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_FIFOTHRESHOLD_FULL 1342:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 1343:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1344:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_SetFIFOThreshold(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Threshold 1345:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, 1347:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1348:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1349:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1350:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get FIFO threshold. 1351:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll FCR FTH LL_DMA_GetFIFOThreshold 1352:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 1353:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: 1354:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 1355:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 1356:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 1357:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 1358:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 1359:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 1360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 1361:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 1362:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval Returned value can be one of the following values: 1363:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_FIFOTHRESHOLD_1_4 1364:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_FIFOTHRESHOLD_1_2 1365:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_FIFOTHRESHOLD_3_4 1366:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_FIFOTHRESHOLD_FULL 1367:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1368:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_GetFIFOThreshold(DMA_TypeDef *DMAx, uint32_t Stream) 1369:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))- 1371:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1374:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Configure the FIFO . ARM GAS /tmp/ccYgfTud.s page 352 1375:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll FCR FTH LL_DMA_ConfigFifo\n 1376:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * FCR DMDIS LL_DMA_ConfigFifo 1377:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 1378:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: 1379:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 1380:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 1381:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 1382:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 1383:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 1384:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 1385:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 1386:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 1387:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param FifoMode This parameter can be one of the following values: 1388:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_FIFOMODE_ENABLE 1389:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_FIFOMODE_DISABLE 1390:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param FifoThreshold This parameter can be one of the following values: 1391:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_FIFOTHRESHOLD_1_4 1392:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_FIFOTHRESHOLD_1_2 1393:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_FIFOTHRESHOLD_3_4 1394:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_FIFOTHRESHOLD_FULL 1395:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 1396:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1397:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ConfigFifo(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t FifoMode, uint3 1398:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1399:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, 1400:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1401:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1402:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1403:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Configure the Source and Destination addresses. 1404:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @note This API must not be called when the DMA stream is enabled. 1405:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll M0AR M0A LL_DMA_ConfigAddresses\n 1406:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * PAR PA LL_DMA_ConfigAddresses 1407:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 1408:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: 1409:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 1410:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 1411:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 1412:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 1413:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 1414:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 1415:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 1416:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 1417:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param SrcAddress Between 0 to 0xFFFFFFFF 1418:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DstAddress Between 0 to 0xFFFFFFFF 1419:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Direction This parameter can be one of the following values: 1420:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY 1421:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH 1422:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY 1423:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 1424:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1425:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ConfigAddresses(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t SrcAddress 1426:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1427:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /* Direction Memory to Periph */ 1428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** if (Direction == LL_DMA_DIRECTION_MEMORY_TO_PERIPH) 1429:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1430:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR 1431:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR, ARM GAS /tmp/ccYgfTud.s page 353 1432:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1433:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /* Direction Periph to Memory and Memory to Memory */ 1434:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** else 1435:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1436:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR, 1437:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR 1438:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1439:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1440:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1441:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1442:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Set the Memory address. 1443:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll M0AR M0A LL_DMA_SetMemoryAddress 1444:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMO 1445:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @note This API must not be called when the DMA channel is enabled. 1446:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 1447:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: 1448:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 1449:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 1450:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 1451:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 1452:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 1453:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 1454:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 1455:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 1456:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param MemoryAddress Between 0 to 0xFFFFFFFF 1457:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 1458:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1459:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_SetMemoryAddress(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t MemoryAdd 1460:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1461:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR, 1462:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1464:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1465:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Set the Peripheral address. 1466:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll PAR PA LL_DMA_SetPeriphAddress 1467:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMO 1468:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @note This API must not be called when the DMA channel is enabled. 1469:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 1470:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: 1471:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 1472:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 1473:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 1474:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 1475:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 1476:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 1477:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 1478:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 1479:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param PeriphAddress Between 0 to 0xFFFFFFFF 1480:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 1481:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1482:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_SetPeriphAddress(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t PeriphAdd 1483:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1484:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR, P 1485:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1486:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1487:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1488:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get the Memory address. ARM GAS /tmp/ccYgfTud.s page 354 1489:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll M0AR M0A LL_DMA_GetMemoryAddress 1490:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMO 1491:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 1492:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: 1493:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 1494:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 1495:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 1496:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 1497:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 1498:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 1499:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 1500:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 1501:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval Between 0 to 0xFFFFFFFF 1502:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1503:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress(DMA_TypeDef* DMAx, uint32_t Stream) 1504:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1505:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))- 1506:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1507:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1508:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1509:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get the Peripheral address. 1510:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll PAR PA LL_DMA_GetPeriphAddress 1511:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMO 1512:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 1513:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: 1514:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 1515:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 1516:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 1517:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 1518:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 1519:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 1520:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 1521:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 1522:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval Between 0 to 0xFFFFFFFF 1523:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1524:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress(DMA_TypeDef* DMAx, uint32_t Stream) 1525:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1526:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_REG(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream]))) 1527:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1528:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1529:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1530:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Set the Memory to Memory Source address. 1531:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll PAR PA LL_DMA_SetM2MSrcAddress 1532:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only. 1533:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @note This API must not be called when the DMA channel is enabled. 1534:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 1535:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: 1536:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 1537:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 1538:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 1539:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 1540:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 1541:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 1542:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 1543:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 1544:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param MemoryAddress Between 0 to 0xFFFFFFFF 1545:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None ARM GAS /tmp/ccYgfTud.s page 355 1546:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1547:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_SetM2MSrcAddress(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t MemoryAdd 1548:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1549:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR, M 1550:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1551:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1552:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1553:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Set the Memory to Memory Destination address. 1554:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll M0AR M0A LL_DMA_SetM2MDstAddress 1555:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only. 1556:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @note This API must not be called when the DMA channel is enabled. 1557:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 1558:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: 1559:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 1560:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 1561:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 1562:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 1563:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 1564:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 1565:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 1566:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 1567:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param MemoryAddress Between 0 to 0xFFFFFFFF 1568:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 1569:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1570:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_SetM2MDstAddress(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t MemoryAdd 1571:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1572:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR 1573:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1574:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1575:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1576:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get the Memory to Memory Source address. 1577:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll PAR PA LL_DMA_GetM2MSrcAddress 1578:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only. 1579:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 1580:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: 1581:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 1582:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 1583:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 1584:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 1585:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 1586:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 1587:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 1588:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 1589:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval Between 0 to 0xFFFFFFFF 1590:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1591:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress(DMA_TypeDef* DMAx, uint32_t Stream) 1592:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1593:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_REG(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])) 1594:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1595:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1596:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1597:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get the Memory to Memory Destination address. 1598:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll M0AR M0A LL_DMA_GetM2MDstAddress 1599:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only. 1600:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 1601:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: 1602:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 ARM GAS /tmp/ccYgfTud.s page 356 1603:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 1604:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 1605:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 1606:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 1607:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 1608:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 1609:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 1610:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval Between 0 to 0xFFFFFFFF 1611:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1612:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(DMA_TypeDef* DMAx, uint32_t Stream) 1613:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1614:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))-> 1615:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1616:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1617:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1618:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Set Memory 1 address (used in case of Double buffer mode). 1619:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll M1AR M1A LL_DMA_SetMemory1Address 1620:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 1621:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: 1622:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 1623:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 1624:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 1625:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 1626:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 1627:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 1628:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 1629:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 1630:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Address Between 0 to 0xFFFFFFFF 1631:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 1632:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1633:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_SetMemory1Address(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Address) 1634:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1635:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M1AR, 1636:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1637:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1638:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1639:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Memory 1 address (used in case of Double buffer mode). 1640:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll M1AR M1A LL_DMA_GetMemory1Address 1641:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 1642:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: 1643:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 1644:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 1645:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 1646:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 1647:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 1648:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 1649:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 1650:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 1651:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval Between 0 to 0xFFFFFFFF 1652:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1653:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_GetMemory1Address(DMA_TypeDef *DMAx, uint32_t Stream) 1654:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1655:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M1AR); 1656:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1657:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1658:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1659:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @} ARM GAS /tmp/ccYgfTud.s page 357 1660:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1661:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1662:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_EF_FLAG_Management FLAG_Management 1663:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @{ 1664:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1665:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1666:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1667:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 0 half transfer flag. 1668:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LISR HTIF0 LL_DMA_IsActiveFlag_HT0 1669:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 1670:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). 1671:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1672:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT0(DMA_TypeDef *DMAx) 1673:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1674:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->LISR ,DMA_LISR_HTIF0)==(DMA_LISR_HTIF0)); 1675:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1676:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1677:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1678:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 1 half transfer flag. 1679:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LISR HTIF1 LL_DMA_IsActiveFlag_HT1 1680:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 1681:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). 1682:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1683:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT1(DMA_TypeDef *DMAx) 1684:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1685:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->LISR ,DMA_LISR_HTIF1)==(DMA_LISR_HTIF1)); 1686:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1687:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1688:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1689:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 2 half transfer flag. 1690:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LISR HTIF2 LL_DMA_IsActiveFlag_HT2 1691:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 1692:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). 1693:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1694:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT2(DMA_TypeDef *DMAx) 1695:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1696:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->LISR ,DMA_LISR_HTIF2)==(DMA_LISR_HTIF2)); 1697:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1698:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1699:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1700:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 3 half transfer flag. 1701:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LISR HTIF3 LL_DMA_IsActiveFlag_HT3 1702:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 1703:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). 1704:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1705:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT3(DMA_TypeDef *DMAx) 1706:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1707:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->LISR ,DMA_LISR_HTIF3)==(DMA_LISR_HTIF3)); 1708:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1709:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1710:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1711:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 4 half transfer flag. 1712:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HISR HTIF4 LL_DMA_IsActiveFlag_HT4 1713:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 1714:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). 1715:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1716:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT4(DMA_TypeDef *DMAx) ARM GAS /tmp/ccYgfTud.s page 358 1717:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1718:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->HISR ,DMA_HISR_HTIF4)==(DMA_HISR_HTIF4)); 1719:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1720:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1721:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1722:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 5 half transfer flag. 1723:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HISR HTIF0 LL_DMA_IsActiveFlag_HT5 1724:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 1725:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). 1726:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1727:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT5(DMA_TypeDef *DMAx) 1728:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1729:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->HISR ,DMA_HISR_HTIF5)==(DMA_HISR_HTIF5)); 1730:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1731:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1732:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1733:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 6 half transfer flag. 1734:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HISR HTIF6 LL_DMA_IsActiveFlag_HT6 1735:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 1736:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). 1737:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1738:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT6(DMA_TypeDef *DMAx) 1739:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1740:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->HISR ,DMA_HISR_HTIF6)==(DMA_HISR_HTIF6)); 1741:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1742:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1743:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1744:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 7 half transfer flag. 1745:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HISR HTIF7 LL_DMA_IsActiveFlag_HT7 1746:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 1747:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). 1748:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1749:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT7(DMA_TypeDef *DMAx) 1750:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1751:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->HISR ,DMA_HISR_HTIF7)==(DMA_HISR_HTIF7)); 1752:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1753:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1754:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1755:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 0 transfer complete flag. 1756:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LISR TCIF0 LL_DMA_IsActiveFlag_TC0 1757:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 1758:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). 1759:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1760:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC0(DMA_TypeDef *DMAx) 1761:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1762:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->LISR ,DMA_LISR_TCIF0)==(DMA_LISR_TCIF0)); 1763:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1764:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1765:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1766:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 1 transfer complete flag. 1767:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LISR TCIF1 LL_DMA_IsActiveFlag_TC1 1768:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 1769:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). 1770:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1771:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC1(DMA_TypeDef *DMAx) 1772:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1773:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->LISR ,DMA_LISR_TCIF1)==(DMA_LISR_TCIF1)); ARM GAS /tmp/ccYgfTud.s page 359 1774:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1775:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1776:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1777:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 2 transfer complete flag. 1778:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LISR TCIF2 LL_DMA_IsActiveFlag_TC2 1779:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 1780:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). 1781:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1782:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC2(DMA_TypeDef *DMAx) 1783:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1784:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->LISR ,DMA_LISR_TCIF2)==(DMA_LISR_TCIF2)); 1785:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1786:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1787:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1788:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 3 transfer complete flag. 1789:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LISR TCIF3 LL_DMA_IsActiveFlag_TC3 1790:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 1791:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). 1792:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1793:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC3(DMA_TypeDef *DMAx) 1794:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1795:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->LISR ,DMA_LISR_TCIF3)==(DMA_LISR_TCIF3)); 1796:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1797:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1798:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1799:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 4 transfer complete flag. 1800:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HISR TCIF4 LL_DMA_IsActiveFlag_TC4 1801:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 1802:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). 1803:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1804:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC4(DMA_TypeDef *DMAx) 1805:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1806:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->HISR ,DMA_HISR_TCIF4)==(DMA_HISR_TCIF4)); 1807:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1808:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1809:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1810:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 5 transfer complete flag. 1811:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HISR TCIF0 LL_DMA_IsActiveFlag_TC5 1812:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 1813:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). 1814:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1815:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC5(DMA_TypeDef *DMAx) 1816:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1817:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->HISR ,DMA_HISR_TCIF5)==(DMA_HISR_TCIF5)); 1818:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1819:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1820:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1821:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 6 transfer complete flag. 1822:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HISR TCIF6 LL_DMA_IsActiveFlag_TC6 1823:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 1824:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). 1825:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1826:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC6(DMA_TypeDef *DMAx) 1827:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1828:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->HISR ,DMA_HISR_TCIF6)==(DMA_HISR_TCIF6)); 1829:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1830:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** ARM GAS /tmp/ccYgfTud.s page 360 1831:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1832:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 7 transfer complete flag. 1833:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HISR TCIF7 LL_DMA_IsActiveFlag_TC7 1834:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 1835:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). 1836:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1837:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC7(DMA_TypeDef *DMAx) 1838:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1839:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->HISR ,DMA_HISR_TCIF7)==(DMA_HISR_TCIF7)); 1840:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1841:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1842:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1843:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 0 transfer error flag. 1844:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LISR TEIF0 LL_DMA_IsActiveFlag_TE0 1845:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 1846:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). 1847:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1848:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE0(DMA_TypeDef *DMAx) 1849:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1850:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->LISR ,DMA_LISR_TEIF0)==(DMA_LISR_TEIF0)); 1851:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1852:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1853:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1854:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 1 transfer error flag. 1855:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LISR TEIF1 LL_DMA_IsActiveFlag_TE1 1856:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 1857:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). 1858:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1859:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE1(DMA_TypeDef *DMAx) 1860:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1861:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->LISR ,DMA_LISR_TEIF1)==(DMA_LISR_TEIF1)); 1862:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1863:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1864:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1865:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 2 transfer error flag. 1866:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LISR TEIF2 LL_DMA_IsActiveFlag_TE2 1867:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 1868:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). 1869:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1870:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE2(DMA_TypeDef *DMAx) 1871:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1872:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->LISR ,DMA_LISR_TEIF2)==(DMA_LISR_TEIF2)); 1873:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1874:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1875:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1876:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 3 transfer error flag. 1877:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LISR TEIF3 LL_DMA_IsActiveFlag_TE3 1878:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 1879:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). 1880:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1881:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE3(DMA_TypeDef *DMAx) 1882:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1883:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->LISR ,DMA_LISR_TEIF3)==(DMA_LISR_TEIF3)); 1884:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1885:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1886:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1887:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 4 transfer error flag. ARM GAS /tmp/ccYgfTud.s page 361 1888:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HISR TEIF4 LL_DMA_IsActiveFlag_TE4 1889:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 1890:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). 1891:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1892:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE4(DMA_TypeDef *DMAx) 1893:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1894:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->HISR ,DMA_HISR_TEIF4)==(DMA_HISR_TEIF4)); 1895:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1896:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1897:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1898:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 5 transfer error flag. 1899:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HISR TEIF0 LL_DMA_IsActiveFlag_TE5 1900:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 1901:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). 1902:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1903:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE5(DMA_TypeDef *DMAx) 1904:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1905:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->HISR ,DMA_HISR_TEIF5)==(DMA_HISR_TEIF5)); 1906:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1908:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1909:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 6 transfer error flag. 1910:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HISR TEIF6 LL_DMA_IsActiveFlag_TE6 1911:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 1912:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). 1913:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1914:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE6(DMA_TypeDef *DMAx) 1915:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1916:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->HISR ,DMA_HISR_TEIF6)==(DMA_HISR_TEIF6)); 1917:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1919:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1920:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 7 transfer error flag. 1921:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HISR TEIF7 LL_DMA_IsActiveFlag_TE7 1922:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 1923:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). 1924:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1925:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE7(DMA_TypeDef *DMAx) 1926:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1927:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->HISR ,DMA_HISR_TEIF7)==(DMA_HISR_TEIF7)); 1928:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1929:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1930:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1931:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 0 direct mode error flag. 1932:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LISR DMEIF0 LL_DMA_IsActiveFlag_DME0 1933:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 1934:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). 1935:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1936:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME0(DMA_TypeDef *DMAx) 1937:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1938:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->LISR ,DMA_LISR_DMEIF0)==(DMA_LISR_DMEIF0)); 1939:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1940:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1941:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1942:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 1 direct mode error flag. 1943:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LISR DMEIF1 LL_DMA_IsActiveFlag_DME1 1944:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance ARM GAS /tmp/ccYgfTud.s page 362 1945:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). 1946:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1947:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME1(DMA_TypeDef *DMAx) 1948:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1949:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->LISR ,DMA_LISR_DMEIF1)==(DMA_LISR_DMEIF1)); 1950:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1951:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1952:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1953:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 2 direct mode error flag. 1954:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LISR DMEIF2 LL_DMA_IsActiveFlag_DME2 1955:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 1956:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). 1957:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1958:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME2(DMA_TypeDef *DMAx) 1959:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1960:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->LISR ,DMA_LISR_DMEIF2)==(DMA_LISR_DMEIF2)); 1961:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1962:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1963:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1964:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 3 direct mode error flag. 1965:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LISR DMEIF3 LL_DMA_IsActiveFlag_DME3 1966:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 1967:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). 1968:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1969:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME3(DMA_TypeDef *DMAx) 1970:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1971:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->LISR ,DMA_LISR_DMEIF3)==(DMA_LISR_DMEIF3)); 1972:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1973:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1974:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1975:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 4 direct mode error flag. 1976:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HISR DMEIF4 LL_DMA_IsActiveFlag_DME4 1977:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 1978:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). 1979:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1980:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME4(DMA_TypeDef *DMAx) 1981:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1982:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->HISR ,DMA_HISR_DMEIF4)==(DMA_HISR_DMEIF4)); 1983:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1984:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1985:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1986:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 5 direct mode error flag. 1987:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HISR DMEIF0 LL_DMA_IsActiveFlag_DME5 1988:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 1989:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). 1990:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1991:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME5(DMA_TypeDef *DMAx) 1992:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1993:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->HISR ,DMA_HISR_DMEIF5)==(DMA_HISR_DMEIF5)); 1994:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1995:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1996:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1997:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 6 direct mode error flag. 1998:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HISR DMEIF6 LL_DMA_IsActiveFlag_DME6 1999:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 2000:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). 2001:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ ARM GAS /tmp/ccYgfTud.s page 363 2002:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME6(DMA_TypeDef *DMAx) 2003:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 2004:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->HISR ,DMA_HISR_DMEIF6)==(DMA_HISR_DMEIF6)); 2005:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 2006:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 2007:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 2008:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 7 direct mode error flag. 2009:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HISR DMEIF7 LL_DMA_IsActiveFlag_DME7 2010:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 2011:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). 2012:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 2013:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME7(DMA_TypeDef *DMAx) 2014:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 2015:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->HISR ,DMA_HISR_DMEIF7)==(DMA_HISR_DMEIF7)); 2016:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 2017:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 2018:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 2019:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 0 FIFO error flag. 2020:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LISR FEIF0 LL_DMA_IsActiveFlag_FE0 2021:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 2022:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). 2023:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 2024:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE0(DMA_TypeDef *DMAx) 2025:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 2026:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->LISR ,DMA_LISR_FEIF0)==(DMA_LISR_FEIF0)); 2027:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 2028:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 2029:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 2030:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 1 FIFO error flag. 2031:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LISR FEIF1 LL_DMA_IsActiveFlag_FE1 2032:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 2033:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). 2034:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 2035:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE1(DMA_TypeDef *DMAx) 2036:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 2037:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->LISR ,DMA_LISR_FEIF1)==(DMA_LISR_FEIF1)); 2038:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 2039:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 2040:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 2041:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 2 FIFO error flag. 2042:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LISR FEIF2 LL_DMA_IsActiveFlag_FE2 2043:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 2044:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). 2045:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 2046:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE2(DMA_TypeDef *DMAx) 2047:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 2048:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->LISR ,DMA_LISR_FEIF2)==(DMA_LISR_FEIF2)); 2049:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 2050:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 2051:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 2052:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 3 FIFO error flag. 2053:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LISR FEIF3 LL_DMA_IsActiveFlag_FE3 2054:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 2055:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). 2056:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 2057:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE3(DMA_TypeDef *DMAx) 2058:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { ARM GAS /tmp/ccYgfTud.s page 364 2059:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->LISR ,DMA_LISR_FEIF3)==(DMA_LISR_FEIF3)); 2060:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 2061:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 2062:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 2063:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 4 FIFO error flag. 2064:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HISR FEIF4 LL_DMA_IsActiveFlag_FE4 2065:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 2066:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). 2067:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 2068:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE4(DMA_TypeDef *DMAx) 2069:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 2070:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->HISR ,DMA_HISR_FEIF4)==(DMA_HISR_FEIF4)); 2071:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 2072:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 2073:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 2074:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 5 FIFO error flag. 2075:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HISR FEIF0 LL_DMA_IsActiveFlag_FE5 2076:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 2077:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). 2078:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 2079:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE5(DMA_TypeDef *DMAx) 2080:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 2081:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->HISR ,DMA_HISR_FEIF5)==(DMA_HISR_FEIF5)); 2082:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 2083:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 2084:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 2085:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 6 FIFO error flag. 2086:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HISR FEIF6 LL_DMA_IsActiveFlag_FE6 2087:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 2088:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). 2089:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 2090:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE6(DMA_TypeDef *DMAx) 2091:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 2092:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->HISR ,DMA_HISR_FEIF6)==(DMA_HISR_FEIF6)); 2093:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 2094:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 2095:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 2096:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 7 FIFO error flag. 2097:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HISR FEIF7 LL_DMA_IsActiveFlag_FE7 2098:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 2099:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). 2100:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 2101:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE7(DMA_TypeDef *DMAx) 2102:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 2103:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->HISR ,DMA_HISR_FEIF7)==(DMA_HISR_FEIF7)); 2104:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 2105:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 2106:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 2107:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Clear Stream 0 half transfer flag. 2108:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LIFCR CHTIF0 LL_DMA_ClearFlag_HT0 2109:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 2110:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 2111:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 2112:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_HT0(DMA_TypeDef *DMAx) 2113:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 2114:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CHTIF0); 2115:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } ARM GAS /tmp/ccYgfTud.s page 365 2116:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 2117:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 2118:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Clear Stream 1 half transfer flag. 2119:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LIFCR CHTIF1 LL_DMA_ClearFlag_HT1 2120:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 2121:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 2122:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 2123:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_HT1(DMA_TypeDef *DMAx) 2124:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 2125:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CHTIF1); 2126:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 2127:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 2128:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 2129:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Clear Stream 2 half transfer flag. 2130:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LIFCR CHTIF2 LL_DMA_ClearFlag_HT2 2131:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 2132:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 2133:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 2134:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_HT2(DMA_TypeDef *DMAx) 2135:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 2136:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CHTIF2); 2137:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 2138:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 2139:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 2140:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Clear Stream 3 half transfer flag. 2141:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LIFCR CHTIF3 LL_DMA_ClearFlag_HT3 2142:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 2143:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 2144:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 2145:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_HT3(DMA_TypeDef *DMAx) 2146:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 2147:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CHTIF3); 2148:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 2149:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 2150:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 2151:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Clear Stream 4 half transfer flag. 2152:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HIFCR CHTIF4 LL_DMA_ClearFlag_HT4 2153:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 2154:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 2155:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 2156:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_HT4(DMA_TypeDef *DMAx) 2157:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 2158:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CHTIF4); 2159:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 2160:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 2161:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 2162:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Clear Stream 5 half transfer flag. 2163:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HIFCR CHTIF5 LL_DMA_ClearFlag_HT5 2164:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 2165:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 2166:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 2167:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_HT5(DMA_TypeDef *DMAx) 2168:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 2169:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CHTIF5); 2170:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 2171:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 2172:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** ARM GAS /tmp/ccYgfTud.s page 366 2173:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Clear Stream 6 half transfer flag. 2174:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HIFCR CHTIF6 LL_DMA_ClearFlag_HT6 2175:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 2176:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 2177:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 2178:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_HT6(DMA_TypeDef *DMAx) 2179:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 2180:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CHTIF6); 2181:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 2182:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 2183:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 2184:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Clear Stream 7 half transfer flag. 2185:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HIFCR CHTIF7 LL_DMA_ClearFlag_HT7 2186:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 2187:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 2188:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 2189:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_HT7(DMA_TypeDef *DMAx) 2190:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 2191:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CHTIF7); 2192:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 2193:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 2194:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 2195:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Clear Stream 0 transfer complete flag. 2196:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LIFCR CTCIF0 LL_DMA_ClearFlag_TC0 2197:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 2198:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 2199:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 2200:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_TC0(DMA_TypeDef *DMAx) 2201:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 2202:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTCIF0); 2203:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 2204:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 2205:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 2206:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Clear Stream 1 transfer complete flag. 2207:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LIFCR CTCIF1 LL_DMA_ClearFlag_TC1 2208:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 2209:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 2210:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 2211:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_TC1(DMA_TypeDef *DMAx) 2212:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 2213:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTCIF1); 2214:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 2215:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 2216:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 2217:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Clear Stream 2 transfer complete flag. 2218:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LIFCR CTCIF2 LL_DMA_ClearFlag_TC2 2219:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 2220:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 2221:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 2222:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_TC2(DMA_TypeDef *DMAx) 2223:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 2224:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTCIF2); 2225:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 2226:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 2227:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 2228:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Clear Stream 3 transfer complete flag. 2229:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LIFCR CTCIF3 LL_DMA_ClearFlag_TC3 ARM GAS /tmp/ccYgfTud.s page 367 2230:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 2231:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 2232:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 2233:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_TC3(DMA_TypeDef *DMAx) 2234:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 2235:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTCIF3); 2236:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 2237:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 2238:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 2239:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Clear Stream 4 transfer complete flag. 2240:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HIFCR CTCIF4 LL_DMA_ClearFlag_TC4 2241:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 2242:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 2243:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 2244:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_TC4(DMA_TypeDef *DMAx) 2245:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 2246:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTCIF4); 2247:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 2248:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 2249:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 2250:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Clear Stream 5 transfer complete flag. 2251:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HIFCR CTCIF5 LL_DMA_ClearFlag_TC5 2252:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 2253:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 2254:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 2255:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_TC5(DMA_TypeDef *DMAx) 2256:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 2257:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTCIF5); 2258:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 2259:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 2260:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 2261:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Clear Stream 6 transfer complete flag. 2262:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HIFCR CTCIF6 LL_DMA_ClearFlag_TC6 2263:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 2264:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 2265:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 2266:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_TC6(DMA_TypeDef *DMAx) 2267:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 2268:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTCIF6); 2269:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 2270:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 2271:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 2272:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Clear Stream 7 transfer complete flag. 2273:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HIFCR CTCIF7 LL_DMA_ClearFlag_TC7 2274:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 2275:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 2276:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 2277:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_TC7(DMA_TypeDef *DMAx) 5103 .loc 6 2277 22 view .LVU1648 5104 .LBB527: 2278:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 2279:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTCIF7); 5105 .loc 6 2279 3 view .LVU1649 5106 00dc 4FF00062 mov r2, #134217728 5107 00e0 DA60 str r2, [r3, #12] 5108 .LVL414: 5109 .loc 6 2279 3 is_stmt 0 view .LVU1650 ARM GAS /tmp/ccYgfTud.s page 368 5110 .LBE527: 5111 .LBE526: 2069:Src/main.c **** LL_USART_EnableDMAReq_TX(USART1); 5112 .loc 1 2069 3 is_stmt 1 view .LVU1651 5113 .LBB528: 5114 .LBI528: 2280:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 2281:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 2282:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 2283:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Clear Stream 0 transfer error flag. 2284:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LIFCR CTEIF0 LL_DMA_ClearFlag_TE0 2285:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 2286:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 2287:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 2288:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_TE0(DMA_TypeDef *DMAx) 2289:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 2290:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTEIF0); 2291:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 2292:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 2293:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 2294:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Clear Stream 1 transfer error flag. 2295:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LIFCR CTEIF1 LL_DMA_ClearFlag_TE1 2296:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 2297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 2298:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 2299:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_TE1(DMA_TypeDef *DMAx) 2300:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 2301:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTEIF1); 2302:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 2303:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 2304:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 2305:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Clear Stream 2 transfer error flag. 2306:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LIFCR CTEIF2 LL_DMA_ClearFlag_TE2 2307:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 2308:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 2309:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 2310:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_TE2(DMA_TypeDef *DMAx) 2311:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 2312:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTEIF2); 2313:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 2314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 2315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 2316:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Clear Stream 3 transfer error flag. 2317:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LIFCR CTEIF3 LL_DMA_ClearFlag_TE3 2318:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 2319:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 2320:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 2321:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_TE3(DMA_TypeDef *DMAx) 2322:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 2323:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTEIF3); 2324:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 2325:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 2326:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 2327:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Clear Stream 4 transfer error flag. 2328:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HIFCR CTEIF4 LL_DMA_ClearFlag_TE4 2329:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 2330:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None ARM GAS /tmp/ccYgfTud.s page 369 2331:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 2332:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_TE4(DMA_TypeDef *DMAx) 2333:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 2334:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTEIF4); 2335:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 2336:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 2337:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 2338:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Clear Stream 5 transfer error flag. 2339:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HIFCR CTEIF5 LL_DMA_ClearFlag_TE5 2340:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 2341:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 2342:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 2343:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_TE5(DMA_TypeDef *DMAx) 2344:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 2345:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTEIF5); 2346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 2347:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 2348:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 2349:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Clear Stream 6 transfer error flag. 2350:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HIFCR CTEIF6 LL_DMA_ClearFlag_TE6 2351:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 2352:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 2353:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 2354:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_TE6(DMA_TypeDef *DMAx) 2355:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 2356:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTEIF6); 2357:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 2358:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 2359:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 2360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Clear Stream 7 transfer error flag. 2361:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HIFCR CTEIF7 LL_DMA_ClearFlag_TE7 2362:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 2363:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 2364:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 2365:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_TE7(DMA_TypeDef *DMAx) 5115 .loc 6 2365 22 view .LVU1652 5116 .LBB529: 2366:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 2367:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTEIF7); 5117 .loc 6 2367 3 view .LVU1653 5118 00e2 4FF00072 mov r2, #33554432 5119 00e6 DA60 str r2, [r3, #12] 5120 .LVL415: 5121 .loc 6 2367 3 is_stmt 0 view .LVU1654 5122 .LBE529: 5123 .LBE528: 2070:Src/main.c **** LL_DMA_EnableIT_TC(DMA2, LL_DMA_STREAM_7); 5124 .loc 1 2070 3 is_stmt 1 view .LVU1655 5125 .LBB530: 5126 .LBI530: 5127 .file 7 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h" 1:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ****************************************************************************** 3:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @file stm32f7xx_ll_usart.h 4:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @author MCD Application Team 5:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Header file of USART LL module. 6:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ****************************************************************************** ARM GAS /tmp/ccYgfTud.s page 370 7:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @attention 8:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * 9:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Copyright (c) 2017 STMicroelectronics. 10:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * All rights reserved. 11:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * 12:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * This software is licensed under terms that can be found in the LICENSE file 13:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * in the root directory of this software component. 14:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * If no LICENSE file comes with this software, it is provided AS-IS. 15:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * 16:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ****************************************************************************** 17:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 18:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 19:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* Define to prevent recursive inclusion -------------------------------------*/ 20:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #ifndef STM32F7xx_LL_USART_H 21:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define STM32F7xx_LL_USART_H 22:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 23:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #ifdef __cplusplus 24:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** extern "C" { 25:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif 26:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 27:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* Includes ------------------------------------------------------------------*/ 28:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #include "stm32f7xx.h" 29:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 30:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @addtogroup STM32F7xx_LL_Driver 31:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ 32:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 33:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 34:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART1) || defined(USART2) || defined(USART3) || defined(USART6) \ 35:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** || defined(UART4) || defined(UART5) || defined(UART7) || defined(UART8) 36:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 37:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL USART 38:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ 39:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 40:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 41:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* Private types -------------------------------------------------------------*/ 42:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* Private variables ---------------------------------------------------------*/ 43:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 44:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* Private constants ---------------------------------------------------------*/ 45:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_Private_Constants USART Private Constants 46:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ 47:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 48:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 49:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} 50:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 51:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* Private macros ------------------------------------------------------------*/ 52:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USE_FULL_LL_DRIVER) 53:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_Private_Macros USART Private Macros 54:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ 55:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 56:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 57:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} 58:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 59:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /*USE_FULL_LL_DRIVER*/ 60:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 61:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* Exported types ------------------------------------------------------------*/ 62:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USE_FULL_LL_DRIVER) 63:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_ES_INIT USART Exported Init structures ARM GAS /tmp/ccYgfTud.s page 371 64:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ 65:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 66:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 67:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 68:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief LL USART Init Structure definition 69:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 70:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** typedef struct 71:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 72:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 73:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** uint32_t BaudRate; /*!< This field defines expected Usart communication baud rat 74:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 75:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** This feature can be modified afterwards using unitary 76:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** function @ref LL_USART_SetBaudRate().*/ 77:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 78:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** uint32_t DataWidth; /*!< Specifies the number of data bits transmitted or receive 79:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** This parameter can be a value of @ref USART_LL_EC_DATAWI 80:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 81:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** This feature can be modified afterwards using unitary 82:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** function @ref LL_USART_SetDataWidth().*/ 83:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 84:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** uint32_t StopBits; /*!< Specifies the number of stop bits transmitted. 85:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** This parameter can be a value of @ref USART_LL_EC_STOPBI 86:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 87:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** This feature can be modified afterwards using unitary 88:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** function @ref LL_USART_SetStopBitsLength().*/ 89:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 90:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** uint32_t Parity; /*!< Specifies the parity mode. 91:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** This parameter can be a value of @ref USART_LL_EC_PARITY 92:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 93:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** This feature can be modified afterwards using unitary 94:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** function @ref LL_USART_SetParity().*/ 95:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 96:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** uint32_t TransferDirection; /*!< Specifies whether the Receive and/or Transmit mode is en 97:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** This parameter can be a value of @ref USART_LL_EC_DIRECT 98:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 99:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** This feature can be modified afterwards using unitary 100:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** function @ref LL_USART_SetTransferDirection().*/ 101:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 102:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** uint32_t HardwareFlowControl; /*!< Specifies whether the hardware flow control mode is enab 103:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** This parameter can be a value of @ref USART_LL_EC_HWCONT 104:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 105:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** This feature can be modified afterwards using unitary 106:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** function @ref LL_USART_SetHWFlowCtrl().*/ 107:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 108:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** uint32_t OverSampling; /*!< Specifies whether USART oversampling mode is 16 or 8. 109:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** This parameter can be a value of @ref USART_LL_EC_OVERSA 110:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 111:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** This feature can be modified afterwards using unitary 112:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** function @ref LL_USART_SetOverSampling().*/ 113:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 114:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } LL_USART_InitTypeDef; 115:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 116:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 117:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief LL USART Clock Init Structure definition 118:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 119:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** typedef struct 120:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { ARM GAS /tmp/ccYgfTud.s page 372 121:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** uint32_t ClockOutput; /*!< Specifies whether the USART clock is enabled or disabled 122:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** This parameter can be a value of @ref USART_LL_EC_CLOCK. 123:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 124:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** USART HW configuration can be modified afterwards using 125:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** @ref LL_USART_EnableSCLKOutput() or @ref LL_USART_Disabl 126:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** For more details, refer to description of this function. 127:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 128:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** uint32_t ClockPolarity; /*!< Specifies the steady state of the serial clock. 129:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** This parameter can be a value of @ref USART_LL_EC_POLARI 130:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 131:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** USART HW configuration can be modified afterwards using 132:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** functions @ref LL_USART_SetClockPolarity(). 133:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** For more details, refer to description of this function. 134:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 135:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** uint32_t ClockPhase; /*!< Specifies the clock transition on which the bit capture 136:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** This parameter can be a value of @ref USART_LL_EC_PHASE. 137:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 138:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** USART HW configuration can be modified afterwards using 139:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** functions @ref LL_USART_SetClockPhase(). 140:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** For more details, refer to description of this function. 141:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 142:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** uint32_t LastBitClockPulse; /*!< Specifies whether the clock pulse corresponding to the l 143:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** data bit (MSB) has to be output on the SCLK pin in synch 144:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** This parameter can be a value of @ref USART_LL_EC_LASTCL 145:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 146:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** USART HW configuration can be modified afterwards using 147:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** functions @ref LL_USART_SetLastClkPulseOutput(). 148:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** For more details, refer to description of this function. 149:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 150:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } LL_USART_ClockInitTypeDef; 151:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 152:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 153:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} 154:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 155:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USE_FULL_LL_DRIVER */ 156:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 157:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* Exported constants --------------------------------------------------------*/ 158:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_Exported_Constants USART Exported Constants 159:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ 160:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 161:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 162:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_CLEAR_FLAG Clear Flags Defines 163:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Flags defines which can be used with LL_USART_WriteReg function 164:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ 165:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 166:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ICR_PECF USART_ICR_PECF /*!< Parity error cle 167:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ICR_FECF USART_ICR_FECF /*!< Framing error cl 168:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ICR_NCF USART_ICR_NCF /*!< Noise error dete 169:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ICR_ORECF USART_ICR_ORECF /*!< Overrun error cl 170:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ICR_IDLECF USART_ICR_IDLECF /*!< Idle line detect 171:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ICR_TCCF USART_ICR_TCCF /*!< Transmission com 172:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_TCBGT_SUPPORT) 173:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ICR_TCBGTCF USART_ICR_TCBGTCF /*!< Transmission com 174:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_TCBGT_SUPPORT */ 175:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ICR_LBDCF USART_ICR_LBDCF /*!< LIN break detect 176:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ICR_CTSCF USART_ICR_CTSCF /*!< CTS clear flag * 177:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ICR_RTOCF USART_ICR_RTOCF /*!< Receiver timeout ARM GAS /tmp/ccYgfTud.s page 373 178:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ICR_EOBCF USART_ICR_EOBCF /*!< End of block cle 179:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ICR_CMCF USART_ICR_CMCF /*!< Character match 180:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_CR1_UESM) 181:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_CR3_WUFIE) 182:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ICR_WUCF USART_ICR_WUCF /*!< Wakeup from Stop 183:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_CR3_WUFIE */ 184:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_CR1_UESM */ 185:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 186:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} 187:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 188:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 189:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_GET_FLAG Get Flags Defines 190:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Flags defines which can be used with LL_USART_ReadReg function 191:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ 192:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 193:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_PE USART_ISR_PE /*!< Parity error fla 194:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_FE USART_ISR_FE /*!< Framing error fl 195:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_NE USART_ISR_NE /*!< Noise detected f 196:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_ORE USART_ISR_ORE /*!< Overrun error fl 197:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_IDLE USART_ISR_IDLE /*!< Idle line detect 198:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_RXNE USART_ISR_RXNE /*!< Read data regist 199:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_TC USART_ISR_TC /*!< Transmission com 200:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_TXE USART_ISR_TXE /*!< Transmit data re 201:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_LBDF USART_ISR_LBDF /*!< LIN break detect 202:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_CTSIF USART_ISR_CTSIF /*!< CTS interrupt fl 203:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_CTS USART_ISR_CTS /*!< CTS flag */ 204:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_RTOF USART_ISR_RTOF /*!< Receiver timeout 205:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_EOBF USART_ISR_EOBF /*!< End of block fla 206:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_ABRE USART_ISR_ABRE /*!< Auto baud rate e 207:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_ABRF USART_ISR_ABRF /*!< Auto baud rate f 208:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_BUSY USART_ISR_BUSY /*!< Busy flag */ 209:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_CMF USART_ISR_CMF /*!< Character match 210:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_SBKF USART_ISR_SBKF /*!< Send break flag 211:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_RWU USART_ISR_RWU /*!< Receiver wakeup 212:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_CR1_UESM) 213:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_CR3_WUFIE) 214:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_WUF USART_ISR_WUF /*!< Wakeup from Stop 215:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_CR3_WUFIE */ 216:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_CR1_UESM */ 217:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_TEACK USART_ISR_TEACK /*!< Transmit enable 218:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_ISR_REACK) 219:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_REACK USART_ISR_REACK /*!< Receive enable a 220:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_ISR_REACK */ 221:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_TCBGT_SUPPORT) 222:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_TCBGT USART_ISR_TCBGT /*!< Transmission com 223:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_TCBGT_SUPPORT */ 224:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 225:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} 226:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 227:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 228:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_IT IT Defines 229:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief IT defines which can be used with LL_USART_ReadReg and LL_USART_WriteReg functions 230:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ 231:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 232:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_CR1_IDLEIE USART_CR1_IDLEIE /*!< IDLE interrupt e 233:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_CR1_RXNEIE USART_CR1_RXNEIE /*!< Read data regist 234:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_CR1_TCIE USART_CR1_TCIE /*!< Transmission com ARM GAS /tmp/ccYgfTud.s page 374 235:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_CR1_TXEIE USART_CR1_TXEIE /*!< Transmit data re 236:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_CR1_PEIE USART_CR1_PEIE /*!< Parity error */ 237:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_CR1_CMIE USART_CR1_CMIE /*!< Character match 238:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_CR1_RTOIE USART_CR1_RTOIE /*!< Receiver timeout 239:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_CR1_EOBIE USART_CR1_EOBIE /*!< End of Block int 240:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_CR2_LBDIE USART_CR2_LBDIE /*!< LIN break detect 241:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_CR3_EIE USART_CR3_EIE /*!< Error interrupt 242:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_CR3_CTSIE USART_CR3_CTSIE /*!< CTS interrupt en 243:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_CR1_UESM) 244:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_CR3_WUFIE) 245:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_CR3_WUFIE USART_CR3_WUFIE /*!< Wakeup from Stop 246:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_CR3_WUFIE */ 247:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_CR1_UESM */ 248:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_TCBGT_SUPPORT) 249:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_CR3_TCBGTIE USART_CR3_TCBGTIE /*!< Transmission com 250:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_TCBGT_SUPPORT */ 251:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 252:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} 253:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 254:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 255:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_DIRECTION Communication Direction 256:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ 257:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 258:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_DIRECTION_NONE 0x00000000U /*!< Transmitter 259:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_DIRECTION_RX USART_CR1_RE /*!< Transmitter 260:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_DIRECTION_TX USART_CR1_TE /*!< Transmitter 261:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_DIRECTION_TX_RX (USART_CR1_TE |USART_CR1_RE) /*!< Transmitter 262:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 263:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} 264:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 265:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 266:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_PARITY Parity Control 267:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ 268:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 269:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_PARITY_NONE 0x00000000U /*!< Parity co 270:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_PARITY_EVEN USART_CR1_PCE /*!< Parity co 271:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS) /*!< Parity co 272:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 273:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} 274:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 275:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 276:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_WAKEUP Wakeup 277:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ 278:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 279:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_WAKEUP_IDLELINE 0x00000000U /*!< USART wake up from Mute 280:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_WAKEUP_ADDRESSMARK USART_CR1_WAKE /*!< USART wake up from Mute 281:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 282:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} 283:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 284:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 285:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_DATAWIDTH Datawidth 286:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ 287:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 288:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_DATAWIDTH_7B USART_CR1_M1 /*!< 7 bits word length : S 289:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_DATAWIDTH_8B 0x00000000U /*!< 8 bits word length : S 290:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_DATAWIDTH_9B USART_CR1_M0 /*!< 9 bits word length : S 291:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** ARM GAS /tmp/ccYgfTud.s page 375 292:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} 293:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 294:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 295:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_OVERSAMPLING Oversampling 296:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ 297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 298:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_OVERSAMPLING_16 0x00000000U /*!< Oversampling by 16 */ 299:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_OVERSAMPLING_8 USART_CR1_OVER8 /*!< Oversampling by 8 */ 300:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 301:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} 302:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 303:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 304:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USE_FULL_LL_DRIVER) 305:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_CLOCK Clock Signal 306:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ 307:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 308:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 309:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_CLOCK_DISABLE 0x00000000U /*!< Clock signal not provid 310:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_CLOCK_ENABLE USART_CR2_CLKEN /*!< Clock signal provided * 311:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 312:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} 313:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /*USE_FULL_LL_DRIVER*/ 315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 316:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_LASTCLKPULSE Last Clock Pulse 317:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ 318:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 319:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_LASTCLKPULSE_NO_OUTPUT 0x00000000U /*!< The clock pulse of the l 320:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_LASTCLKPULSE_OUTPUT USART_CR2_LBCL /*!< The clock pulse of the l 321:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 322:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} 323:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 324:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 325:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_PHASE Clock Phase 326:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ 327:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 328:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_PHASE_1EDGE 0x00000000U /*!< The first clock transiti 329:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_PHASE_2EDGE USART_CR2_CPHA /*!< The second clock transit 330:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 331:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} 332:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 333:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 334:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_POLARITY Clock Polarity 335:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ 336:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 337:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_POLARITY_LOW 0x00000000U /*!< Steady low value on SCLK 338:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_POLARITY_HIGH USART_CR2_CPOL /*!< Steady high value on SCL 339:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 340:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} 341:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 342:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 343:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_STOPBITS Stop Bits 344:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ 345:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_STOPBITS_0_5 USART_CR2_STOP_0 /*!< 0.5 347:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_STOPBITS_1 0x00000000U /*!< 1 s 348:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_STOPBITS_1_5 (USART_CR2_STOP_0 | USART_CR2_STOP_1) /*!< 1.5 ARM GAS /tmp/ccYgfTud.s page 376 349:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_STOPBITS_2 USART_CR2_STOP_1 /*!< 2 s 350:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 351:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} 352:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 353:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 354:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_TXRX TX RX Pins Swap 355:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ 356:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 357:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_TXRX_STANDARD 0x00000000U /*!< TX/RX pins are used as d 358:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_TXRX_SWAPPED (USART_CR2_SWAP) /*!< TX and RX pins functions 359:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} 361:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 362:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 363:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_RXPIN_LEVEL RX Pin Active Level Inversion 364:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ 365:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 366:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_RXPIN_LEVEL_STANDARD 0x00000000U /*!< RX pin signal works usin 367:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_RXPIN_LEVEL_INVERTED (USART_CR2_RXINV) /*!< RX pin signal values are 368:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 369:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} 370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 371:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_TXPIN_LEVEL TX Pin Active Level Inversion 373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ 374:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 375:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_TXPIN_LEVEL_STANDARD 0x00000000U /*!< TX pin signal works usin 376:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_TXPIN_LEVEL_INVERTED (USART_CR2_TXINV) /*!< TX pin signal values are 377:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 378:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} 379:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 380:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 381:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_BINARY_LOGIC Binary Data Inversion 382:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ 383:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 384:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_BINARY_LOGIC_POSITIVE 0x00000000U /*!< Logical data from the da 385:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_BINARY_LOGIC_NEGATIVE USART_CR2_DATAINV /*!< Logical data from the da 386:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 387:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} 388:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 389:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 390:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_BITORDER Bit Order 391:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ 392:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 393:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_BITORDER_LSBFIRST 0x00000000U /*!< data is transmitted/rece 394:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_BITORDER_MSBFIRST USART_CR2_MSBFIRST /*!< data is transmitted/rece 395:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 396:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} 397:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 398:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 399:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_AUTOBAUD_DETECT_ON Autobaud Detection 400:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ 401:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 402:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_AUTOBAUD_DETECT_ON_STARTBIT 0x00000000U /*!< Me 403:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_AUTOBAUD_DETECT_ON_FALLINGEDGE USART_CR2_ABRMODE_0 /*!< Fa 404:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME USART_CR2_ABRMODE_1 /*!< 0x 405:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_AUTOBAUD_DETECT_ON_55_FRAME (USART_CR2_ABRMODE_1 | USART_CR2_ABRMODE_0) /*!< 0x ARM GAS /tmp/ccYgfTud.s page 377 406:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 407:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} 408:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 409:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 410:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_ADDRESS_DETECT Address Length Detection 411:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ 412:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 413:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ADDRESS_DETECT_4B 0x00000000U /*!< 4-bit address detection 414:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ADDRESS_DETECT_7B USART_CR2_ADDM7 /*!< 7-bit address detection 415:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 416:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} 417:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 418:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 419:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_HWCONTROL Hardware Control 420:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ 421:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 422:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_HWCONTROL_NONE 0x00000000U /*!< CTS and R 423:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_HWCONTROL_RTS USART_CR3_RTSE /*!< RTS outpu 424:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_HWCONTROL_CTS USART_CR3_CTSE /*!< CTS mode 425:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_HWCONTROL_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE) /*!< CTS and R 426:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 427:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} 428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 429:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 430:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_CR1_UESM) 431:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_CR3_WUS) 432:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_WAKEUP_ON Wakeup Activation 433:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ 434:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 435:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_WAKEUP_ON_ADDRESS 0x00000000U /*!< Wake u 436:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_WAKEUP_ON_STARTBIT USART_CR3_WUS_1 /*!< Wake u 437:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_WAKEUP_ON_RXNE (USART_CR3_WUS_0 | USART_CR3_WUS_1) /*!< Wake u 438:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 439:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} 440:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 441:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 442:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_CR3_WUS */ 443:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_CR1_UESM */ 444:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_IRDA_POWER IrDA Power 445:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ 446:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 447:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_IRDA_POWER_NORMAL 0x00000000U /*!< IrDA normal power mode * 448:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_IRDA_POWER_LOW USART_CR3_IRLP /*!< IrDA low power mode */ 449:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 450:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} 451:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 452:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 453:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_LINBREAK_DETECT LIN Break Detection Length 454:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ 455:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 456:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_LINBREAK_DETECT_10B 0x00000000U /*!< 10-bit break detection m 457:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_LINBREAK_DETECT_11B USART_CR2_LBDL /*!< 11-bit break detection m 458:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 459:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} 460:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 461:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 462:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_DE_POLARITY Driver Enable Polarity ARM GAS /tmp/ccYgfTud.s page 378 463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ 464:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 465:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_DE_POLARITY_HIGH 0x00000000U /*!< DE signal is active high 466:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_DE_POLARITY_LOW USART_CR3_DEP /*!< DE signal is active low 467:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 468:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} 469:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 470:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 471:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_DMA_REG_DATA DMA Register Data 472:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ 473:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 474:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_DMA_REG_DATA_TRANSMIT 0x00000000U /*!< Get address of data regis 475:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_DMA_REG_DATA_RECEIVE 0x00000001U /*!< Get address of data regis 476:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 477:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} 478:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 479:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 480:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 481:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} 482:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 483:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 484:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* Exported macro ------------------------------------------------------------*/ 485:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_Exported_Macros USART Exported Macros 486:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ 487:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 488:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 489:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EM_WRITE_READ Common Write and read registers Macros 490:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ 491:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 492:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 493:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 494:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Write a value in USART register 495:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param __INSTANCE__ USART Instance 496:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param __REG__ Register to be written 497:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param __VALUE__ Value to be written in the register 498:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 499:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 500:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VAL 501:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 502:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 503:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Read a value in USART register 504:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param __INSTANCE__ USART Instance 505:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param __REG__ Register to be read 506:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Register value 507:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 508:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) 509:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 510:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} 511:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 512:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 513:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EM_Exported_Macros_Helper Exported_Macros_Helper 514:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ 515:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 516:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 517:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 518:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Compute USARTDIV value according to Peripheral Clock and 519:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * expected Baud Rate in 8 bits sampling mode (32 bits value of USARTDIV is returned) ARM GAS /tmp/ccYgfTud.s page 379 520:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param __PERIPHCLK__ Peripheral Clock frequency used for USART instance 521:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param __BAUDRATE__ Baud rate value to achieve 522:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval USARTDIV value to be used for BRR register filling in OverSampling_8 case 523:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 524:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define __LL_USART_DIV_SAMPLING8(__PERIPHCLK__, __BAUDRATE__) ((((__PERIPHCLK__)*2U)\ 525:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + ((__BAUDRATE__)/2U))/(__BAUDRATE_ 526:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 527:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 528:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Compute USARTDIV value according to Peripheral Clock and 529:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * expected Baud Rate in 16 bits sampling mode (32 bits value of USARTDIV is returned) 530:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param __PERIPHCLK__ Peripheral Clock frequency used for USART instance 531:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param __BAUDRATE__ Baud rate value to achieve 532:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval USARTDIV value to be used for BRR register filling in OverSampling_16 case 533:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 534:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define __LL_USART_DIV_SAMPLING16(__PERIPHCLK__, __BAUDRATE__) (((__PERIPHCLK__) + ((__BAUDRATE__)/ 535:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 536:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 537:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} 538:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 539:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 540:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 541:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} 542:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 543:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 544:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* Exported functions --------------------------------------------------------*/ 545:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 546:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_Exported_Functions USART Exported Functions 547:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ 548:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 549:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 550:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EF_Configuration Configuration functions 551:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ 552:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 553:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 554:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 555:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief USART Enable 556:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 UE LL_USART_Enable 557:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 558:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 559:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 560:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_Enable(USART_TypeDef *USARTx) 561:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 562:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** SET_BIT(USARTx->CR1, USART_CR1_UE); 563:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 564:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 565:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 566:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief USART Disable (all USART prescalers and outputs are disabled) 567:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note When USART is disabled, USART prescalers and outputs are stopped immediately, 568:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * and current operations are discarded. The configuration of the USART is kept, but all t 569:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * flags, in the USARTx_ISR are set to their default values. 570:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 UE LL_USART_Disable 571:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 572:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 573:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 574:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_Disable(USART_TypeDef *USARTx) 575:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 576:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** CLEAR_BIT(USARTx->CR1, USART_CR1_UE); ARM GAS /tmp/ccYgfTud.s page 380 577:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 578:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 579:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 580:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Indicate if USART is enabled 581:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 UE LL_USART_IsEnabled 582:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 583:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). 584:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 585:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabled(const USART_TypeDef *USARTx) 586:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 587:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->CR1, USART_CR1_UE) == (USART_CR1_UE)) ? 1UL : 0UL); 588:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 589:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 590:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_CR1_UESM) 591:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 592:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief USART enabled in STOP Mode. 593:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note When this function is enabled, USART is able to wake up the MCU from Stop mode, provide 594:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * USART clock selection is HSI or LSE in RCC. 595:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not 596:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Wake-up from Stop mode feature is supported by the USARTx instance. 597:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 UESM LL_USART_EnableInStopMode 598:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 599:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 600:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 601:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableInStopMode(USART_TypeDef *USARTx) 602:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 603:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_UESM); 604:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 605:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 606:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 607:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief USART disabled in STOP Mode. 608:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note When this function is disabled, USART is not able to wake up the MCU from Stop mode 609:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not 610:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Wake-up from Stop mode feature is supported by the USARTx instance. 611:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 UESM LL_USART_DisableInStopMode 612:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 613:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 614:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 615:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableInStopMode(USART_TypeDef *USARTx) 616:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 617:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_UESM); 618:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 619:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 620:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 621:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Indicate if USART is enabled in STOP Mode (able to wake up MCU from Stop mode or not) 622:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not 623:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Wake-up from Stop mode feature is supported by the USARTx instance. 624:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 UESM LL_USART_IsEnabledInStopMode 625:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 626:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). 627:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 628:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledInStopMode(const USART_TypeDef *USARTx) 629:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 630:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->CR1, USART_CR1_UESM) == (USART_CR1_UESM)) ? 1UL : 0UL); 631:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 632:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 633:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_CR3_UCESM) ARM GAS /tmp/ccYgfTud.s page 381 634:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 635:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief USART Clock enabled in STOP Mode 636:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note When this function is called, USART Clock is enabled while in STOP mode 637:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 UCESM LL_USART_EnableClockInStopMode 638:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 639:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 640:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 641:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableClockInStopMode(USART_TypeDef *USARTx) 642:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 643:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_UCESM); 644:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 645:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 646:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 647:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief USART clock disabled in STOP Mode 648:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note When this function is called, USART Clock is disabled while in STOP mode 649:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 UCESM LL_USART_DisableClockInStopMode 650:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 651:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 652:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 653:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableClockInStopMode(USART_TypeDef *USARTx) 654:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 655:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_UCESM); 656:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 657:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 658:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 659:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Indicate if USART clock is enabled in STOP Mode 660:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 UCESM LL_USART_IsClockEnabledInStopMode 661:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 662:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). 663:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 664:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsClockEnabledInStopMode(const USART_TypeDef *USARTx) 665:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 666:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return (READ_BIT(USARTx->CR3, USART_CR3_UCESM) == (USART_CR3_UCESM)); 667:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 668:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 669:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_CR3_UCESM */ 670:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_CR1_UESM*/ 671:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 672:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Receiver Enable (Receiver is enabled and begins searching for a start bit) 673:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 RE LL_USART_EnableDirectionRx 674:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 675:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 676:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 677:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableDirectionRx(USART_TypeDef *USARTx) 678:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 679:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_RE); 680:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 681:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 682:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 683:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Receiver Disable 684:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 RE LL_USART_DisableDirectionRx 685:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 686:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 687:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 688:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableDirectionRx(USART_TypeDef *USARTx) 689:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 690:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_RE); ARM GAS /tmp/ccYgfTud.s page 382 691:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 692:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 693:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 694:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Transmitter Enable 695:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 TE LL_USART_EnableDirectionTx 696:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 697:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 698:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 699:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableDirectionTx(USART_TypeDef *USARTx) 700:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 701:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_TE); 702:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 703:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 704:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 705:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Transmitter Disable 706:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 TE LL_USART_DisableDirectionTx 707:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 708:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 709:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 710:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableDirectionTx(USART_TypeDef *USARTx) 711:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 712:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_TE); 713:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 714:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 715:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 716:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Configure simultaneously enabled/disabled states 717:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * of Transmitter and Receiver 718:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 RE LL_USART_SetTransferDirection\n 719:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR1 TE LL_USART_SetTransferDirection 720:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 721:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param TransferDirection This parameter can be one of the following values: 722:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_DIRECTION_NONE 723:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_DIRECTION_RX 724:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_DIRECTION_TX 725:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_DIRECTION_TX_RX 726:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 727:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 728:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetTransferDirection(USART_TypeDef *USARTx, uint32_t TransferDirectio 729:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 730:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_MODIFY_REG(USARTx->CR1, USART_CR1_RE | USART_CR1_TE, TransferDirection); 731:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 732:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 733:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 734:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Return enabled/disabled states of Transmitter and Receiver 735:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 RE LL_USART_GetTransferDirection\n 736:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR1 TE LL_USART_GetTransferDirection 737:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 738:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Returned value can be one of the following values: 739:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_DIRECTION_NONE 740:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_DIRECTION_RX 741:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_DIRECTION_TX 742:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_DIRECTION_TX_RX 743:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 744:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetTransferDirection(const USART_TypeDef *USARTx) 745:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 746:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_RE | USART_CR1_TE)); 747:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } ARM GAS /tmp/ccYgfTud.s page 383 748:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 749:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 750:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Configure Parity (enabled/disabled and parity mode if enabled). 751:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note This function selects if hardware parity control (generation and detection) is enabled 752:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * When the parity control is enabled (Odd or Even), computed parity bit is inserted at th 753:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * (9th or 8th bit depending on data width) and parity is checked on the received data. 754:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 PS LL_USART_SetParity\n 755:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR1 PCE LL_USART_SetParity 756:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 757:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param Parity This parameter can be one of the following values: 758:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_PARITY_NONE 759:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_PARITY_EVEN 760:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_PARITY_ODD 761:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 762:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 763:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetParity(USART_TypeDef *USARTx, uint32_t Parity) 764:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 765:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** MODIFY_REG(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE, Parity); 766:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 767:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 768:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 769:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Return Parity configuration (enabled/disabled and parity mode if enabled) 770:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 PS LL_USART_GetParity\n 771:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR1 PCE LL_USART_GetParity 772:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 773:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Returned value can be one of the following values: 774:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_PARITY_NONE 775:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_PARITY_EVEN 776:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_PARITY_ODD 777:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 778:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetParity(const USART_TypeDef *USARTx) 779:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 780:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE)); 781:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 782:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 783:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 784:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Set Receiver Wake Up method from Mute mode. 785:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 WAKE LL_USART_SetWakeUpMethod 786:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 787:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param Method This parameter can be one of the following values: 788:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_WAKEUP_IDLELINE 789:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_WAKEUP_ADDRESSMARK 790:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 791:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 792:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetWakeUpMethod(USART_TypeDef *USARTx, uint32_t Method) 793:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 794:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** MODIFY_REG(USARTx->CR1, USART_CR1_WAKE, Method); 795:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 796:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 797:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 798:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Return Receiver Wake Up method from Mute mode 799:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 WAKE LL_USART_GetWakeUpMethod 800:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 801:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Returned value can be one of the following values: 802:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_WAKEUP_IDLELINE 803:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_WAKEUP_ADDRESSMARK 804:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ ARM GAS /tmp/ccYgfTud.s page 384 805:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetWakeUpMethod(const USART_TypeDef *USARTx) 806:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 807:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_WAKE)); 808:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 809:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 810:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 811:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Set Word length (i.e. nb of data bits, excluding start and stop bits) 812:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 M0 LL_USART_SetDataWidth\n 813:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR1 M1 LL_USART_SetDataWidth 814:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 815:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param DataWidth This parameter can be one of the following values: 816:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_DATAWIDTH_7B 817:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_DATAWIDTH_8B 818:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_DATAWIDTH_9B 819:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 820:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 821:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetDataWidth(USART_TypeDef *USARTx, uint32_t DataWidth) 822:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 823:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** MODIFY_REG(USARTx->CR1, USART_CR1_M, DataWidth); 824:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 825:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 826:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 827:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Return Word length (i.e. nb of data bits, excluding start and stop bits) 828:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 M0 LL_USART_GetDataWidth\n 829:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR1 M1 LL_USART_GetDataWidth 830:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 831:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Returned value can be one of the following values: 832:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_DATAWIDTH_7B 833:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_DATAWIDTH_8B 834:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_DATAWIDTH_9B 835:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 836:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetDataWidth(const USART_TypeDef *USARTx) 837:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 838:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_M)); 839:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 840:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 841:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 842:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Allow switch between Mute Mode and Active mode 843:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 MME LL_USART_EnableMuteMode 844:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 845:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 846:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 847:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableMuteMode(USART_TypeDef *USARTx) 848:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 849:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_MME); 850:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 851:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 852:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 853:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Prevent Mute Mode use. Set Receiver in active mode permanently. 854:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 MME LL_USART_DisableMuteMode 855:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 856:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 857:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 858:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableMuteMode(USART_TypeDef *USARTx) 859:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 860:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_MME); 861:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } ARM GAS /tmp/ccYgfTud.s page 385 862:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 863:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 864:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Indicate if switch between Mute Mode and Active mode is allowed 865:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 MME LL_USART_IsEnabledMuteMode 866:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 867:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). 868:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 869:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledMuteMode(const USART_TypeDef *USARTx) 870:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 871:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->CR1, USART_CR1_MME) == (USART_CR1_MME)) ? 1UL : 0UL); 872:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 873:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 874:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 875:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Set Oversampling to 8-bit or 16-bit mode 876:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 OVER8 LL_USART_SetOverSampling 877:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 878:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param OverSampling This parameter can be one of the following values: 879:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_OVERSAMPLING_16 880:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_OVERSAMPLING_8 881:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 882:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 883:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetOverSampling(USART_TypeDef *USARTx, uint32_t OverSampling) 884:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 885:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** MODIFY_REG(USARTx->CR1, USART_CR1_OVER8, OverSampling); 886:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 887:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 888:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 889:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Return Oversampling mode 890:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 OVER8 LL_USART_GetOverSampling 891:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 892:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Returned value can be one of the following values: 893:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_OVERSAMPLING_16 894:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_OVERSAMPLING_8 895:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 896:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetOverSampling(const USART_TypeDef *USARTx) 897:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 898:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_OVER8)); 899:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 900:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 901:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 902:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Configure if Clock pulse of the last data bit is output to the SCLK pin or not 903:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not 904:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Synchronous mode is supported by the USARTx instance. 905:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 LBCL LL_USART_SetLastClkPulseOutput 906:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param LastBitClockPulse This parameter can be one of the following values: 908:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT 909:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_LASTCLKPULSE_OUTPUT 910:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 911:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 912:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetLastClkPulseOutput(USART_TypeDef *USARTx, uint32_t LastBitClockPul 913:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 914:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** MODIFY_REG(USARTx->CR2, USART_CR2_LBCL, LastBitClockPulse); 915:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 916:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 917:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Retrieve Clock pulse of the last data bit output configuration ARM GAS /tmp/ccYgfTud.s page 386 919:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * (Last bit Clock pulse output to the SCLK pin or not) 920:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not 921:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Synchronous mode is supported by the USARTx instance. 922:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 LBCL LL_USART_GetLastClkPulseOutput 923:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 924:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Returned value can be one of the following values: 925:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT 926:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_LASTCLKPULSE_OUTPUT 927:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 928:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetLastClkPulseOutput(const USART_TypeDef *USARTx) 929:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 930:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_LBCL)); 931:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 932:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 933:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 934:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Select the phase of the clock output on the SCLK pin in synchronous mode 935:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not 936:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Synchronous mode is supported by the USARTx instance. 937:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 CPHA LL_USART_SetClockPhase 938:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 939:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param ClockPhase This parameter can be one of the following values: 940:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_PHASE_1EDGE 941:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_PHASE_2EDGE 942:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 943:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 944:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetClockPhase(USART_TypeDef *USARTx, uint32_t ClockPhase) 945:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 946:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** MODIFY_REG(USARTx->CR2, USART_CR2_CPHA, ClockPhase); 947:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 948:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 949:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 950:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Return phase of the clock output on the SCLK pin in synchronous mode 951:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not 952:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Synchronous mode is supported by the USARTx instance. 953:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 CPHA LL_USART_GetClockPhase 954:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 955:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Returned value can be one of the following values: 956:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_PHASE_1EDGE 957:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_PHASE_2EDGE 958:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 959:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetClockPhase(const USART_TypeDef *USARTx) 960:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 961:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_CPHA)); 962:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 963:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 964:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 965:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Select the polarity of the clock output on the SCLK pin in synchronous mode 966:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not 967:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Synchronous mode is supported by the USARTx instance. 968:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 CPOL LL_USART_SetClockPolarity 969:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 970:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param ClockPolarity This parameter can be one of the following values: 971:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_POLARITY_LOW 972:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_POLARITY_HIGH 973:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 974:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 975:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetClockPolarity(USART_TypeDef *USARTx, uint32_t ClockPolarity) ARM GAS /tmp/ccYgfTud.s page 387 976:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 977:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** MODIFY_REG(USARTx->CR2, USART_CR2_CPOL, ClockPolarity); 978:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 979:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 980:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 981:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Return polarity of the clock output on the SCLK pin in synchronous mode 982:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not 983:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Synchronous mode is supported by the USARTx instance. 984:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 CPOL LL_USART_GetClockPolarity 985:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 986:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Returned value can be one of the following values: 987:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_POLARITY_LOW 988:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_POLARITY_HIGH 989:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 990:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetClockPolarity(const USART_TypeDef *USARTx) 991:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 992:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_CPOL)); 993:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 994:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 995:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 996:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Configure Clock signal format (Phase Polarity and choice about output of last bit clock 997:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not 998:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Synchronous mode is supported by the USARTx instance. 999:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Call of this function is equivalent to following function call sequence : 1000:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Clock Phase configuration using @ref LL_USART_SetClockPhase() function 1001:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Clock Polarity configuration using @ref LL_USART_SetClockPolarity() function 1002:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Output of Last bit Clock pulse configuration using @ref LL_USART_SetLastClkPulseOutpu 1003:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 CPHA LL_USART_ConfigClock\n 1004:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR2 CPOL LL_USART_ConfigClock\n 1005:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR2 LBCL LL_USART_ConfigClock 1006:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1007:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param Phase This parameter can be one of the following values: 1008:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_PHASE_1EDGE 1009:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_PHASE_2EDGE 1010:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param Polarity This parameter can be one of the following values: 1011:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_POLARITY_LOW 1012:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_POLARITY_HIGH 1013:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param LBCPOutput This parameter can be one of the following values: 1014:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT 1015:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_LASTCLKPULSE_OUTPUT 1016:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 1017:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1018:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_ConfigClock(USART_TypeDef *USARTx, uint32_t Phase, uint32_t Polarity, 1019:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1020:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** MODIFY_REG(USARTx->CR2, USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_LBCL, Phase | Polarity | LBCP 1021:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1022:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1023:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1024:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Enable Clock output on SCLK pin 1025:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not 1026:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Synchronous mode is supported by the USARTx instance. 1027:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 CLKEN LL_USART_EnableSCLKOutput 1028:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1029:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 1030:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1031:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableSCLKOutput(USART_TypeDef *USARTx) 1032:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { ARM GAS /tmp/ccYgfTud.s page 388 1033:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** SET_BIT(USARTx->CR2, USART_CR2_CLKEN); 1034:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1035:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1036:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1037:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Disable Clock output on SCLK pin 1038:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not 1039:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Synchronous mode is supported by the USARTx instance. 1040:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 CLKEN LL_USART_DisableSCLKOutput 1041:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1042:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 1043:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1044:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableSCLKOutput(USART_TypeDef *USARTx) 1045:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1046:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** CLEAR_BIT(USARTx->CR2, USART_CR2_CLKEN); 1047:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1048:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1049:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1050:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Indicate if Clock output on SCLK pin is enabled 1051:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not 1052:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Synchronous mode is supported by the USARTx instance. 1053:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 CLKEN LL_USART_IsEnabledSCLKOutput 1054:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1055:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). 1056:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1057:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledSCLKOutput(const USART_TypeDef *USARTx) 1058:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1059:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->CR2, USART_CR2_CLKEN) == (USART_CR2_CLKEN)) ? 1UL : 0UL); 1060:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1061:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1062:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1063:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Set the length of the stop bits 1064:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 STOP LL_USART_SetStopBitsLength 1065:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1066:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param StopBits This parameter can be one of the following values: 1067:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_STOPBITS_0_5 1068:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_STOPBITS_1 1069:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_STOPBITS_1_5 1070:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_STOPBITS_2 1071:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 1072:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1073:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetStopBitsLength(USART_TypeDef *USARTx, uint32_t StopBits) 1074:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1075:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** MODIFY_REG(USARTx->CR2, USART_CR2_STOP, StopBits); 1076:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1077:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1078:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1079:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Retrieve the length of the stop bits 1080:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 STOP LL_USART_GetStopBitsLength 1081:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1082:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Returned value can be one of the following values: 1083:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_STOPBITS_0_5 1084:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_STOPBITS_1 1085:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_STOPBITS_1_5 1086:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_STOPBITS_2 1087:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1088:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetStopBitsLength(const USART_TypeDef *USARTx) 1089:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { ARM GAS /tmp/ccYgfTud.s page 389 1090:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_STOP)); 1091:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1092:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1093:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1094:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Configure Character frame format (Datawidth, Parity control, Stop Bits) 1095:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Call of this function is equivalent to following function call sequence : 1096:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Data Width configuration using @ref LL_USART_SetDataWidth() function 1097:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Parity Control and mode configuration using @ref LL_USART_SetParity() function 1098:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Stop bits configuration using @ref LL_USART_SetStopBitsLength() function 1099:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 PS LL_USART_ConfigCharacter\n 1100:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR1 PCE LL_USART_ConfigCharacter\n 1101:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR1 M0 LL_USART_ConfigCharacter\n 1102:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR1 M1 LL_USART_ConfigCharacter\n 1103:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR2 STOP LL_USART_ConfigCharacter 1104:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1105:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param DataWidth This parameter can be one of the following values: 1106:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_DATAWIDTH_7B 1107:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_DATAWIDTH_8B 1108:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_DATAWIDTH_9B 1109:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param Parity This parameter can be one of the following values: 1110:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_PARITY_NONE 1111:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_PARITY_EVEN 1112:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_PARITY_ODD 1113:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param StopBits This parameter can be one of the following values: 1114:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_STOPBITS_0_5 1115:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_STOPBITS_1 1116:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_STOPBITS_1_5 1117:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_STOPBITS_2 1118:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 1119:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1120:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_ConfigCharacter(USART_TypeDef *USARTx, uint32_t DataWidth, uint32_t P 1121:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** uint32_t StopBits) 1122:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1123:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** MODIFY_REG(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE | USART_CR1_M, Parity | DataWidth); 1124:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** MODIFY_REG(USARTx->CR2, USART_CR2_STOP, StopBits); 1125:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1126:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1127:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1128:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Configure TX/RX pins swapping setting. 1129:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 SWAP LL_USART_SetTXRXSwap 1130:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1131:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param SwapConfig This parameter can be one of the following values: 1132:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_TXRX_STANDARD 1133:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_TXRX_SWAPPED 1134:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 1135:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1136:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetTXRXSwap(USART_TypeDef *USARTx, uint32_t SwapConfig) 1137:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1138:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** MODIFY_REG(USARTx->CR2, USART_CR2_SWAP, SwapConfig); 1139:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1140:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1141:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1142:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Retrieve TX/RX pins swapping configuration. 1143:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 SWAP LL_USART_GetTXRXSwap 1144:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1145:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Returned value can be one of the following values: 1146:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_TXRX_STANDARD ARM GAS /tmp/ccYgfTud.s page 390 1147:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_TXRX_SWAPPED 1148:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1149:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetTXRXSwap(const USART_TypeDef *USARTx) 1150:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1151:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_SWAP)); 1152:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1153:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1154:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1155:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Configure RX pin active level logic 1156:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 RXINV LL_USART_SetRXPinLevel 1157:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1158:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param PinInvMethod This parameter can be one of the following values: 1159:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_RXPIN_LEVEL_STANDARD 1160:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_RXPIN_LEVEL_INVERTED 1161:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 1162:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1163:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetRXPinLevel(USART_TypeDef *USARTx, uint32_t PinInvMethod) 1164:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1165:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** MODIFY_REG(USARTx->CR2, USART_CR2_RXINV, PinInvMethod); 1166:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1167:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1168:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1169:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Retrieve RX pin active level logic configuration 1170:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 RXINV LL_USART_GetRXPinLevel 1171:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1172:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Returned value can be one of the following values: 1173:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_RXPIN_LEVEL_STANDARD 1174:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_RXPIN_LEVEL_INVERTED 1175:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1176:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetRXPinLevel(const USART_TypeDef *USARTx) 1177:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1178:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_RXINV)); 1179:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1180:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1181:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1182:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Configure TX pin active level logic 1183:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 TXINV LL_USART_SetTXPinLevel 1184:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1185:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param PinInvMethod This parameter can be one of the following values: 1186:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_TXPIN_LEVEL_STANDARD 1187:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_TXPIN_LEVEL_INVERTED 1188:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 1189:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1190:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetTXPinLevel(USART_TypeDef *USARTx, uint32_t PinInvMethod) 1191:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1192:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** MODIFY_REG(USARTx->CR2, USART_CR2_TXINV, PinInvMethod); 1193:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1194:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1195:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1196:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Retrieve TX pin active level logic configuration 1197:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 TXINV LL_USART_GetTXPinLevel 1198:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1199:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Returned value can be one of the following values: 1200:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_TXPIN_LEVEL_STANDARD 1201:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_TXPIN_LEVEL_INVERTED 1202:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1203:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetTXPinLevel(const USART_TypeDef *USARTx) ARM GAS /tmp/ccYgfTud.s page 391 1204:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1205:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_TXINV)); 1206:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1207:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1208:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1209:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Configure Binary data logic. 1210:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Allow to define how Logical data from the data register are send/received : 1211:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * either in positive/direct logic (1=H, 0=L) or in negative/inverse logic (1=L, 0=H) 1212:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 DATAINV LL_USART_SetBinaryDataLogic 1213:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1214:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param DataLogic This parameter can be one of the following values: 1215:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_BINARY_LOGIC_POSITIVE 1216:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_BINARY_LOGIC_NEGATIVE 1217:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 1218:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1219:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetBinaryDataLogic(USART_TypeDef *USARTx, uint32_t DataLogic) 1220:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1221:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** MODIFY_REG(USARTx->CR2, USART_CR2_DATAINV, DataLogic); 1222:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1223:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1224:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1225:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Retrieve Binary data configuration 1226:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 DATAINV LL_USART_GetBinaryDataLogic 1227:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1228:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Returned value can be one of the following values: 1229:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_BINARY_LOGIC_POSITIVE 1230:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_BINARY_LOGIC_NEGATIVE 1231:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1232:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetBinaryDataLogic(const USART_TypeDef *USARTx) 1233:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1234:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_DATAINV)); 1235:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1236:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1237:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1238:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Configure transfer bit order (either Less or Most Significant Bit First) 1239:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note MSB First means data is transmitted/received with the MSB first, following the start bi 1240:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * LSB First means data is transmitted/received with data bit 0 first, following the start 1241:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 MSBFIRST LL_USART_SetTransferBitOrder 1242:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1243:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param BitOrder This parameter can be one of the following values: 1244:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_BITORDER_LSBFIRST 1245:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_BITORDER_MSBFIRST 1246:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 1247:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1248:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetTransferBitOrder(USART_TypeDef *USARTx, uint32_t BitOrder) 1249:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1250:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** MODIFY_REG(USARTx->CR2, USART_CR2_MSBFIRST, BitOrder); 1251:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1252:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1253:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1254:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Return transfer bit order (either Less or Most Significant Bit First) 1255:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note MSB First means data is transmitted/received with the MSB first, following the start bi 1256:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * LSB First means data is transmitted/received with data bit 0 first, following the start 1257:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 MSBFIRST LL_USART_GetTransferBitOrder 1258:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1259:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Returned value can be one of the following values: 1260:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_BITORDER_LSBFIRST ARM GAS /tmp/ccYgfTud.s page 392 1261:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_BITORDER_MSBFIRST 1262:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1263:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetTransferBitOrder(const USART_TypeDef *USARTx) 1264:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1265:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_MSBFIRST)); 1266:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1267:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1268:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1269:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Enable Auto Baud-Rate Detection 1270:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or 1271:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Auto Baud Rate detection feature is supported by the USARTx instance. 1272:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 ABREN LL_USART_EnableAutoBaudRate 1273:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1274:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 1275:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1276:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableAutoBaudRate(USART_TypeDef *USARTx) 1277:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1278:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** SET_BIT(USARTx->CR2, USART_CR2_ABREN); 1279:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1280:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1281:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1282:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Disable Auto Baud-Rate Detection 1283:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or 1284:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Auto Baud Rate detection feature is supported by the USARTx instance. 1285:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 ABREN LL_USART_DisableAutoBaudRate 1286:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1287:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 1288:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1289:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableAutoBaudRate(USART_TypeDef *USARTx) 1290:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1291:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** CLEAR_BIT(USARTx->CR2, USART_CR2_ABREN); 1292:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1293:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1294:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1295:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Indicate if Auto Baud-Rate Detection mechanism is enabled 1296:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or 1297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Auto Baud Rate detection feature is supported by the USARTx instance. 1298:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 ABREN LL_USART_IsEnabledAutoBaud 1299:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1300:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). 1301:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1302:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledAutoBaud(const USART_TypeDef *USARTx) 1303:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1304:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->CR2, USART_CR2_ABREN) == (USART_CR2_ABREN)) ? 1UL : 0UL); 1305:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1306:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1307:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1308:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Set Auto Baud-Rate mode bits 1309:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or 1310:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Auto Baud Rate detection feature is supported by the USARTx instance. 1311:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 ABRMODE LL_USART_SetAutoBaudRateMode 1312:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1313:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param AutoBaudRateMode This parameter can be one of the following values: 1314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_STARTBIT 1315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_FALLINGEDGE 1316:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME 1317:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_55_FRAME ARM GAS /tmp/ccYgfTud.s page 393 1318:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 1319:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1320:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetAutoBaudRateMode(USART_TypeDef *USARTx, uint32_t AutoBaudRateMode) 1321:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1322:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** MODIFY_REG(USARTx->CR2, USART_CR2_ABRMODE, AutoBaudRateMode); 1323:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1324:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1325:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1326:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Return Auto Baud-Rate mode 1327:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or 1328:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Auto Baud Rate detection feature is supported by the USARTx instance. 1329:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 ABRMODE LL_USART_GetAutoBaudRateMode 1330:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1331:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Returned value can be one of the following values: 1332:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_STARTBIT 1333:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_FALLINGEDGE 1334:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME 1335:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_55_FRAME 1336:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1337:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetAutoBaudRateMode(const USART_TypeDef *USARTx) 1338:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1339:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_ABRMODE)); 1340:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1341:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1342:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1343:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Enable Receiver Timeout 1344:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 RTOEN LL_USART_EnableRxTimeout 1345:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 1347:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1348:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableRxTimeout(USART_TypeDef *USARTx) 1349:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1350:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** SET_BIT(USARTx->CR2, USART_CR2_RTOEN); 1351:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1352:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1353:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1354:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Disable Receiver Timeout 1355:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 RTOEN LL_USART_DisableRxTimeout 1356:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1357:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 1358:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1359:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableRxTimeout(USART_TypeDef *USARTx) 1360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1361:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** CLEAR_BIT(USARTx->CR2, USART_CR2_RTOEN); 1362:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1363:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1364:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1365:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Indicate if Receiver Timeout feature is enabled 1366:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 RTOEN LL_USART_IsEnabledRxTimeout 1367:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1368:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). 1369:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledRxTimeout(const USART_TypeDef *USARTx) 1371:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->CR2, USART_CR2_RTOEN) == (USART_CR2_RTOEN)) ? 1UL : 0UL); 1373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1374:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ARM GAS /tmp/ccYgfTud.s page 394 1375:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1376:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Set Address of the USART node. 1377:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note This is used in multiprocessor communication during Mute mode or Stop mode, 1378:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * for wake up with address mark detection. 1379:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note 4bits address node is used when 4-bit Address Detection is selected in ADDM7. 1380:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * (b7-b4 should be set to 0) 1381:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * 8bits address node is used when 7-bit Address Detection is selected in ADDM7. 1382:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * (This is used in multiprocessor communication during Mute mode or Stop mode, 1383:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * for wake up with 7-bit address mark detection. 1384:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * The MSB of the character sent by the transmitter should be equal to 1. 1385:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * It may also be used for character detection during normal reception, 1386:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Mute mode inactive (for example, end of block detection in ModBus protocol). 1387:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * In this case, the whole received character (8-bit) is compared to the ADD[7:0] 1388:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * value and CMF flag is set on match) 1389:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 ADD LL_USART_ConfigNodeAddress\n 1390:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR2 ADDM7 LL_USART_ConfigNodeAddress 1391:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1392:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param AddressLen This parameter can be one of the following values: 1393:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_ADDRESS_DETECT_4B 1394:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_ADDRESS_DETECT_7B 1395:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param NodeAddress 4 or 7 bit Address of the USART node. 1396:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 1397:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1398:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_ConfigNodeAddress(USART_TypeDef *USARTx, uint32_t AddressLen, uint32_ 1399:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1400:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** MODIFY_REG(USARTx->CR2, USART_CR2_ADD | USART_CR2_ADDM7, 1401:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** (uint32_t)(AddressLen | (NodeAddress << USART_CR2_ADD_Pos))); 1402:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1403:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1404:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1405:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Return 8 bit Address of the USART node as set in ADD field of CR2. 1406:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note If 4-bit Address Detection is selected in ADDM7, 1407:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * only 4bits (b3-b0) of returned value are relevant (b31-b4 are not relevant) 1408:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * If 7-bit Address Detection is selected in ADDM7, 1409:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * only 8bits (b7-b0) of returned value are relevant (b31-b8 are not relevant) 1410:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 ADD LL_USART_GetNodeAddress 1411:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1412:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Address of the USART node (Value between Min_Data=0 and Max_Data=255) 1413:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1414:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetNodeAddress(const USART_TypeDef *USARTx) 1415:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1416:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_ADD) >> USART_CR2_ADD_Pos); 1417:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1418:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1419:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1420:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Return Length of Node Address used in Address Detection mode (7-bit or 4-bit) 1421:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 ADDM7 LL_USART_GetNodeAddressLen 1422:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1423:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Returned value can be one of the following values: 1424:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_ADDRESS_DETECT_4B 1425:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_ADDRESS_DETECT_7B 1426:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1427:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetNodeAddressLen(const USART_TypeDef *USARTx) 1428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1429:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_ADDM7)); 1430:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1431:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ARM GAS /tmp/ccYgfTud.s page 395 1432:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1433:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Enable RTS HW Flow Control 1434:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not 1435:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Hardware Flow control feature is supported by the USARTx instance. 1436:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 RTSE LL_USART_EnableRTSHWFlowCtrl 1437:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1438:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 1439:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1440:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableRTSHWFlowCtrl(USART_TypeDef *USARTx) 1441:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1442:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** SET_BIT(USARTx->CR3, USART_CR3_RTSE); 1443:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1444:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1445:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1446:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Disable RTS HW Flow Control 1447:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not 1448:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Hardware Flow control feature is supported by the USARTx instance. 1449:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 RTSE LL_USART_DisableRTSHWFlowCtrl 1450:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1451:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 1452:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1453:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableRTSHWFlowCtrl(USART_TypeDef *USARTx) 1454:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1455:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** CLEAR_BIT(USARTx->CR3, USART_CR3_RTSE); 1456:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1457:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1458:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1459:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Enable CTS HW Flow Control 1460:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not 1461:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Hardware Flow control feature is supported by the USARTx instance. 1462:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 CTSE LL_USART_EnableCTSHWFlowCtrl 1463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1464:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 1465:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1466:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableCTSHWFlowCtrl(USART_TypeDef *USARTx) 1467:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1468:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** SET_BIT(USARTx->CR3, USART_CR3_CTSE); 1469:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1470:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1471:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1472:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Disable CTS HW Flow Control 1473:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not 1474:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Hardware Flow control feature is supported by the USARTx instance. 1475:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 CTSE LL_USART_DisableCTSHWFlowCtrl 1476:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1477:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 1478:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1479:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableCTSHWFlowCtrl(USART_TypeDef *USARTx) 1480:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1481:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** CLEAR_BIT(USARTx->CR3, USART_CR3_CTSE); 1482:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1483:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1484:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1485:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Configure HW Flow Control mode (both CTS and RTS) 1486:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not 1487:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Hardware Flow control feature is supported by the USARTx instance. 1488:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 RTSE LL_USART_SetHWFlowCtrl\n ARM GAS /tmp/ccYgfTud.s page 396 1489:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR3 CTSE LL_USART_SetHWFlowCtrl 1490:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1491:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param HardwareFlowControl This parameter can be one of the following values: 1492:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_HWCONTROL_NONE 1493:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_HWCONTROL_RTS 1494:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_HWCONTROL_CTS 1495:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_HWCONTROL_RTS_CTS 1496:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 1497:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1498:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetHWFlowCtrl(USART_TypeDef *USARTx, uint32_t HardwareFlowControl) 1499:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1500:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** MODIFY_REG(USARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE, HardwareFlowControl); 1501:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1502:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1503:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1504:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Return HW Flow Control configuration (both CTS and RTS) 1505:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not 1506:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Hardware Flow control feature is supported by the USARTx instance. 1507:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 RTSE LL_USART_GetHWFlowCtrl\n 1508:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR3 CTSE LL_USART_GetHWFlowCtrl 1509:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1510:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Returned value can be one of the following values: 1511:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_HWCONTROL_NONE 1512:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_HWCONTROL_RTS 1513:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_HWCONTROL_CTS 1514:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_HWCONTROL_RTS_CTS 1515:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1516:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetHWFlowCtrl(const USART_TypeDef *USARTx) 1517:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1518:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE)); 1519:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1520:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1521:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1522:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Enable One bit sampling method 1523:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 ONEBIT LL_USART_EnableOneBitSamp 1524:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1525:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 1526:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1527:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableOneBitSamp(USART_TypeDef *USARTx) 1528:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1529:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** SET_BIT(USARTx->CR3, USART_CR3_ONEBIT); 1530:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1531:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1532:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1533:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Disable One bit sampling method 1534:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 ONEBIT LL_USART_DisableOneBitSamp 1535:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1536:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 1537:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1538:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableOneBitSamp(USART_TypeDef *USARTx) 1539:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1540:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** CLEAR_BIT(USARTx->CR3, USART_CR3_ONEBIT); 1541:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1542:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1543:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1544:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Indicate if One bit sampling method is enabled 1545:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 ONEBIT LL_USART_IsEnabledOneBitSamp ARM GAS /tmp/ccYgfTud.s page 397 1546:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1547:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). 1548:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1549:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledOneBitSamp(const USART_TypeDef *USARTx) 1550:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1551:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->CR3, USART_CR3_ONEBIT) == (USART_CR3_ONEBIT)) ? 1UL : 0UL); 1552:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1553:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1554:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1555:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Enable Overrun detection 1556:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 OVRDIS LL_USART_EnableOverrunDetect 1557:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1558:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 1559:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1560:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableOverrunDetect(USART_TypeDef *USARTx) 1561:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1562:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** CLEAR_BIT(USARTx->CR3, USART_CR3_OVRDIS); 1563:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1564:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1565:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1566:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Disable Overrun detection 1567:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 OVRDIS LL_USART_DisableOverrunDetect 1568:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1569:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 1570:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1571:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableOverrunDetect(USART_TypeDef *USARTx) 1572:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1573:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** SET_BIT(USARTx->CR3, USART_CR3_OVRDIS); 1574:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1575:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1576:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1577:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Indicate if Overrun detection is enabled 1578:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 OVRDIS LL_USART_IsEnabledOverrunDetect 1579:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1580:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). 1581:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1582:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledOverrunDetect(const USART_TypeDef *USARTx) 1583:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1584:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->CR3, USART_CR3_OVRDIS) != USART_CR3_OVRDIS) ? 1UL : 0UL); 1585:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1586:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1587:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_CR1_UESM) 1588:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_CR3_WUS) 1589:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1590:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Select event type for Wake UP Interrupt Flag (WUS[1:0] bits) 1591:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not 1592:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Wake-up from Stop mode feature is supported by the USARTx instance. 1593:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 WUS LL_USART_SetWKUPType 1594:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1595:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param Type This parameter can be one of the following values: 1596:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_WAKEUP_ON_ADDRESS 1597:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_WAKEUP_ON_STARTBIT 1598:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_WAKEUP_ON_RXNE 1599:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 1600:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1601:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetWKUPType(USART_TypeDef *USARTx, uint32_t Type) 1602:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { ARM GAS /tmp/ccYgfTud.s page 398 1603:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** MODIFY_REG(USARTx->CR3, USART_CR3_WUS, Type); 1604:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1605:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1606:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1607:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Return event type for Wake UP Interrupt Flag (WUS[1:0] bits) 1608:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not 1609:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Wake-up from Stop mode feature is supported by the USARTx instance. 1610:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 WUS LL_USART_GetWKUPType 1611:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1612:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Returned value can be one of the following values: 1613:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_WAKEUP_ON_ADDRESS 1614:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_WAKEUP_ON_STARTBIT 1615:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_WAKEUP_ON_RXNE 1616:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1617:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetWKUPType(const USART_TypeDef *USARTx) 1618:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1619:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_WUS)); 1620:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1621:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1622:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_CR3_WUS */ 1623:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_CR1_UESM */ 1624:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1625:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Configure USART BRR register for achieving expected Baud Rate value. 1626:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Compute and set USARTDIV value in BRR Register (full BRR content) 1627:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * according to used Peripheral Clock, Oversampling mode, and expected Baud Rate values 1628:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Peripheral clock and Baud rate values provided as function parameters should be valid 1629:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * (Baud rate value != 0) 1630:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note In case of oversampling by 16 and 8, BRR content must be greater than or equal to 16d. 1631:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll BRR BRR LL_USART_SetBaudRate 1632:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1633:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param PeriphClk Peripheral Clock 1634:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param OverSampling This parameter can be one of the following values: 1635:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_OVERSAMPLING_16 1636:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_OVERSAMPLING_8 1637:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param BaudRate Baud Rate 1638:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 1639:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1640:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetBaudRate(USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t OverS 1641:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** uint32_t BaudRate) 1642:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1643:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** uint32_t usartdiv; 1644:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** uint32_t brrtemp; 1645:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1646:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** if (OverSampling == LL_USART_OVERSAMPLING_8) 1647:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1648:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** usartdiv = (uint16_t)(__LL_USART_DIV_SAMPLING8(PeriphClk, BaudRate)); 1649:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** brrtemp = usartdiv & 0xFFF0U; 1650:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U); 1651:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** USARTx->BRR = brrtemp; 1652:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1653:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** else 1654:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1655:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** USARTx->BRR = (uint16_t)(__LL_USART_DIV_SAMPLING16(PeriphClk, BaudRate)); 1656:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1657:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1658:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1659:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** ARM GAS /tmp/ccYgfTud.s page 399 1660:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Return current Baud Rate value, according to USARTDIV present in BRR register 1661:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * (full BRR content), and to used Peripheral Clock and Oversampling mode values 1662:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note In case of non-initialized or invalid value stored in BRR register, value 0 will be ret 1663:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note In case of oversampling by 16 and 8, BRR content must be greater than or equal to 16d. 1664:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll BRR BRR LL_USART_GetBaudRate 1665:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1666:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param PeriphClk Peripheral Clock 1667:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param OverSampling This parameter can be one of the following values: 1668:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_OVERSAMPLING_16 1669:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_OVERSAMPLING_8 1670:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Baud Rate 1671:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1672:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetBaudRate(const USART_TypeDef *USARTx, uint32_t PeriphClk, uint 1673:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1674:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** uint32_t usartdiv; 1675:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** uint32_t brrresult = 0x0U; 1676:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1677:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** usartdiv = USARTx->BRR; 1678:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1679:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** if (usartdiv == 0U) 1680:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1681:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* Do not perform a division by 0 */ 1682:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1683:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** else if (OverSampling == LL_USART_OVERSAMPLING_8) 1684:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1685:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** usartdiv = (uint16_t)((usartdiv & 0xFFF0U) | ((usartdiv & 0x0007U) << 1U)) ; 1686:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** if (usartdiv != 0U) 1687:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1688:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** brrresult = (PeriphClk * 2U) / usartdiv; 1689:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1690:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1691:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** else 1692:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1693:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** if ((usartdiv & 0xFFFFU) != 0U) 1694:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1695:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** brrresult = PeriphClk / usartdiv; 1696:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1697:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1698:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return (brrresult); 1699:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1700:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1701:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1702:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Set Receiver Time Out Value (expressed in nb of bits duration) 1703:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll RTOR RTO LL_USART_SetRxTimeout 1704:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1705:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param Timeout Value between Min_Data=0x00 and Max_Data=0x00FFFFFF 1706:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 1707:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1708:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetRxTimeout(USART_TypeDef *USARTx, uint32_t Timeout) 1709:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1710:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** MODIFY_REG(USARTx->RTOR, USART_RTOR_RTO, Timeout); 1711:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1712:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1713:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1714:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Get Receiver Time Out Value (expressed in nb of bits duration) 1715:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll RTOR RTO LL_USART_GetRxTimeout 1716:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance ARM GAS /tmp/ccYgfTud.s page 400 1717:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Value between Min_Data=0x00 and Max_Data=0x00FFFFFF 1718:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1719:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetRxTimeout(const USART_TypeDef *USARTx) 1720:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1721:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return (uint32_t)(READ_BIT(USARTx->RTOR, USART_RTOR_RTO)); 1722:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1723:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1724:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1725:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Set Block Length value in reception 1726:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll RTOR BLEN LL_USART_SetBlockLength 1727:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1728:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param BlockLength Value between Min_Data=0x00 and Max_Data=0xFF 1729:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 1730:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1731:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetBlockLength(USART_TypeDef *USARTx, uint32_t BlockLength) 1732:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1733:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** MODIFY_REG(USARTx->RTOR, USART_RTOR_BLEN, BlockLength << USART_RTOR_BLEN_Pos); 1734:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1735:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1736:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1737:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Get Block Length value in reception 1738:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll RTOR BLEN LL_USART_GetBlockLength 1739:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1740:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Value between Min_Data=0x00 and Max_Data=0xFF 1741:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1742:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetBlockLength(const USART_TypeDef *USARTx) 1743:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1744:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return (uint32_t)(READ_BIT(USARTx->RTOR, USART_RTOR_BLEN) >> USART_RTOR_BLEN_Pos); 1745:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1746:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1747:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1748:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} 1749:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1750:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1751:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EF_Configuration_IRDA Configuration functions related to Irda feature 1752:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ 1753:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1754:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1755:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1756:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Enable IrDA mode 1757:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not 1758:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * IrDA feature is supported by the USARTx instance. 1759:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 IREN LL_USART_EnableIrda 1760:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1761:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 1762:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1763:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableIrda(USART_TypeDef *USARTx) 1764:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1765:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** SET_BIT(USARTx->CR3, USART_CR3_IREN); 1766:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1767:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1768:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1769:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Disable IrDA mode 1770:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not 1771:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * IrDA feature is supported by the USARTx instance. 1772:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 IREN LL_USART_DisableIrda 1773:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance ARM GAS /tmp/ccYgfTud.s page 401 1774:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 1775:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1776:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableIrda(USART_TypeDef *USARTx) 1777:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1778:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** CLEAR_BIT(USARTx->CR3, USART_CR3_IREN); 1779:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1780:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1781:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1782:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Indicate if IrDA mode is enabled 1783:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not 1784:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * IrDA feature is supported by the USARTx instance. 1785:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 IREN LL_USART_IsEnabledIrda 1786:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1787:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). 1788:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1789:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledIrda(const USART_TypeDef *USARTx) 1790:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1791:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->CR3, USART_CR3_IREN) == (USART_CR3_IREN)) ? 1UL : 0UL); 1792:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1793:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1794:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1795:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Configure IrDA Power Mode (Normal or Low Power) 1796:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not 1797:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * IrDA feature is supported by the USARTx instance. 1798:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 IRLP LL_USART_SetIrdaPowerMode 1799:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1800:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param PowerMode This parameter can be one of the following values: 1801:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_IRDA_POWER_NORMAL 1802:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_IRDA_POWER_LOW 1803:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 1804:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1805:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetIrdaPowerMode(USART_TypeDef *USARTx, uint32_t PowerMode) 1806:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1807:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** MODIFY_REG(USARTx->CR3, USART_CR3_IRLP, PowerMode); 1808:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1809:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1810:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1811:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Retrieve IrDA Power Mode configuration (Normal or Low Power) 1812:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not 1813:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * IrDA feature is supported by the USARTx instance. 1814:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 IRLP LL_USART_GetIrdaPowerMode 1815:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1816:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Returned value can be one of the following values: 1817:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_IRDA_POWER_NORMAL 1818:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_PHASE_2EDGE 1819:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1820:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetIrdaPowerMode(const USART_TypeDef *USARTx) 1821:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1822:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_IRLP)); 1823:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1824:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1825:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1826:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Set Irda prescaler value, used for dividing the USART clock source 1827:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * to achieve the Irda Low Power frequency (8 bits value) 1828:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not 1829:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * IrDA feature is supported by the USARTx instance. 1830:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll GTPR PSC LL_USART_SetIrdaPrescaler ARM GAS /tmp/ccYgfTud.s page 402 1831:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1832:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param PrescalerValue Value between Min_Data=0x00 and Max_Data=0xFF 1833:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 1834:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1835:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetIrdaPrescaler(USART_TypeDef *USARTx, uint32_t PrescalerValue) 1836:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1837:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** MODIFY_REG(USARTx->GTPR, USART_GTPR_PSC, (uint16_t)PrescalerValue); 1838:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1839:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1840:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1841:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Return Irda prescaler value, used for dividing the USART clock source 1842:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * to achieve the Irda Low Power frequency (8 bits value) 1843:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not 1844:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * IrDA feature is supported by the USARTx instance. 1845:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll GTPR PSC LL_USART_GetIrdaPrescaler 1846:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1847:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Irda prescaler value (Value between Min_Data=0x00 and Max_Data=0xFF) 1848:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1849:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetIrdaPrescaler(const USART_TypeDef *USARTx) 1850:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1851:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_PSC)); 1852:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1853:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1854:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1855:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} 1856:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1857:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1858:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EF_Configuration_Smartcard Configuration functions related to Smartcard feat 1859:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ 1860:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1861:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1862:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1863:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Enable Smartcard NACK transmission 1864:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not 1865:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Smartcard feature is supported by the USARTx instance. 1866:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 NACK LL_USART_EnableSmartcardNACK 1867:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1868:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 1869:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1870:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableSmartcardNACK(USART_TypeDef *USARTx) 1871:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1872:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** SET_BIT(USARTx->CR3, USART_CR3_NACK); 1873:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1874:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1875:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1876:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Disable Smartcard NACK transmission 1877:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not 1878:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Smartcard feature is supported by the USARTx instance. 1879:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 NACK LL_USART_DisableSmartcardNACK 1880:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1881:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 1882:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1883:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableSmartcardNACK(USART_TypeDef *USARTx) 1884:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1885:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** CLEAR_BIT(USARTx->CR3, USART_CR3_NACK); 1886:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1887:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ARM GAS /tmp/ccYgfTud.s page 403 1888:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1889:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Indicate if Smartcard NACK transmission is enabled 1890:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not 1891:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Smartcard feature is supported by the USARTx instance. 1892:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 NACK LL_USART_IsEnabledSmartcardNACK 1893:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1894:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). 1895:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1896:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcardNACK(const USART_TypeDef *USARTx) 1897:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1898:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->CR3, USART_CR3_NACK) == (USART_CR3_NACK)) ? 1UL : 0UL); 1899:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1900:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1901:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1902:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Enable Smartcard mode 1903:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not 1904:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Smartcard feature is supported by the USARTx instance. 1905:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 SCEN LL_USART_EnableSmartcard 1906:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 1908:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1909:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableSmartcard(USART_TypeDef *USARTx) 1910:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1911:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** SET_BIT(USARTx->CR3, USART_CR3_SCEN); 1912:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1913:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1914:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1915:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Disable Smartcard mode 1916:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not 1917:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Smartcard feature is supported by the USARTx instance. 1918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 SCEN LL_USART_DisableSmartcard 1919:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1920:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 1921:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1922:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableSmartcard(USART_TypeDef *USARTx) 1923:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1924:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** CLEAR_BIT(USARTx->CR3, USART_CR3_SCEN); 1925:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1926:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1927:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1928:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Indicate if Smartcard mode is enabled 1929:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not 1930:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Smartcard feature is supported by the USARTx instance. 1931:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 SCEN LL_USART_IsEnabledSmartcard 1932:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1933:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). 1934:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1935:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcard(const USART_TypeDef *USARTx) 1936:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1937:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->CR3, USART_CR3_SCEN) == (USART_CR3_SCEN)) ? 1UL : 0UL); 1938:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1939:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1940:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1941:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Set Smartcard Auto-Retry Count value (SCARCNT[2:0] bits) 1942:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not 1943:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Smartcard feature is supported by the USARTx instance. 1944:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note This bit-field specifies the number of retries in transmit and receive, in Smartcard mo ARM GAS /tmp/ccYgfTud.s page 404 1945:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * In transmission mode, it specifies the number of automatic retransmission retries, befo 1946:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * generating a transmission error (FE bit set). 1947:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * In reception mode, it specifies the number or erroneous reception trials, before genera 1948:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * reception error (RXNE and PE bits set) 1949:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 SCARCNT LL_USART_SetSmartcardAutoRetryCount 1950:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1951:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param AutoRetryCount Value between Min_Data=0 and Max_Data=7 1952:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 1953:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1954:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetSmartcardAutoRetryCount(USART_TypeDef *USARTx, uint32_t AutoRetryC 1955:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1956:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** MODIFY_REG(USARTx->CR3, USART_CR3_SCARCNT, AutoRetryCount << USART_CR3_SCARCNT_Pos); 1957:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1958:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1959:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1960:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Return Smartcard Auto-Retry Count value (SCARCNT[2:0] bits) 1961:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not 1962:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Smartcard feature is supported by the USARTx instance. 1963:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 SCARCNT LL_USART_GetSmartcardAutoRetryCount 1964:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1965:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Smartcard Auto-Retry Count value (Value between Min_Data=0 and Max_Data=7) 1966:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1967:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetSmartcardAutoRetryCount(const USART_TypeDef *USARTx) 1968:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1969:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_SCARCNT) >> USART_CR3_SCARCNT_Pos); 1970:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1971:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1972:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1973:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Set Smartcard prescaler value, used for dividing the USART clock 1974:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * source to provide the SMARTCARD Clock (5 bits value) 1975:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not 1976:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Smartcard feature is supported by the USARTx instance. 1977:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll GTPR PSC LL_USART_SetSmartcardPrescaler 1978:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1979:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param PrescalerValue Value between Min_Data=0 and Max_Data=31 1980:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 1981:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1982:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetSmartcardPrescaler(USART_TypeDef *USARTx, uint32_t PrescalerValue) 1983:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1984:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** MODIFY_REG(USARTx->GTPR, USART_GTPR_PSC, (uint16_t)PrescalerValue); 1985:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1986:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1987:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1988:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Return Smartcard prescaler value, used for dividing the USART clock 1989:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * source to provide the SMARTCARD Clock (5 bits value) 1990:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not 1991:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Smartcard feature is supported by the USARTx instance. 1992:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll GTPR PSC LL_USART_GetSmartcardPrescaler 1993:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1994:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Smartcard prescaler value (Value between Min_Data=0 and Max_Data=31) 1995:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1996:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetSmartcardPrescaler(const USART_TypeDef *USARTx) 1997:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1998:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_PSC)); 1999:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2000:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2001:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** ARM GAS /tmp/ccYgfTud.s page 405 2002:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Set Smartcard Guard time value, expressed in nb of baud clocks periods 2003:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * (GT[7:0] bits : Guard time value) 2004:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not 2005:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Smartcard feature is supported by the USARTx instance. 2006:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll GTPR GT LL_USART_SetSmartcardGuardTime 2007:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2008:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param GuardTime Value between Min_Data=0x00 and Max_Data=0xFF 2009:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 2010:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2011:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetSmartcardGuardTime(USART_TypeDef *USARTx, uint32_t GuardTime) 2012:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2013:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** MODIFY_REG(USARTx->GTPR, USART_GTPR_GT, (uint16_t)(GuardTime << USART_GTPR_GT_Pos)); 2014:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2015:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2016:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2017:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Return Smartcard Guard time value, expressed in nb of baud clocks periods 2018:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * (GT[7:0] bits : Guard time value) 2019:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not 2020:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Smartcard feature is supported by the USARTx instance. 2021:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll GTPR GT LL_USART_GetSmartcardGuardTime 2022:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2023:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Smartcard Guard time value (Value between Min_Data=0x00 and Max_Data=0xFF) 2024:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2025:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetSmartcardGuardTime(const USART_TypeDef *USARTx) 2026:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2027:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_GT) >> USART_GTPR_GT_Pos); 2028:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2029:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2030:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2031:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} 2032:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2033:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2034:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EF_Configuration_HalfDuplex Configuration functions related to Half Duplex f 2035:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ 2036:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2037:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2038:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2039:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Enable Single Wire Half-Duplex mode 2040:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not 2041:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Half-Duplex mode is supported by the USARTx instance. 2042:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 HDSEL LL_USART_EnableHalfDuplex 2043:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2044:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 2045:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2046:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableHalfDuplex(USART_TypeDef *USARTx) 2047:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2048:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** SET_BIT(USARTx->CR3, USART_CR3_HDSEL); 2049:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2050:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2051:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2052:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Disable Single Wire Half-Duplex mode 2053:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not 2054:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Half-Duplex mode is supported by the USARTx instance. 2055:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 HDSEL LL_USART_DisableHalfDuplex 2056:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2057:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 2058:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ ARM GAS /tmp/ccYgfTud.s page 406 2059:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableHalfDuplex(USART_TypeDef *USARTx) 2060:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2061:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** CLEAR_BIT(USARTx->CR3, USART_CR3_HDSEL); 2062:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2063:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2064:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2065:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Indicate if Single Wire Half-Duplex mode is enabled 2066:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not 2067:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Half-Duplex mode is supported by the USARTx instance. 2068:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 HDSEL LL_USART_IsEnabledHalfDuplex 2069:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2070:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). 2071:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2072:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledHalfDuplex(const USART_TypeDef *USARTx) 2073:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2074:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->CR3, USART_CR3_HDSEL) == (USART_CR3_HDSEL)) ? 1UL : 0UL); 2075:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2076:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2077:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2078:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} 2079:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2080:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2081:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EF_Configuration_LIN Configuration functions related to LIN feature 2082:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ 2083:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2084:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2085:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2086:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Set LIN Break Detection Length 2087:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not 2088:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * LIN feature is supported by the USARTx instance. 2089:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 LBDL LL_USART_SetLINBrkDetectionLen 2090:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2091:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param LINBDLength This parameter can be one of the following values: 2092:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_LINBREAK_DETECT_10B 2093:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_LINBREAK_DETECT_11B 2094:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 2095:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2096:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetLINBrkDetectionLen(USART_TypeDef *USARTx, uint32_t LINBDLength) 2097:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2098:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** MODIFY_REG(USARTx->CR2, USART_CR2_LBDL, LINBDLength); 2099:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2100:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2101:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2102:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Return LIN Break Detection Length 2103:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not 2104:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * LIN feature is supported by the USARTx instance. 2105:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 LBDL LL_USART_GetLINBrkDetectionLen 2106:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2107:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Returned value can be one of the following values: 2108:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_LINBREAK_DETECT_10B 2109:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_LINBREAK_DETECT_11B 2110:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2111:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetLINBrkDetectionLen(const USART_TypeDef *USARTx) 2112:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2113:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_LBDL)); 2114:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2115:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ARM GAS /tmp/ccYgfTud.s page 407 2116:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2117:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Enable LIN mode 2118:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not 2119:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * LIN feature is supported by the USARTx instance. 2120:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 LINEN LL_USART_EnableLIN 2121:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2122:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 2123:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2124:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableLIN(USART_TypeDef *USARTx) 2125:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2126:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** SET_BIT(USARTx->CR2, USART_CR2_LINEN); 2127:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2128:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2129:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2130:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Disable LIN mode 2131:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not 2132:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * LIN feature is supported by the USARTx instance. 2133:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 LINEN LL_USART_DisableLIN 2134:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2135:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 2136:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2137:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableLIN(USART_TypeDef *USARTx) 2138:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2139:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** CLEAR_BIT(USARTx->CR2, USART_CR2_LINEN); 2140:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2141:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2142:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2143:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Indicate if LIN mode is enabled 2144:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not 2145:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * LIN feature is supported by the USARTx instance. 2146:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 LINEN LL_USART_IsEnabledLIN 2147:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2148:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). 2149:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2150:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledLIN(const USART_TypeDef *USARTx) 2151:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2152:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->CR2, USART_CR2_LINEN) == (USART_CR2_LINEN)) ? 1UL : 0UL); 2153:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2154:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2155:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2156:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} 2157:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2158:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2159:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EF_Configuration_DE Configuration functions related to Driver Enable feature 2160:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ 2161:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2162:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2163:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2164:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Set DEDT (Driver Enable De-Assertion Time), Time value expressed on 5 bits ([4:0] bits) 2165:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not 2166:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Driver Enable feature is supported by the USARTx instance. 2167:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 DEDT LL_USART_SetDEDeassertionTime 2168:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2169:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param Time Value between Min_Data=0 and Max_Data=31 2170:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 2171:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2172:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetDEDeassertionTime(USART_TypeDef *USARTx, uint32_t Time) ARM GAS /tmp/ccYgfTud.s page 408 2173:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2174:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** MODIFY_REG(USARTx->CR1, USART_CR1_DEDT, Time << USART_CR1_DEDT_Pos); 2175:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2176:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2177:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2178:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Return DEDT (Driver Enable De-Assertion Time) 2179:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not 2180:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Driver Enable feature is supported by the USARTx instance. 2181:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 DEDT LL_USART_GetDEDeassertionTime 2182:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2183:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Time value expressed on 5 bits ([4:0] bits) : Value between Min_Data=0 and Max_Data=31 2184:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2185:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetDEDeassertionTime(const USART_TypeDef *USARTx) 2186:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2187:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_DEDT) >> USART_CR1_DEDT_Pos); 2188:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2189:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2190:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2191:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Set DEAT (Driver Enable Assertion Time), Time value expressed on 5 bits ([4:0] bits). 2192:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not 2193:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Driver Enable feature is supported by the USARTx instance. 2194:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 DEAT LL_USART_SetDEAssertionTime 2195:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2196:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param Time Value between Min_Data=0 and Max_Data=31 2197:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 2198:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2199:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetDEAssertionTime(USART_TypeDef *USARTx, uint32_t Time) 2200:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2201:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** MODIFY_REG(USARTx->CR1, USART_CR1_DEAT, Time << USART_CR1_DEAT_Pos); 2202:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2203:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2204:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2205:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Return DEAT (Driver Enable Assertion Time) 2206:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not 2207:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Driver Enable feature is supported by the USARTx instance. 2208:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 DEAT LL_USART_GetDEAssertionTime 2209:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2210:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Time value expressed on 5 bits ([4:0] bits) : Value between Min_Data=0 and Max_Data=31 2211:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2212:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetDEAssertionTime(const USART_TypeDef *USARTx) 2213:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2214:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_DEAT) >> USART_CR1_DEAT_Pos); 2215:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2216:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2217:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2218:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Enable Driver Enable (DE) Mode 2219:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not 2220:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Driver Enable feature is supported by the USARTx instance. 2221:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 DEM LL_USART_EnableDEMode 2222:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2223:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 2224:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2225:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableDEMode(USART_TypeDef *USARTx) 2226:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2227:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** SET_BIT(USARTx->CR3, USART_CR3_DEM); 2228:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2229:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ARM GAS /tmp/ccYgfTud.s page 409 2230:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2231:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Disable Driver Enable (DE) Mode 2232:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not 2233:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Driver Enable feature is supported by the USARTx instance. 2234:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 DEM LL_USART_DisableDEMode 2235:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2236:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 2237:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2238:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableDEMode(USART_TypeDef *USARTx) 2239:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2240:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** CLEAR_BIT(USARTx->CR3, USART_CR3_DEM); 2241:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2242:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2243:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2244:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Indicate if Driver Enable (DE) Mode is enabled 2245:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not 2246:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Driver Enable feature is supported by the USARTx instance. 2247:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 DEM LL_USART_IsEnabledDEMode 2248:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2249:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). 2250:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2251:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledDEMode(const USART_TypeDef *USARTx) 2252:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2253:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->CR3, USART_CR3_DEM) == (USART_CR3_DEM)) ? 1UL : 0UL); 2254:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2255:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2256:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2257:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Select Driver Enable Polarity 2258:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not 2259:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Driver Enable feature is supported by the USARTx instance. 2260:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 DEP LL_USART_SetDESignalPolarity 2261:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2262:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param Polarity This parameter can be one of the following values: 2263:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_DE_POLARITY_HIGH 2264:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_DE_POLARITY_LOW 2265:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 2266:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2267:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetDESignalPolarity(USART_TypeDef *USARTx, uint32_t Polarity) 2268:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2269:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** MODIFY_REG(USARTx->CR3, USART_CR3_DEP, Polarity); 2270:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2271:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2272:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2273:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Return Driver Enable Polarity 2274:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not 2275:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Driver Enable feature is supported by the USARTx instance. 2276:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 DEP LL_USART_GetDESignalPolarity 2277:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2278:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Returned value can be one of the following values: 2279:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_DE_POLARITY_HIGH 2280:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_DE_POLARITY_LOW 2281:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2282:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetDESignalPolarity(const USART_TypeDef *USARTx) 2283:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2284:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_DEP)); 2285:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2286:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ARM GAS /tmp/ccYgfTud.s page 410 2287:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2288:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} 2289:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2290:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2291:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EF_AdvancedConfiguration Advanced Configurations services 2292:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ 2293:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2294:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2295:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2296:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Perform basic configuration of USART for enabling use in Asynchronous Mode (UART) 2297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note In UART mode, the following bits must be kept cleared: 2298:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - LINEN bit in the USART_CR2 register, 2299:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - CLKEN bit in the USART_CR2 register, 2300:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - SCEN bit in the USART_CR3 register, 2301:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - IREN bit in the USART_CR3 register, 2302:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - HDSEL bit in the USART_CR3 register. 2303:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Call of this function is equivalent to following function call sequence : 2304:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function 2305:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function 2306:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function 2307:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function 2308:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function 2309:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Other remaining configurations items related to Asynchronous Mode 2310:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * (as Baud Rate, Word length, Parity, ...) should be set using 2311:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * dedicated functions 2312:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 LINEN LL_USART_ConfigAsyncMode\n 2313:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR2 CLKEN LL_USART_ConfigAsyncMode\n 2314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR3 SCEN LL_USART_ConfigAsyncMode\n 2315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR3 IREN LL_USART_ConfigAsyncMode\n 2316:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR3 HDSEL LL_USART_ConfigAsyncMode 2317:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2318:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 2319:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2320:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_ConfigAsyncMode(USART_TypeDef *USARTx) 2321:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2322:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* In Asynchronous mode, the following bits must be kept cleared: 2323:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** - LINEN, CLKEN bits in the USART_CR2 register, 2324:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** - SCEN, IREN and HDSEL bits in the USART_CR3 register. 2325:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2326:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); 2327:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN | USART_CR3_HDSEL)); 2328:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2329:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2330:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2331:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Perform basic configuration of USART for enabling use in Synchronous Mode 2332:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note In Synchronous mode, the following bits must be kept cleared: 2333:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - LINEN bit in the USART_CR2 register, 2334:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - SCEN bit in the USART_CR3 register, 2335:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - IREN bit in the USART_CR3 register, 2336:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - HDSEL bit in the USART_CR3 register. 2337:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * This function also sets the USART in Synchronous mode. 2338:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not 2339:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Synchronous mode is supported by the USARTx instance. 2340:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Call of this function is equivalent to following function call sequence : 2341:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function 2342:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function 2343:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function ARM GAS /tmp/ccYgfTud.s page 411 2344:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function 2345:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Set CLKEN in CR2 using @ref LL_USART_EnableSCLKOutput() function 2346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Other remaining configurations items related to Synchronous Mode 2347:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * (as Baud Rate, Word length, Parity, Clock Polarity, ...) should be set using 2348:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * dedicated functions 2349:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 LINEN LL_USART_ConfigSyncMode\n 2350:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR2 CLKEN LL_USART_ConfigSyncMode\n 2351:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR3 SCEN LL_USART_ConfigSyncMode\n 2352:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR3 IREN LL_USART_ConfigSyncMode\n 2353:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR3 HDSEL LL_USART_ConfigSyncMode 2354:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2355:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 2356:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2357:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_ConfigSyncMode(USART_TypeDef *USARTx) 2358:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2359:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* In Synchronous mode, the following bits must be kept cleared: 2360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** - LINEN bit in the USART_CR2 register, 2361:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** - SCEN, IREN and HDSEL bits in the USART_CR3 register. 2362:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2363:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN)); 2364:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN | USART_CR3_HDSEL)); 2365:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* set the UART/USART in Synchronous mode */ 2366:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** SET_BIT(USARTx->CR2, USART_CR2_CLKEN); 2367:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2368:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2369:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Perform basic configuration of USART for enabling use in LIN Mode 2371:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note In LIN mode, the following bits must be kept cleared: 2372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - STOP and CLKEN bits in the USART_CR2 register, 2373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - SCEN bit in the USART_CR3 register, 2374:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - IREN bit in the USART_CR3 register, 2375:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - HDSEL bit in the USART_CR3 register. 2376:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * This function also set the UART/USART in LIN mode. 2377:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not 2378:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * LIN feature is supported by the USARTx instance. 2379:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Call of this function is equivalent to following function call sequence : 2380:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function 2381:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Clear STOP in CR2 using @ref LL_USART_SetStopBitsLength() function 2382:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function 2383:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function 2384:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function 2385:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Set LINEN in CR2 using @ref LL_USART_EnableLIN() function 2386:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Other remaining configurations items related to LIN Mode 2387:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * (as Baud Rate, Word length, LIN Break Detection Length, ...) should be set using 2388:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * dedicated functions 2389:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 CLKEN LL_USART_ConfigLINMode\n 2390:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR2 STOP LL_USART_ConfigLINMode\n 2391:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR2 LINEN LL_USART_ConfigLINMode\n 2392:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR3 IREN LL_USART_ConfigLINMode\n 2393:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR3 SCEN LL_USART_ConfigLINMode\n 2394:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR3 HDSEL LL_USART_ConfigLINMode 2395:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2396:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 2397:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2398:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_ConfigLINMode(USART_TypeDef *USARTx) 2399:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2400:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* In LIN mode, the following bits must be kept cleared: ARM GAS /tmp/ccYgfTud.s page 412 2401:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** - STOP and CLKEN bits in the USART_CR2 register, 2402:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** - IREN, SCEN and HDSEL bits in the USART_CR3 register. 2403:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2404:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** CLEAR_BIT(USARTx->CR2, (USART_CR2_CLKEN | USART_CR2_STOP)); 2405:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** CLEAR_BIT(USARTx->CR3, (USART_CR3_IREN | USART_CR3_SCEN | USART_CR3_HDSEL)); 2406:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* Set the UART/USART in LIN mode */ 2407:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** SET_BIT(USARTx->CR2, USART_CR2_LINEN); 2408:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2409:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2410:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2411:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Perform basic configuration of USART for enabling use in Half Duplex Mode 2412:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note In Half Duplex mode, the following bits must be kept cleared: 2413:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - LINEN bit in the USART_CR2 register, 2414:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - CLKEN bit in the USART_CR2 register, 2415:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - SCEN bit in the USART_CR3 register, 2416:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - IREN bit in the USART_CR3 register, 2417:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * This function also sets the UART/USART in Half Duplex mode. 2418:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not 2419:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Half-Duplex mode is supported by the USARTx instance. 2420:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Call of this function is equivalent to following function call sequence : 2421:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function 2422:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function 2423:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function 2424:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function 2425:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Set HDSEL in CR3 using @ref LL_USART_EnableHalfDuplex() function 2426:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Other remaining configurations items related to Half Duplex Mode 2427:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * (as Baud Rate, Word length, Parity, ...) should be set using 2428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * dedicated functions 2429:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 LINEN LL_USART_ConfigHalfDuplexMode\n 2430:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR2 CLKEN LL_USART_ConfigHalfDuplexMode\n 2431:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR3 HDSEL LL_USART_ConfigHalfDuplexMode\n 2432:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR3 SCEN LL_USART_ConfigHalfDuplexMode\n 2433:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR3 IREN LL_USART_ConfigHalfDuplexMode 2434:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2435:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 2436:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2437:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_ConfigHalfDuplexMode(USART_TypeDef *USARTx) 2438:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2439:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* In Half Duplex mode, the following bits must be kept cleared: 2440:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** - LINEN and CLKEN bits in the USART_CR2 register, 2441:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** - SCEN and IREN bits in the USART_CR3 register. 2442:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2443:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); 2444:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN)); 2445:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* set the UART/USART in Half Duplex mode */ 2446:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** SET_BIT(USARTx->CR3, USART_CR3_HDSEL); 2447:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2448:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2449:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2450:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Perform basic configuration of USART for enabling use in Smartcard Mode 2451:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note In Smartcard mode, the following bits must be kept cleared: 2452:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - LINEN bit in the USART_CR2 register, 2453:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - IREN bit in the USART_CR3 register, 2454:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - HDSEL bit in the USART_CR3 register. 2455:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * This function also configures Stop bits to 1.5 bits and 2456:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * sets the USART in Smartcard mode (SCEN bit). 2457:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Clock Output is also enabled (CLKEN). ARM GAS /tmp/ccYgfTud.s page 413 2458:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not 2459:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Smartcard feature is supported by the USARTx instance. 2460:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Call of this function is equivalent to following function call sequence : 2461:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function 2462:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function 2463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function 2464:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Configure STOP in CR2 using @ref LL_USART_SetStopBitsLength() function 2465:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Set CLKEN in CR2 using @ref LL_USART_EnableSCLKOutput() function 2466:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Set SCEN in CR3 using @ref LL_USART_EnableSmartcard() function 2467:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Other remaining configurations items related to Smartcard Mode 2468:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * (as Baud Rate, Word length, Parity, ...) should be set using 2469:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * dedicated functions 2470:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 LINEN LL_USART_ConfigSmartcardMode\n 2471:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR2 STOP LL_USART_ConfigSmartcardMode\n 2472:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR2 CLKEN LL_USART_ConfigSmartcardMode\n 2473:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR3 HDSEL LL_USART_ConfigSmartcardMode\n 2474:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR3 SCEN LL_USART_ConfigSmartcardMode 2475:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2476:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 2477:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2478:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_ConfigSmartcardMode(USART_TypeDef *USARTx) 2479:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2480:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* In Smartcard mode, the following bits must be kept cleared: 2481:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** - LINEN bit in the USART_CR2 register, 2482:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** - IREN and HDSEL bits in the USART_CR3 register. 2483:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2484:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN)); 2485:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** CLEAR_BIT(USARTx->CR3, (USART_CR3_IREN | USART_CR3_HDSEL)); 2486:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* Configure Stop bits to 1.5 bits */ 2487:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* Synchronous mode is activated by default */ 2488:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** SET_BIT(USARTx->CR2, (USART_CR2_STOP_0 | USART_CR2_STOP_1 | USART_CR2_CLKEN)); 2489:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* set the UART/USART in Smartcard mode */ 2490:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** SET_BIT(USARTx->CR3, USART_CR3_SCEN); 2491:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2492:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2493:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2494:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Perform basic configuration of USART for enabling use in Irda Mode 2495:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note In IRDA mode, the following bits must be kept cleared: 2496:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - LINEN bit in the USART_CR2 register, 2497:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - STOP and CLKEN bits in the USART_CR2 register, 2498:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - SCEN bit in the USART_CR3 register, 2499:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - HDSEL bit in the USART_CR3 register. 2500:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * This function also sets the UART/USART in IRDA mode (IREN bit). 2501:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not 2502:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * IrDA feature is supported by the USARTx instance. 2503:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Call of this function is equivalent to following function call sequence : 2504:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function 2505:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function 2506:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function 2507:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function 2508:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Configure STOP in CR2 using @ref LL_USART_SetStopBitsLength() function 2509:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Set IREN in CR3 using @ref LL_USART_EnableIrda() function 2510:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Other remaining configurations items related to Irda Mode 2511:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * (as Baud Rate, Word length, Power mode, ...) should be set using 2512:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * dedicated functions 2513:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 LINEN LL_USART_ConfigIrdaMode\n 2514:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR2 CLKEN LL_USART_ConfigIrdaMode\n ARM GAS /tmp/ccYgfTud.s page 414 2515:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR2 STOP LL_USART_ConfigIrdaMode\n 2516:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR3 SCEN LL_USART_ConfigIrdaMode\n 2517:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR3 HDSEL LL_USART_ConfigIrdaMode\n 2518:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR3 IREN LL_USART_ConfigIrdaMode 2519:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2520:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 2521:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2522:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_ConfigIrdaMode(USART_TypeDef *USARTx) 2523:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2524:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* In IRDA mode, the following bits must be kept cleared: 2525:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** - LINEN, STOP and CLKEN bits in the USART_CR2 register, 2526:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** - SCEN and HDSEL bits in the USART_CR3 register. 2527:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2528:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN | USART_CR2_STOP)); 2529:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL)); 2530:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* set the UART/USART in IRDA mode */ 2531:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** SET_BIT(USARTx->CR3, USART_CR3_IREN); 2532:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2533:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2534:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2535:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Perform basic configuration of USART for enabling use in Multi processor Mode 2536:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * (several USARTs connected in a network, one of the USARTs can be the master, 2537:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * its TX output connected to the RX inputs of the other slaves USARTs). 2538:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note In MultiProcessor mode, the following bits must be kept cleared: 2539:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - LINEN bit in the USART_CR2 register, 2540:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - CLKEN bit in the USART_CR2 register, 2541:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - SCEN bit in the USART_CR3 register, 2542:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - IREN bit in the USART_CR3 register, 2543:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - HDSEL bit in the USART_CR3 register. 2544:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Call of this function is equivalent to following function call sequence : 2545:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function 2546:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function 2547:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function 2548:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function 2549:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function 2550:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Other remaining configurations items related to Multi processor Mode 2551:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * (as Baud Rate, Wake Up Method, Node address, ...) should be set using 2552:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * dedicated functions 2553:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 LINEN LL_USART_ConfigMultiProcessMode\n 2554:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR2 CLKEN LL_USART_ConfigMultiProcessMode\n 2555:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR3 SCEN LL_USART_ConfigMultiProcessMode\n 2556:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR3 HDSEL LL_USART_ConfigMultiProcessMode\n 2557:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR3 IREN LL_USART_ConfigMultiProcessMode 2558:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2559:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 2560:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2561:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_ConfigMultiProcessMode(USART_TypeDef *USARTx) 2562:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2563:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* In Multi Processor mode, the following bits must be kept cleared: 2564:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** - LINEN and CLKEN bits in the USART_CR2 register, 2565:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** - IREN, SCEN and HDSEL bits in the USART_CR3 register. 2566:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2567:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); 2568:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN)); 2569:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2570:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2571:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** ARM GAS /tmp/ccYgfTud.s page 415 2572:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} 2573:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2574:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2575:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EF_FLAG_Management FLAG_Management 2576:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ 2577:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2578:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2579:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2580:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if the USART Parity Error Flag is set or not 2581:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll ISR PE LL_USART_IsActiveFlag_PE 2582:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2583:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). 2584:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2585:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_PE(const USART_TypeDef *USARTx) 2586:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2587:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->ISR, USART_ISR_PE) == (USART_ISR_PE)) ? 1UL : 0UL); 2588:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2589:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2590:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2591:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if the USART Framing Error Flag is set or not 2592:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll ISR FE LL_USART_IsActiveFlag_FE 2593:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2594:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). 2595:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2596:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_FE(const USART_TypeDef *USARTx) 2597:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2598:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->ISR, USART_ISR_FE) == (USART_ISR_FE)) ? 1UL : 0UL); 2599:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2600:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2601:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2602:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if the USART Noise error detected Flag is set or not 2603:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll ISR NE LL_USART_IsActiveFlag_NE 2604:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2605:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). 2606:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2607:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_NE(const USART_TypeDef *USARTx) 2608:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2609:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->ISR, USART_ISR_NE) == (USART_ISR_NE)) ? 1UL : 0UL); 2610:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2611:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2612:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2613:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if the USART OverRun Error Flag is set or not 2614:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll ISR ORE LL_USART_IsActiveFlag_ORE 2615:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2616:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). 2617:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2618:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ORE(const USART_TypeDef *USARTx) 2619:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2620:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->ISR, USART_ISR_ORE) == (USART_ISR_ORE)) ? 1UL : 0UL); 2621:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2622:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2623:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2624:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if the USART IDLE line detected Flag is set or not 2625:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll ISR IDLE LL_USART_IsActiveFlag_IDLE 2626:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2627:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). 2628:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ ARM GAS /tmp/ccYgfTud.s page 416 2629:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_IDLE(const USART_TypeDef *USARTx) 2630:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2631:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->ISR, USART_ISR_IDLE) == (USART_ISR_IDLE)) ? 1UL : 0UL); 2632:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2633:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2634:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2635:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if the USART Read Data Register Not Empty Flag is set or not 2636:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll ISR RXNE LL_USART_IsActiveFlag_RXNE 2637:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2638:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). 2639:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2640:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXNE(const USART_TypeDef *USARTx) 2641:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2642:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->ISR, USART_ISR_RXNE) == (USART_ISR_RXNE)) ? 1UL : 0UL); 2643:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2644:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2645:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2646:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if the USART Transmission Complete Flag is set or not 2647:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll ISR TC LL_USART_IsActiveFlag_TC 2648:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2649:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). 2650:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2651:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TC(const USART_TypeDef *USARTx) 2652:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2653:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->ISR, USART_ISR_TC) == (USART_ISR_TC)) ? 1UL : 0UL); 2654:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2655:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2656:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2657:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if the USART Transmit Data Register Empty Flag is set or not 2658:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll ISR TXE LL_USART_IsActiveFlag_TXE 2659:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2660:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). 2661:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2662:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXE(const USART_TypeDef *USARTx) 2663:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2664:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->ISR, USART_ISR_TXE) == (USART_ISR_TXE)) ? 1UL : 0UL); 2665:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2666:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2667:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2668:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if the USART LIN Break Detection Flag is set or not 2669:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not 2670:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * LIN feature is supported by the USARTx instance. 2671:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll ISR LBDF LL_USART_IsActiveFlag_LBD 2672:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2673:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). 2674:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2675:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_LBD(const USART_TypeDef *USARTx) 2676:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2677:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->ISR, USART_ISR_LBDF) == (USART_ISR_LBDF)) ? 1UL : 0UL); 2678:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2679:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2680:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2681:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if the USART CTS interrupt Flag is set or not 2682:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not 2683:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Hardware Flow control feature is supported by the USARTx instance. 2684:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll ISR CTSIF LL_USART_IsActiveFlag_nCTS 2685:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance ARM GAS /tmp/ccYgfTud.s page 417 2686:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). 2687:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2688:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_nCTS(const USART_TypeDef *USARTx) 2689:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2690:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->ISR, USART_ISR_CTSIF) == (USART_ISR_CTSIF)) ? 1UL : 0UL); 2691:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2692:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2693:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2694:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if the USART CTS Flag is set or not 2695:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not 2696:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Hardware Flow control feature is supported by the USARTx instance. 2697:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll ISR CTS LL_USART_IsActiveFlag_CTS 2698:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2699:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). 2700:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2701:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_CTS(const USART_TypeDef *USARTx) 2702:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2703:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->ISR, USART_ISR_CTS) == (USART_ISR_CTS)) ? 1UL : 0UL); 2704:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2705:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2706:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2707:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if the USART Receiver Time Out Flag is set or not 2708:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll ISR RTOF LL_USART_IsActiveFlag_RTO 2709:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2710:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). 2711:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2712:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RTO(const USART_TypeDef *USARTx) 2713:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2714:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->ISR, USART_ISR_RTOF) == (USART_ISR_RTOF)) ? 1UL : 0UL); 2715:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2716:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2717:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2718:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if the USART End Of Block Flag is set or not 2719:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not 2720:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Smartcard feature is supported by the USARTx instance. 2721:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll ISR EOBF LL_USART_IsActiveFlag_EOB 2722:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2723:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). 2724:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2725:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_EOB(const USART_TypeDef *USARTx) 2726:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2727:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->ISR, USART_ISR_EOBF) == (USART_ISR_EOBF)) ? 1UL : 0UL); 2728:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2729:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2730:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2731:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if the USART Auto-Baud Rate Error Flag is set or not 2732:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or 2733:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Auto Baud Rate detection feature is supported by the USARTx instance. 2734:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll ISR ABRE LL_USART_IsActiveFlag_ABRE 2735:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2736:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). 2737:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2738:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ABRE(const USART_TypeDef *USARTx) 2739:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2740:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->ISR, USART_ISR_ABRE) == (USART_ISR_ABRE)) ? 1UL : 0UL); 2741:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2742:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ARM GAS /tmp/ccYgfTud.s page 418 2743:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2744:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if the USART Auto-Baud Rate Flag is set or not 2745:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or 2746:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Auto Baud Rate detection feature is supported by the USARTx instance. 2747:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll ISR ABRF LL_USART_IsActiveFlag_ABR 2748:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2749:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). 2750:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2751:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ABR(const USART_TypeDef *USARTx) 2752:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2753:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->ISR, USART_ISR_ABRF) == (USART_ISR_ABRF)) ? 1UL : 0UL); 2754:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2755:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2756:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2757:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if the USART Busy Flag is set or not 2758:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll ISR BUSY LL_USART_IsActiveFlag_BUSY 2759:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2760:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). 2761:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2762:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_BUSY(const USART_TypeDef *USARTx) 2763:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2764:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->ISR, USART_ISR_BUSY) == (USART_ISR_BUSY)) ? 1UL : 0UL); 2765:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2766:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2767:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2768:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if the USART Character Match Flag is set or not 2769:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll ISR CMF LL_USART_IsActiveFlag_CM 2770:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2771:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). 2772:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2773:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_CM(const USART_TypeDef *USARTx) 2774:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2775:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->ISR, USART_ISR_CMF) == (USART_ISR_CMF)) ? 1UL : 0UL); 2776:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2777:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2778:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2779:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if the USART Send Break Flag is set or not 2780:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll ISR SBKF LL_USART_IsActiveFlag_SBK 2781:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2782:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). 2783:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2784:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_SBK(const USART_TypeDef *USARTx) 2785:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2786:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->ISR, USART_ISR_SBKF) == (USART_ISR_SBKF)) ? 1UL : 0UL); 2787:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2788:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2789:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2790:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if the USART Receive Wake Up from mute mode Flag is set or not 2791:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll ISR RWU LL_USART_IsActiveFlag_RWU 2792:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2793:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). 2794:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2795:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RWU(const USART_TypeDef *USARTx) 2796:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2797:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->ISR, USART_ISR_RWU) == (USART_ISR_RWU)) ? 1UL : 0UL); 2798:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2799:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ARM GAS /tmp/ccYgfTud.s page 419 2800:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_CR1_UESM) 2801:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_CR3_WUFIE) 2802:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2803:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if the USART Wake Up from stop mode Flag is set or not 2804:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not 2805:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Wake-up from Stop mode feature is supported by the USARTx instance. 2806:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll ISR WUF LL_USART_IsActiveFlag_WKUP 2807:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2808:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). 2809:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2810:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_WKUP(const USART_TypeDef *USARTx) 2811:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2812:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->ISR, USART_ISR_WUF) == (USART_ISR_WUF)) ? 1UL : 0UL); 2813:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2814:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2815:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_CR3_WUFIE */ 2816:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_CR1_UESM */ 2817:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2818:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if the USART Transmit Enable Acknowledge Flag is set or not 2819:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll ISR TEACK LL_USART_IsActiveFlag_TEACK 2820:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2821:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). 2822:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2823:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TEACK(const USART_TypeDef *USARTx) 2824:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2825:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->ISR, USART_ISR_TEACK) == (USART_ISR_TEACK)) ? 1UL : 0UL); 2826:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2827:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2828:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_ISR_REACK) 2829:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2830:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if the USART Receive Enable Acknowledge Flag is set or not 2831:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll ISR REACK LL_USART_IsActiveFlag_REACK 2832:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2833:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). 2834:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2835:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_REACK(const USART_TypeDef *USARTx) 2836:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2837:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->ISR, USART_ISR_REACK) == (USART_ISR_REACK)) ? 1UL : 0UL); 2838:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2839:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2840:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_ISR_REACK */ 2841:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_TCBGT_SUPPORT) 2842:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* Function available only on devices supporting Transmit Complete before Guard Time feature */ 2843:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2844:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if the Smartcard Transmission Complete Before Guard Time Flag is set or not 2845:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll ISR TCBGT LL_USART_IsActiveFlag_TCBGT 2846:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2847:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). 2848:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2849:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TCBGT(const USART_TypeDef *USARTx) 2850:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2851:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->ISR, USART_ISR_TCBGT) == (USART_ISR_TCBGT)) ? 1UL : 0UL); 2852:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2853:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2854:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_TCBGT_SUPPORT */ 2855:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2856:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Clear Parity Error Flag ARM GAS /tmp/ccYgfTud.s page 420 2857:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll ICR PECF LL_USART_ClearFlag_PE 2858:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2859:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 2860:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2861:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_ClearFlag_PE(USART_TypeDef *USARTx) 2862:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2863:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** WRITE_REG(USARTx->ICR, USART_ICR_PECF); 2864:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2865:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2866:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2867:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Clear Framing Error Flag 2868:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll ICR FECF LL_USART_ClearFlag_FE 2869:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2870:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 2871:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2872:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_ClearFlag_FE(USART_TypeDef *USARTx) 2873:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2874:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** WRITE_REG(USARTx->ICR, USART_ICR_FECF); 2875:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2876:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2877:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2878:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Clear Noise Error detected Flag 2879:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll ICR NCF LL_USART_ClearFlag_NE 2880:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2881:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 2882:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2883:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_ClearFlag_NE(USART_TypeDef *USARTx) 2884:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2885:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** WRITE_REG(USARTx->ICR, USART_ICR_NCF); 2886:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2887:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2888:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2889:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Clear OverRun Error Flag 2890:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll ICR ORECF LL_USART_ClearFlag_ORE 2891:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2892:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 2893:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2894:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_ClearFlag_ORE(USART_TypeDef *USARTx) 2895:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2896:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** WRITE_REG(USARTx->ICR, USART_ICR_ORECF); 2897:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2898:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2899:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2900:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Clear IDLE line detected Flag 2901:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll ICR IDLECF LL_USART_ClearFlag_IDLE 2902:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2903:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 2904:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2905:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_ClearFlag_IDLE(USART_TypeDef *USARTx) 2906:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** WRITE_REG(USARTx->ICR, USART_ICR_IDLECF); 2908:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2909:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2910:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2911:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Clear Transmission Complete Flag 2912:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll ICR TCCF LL_USART_ClearFlag_TC 2913:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance ARM GAS /tmp/ccYgfTud.s page 421 2914:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 2915:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2916:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_ClearFlag_TC(USART_TypeDef *USARTx) 2917:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** WRITE_REG(USARTx->ICR, USART_ICR_TCCF); 2919:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2920:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2921:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_TCBGT_SUPPORT) 2922:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* Function available only on devices supporting Transmit Complete before Guard Time feature */ 2923:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2924:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Clear Smartcard Transmission Complete Before Guard Time Flag 2925:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll ICR TCBGTCF LL_USART_ClearFlag_TCBGT 2926:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2927:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 2928:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2929:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_ClearFlag_TCBGT(USART_TypeDef *USARTx) 2930:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2931:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** WRITE_REG(USARTx->ICR, USART_ICR_TCBGTCF); 2932:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2933:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_TCBGT_SUPPORT */ 2934:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2935:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2936:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Clear LIN Break Detection Flag 2937:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not 2938:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * LIN feature is supported by the USARTx instance. 2939:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll ICR LBDCF LL_USART_ClearFlag_LBD 2940:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2941:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 2942:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2943:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_ClearFlag_LBD(USART_TypeDef *USARTx) 2944:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2945:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** WRITE_REG(USARTx->ICR, USART_ICR_LBDCF); 2946:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2947:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2948:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2949:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Clear CTS Interrupt Flag 2950:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not 2951:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Hardware Flow control feature is supported by the USARTx instance. 2952:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll ICR CTSCF LL_USART_ClearFlag_nCTS 2953:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2954:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 2955:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2956:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_ClearFlag_nCTS(USART_TypeDef *USARTx) 2957:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2958:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** WRITE_REG(USARTx->ICR, USART_ICR_CTSCF); 2959:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2960:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2961:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2962:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Clear Receiver Time Out Flag 2963:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll ICR RTOCF LL_USART_ClearFlag_RTO 2964:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2965:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 2966:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2967:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_ClearFlag_RTO(USART_TypeDef *USARTx) 2968:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2969:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** WRITE_REG(USARTx->ICR, USART_ICR_RTOCF); 2970:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } ARM GAS /tmp/ccYgfTud.s page 422 2971:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2972:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2973:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Clear End Of Block Flag 2974:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not 2975:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Smartcard feature is supported by the USARTx instance. 2976:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll ICR EOBCF LL_USART_ClearFlag_EOB 2977:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2978:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 2979:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2980:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_ClearFlag_EOB(USART_TypeDef *USARTx) 2981:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2982:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** WRITE_REG(USARTx->ICR, USART_ICR_EOBCF); 2983:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2984:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2985:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2986:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Clear Character Match Flag 2987:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll ICR CMCF LL_USART_ClearFlag_CM 2988:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2989:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 2990:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2991:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_ClearFlag_CM(USART_TypeDef *USARTx) 2992:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2993:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** WRITE_REG(USARTx->ICR, USART_ICR_CMCF); 2994:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2995:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2996:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_CR1_UESM) 2997:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_CR3_WUFIE) 2998:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2999:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Clear Wake Up from stop mode Flag 3000:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not 3001:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Wake-up from Stop mode feature is supported by the USARTx instance. 3002:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll ICR WUCF LL_USART_ClearFlag_WKUP 3003:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 3004:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 3005:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3006:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_ClearFlag_WKUP(USART_TypeDef *USARTx) 3007:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 3008:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** WRITE_REG(USARTx->ICR, USART_ICR_WUCF); 3009:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 3010:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3011:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_CR3_WUFIE */ 3012:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_CR1_UESM */ 3013:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 3014:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} 3015:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3016:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3017:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EF_IT_Management IT_Management 3018:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ 3019:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3020:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3021:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 3022:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Enable IDLE Interrupt 3023:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 IDLEIE LL_USART_EnableIT_IDLE 3024:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 3025:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 3026:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3027:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableIT_IDLE(USART_TypeDef *USARTx) ARM GAS /tmp/ccYgfTud.s page 423 3028:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 3029:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_IDLEIE); 3030:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 3031:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3032:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 3033:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Enable RX Not Empty Interrupt 3034:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 RXNEIE LL_USART_EnableIT_RXNE 3035:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 3036:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 3037:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3038:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableIT_RXNE(USART_TypeDef *USARTx) 3039:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 3040:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_RXNEIE); 3041:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 3042:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3043:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 3044:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Enable Transmission Complete Interrupt 3045:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 TCIE LL_USART_EnableIT_TC 3046:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 3047:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 3048:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3049:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableIT_TC(USART_TypeDef *USARTx) 3050:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 3051:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_TCIE); 3052:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 3053:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3054:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 3055:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Enable TX Empty Interrupt 3056:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 TXEIE LL_USART_EnableIT_TXE 3057:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 3058:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 3059:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3060:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableIT_TXE(USART_TypeDef *USARTx) 3061:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 3062:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_TXEIE); 3063:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 3064:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3065:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 3066:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Enable Parity Error Interrupt 3067:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 PEIE LL_USART_EnableIT_PE 3068:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 3069:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 3070:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3071:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableIT_PE(USART_TypeDef *USARTx) 3072:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 3073:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_PEIE); 3074:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 3075:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3076:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 3077:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Enable Character Match Interrupt 3078:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 CMIE LL_USART_EnableIT_CM 3079:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 3080:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 3081:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3082:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableIT_CM(USART_TypeDef *USARTx) 3083:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 3084:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_CMIE); ARM GAS /tmp/ccYgfTud.s page 424 3085:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 3086:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3087:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 3088:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Enable Receiver Timeout Interrupt 3089:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 RTOIE LL_USART_EnableIT_RTO 3090:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 3091:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 3092:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3093:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableIT_RTO(USART_TypeDef *USARTx) 3094:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 3095:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_RTOIE); 3096:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 3097:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3098:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 3099:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Enable End Of Block Interrupt 3100:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not 3101:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Smartcard feature is supported by the USARTx instance. 3102:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 EOBIE LL_USART_EnableIT_EOB 3103:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 3104:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 3105:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3106:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableIT_EOB(USART_TypeDef *USARTx) 3107:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 3108:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_EOBIE); 3109:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 3110:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3111:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 3112:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Enable LIN Break Detection Interrupt 3113:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not 3114:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * LIN feature is supported by the USARTx instance. 3115:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 LBDIE LL_USART_EnableIT_LBD 3116:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 3117:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 3118:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3119:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableIT_LBD(USART_TypeDef *USARTx) 3120:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 3121:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** SET_BIT(USARTx->CR2, USART_CR2_LBDIE); 3122:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 3123:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3124:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 3125:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Enable Error Interrupt 3126:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a fram 3127:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the USARTx_ISR register). 3128:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * 0: Interrupt is inhibited 3129:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * 1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the USARTx_ISR register. 3130:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 EIE LL_USART_EnableIT_ERROR 3131:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 3132:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 3133:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3134:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableIT_ERROR(USART_TypeDef *USARTx) 3135:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 3136:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_EIE); 3137:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 3138:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3139:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 3140:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Enable CTS Interrupt 3141:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not ARM GAS /tmp/ccYgfTud.s page 425 3142:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Hardware Flow control feature is supported by the USARTx instance. 3143:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 CTSIE LL_USART_EnableIT_CTS 3144:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 3145:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 3146:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3147:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableIT_CTS(USART_TypeDef *USARTx) 3148:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 3149:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_CTSIE); 3150:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 3151:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3152:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_CR1_UESM) 3153:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_CR3_WUFIE) 3154:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 3155:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Enable Wake Up from Stop Mode Interrupt 3156:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not 3157:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Wake-up from Stop mode feature is supported by the USARTx instance. 3158:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 WUFIE LL_USART_EnableIT_WKUP 3159:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 3160:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 3161:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3162:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableIT_WKUP(USART_TypeDef *USARTx) 3163:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 3164:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_WUFIE); 3165:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 3166:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3167:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_CR3_WUFIE */ 3168:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_CR1_UESM */ 3169:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_TCBGT_SUPPORT) 3170:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* Function available only on devices supporting Transmit Complete before Guard Time feature */ 3171:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 3172:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Enable Smartcard Transmission Complete Before Guard Time Interrupt 3173:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not 3174:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Smartcard feature is supported by the USARTx instance. 3175:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 TCBGTIE LL_USART_EnableIT_TCBGT 3176:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 3177:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 3178:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3179:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableIT_TCBGT(USART_TypeDef *USARTx) 3180:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 3181:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_TCBGTIE); 3182:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 3183:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_TCBGT_SUPPORT */ 3184:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3185:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 3186:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Disable IDLE Interrupt 3187:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 IDLEIE LL_USART_DisableIT_IDLE 3188:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 3189:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 3190:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3191:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableIT_IDLE(USART_TypeDef *USARTx) 3192:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 3193:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_IDLEIE); 3194:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 3195:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3196:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 3197:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Disable RX Not Empty Interrupt 3198:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 RXNEIE LL_USART_DisableIT_RXNE ARM GAS /tmp/ccYgfTud.s page 426 3199:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 3200:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 3201:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3202:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableIT_RXNE(USART_TypeDef *USARTx) 3203:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 3204:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_RXNEIE); 3205:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 3206:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3207:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 3208:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Disable Transmission Complete Interrupt 3209:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 TCIE LL_USART_DisableIT_TC 3210:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 3211:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 3212:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3213:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableIT_TC(USART_TypeDef *USARTx) 3214:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 3215:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_TCIE); 3216:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 3217:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3218:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 3219:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Disable TX Empty Interrupt 3220:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 TXEIE LL_USART_DisableIT_TXE 3221:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 3222:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 3223:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3224:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableIT_TXE(USART_TypeDef *USARTx) 3225:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 3226:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_TXEIE); 3227:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 3228:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3229:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 3230:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Disable Parity Error Interrupt 3231:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 PEIE LL_USART_DisableIT_PE 3232:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 3233:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 3234:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3235:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableIT_PE(USART_TypeDef *USARTx) 3236:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 3237:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_PEIE); 3238:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 3239:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3240:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 3241:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Disable Character Match Interrupt 3242:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 CMIE LL_USART_DisableIT_CM 3243:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 3244:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 3245:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3246:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableIT_CM(USART_TypeDef *USARTx) 3247:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 3248:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_CMIE); 3249:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 3250:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3251:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 3252:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Disable Receiver Timeout Interrupt 3253:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 RTOIE LL_USART_DisableIT_RTO 3254:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 3255:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None ARM GAS /tmp/ccYgfTud.s page 427 3256:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3257:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableIT_RTO(USART_TypeDef *USARTx) 3258:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 3259:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_RTOIE); 3260:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 3261:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3262:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 3263:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Disable End Of Block Interrupt 3264:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not 3265:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Smartcard feature is supported by the USARTx instance. 3266:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 EOBIE LL_USART_DisableIT_EOB 3267:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 3268:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 3269:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3270:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableIT_EOB(USART_TypeDef *USARTx) 3271:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 3272:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_EOBIE); 3273:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 3274:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3275:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 3276:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Disable LIN Break Detection Interrupt 3277:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not 3278:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * LIN feature is supported by the USARTx instance. 3279:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 LBDIE LL_USART_DisableIT_LBD 3280:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 3281:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 3282:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3283:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableIT_LBD(USART_TypeDef *USARTx) 3284:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 3285:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** CLEAR_BIT(USARTx->CR2, USART_CR2_LBDIE); 3286:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 3287:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3288:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 3289:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Disable Error Interrupt 3290:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a fram 3291:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the USARTx_ISR register). 3292:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * 0: Interrupt is inhibited 3293:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * 1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the USARTx_ISR register. 3294:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 EIE LL_USART_DisableIT_ERROR 3295:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 3296:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 3297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3298:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableIT_ERROR(USART_TypeDef *USARTx) 3299:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 3300:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_EIE); 3301:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 3302:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3303:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 3304:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Disable CTS Interrupt 3305:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not 3306:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Hardware Flow control feature is supported by the USARTx instance. 3307:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 CTSIE LL_USART_DisableIT_CTS 3308:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 3309:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 3310:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3311:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableIT_CTS(USART_TypeDef *USARTx) 3312:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { ARM GAS /tmp/ccYgfTud.s page 428 3313:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_CTSIE); 3314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 3315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3316:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_CR1_UESM) 3317:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_CR3_WUFIE) 3318:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 3319:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Disable Wake Up from Stop Mode Interrupt 3320:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not 3321:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Wake-up from Stop mode feature is supported by the USARTx instance. 3322:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 WUFIE LL_USART_DisableIT_WKUP 3323:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 3324:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 3325:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3326:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableIT_WKUP(USART_TypeDef *USARTx) 3327:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 3328:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_WUFIE); 3329:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 3330:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3331:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_CR3_WUFIE */ 3332:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_CR1_UESM */ 3333:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_TCBGT_SUPPORT) 3334:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* Function available only on devices supporting Transmit Complete before Guard Time feature */ 3335:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 3336:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Disable Smartcard Transmission Complete Before Guard Time Interrupt 3337:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not 3338:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Smartcard feature is supported by the USARTx instance. 3339:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 TCBGTIE LL_USART_DisableIT_TCBGT 3340:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 3341:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 3342:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3343:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableIT_TCBGT(USART_TypeDef *USARTx) 3344:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 3345:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_TCBGTIE); 3346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 3347:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_TCBGT_SUPPORT */ 3348:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3349:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 3350:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if the USART IDLE Interrupt source is enabled or disabled. 3351:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 IDLEIE LL_USART_IsEnabledIT_IDLE 3352:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 3353:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). 3354:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3355:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_IDLE(const USART_TypeDef *USARTx) 3356:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 3357:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->CR1, USART_CR1_IDLEIE) == (USART_CR1_IDLEIE)) ? 1UL : 0UL); 3358:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 3359:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 3361:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if the USART RX Not Empty Interrupt is enabled or disabled. 3362:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 RXNEIE LL_USART_IsEnabledIT_RXNE 3363:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 3364:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). 3365:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3366:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXNE(const USART_TypeDef *USARTx) 3367:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 3368:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->CR1, USART_CR1_RXNEIE) == (USART_CR1_RXNEIE)) ? 1U : 0U); 3369:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } ARM GAS /tmp/ccYgfTud.s page 429 3370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3371:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 3372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if the USART Transmission Complete Interrupt is enabled or disabled. 3373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 TCIE LL_USART_IsEnabledIT_TC 3374:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 3375:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). 3376:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3377:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TC(const USART_TypeDef *USARTx) 3378:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 3379:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->CR1, USART_CR1_TCIE) == (USART_CR1_TCIE)) ? 1UL : 0UL); 3380:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 3381:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3382:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 3383:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if the USART TX Empty Interrupt is enabled or disabled. 3384:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 TXEIE LL_USART_IsEnabledIT_TXE 3385:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 3386:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). 3387:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3388:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXE(const USART_TypeDef *USARTx) 3389:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 3390:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->CR1, USART_CR1_TXEIE) == (USART_CR1_TXEIE)) ? 1U : 0U); 3391:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 3392:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3393:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 3394:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if the USART Parity Error Interrupt is enabled or disabled. 3395:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 PEIE LL_USART_IsEnabledIT_PE 3396:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 3397:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). 3398:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3399:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_PE(const USART_TypeDef *USARTx) 3400:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 3401:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->CR1, USART_CR1_PEIE) == (USART_CR1_PEIE)) ? 1UL : 0UL); 3402:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 3403:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3404:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 3405:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if the USART Character Match Interrupt is enabled or disabled. 3406:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 CMIE LL_USART_IsEnabledIT_CM 3407:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 3408:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). 3409:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3410:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_CM(const USART_TypeDef *USARTx) 3411:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 3412:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->CR1, USART_CR1_CMIE) == (USART_CR1_CMIE)) ? 1UL : 0UL); 3413:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 3414:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3415:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 3416:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if the USART Receiver Timeout Interrupt is enabled or disabled. 3417:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 RTOIE LL_USART_IsEnabledIT_RTO 3418:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 3419:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). 3420:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3421:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RTO(const USART_TypeDef *USARTx) 3422:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 3423:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->CR1, USART_CR1_RTOIE) == (USART_CR1_RTOIE)) ? 1UL : 0UL); 3424:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 3425:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3426:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** ARM GAS /tmp/ccYgfTud.s page 430 3427:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if the USART End Of Block Interrupt is enabled or disabled. 3428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not 3429:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Smartcard feature is supported by the USARTx instance. 3430:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 EOBIE LL_USART_IsEnabledIT_EOB 3431:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 3432:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). 3433:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3434:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_EOB(const USART_TypeDef *USARTx) 3435:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 3436:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->CR1, USART_CR1_EOBIE) == (USART_CR1_EOBIE)) ? 1UL : 0UL); 3437:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 3438:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3439:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 3440:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if the USART LIN Break Detection Interrupt is enabled or disabled. 3441:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not 3442:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * LIN feature is supported by the USARTx instance. 3443:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 LBDIE LL_USART_IsEnabledIT_LBD 3444:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 3445:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). 3446:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3447:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_LBD(const USART_TypeDef *USARTx) 3448:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 3449:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->CR2, USART_CR2_LBDIE) == (USART_CR2_LBDIE)) ? 1UL : 0UL); 3450:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 3451:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3452:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 3453:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if the USART Error Interrupt is enabled or disabled. 3454:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 EIE LL_USART_IsEnabledIT_ERROR 3455:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 3456:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). 3457:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3458:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_ERROR(const USART_TypeDef *USARTx) 3459:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 3460:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->CR3, USART_CR3_EIE) == (USART_CR3_EIE)) ? 1UL : 0UL); 3461:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 3462:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 3464:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if the USART CTS Interrupt is enabled or disabled. 3465:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not 3466:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Hardware Flow control feature is supported by the USARTx instance. 3467:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 CTSIE LL_USART_IsEnabledIT_CTS 3468:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 3469:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). 3470:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3471:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_CTS(const USART_TypeDef *USARTx) 3472:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 3473:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->CR3, USART_CR3_CTSIE) == (USART_CR3_CTSIE)) ? 1UL : 0UL); 3474:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 3475:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3476:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_CR1_UESM) 3477:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_CR3_WUFIE) 3478:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 3479:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if the USART Wake Up from Stop Mode Interrupt is enabled or disabled. 3480:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not 3481:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Wake-up from Stop mode feature is supported by the USARTx instance. 3482:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 WUFIE LL_USART_IsEnabledIT_WKUP 3483:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance ARM GAS /tmp/ccYgfTud.s page 431 3484:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). 3485:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3486:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_WKUP(const USART_TypeDef *USARTx) 3487:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 3488:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->CR3, USART_CR3_WUFIE) == (USART_CR3_WUFIE)) ? 1UL : 0UL); 3489:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 3490:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3491:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_CR3_WUFIE */ 3492:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_CR1_UESM */ 3493:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_TCBGT_SUPPORT) 3494:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* Function available only on devices supporting Transmit Complete before Guard Time feature */ 3495:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 3496:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if the Smartcard Transmission Complete Before Guard Time Interrupt is enabled or 3497:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not 3498:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Smartcard feature is supported by the USARTx instance. 3499:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 TCBGTIE LL_USART_IsEnabledIT_TCBGT 3500:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 3501:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). 3502:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3503:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TCBGT(const USART_TypeDef *USARTx) 3504:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 3505:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->CR3, USART_CR3_TCBGTIE) == (USART_CR3_TCBGTIE)) ? 1UL : 0UL); 3506:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 3507:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_TCBGT_SUPPORT */ 3508:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3509:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 3510:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} 3511:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3512:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3513:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EF_DMA_Management DMA_Management 3514:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ 3515:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3516:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3517:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 3518:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Enable DMA Mode for reception 3519:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 DMAR LL_USART_EnableDMAReq_RX 3520:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 3521:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 3522:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3523:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableDMAReq_RX(USART_TypeDef *USARTx) 3524:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 3525:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_DMAR); 3526:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 3527:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3528:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 3529:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Disable DMA Mode for reception 3530:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 DMAR LL_USART_DisableDMAReq_RX 3531:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 3532:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 3533:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3534:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableDMAReq_RX(USART_TypeDef *USARTx) 3535:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 3536:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_DMAR); 3537:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 3538:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3539:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 3540:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if DMA Mode is enabled for reception ARM GAS /tmp/ccYgfTud.s page 432 3541:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 DMAR LL_USART_IsEnabledDMAReq_RX 3542:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 3543:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). 3544:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3545:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_RX(const USART_TypeDef *USARTx) 3546:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 3547:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->CR3, USART_CR3_DMAR) == (USART_CR3_DMAR)) ? 1UL : 0UL); 3548:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 3549:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3550:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 3551:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Enable DMA Mode for transmission 3552:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 DMAT LL_USART_EnableDMAReq_TX 3553:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 3554:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 3555:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3556:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableDMAReq_TX(USART_TypeDef *USARTx) 5128 .loc 7 3556 22 view .LVU1656 5129 .L216: 3557:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 3558:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_DMAT); 5130 .loc 7 3558 3 discriminator 1 view .LVU1657 5131 .LBB531: 5132 .loc 7 3558 3 discriminator 1 view .LVU1658 5133 .loc 7 3558 3 discriminator 1 view .LVU1659 5134 .loc 7 3558 3 discriminator 1 view .LVU1660 5135 .LBB532: 5136 .LBI532: 5137 .file 8 "Drivers/CMSIS/Include/cmsis_gcc.h" 1:Drivers/CMSIS/Include/cmsis_gcc.h **** /**************************************************************************//** 2:Drivers/CMSIS/Include/cmsis_gcc.h **** * @file cmsis_gcc.h 3:Drivers/CMSIS/Include/cmsis_gcc.h **** * @brief CMSIS compiler GCC header file 4:Drivers/CMSIS/Include/cmsis_gcc.h **** * @version V5.0.4 5:Drivers/CMSIS/Include/cmsis_gcc.h **** * @date 09. April 2018 6:Drivers/CMSIS/Include/cmsis_gcc.h **** ******************************************************************************/ 7:Drivers/CMSIS/Include/cmsis_gcc.h **** /* 8:Drivers/CMSIS/Include/cmsis_gcc.h **** * Copyright (c) 2009-2018 Arm Limited. All rights reserved. 9:Drivers/CMSIS/Include/cmsis_gcc.h **** * 10:Drivers/CMSIS/Include/cmsis_gcc.h **** * SPDX-License-Identifier: Apache-2.0 11:Drivers/CMSIS/Include/cmsis_gcc.h **** * 12:Drivers/CMSIS/Include/cmsis_gcc.h **** * Licensed under the Apache License, Version 2.0 (the License); you may 13:Drivers/CMSIS/Include/cmsis_gcc.h **** * not use this file except in compliance with the License. 14:Drivers/CMSIS/Include/cmsis_gcc.h **** * You may obtain a copy of the License at 15:Drivers/CMSIS/Include/cmsis_gcc.h **** * 16:Drivers/CMSIS/Include/cmsis_gcc.h **** * www.apache.org/licenses/LICENSE-2.0 17:Drivers/CMSIS/Include/cmsis_gcc.h **** * 18:Drivers/CMSIS/Include/cmsis_gcc.h **** * Unless required by applicable law or agreed to in writing, software 19:Drivers/CMSIS/Include/cmsis_gcc.h **** * distributed under the License is distributed on an AS IS BASIS, WITHOUT 20:Drivers/CMSIS/Include/cmsis_gcc.h **** * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 21:Drivers/CMSIS/Include/cmsis_gcc.h **** * See the License for the specific language governing permissions and 22:Drivers/CMSIS/Include/cmsis_gcc.h **** * limitations under the License. 23:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 24:Drivers/CMSIS/Include/cmsis_gcc.h **** 25:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __CMSIS_GCC_H 26:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_H 27:Drivers/CMSIS/Include/cmsis_gcc.h **** 28:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ignore some GCC warnings */ 29:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push ARM GAS /tmp/ccYgfTud.s page 433 30:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wsign-conversion" 31:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wconversion" 32:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wunused-parameter" 33:Drivers/CMSIS/Include/cmsis_gcc.h **** 34:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Fallback for __has_builtin */ 35:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __has_builtin 36:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __has_builtin(x) (0) 37:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 38:Drivers/CMSIS/Include/cmsis_gcc.h **** 39:Drivers/CMSIS/Include/cmsis_gcc.h **** /* CMSIS compiler specific defines */ 40:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __ASM 41:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __ASM __asm 42:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 43:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __INLINE 44:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __INLINE inline 45:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 46:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __STATIC_INLINE 47:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __STATIC_INLINE static inline 48:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 49:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __STATIC_FORCEINLINE 50:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline 51:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 52:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __NO_RETURN 53:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __NO_RETURN __attribute__((__noreturn__)) 54:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 55:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __USED 56:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __USED __attribute__((used)) 57:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 58:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __WEAK 59:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __WEAK __attribute__((weak)) 60:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 61:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PACKED 62:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PACKED __attribute__((packed, aligned(1))) 63:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 64:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PACKED_STRUCT 65:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) 66:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 67:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PACKED_UNION 68:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PACKED_UNION union __attribute__((packed, aligned(1))) 69:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 70:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT32 /* deprecated */ 71:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push 72:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" 73:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" 74:Drivers/CMSIS/Include/cmsis_gcc.h **** struct __attribute__((packed)) T_UINT32 { uint32_t v; }; 75:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop 76:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) 77:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 78:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT16_WRITE 79:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push 80:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" 81:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" 82:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; 83:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop 84:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))- 85:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 86:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT16_READ ARM GAS /tmp/ccYgfTud.s page 434 87:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push 88:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" 89:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" 90:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; 91:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop 92:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(add 93:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 94:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT32_WRITE 95:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push 96:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" 97:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" 98:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; 99:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop 100:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))- 101:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 102:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT32_READ 103:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push 104:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" 105:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" 106:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; 107:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop 108:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(add 109:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 110:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __ALIGNED 111:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __ALIGNED(x) __attribute__((aligned(x))) 112:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 113:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __RESTRICT 114:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __RESTRICT __restrict 115:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 116:Drivers/CMSIS/Include/cmsis_gcc.h **** 117:Drivers/CMSIS/Include/cmsis_gcc.h **** 118:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ########################### Core Function Access ########################### */ 119:Drivers/CMSIS/Include/cmsis_gcc.h **** /** \ingroup CMSIS_Core_FunctionInterface 120:Drivers/CMSIS/Include/cmsis_gcc.h **** \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions 121:Drivers/CMSIS/Include/cmsis_gcc.h **** @{ 122:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 123:Drivers/CMSIS/Include/cmsis_gcc.h **** 124:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 125:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Enable IRQ Interrupts 126:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Enables IRQ interrupts by clearing the I-bit in the CPSR. 127:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes. 128:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 129:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __enable_irq(void) 130:Drivers/CMSIS/Include/cmsis_gcc.h **** { 131:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsie i" : : : "memory"); 132:Drivers/CMSIS/Include/cmsis_gcc.h **** } 133:Drivers/CMSIS/Include/cmsis_gcc.h **** 134:Drivers/CMSIS/Include/cmsis_gcc.h **** 135:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 136:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Disable IRQ Interrupts 137:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Disables IRQ interrupts by setting the I-bit in the CPSR. 138:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes. 139:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 140:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __disable_irq(void) 141:Drivers/CMSIS/Include/cmsis_gcc.h **** { 142:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsid i" : : : "memory"); 143:Drivers/CMSIS/Include/cmsis_gcc.h **** } ARM GAS /tmp/ccYgfTud.s page 435 144:Drivers/CMSIS/Include/cmsis_gcc.h **** 145:Drivers/CMSIS/Include/cmsis_gcc.h **** 146:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 147:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Control Register 148:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the Control Register. 149:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Control Register value 150:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 151:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_CONTROL(void) 152:Drivers/CMSIS/Include/cmsis_gcc.h **** { 153:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 154:Drivers/CMSIS/Include/cmsis_gcc.h **** 155:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, control" : "=r" (result) ); 156:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 157:Drivers/CMSIS/Include/cmsis_gcc.h **** } 158:Drivers/CMSIS/Include/cmsis_gcc.h **** 159:Drivers/CMSIS/Include/cmsis_gcc.h **** 160:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) 161:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 162:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Control Register (non-secure) 163:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the non-secure Control Register when in secure mode. 164:Drivers/CMSIS/Include/cmsis_gcc.h **** \return non-secure Control Register value 165:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 166:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) 167:Drivers/CMSIS/Include/cmsis_gcc.h **** { 168:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 169:Drivers/CMSIS/Include/cmsis_gcc.h **** 170:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); 171:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 172:Drivers/CMSIS/Include/cmsis_gcc.h **** } 173:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 174:Drivers/CMSIS/Include/cmsis_gcc.h **** 175:Drivers/CMSIS/Include/cmsis_gcc.h **** 176:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 177:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Control Register 178:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Writes the given value to the Control Register. 179:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] control Control Register value to set 180:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 181:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) 182:Drivers/CMSIS/Include/cmsis_gcc.h **** { 183:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); 184:Drivers/CMSIS/Include/cmsis_gcc.h **** } 185:Drivers/CMSIS/Include/cmsis_gcc.h **** 186:Drivers/CMSIS/Include/cmsis_gcc.h **** 187:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) 188:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 189:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Control Register (non-secure) 190:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Writes the given value to the non-secure Control Register when in secure state. 191:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] control Control Register value to set 192:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 193:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) 194:Drivers/CMSIS/Include/cmsis_gcc.h **** { 195:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); 196:Drivers/CMSIS/Include/cmsis_gcc.h **** } 197:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 198:Drivers/CMSIS/Include/cmsis_gcc.h **** 199:Drivers/CMSIS/Include/cmsis_gcc.h **** 200:Drivers/CMSIS/Include/cmsis_gcc.h **** /** ARM GAS /tmp/ccYgfTud.s page 436 201:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get IPSR Register 202:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the IPSR Register. 203:Drivers/CMSIS/Include/cmsis_gcc.h **** \return IPSR Register value 204:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 205:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_IPSR(void) 206:Drivers/CMSIS/Include/cmsis_gcc.h **** { 207:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 208:Drivers/CMSIS/Include/cmsis_gcc.h **** 209:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); 210:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 211:Drivers/CMSIS/Include/cmsis_gcc.h **** } 212:Drivers/CMSIS/Include/cmsis_gcc.h **** 213:Drivers/CMSIS/Include/cmsis_gcc.h **** 214:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 215:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get APSR Register 216:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the APSR Register. 217:Drivers/CMSIS/Include/cmsis_gcc.h **** \return APSR Register value 218:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 219:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_APSR(void) 220:Drivers/CMSIS/Include/cmsis_gcc.h **** { 221:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 222:Drivers/CMSIS/Include/cmsis_gcc.h **** 223:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, apsr" : "=r" (result) ); 224:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 225:Drivers/CMSIS/Include/cmsis_gcc.h **** } 226:Drivers/CMSIS/Include/cmsis_gcc.h **** 227:Drivers/CMSIS/Include/cmsis_gcc.h **** 228:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 229:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get xPSR Register 230:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the xPSR Register. 231:Drivers/CMSIS/Include/cmsis_gcc.h **** \return xPSR Register value 232:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 233:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_xPSR(void) 234:Drivers/CMSIS/Include/cmsis_gcc.h **** { 235:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 236:Drivers/CMSIS/Include/cmsis_gcc.h **** 237:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); 238:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 239:Drivers/CMSIS/Include/cmsis_gcc.h **** } 240:Drivers/CMSIS/Include/cmsis_gcc.h **** 241:Drivers/CMSIS/Include/cmsis_gcc.h **** 242:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 243:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Process Stack Pointer 244:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Process Stack Pointer (PSP). 245:Drivers/CMSIS/Include/cmsis_gcc.h **** \return PSP Register value 246:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 247:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_PSP(void) 248:Drivers/CMSIS/Include/cmsis_gcc.h **** { 249:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 250:Drivers/CMSIS/Include/cmsis_gcc.h **** 251:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, psp" : "=r" (result) ); 252:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 253:Drivers/CMSIS/Include/cmsis_gcc.h **** } 254:Drivers/CMSIS/Include/cmsis_gcc.h **** 255:Drivers/CMSIS/Include/cmsis_gcc.h **** 256:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) 257:Drivers/CMSIS/Include/cmsis_gcc.h **** /** ARM GAS /tmp/ccYgfTud.s page 437 258:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Process Stack Pointer (non-secure) 259:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure s 260:Drivers/CMSIS/Include/cmsis_gcc.h **** \return PSP Register value 261:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 262:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) 263:Drivers/CMSIS/Include/cmsis_gcc.h **** { 264:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 265:Drivers/CMSIS/Include/cmsis_gcc.h **** 266:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); 267:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 268:Drivers/CMSIS/Include/cmsis_gcc.h **** } 269:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 270:Drivers/CMSIS/Include/cmsis_gcc.h **** 271:Drivers/CMSIS/Include/cmsis_gcc.h **** 272:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 273:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Process Stack Pointer 274:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Process Stack Pointer (PSP). 275:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfProcStack Process Stack Pointer value to set 276:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 277:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) 278:Drivers/CMSIS/Include/cmsis_gcc.h **** { 279:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); 280:Drivers/CMSIS/Include/cmsis_gcc.h **** } 281:Drivers/CMSIS/Include/cmsis_gcc.h **** 282:Drivers/CMSIS/Include/cmsis_gcc.h **** 283:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) 284:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 285:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Process Stack Pointer (non-secure) 286:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure sta 287:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfProcStack Process Stack Pointer value to set 288:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 289:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) 290:Drivers/CMSIS/Include/cmsis_gcc.h **** { 291:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); 292:Drivers/CMSIS/Include/cmsis_gcc.h **** } 293:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 294:Drivers/CMSIS/Include/cmsis_gcc.h **** 295:Drivers/CMSIS/Include/cmsis_gcc.h **** 296:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 297:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Main Stack Pointer 298:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Main Stack Pointer (MSP). 299:Drivers/CMSIS/Include/cmsis_gcc.h **** \return MSP Register value 300:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 301:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_MSP(void) 302:Drivers/CMSIS/Include/cmsis_gcc.h **** { 303:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 304:Drivers/CMSIS/Include/cmsis_gcc.h **** 305:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, msp" : "=r" (result) ); 306:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 307:Drivers/CMSIS/Include/cmsis_gcc.h **** } 308:Drivers/CMSIS/Include/cmsis_gcc.h **** 309:Drivers/CMSIS/Include/cmsis_gcc.h **** 310:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) 311:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 312:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Main Stack Pointer (non-secure) 313:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure stat 314:Drivers/CMSIS/Include/cmsis_gcc.h **** \return MSP Register value ARM GAS /tmp/ccYgfTud.s page 438 315:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 316:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) 317:Drivers/CMSIS/Include/cmsis_gcc.h **** { 318:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 319:Drivers/CMSIS/Include/cmsis_gcc.h **** 320:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); 321:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 322:Drivers/CMSIS/Include/cmsis_gcc.h **** } 323:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 324:Drivers/CMSIS/Include/cmsis_gcc.h **** 325:Drivers/CMSIS/Include/cmsis_gcc.h **** 326:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 327:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Main Stack Pointer 328:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Main Stack Pointer (MSP). 329:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfMainStack Main Stack Pointer value to set 330:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 331:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) 332:Drivers/CMSIS/Include/cmsis_gcc.h **** { 333:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); 334:Drivers/CMSIS/Include/cmsis_gcc.h **** } 335:Drivers/CMSIS/Include/cmsis_gcc.h **** 336:Drivers/CMSIS/Include/cmsis_gcc.h **** 337:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) 338:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 339:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Main Stack Pointer (non-secure) 340:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. 341:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfMainStack Main Stack Pointer value to set 342:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 343:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) 344:Drivers/CMSIS/Include/cmsis_gcc.h **** { 345:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); 346:Drivers/CMSIS/Include/cmsis_gcc.h **** } 347:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 348:Drivers/CMSIS/Include/cmsis_gcc.h **** 349:Drivers/CMSIS/Include/cmsis_gcc.h **** 350:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) 351:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 352:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Stack Pointer (non-secure) 353:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. 354:Drivers/CMSIS/Include/cmsis_gcc.h **** \return SP Register value 355:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 356:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) 357:Drivers/CMSIS/Include/cmsis_gcc.h **** { 358:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 359:Drivers/CMSIS/Include/cmsis_gcc.h **** 360:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); 361:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 362:Drivers/CMSIS/Include/cmsis_gcc.h **** } 363:Drivers/CMSIS/Include/cmsis_gcc.h **** 364:Drivers/CMSIS/Include/cmsis_gcc.h **** 365:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 366:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Stack Pointer (non-secure) 367:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. 368:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfStack Stack Pointer value to set 369:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 370:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) 371:Drivers/CMSIS/Include/cmsis_gcc.h **** { ARM GAS /tmp/ccYgfTud.s page 439 372:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); 373:Drivers/CMSIS/Include/cmsis_gcc.h **** } 374:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 375:Drivers/CMSIS/Include/cmsis_gcc.h **** 376:Drivers/CMSIS/Include/cmsis_gcc.h **** 377:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 378:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Priority Mask 379:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current state of the priority mask bit from the Priority Mask Register. 380:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Priority Mask value 381:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 382:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) 383:Drivers/CMSIS/Include/cmsis_gcc.h **** { 384:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 385:Drivers/CMSIS/Include/cmsis_gcc.h **** 386:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); 387:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 388:Drivers/CMSIS/Include/cmsis_gcc.h **** } 389:Drivers/CMSIS/Include/cmsis_gcc.h **** 390:Drivers/CMSIS/Include/cmsis_gcc.h **** 391:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) 392:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 393:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Priority Mask (non-secure) 394:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current state of the non-secure priority mask bit from the Priority Mask Reg 395:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Priority Mask value 396:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 397:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) 398:Drivers/CMSIS/Include/cmsis_gcc.h **** { 399:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 400:Drivers/CMSIS/Include/cmsis_gcc.h **** 401:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, primask_ns" : "=r" (result) :: "memory"); 402:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 403:Drivers/CMSIS/Include/cmsis_gcc.h **** } 404:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 405:Drivers/CMSIS/Include/cmsis_gcc.h **** 406:Drivers/CMSIS/Include/cmsis_gcc.h **** 407:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 408:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Priority Mask 409:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Priority Mask Register. 410:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] priMask Priority Mask 411:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 412:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) 413:Drivers/CMSIS/Include/cmsis_gcc.h **** { 414:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); 415:Drivers/CMSIS/Include/cmsis_gcc.h **** } 416:Drivers/CMSIS/Include/cmsis_gcc.h **** 417:Drivers/CMSIS/Include/cmsis_gcc.h **** 418:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) 419:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 420:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Priority Mask (non-secure) 421:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Priority Mask Register when in secure state. 422:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] priMask Priority Mask 423:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 424:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) 425:Drivers/CMSIS/Include/cmsis_gcc.h **** { 426:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); 427:Drivers/CMSIS/Include/cmsis_gcc.h **** } 428:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif ARM GAS /tmp/ccYgfTud.s page 440 429:Drivers/CMSIS/Include/cmsis_gcc.h **** 430:Drivers/CMSIS/Include/cmsis_gcc.h **** 431:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ 432:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ 433:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) 434:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 435:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Enable FIQ 436:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Enables FIQ interrupts by clearing the F-bit in the CPSR. 437:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes. 438:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 439:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __enable_fault_irq(void) 440:Drivers/CMSIS/Include/cmsis_gcc.h **** { 441:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsie f" : : : "memory"); 442:Drivers/CMSIS/Include/cmsis_gcc.h **** } 443:Drivers/CMSIS/Include/cmsis_gcc.h **** 444:Drivers/CMSIS/Include/cmsis_gcc.h **** 445:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 446:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Disable FIQ 447:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Disables FIQ interrupts by setting the F-bit in the CPSR. 448:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes. 449:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 450:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __disable_fault_irq(void) 451:Drivers/CMSIS/Include/cmsis_gcc.h **** { 452:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsid f" : : : "memory"); 453:Drivers/CMSIS/Include/cmsis_gcc.h **** } 454:Drivers/CMSIS/Include/cmsis_gcc.h **** 455:Drivers/CMSIS/Include/cmsis_gcc.h **** 456:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 457:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Base Priority 458:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Base Priority register. 459:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Base Priority register value 460:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 461:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) 462:Drivers/CMSIS/Include/cmsis_gcc.h **** { 463:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 464:Drivers/CMSIS/Include/cmsis_gcc.h **** 465:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, basepri" : "=r" (result) ); 466:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 467:Drivers/CMSIS/Include/cmsis_gcc.h **** } 468:Drivers/CMSIS/Include/cmsis_gcc.h **** 469:Drivers/CMSIS/Include/cmsis_gcc.h **** 470:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) 471:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 472:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Base Priority (non-secure) 473:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Base Priority register when in secure state. 474:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Base Priority register value 475:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 476:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) 477:Drivers/CMSIS/Include/cmsis_gcc.h **** { 478:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 479:Drivers/CMSIS/Include/cmsis_gcc.h **** 480:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); 481:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 482:Drivers/CMSIS/Include/cmsis_gcc.h **** } 483:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 484:Drivers/CMSIS/Include/cmsis_gcc.h **** 485:Drivers/CMSIS/Include/cmsis_gcc.h **** ARM GAS /tmp/ccYgfTud.s page 441 486:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 487:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Base Priority 488:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Base Priority register. 489:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] basePri Base Priority value to set 490:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 491:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) 492:Drivers/CMSIS/Include/cmsis_gcc.h **** { 493:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); 494:Drivers/CMSIS/Include/cmsis_gcc.h **** } 495:Drivers/CMSIS/Include/cmsis_gcc.h **** 496:Drivers/CMSIS/Include/cmsis_gcc.h **** 497:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) 498:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 499:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Base Priority (non-secure) 500:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Base Priority register when in secure state. 501:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] basePri Base Priority value to set 502:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 503:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) 504:Drivers/CMSIS/Include/cmsis_gcc.h **** { 505:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); 506:Drivers/CMSIS/Include/cmsis_gcc.h **** } 507:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 508:Drivers/CMSIS/Include/cmsis_gcc.h **** 509:Drivers/CMSIS/Include/cmsis_gcc.h **** 510:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 511:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Base Priority with condition 512:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Base Priority register only if BASEPRI masking is disable 513:Drivers/CMSIS/Include/cmsis_gcc.h **** or the new value increases the BASEPRI priority level. 514:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] basePri Base Priority value to set 515:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 516:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) 517:Drivers/CMSIS/Include/cmsis_gcc.h **** { 518:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); 519:Drivers/CMSIS/Include/cmsis_gcc.h **** } 520:Drivers/CMSIS/Include/cmsis_gcc.h **** 521:Drivers/CMSIS/Include/cmsis_gcc.h **** 522:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 523:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Fault Mask 524:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Fault Mask register. 525:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Fault Mask register value 526:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 527:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) 528:Drivers/CMSIS/Include/cmsis_gcc.h **** { 529:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 530:Drivers/CMSIS/Include/cmsis_gcc.h **** 531:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); 532:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 533:Drivers/CMSIS/Include/cmsis_gcc.h **** } 534:Drivers/CMSIS/Include/cmsis_gcc.h **** 535:Drivers/CMSIS/Include/cmsis_gcc.h **** 536:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) 537:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 538:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Fault Mask (non-secure) 539:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Fault Mask register when in secure state. 540:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Fault Mask register value 541:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 542:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) ARM GAS /tmp/ccYgfTud.s page 442 543:Drivers/CMSIS/Include/cmsis_gcc.h **** { 544:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 545:Drivers/CMSIS/Include/cmsis_gcc.h **** 546:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); 547:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 548:Drivers/CMSIS/Include/cmsis_gcc.h **** } 549:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 550:Drivers/CMSIS/Include/cmsis_gcc.h **** 551:Drivers/CMSIS/Include/cmsis_gcc.h **** 552:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 553:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Fault Mask 554:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Fault Mask register. 555:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] faultMask Fault Mask value to set 556:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 557:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) 558:Drivers/CMSIS/Include/cmsis_gcc.h **** { 559:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); 560:Drivers/CMSIS/Include/cmsis_gcc.h **** } 561:Drivers/CMSIS/Include/cmsis_gcc.h **** 562:Drivers/CMSIS/Include/cmsis_gcc.h **** 563:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) 564:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 565:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Fault Mask (non-secure) 566:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Fault Mask register when in secure state. 567:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] faultMask Fault Mask value to set 568:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 569:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) 570:Drivers/CMSIS/Include/cmsis_gcc.h **** { 571:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); 572:Drivers/CMSIS/Include/cmsis_gcc.h **** } 573:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 574:Drivers/CMSIS/Include/cmsis_gcc.h **** 575:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ 576:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ 577:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ 578:Drivers/CMSIS/Include/cmsis_gcc.h **** 579:Drivers/CMSIS/Include/cmsis_gcc.h **** 580:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ 581:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) 582:Drivers/CMSIS/Include/cmsis_gcc.h **** 583:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 584:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Process Stack Pointer Limit 585:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure 586:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence zero is returned always in non-secure 587:Drivers/CMSIS/Include/cmsis_gcc.h **** mode. 588:Drivers/CMSIS/Include/cmsis_gcc.h **** 589:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). 590:Drivers/CMSIS/Include/cmsis_gcc.h **** \return PSPLIM Register value 591:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 592:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) 593:Drivers/CMSIS/Include/cmsis_gcc.h **** { 594:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ 595:Drivers/CMSIS/Include/cmsis_gcc.h **** (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) 596:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure PSPLIM is RAZ/WI 597:Drivers/CMSIS/Include/cmsis_gcc.h **** return 0U; 598:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 599:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; ARM GAS /tmp/ccYgfTud.s page 443 600:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, psplim" : "=r" (result) ); 601:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; 602:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 603:Drivers/CMSIS/Include/cmsis_gcc.h **** } 604:Drivers/CMSIS/Include/cmsis_gcc.h **** 605:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) 606:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 607:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Process Stack Pointer Limit (non-secure) 608:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure 609:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence zero is returned always. 610:Drivers/CMSIS/Include/cmsis_gcc.h **** 611:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in 612:Drivers/CMSIS/Include/cmsis_gcc.h **** \return PSPLIM Register value 613:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 614:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) 615:Drivers/CMSIS/Include/cmsis_gcc.h **** { 616:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) 617:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure PSPLIM is RAZ/WI 618:Drivers/CMSIS/Include/cmsis_gcc.h **** return 0U; 619:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 620:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 621:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); 622:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; 623:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 624:Drivers/CMSIS/Include/cmsis_gcc.h **** } 625:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 626:Drivers/CMSIS/Include/cmsis_gcc.h **** 627:Drivers/CMSIS/Include/cmsis_gcc.h **** 628:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 629:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Process Stack Pointer Limit 630:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure 631:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence the write is silently ignored in non-secure 632:Drivers/CMSIS/Include/cmsis_gcc.h **** mode. 633:Drivers/CMSIS/Include/cmsis_gcc.h **** 634:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). 635:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set 636:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 637:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) 638:Drivers/CMSIS/Include/cmsis_gcc.h **** { 639:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ 640:Drivers/CMSIS/Include/cmsis_gcc.h **** (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) 641:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure PSPLIM is RAZ/WI 642:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)ProcStackPtrLimit; 643:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 644:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); 645:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 646:Drivers/CMSIS/Include/cmsis_gcc.h **** } 647:Drivers/CMSIS/Include/cmsis_gcc.h **** 648:Drivers/CMSIS/Include/cmsis_gcc.h **** 649:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) 650:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 651:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Process Stack Pointer (non-secure) 652:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure 653:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence the write is silently ignored. 654:Drivers/CMSIS/Include/cmsis_gcc.h **** 655:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in s 656:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set ARM GAS /tmp/ccYgfTud.s page 444 657:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 658:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) 659:Drivers/CMSIS/Include/cmsis_gcc.h **** { 660:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) 661:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure PSPLIM is RAZ/WI 662:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)ProcStackPtrLimit; 663:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 664:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); 665:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 666:Drivers/CMSIS/Include/cmsis_gcc.h **** } 667:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 668:Drivers/CMSIS/Include/cmsis_gcc.h **** 669:Drivers/CMSIS/Include/cmsis_gcc.h **** 670:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 671:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Main Stack Pointer Limit 672:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure 673:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence zero is returned always in non-secure 674:Drivers/CMSIS/Include/cmsis_gcc.h **** mode. 675:Drivers/CMSIS/Include/cmsis_gcc.h **** 676:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). 677:Drivers/CMSIS/Include/cmsis_gcc.h **** \return MSPLIM Register value 678:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 679:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) 680:Drivers/CMSIS/Include/cmsis_gcc.h **** { 681:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ 682:Drivers/CMSIS/Include/cmsis_gcc.h **** (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) 683:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure MSPLIM is RAZ/WI 684:Drivers/CMSIS/Include/cmsis_gcc.h **** return 0U; 685:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 686:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 687:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, msplim" : "=r" (result) ); 688:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; 689:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 690:Drivers/CMSIS/Include/cmsis_gcc.h **** } 691:Drivers/CMSIS/Include/cmsis_gcc.h **** 692:Drivers/CMSIS/Include/cmsis_gcc.h **** 693:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) 694:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 695:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Main Stack Pointer Limit (non-secure) 696:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure 697:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence zero is returned always. 698:Drivers/CMSIS/Include/cmsis_gcc.h **** 699:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in sec 700:Drivers/CMSIS/Include/cmsis_gcc.h **** \return MSPLIM Register value 701:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 702:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) 703:Drivers/CMSIS/Include/cmsis_gcc.h **** { 704:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) 705:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure MSPLIM is RAZ/WI 706:Drivers/CMSIS/Include/cmsis_gcc.h **** return 0U; 707:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 708:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 709:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); 710:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; 711:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 712:Drivers/CMSIS/Include/cmsis_gcc.h **** } 713:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif ARM GAS /tmp/ccYgfTud.s page 445 714:Drivers/CMSIS/Include/cmsis_gcc.h **** 715:Drivers/CMSIS/Include/cmsis_gcc.h **** 716:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 717:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Main Stack Pointer Limit 718:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure 719:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence the write is silently ignored in non-secure 720:Drivers/CMSIS/Include/cmsis_gcc.h **** mode. 721:Drivers/CMSIS/Include/cmsis_gcc.h **** 722:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). 723:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set 724:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 725:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) 726:Drivers/CMSIS/Include/cmsis_gcc.h **** { 727:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ 728:Drivers/CMSIS/Include/cmsis_gcc.h **** (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) 729:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure MSPLIM is RAZ/WI 730:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)MainStackPtrLimit; 731:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 732:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); 733:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 734:Drivers/CMSIS/Include/cmsis_gcc.h **** } 735:Drivers/CMSIS/Include/cmsis_gcc.h **** 736:Drivers/CMSIS/Include/cmsis_gcc.h **** 737:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) 738:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 739:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Main Stack Pointer Limit (non-secure) 740:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure 741:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence the write is silently ignored. 742:Drivers/CMSIS/Include/cmsis_gcc.h **** 743:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secu 744:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] MainStackPtrLimit Main Stack Pointer value to set 745:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 746:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) 747:Drivers/CMSIS/Include/cmsis_gcc.h **** { 748:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) 749:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure MSPLIM is RAZ/WI 750:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)MainStackPtrLimit; 751:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 752:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); 753:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 754:Drivers/CMSIS/Include/cmsis_gcc.h **** } 755:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 756:Drivers/CMSIS/Include/cmsis_gcc.h **** 757:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ 758:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ 759:Drivers/CMSIS/Include/cmsis_gcc.h **** 760:Drivers/CMSIS/Include/cmsis_gcc.h **** 761:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 762:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get FPSCR 763:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Floating Point Status/Control register. 764:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Floating Point Status/Control register value 765:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 766:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_FPSCR(void) 767:Drivers/CMSIS/Include/cmsis_gcc.h **** { 768:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ 769:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) 770:Drivers/CMSIS/Include/cmsis_gcc.h **** #if __has_builtin(__builtin_arm_get_fpscr) ARM GAS /tmp/ccYgfTud.s page 446 771:Drivers/CMSIS/Include/cmsis_gcc.h **** // Re-enable using built-in when GCC has been fixed 772:Drivers/CMSIS/Include/cmsis_gcc.h **** // || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) 773:Drivers/CMSIS/Include/cmsis_gcc.h **** /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ 774:Drivers/CMSIS/Include/cmsis_gcc.h **** return __builtin_arm_get_fpscr(); 775:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 776:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 777:Drivers/CMSIS/Include/cmsis_gcc.h **** 778:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); 779:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 780:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 781:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 782:Drivers/CMSIS/Include/cmsis_gcc.h **** return(0U); 783:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 784:Drivers/CMSIS/Include/cmsis_gcc.h **** } 785:Drivers/CMSIS/Include/cmsis_gcc.h **** 786:Drivers/CMSIS/Include/cmsis_gcc.h **** 787:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 788:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set FPSCR 789:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Floating Point Status/Control register. 790:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] fpscr Floating Point Status/Control value to set 791:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 792:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) 793:Drivers/CMSIS/Include/cmsis_gcc.h **** { 794:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ 795:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) 796:Drivers/CMSIS/Include/cmsis_gcc.h **** #if __has_builtin(__builtin_arm_set_fpscr) 797:Drivers/CMSIS/Include/cmsis_gcc.h **** // Re-enable using built-in when GCC has been fixed 798:Drivers/CMSIS/Include/cmsis_gcc.h **** // || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) 799:Drivers/CMSIS/Include/cmsis_gcc.h **** /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ 800:Drivers/CMSIS/Include/cmsis_gcc.h **** __builtin_arm_set_fpscr(fpscr); 801:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 802:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory"); 803:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 804:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 805:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)fpscr; 806:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 807:Drivers/CMSIS/Include/cmsis_gcc.h **** } 808:Drivers/CMSIS/Include/cmsis_gcc.h **** 809:Drivers/CMSIS/Include/cmsis_gcc.h **** 810:Drivers/CMSIS/Include/cmsis_gcc.h **** /*@} end of CMSIS_Core_RegAccFunctions */ 811:Drivers/CMSIS/Include/cmsis_gcc.h **** 812:Drivers/CMSIS/Include/cmsis_gcc.h **** 813:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ########################## Core Instruction Access ######################### */ 814:Drivers/CMSIS/Include/cmsis_gcc.h **** /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface 815:Drivers/CMSIS/Include/cmsis_gcc.h **** Access to dedicated instructions 816:Drivers/CMSIS/Include/cmsis_gcc.h **** @{ 817:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 818:Drivers/CMSIS/Include/cmsis_gcc.h **** 819:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Define macros for porting to both thumb1 and thumb2. 820:Drivers/CMSIS/Include/cmsis_gcc.h **** * For thumb1, use low register (r0-r7), specified by constraint "l" 821:Drivers/CMSIS/Include/cmsis_gcc.h **** * Otherwise, use general registers, specified by constraint "r" */ 822:Drivers/CMSIS/Include/cmsis_gcc.h **** #if defined (__thumb__) && !defined (__thumb2__) 823:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_OUT_REG(r) "=l" (r) 824:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_RW_REG(r) "+l" (r) 825:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_USE_REG(r) "l" (r) 826:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 827:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_OUT_REG(r) "=r" (r) ARM GAS /tmp/ccYgfTud.s page 447 828:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_RW_REG(r) "+r" (r) 829:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_USE_REG(r) "r" (r) 830:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 831:Drivers/CMSIS/Include/cmsis_gcc.h **** 832:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 833:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief No Operation 834:Drivers/CMSIS/Include/cmsis_gcc.h **** \details No Operation does nothing. This instruction can be used for code alignment purposes. 835:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 836:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __NOP() __ASM volatile ("nop") 837:Drivers/CMSIS/Include/cmsis_gcc.h **** 838:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 839:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Wait For Interrupt 840:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Wait For Interrupt is a hint instruction that suspends execution until one of a number o 841:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 842:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __WFI() __ASM volatile ("wfi") 843:Drivers/CMSIS/Include/cmsis_gcc.h **** 844:Drivers/CMSIS/Include/cmsis_gcc.h **** 845:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 846:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Wait For Event 847:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Wait For Event is a hint instruction that permits the processor to enter 848:Drivers/CMSIS/Include/cmsis_gcc.h **** a low-power state until one of a number of events occurs. 849:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 850:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __WFE() __ASM volatile ("wfe") 851:Drivers/CMSIS/Include/cmsis_gcc.h **** 852:Drivers/CMSIS/Include/cmsis_gcc.h **** 853:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 854:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Send Event 855:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. 856:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 857:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __SEV() __ASM volatile ("sev") 858:Drivers/CMSIS/Include/cmsis_gcc.h **** 859:Drivers/CMSIS/Include/cmsis_gcc.h **** 860:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 861:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Instruction Synchronization Barrier 862:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Instruction Synchronization Barrier flushes the pipeline in the processor, 863:Drivers/CMSIS/Include/cmsis_gcc.h **** so that all instructions following the ISB are fetched from cache or memory, 864:Drivers/CMSIS/Include/cmsis_gcc.h **** after the instruction has been completed. 865:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 866:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __ISB(void) 867:Drivers/CMSIS/Include/cmsis_gcc.h **** { 868:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("isb 0xF":::"memory"); 869:Drivers/CMSIS/Include/cmsis_gcc.h **** } 870:Drivers/CMSIS/Include/cmsis_gcc.h **** 871:Drivers/CMSIS/Include/cmsis_gcc.h **** 872:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 873:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Data Synchronization Barrier 874:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Acts as a special kind of Data Memory Barrier. 875:Drivers/CMSIS/Include/cmsis_gcc.h **** It completes when all explicit memory accesses before this instruction complete. 876:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 877:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __DSB(void) 878:Drivers/CMSIS/Include/cmsis_gcc.h **** { 879:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("dsb 0xF":::"memory"); 880:Drivers/CMSIS/Include/cmsis_gcc.h **** } 881:Drivers/CMSIS/Include/cmsis_gcc.h **** 882:Drivers/CMSIS/Include/cmsis_gcc.h **** 883:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 884:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Data Memory Barrier ARM GAS /tmp/ccYgfTud.s page 448 885:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Ensures the apparent order of the explicit memory operations before 886:Drivers/CMSIS/Include/cmsis_gcc.h **** and after the instruction, without ensuring their completion. 887:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 888:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __DMB(void) 889:Drivers/CMSIS/Include/cmsis_gcc.h **** { 890:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("dmb 0xF":::"memory"); 891:Drivers/CMSIS/Include/cmsis_gcc.h **** } 892:Drivers/CMSIS/Include/cmsis_gcc.h **** 893:Drivers/CMSIS/Include/cmsis_gcc.h **** 894:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 895:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Reverse byte order (32 bit) 896:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x785 897:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to reverse 898:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Reversed value 899:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 900:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __REV(uint32_t value) 901:Drivers/CMSIS/Include/cmsis_gcc.h **** { 902:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) 903:Drivers/CMSIS/Include/cmsis_gcc.h **** return __builtin_bswap32(value); 904:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 905:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 906:Drivers/CMSIS/Include/cmsis_gcc.h **** 907:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); 908:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; 909:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 910:Drivers/CMSIS/Include/cmsis_gcc.h **** } 911:Drivers/CMSIS/Include/cmsis_gcc.h **** 912:Drivers/CMSIS/Include/cmsis_gcc.h **** 913:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 914:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Reverse byte order (16 bit) 915:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 916:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to reverse 917:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Reversed value 918:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 919:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __REV16(uint32_t value) 920:Drivers/CMSIS/Include/cmsis_gcc.h **** { 921:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 922:Drivers/CMSIS/Include/cmsis_gcc.h **** 923:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); 924:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; 925:Drivers/CMSIS/Include/cmsis_gcc.h **** } 926:Drivers/CMSIS/Include/cmsis_gcc.h **** 927:Drivers/CMSIS/Include/cmsis_gcc.h **** 928:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 929:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Reverse byte order (16 bit) 930:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For exam 931:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to reverse 932:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Reversed value 933:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 934:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE int16_t __REVSH(int16_t value) 935:Drivers/CMSIS/Include/cmsis_gcc.h **** { 936:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) 937:Drivers/CMSIS/Include/cmsis_gcc.h **** return (int16_t)__builtin_bswap16(value); 938:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 939:Drivers/CMSIS/Include/cmsis_gcc.h **** int16_t result; 940:Drivers/CMSIS/Include/cmsis_gcc.h **** 941:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); ARM GAS /tmp/ccYgfTud.s page 449 942:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; 943:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 944:Drivers/CMSIS/Include/cmsis_gcc.h **** } 945:Drivers/CMSIS/Include/cmsis_gcc.h **** 946:Drivers/CMSIS/Include/cmsis_gcc.h **** 947:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 948:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Rotate Right in unsigned value (32 bit) 949:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Rotate Right (immediate) provides the value of the contents of a register rotated by a v 950:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] op1 Value to rotate 951:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] op2 Number of Bits to rotate 952:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Rotated value 953:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 954:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) 955:Drivers/CMSIS/Include/cmsis_gcc.h **** { 956:Drivers/CMSIS/Include/cmsis_gcc.h **** op2 %= 32U; 957:Drivers/CMSIS/Include/cmsis_gcc.h **** if (op2 == 0U) 958:Drivers/CMSIS/Include/cmsis_gcc.h **** { 959:Drivers/CMSIS/Include/cmsis_gcc.h **** return op1; 960:Drivers/CMSIS/Include/cmsis_gcc.h **** } 961:Drivers/CMSIS/Include/cmsis_gcc.h **** return (op1 >> op2) | (op1 << (32U - op2)); 962:Drivers/CMSIS/Include/cmsis_gcc.h **** } 963:Drivers/CMSIS/Include/cmsis_gcc.h **** 964:Drivers/CMSIS/Include/cmsis_gcc.h **** 965:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 966:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Breakpoint 967:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Causes the processor to enter Debug state. 968:Drivers/CMSIS/Include/cmsis_gcc.h **** Debug tools can use this to investigate system state when the instruction at a particula 969:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value is ignored by the processor. 970:Drivers/CMSIS/Include/cmsis_gcc.h **** If required, a debugger can use it to store additional information about the break 971:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 972:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __BKPT(value) __ASM volatile ("bkpt "#value) 973:Drivers/CMSIS/Include/cmsis_gcc.h **** 974:Drivers/CMSIS/Include/cmsis_gcc.h **** 975:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 976:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Reverse bit order of value 977:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Reverses the bit order of the given value. 978:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to reverse 979:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Reversed value 980:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 981:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value) 982:Drivers/CMSIS/Include/cmsis_gcc.h **** { 983:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 984:Drivers/CMSIS/Include/cmsis_gcc.h **** 985:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ 986:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ 987:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) 988:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 989:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 990:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ 991:Drivers/CMSIS/Include/cmsis_gcc.h **** 992:Drivers/CMSIS/Include/cmsis_gcc.h **** result = value; /* r will be reversed bits of v; first get LSB of v */ 993:Drivers/CMSIS/Include/cmsis_gcc.h **** for (value >>= 1U; value != 0U; value >>= 1U) 994:Drivers/CMSIS/Include/cmsis_gcc.h **** { 995:Drivers/CMSIS/Include/cmsis_gcc.h **** result <<= 1U; 996:Drivers/CMSIS/Include/cmsis_gcc.h **** result |= value & 1U; 997:Drivers/CMSIS/Include/cmsis_gcc.h **** s--; 998:Drivers/CMSIS/Include/cmsis_gcc.h **** } ARM GAS /tmp/ccYgfTud.s page 450 999:Drivers/CMSIS/Include/cmsis_gcc.h **** result <<= s; /* shift when v's highest bits are zero */ 1000:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 1001:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; 1002:Drivers/CMSIS/Include/cmsis_gcc.h **** } 1003:Drivers/CMSIS/Include/cmsis_gcc.h **** 1004:Drivers/CMSIS/Include/cmsis_gcc.h **** 1005:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 1006:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Count leading zeros 1007:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Counts the number of leading zeros of a data value. 1008:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to count the leading zeros 1009:Drivers/CMSIS/Include/cmsis_gcc.h **** \return number of leading zeros in value 1010:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 1011:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CLZ (uint8_t)__builtin_clz 1012:Drivers/CMSIS/Include/cmsis_gcc.h **** 1013:Drivers/CMSIS/Include/cmsis_gcc.h **** 1014:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ 1015:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ 1016:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ 1017:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) 1018:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 1019:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief LDR Exclusive (8 bit) 1020:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Executes a exclusive LDR instruction for 8 bit value. 1021:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ptr Pointer to data 1022:Drivers/CMSIS/Include/cmsis_gcc.h **** \return value of type uint8_t at (*ptr) 1023:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 1024:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr) 1025:Drivers/CMSIS/Include/cmsis_gcc.h **** { 1026:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 1027:Drivers/CMSIS/Include/cmsis_gcc.h **** 1028:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) 1029:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); 1030:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 1031:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not 1032:Drivers/CMSIS/Include/cmsis_gcc.h **** accepted by assembler. So has to use following less efficient pattern. 1033:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 1034:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); 1035:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 1036:Drivers/CMSIS/Include/cmsis_gcc.h **** return ((uint8_t) result); /* Add explicit type cast here */ 1037:Drivers/CMSIS/Include/cmsis_gcc.h **** } 1038:Drivers/CMSIS/Include/cmsis_gcc.h **** 1039:Drivers/CMSIS/Include/cmsis_gcc.h **** 1040:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 1041:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief LDR Exclusive (16 bit) 1042:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Executes a exclusive LDR instruction for 16 bit values. 1043:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ptr Pointer to data 1044:Drivers/CMSIS/Include/cmsis_gcc.h **** \return value of type uint16_t at (*ptr) 1045:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 1046:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr) 1047:Drivers/CMSIS/Include/cmsis_gcc.h **** { 1048:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 1049:Drivers/CMSIS/Include/cmsis_gcc.h **** 1050:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) 1051:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); 1052:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 1053:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not 1054:Drivers/CMSIS/Include/cmsis_gcc.h **** accepted by assembler. So has to use following less efficient pattern. 1055:Drivers/CMSIS/Include/cmsis_gcc.h **** */ ARM GAS /tmp/ccYgfTud.s page 451 1056:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); 1057:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 1058:Drivers/CMSIS/Include/cmsis_gcc.h **** return ((uint16_t) result); /* Add explicit type cast here */ 1059:Drivers/CMSIS/Include/cmsis_gcc.h **** } 1060:Drivers/CMSIS/Include/cmsis_gcc.h **** 1061:Drivers/CMSIS/Include/cmsis_gcc.h **** 1062:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 1063:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief LDR Exclusive (32 bit) 1064:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Executes a exclusive LDR instruction for 32 bit values. 1065:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ptr Pointer to data 1066:Drivers/CMSIS/Include/cmsis_gcc.h **** \return value of type uint32_t at (*ptr) 1067:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 1068:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr) 5138 .loc 8 1068 31 view .LVU1661 5139 .LBB533: 1069:Drivers/CMSIS/Include/cmsis_gcc.h **** { 1070:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 5140 .loc 8 1070 5 view .LVU1662 1071:Drivers/CMSIS/Include/cmsis_gcc.h **** 1072:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 5141 .loc 8 1072 4 view .LVU1663 5142 00e8 794A ldr r2, .L225+76 5143 00ea 02F10803 add r3, r2, #8 5144 .syntax unified 5145 @ 1072 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 5146 00ee 53E8003F ldrex r3, [r3] 5147 @ 0 "" 2 5148 .LVL416: 1073:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 5149 .loc 8 1073 4 view .LVU1664 5150 .loc 8 1073 4 is_stmt 0 view .LVU1665 5151 .thumb 5152 .syntax unified 5153 .LBE533: 5154 .LBE532: 5155 .loc 7 3558 3 discriminator 1 view .LVU1666 5156 00f2 43F08003 orr r3, r3, #128 5157 .LVL417: 5158 .loc 7 3558 3 is_stmt 1 discriminator 1 view .LVU1667 5159 .LBB534: 5160 .LBI534: 1074:Drivers/CMSIS/Include/cmsis_gcc.h **** } 1075:Drivers/CMSIS/Include/cmsis_gcc.h **** 1076:Drivers/CMSIS/Include/cmsis_gcc.h **** 1077:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 1078:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief STR Exclusive (8 bit) 1079:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Executes a exclusive STR instruction for 8 bit values. 1080:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to store 1081:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ptr Pointer to location 1082:Drivers/CMSIS/Include/cmsis_gcc.h **** \return 0 Function succeeded 1083:Drivers/CMSIS/Include/cmsis_gcc.h **** \return 1 Function failed 1084:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 1085:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) 1086:Drivers/CMSIS/Include/cmsis_gcc.h **** { 1087:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 1088:Drivers/CMSIS/Include/cmsis_gcc.h **** 1089:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); ARM GAS /tmp/ccYgfTud.s page 452 1090:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 1091:Drivers/CMSIS/Include/cmsis_gcc.h **** } 1092:Drivers/CMSIS/Include/cmsis_gcc.h **** 1093:Drivers/CMSIS/Include/cmsis_gcc.h **** 1094:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 1095:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief STR Exclusive (16 bit) 1096:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Executes a exclusive STR instruction for 16 bit values. 1097:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to store 1098:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ptr Pointer to location 1099:Drivers/CMSIS/Include/cmsis_gcc.h **** \return 0 Function succeeded 1100:Drivers/CMSIS/Include/cmsis_gcc.h **** \return 1 Function failed 1101:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 1102:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) 1103:Drivers/CMSIS/Include/cmsis_gcc.h **** { 1104:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 1105:Drivers/CMSIS/Include/cmsis_gcc.h **** 1106:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); 1107:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 1108:Drivers/CMSIS/Include/cmsis_gcc.h **** } 1109:Drivers/CMSIS/Include/cmsis_gcc.h **** 1110:Drivers/CMSIS/Include/cmsis_gcc.h **** 1111:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 1112:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief STR Exclusive (32 bit) 1113:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Executes a exclusive STR instruction for 32 bit values. 1114:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to store 1115:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ptr Pointer to location 1116:Drivers/CMSIS/Include/cmsis_gcc.h **** \return 0 Function succeeded 1117:Drivers/CMSIS/Include/cmsis_gcc.h **** \return 1 Function failed 1118:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 1119:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) 5161 .loc 8 1119 31 view .LVU1668 5162 .LBB535: 1120:Drivers/CMSIS/Include/cmsis_gcc.h **** { 1121:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 5163 .loc 8 1121 4 view .LVU1669 1122:Drivers/CMSIS/Include/cmsis_gcc.h **** 1123:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 5164 .loc 8 1123 4 view .LVU1670 5165 00f6 0832 adds r2, r2, #8 5166 .syntax unified 5167 @ 1123 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 5168 00f8 42E80031 strex r1, r3, [r2] 5169 @ 0 "" 2 5170 .LVL418: 1124:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 5171 .loc 8 1124 4 view .LVU1671 5172 .loc 8 1124 4 is_stmt 0 view .LVU1672 5173 .thumb 5174 .syntax unified 5175 .LBE535: 5176 .LBE534: 5177 .loc 7 3558 3 discriminator 1 view .LVU1673 5178 00fc 0029 cmp r1, #0 5179 00fe F3D1 bne .L216 5180 .LBE531: 5181 .loc 7 3558 3 is_stmt 1 discriminator 2 view .LVU1674 5182 .LVL419: ARM GAS /tmp/ccYgfTud.s page 453 5183 .loc 7 3558 3 is_stmt 0 discriminator 2 view .LVU1675 5184 .LBE530: 2071:Src/main.c **** LL_DMA_EnableIT_TE(DMA2, LL_DMA_STREAM_7); 5185 .loc 1 2071 3 is_stmt 1 view .LVU1676 5186 .LBB536: 5187 .LBI536: 2368:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 2369:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 2370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 2371:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Clear Stream 0 direct mode error flag. 2372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LIFCR CDMEIF0 LL_DMA_ClearFlag_DME0 2373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 2374:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 2375:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 2376:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_DME0(DMA_TypeDef *DMAx) 2377:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 2378:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CDMEIF0); 2379:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 2380:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 2381:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 2382:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Clear Stream 1 direct mode error flag. 2383:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LIFCR CDMEIF1 LL_DMA_ClearFlag_DME1 2384:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 2385:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 2386:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 2387:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_DME1(DMA_TypeDef *DMAx) 2388:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 2389:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CDMEIF1); 2390:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 2391:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 2392:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 2393:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Clear Stream 2 direct mode error flag. 2394:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LIFCR CDMEIF2 LL_DMA_ClearFlag_DME2 2395:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 2396:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 2397:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 2398:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_DME2(DMA_TypeDef *DMAx) 2399:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 2400:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CDMEIF2); 2401:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 2402:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 2403:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 2404:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Clear Stream 3 direct mode error flag. 2405:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LIFCR CDMEIF3 LL_DMA_ClearFlag_DME3 2406:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 2407:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 2408:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 2409:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_DME3(DMA_TypeDef *DMAx) 2410:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 2411:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CDMEIF3); 2412:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 2413:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 2414:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 2415:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Clear Stream 4 direct mode error flag. 2416:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HIFCR CDMEIF4 LL_DMA_ClearFlag_DME4 2417:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 2418:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None ARM GAS /tmp/ccYgfTud.s page 454 2419:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 2420:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_DME4(DMA_TypeDef *DMAx) 2421:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 2422:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CDMEIF4); 2423:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 2424:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 2425:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 2426:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Clear Stream 5 direct mode error flag. 2427:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HIFCR CDMEIF5 LL_DMA_ClearFlag_DME5 2428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 2429:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 2430:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 2431:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_DME5(DMA_TypeDef *DMAx) 2432:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 2433:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CDMEIF5); 2434:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 2435:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 2436:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 2437:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Clear Stream 6 direct mode error flag. 2438:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HIFCR CDMEIF6 LL_DMA_ClearFlag_DME6 2439:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 2440:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 2441:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 2442:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_DME6(DMA_TypeDef *DMAx) 2443:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 2444:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CDMEIF6); 2445:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 2446:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 2447:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 2448:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Clear Stream 7 direct mode error flag. 2449:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HIFCR CDMEIF7 LL_DMA_ClearFlag_DME7 2450:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 2451:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 2452:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 2453:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_DME7(DMA_TypeDef *DMAx) 2454:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 2455:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CDMEIF7); 2456:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 2457:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 2458:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 2459:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Clear Stream 0 FIFO error flag. 2460:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LIFCR CFEIF0 LL_DMA_ClearFlag_FE0 2461:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 2462:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 2463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 2464:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_FE0(DMA_TypeDef *DMAx) 2465:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 2466:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CFEIF0); 2467:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 2468:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 2469:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 2470:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Clear Stream 1 FIFO error flag. 2471:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LIFCR CFEIF1 LL_DMA_ClearFlag_FE1 2472:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 2473:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 2474:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 2475:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_FE1(DMA_TypeDef *DMAx) ARM GAS /tmp/ccYgfTud.s page 455 2476:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 2477:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CFEIF1); 2478:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 2479:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 2480:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 2481:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Clear Stream 2 FIFO error flag. 2482:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LIFCR CFEIF2 LL_DMA_ClearFlag_FE2 2483:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 2484:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 2485:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 2486:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_FE2(DMA_TypeDef *DMAx) 2487:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 2488:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CFEIF2); 2489:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 2490:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 2491:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 2492:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Clear Stream 3 FIFO error flag. 2493:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LIFCR CFEIF3 LL_DMA_ClearFlag_FE3 2494:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 2495:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 2496:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 2497:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_FE3(DMA_TypeDef *DMAx) 2498:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 2499:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CFEIF3); 2500:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 2501:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 2502:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 2503:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Clear Stream 4 FIFO error flag. 2504:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HIFCR CFEIF4 LL_DMA_ClearFlag_FE4 2505:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 2506:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 2507:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 2508:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_FE4(DMA_TypeDef *DMAx) 2509:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 2510:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CFEIF4); 2511:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 2512:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 2513:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 2514:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Clear Stream 5 FIFO error flag. 2515:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HIFCR CFEIF5 LL_DMA_ClearFlag_FE5 2516:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 2517:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 2518:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 2519:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_FE5(DMA_TypeDef *DMAx) 2520:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 2521:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CFEIF5); 2522:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 2523:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 2524:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 2525:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Clear Stream 6 FIFO error flag. 2526:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HIFCR CFEIF6 LL_DMA_ClearFlag_FE6 2527:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 2528:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 2529:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 2530:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_FE6(DMA_TypeDef *DMAx) 2531:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 2532:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CFEIF6); ARM GAS /tmp/ccYgfTud.s page 456 2533:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 2534:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 2535:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 2536:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Clear Stream 7 FIFO error flag. 2537:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HIFCR CFEIF7 LL_DMA_ClearFlag_FE7 2538:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 2539:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 2540:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 2541:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_FE7(DMA_TypeDef *DMAx) 2542:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 2543:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CFEIF7); 2544:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 2545:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 2546:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 2547:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @} 2548:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 2549:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 2550:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_EF_IT_Management IT_Management 2551:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @{ 2552:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 2553:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 2554:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 2555:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Enable Half transfer interrupt. 2556:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR HTIE LL_DMA_EnableIT_HT 2557:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 2558:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: 2559:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 2560:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 2561:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 2562:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 2563:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 2564:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 2565:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 2566:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 2567:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 2568:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 2569:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_EnableIT_HT(DMA_TypeDef *DMAx, uint32_t Stream) 2570:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 2571:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA 2572:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 2573:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 2574:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 2575:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Enable Transfer error interrupt. 2576:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR TEIE LL_DMA_EnableIT_TE 2577:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 2578:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: 2579:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 2580:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 2581:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 2582:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 2583:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 2584:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 2585:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 2586:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 2587:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 2588:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 2589:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_EnableIT_TE(DMA_TypeDef *DMAx, uint32_t Stream) ARM GAS /tmp/ccYgfTud.s page 457 2590:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 2591:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA 2592:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 2593:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 2594:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 2595:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Enable Transfer complete interrupt. 2596:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR TCIE LL_DMA_EnableIT_TC 2597:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 2598:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: 2599:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 2600:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 2601:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 2602:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 2603:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 2604:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 2605:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 2606:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 2607:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 2608:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 2609:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_EnableIT_TC(DMA_TypeDef *DMAx, uint32_t Stream) 5188 .loc 6 2609 22 view .LVU1677 5189 .LBB537: 2610:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 2611:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA 5190 .loc 6 2611 3 view .LVU1678 5191 0100 744B ldr r3, .L225+80 5192 0102 D3F8B820 ldr r2, [r3, #184] 5193 0106 42F01002 orr r2, r2, #16 5194 010a C3F8B820 str r2, [r3, #184] 5195 .LVL420: 5196 .loc 6 2611 3 is_stmt 0 view .LVU1679 5197 .LBE537: 5198 .LBE536: 2072:Src/main.c **** LL_DMA_ClearFlag_TC7(DMA2); 5199 .loc 1 2072 3 is_stmt 1 view .LVU1680 5200 .LBB538: 5201 .LBI538: 2589:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 5202 .loc 6 2589 22 view .LVU1681 5203 .LBB539: 2591:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 5204 .loc 6 2591 3 view .LVU1682 5205 010e D3F8B820 ldr r2, [r3, #184] 5206 0112 42F00402 orr r2, r2, #4 5207 0116 C3F8B820 str r2, [r3, #184] 5208 .LVL421: 2591:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 5209 .loc 6 2591 3 is_stmt 0 view .LVU1683 5210 .LBE539: 5211 .LBE538: 2073:Src/main.c **** LL_DMA_ClearFlag_TE7(DMA2); 5212 .loc 1 2073 3 is_stmt 1 view .LVU1684 5213 .LBB540: 5214 .LBI540: 2277:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 5215 .loc 6 2277 22 view .LVU1685 5216 .LBB541: ARM GAS /tmp/ccYgfTud.s page 458 2279:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 5217 .loc 6 2279 3 view .LVU1686 5218 011a 4FF00062 mov r2, #134217728 5219 011e DA60 str r2, [r3, #12] 5220 .LVL422: 2279:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 5221 .loc 6 2279 3 is_stmt 0 view .LVU1687 5222 .LBE541: 5223 .LBE540: 2074:Src/main.c **** LL_DMA_ConfigAddresses(DMA2, LL_DMA_STREAM_7, (uint32_t)&UART_DATA, LL_USART_DMA_GetRegAddr(USART 5224 .loc 1 2074 3 is_stmt 1 view .LVU1688 5225 .LBB542: 5226 .LBI542: 2365:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 5227 .loc 6 2365 22 view .LVU1689 5228 .LBB543: 2367:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 5229 .loc 6 2367 3 view .LVU1690 5230 0120 4FF00072 mov r2, #33554432 5231 0124 DA60 str r2, [r3, #12] 5232 .LVL423: 2367:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 5233 .loc 6 2367 3 is_stmt 0 view .LVU1691 5234 .LBE543: 5235 .LBE542: 2075:Src/main.c **** 5236 .loc 1 2075 3 is_stmt 1 view .LVU1692 5237 0126 6C4A ldr r2, .L225+84 5238 .LVL424: 5239 .LBB544: 5240 .LBI544: 621:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 5241 .loc 6 621 26 view .LVU1693 5242 .LBB545: 623:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 5243 .loc 6 623 3 view .LVU1694 623:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 5244 .loc 6 623 11 is_stmt 0 view .LVU1695 5245 0128 D3F8B830 ldr r3, [r3, #184] 5246 012c 03F0C003 and r3, r3, #192 5247 .LVL425: 623:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 5248 .loc 6 623 11 view .LVU1696 5249 .LBE545: 5250 .LBE544: 5251 .LBB546: 5252 .LBI546: 1425:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 5253 .loc 6 1425 22 is_stmt 1 view .LVU1697 5254 .LBB547: 1428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 5255 .loc 6 1428 3 view .LVU1698 1428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 5256 .loc 6 1428 6 is_stmt 0 view .LVU1699 5257 0130 402B cmp r3, #64 5258 0132 7DD0 beq .L222 1436:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR ARM GAS /tmp/ccYgfTud.s page 459 5259 .loc 6 1436 5 is_stmt 1 view .LVU1700 5260 0134 674B ldr r3, .L225+80 5261 .LVL426: 1436:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR 5262 .loc 6 1436 5 is_stmt 0 view .LVU1701 5263 0136 C3F8C020 str r2, [r3, #192] 1437:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 5264 .loc 6 1437 5 is_stmt 1 view .LVU1702 5265 013a 684A ldr r2, .L225+88 5266 013c C3F8C420 str r2, [r3, #196] 5267 .L218: 5268 .LVL427: 1437:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 5269 .loc 6 1437 5 is_stmt 0 view .LVU1703 5270 .LBE547: 5271 .LBE546: 2080:Src/main.c **** SD_SLIDE = 0; 5272 .loc 1 2080 2 is_stmt 1 view .LVU1704 2080:Src/main.c **** SD_SLIDE = 0; 5273 .loc 1 2080 10 is_stmt 0 view .LVU1705 5274 0140 0024 movs r4, #0 5275 0142 674B ldr r3, .L225+92 5276 0144 1C60 str r4, [r3] 2081:Src/main.c **** //Reset all periphery 5277 .loc 1 2081 2 is_stmt 1 view .LVU1706 2081:Src/main.c **** //Reset all periphery 5278 .loc 1 2081 11 is_stmt 0 view .LVU1707 5279 0146 674B ldr r3, .L225+96 5280 0148 1C60 str r4, [r3] 2083:Src/main.c **** HAL_GPIO_WritePin(EN_5V2_GPIO_Port, EN_5V2_Pin, GPIO_PIN_RESET); 5281 .loc 1 2083 2 is_stmt 1 view .LVU1708 5282 014a 674F ldr r7, .L225+100 5283 014c 2246 mov r2, r4 5284 014e 0821 movs r1, #8 5285 0150 3846 mov r0, r7 5286 0152 FFF7FEFF bl HAL_GPIO_WritePin 5287 .LVL428: 2084:Src/main.c **** HAL_GPIO_WritePin(LD1_EN_GPIO_Port, LD1_EN_Pin, GPIO_PIN_RESET); 5288 .loc 1 2084 2 view .LVU1709 5289 0156 2246 mov r2, r4 5290 0158 0421 movs r1, #4 5291 015a 3846 mov r0, r7 5292 015c FFF7FEFF bl HAL_GPIO_WritePin 5293 .LVL429: 2085:Src/main.c **** HAL_GPIO_WritePin(LD2_EN_GPIO_Port, LD2_EN_Pin, GPIO_PIN_RESET); 5294 .loc 1 2085 2 view .LVU1710 5295 0160 DFF8A881 ldr r8, .L225+136 5296 0164 2246 mov r2, r4 5297 0166 4FF48071 mov r1, #256 5298 016a 4046 mov r0, r8 5299 016c FFF7FEFF bl HAL_GPIO_WritePin 5300 .LVL430: 2086:Src/main.c **** HAL_GPIO_WritePin(REF0_EN_GPIO_Port, REF0_EN_Pin, GPIO_PIN_RESET); 5301 .loc 1 2086 2 view .LVU1711 5302 0170 2246 mov r2, r4 5303 0172 1021 movs r1, #16 5304 0174 3846 mov r0, r7 ARM GAS /tmp/ccYgfTud.s page 460 5305 0176 FFF7FEFF bl HAL_GPIO_WritePin 5306 .LVL431: 2087:Src/main.c **** HAL_GPIO_WritePin(REF2_ON_GPIO_Port, REF2_ON_Pin, GPIO_PIN_RESET); 5307 .loc 1 2087 2 view .LVU1712 5308 017a 5C4E ldr r6, .L225+104 5309 017c 2246 mov r2, r4 5310 017e 4FF48061 mov r1, #1024 5311 0182 3046 mov r0, r6 5312 0184 FFF7FEFF bl HAL_GPIO_WritePin 5313 .LVL432: 2088:Src/main.c **** HAL_GPIO_WritePin(TECEN1_GPIO_Port, TECEN1_Pin, GPIO_PIN_RESET); 5314 .loc 1 2088 2 view .LVU1713 5315 0188 594D ldr r5, .L225+108 5316 018a 2246 mov r2, r4 5317 018c 0821 movs r1, #8 5318 018e 2846 mov r0, r5 5319 0190 FFF7FEFF bl HAL_GPIO_WritePin 5320 .LVL433: 2089:Src/main.c **** HAL_GPIO_WritePin(TECEN2_GPIO_Port, TECEN2_Pin, GPIO_PIN_RESET); 5321 .loc 1 2089 2 view .LVU1714 5322 0194 2246 mov r2, r4 5323 0196 0121 movs r1, #1 5324 0198 2846 mov r0, r5 5325 019a FFF7FEFF bl HAL_GPIO_WritePin 5326 .LVL434: 2090:Src/main.c **** HAL_GPIO_WritePin(TEC1_PD_GPIO_Port, TEC1_PD_Pin, GPIO_PIN_RESET); 5327 .loc 1 2090 2 view .LVU1715 5328 019e 2246 mov r2, r4 5329 01a0 0221 movs r1, #2 5330 01a2 2846 mov r0, r5 5331 01a4 FFF7FEFF bl HAL_GPIO_WritePin 5332 .LVL435: 2091:Src/main.c **** HAL_GPIO_WritePin(TEC2_PD_GPIO_Port, TEC2_PD_Pin, GPIO_PIN_RESET); 5333 .loc 1 2091 2 view .LVU1716 5334 01a8 2246 mov r2, r4 5335 01aa 4FF40061 mov r1, #2048 5336 01ae 3046 mov r0, r6 5337 01b0 FFF7FEFF bl HAL_GPIO_WritePin 5338 .LVL436: 2092:Src/main.c **** // for (uint16_t i = 0; i < SD_Length; i++) 5339 .loc 1 2092 2 view .LVU1717 5340 01b4 2246 mov r2, r4 5341 01b6 2021 movs r1, #32 5342 01b8 3846 mov r0, r7 5343 01ba FFF7FEFF bl HAL_GPIO_WritePin 5344 .LVL437: 2102:Src/main.c **** HAL_GPIO_WritePin(ADC_MPD2_CS_GPIO_Port, ADC_MPD2_CS_Pin, GPIO_PIN_SET);//Enable SPI for MPhD2 ADC 5345 .loc 1 2102 2 view .LVU1718 5346 01be 07F50067 add r7, r7, #2048 5347 01c2 0122 movs r2, #1 5348 01c4 4FF48061 mov r1, #1024 5349 01c8 3846 mov r0, r7 5350 01ca FFF7FEFF bl HAL_GPIO_WritePin 5351 .LVL438: 2103:Src/main.c **** HAL_GPIO_WritePin(SPI4_CNV_GPIO_Port, SPI4_CNV_Pin, GPIO_PIN_SET); 5352 .loc 1 2103 2 view .LVU1719 5353 01ce 494C ldr r4, .L225+112 ARM GAS /tmp/ccYgfTud.s page 461 5354 01d0 0122 movs r2, #1 5355 01d2 4021 movs r1, #64 5356 01d4 2046 mov r0, r4 5357 01d6 FFF7FEFF bl HAL_GPIO_WritePin 5358 .LVL439: 2104:Src/main.c **** HAL_GPIO_WritePin(SPI5_CNV_GPIO_Port, SPI4_CNV_Pin, GPIO_PIN_SET); 5359 .loc 1 2104 2 view .LVU1720 5360 01da 0122 movs r2, #1 5361 01dc 4FF48041 mov r1, #16384 5362 01e0 3846 mov r0, r7 5363 01e2 FFF7FEFF bl HAL_GPIO_WritePin 5364 .LVL440: 2105:Src/main.c **** HAL_GPIO_WritePin(DAC_LD1_CS_GPIO_Port, DAC_LD1_CS_Pin, GPIO_PIN_SET);//End operation with LDAC1 5365 .loc 1 2105 2 view .LVU1721 5366 01e6 0122 movs r2, #1 5367 01e8 4FF48041 mov r1, #16384 5368 01ec 2046 mov r0, r4 5369 01ee FFF7FEFF bl HAL_GPIO_WritePin 5370 .LVL441: 2106:Src/main.c **** HAL_GPIO_WritePin(DAC_LD2_CS_GPIO_Port, DAC_LD2_CS_Pin, GPIO_PIN_SET);//End operation with LDAC2 5371 .loc 1 2106 2 view .LVU1722 5372 01f2 0122 movs r2, #1 5373 01f4 4FF48041 mov r1, #16384 5374 01f8 3046 mov r0, r6 5375 01fa FFF7FEFF bl HAL_GPIO_WritePin 5376 .LVL442: 2107:Src/main.c **** HAL_GPIO_WritePin(DAC_TEC1_CS_GPIO_Port, DAC_TEC1_CS_Pin, GPIO_PIN_SET);//End operation with TEC1 5377 .loc 1 2107 2 view .LVU1723 5378 01fe 0122 movs r2, #1 5379 0200 4021 movs r1, #64 5380 0202 2846 mov r0, r5 5381 0204 FFF7FEFF bl HAL_GPIO_WritePin 5382 .LVL443: 2108:Src/main.c **** HAL_GPIO_WritePin(DAC_TEC2_CS_GPIO_Port, DAC_TEC2_CS_Pin, GPIO_PIN_SET);//End operation with TEC2 5383 .loc 1 2108 2 view .LVU1724 5384 0208 0122 movs r2, #1 5385 020a 4FF48051 mov r1, #4096 5386 020e 3046 mov r0, r6 5387 0210 FFF7FEFF bl HAL_GPIO_WritePin 5388 .LVL444: 2109:Src/main.c **** 5389 .loc 1 2109 2 view .LVU1725 5390 0214 0122 movs r2, #1 5391 0216 1021 movs r1, #16 5392 0218 2846 mov r0, r5 5393 021a FFF7FEFF bl HAL_GPIO_WritePin 5394 .LVL445: 2113:Src/main.c **** { 5395 .loc 1 2113 2 view .LVU1726 2113:Src/main.c **** { 5396 .loc 1 2113 6 is_stmt 0 view .LVU1727 5397 021e 0121 movs r1, #1 5398 0220 4046 mov r0, r8 5399 0222 FFF7FEFF bl HAL_GPIO_ReadPin 5400 .LVL446: 2113:Src/main.c **** { 5401 .loc 1 2113 5 discriminator 1 view .LVU1728 ARM GAS /tmp/ccYgfTud.s page 462 5402 0226 50B1 cbz r0, .L223 5403 .L219: 2144:Src/main.c **** } 5404 .loc 1 2144 2 is_stmt 1 view .LVU1729 5405 0228 FFF7FEFF bl AD9102_Init 5406 .LVL447: 2145:Src/main.c **** static void Decode_uart(uint16_t *Command, LDx_SetupTypeDef *LD1_curr_setup, LDx_SetupTypeDef *LD2_ 5407 .loc 1 2145 1 is_stmt 0 view .LVU1730 5408 022c BDE8F081 pop {r4, r5, r6, r7, r8, pc} 5409 .LVL448: 5410 .L222: 5411 .LBB549: 5412 .LBB548: 1430:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR, 5413 .loc 6 1430 5 is_stmt 1 view .LVU1731 5414 0230 284B ldr r3, .L225+80 5415 .LVL449: 1430:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR, 5416 .loc 6 1430 5 is_stmt 0 view .LVU1732 5417 0232 C3F8C420 str r2, [r3, #196] 1431:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 5418 .loc 6 1431 5 is_stmt 1 view .LVU1733 5419 0236 294A ldr r2, .L225+88 5420 0238 C3F8C020 str r2, [r3, #192] 5421 023c 80E7 b .L218 5422 .LVL450: 5423 .L223: 1431:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 5424 .loc 6 1431 5 is_stmt 0 view .LVU1734 5425 .LBE548: 5426 .LBE549: 2116:Src/main.c **** { 5427 .loc 1 2116 3 is_stmt 1 view .LVU1735 2116:Src/main.c **** { 5428 .loc 1 2116 7 is_stmt 0 view .LVU1736 5429 023e 4FF48071 mov r1, #256 5430 0242 2846 mov r0, r5 5431 0244 FFF7FEFF bl HAL_GPIO_ReadPin 5432 .LVL451: 2116:Src/main.c **** { 5433 .loc 1 2116 6 discriminator 1 view .LVU1737 5434 0248 0028 cmp r0, #0 5435 024a EDD1 bne .L219 2119:Src/main.c **** if (test == 0) //0 - suc 5436 .loc 1 2119 4 is_stmt 1 view .LVU1738 2119:Src/main.c **** if (test == 0) //0 - suc 5437 .loc 1 2119 11 is_stmt 0 view .LVU1739 5438 024c 2A48 ldr r0, .L225+116 5439 024e FFF7FEFF bl Mount_SD 5440 .LVL452: 2119:Src/main.c **** if (test == 0) //0 - suc 5441 .loc 1 2119 9 discriminator 1 view .LVU1740 5442 0252 2A4B ldr r3, .L225+120 5443 0254 1860 str r0, [r3] 2120:Src/main.c **** { 5444 .loc 1 2120 4 is_stmt 1 view .LVU1741 2120:Src/main.c **** { ARM GAS /tmp/ccYgfTud.s page 463 5445 .loc 1 2120 7 is_stmt 0 view .LVU1742 5446 0256 18B1 cbz r0, .L224 5447 .L220: 2132:Src/main.c **** } 5448 .loc 1 2132 4 is_stmt 1 view .LVU1743 2132:Src/main.c **** } 5449 .loc 1 2132 14 is_stmt 0 view .LVU1744 5450 0258 294B ldr r3, .L225+124 5451 025a 0122 movs r2, #1 5452 025c 1A70 strb r2, [r3] 5453 025e E3E7 b .L219 5454 .L224: 2123:Src/main.c **** test = Unmount_SD("/"); // 0 - succ 5455 .loc 1 2123 5 is_stmt 1 view .LVU1745 2123:Src/main.c **** test = Unmount_SD("/"); // 0 - succ 5456 .loc 1 2123 12 is_stmt 0 view .LVU1746 5457 0260 1E23 movs r3, #30 5458 0262 1A46 mov r2, r3 5459 0264 2749 ldr r1, .L225+128 5460 0266 2848 ldr r0, .L225+132 5461 0268 FFF7FEFF bl Seek_Read_File 5462 .LVL453: 2123:Src/main.c **** test = Unmount_SD("/"); // 0 - succ 5463 .loc 1 2123 10 discriminator 1 view .LVU1747 5464 026c 234C ldr r4, .L225+120 5465 026e 2060 str r0, [r4] 2124:Src/main.c **** UART_rec_incr = 0; 5466 .loc 1 2124 5 is_stmt 1 view .LVU1748 2124:Src/main.c **** UART_rec_incr = 0; 5467 .loc 1 2124 12 is_stmt 0 view .LVU1749 5468 0270 2148 ldr r0, .L225+116 5469 0272 FFF7FEFF bl Unmount_SD 5470 .LVL454: 2124:Src/main.c **** UART_rec_incr = 0; 5471 .loc 1 2124 10 discriminator 1 view .LVU1750 5472 0276 2060 str r0, [r4] 2125:Src/main.c **** flg_tmt = 0;//Reset the timeout flag 5473 .loc 1 2125 5 is_stmt 1 view .LVU1751 2125:Src/main.c **** flg_tmt = 0;//Reset the timeout flag 5474 .loc 1 2125 19 is_stmt 0 view .LVU1752 5475 0278 0023 movs r3, #0 5476 027a 084A ldr r2, .L225+24 5477 027c 1380 strh r3, [r2] @ movhi 2126:Src/main.c **** } 5478 .loc 1 2126 5 is_stmt 1 view .LVU1753 2126:Src/main.c **** } 5479 .loc 1 2126 13 is_stmt 0 view .LVU1754 5480 027e 064A ldr r2, .L225+20 5481 0280 1370 strb r3, [r2] 5482 0282 E9E7 b .L220 5483 .L226: 5484 .align 2 5485 .L225: 5486 0284 00000000 .word TO6 5487 0288 00000000 .word TO7 5488 028c 00000000 .word TO7_before 5489 0290 00000000 .word TO6_before ARM GAS /tmp/ccYgfTud.s page 464 5490 0294 00000000 .word TO6_uart 5491 0298 00000000 .word flg_tmt 5492 029c 00000000 .word UART_rec_incr 5493 02a0 00000000 .word fgoto 5494 02a4 00000000 .word sizeoffile 5495 02a8 00000000 .word u_tx_flg 5496 02ac 00000000 .word u_rx_flg 5497 02b0 00000000 .word Long_Data 5498 02b4 00000000 .word Def_setup 5499 02b8 00000000 .word LD1_def_setup 5500 02bc 00000000 .word LD2_def_setup 5501 02c0 00000000 .word Curr_setup 5502 02c4 00000000 .word LD1_curr_setup 5503 02c8 00000000 .word LD2_curr_setup 5504 02cc 00100040 .word 1073745920 5505 02d0 00100140 .word 1073811456 5506 02d4 00640240 .word 1073898496 5507 02d8 00000000 .word UART_DATA 5508 02dc 28100140 .word 1073811496 5509 02e0 00000000 .word SD_SEEK 5510 02e4 00000000 .word SD_SLIDE 5511 02e8 00080240 .word 1073874944 5512 02ec 00040240 .word 1073873920 5513 02f0 00000240 .word 1073872896 5514 02f4 00140240 .word 1073878016 5515 02f8 00000000 .word .LC0 5516 02fc 00000000 .word test 5517 0300 00000000 .word CPU_state 5518 0304 00000000 .word COMMAND 5519 0308 04000000 .word .LC1 5520 030c 000C0240 .word 1073875968 5521 .cfi_endproc 5522 .LFE1207: 5524 .section .text.Get_ADC,"ax",%progbits 5525 .align 1 5526 .syntax unified 5527 .thumb 5528 .thumb_func 5530 Get_ADC: 5531 .LVL455: 5532 .LFB1219: 2785:Src/main.c **** uint16_t OUT; 5533 .loc 1 2785 1 is_stmt 1 view -0 5534 .cfi_startproc 5535 @ args = 0, pretend = 0, frame = 0 5536 @ frame_needed = 0, uses_anonymous_args = 0 2785:Src/main.c **** uint16_t OUT; 5537 .loc 1 2785 1 is_stmt 0 view .LVU1756 5538 0000 10B5 push {r4, lr} 5539 .LCFI54: 5540 .cfi_def_cfa_offset 8 5541 .cfi_offset 4, -8 5542 .cfi_offset 14, -4 5543 0002 0024 movs r4, #0 2786:Src/main.c **** switch (num) 5544 .loc 1 2786 2 is_stmt 1 view .LVU1757 2787:Src/main.c **** { ARM GAS /tmp/ccYgfTud.s page 465 5545 .loc 1 2787 2 view .LVU1758 5546 0004 0528 cmp r0, #5 5547 0006 2CD8 bhi .L236 5548 0008 DFE800F0 tbb [pc, r0] 5549 .L230: 5550 000c 03 .byte (.L235-.L230)/2 5551 000d 08 .byte (.L234-.L230)/2 5552 000e 12 .byte (.L233-.L230)/2 5553 000f 17 .byte (.L232-.L230)/2 5554 0010 1C .byte (.L231-.L230)/2 5555 0011 26 .byte (.L229-.L230)/2 5556 .p2align 1 5557 .L235: 2790:Src/main.c **** break; 5558 .loc 1 2790 5 view .LVU1759 5559 0012 1548 ldr r0, .L238 5560 .LVL456: 2790:Src/main.c **** break; 5561 .loc 1 2790 5 is_stmt 0 view .LVU1760 5562 0014 FFF7FEFF bl HAL_ADC_Start 5563 .LVL457: 2791:Src/main.c **** case 1: 5564 .loc 1 2791 4 is_stmt 1 view .LVU1761 5565 0018 2046 mov r0, r4 5566 .L228: 5567 .LVL458: 2810:Src/main.c **** } 5568 .loc 1 2810 2 view .LVU1762 2811:Src/main.c **** 5569 .loc 1 2811 1 is_stmt 0 view .LVU1763 5570 001a 10BD pop {r4, pc} 5571 .LVL459: 5572 .L234: 2793:Src/main.c **** OUT = HAL_ADC_GetValue(&hadc1); // Get value adc 5573 .loc 1 2793 5 is_stmt 1 view .LVU1764 5574 001c 124C ldr r4, .L238 5575 001e 6421 movs r1, #100 5576 0020 2046 mov r0, r4 5577 .LVL460: 2793:Src/main.c **** OUT = HAL_ADC_GetValue(&hadc1); // Get value adc 5578 .loc 1 2793 5 is_stmt 0 view .LVU1765 5579 0022 FFF7FEFF bl HAL_ADC_PollForConversion 5580 .LVL461: 2794:Src/main.c **** break; 5581 .loc 1 2794 9 is_stmt 1 view .LVU1766 2794:Src/main.c **** break; 5582 .loc 1 2794 15 is_stmt 0 view .LVU1767 5583 0026 2046 mov r0, r4 5584 0028 FFF7FEFF bl HAL_ADC_GetValue 5585 .LVL462: 2794:Src/main.c **** break; 5586 .loc 1 2794 13 discriminator 1 view .LVU1768 5587 002c 80B2 uxth r0, r0 5588 .LVL463: 2795:Src/main.c **** case 2: 5589 .loc 1 2795 4 is_stmt 1 view .LVU1769 5590 002e F4E7 b .L228 ARM GAS /tmp/ccYgfTud.s page 466 5591 .LVL464: 5592 .L233: 2797:Src/main.c **** break; 5593 .loc 1 2797 5 view .LVU1770 5594 0030 0D48 ldr r0, .L238 5595 .LVL465: 2797:Src/main.c **** break; 5596 .loc 1 2797 5 is_stmt 0 view .LVU1771 5597 0032 FFF7FEFF bl HAL_ADC_Stop 5598 .LVL466: 2798:Src/main.c **** case 3: 5599 .loc 1 2798 4 is_stmt 1 view .LVU1772 5600 0036 2046 mov r0, r4 5601 0038 EFE7 b .L228 5602 .LVL467: 5603 .L232: 2800:Src/main.c **** break; 5604 .loc 1 2800 5 view .LVU1773 5605 003a 0C48 ldr r0, .L238+4 5606 .LVL468: 2800:Src/main.c **** break; 5607 .loc 1 2800 5 is_stmt 0 view .LVU1774 5608 003c FFF7FEFF bl HAL_ADC_Start 5609 .LVL469: 2801:Src/main.c **** case 4: 5610 .loc 1 2801 4 is_stmt 1 view .LVU1775 5611 0040 2046 mov r0, r4 5612 0042 EAE7 b .L228 5613 .LVL470: 5614 .L231: 2803:Src/main.c **** OUT = HAL_ADC_GetValue(&hadc3); // Get value adc 5615 .loc 1 2803 5 view .LVU1776 5616 0044 094C ldr r4, .L238+4 5617 0046 6421 movs r1, #100 5618 0048 2046 mov r0, r4 5619 .LVL471: 2803:Src/main.c **** OUT = HAL_ADC_GetValue(&hadc3); // Get value adc 5620 .loc 1 2803 5 is_stmt 0 view .LVU1777 5621 004a FFF7FEFF bl HAL_ADC_PollForConversion 5622 .LVL472: 2804:Src/main.c **** break; 5623 .loc 1 2804 9 is_stmt 1 view .LVU1778 2804:Src/main.c **** break; 5624 .loc 1 2804 15 is_stmt 0 view .LVU1779 5625 004e 2046 mov r0, r4 5626 0050 FFF7FEFF bl HAL_ADC_GetValue 5627 .LVL473: 2804:Src/main.c **** break; 5628 .loc 1 2804 13 discriminator 1 view .LVU1780 5629 0054 80B2 uxth r0, r0 5630 .LVL474: 2805:Src/main.c **** case 5: 5631 .loc 1 2805 4 is_stmt 1 view .LVU1781 5632 0056 E0E7 b .L228 5633 .LVL475: 5634 .L229: 2807:Src/main.c **** break; ARM GAS /tmp/ccYgfTud.s page 467 5635 .loc 1 2807 9 view .LVU1782 5636 0058 0448 ldr r0, .L238+4 5637 .LVL476: 2807:Src/main.c **** break; 5638 .loc 1 2807 9 is_stmt 0 view .LVU1783 5639 005a FFF7FEFF bl HAL_ADC_Stop 5640 .LVL477: 2808:Src/main.c **** } 5641 .loc 1 2808 4 is_stmt 1 view .LVU1784 5642 005e 2046 mov r0, r4 5643 0060 DBE7 b .L228 5644 .LVL478: 5645 .L236: 2787:Src/main.c **** { 5646 .loc 1 2787 2 is_stmt 0 view .LVU1785 5647 0062 2046 mov r0, r4 5648 .LVL479: 2787:Src/main.c **** { 5649 .loc 1 2787 2 view .LVU1786 5650 0064 D9E7 b .L228 5651 .L239: 5652 0066 00BF .align 2 5653 .L238: 5654 0068 00000000 .word hadc1 5655 006c 00000000 .word hadc3 5656 .cfi_endproc 5657 .LFE1219: 5659 .section .text.Set_LTEC,"ax",%progbits 5660 .align 1 5661 .global Set_LTEC 5662 .syntax unified 5663 .thumb 5664 .thumb_func 5666 Set_LTEC: 5667 .LVL480: 5668 .LFB1217: 2605:Src/main.c **** uint32_t tmp32; 5669 .loc 1 2605 1 is_stmt 1 view -0 5670 .cfi_startproc 5671 @ args = 0, pretend = 0, frame = 0 5672 @ frame_needed = 0, uses_anonymous_args = 0 2606:Src/main.c **** 5673 .loc 1 2606 2 view .LVU1788 2610:Src/main.c **** { 5674 .loc 1 2610 2 view .LVU1789 2610:Src/main.c **** { 5675 .loc 1 2610 5 is_stmt 0 view .LVU1790 5676 0000 0328 cmp r0, #3 5677 0002 18BF it ne 5678 0004 0128 cmpne r0, #1 5679 0006 00F0A380 beq .L274 2605:Src/main.c **** uint32_t tmp32; 5680 .loc 1 2605 1 view .LVU1791 5681 000a 38B5 push {r3, r4, r5, lr} 5682 .LCFI55: 5683 .cfi_def_cfa_offset 16 5684 .cfi_offset 3, -16 ARM GAS /tmp/ccYgfTud.s page 468 5685 .cfi_offset 4, -12 5686 .cfi_offset 5, -8 5687 .cfi_offset 14, -4 5688 000c 0C46 mov r4, r1 2616:Src/main.c **** { 5689 .loc 1 2616 2 is_stmt 1 view .LVU1792 5690 000e 0138 subs r0, r0, #1 5691 .LVL481: 2616:Src/main.c **** { 5692 .loc 1 2616 2 is_stmt 0 view .LVU1793 5693 0010 0328 cmp r0, #3 5694 0012 23D8 bhi .L242 5695 0014 DFE800F0 tbb [pc, r0] 5696 .L244: 5697 0018 02 .byte (.L247-.L244)/2 5698 0019 3B .byte (.L246-.L244)/2 5699 001a 5B .byte (.L245-.L244)/2 5700 001b 7C .byte (.L243-.L244)/2 5701 .p2align 1 5702 .L247: 2619:Src/main.c **** //tmp32=0; 5703 .loc 1 2619 4 is_stmt 1 view .LVU1794 5704 001c 0022 movs r2, #0 5705 001e 4FF48041 mov r1, #16384 5706 .LVL482: 2619:Src/main.c **** //tmp32=0; 5707 .loc 1 2619 4 is_stmt 0 view .LVU1795 5708 0022 4C48 ldr r0, .L277 5709 .LVL483: 2619:Src/main.c **** //tmp32=0; 5710 .loc 1 2619 4 view .LVU1796 5711 0024 FFF7FEFF bl HAL_GPIO_WritePin 5712 .LVL484: 2622:Src/main.c **** while((!LL_SPI_IsActiveFlag_TXE(SPI2))&&(tmp32<=500)) {tmp32++;}//When trans. last data cycle wi 5713 .loc 1 2622 4 is_stmt 1 view .LVU1797 2623:Src/main.c **** LL_SPI_TransmitData16(SPI2, DATA);//Transmit word to Laser1 DAC 5714 .loc 1 2623 4 view .LVU1798 2622:Src/main.c **** while((!LL_SPI_IsActiveFlag_TXE(SPI2))&&(tmp32<=500)) {tmp32++;}//When trans. last data cycle wi 5715 .loc 1 2622 10 is_stmt 0 view .LVU1799 5716 0028 0022 movs r2, #0 5717 .LVL485: 5718 .L248: 2623:Src/main.c **** LL_SPI_TransmitData16(SPI2, DATA);//Transmit word to Laser1 DAC 5719 .loc 1 2623 42 is_stmt 1 discriminator 1 view .LVU1800 5720 .LBB550: 5721 .LBI550: 916:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 5722 .loc 4 916 26 view .LVU1801 5723 .LBB551: 918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 5724 .loc 4 918 3 view .LVU1802 918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 5725 .loc 4 918 12 is_stmt 0 view .LVU1803 5726 002a 4B4B ldr r3, .L277+4 5727 002c 9B68 ldr r3, [r3, #8] 918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 5728 .loc 4 918 66 view .LVU1804 ARM GAS /tmp/ccYgfTud.s page 469 5729 002e 13F0020F tst r3, #2 5730 0032 04D1 bne .L249 5731 .LVL486: 918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 5732 .loc 4 918 66 view .LVU1805 5733 .LBE551: 5734 .LBE550: 2623:Src/main.c **** LL_SPI_TransmitData16(SPI2, DATA);//Transmit word to Laser1 DAC 5735 .loc 1 2623 42 discriminator 2 view .LVU1806 5736 0034 B2F5FA7F cmp r2, #500 5737 0038 01D8 bhi .L249 2623:Src/main.c **** LL_SPI_TransmitData16(SPI2, DATA);//Transmit word to Laser1 DAC 5738 .loc 1 2623 59 is_stmt 1 discriminator 3 view .LVU1807 2623:Src/main.c **** LL_SPI_TransmitData16(SPI2, DATA);//Transmit word to Laser1 DAC 5739 .loc 1 2623 64 is_stmt 0 discriminator 3 view .LVU1808 5740 003a 0132 adds r2, r2, #1 5741 .LVL487: 2623:Src/main.c **** LL_SPI_TransmitData16(SPI2, DATA);//Transmit word to Laser1 DAC 5742 .loc 1 2623 64 discriminator 3 view .LVU1809 5743 003c F5E7 b .L248 5744 .L249: 2624:Src/main.c **** tmp32 = 0; 5745 .loc 1 2624 4 is_stmt 1 view .LVU1810 5746 .LVL488: 5747 .LBB552: 5748 .LBI552: 1373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 5749 .loc 4 1373 22 view .LVU1811 5750 .LBB553: 1376:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** *spidr = TxData; 5751 .loc 4 1376 3 view .LVU1812 5752 .loc 4 1377 3 view .LVU1813 5753 .loc 4 1377 10 is_stmt 0 view .LVU1814 5754 003e 464B ldr r3, .L277+4 5755 0040 9C81 strh r4, [r3, #12] @ movhi 5756 .LVL489: 5757 .loc 4 1377 10 view .LVU1815 5758 .LBE553: 5759 .LBE552: 2625:Src/main.c **** while((!LL_SPI_IsActiveFlag_RXNE(SPI2))&&(tmp32<=500)) {tmp32++;}//When trans. last data cycle w 5760 .loc 1 2625 4 is_stmt 1 view .LVU1816 2626:Src/main.c **** (void) SPI2->DR; 5761 .loc 1 2626 4 view .LVU1817 2625:Src/main.c **** while((!LL_SPI_IsActiveFlag_RXNE(SPI2))&&(tmp32<=500)) {tmp32++;}//When trans. last data cycle w 5762 .loc 1 2625 10 is_stmt 0 view .LVU1818 5763 0042 0022 movs r2, #0 5764 .LVL490: 5765 .L251: 2626:Src/main.c **** (void) SPI2->DR; 5766 .loc 1 2626 43 is_stmt 1 discriminator 1 view .LVU1819 5767 .LBB554: 5768 .LBI554: 905:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 5769 .loc 4 905 26 view .LVU1820 5770 .LBB555: 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 5771 .loc 4 907 3 view .LVU1821 ARM GAS /tmp/ccYgfTud.s page 470 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 5772 .loc 4 907 12 is_stmt 0 view .LVU1822 5773 0044 444B ldr r3, .L277+4 5774 0046 9B68 ldr r3, [r3, #8] 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 5775 .loc 4 907 68 view .LVU1823 5776 0048 13F0010F tst r3, #1 5777 004c 04D1 bne .L252 5778 .LVL491: 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 5779 .loc 4 907 68 view .LVU1824 5780 .LBE555: 5781 .LBE554: 2626:Src/main.c **** (void) SPI2->DR; 5782 .loc 1 2626 43 discriminator 2 view .LVU1825 5783 004e B2F5FA7F cmp r2, #500 5784 0052 01D8 bhi .L252 2626:Src/main.c **** (void) SPI2->DR; 5785 .loc 1 2626 60 is_stmt 1 discriminator 3 view .LVU1826 2626:Src/main.c **** (void) SPI2->DR; 5786 .loc 1 2626 65 is_stmt 0 discriminator 3 view .LVU1827 5787 0054 0132 adds r2, r2, #1 5788 .LVL492: 2626:Src/main.c **** (void) SPI2->DR; 5789 .loc 1 2626 65 discriminator 3 view .LVU1828 5790 0056 F5E7 b .L251 5791 .L252: 2627:Src/main.c **** break; 5792 .loc 1 2627 4 is_stmt 1 view .LVU1829 5793 0058 3F4B ldr r3, .L277+4 5794 005a DB68 ldr r3, [r3, #12] 2628:Src/main.c **** case 2: 5795 .loc 1 2628 3 view .LVU1830 5796 .LVL493: 5797 .L242: 2664:Src/main.c **** HAL_GPIO_WritePin(DAC_LD2_CS_GPIO_Port, DAC_LD2_CS_Pin, GPIO_PIN_SET);//End operation with LDAC2 5798 .loc 1 2664 2 view .LVU1831 5799 005c 3D4D ldr r5, .L277 5800 005e 0122 movs r2, #1 5801 0060 4FF48041 mov r1, #16384 5802 0064 2846 mov r0, r5 5803 0066 FFF7FEFF bl HAL_GPIO_WritePin 5804 .LVL494: 2665:Src/main.c **** HAL_GPIO_WritePin(DAC_TEC1_CS_GPIO_Port, DAC_TEC1_CS_Pin, GPIO_PIN_SET);//End operation with TEC1 5805 .loc 1 2665 2 view .LVU1832 5806 006a 3C4C ldr r4, .L277+8 5807 .LVL495: 2665:Src/main.c **** HAL_GPIO_WritePin(DAC_TEC1_CS_GPIO_Port, DAC_TEC1_CS_Pin, GPIO_PIN_SET);//End operation with TEC1 5808 .loc 1 2665 2 is_stmt 0 view .LVU1833 5809 006c 0122 movs r2, #1 5810 006e 4021 movs r1, #64 5811 0070 2046 mov r0, r4 5812 0072 FFF7FEFF bl HAL_GPIO_WritePin 5813 .LVL496: 2666:Src/main.c **** HAL_GPIO_WritePin(DAC_TEC2_CS_GPIO_Port, DAC_TEC2_CS_Pin, GPIO_PIN_SET);//End operation with TEC2 5814 .loc 1 2666 2 is_stmt 1 view .LVU1834 5815 0076 0122 movs r2, #1 ARM GAS /tmp/ccYgfTud.s page 471 5816 0078 4FF48051 mov r1, #4096 5817 007c 2846 mov r0, r5 5818 007e FFF7FEFF bl HAL_GPIO_WritePin 5819 .LVL497: 2667:Src/main.c **** } 5820 .loc 1 2667 2 view .LVU1835 5821 0082 0122 movs r2, #1 5822 0084 1021 movs r1, #16 5823 0086 2046 mov r0, r4 5824 0088 FFF7FEFF bl HAL_GPIO_WritePin 5825 .LVL498: 2668:Src/main.c **** static uint16_t MPhD_T(uint8_t num) 5826 .loc 1 2668 1 is_stmt 0 view .LVU1836 5827 008c 38BD pop {r3, r4, r5, pc} 5828 .LVL499: 5829 .L246: 2631:Src/main.c **** //tmp32=0; 5830 .loc 1 2631 4 is_stmt 1 view .LVU1837 5831 008e 0022 movs r2, #0 5832 0090 4021 movs r1, #64 5833 .LVL500: 2631:Src/main.c **** //tmp32=0; 5834 .loc 1 2631 4 is_stmt 0 view .LVU1838 5835 0092 3248 ldr r0, .L277+8 5836 0094 FFF7FEFF bl HAL_GPIO_WritePin 5837 .LVL501: 2634:Src/main.c **** while((!LL_SPI_IsActiveFlag_TXE(SPI6))&&(tmp32<=500)) {tmp32++;}//When trans. last data cycle wi 5838 .loc 1 2634 4 is_stmt 1 view .LVU1839 2635:Src/main.c **** LL_SPI_TransmitData16(SPI6, DATA);//Transmit word to Laser1 DAC 5839 .loc 1 2635 4 view .LVU1840 2634:Src/main.c **** while((!LL_SPI_IsActiveFlag_TXE(SPI6))&&(tmp32<=500)) {tmp32++;}//When trans. last data cycle wi 5840 .loc 1 2634 10 is_stmt 0 view .LVU1841 5841 0098 0022 movs r2, #0 5842 .LVL502: 5843 .L254: 2635:Src/main.c **** LL_SPI_TransmitData16(SPI6, DATA);//Transmit word to Laser1 DAC 5844 .loc 1 2635 42 is_stmt 1 discriminator 1 view .LVU1842 5845 .LBB556: 5846 .LBI556: 916:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 5847 .loc 4 916 26 view .LVU1843 5848 .LBB557: 918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 5849 .loc 4 918 3 view .LVU1844 918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 5850 .loc 4 918 12 is_stmt 0 view .LVU1845 5851 009a 314B ldr r3, .L277+12 5852 009c 9B68 ldr r3, [r3, #8] 918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 5853 .loc 4 918 66 view .LVU1846 5854 009e 13F0020F tst r3, #2 5855 00a2 04D1 bne .L255 5856 .LVL503: 918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 5857 .loc 4 918 66 view .LVU1847 5858 .LBE557: 5859 .LBE556: ARM GAS /tmp/ccYgfTud.s page 472 2635:Src/main.c **** LL_SPI_TransmitData16(SPI6, DATA);//Transmit word to Laser1 DAC 5860 .loc 1 2635 42 discriminator 2 view .LVU1848 5861 00a4 B2F5FA7F cmp r2, #500 5862 00a8 01D8 bhi .L255 2635:Src/main.c **** LL_SPI_TransmitData16(SPI6, DATA);//Transmit word to Laser1 DAC 5863 .loc 1 2635 59 is_stmt 1 discriminator 3 view .LVU1849 2635:Src/main.c **** LL_SPI_TransmitData16(SPI6, DATA);//Transmit word to Laser1 DAC 5864 .loc 1 2635 64 is_stmt 0 discriminator 3 view .LVU1850 5865 00aa 0132 adds r2, r2, #1 5866 .LVL504: 2635:Src/main.c **** LL_SPI_TransmitData16(SPI6, DATA);//Transmit word to Laser1 DAC 5867 .loc 1 2635 64 discriminator 3 view .LVU1851 5868 00ac F5E7 b .L254 5869 .L255: 2636:Src/main.c **** tmp32 = 0; 5870 .loc 1 2636 4 is_stmt 1 view .LVU1852 5871 .LVL505: 5872 .LBB558: 5873 .LBI558: 1373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 5874 .loc 4 1373 22 view .LVU1853 5875 .LBB559: 1376:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** *spidr = TxData; 5876 .loc 4 1376 3 view .LVU1854 5877 .loc 4 1377 3 view .LVU1855 5878 .loc 4 1377 10 is_stmt 0 view .LVU1856 5879 00ae 2C4B ldr r3, .L277+12 5880 00b0 9C81 strh r4, [r3, #12] @ movhi 5881 .LVL506: 5882 .loc 4 1377 10 view .LVU1857 5883 .LBE559: 5884 .LBE558: 2637:Src/main.c **** while((!LL_SPI_IsActiveFlag_RXNE(SPI6))&&(tmp32<=500)) {tmp32++;}//When trans. last data cycle w 5885 .loc 1 2637 4 is_stmt 1 view .LVU1858 2638:Src/main.c **** (void) SPI6->DR; 5886 .loc 1 2638 4 view .LVU1859 2637:Src/main.c **** while((!LL_SPI_IsActiveFlag_RXNE(SPI6))&&(tmp32<=500)) {tmp32++;}//When trans. last data cycle w 5887 .loc 1 2637 10 is_stmt 0 view .LVU1860 5888 00b2 0022 movs r2, #0 5889 .LVL507: 5890 .L257: 2638:Src/main.c **** (void) SPI6->DR; 5891 .loc 1 2638 43 is_stmt 1 discriminator 1 view .LVU1861 5892 .LBB560: 5893 .LBI560: 905:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 5894 .loc 4 905 26 view .LVU1862 5895 .LBB561: 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 5896 .loc 4 907 3 view .LVU1863 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 5897 .loc 4 907 12 is_stmt 0 view .LVU1864 5898 00b4 2A4B ldr r3, .L277+12 5899 00b6 9B68 ldr r3, [r3, #8] 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 5900 .loc 4 907 68 view .LVU1865 5901 00b8 13F0010F tst r3, #1 ARM GAS /tmp/ccYgfTud.s page 473 5902 00bc 04D1 bne .L258 5903 .LVL508: 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 5904 .loc 4 907 68 view .LVU1866 5905 .LBE561: 5906 .LBE560: 2638:Src/main.c **** (void) SPI6->DR; 5907 .loc 1 2638 43 discriminator 2 view .LVU1867 5908 00be B2F5FA7F cmp r2, #500 5909 00c2 01D8 bhi .L258 2638:Src/main.c **** (void) SPI6->DR; 5910 .loc 1 2638 60 is_stmt 1 discriminator 3 view .LVU1868 2638:Src/main.c **** (void) SPI6->DR; 5911 .loc 1 2638 65 is_stmt 0 discriminator 3 view .LVU1869 5912 00c4 0132 adds r2, r2, #1 5913 .LVL509: 2638:Src/main.c **** (void) SPI6->DR; 5914 .loc 1 2638 65 discriminator 3 view .LVU1870 5915 00c6 F5E7 b .L257 5916 .L258: 2639:Src/main.c **** break; 5917 .loc 1 2639 4 is_stmt 1 view .LVU1871 5918 00c8 254B ldr r3, .L277+12 5919 00ca DB68 ldr r3, [r3, #12] 2640:Src/main.c **** case 3: 5920 .loc 1 2640 3 view .LVU1872 5921 00cc C6E7 b .L242 5922 .LVL510: 5923 .L245: 2642:Src/main.c **** //tmp32=0; 5924 .loc 1 2642 4 view .LVU1873 5925 00ce 0022 movs r2, #0 5926 00d0 4FF48051 mov r1, #4096 5927 .LVL511: 2642:Src/main.c **** //tmp32=0; 5928 .loc 1 2642 4 is_stmt 0 view .LVU1874 5929 00d4 1F48 ldr r0, .L277 5930 00d6 FFF7FEFF bl HAL_GPIO_WritePin 5931 .LVL512: 2645:Src/main.c **** while((!LL_SPI_IsActiveFlag_TXE(SPI2))&&(tmp32<=500)) {tmp32++;}//When trans. last data cycle wi 5932 .loc 1 2645 4 is_stmt 1 view .LVU1875 2646:Src/main.c **** LL_SPI_TransmitData16(SPI2, DATA);//Transmit word to Laser1 DAC 5933 .loc 1 2646 4 view .LVU1876 2645:Src/main.c **** while((!LL_SPI_IsActiveFlag_TXE(SPI2))&&(tmp32<=500)) {tmp32++;}//When trans. last data cycle wi 5934 .loc 1 2645 10 is_stmt 0 view .LVU1877 5935 00da 0022 movs r2, #0 5936 .LVL513: 5937 .L260: 2646:Src/main.c **** LL_SPI_TransmitData16(SPI2, DATA);//Transmit word to Laser1 DAC 5938 .loc 1 2646 42 is_stmt 1 discriminator 1 view .LVU1878 5939 .LBB562: 5940 .LBI562: 916:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 5941 .loc 4 916 26 view .LVU1879 5942 .LBB563: 918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 5943 .loc 4 918 3 view .LVU1880 ARM GAS /tmp/ccYgfTud.s page 474 918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 5944 .loc 4 918 12 is_stmt 0 view .LVU1881 5945 00dc 1E4B ldr r3, .L277+4 5946 00de 9B68 ldr r3, [r3, #8] 918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 5947 .loc 4 918 66 view .LVU1882 5948 00e0 13F0020F tst r3, #2 5949 00e4 04D1 bne .L261 5950 .LVL514: 918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 5951 .loc 4 918 66 view .LVU1883 5952 .LBE563: 5953 .LBE562: 2646:Src/main.c **** LL_SPI_TransmitData16(SPI2, DATA);//Transmit word to Laser1 DAC 5954 .loc 1 2646 42 discriminator 2 view .LVU1884 5955 00e6 B2F5FA7F cmp r2, #500 5956 00ea 01D8 bhi .L261 2646:Src/main.c **** LL_SPI_TransmitData16(SPI2, DATA);//Transmit word to Laser1 DAC 5957 .loc 1 2646 59 is_stmt 1 discriminator 3 view .LVU1885 2646:Src/main.c **** LL_SPI_TransmitData16(SPI2, DATA);//Transmit word to Laser1 DAC 5958 .loc 1 2646 64 is_stmt 0 discriminator 3 view .LVU1886 5959 00ec 0132 adds r2, r2, #1 5960 .LVL515: 2646:Src/main.c **** LL_SPI_TransmitData16(SPI2, DATA);//Transmit word to Laser1 DAC 5961 .loc 1 2646 64 discriminator 3 view .LVU1887 5962 00ee F5E7 b .L260 5963 .L261: 2647:Src/main.c **** tmp32 = 0; 5964 .loc 1 2647 4 is_stmt 1 view .LVU1888 5965 .LVL516: 5966 .LBB564: 5967 .LBI564: 1373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 5968 .loc 4 1373 22 view .LVU1889 5969 .LBB565: 1376:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** *spidr = TxData; 5970 .loc 4 1376 3 view .LVU1890 5971 .loc 4 1377 3 view .LVU1891 5972 .loc 4 1377 10 is_stmt 0 view .LVU1892 5973 00f0 194B ldr r3, .L277+4 5974 00f2 9C81 strh r4, [r3, #12] @ movhi 5975 .LVL517: 5976 .loc 4 1377 10 view .LVU1893 5977 .LBE565: 5978 .LBE564: 2648:Src/main.c **** while((!LL_SPI_IsActiveFlag_RXNE(SPI2))&&(tmp32<=500)) {tmp32++;}//When trans. last data cycle w 5979 .loc 1 2648 4 is_stmt 1 view .LVU1894 2649:Src/main.c **** (void) SPI2->DR; 5980 .loc 1 2649 4 view .LVU1895 2648:Src/main.c **** while((!LL_SPI_IsActiveFlag_RXNE(SPI2))&&(tmp32<=500)) {tmp32++;}//When trans. last data cycle w 5981 .loc 1 2648 10 is_stmt 0 view .LVU1896 5982 00f4 0022 movs r2, #0 5983 .LVL518: 5984 .L263: 2649:Src/main.c **** (void) SPI2->DR; 5985 .loc 1 2649 43 is_stmt 1 discriminator 1 view .LVU1897 5986 .LBB566: ARM GAS /tmp/ccYgfTud.s page 475 5987 .LBI566: 905:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 5988 .loc 4 905 26 view .LVU1898 5989 .LBB567: 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 5990 .loc 4 907 3 view .LVU1899 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 5991 .loc 4 907 12 is_stmt 0 view .LVU1900 5992 00f6 184B ldr r3, .L277+4 5993 00f8 9B68 ldr r3, [r3, #8] 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 5994 .loc 4 907 68 view .LVU1901 5995 00fa 13F0010F tst r3, #1 5996 00fe 04D1 bne .L264 5997 .LVL519: 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 5998 .loc 4 907 68 view .LVU1902 5999 .LBE567: 6000 .LBE566: 2649:Src/main.c **** (void) SPI2->DR; 6001 .loc 1 2649 43 discriminator 2 view .LVU1903 6002 0100 B2F5FA7F cmp r2, #500 6003 0104 01D8 bhi .L264 2649:Src/main.c **** (void) SPI2->DR; 6004 .loc 1 2649 60 is_stmt 1 discriminator 3 view .LVU1904 2649:Src/main.c **** (void) SPI2->DR; 6005 .loc 1 2649 65 is_stmt 0 discriminator 3 view .LVU1905 6006 0106 0132 adds r2, r2, #1 6007 .LVL520: 2649:Src/main.c **** (void) SPI2->DR; 6008 .loc 1 2649 65 discriminator 3 view .LVU1906 6009 0108 F5E7 b .L263 6010 .L264: 2650:Src/main.c **** break; 6011 .loc 1 2650 4 is_stmt 1 view .LVU1907 6012 010a 134B ldr r3, .L277+4 6013 010c DB68 ldr r3, [r3, #12] 2651:Src/main.c **** case 4: 6014 .loc 1 2651 3 view .LVU1908 6015 010e A5E7 b .L242 6016 .LVL521: 6017 .L243: 2653:Src/main.c **** //tmp32=0; 6018 .loc 1 2653 4 view .LVU1909 6019 0110 0022 movs r2, #0 6020 0112 1021 movs r1, #16 6021 .LVL522: 2653:Src/main.c **** //tmp32=0; 6022 .loc 1 2653 4 is_stmt 0 view .LVU1910 6023 0114 1148 ldr r0, .L277+8 6024 0116 FFF7FEFF bl HAL_GPIO_WritePin 6025 .LVL523: 2656:Src/main.c **** while((!LL_SPI_IsActiveFlag_TXE(SPI6))&&(tmp32<=500)) {tmp32++;}//When trans. last data cycle wi 6026 .loc 1 2656 4 is_stmt 1 view .LVU1911 2657:Src/main.c **** LL_SPI_TransmitData16(SPI6, DATA);//Transmit word to Laser1 DAC 6027 .loc 1 2657 4 view .LVU1912 2656:Src/main.c **** while((!LL_SPI_IsActiveFlag_TXE(SPI6))&&(tmp32<=500)) {tmp32++;}//When trans. last data cycle wi ARM GAS /tmp/ccYgfTud.s page 476 6028 .loc 1 2656 10 is_stmt 0 view .LVU1913 6029 011a 0022 movs r2, #0 6030 .LVL524: 6031 .L266: 2657:Src/main.c **** LL_SPI_TransmitData16(SPI6, DATA);//Transmit word to Laser1 DAC 6032 .loc 1 2657 42 is_stmt 1 discriminator 1 view .LVU1914 6033 .LBB568: 6034 .LBI568: 916:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 6035 .loc 4 916 26 view .LVU1915 6036 .LBB569: 918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 6037 .loc 4 918 3 view .LVU1916 918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 6038 .loc 4 918 12 is_stmt 0 view .LVU1917 6039 011c 104B ldr r3, .L277+12 6040 011e 9B68 ldr r3, [r3, #8] 918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 6041 .loc 4 918 66 view .LVU1918 6042 0120 13F0020F tst r3, #2 6043 0124 04D1 bne .L267 6044 .LVL525: 918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 6045 .loc 4 918 66 view .LVU1919 6046 .LBE569: 6047 .LBE568: 2657:Src/main.c **** LL_SPI_TransmitData16(SPI6, DATA);//Transmit word to Laser1 DAC 6048 .loc 1 2657 42 discriminator 2 view .LVU1920 6049 0126 B2F5FA7F cmp r2, #500 6050 012a 01D8 bhi .L267 2657:Src/main.c **** LL_SPI_TransmitData16(SPI6, DATA);//Transmit word to Laser1 DAC 6051 .loc 1 2657 59 is_stmt 1 discriminator 3 view .LVU1921 2657:Src/main.c **** LL_SPI_TransmitData16(SPI6, DATA);//Transmit word to Laser1 DAC 6052 .loc 1 2657 64 is_stmt 0 discriminator 3 view .LVU1922 6053 012c 0132 adds r2, r2, #1 6054 .LVL526: 2657:Src/main.c **** LL_SPI_TransmitData16(SPI6, DATA);//Transmit word to Laser1 DAC 6055 .loc 1 2657 64 discriminator 3 view .LVU1923 6056 012e F5E7 b .L266 6057 .L267: 2658:Src/main.c **** tmp32 = 0; 6058 .loc 1 2658 4 is_stmt 1 view .LVU1924 6059 .LVL527: 6060 .LBB570: 6061 .LBI570: 1373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 6062 .loc 4 1373 22 view .LVU1925 6063 .LBB571: 1376:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** *spidr = TxData; 6064 .loc 4 1376 3 view .LVU1926 6065 .loc 4 1377 3 view .LVU1927 6066 .loc 4 1377 10 is_stmt 0 view .LVU1928 6067 0130 0B4B ldr r3, .L277+12 6068 0132 9C81 strh r4, [r3, #12] @ movhi 6069 .LVL528: 6070 .loc 4 1377 10 view .LVU1929 6071 .LBE571: ARM GAS /tmp/ccYgfTud.s page 477 6072 .LBE570: 2659:Src/main.c **** while((!LL_SPI_IsActiveFlag_RXNE(SPI6))&&(tmp32<=500)) {tmp32++;}//When trans. last data cycle w 6073 .loc 1 2659 4 is_stmt 1 view .LVU1930 2660:Src/main.c **** (void) SPI6->DR; 6074 .loc 1 2660 4 view .LVU1931 2659:Src/main.c **** while((!LL_SPI_IsActiveFlag_RXNE(SPI6))&&(tmp32<=500)) {tmp32++;}//When trans. last data cycle w 6075 .loc 1 2659 10 is_stmt 0 view .LVU1932 6076 0134 0022 movs r2, #0 6077 .LVL529: 6078 .L269: 2660:Src/main.c **** (void) SPI6->DR; 6079 .loc 1 2660 43 is_stmt 1 discriminator 1 view .LVU1933 6080 .LBB572: 6081 .LBI572: 905:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 6082 .loc 4 905 26 view .LVU1934 6083 .LBB573: 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 6084 .loc 4 907 3 view .LVU1935 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 6085 .loc 4 907 12 is_stmt 0 view .LVU1936 6086 0136 0A4B ldr r3, .L277+12 6087 0138 9B68 ldr r3, [r3, #8] 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 6088 .loc 4 907 68 view .LVU1937 6089 013a 13F0010F tst r3, #1 6090 013e 04D1 bne .L270 6091 .LVL530: 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 6092 .loc 4 907 68 view .LVU1938 6093 .LBE573: 6094 .LBE572: 2660:Src/main.c **** (void) SPI6->DR; 6095 .loc 1 2660 43 discriminator 2 view .LVU1939 6096 0140 B2F5FA7F cmp r2, #500 6097 0144 01D8 bhi .L270 2660:Src/main.c **** (void) SPI6->DR; 6098 .loc 1 2660 60 is_stmt 1 discriminator 3 view .LVU1940 2660:Src/main.c **** (void) SPI6->DR; 6099 .loc 1 2660 65 is_stmt 0 discriminator 3 view .LVU1941 6100 0146 0132 adds r2, r2, #1 6101 .LVL531: 2660:Src/main.c **** (void) SPI6->DR; 6102 .loc 1 2660 65 discriminator 3 view .LVU1942 6103 0148 F5E7 b .L269 6104 .L270: 2661:Src/main.c **** break; 6105 .loc 1 2661 4 is_stmt 1 view .LVU1943 6106 014a 054B ldr r3, .L277+12 6107 014c DB68 ldr r3, [r3, #12] 2662:Src/main.c **** } 6108 .loc 1 2662 3 view .LVU1944 6109 014e 85E7 b .L242 6110 .LVL532: 6111 .L274: 6112 .LCFI56: 6113 .cfi_def_cfa_offset 0 ARM GAS /tmp/ccYgfTud.s page 478 6114 .cfi_restore 3 6115 .cfi_restore 4 6116 .cfi_restore 5 6117 .cfi_restore 14 2662:Src/main.c **** } 6118 .loc 1 2662 3 is_stmt 0 view .LVU1945 6119 0150 7047 bx lr 6120 .L278: 6121 0152 00BF .align 2 6122 .L277: 6123 0154 00040240 .word 1073873920 6124 0158 00380040 .word 1073756160 6125 015c 00000240 .word 1073872896 6126 0160 00540140 .word 1073828864 6127 .cfi_endproc 6128 .LFE1217: 6130 .section .text.Decode_uart,"ax",%progbits 6131 .align 1 6132 .syntax unified 6133 .thumb 6134 .thumb_func 6136 Decode_uart: 6137 .LVL533: 6138 .LFB1208: 2147:Src/main.c **** // uint8_t *temp1; 6139 .loc 1 2147 1 is_stmt 1 view -0 6140 .cfi_startproc 6141 @ args = 0, pretend = 0, frame = 0 6142 @ frame_needed = 0, uses_anonymous_args = 0 2147:Src/main.c **** // uint8_t *temp1; 6143 .loc 1 2147 1 is_stmt 0 view .LVU1947 6144 0000 2DE9F843 push {r3, r4, r5, r6, r7, r8, r9, lr} 6145 .LCFI57: 6146 .cfi_def_cfa_offset 32 6147 .cfi_offset 3, -32 6148 .cfi_offset 4, -28 6149 .cfi_offset 5, -24 6150 .cfi_offset 6, -20 6151 .cfi_offset 7, -16 6152 .cfi_offset 8, -12 6153 .cfi_offset 9, -8 6154 .cfi_offset 14, -4 6155 0004 0546 mov r5, r0 6156 0006 0F46 mov r7, r1 6157 0008 1646 mov r6, r2 6158 000a 1C46 mov r4, r3 2149:Src/main.c **** 6159 .loc 1 2149 2 is_stmt 1 view .LVU1948 2154:Src/main.c **** if ((HAL_GPIO_ReadPin(SDMMC1_EN_GPIO_Port, SDMMC1_EN_Pin) == GPIO_PIN_RESET)&& 6160 .loc 1 2154 2 view .LVU1949 2154:Src/main.c **** if ((HAL_GPIO_ReadPin(SDMMC1_EN_GPIO_Port, SDMMC1_EN_Pin) == GPIO_PIN_RESET)&& 6161 .loc 1 2154 6 is_stmt 0 view .LVU1950 6162 000c AF4B ldr r3, .L303 6163 .LVL534: 2154:Src/main.c **** if ((HAL_GPIO_ReadPin(SDMMC1_EN_GPIO_Port, SDMMC1_EN_Pin) == GPIO_PIN_RESET)&& 6164 .loc 1 2154 6 view .LVU1951 6165 000e 0022 movs r2, #0 ARM GAS /tmp/ccYgfTud.s page 479 6166 .LVL535: 2154:Src/main.c **** if ((HAL_GPIO_ReadPin(SDMMC1_EN_GPIO_Port, SDMMC1_EN_Pin) == GPIO_PIN_RESET)&& 6167 .loc 1 2154 6 view .LVU1952 6168 0010 1A60 str r2, [r3] 2155:Src/main.c **** (HAL_GPIO_ReadPin(USB_FLAG_GPIO_Port, USB_FLAG_Pin) == GPIO_PIN_SET))//if exist sd && connect u 6169 .loc 1 2155 2 is_stmt 1 view .LVU1953 2155:Src/main.c **** (HAL_GPIO_ReadPin(USB_FLAG_GPIO_Port, USB_FLAG_Pin) == GPIO_PIN_SET))//if exist sd && connect u 6170 .loc 1 2155 7 is_stmt 0 view .LVU1954 6171 0012 0121 movs r1, #1 6172 .LVL536: 2155:Src/main.c **** (HAL_GPIO_ReadPin(USB_FLAG_GPIO_Port, USB_FLAG_Pin) == GPIO_PIN_SET))//if exist sd && connect u 6173 .loc 1 2155 7 view .LVU1955 6174 0014 AE48 ldr r0, .L303+4 6175 .LVL537: 2155:Src/main.c **** (HAL_GPIO_ReadPin(USB_FLAG_GPIO_Port, USB_FLAG_Pin) == GPIO_PIN_SET))//if exist sd && connect u 6176 .loc 1 2155 7 view .LVU1956 6177 0016 FFF7FEFF bl HAL_GPIO_ReadPin 6178 .LVL538: 2155:Src/main.c **** (HAL_GPIO_ReadPin(USB_FLAG_GPIO_Port, USB_FLAG_Pin) == GPIO_PIN_SET))//if exist sd && connect u 6179 .loc 1 2155 5 discriminator 1 view .LVU1957 6180 001a 0028 cmp r0, #0 6181 001c 00F0D280 beq .L300 6182 .L280: 2170:Src/main.c **** Curr_setup->WORK_EN = ((uint8_t)((*temp2)>>0))&0x01; 6183 .loc 1 2170 2 is_stmt 1 view .LVU1958 6184 .LVL539: 2171:Src/main.c **** Curr_setup->U5V1_EN = ((uint8_t)((*temp2)>>1))&0x01; 6185 .loc 1 2171 2 view .LVU1959 2171:Src/main.c **** Curr_setup->U5V1_EN = ((uint8_t)((*temp2)>>1))&0x01; 6186 .loc 1 2171 36 is_stmt 0 view .LVU1960 6187 0020 2B88 ldrh r3, [r5] 2171:Src/main.c **** Curr_setup->U5V1_EN = ((uint8_t)((*temp2)>>1))&0x01; 6188 .loc 1 2171 48 view .LVU1961 6189 0022 03F00103 and r3, r3, #1 2171:Src/main.c **** Curr_setup->U5V1_EN = ((uint8_t)((*temp2)>>1))&0x01; 6190 .loc 1 2171 22 view .LVU1962 6191 0026 2370 strb r3, [r4] 2172:Src/main.c **** Curr_setup->U5V2_EN = ((uint8_t)((*temp2)>>2))&0x01; 6192 .loc 1 2172 2 is_stmt 1 view .LVU1963 2172:Src/main.c **** Curr_setup->U5V2_EN = ((uint8_t)((*temp2)>>2))&0x01; 6193 .loc 1 2172 36 is_stmt 0 view .LVU1964 6194 0028 2B88 ldrh r3, [r5] 2172:Src/main.c **** Curr_setup->U5V2_EN = ((uint8_t)((*temp2)>>2))&0x01; 6195 .loc 1 2172 48 view .LVU1965 6196 002a C3F34003 ubfx r3, r3, #1, #1 2172:Src/main.c **** Curr_setup->U5V2_EN = ((uint8_t)((*temp2)>>2))&0x01; 6197 .loc 1 2172 22 view .LVU1966 6198 002e 6370 strb r3, [r4, #1] 2173:Src/main.c **** Curr_setup->LD1_EN = ((uint8_t)((*temp2)>>3))&0x01; 6199 .loc 1 2173 2 is_stmt 1 view .LVU1967 2173:Src/main.c **** Curr_setup->LD1_EN = ((uint8_t)((*temp2)>>3))&0x01; 6200 .loc 1 2173 36 is_stmt 0 view .LVU1968 6201 0030 2B88 ldrh r3, [r5] 2173:Src/main.c **** Curr_setup->LD1_EN = ((uint8_t)((*temp2)>>3))&0x01; 6202 .loc 1 2173 48 view .LVU1969 6203 0032 C3F38003 ubfx r3, r3, #2, #1 2173:Src/main.c **** Curr_setup->LD1_EN = ((uint8_t)((*temp2)>>3))&0x01; ARM GAS /tmp/ccYgfTud.s page 480 6204 .loc 1 2173 22 view .LVU1970 6205 0036 A370 strb r3, [r4, #2] 2174:Src/main.c **** Curr_setup->LD2_EN = ((uint8_t)((*temp2)>>4))&0x01; 6206 .loc 1 2174 2 is_stmt 1 view .LVU1971 2174:Src/main.c **** Curr_setup->LD2_EN = ((uint8_t)((*temp2)>>4))&0x01; 6207 .loc 1 2174 35 is_stmt 0 view .LVU1972 6208 0038 2B88 ldrh r3, [r5] 2174:Src/main.c **** Curr_setup->LD2_EN = ((uint8_t)((*temp2)>>4))&0x01; 6209 .loc 1 2174 47 view .LVU1973 6210 003a C3F3C003 ubfx r3, r3, #3, #1 2174:Src/main.c **** Curr_setup->LD2_EN = ((uint8_t)((*temp2)>>4))&0x01; 6211 .loc 1 2174 21 view .LVU1974 6212 003e E370 strb r3, [r4, #3] 2175:Src/main.c **** Curr_setup->REF1_EN = ((uint8_t)((*temp2)>>5))&0x01; 6213 .loc 1 2175 2 is_stmt 1 view .LVU1975 2175:Src/main.c **** Curr_setup->REF1_EN = ((uint8_t)((*temp2)>>5))&0x01; 6214 .loc 1 2175 35 is_stmt 0 view .LVU1976 6215 0040 2B88 ldrh r3, [r5] 2175:Src/main.c **** Curr_setup->REF1_EN = ((uint8_t)((*temp2)>>5))&0x01; 6216 .loc 1 2175 47 view .LVU1977 6217 0042 C3F30013 ubfx r3, r3, #4, #1 2175:Src/main.c **** Curr_setup->REF1_EN = ((uint8_t)((*temp2)>>5))&0x01; 6218 .loc 1 2175 21 view .LVU1978 6219 0046 2371 strb r3, [r4, #4] 2176:Src/main.c **** Curr_setup->REF2_EN = ((uint8_t)((*temp2)>>6))&0x01; 6220 .loc 1 2176 2 is_stmt 1 view .LVU1979 2176:Src/main.c **** Curr_setup->REF2_EN = ((uint8_t)((*temp2)>>6))&0x01; 6221 .loc 1 2176 36 is_stmt 0 view .LVU1980 6222 0048 2B88 ldrh r3, [r5] 2176:Src/main.c **** Curr_setup->REF2_EN = ((uint8_t)((*temp2)>>6))&0x01; 6223 .loc 1 2176 48 view .LVU1981 6224 004a C3F34013 ubfx r3, r3, #5, #1 2176:Src/main.c **** Curr_setup->REF2_EN = ((uint8_t)((*temp2)>>6))&0x01; 6225 .loc 1 2176 22 view .LVU1982 6226 004e 6371 strb r3, [r4, #5] 2177:Src/main.c **** Curr_setup->TEC1_EN = ((uint8_t)((*temp2)>>7))&0x01; 6227 .loc 1 2177 2 is_stmt 1 view .LVU1983 2177:Src/main.c **** Curr_setup->TEC1_EN = ((uint8_t)((*temp2)>>7))&0x01; 6228 .loc 1 2177 36 is_stmt 0 view .LVU1984 6229 0050 2B88 ldrh r3, [r5] 2177:Src/main.c **** Curr_setup->TEC1_EN = ((uint8_t)((*temp2)>>7))&0x01; 6230 .loc 1 2177 48 view .LVU1985 6231 0052 C3F38013 ubfx r3, r3, #6, #1 2177:Src/main.c **** Curr_setup->TEC1_EN = ((uint8_t)((*temp2)>>7))&0x01; 6232 .loc 1 2177 22 view .LVU1986 6233 0056 A371 strb r3, [r4, #6] 2178:Src/main.c **** Curr_setup->TEC2_EN = ((uint8_t)((*temp2)>>8))&0x01; 6234 .loc 1 2178 2 is_stmt 1 view .LVU1987 2178:Src/main.c **** Curr_setup->TEC2_EN = ((uint8_t)((*temp2)>>8))&0x01; 6235 .loc 1 2178 36 is_stmt 0 view .LVU1988 6236 0058 2B88 ldrh r3, [r5] 2178:Src/main.c **** Curr_setup->TEC2_EN = ((uint8_t)((*temp2)>>8))&0x01; 6237 .loc 1 2178 48 view .LVU1989 6238 005a C3F3C013 ubfx r3, r3, #7, #1 2178:Src/main.c **** Curr_setup->TEC2_EN = ((uint8_t)((*temp2)>>8))&0x01; 6239 .loc 1 2178 22 view .LVU1990 6240 005e E371 strb r3, [r4, #7] ARM GAS /tmp/ccYgfTud.s page 481 2179:Src/main.c **** Curr_setup->TS1_EN = ((uint8_t)((*temp2)>>9))&0x01; 6241 .loc 1 2179 2 is_stmt 1 view .LVU1991 2179:Src/main.c **** Curr_setup->TS1_EN = ((uint8_t)((*temp2)>>9))&0x01; 6242 .loc 1 2179 36 is_stmt 0 view .LVU1992 6243 0060 2B88 ldrh r3, [r5] 2179:Src/main.c **** Curr_setup->TS1_EN = ((uint8_t)((*temp2)>>9))&0x01; 6244 .loc 1 2179 48 view .LVU1993 6245 0062 C3F30023 ubfx r3, r3, #8, #1 2179:Src/main.c **** Curr_setup->TS1_EN = ((uint8_t)((*temp2)>>9))&0x01; 6246 .loc 1 2179 22 view .LVU1994 6247 0066 2372 strb r3, [r4, #8] 2180:Src/main.c **** Curr_setup->TS2_EN = ((uint8_t)((*temp2)>>10))&0x01; 6248 .loc 1 2180 2 is_stmt 1 view .LVU1995 2180:Src/main.c **** Curr_setup->TS2_EN = ((uint8_t)((*temp2)>>10))&0x01; 6249 .loc 1 2180 35 is_stmt 0 view .LVU1996 6250 0068 2B88 ldrh r3, [r5] 2180:Src/main.c **** Curr_setup->TS2_EN = ((uint8_t)((*temp2)>>10))&0x01; 6251 .loc 1 2180 47 view .LVU1997 6252 006a C3F34023 ubfx r3, r3, #9, #1 2180:Src/main.c **** Curr_setup->TS2_EN = ((uint8_t)((*temp2)>>10))&0x01; 6253 .loc 1 2180 21 view .LVU1998 6254 006e 6372 strb r3, [r4, #9] 2181:Src/main.c **** Curr_setup->SD_EN = ((uint8_t)((*temp2)>>11))&0x01; 6255 .loc 1 2181 2 is_stmt 1 view .LVU1999 2181:Src/main.c **** Curr_setup->SD_EN = ((uint8_t)((*temp2)>>11))&0x01; 6256 .loc 1 2181 35 is_stmt 0 view .LVU2000 6257 0070 2B88 ldrh r3, [r5] 2181:Src/main.c **** Curr_setup->SD_EN = ((uint8_t)((*temp2)>>11))&0x01; 6258 .loc 1 2181 48 view .LVU2001 6259 0072 C3F38023 ubfx r3, r3, #10, #1 2181:Src/main.c **** Curr_setup->SD_EN = ((uint8_t)((*temp2)>>11))&0x01; 6260 .loc 1 2181 21 view .LVU2002 6261 0076 A372 strb r3, [r4, #10] 2182:Src/main.c **** Curr_setup->PI1_RD = ((uint8_t)((*temp2)>>12))&0x01; 6262 .loc 1 2182 2 is_stmt 1 view .LVU2003 2182:Src/main.c **** Curr_setup->PI1_RD = ((uint8_t)((*temp2)>>12))&0x01; 6263 .loc 1 2182 34 is_stmt 0 view .LVU2004 6264 0078 2B88 ldrh r3, [r5] 2182:Src/main.c **** Curr_setup->PI1_RD = ((uint8_t)((*temp2)>>12))&0x01; 6265 .loc 1 2182 47 view .LVU2005 6266 007a C3F3C023 ubfx r3, r3, #11, #1 2182:Src/main.c **** Curr_setup->PI1_RD = ((uint8_t)((*temp2)>>12))&0x01; 6267 .loc 1 2182 20 view .LVU2006 6268 007e E372 strb r3, [r4, #11] 2183:Src/main.c **** Curr_setup->PI2_RD = ((uint8_t)((*temp2)>>13))&0x01; 6269 .loc 1 2183 2 is_stmt 1 view .LVU2007 2183:Src/main.c **** Curr_setup->PI2_RD = ((uint8_t)((*temp2)>>13))&0x01; 6270 .loc 1 2183 35 is_stmt 0 view .LVU2008 6271 0080 2B88 ldrh r3, [r5] 2183:Src/main.c **** Curr_setup->PI2_RD = ((uint8_t)((*temp2)>>13))&0x01; 6272 .loc 1 2183 48 view .LVU2009 6273 0082 C3F30033 ubfx r3, r3, #12, #1 2183:Src/main.c **** Curr_setup->PI2_RD = ((uint8_t)((*temp2)>>13))&0x01; 6274 .loc 1 2183 21 view .LVU2010 6275 0086 2373 strb r3, [r4, #12] 2184:Src/main.c **** 6276 .loc 1 2184 2 is_stmt 1 view .LVU2011 ARM GAS /tmp/ccYgfTud.s page 482 2184:Src/main.c **** 6277 .loc 1 2184 35 is_stmt 0 view .LVU2012 6278 0088 2B88 ldrh r3, [r5] 2184:Src/main.c **** 6279 .loc 1 2184 48 view .LVU2013 6280 008a C3F34033 ubfx r3, r3, #13, #1 2184:Src/main.c **** 6281 .loc 1 2184 21 view .LVU2014 6282 008e 6373 strb r3, [r4, #13] 2186:Src/main.c **** LD1_curr_setup->LD_TEMP = (uint16_t)(*temp2); 6283 .loc 1 2186 2 is_stmt 1 view .LVU2015 6284 .LVL540: 2187:Src/main.c **** temp2++; 6285 .loc 1 2187 2 view .LVU2016 2187:Src/main.c **** temp2++; 6286 .loc 1 2187 28 is_stmt 0 view .LVU2017 6287 0090 6B88 ldrh r3, [r5, #2] 2187:Src/main.c **** temp2++; 6288 .loc 1 2187 26 view .LVU2018 6289 0092 3B80 strh r3, [r7] @ movhi 2188:Src/main.c **** LD2_curr_setup->LD_TEMP = (uint16_t)(*temp2); 6290 .loc 1 2188 2 is_stmt 1 view .LVU2019 6291 .LVL541: 2189:Src/main.c **** temp2++; 6292 .loc 1 2189 2 view .LVU2020 2189:Src/main.c **** temp2++; 6293 .loc 1 2189 28 is_stmt 0 view .LVU2021 6294 0094 AB88 ldrh r3, [r5, #4] 2189:Src/main.c **** temp2++; 6295 .loc 1 2189 26 view .LVU2022 6296 0096 3380 strh r3, [r6] @ movhi 2190:Src/main.c **** temp2++; 6297 .loc 1 2190 2 is_stmt 1 view .LVU2023 6298 .LVL542: 2191:Src/main.c **** temp2++; 6299 .loc 1 2191 2 view .LVU2024 2192:Src/main.c **** Curr_setup->AVERAGES = (uint16_t)(*temp2); 6300 .loc 1 2192 2 view .LVU2025 2193:Src/main.c **** temp2++; 6301 .loc 1 2193 2 view .LVU2026 2193:Src/main.c **** temp2++; 6302 .loc 1 2193 25 is_stmt 0 view .LVU2027 6303 0098 6B89 ldrh r3, [r5, #10] 2193:Src/main.c **** temp2++; 6304 .loc 1 2193 23 view .LVU2028 6305 009a E381 strh r3, [r4, #14] @ movhi 2194:Src/main.c **** LD1_curr_setup->P_coef_temp = (float)((uint16_t)(*temp2))/((float)(256));//(float)(1/(float)((uint 6306 .loc 1 2194 2 is_stmt 1 view .LVU2029 6307 .LVL543: 2195:Src/main.c **** temp2++; 6308 .loc 1 2195 2 view .LVU2030 2195:Src/main.c **** temp2++; 6309 .loc 1 2195 51 is_stmt 0 view .LVU2031 6310 009c AB89 ldrh r3, [r5, #12] 6311 009e 07EE903A vmov s15, r3 @ int 2195:Src/main.c **** temp2++; 6312 .loc 1 2195 32 view .LVU2032 ARM GAS /tmp/ccYgfTud.s page 483 6313 00a2 F8EE677A vcvt.f32.u32 s15, s15 2195:Src/main.c **** temp2++; 6314 .loc 1 2195 59 view .LVU2033 6315 00a6 9FED8B7A vldr.32 s14, .L303+8 6316 00aa 67EE877A vmul.f32 s15, s15, s14 2195:Src/main.c **** temp2++; 6317 .loc 1 2195 30 view .LVU2034 6318 00ae C7ED017A vstr.32 s15, [r7, #4] 2196:Src/main.c **** LD1_curr_setup->I_coef_temp = (float)((uint16_t)(*temp2))/((float)(256));//(float)(1/(float)((uint 6319 .loc 1 2196 2 is_stmt 1 view .LVU2035 6320 .LVL544: 2197:Src/main.c **** temp2++; 6321 .loc 1 2197 2 view .LVU2036 2197:Src/main.c **** temp2++; 6322 .loc 1 2197 51 is_stmt 0 view .LVU2037 6323 00b2 EB89 ldrh r3, [r5, #14] 6324 00b4 07EE903A vmov s15, r3 @ int 2197:Src/main.c **** temp2++; 6325 .loc 1 2197 32 view .LVU2038 6326 00b8 F8EE677A vcvt.f32.u32 s15, s15 2197:Src/main.c **** temp2++; 6327 .loc 1 2197 59 view .LVU2039 6328 00bc 67EE877A vmul.f32 s15, s15, s14 2197:Src/main.c **** temp2++; 6329 .loc 1 2197 30 view .LVU2040 6330 00c0 C7ED027A vstr.32 s15, [r7, #8] 2198:Src/main.c **** LD2_curr_setup->P_coef_temp = (float)((uint16_t)(*temp2))/((float)(256));//(float)(1/(float)((uint 6331 .loc 1 2198 2 is_stmt 1 view .LVU2041 6332 .LVL545: 2199:Src/main.c **** temp2++; 6333 .loc 1 2199 2 view .LVU2042 2199:Src/main.c **** temp2++; 6334 .loc 1 2199 51 is_stmt 0 view .LVU2043 6335 00c4 2B8A ldrh r3, [r5, #16] 6336 00c6 07EE903A vmov s15, r3 @ int 2199:Src/main.c **** temp2++; 6337 .loc 1 2199 32 view .LVU2044 6338 00ca F8EE677A vcvt.f32.u32 s15, s15 2199:Src/main.c **** temp2++; 6339 .loc 1 2199 59 view .LVU2045 6340 00ce 67EE877A vmul.f32 s15, s15, s14 2199:Src/main.c **** temp2++; 6341 .loc 1 2199 30 view .LVU2046 6342 00d2 C6ED017A vstr.32 s15, [r6, #4] 2200:Src/main.c **** LD2_curr_setup->I_coef_temp = (float)((uint16_t)(*temp2))/((float)(256));//(float)(1/(float)((uint 6343 .loc 1 2200 2 is_stmt 1 view .LVU2047 6344 .LVL546: 2201:Src/main.c **** temp2++; 6345 .loc 1 2201 2 view .LVU2048 2201:Src/main.c **** temp2++; 6346 .loc 1 2201 51 is_stmt 0 view .LVU2049 6347 00d6 6B8A ldrh r3, [r5, #18] 6348 00d8 07EE903A vmov s15, r3 @ int 2201:Src/main.c **** temp2++; 6349 .loc 1 2201 32 view .LVU2050 6350 00dc F8EE677A vcvt.f32.u32 s15, s15 2201:Src/main.c **** temp2++; ARM GAS /tmp/ccYgfTud.s page 484 6351 .loc 1 2201 59 view .LVU2051 6352 00e0 67EE877A vmul.f32 s15, s15, s14 2201:Src/main.c **** temp2++; 6353 .loc 1 2201 30 view .LVU2052 6354 00e4 C6ED027A vstr.32 s15, [r6, #8] 2202:Src/main.c **** Long_Data[13] = (uint16_t)(*temp2);//Message ID 6355 .loc 1 2202 2 is_stmt 1 view .LVU2053 6356 .LVL547: 2203:Src/main.c **** temp2++; 6357 .loc 1 2203 2 view .LVU2054 2203:Src/main.c **** temp2++; 6358 .loc 1 2203 18 is_stmt 0 view .LVU2055 6359 00e8 AA8A ldrh r2, [r5, #20] 2203:Src/main.c **** temp2++; 6360 .loc 1 2203 16 view .LVU2056 6361 00ea 7B4B ldr r3, .L303+12 6362 00ec 5A83 strh r2, [r3, #26] @ movhi 2204:Src/main.c **** LD1_curr_setup->CURRENT = (uint16_t)(*temp2); 6363 .loc 1 2204 2 is_stmt 1 view .LVU2057 6364 .LVL548: 2205:Src/main.c **** temp2++; 6365 .loc 1 2205 2 view .LVU2058 2205:Src/main.c **** temp2++; 6366 .loc 1 2205 28 is_stmt 0 view .LVU2059 6367 00ee EB8A ldrh r3, [r5, #22] 2205:Src/main.c **** temp2++; 6368 .loc 1 2205 26 view .LVU2060 6369 00f0 BB81 strh r3, [r7, #12] @ movhi 2206:Src/main.c **** LD2_curr_setup->CURRENT = (uint16_t)(*temp2); 6370 .loc 1 2206 2 is_stmt 1 view .LVU2061 6371 .LVL549: 2207:Src/main.c **** temp2++; 6372 .loc 1 2207 2 view .LVU2062 2207:Src/main.c **** temp2++; 6373 .loc 1 2207 28 is_stmt 0 view .LVU2063 6374 00f2 2B8B ldrh r3, [r5, #24] 2207:Src/main.c **** temp2++; 6375 .loc 1 2207 26 view .LVU2064 6376 00f4 B381 strh r3, [r6, #12] @ movhi 2208:Src/main.c **** 6377 .loc 1 2208 2 is_stmt 1 view .LVU2065 6378 .LVL550: 2210:Src/main.c **** { 6379 .loc 1 2210 2 view .LVU2066 2210:Src/main.c **** { 6380 .loc 1 2210 16 is_stmt 0 view .LVU2067 6381 00f6 6378 ldrb r3, [r4, #1] @ zero_extendqisi2 2210:Src/main.c **** { 6382 .loc 1 2210 5 view .LVU2068 6383 00f8 002B cmp r3, #0 6384 00fa 00F09580 beq .L281 2212:Src/main.c **** } 6385 .loc 1 2212 3 is_stmt 1 view .LVU2069 6386 00fe 0122 movs r2, #1 6387 0100 0821 movs r1, #8 6388 0102 7648 ldr r0, .L303+16 6389 0104 FFF7FEFF bl HAL_GPIO_WritePin ARM GAS /tmp/ccYgfTud.s page 485 6390 .LVL551: 6391 .L282: 2219:Src/main.c **** { 6392 .loc 1 2219 2 view .LVU2070 2219:Src/main.c **** { 6393 .loc 1 2219 16 is_stmt 0 view .LVU2071 6394 0108 A378 ldrb r3, [r4, #2] @ zero_extendqisi2 2219:Src/main.c **** { 6395 .loc 1 2219 5 view .LVU2072 6396 010a 002B cmp r3, #0 6397 010c 00F09280 beq .L283 2221:Src/main.c **** } 6398 .loc 1 2221 3 is_stmt 1 view .LVU2073 6399 0110 0122 movs r2, #1 6400 0112 0421 movs r1, #4 6401 0114 7148 ldr r0, .L303+16 6402 0116 FFF7FEFF bl HAL_GPIO_WritePin 6403 .LVL552: 6404 .L284: 2228:Src/main.c **** { 6405 .loc 1 2228 2 view .LVU2074 2228:Src/main.c **** { 6406 .loc 1 2228 16 is_stmt 0 view .LVU2075 6407 011a E378 ldrb r3, [r4, #3] @ zero_extendqisi2 2228:Src/main.c **** { 6408 .loc 1 2228 5 view .LVU2076 6409 011c 002B cmp r3, #0 6410 011e 00F08F80 beq .L285 2230:Src/main.c **** //LL_SPI_Enable(SPI2);//Enable SPI for Laser1 DAC 6411 .loc 1 2230 3 is_stmt 1 view .LVU2077 6412 0122 0122 movs r2, #1 6413 0124 4FF48071 mov r1, #256 6414 0128 6948 ldr r0, .L303+4 6415 012a FFF7FEFF bl HAL_GPIO_WritePin 6416 .LVL553: 6417 .L286: 2239:Src/main.c **** { 6418 .loc 1 2239 2 view .LVU2078 2239:Src/main.c **** { 6419 .loc 1 2239 16 is_stmt 0 view .LVU2079 6420 012e 2379 ldrb r3, [r4, #4] @ zero_extendqisi2 2239:Src/main.c **** { 6421 .loc 1 2239 5 view .LVU2080 6422 0130 002B cmp r3, #0 6423 0132 00F08C80 beq .L287 2241:Src/main.c **** //LL_SPI_Enable(SPI6);//Enable SPI for Laser2 DAC 6424 .loc 1 2241 3 is_stmt 1 view .LVU2081 6425 0136 0122 movs r2, #1 6426 0138 1021 movs r1, #16 6427 013a 6848 ldr r0, .L303+16 6428 013c FFF7FEFF bl HAL_GPIO_WritePin 6429 .LVL554: 6430 .L288: 2250:Src/main.c **** { 6431 .loc 1 2250 2 view .LVU2082 2250:Src/main.c **** { 6432 .loc 1 2250 16 is_stmt 0 view .LVU2083 ARM GAS /tmp/ccYgfTud.s page 486 6433 0140 6379 ldrb r3, [r4, #5] @ zero_extendqisi2 2250:Src/main.c **** { 6434 .loc 1 2250 5 view .LVU2084 6435 0142 002B cmp r3, #0 6436 0144 00F08980 beq .L289 2252:Src/main.c **** } 6437 .loc 1 2252 3 is_stmt 1 view .LVU2085 6438 0148 0122 movs r2, #1 6439 014a 4FF48061 mov r1, #1024 6440 014e 6448 ldr r0, .L303+20 6441 0150 FFF7FEFF bl HAL_GPIO_WritePin 6442 .LVL555: 6443 .L290: 2259:Src/main.c **** { 6444 .loc 1 2259 2 view .LVU2086 2259:Src/main.c **** { 6445 .loc 1 2259 16 is_stmt 0 view .LVU2087 6446 0154 A379 ldrb r3, [r4, #6] @ zero_extendqisi2 2259:Src/main.c **** { 6447 .loc 1 2259 5 view .LVU2088 6448 0156 002B cmp r3, #0 6449 0158 00F08680 beq .L291 2261:Src/main.c **** } 6450 .loc 1 2261 3 is_stmt 1 view .LVU2089 6451 015c 0122 movs r2, #1 6452 015e 0821 movs r1, #8 6453 0160 6048 ldr r0, .L303+24 6454 0162 FFF7FEFF bl HAL_GPIO_WritePin 6455 .LVL556: 6456 .L292: 2268:Src/main.c **** { 6457 .loc 1 2268 2 view .LVU2090 2268:Src/main.c **** { 6458 .loc 1 2268 17 is_stmt 0 view .LVU2091 6459 0166 637A ldrb r3, [r4, #9] @ zero_extendqisi2 2268:Src/main.c **** { 6460 .loc 1 2268 5 view .LVU2092 6461 0168 1BB1 cbz r3, .L293 2268:Src/main.c **** { 6462 .loc 1 2268 39 discriminator 1 view .LVU2093 6463 016a E379 ldrb r3, [r4, #7] @ zero_extendqisi2 2268:Src/main.c **** { 6464 .loc 1 2268 26 discriminator 1 view .LVU2094 6465 016c 002B cmp r3, #0 6466 016e 40F08180 bne .L301 6467 .L293: 2277:Src/main.c **** HAL_GPIO_WritePin(TEC1_PD_GPIO_Port, TEC1_PD_Pin, GPIO_PIN_RESET); 6468 .loc 1 2277 3 is_stmt 1 view .LVU2095 6469 0172 0022 movs r2, #0 6470 0174 0121 movs r1, #1 6471 0176 5B48 ldr r0, .L303+24 6472 0178 FFF7FEFF bl HAL_GPIO_WritePin 6473 .LVL557: 2278:Src/main.c **** } 6474 .loc 1 2278 3 view .LVU2096 6475 017c 0022 movs r2, #0 6476 017e 4FF40061 mov r1, #2048 ARM GAS /tmp/ccYgfTud.s page 487 6477 0182 5748 ldr r0, .L303+20 6478 0184 FFF7FEFF bl HAL_GPIO_WritePin 6479 .LVL558: 6480 .L294: 2281:Src/main.c **** { 6481 .loc 1 2281 2 view .LVU2097 2281:Src/main.c **** { 6482 .loc 1 2281 17 is_stmt 0 view .LVU2098 6483 0188 A37A ldrb r3, [r4, #10] @ zero_extendqisi2 2281:Src/main.c **** { 6484 .loc 1 2281 5 view .LVU2099 6485 018a 1BB1 cbz r3, .L295 2281:Src/main.c **** { 6486 .loc 1 2281 39 discriminator 1 view .LVU2100 6487 018c 237A ldrb r3, [r4, #8] @ zero_extendqisi2 2281:Src/main.c **** { 6488 .loc 1 2281 26 discriminator 1 view .LVU2101 6489 018e 002B cmp r3, #0 6490 0190 40F08680 bne .L302 6491 .L295: 2290:Src/main.c **** HAL_GPIO_WritePin(TEC2_PD_GPIO_Port, TEC2_PD_Pin, GPIO_PIN_RESET); 6492 .loc 1 2290 3 is_stmt 1 view .LVU2102 6493 0194 0022 movs r2, #0 6494 0196 0221 movs r1, #2 6495 0198 5248 ldr r0, .L303+24 6496 019a FFF7FEFF bl HAL_GPIO_WritePin 6497 .LVL559: 2291:Src/main.c **** } 6498 .loc 1 2291 3 view .LVU2103 6499 019e 0022 movs r2, #0 6500 01a0 2021 movs r1, #32 6501 01a2 4E48 ldr r0, .L303+16 6502 01a4 FFF7FEFF bl HAL_GPIO_WritePin 6503 .LVL560: 6504 .L296: 2294:Src/main.c **** { 6505 .loc 1 2294 2 view .LVU2104 2294:Src/main.c **** { 6506 .loc 1 2294 16 is_stmt 0 view .LVU2105 6507 01a8 237B ldrb r3, [r4, #12] @ zero_extendqisi2 2294:Src/main.c **** { 6508 .loc 1 2294 5 view .LVU2106 6509 01aa 1BB9 cbnz r3, .L297 2296:Src/main.c **** LD1_curr_setup->I_coef_temp = 0.01; 6510 .loc 1 2296 3 is_stmt 1 view .LVU2107 2296:Src/main.c **** LD1_curr_setup->I_coef_temp = 0.01; 6511 .loc 1 2296 31 is_stmt 0 view .LVU2108 6512 01ac 4E4B ldr r3, .L303+28 6513 01ae 7B60 str r3, [r7, #4] @ float 2297:Src/main.c **** } 6514 .loc 1 2297 3 is_stmt 1 view .LVU2109 2297:Src/main.c **** } 6515 .loc 1 2297 31 is_stmt 0 view .LVU2110 6516 01b0 4E4B ldr r3, .L303+32 6517 01b2 BB60 str r3, [r7, #8] @ float 6518 .L297: 2300:Src/main.c **** { ARM GAS /tmp/ccYgfTud.s page 488 6519 .loc 1 2300 2 is_stmt 1 view .LVU2111 2300:Src/main.c **** { 6520 .loc 1 2300 16 is_stmt 0 view .LVU2112 6521 01b4 637B ldrb r3, [r4, #13] @ zero_extendqisi2 2300:Src/main.c **** { 6522 .loc 1 2300 5 view .LVU2113 6523 01b6 1BB9 cbnz r3, .L279 2302:Src/main.c **** LD2_curr_setup->I_coef_temp = 0.01; 6524 .loc 1 2302 3 is_stmt 1 view .LVU2114 2302:Src/main.c **** LD2_curr_setup->I_coef_temp = 0.01; 6525 .loc 1 2302 31 is_stmt 0 view .LVU2115 6526 01b8 4B4B ldr r3, .L303+28 6527 01ba 7360 str r3, [r6, #4] @ float 2303:Src/main.c **** } 6528 .loc 1 2303 3 is_stmt 1 view .LVU2116 2303:Src/main.c **** } 6529 .loc 1 2303 31 is_stmt 0 view .LVU2117 6530 01bc 4B4B ldr r3, .L303+32 6531 01be B360 str r3, [r6, #8] @ float 6532 .L279: 2305:Src/main.c **** 6533 .loc 1 2305 1 view .LVU2118 6534 01c0 BDE8F883 pop {r3, r4, r5, r6, r7, r8, r9, pc} 6535 .LVL561: 6536 .L300: 2156:Src/main.c **** { 6537 .loc 1 2156 6 view .LVU2119 6538 01c4 4FF48071 mov r1, #256 6539 01c8 4648 ldr r0, .L303+24 6540 01ca FFF7FEFF bl HAL_GPIO_ReadPin 6541 .LVL562: 2155:Src/main.c **** (HAL_GPIO_ReadPin(USB_FLAG_GPIO_Port, USB_FLAG_Pin) == GPIO_PIN_SET))//if exist sd && connect u 6542 .loc 1 2155 78 discriminator 1 view .LVU2120 6543 01ce 0128 cmp r0, #1 6544 01d0 7FF426AF bne .L280 2158:Src/main.c **** if (test == 0) //0 - suc 6545 .loc 1 2158 3 is_stmt 1 view .LVU2121 2158:Src/main.c **** if (test == 0) //0 - suc 6546 .loc 1 2158 10 is_stmt 0 view .LVU2122 6547 01d4 4648 ldr r0, .L303+36 6548 01d6 FFF7FEFF bl Mount_SD 6549 .LVL563: 2158:Src/main.c **** if (test == 0) //0 - suc 6550 .loc 1 2158 8 discriminator 1 view .LVU2123 6551 01da 3C4B ldr r3, .L303 6552 01dc 1860 str r0, [r3] 2159:Src/main.c **** { 6553 .loc 1 2159 3 is_stmt 1 view .LVU2124 2159:Src/main.c **** { 6554 .loc 1 2159 6 is_stmt 0 view .LVU2125 6555 01de 0028 cmp r0, #0 6556 01e0 7FF41EAF bne .L280 2162:Src/main.c **** test = Create_File("COMMAND.TXT"); // 0 -succ 6557 .loc 1 2162 4 is_stmt 1 view .LVU2126 2162:Src/main.c **** test = Create_File("COMMAND.TXT"); // 0 -succ 6558 .loc 1 2162 11 is_stmt 0 view .LVU2127 6559 01e4 DFF80C91 ldr r9, .L303+40 ARM GAS /tmp/ccYgfTud.s page 489 6560 01e8 4846 mov r0, r9 6561 01ea FFF7FEFF bl Remove_File 6562 .LVL564: 2162:Src/main.c **** test = Create_File("COMMAND.TXT"); // 0 -succ 6563 .loc 1 2162 9 discriminator 1 view .LVU2128 6564 01ee DFF8DC80 ldr r8, .L303 6565 01f2 C8F80000 str r0, [r8] 2163:Src/main.c **** test = Write_File_byte("COMMAND.TXT", (uint8_t *)Command, CL_8); 6566 .loc 1 2163 4 is_stmt 1 view .LVU2129 2163:Src/main.c **** test = Write_File_byte("COMMAND.TXT", (uint8_t *)Command, CL_8); 6567 .loc 1 2163 11 is_stmt 0 view .LVU2130 6568 01f6 4846 mov r0, r9 6569 01f8 FFF7FEFF bl Create_File 6570 .LVL565: 2163:Src/main.c **** test = Write_File_byte("COMMAND.TXT", (uint8_t *)Command, CL_8); 6571 .loc 1 2163 9 discriminator 1 view .LVU2131 6572 01fc C8F80000 str r0, [r8] 2164:Src/main.c **** test = Update_File_byte("COMMAND.TXT", (uint8_t *)Command, CL_8); 6573 .loc 1 2164 4 is_stmt 1 view .LVU2132 2164:Src/main.c **** test = Update_File_byte("COMMAND.TXT", (uint8_t *)Command, CL_8); 6574 .loc 1 2164 11 is_stmt 0 view .LVU2133 6575 0200 1E22 movs r2, #30 6576 0202 2946 mov r1, r5 6577 0204 4846 mov r0, r9 6578 0206 FFF7FEFF bl Write_File_byte 6579 .LVL566: 2164:Src/main.c **** test = Update_File_byte("COMMAND.TXT", (uint8_t *)Command, CL_8); 6580 .loc 1 2164 9 discriminator 1 view .LVU2134 6581 020a C8F80000 str r0, [r8] 2165:Src/main.c **** test = Unmount_SD("/"); // 0 - succ 6582 .loc 1 2165 4 is_stmt 1 view .LVU2135 2165:Src/main.c **** test = Unmount_SD("/"); // 0 - succ 6583 .loc 1 2165 11 is_stmt 0 view .LVU2136 6584 020e 1E22 movs r2, #30 6585 0210 2946 mov r1, r5 6586 0212 4846 mov r0, r9 6587 0214 FFF7FEFF bl Update_File_byte 6588 .LVL567: 2165:Src/main.c **** test = Unmount_SD("/"); // 0 - succ 6589 .loc 1 2165 9 discriminator 1 view .LVU2137 6590 0218 C8F80000 str r0, [r8] 2166:Src/main.c **** } 6591 .loc 1 2166 4 is_stmt 1 view .LVU2138 2166:Src/main.c **** } 6592 .loc 1 2166 11 is_stmt 0 view .LVU2139 6593 021c 3448 ldr r0, .L303+36 6594 021e FFF7FEFF bl Unmount_SD 6595 .LVL568: 2166:Src/main.c **** } 6596 .loc 1 2166 9 discriminator 1 view .LVU2140 6597 0222 C8F80000 str r0, [r8] 6598 0226 FBE6 b .L280 6599 .LVL569: 6600 .L281: 2216:Src/main.c **** } 6601 .loc 1 2216 3 is_stmt 1 view .LVU2141 6602 0228 0022 movs r2, #0 ARM GAS /tmp/ccYgfTud.s page 490 6603 022a 0821 movs r1, #8 6604 022c 2B48 ldr r0, .L303+16 6605 022e FFF7FEFF bl HAL_GPIO_WritePin 6606 .LVL570: 6607 0232 69E7 b .L282 6608 .L283: 2225:Src/main.c **** } 6609 .loc 1 2225 3 view .LVU2142 6610 0234 0022 movs r2, #0 6611 0236 0421 movs r1, #4 6612 0238 2848 ldr r0, .L303+16 6613 023a FFF7FEFF bl HAL_GPIO_WritePin 6614 .LVL571: 6615 023e 6CE7 b .L284 6616 .L285: 2235:Src/main.c **** //LL_SPI_Disable(SPI2);//Disable SPI for Laser1 DAC 6617 .loc 1 2235 3 view .LVU2143 6618 0240 0022 movs r2, #0 6619 0242 4FF48071 mov r1, #256 6620 0246 2248 ldr r0, .L303+4 6621 0248 FFF7FEFF bl HAL_GPIO_WritePin 6622 .LVL572: 6623 024c 6FE7 b .L286 6624 .L287: 2246:Src/main.c **** //LL_SPI_Disable(SPI6);//Disable SPI for Laser2 DAC 6625 .loc 1 2246 3 view .LVU2144 6626 024e 0022 movs r2, #0 6627 0250 1021 movs r1, #16 6628 0252 2248 ldr r0, .L303+16 6629 0254 FFF7FEFF bl HAL_GPIO_WritePin 6630 .LVL573: 6631 0258 72E7 b .L288 6632 .L289: 2256:Src/main.c **** } 6633 .loc 1 2256 3 view .LVU2145 6634 025a 0022 movs r2, #0 6635 025c 4FF48061 mov r1, #1024 6636 0260 1F48 ldr r0, .L303+20 6637 0262 FFF7FEFF bl HAL_GPIO_WritePin 6638 .LVL574: 6639 0266 75E7 b .L290 6640 .L291: 2265:Src/main.c **** } 6641 .loc 1 2265 3 view .LVU2146 6642 0268 0022 movs r2, #0 6643 026a 0821 movs r1, #8 6644 026c 1D48 ldr r0, .L303+24 6645 026e FFF7FEFF bl HAL_GPIO_WritePin 6646 .LVL575: 6647 0272 78E7 b .L292 6648 .L301: 2270:Src/main.c **** Set_LTEC(3,32767); 6649 .loc 1 2270 3 view .LVU2147 6650 0274 47F6FF71 movw r1, #32767 6651 0278 0320 movs r0, #3 6652 027a FFF7FEFF bl Set_LTEC 6653 .LVL576: ARM GAS /tmp/ccYgfTud.s page 491 2271:Src/main.c **** HAL_GPIO_WritePin(TEC1_PD_GPIO_Port, TEC1_PD_Pin, GPIO_PIN_SET); 6654 .loc 1 2271 3 view .LVU2148 6655 027e 47F6FF71 movw r1, #32767 6656 0282 0320 movs r0, #3 6657 0284 FFF7FEFF bl Set_LTEC 6658 .LVL577: 2272:Src/main.c **** HAL_GPIO_WritePin(TECEN1_GPIO_Port, TECEN1_Pin, GPIO_PIN_SET); 6659 .loc 1 2272 3 view .LVU2149 6660 0288 0122 movs r2, #1 6661 028a 4FF40061 mov r1, #2048 6662 028e 1448 ldr r0, .L303+20 6663 0290 FFF7FEFF bl HAL_GPIO_WritePin 6664 .LVL578: 2273:Src/main.c **** } 6665 .loc 1 2273 3 view .LVU2150 6666 0294 0122 movs r2, #1 6667 0296 1146 mov r1, r2 6668 0298 1248 ldr r0, .L303+24 6669 029a FFF7FEFF bl HAL_GPIO_WritePin 6670 .LVL579: 6671 029e 73E7 b .L294 6672 .L302: 2283:Src/main.c **** Set_LTEC(4,32767); 6673 .loc 1 2283 3 view .LVU2151 6674 02a0 47F6FF71 movw r1, #32767 6675 02a4 0420 movs r0, #4 6676 02a6 FFF7FEFF bl Set_LTEC 6677 .LVL580: 2284:Src/main.c **** HAL_GPIO_WritePin(TEC2_PD_GPIO_Port, TEC2_PD_Pin, GPIO_PIN_SET); 6678 .loc 1 2284 3 view .LVU2152 6679 02aa 47F6FF71 movw r1, #32767 6680 02ae 0420 movs r0, #4 6681 02b0 FFF7FEFF bl Set_LTEC 6682 .LVL581: 2285:Src/main.c **** HAL_GPIO_WritePin(TECEN2_GPIO_Port, TECEN2_Pin, GPIO_PIN_SET); 6683 .loc 1 2285 3 view .LVU2153 6684 02b4 0122 movs r2, #1 6685 02b6 2021 movs r1, #32 6686 02b8 0848 ldr r0, .L303+16 6687 02ba FFF7FEFF bl HAL_GPIO_WritePin 6688 .LVL582: 2286:Src/main.c **** } 6689 .loc 1 2286 3 view .LVU2154 6690 02be 0122 movs r2, #1 6691 02c0 0221 movs r1, #2 6692 02c2 0848 ldr r0, .L303+24 6693 02c4 FFF7FEFF bl HAL_GPIO_WritePin 6694 .LVL583: 6695 02c8 6EE7 b .L296 6696 .L304: 6697 02ca 00BF .align 2 6698 .L303: 6699 02cc 00000000 .word test 6700 02d0 000C0240 .word 1073875968 6701 02d4 0000803B .word 998244352 6702 02d8 00000000 .word Long_Data 6703 02dc 00080240 .word 1073874944 ARM GAS /tmp/ccYgfTud.s page 492 6704 02e0 00040240 .word 1073873920 6705 02e4 00000240 .word 1073872896 6706 02e8 00002041 .word 1092616192 6707 02ec 0AD7233C .word 1008981770 6708 02f0 00000000 .word .LC0 6709 02f4 04000000 .word .LC1 6710 .cfi_endproc 6711 .LFE1208: 6713 .section .text.Advanced_Controller_Temp,"ax",%progbits 6714 .align 1 6715 .global Advanced_Controller_Temp 6716 .syntax unified 6717 .thumb 6718 .thumb_func 6720 Advanced_Controller_Temp: 6721 .LVL584: 6722 .LFB1220: 2814:Src/main.c **** // Main idea: 6723 .loc 1 2814 1 view -0 6724 .cfi_startproc 6725 @ args = 0, pretend = 0, frame = 0 6726 @ frame_needed = 0, uses_anonymous_args = 0 6727 @ link register save eliminated. 2814:Src/main.c **** // Main idea: 6728 .loc 1 2814 1 is_stmt 0 view .LVU2156 6729 0000 30B4 push {r4, r5} 6730 .LCFI58: 6731 .cfi_def_cfa_offset 8 6732 .cfi_offset 4, -8 6733 .cfi_offset 5, -4 2832:Src/main.c **** float P_coef_current;//, I_coef_current; 6734 .loc 1 2832 2 is_stmt 1 view .LVU2157 2833:Src/main.c **** float e_integral; 6735 .loc 1 2833 2 view .LVU2158 2834:Src/main.c **** int x_output; 6736 .loc 1 2834 2 view .LVU2159 2835:Src/main.c **** 6737 .loc 1 2835 2 view .LVU2160 2837:Src/main.c **** 6738 .loc 1 2837 2 view .LVU2161 2837:Src/main.c **** 6739 .loc 1 2837 28 is_stmt 0 view .LVU2162 6740 0002 0B88 ldrh r3, [r1] 2837:Src/main.c **** 6741 .loc 1 2837 65 view .LVU2163 6742 0004 0488 ldrh r4, [r0] 2837:Src/main.c **** 6743 .loc 1 2837 8 view .LVU2164 6744 0006 1B1B subs r3, r3, r4 6745 .LVL585: 2839:Src/main.c **** 6746 .loc 1 2839 2 is_stmt 1 view .LVU2165 2839:Src/main.c **** 6747 .loc 1 2839 13 is_stmt 0 view .LVU2166 6748 0008 D1ED017A vldr.32 s15, [r1, #4] 6749 .LVL586: 2841:Src/main.c **** e_integral += LDx_curr_setup->I_coef_temp * (float)(e_pid) * (float)(TO7 - TO7_PID) / (float) 100 ARM GAS /tmp/ccYgfTud.s page 493 6750 .loc 1 2841 2 is_stmt 1 view .LVU2167 2841:Src/main.c **** e_integral += LDx_curr_setup->I_coef_temp * (float)(e_pid) * (float)(TO7 - TO7_PID) / (float) 100 6751 .loc 1 2841 20 is_stmt 0 view .LVU2168 6752 000c 03F6B73C addw ip, r3, #2999 2841:Src/main.c **** e_integral += LDx_curr_setup->I_coef_temp * (float)(e_pid) * (float)(TO7 - TO7_PID) / (float) 100 6753 .loc 1 2841 4 view .LVU2169 6754 0010 41F26E74 movw r4, #5998 6755 0014 A445 cmp ip, r4 6756 0016 18D8 bhi .L306 2842:Src/main.c **** } 6757 .loc 1 2842 3 is_stmt 1 view .LVU2170 2842:Src/main.c **** } 6758 .loc 1 2842 31 is_stmt 0 view .LVU2171 6759 0018 90ED027A vldr.32 s14, [r0, #8] 2842:Src/main.c **** } 6760 .loc 1 2842 47 view .LVU2172 6761 001c 06EE903A vmov s13, r3 @ int 6762 0020 F8EEE66A vcvt.f32.s32 s13, s13 2842:Src/main.c **** } 6763 .loc 1 2842 45 view .LVU2173 6764 0024 27EE267A vmul.f32 s14, s14, s13 2842:Src/main.c **** } 6765 .loc 1 2842 76 view .LVU2174 6766 0028 284C ldr r4, .L316 6767 002a 2468 ldr r4, [r4] 6768 002c 284D ldr r5, .L316+4 6769 002e 2D68 ldr r5, [r5] 6770 0030 641B subs r4, r4, r5 2842:Src/main.c **** } 6771 .loc 1 2842 64 view .LVU2175 6772 0032 06EE904A vmov s13, r4 @ int 6773 0036 F8EE666A vcvt.f32.u32 s13, s13 2842:Src/main.c **** } 6774 .loc 1 2842 62 view .LVU2176 6775 003a 27EE267A vmul.f32 s14, s14, s13 2842:Src/main.c **** } 6776 .loc 1 2842 87 view .LVU2177 6777 003e 9FED256A vldr.32 s12, .L316+8 6778 0042 C7EE066A vdiv.f32 s13, s14, s12 2842:Src/main.c **** } 6779 .loc 1 2842 14 view .LVU2178 6780 0046 77EEA67A vadd.f32 s15, s15, s13 6781 .LVL587: 6782 .L306: 2844:Src/main.c **** 6783 .loc 1 2844 2 is_stmt 1 view .LVU2179 2844:Src/main.c **** 6784 .loc 1 2844 17 is_stmt 0 view .LVU2180 6785 004a D0ED016A vldr.32 s13, [r0, #4] 6786 .LVL588: 2846:Src/main.c **** e_integral = 32000; 6787 .loc 1 2846 2 is_stmt 1 view .LVU2181 2846:Src/main.c **** e_integral = 32000; 6788 .loc 1 2846 5 is_stmt 0 view .LVU2182 6789 004e 9FED227A vldr.32 s14, .L316+12 6790 0052 F4EEC77A vcmpe.f32 s15, s14 6791 0056 F1EE10FA vmrs APSR_nzcv, FPSCR ARM GAS /tmp/ccYgfTud.s page 494 6792 005a 09DC bgt .L310 2849:Src/main.c **** e_integral = -32000; 6793 .loc 1 2849 7 is_stmt 1 view .LVU2183 2849:Src/main.c **** e_integral = -32000; 6794 .loc 1 2849 10 is_stmt 0 view .LVU2184 6795 005c 9FED1F7A vldr.32 s14, .L316+16 6796 0060 F4EEC77A vcmpe.f32 s15, s14 6797 0064 F1EE10FA vmrs APSR_nzcv, FPSCR 6798 0068 04D5 bpl .L307 2850:Src/main.c **** } 6799 .loc 1 2850 15 view .LVU2185 6800 006a DFED1C7A vldr.32 s15, .L316+16 6801 .LVL589: 2850:Src/main.c **** } 6802 .loc 1 2850 15 view .LVU2186 6803 006e 01E0 b .L307 6804 .LVL590: 6805 .L310: 2847:Src/main.c **** } 6806 .loc 1 2847 15 view .LVU2187 6807 0070 DFED197A vldr.32 s15, .L316+12 6808 .LVL591: 6809 .L307: 2852:Src/main.c **** 6810 .loc 1 2852 2 is_stmt 1 view .LVU2188 2852:Src/main.c **** 6811 .loc 1 2852 26 is_stmt 0 view .LVU2189 6812 0074 C1ED017A vstr.32 s15, [r1, #4] 2854:Src/main.c **** 6813 .loc 1 2854 2 is_stmt 1 view .LVU2190 2854:Src/main.c **** 6814 .loc 1 2854 36 is_stmt 0 view .LVU2191 6815 0078 07EE103A vmov s14, r3 @ int 6816 007c B8EEC77A vcvt.f32.s32 s14, s14 6817 0080 27EE267A vmul.f32 s14, s14, s13 2854:Src/main.c **** 6818 .loc 1 2854 19 view .LVU2192 6819 0084 DFED166A vldr.32 s13, .L316+20 6820 .LVL592: 2854:Src/main.c **** 6821 .loc 1 2854 19 view .LVU2193 6822 0088 37EE267A vadd.f32 s14, s14, s13 2854:Src/main.c **** 6823 .loc 1 2854 46 view .LVU2194 6824 008c FDEEE77A vcvt.s32.f32 s15, s15 6825 .LVL593: 2854:Src/main.c **** 6826 .loc 1 2854 44 view .LVU2195 6827 0090 F8EEE77A vcvt.f32.s32 s15, s15 6828 0094 77EE877A vadd.f32 s15, s15, s14 2854:Src/main.c **** 6829 .loc 1 2854 11 view .LVU2196 6830 0098 FDEEE77A vcvt.s32.f32 s15, s15 6831 009c 17EE900A vmov r0, s15 @ int 6832 .LVL594: 2856:Src/main.c **** x_output = 8800; 6833 .loc 1 2856 2 is_stmt 1 view .LVU2197 ARM GAS /tmp/ccYgfTud.s page 495 2856:Src/main.c **** x_output = 8800; 6834 .loc 1 2856 4 is_stmt 0 view .LVU2198 6835 00a0 B0F57A7F cmp r0, #1000 6836 00a4 06DB blt .L312 2859:Src/main.c **** x_output = 56800; 6837 .loc 1 2859 7 is_stmt 1 view .LVU2199 2859:Src/main.c **** x_output = 56800; 6838 .loc 1 2859 9 is_stmt 0 view .LVU2200 6839 00a6 4DF6E053 movw r3, #56800 6840 .LVL595: 2859:Src/main.c **** x_output = 56800; 6841 .loc 1 2859 9 view .LVU2201 6842 00aa 9842 cmp r0, r3 6843 00ac 04DD ble .L308 2860:Src/main.c **** } 6844 .loc 1 2860 12 view .LVU2202 6845 00ae 4DF6E050 movw r0, #56800 6846 .LVL596: 2860:Src/main.c **** } 6847 .loc 1 2860 12 view .LVU2203 6848 00b2 01E0 b .L308 6849 .LVL597: 6850 .L312: 2857:Src/main.c **** } 6851 .loc 1 2857 12 view .LVU2204 6852 00b4 42F26020 movw r0, #8800 6853 .LVL598: 6854 .L308: 2863:Src/main.c **** TO7_PID = TO7;//Save current time only on 2nd laser 6855 .loc 1 2863 2 is_stmt 1 view .LVU2205 2863:Src/main.c **** TO7_PID = TO7;//Save current time only on 2nd laser 6856 .loc 1 2863 5 is_stmt 0 view .LVU2206 6857 00b8 022A cmp r2, #2 6858 00ba 02D0 beq .L315 6859 .LVL599: 6860 .L309: 2866:Src/main.c **** } 6861 .loc 1 2866 2 is_stmt 1 view .LVU2207 2867:Src/main.c **** 6862 .loc 1 2867 1 is_stmt 0 view .LVU2208 6863 00bc 80B2 uxth r0, r0 6864 .LVL600: 2867:Src/main.c **** 6865 .loc 1 2867 1 view .LVU2209 6866 00be 30BC pop {r4, r5} 6867 .LCFI59: 6868 .cfi_remember_state 6869 .cfi_restore 5 6870 .cfi_restore 4 6871 .cfi_def_cfa_offset 0 6872 00c0 7047 bx lr 6873 .LVL601: 6874 .L315: 6875 .LCFI60: 6876 .cfi_restore_state 2864:Src/main.c **** 6877 .loc 1 2864 3 is_stmt 1 view .LVU2210 ARM GAS /tmp/ccYgfTud.s page 496 2864:Src/main.c **** 6878 .loc 1 2864 11 is_stmt 0 view .LVU2211 6879 00c2 024B ldr r3, .L316 6880 00c4 1A68 ldr r2, [r3] 6881 .LVL602: 2864:Src/main.c **** 6882 .loc 1 2864 11 view .LVU2212 6883 00c6 024B ldr r3, .L316+4 6884 00c8 1A60 str r2, [r3] 6885 00ca F7E7 b .L309 6886 .L317: 6887 .align 2 6888 .L316: 6889 00cc 00000000 .word TO7 6890 00d0 00000000 .word TO7_PID 6891 00d4 0000C842 .word 1120403456 6892 00d8 0000FA46 .word 1190789120 6893 00dc 0000FAC6 .word -956694528 6894 00e0 00000047 .word 1191182336 6895 .cfi_endproc 6896 .LFE1220: 6898 .section .text.CalculateChecksum,"ax",%progbits 6899 .align 1 6900 .global CalculateChecksum 6901 .syntax unified 6902 .thumb 6903 .thumb_func 6905 CalculateChecksum: 6906 .LVL603: 6907 .LFB1223: 2930:Src/main.c **** short i; 6908 .loc 1 2930 1 is_stmt 1 view -0 6909 .cfi_startproc 6910 @ args = 0, pretend = 0, frame = 0 6911 @ frame_needed = 0, uses_anonymous_args = 0 6912 @ link register save eliminated. 2930:Src/main.c **** short i; 6913 .loc 1 2930 1 is_stmt 0 view .LVU2214 6914 0000 8446 mov ip, r0 2931:Src/main.c **** uint16_t cs = *pbuff; 6915 .loc 1 2931 2 is_stmt 1 view .LVU2215 2932:Src/main.c **** 6916 .loc 1 2932 2 view .LVU2216 2932:Src/main.c **** 6917 .loc 1 2932 11 is_stmt 0 view .LVU2217 6918 0002 0088 ldrh r0, [r0] 6919 .LVL604: 2934:Src/main.c **** { 6920 .loc 1 2934 3 is_stmt 1 view .LVU2218 2934:Src/main.c **** { 6921 .loc 1 2934 9 is_stmt 0 view .LVU2219 6922 0004 0123 movs r3, #1 2934:Src/main.c **** { 6923 .loc 1 2934 3 view .LVU2220 6924 0006 04E0 b .L319 6925 .LVL605: 6926 .L320: ARM GAS /tmp/ccYgfTud.s page 497 2936:Src/main.c **** } 6927 .loc 1 2936 3 is_stmt 1 view .LVU2221 2936:Src/main.c **** } 6928 .loc 1 2936 9 is_stmt 0 view .LVU2222 6929 0008 3CF81320 ldrh r2, [ip, r3, lsl #1] 2936:Src/main.c **** } 6930 .loc 1 2936 6 view .LVU2223 6931 000c 5040 eors r0, r0, r2 6932 .LVL606: 2934:Src/main.c **** { 6933 .loc 1 2934 24 is_stmt 1 discriminator 3 view .LVU2224 6934 000e 0133 adds r3, r3, #1 6935 .LVL607: 2934:Src/main.c **** { 6936 .loc 1 2934 24 is_stmt 0 discriminator 3 view .LVU2225 6937 0010 1BB2 sxth r3, r3 6938 .LVL608: 6939 .L319: 2934:Src/main.c **** { 6940 .loc 1 2934 16 is_stmt 1 discriminator 1 view .LVU2226 6941 0012 8B42 cmp r3, r1 6942 0014 F8DB blt .L320 2938:Src/main.c **** } 6943 .loc 1 2938 2 view .LVU2227 2939:Src/main.c **** 6944 .loc 1 2939 1 is_stmt 0 view .LVU2228 6945 0016 7047 bx lr 6946 .cfi_endproc 6947 .LFE1223: 6949 .section .text.CheckChecksum,"ax",%progbits 6950 .align 1 6951 .global CheckChecksum 6952 .syntax unified 6953 .thumb 6954 .thumb_func 6956 CheckChecksum: 6957 .LVL609: 6958 .LFB1222: 2909:Src/main.c **** uint16_t cl_ind; 6959 .loc 1 2909 1 is_stmt 1 view -0 6960 .cfi_startproc 6961 @ args = 0, pretend = 0, frame = 0 6962 @ frame_needed = 0, uses_anonymous_args = 0 2909:Src/main.c **** uint16_t cl_ind; 6963 .loc 1 2909 1 is_stmt 0 view .LVU2230 6964 0000 10B5 push {r4, lr} 6965 .LCFI61: 6966 .cfi_def_cfa_offset 8 6967 .cfi_offset 4, -8 6968 .cfi_offset 14, -4 2910:Src/main.c **** 6969 .loc 1 2910 3 is_stmt 1 view .LVU2231 2912:Src/main.c **** { 6970 .loc 1 2912 3 view .LVU2232 6971 0002 0E4B ldr r3, .L327 6972 0004 1B88 ldrh r3, [r3] 6973 0006 41F21112 movw r2, #4369 ARM GAS /tmp/ccYgfTud.s page 498 6974 000a 9342 cmp r3, r2 6975 000c 05D0 beq .L324 6976 000e 47F27772 movw r2, #30583 6977 0012 9342 cmp r3, r2 6978 0014 0FD1 bne .L325 6979 0016 0E24 movs r4, #14 6980 0018 00E0 b .L322 6981 .L324: 2918:Src/main.c **** break; 6982 .loc 1 2918 14 is_stmt 0 view .LVU2233 6983 001a 0D24 movs r4, #13 6984 .L322: 6985 .LVL610: 2922:Src/main.c **** } 6986 .loc 1 2922 5 is_stmt 1 view .LVU2234 2925:Src/main.c **** 6987 .loc 1 2925 3 view .LVU2235 2925:Src/main.c **** 6988 .loc 1 2925 15 is_stmt 0 view .LVU2236 6989 001c 2146 mov r1, r4 6990 001e FFF7FEFF bl CalculateChecksum 6991 .LVL611: 2925:Src/main.c **** 6992 .loc 1 2925 13 discriminator 1 view .LVU2237 6993 0022 074B ldr r3, .L327+4 6994 0024 1880 strh r0, [r3] @ movhi 2927:Src/main.c **** } 6995 .loc 1 2927 3 is_stmt 1 view .LVU2238 2927:Src/main.c **** } 6996 .loc 1 2927 32 is_stmt 0 view .LVU2239 6997 0026 074B ldr r3, .L327+8 6998 0028 33F81430 ldrh r3, [r3, r4, lsl #1] 2927:Src/main.c **** } 6999 .loc 1 2927 46 view .LVU2240 7000 002c 9842 cmp r0, r3 7001 002e 14BF ite ne 7002 0030 0020 movne r0, #0 7003 0032 0120 moveq r0, #1 7004 .LVL612: 7005 .L323: 2928:Src/main.c **** uint16_t CalculateChecksum(uint16_t *pbuff, uint16_t len) 7006 .loc 1 2928 1 view .LVU2241 7007 0034 10BD pop {r4, pc} 7008 .LVL613: 7009 .L325: 2912:Src/main.c **** { 7010 .loc 1 2912 3 view .LVU2242 7011 0036 0020 movs r0, #0 7012 .LVL614: 2912:Src/main.c **** { 7013 .loc 1 2912 3 view .LVU2243 7014 0038 FCE7 b .L323 7015 .L328: 7016 003a 00BF .align 2 7017 .L327: 7018 003c 00000000 .word UART_header 7019 0040 00000000 .word CS_result ARM GAS /tmp/ccYgfTud.s page 499 7020 0044 00000000 .word COMMAND 7021 .cfi_endproc 7022 .LFE1222: 7024 .section .rodata.SD_SAVE.str1.4,"aMS",%progbits,1 7025 .align 2 7026 .LC2: 7027 0000 46494C45 .ascii "FILE1.TXT\000" 7027 312E5458 7027 5400 7028 .section .text.SD_SAVE,"ax",%progbits 7029 .align 1 7030 .global SD_SAVE 7031 .syntax unified 7032 .thumb 7033 .thumb_func 7035 SD_SAVE: 7036 .LVL615: 7037 .LFB1224: 2968:Src/main.c **** int test=0; 7038 .loc 1 2968 1 is_stmt 1 view -0 7039 .cfi_startproc 7040 @ args = 0, pretend = 0, frame = 0 7041 @ frame_needed = 0, uses_anonymous_args = 0 2968:Src/main.c **** int test=0; 7042 .loc 1 2968 1 is_stmt 0 view .LVU2245 7043 0000 10B5 push {r4, lr} 7044 .LCFI62: 7045 .cfi_def_cfa_offset 8 7046 .cfi_offset 4, -8 7047 .cfi_offset 14, -4 7048 0002 0446 mov r4, r0 2969:Src/main.c **** if (HAL_GPIO_ReadPin(SDMMC1_EN_GPIO_Port, SDMMC1_EN_Pin)==GPIO_PIN_RESET) 7049 .loc 1 2969 2 is_stmt 1 view .LVU2246 7050 .LVL616: 2970:Src/main.c **** { 7051 .loc 1 2970 2 view .LVU2247 2970:Src/main.c **** { 7052 .loc 1 2970 6 is_stmt 0 view .LVU2248 7053 0004 0121 movs r1, #1 7054 0006 0A48 ldr r0, .L336 7055 .LVL617: 2970:Src/main.c **** { 7056 .loc 1 2970 6 view .LVU2249 7057 0008 FFF7FEFF bl HAL_GPIO_ReadPin 7058 .LVL618: 2970:Src/main.c **** { 7059 .loc 1 2970 5 discriminator 1 view .LVU2250 7060 000c 08B1 cbz r0, .L334 2987:Src/main.c **** } 7061 .loc 1 2987 10 view .LVU2251 7062 000e 0120 movs r0, #1 7063 .LVL619: 7064 .L329: 2989:Src/main.c **** 7065 .loc 1 2989 1 view .LVU2252 7066 0010 10BD pop {r4, pc} 7067 .LVL620: ARM GAS /tmp/ccYgfTud.s page 500 7068 .L334: 2972:Src/main.c **** if (test == 0) //0 - suc 7069 .loc 1 2972 3 is_stmt 1 view .LVU2253 2972:Src/main.c **** if (test == 0) //0 - suc 7070 .loc 1 2972 10 is_stmt 0 view .LVU2254 7071 0012 0848 ldr r0, .L336+4 7072 0014 FFF7FEFF bl Mount_SD 7073 .LVL621: 2973:Src/main.c **** { 7074 .loc 1 2973 3 is_stmt 1 view .LVU2255 2973:Src/main.c **** { 7075 .loc 1 2973 6 is_stmt 0 view .LVU2256 7076 0018 08B1 cbz r0, .L335 2982:Src/main.c **** } 7077 .loc 1 2982 11 view .LVU2257 7078 001a 0120 movs r0, #1 7079 .LVL622: 2982:Src/main.c **** } 7080 .loc 1 2982 11 view .LVU2258 7081 001c F8E7 b .L329 7082 .LVL623: 7083 .L335: 2976:Src/main.c **** test = Unmount_SD("/"); // 0 - succ 7084 .loc 1 2976 4 is_stmt 1 view .LVU2259 2976:Src/main.c **** test = Unmount_SD("/"); // 0 - succ 7085 .loc 1 2976 11 is_stmt 0 view .LVU2260 7086 001e 1E22 movs r2, #30 7087 0020 2146 mov r1, r4 7088 0022 0548 ldr r0, .L336+8 7089 .LVL624: 2976:Src/main.c **** test = Unmount_SD("/"); // 0 - succ 7090 .loc 1 2976 11 view .LVU2261 7091 0024 FFF7FEFF bl Update_File_byte 7092 .LVL625: 2977:Src/main.c **** return test; 7093 .loc 1 2977 4 is_stmt 1 view .LVU2262 2977:Src/main.c **** return test; 7094 .loc 1 2977 11 is_stmt 0 view .LVU2263 7095 0028 0248 ldr r0, .L336+4 7096 002a FFF7FEFF bl Unmount_SD 7097 .LVL626: 2978:Src/main.c **** } 7098 .loc 1 2978 4 is_stmt 1 view .LVU2264 2978:Src/main.c **** } 7099 .loc 1 2978 11 is_stmt 0 view .LVU2265 7100 002e EFE7 b .L329 7101 .L337: 7102 .align 2 7103 .L336: 7104 0030 000C0240 .word 1073875968 7105 0034 00000000 .word .LC0 7106 0038 00000000 .word .LC2 7107 .cfi_endproc 7108 .LFE1224: 7110 .section .text.SD_READ,"ax",%progbits 7111 .align 1 7112 .global SD_READ ARM GAS /tmp/ccYgfTud.s page 501 7113 .syntax unified 7114 .thumb 7115 .thumb_func 7117 SD_READ: 7118 .LVL627: 7119 .LFB1225: 2999:Src/main.c **** int test=0; 7120 .loc 1 2999 1 is_stmt 1 view -0 7121 .cfi_startproc 7122 @ args = 0, pretend = 0, frame = 0 7123 @ frame_needed = 0, uses_anonymous_args = 0 2999:Src/main.c **** int test=0; 7124 .loc 1 2999 1 is_stmt 0 view .LVU2267 7125 0000 38B5 push {r3, r4, r5, lr} 7126 .LCFI63: 7127 .cfi_def_cfa_offset 16 7128 .cfi_offset 3, -16 7129 .cfi_offset 4, -12 7130 .cfi_offset 5, -8 7131 .cfi_offset 14, -4 7132 0002 0446 mov r4, r0 3000:Src/main.c **** if (HAL_GPIO_ReadPin(SDMMC1_EN_GPIO_Port, SDMMC1_EN_Pin)==GPIO_PIN_RESET) 7133 .loc 1 3000 2 is_stmt 1 view .LVU2268 7134 .LVL628: 3001:Src/main.c **** { 7135 .loc 1 3001 2 view .LVU2269 3001:Src/main.c **** { 7136 .loc 1 3001 6 is_stmt 0 view .LVU2270 7137 0004 0121 movs r1, #1 7138 0006 0D48 ldr r0, .L345 7139 .LVL629: 3001:Src/main.c **** { 7140 .loc 1 3001 6 view .LVU2271 7141 0008 FFF7FEFF bl HAL_GPIO_ReadPin 7142 .LVL630: 3001:Src/main.c **** { 7143 .loc 1 3001 5 discriminator 1 view .LVU2272 7144 000c 08B1 cbz r0, .L343 3019:Src/main.c **** } 7145 .loc 1 3019 10 view .LVU2273 7146 000e 0120 movs r0, #1 7147 .LVL631: 7148 .L338: 3035:Src/main.c **** 7149 .loc 1 3035 1 view .LVU2274 7150 0010 38BD pop {r3, r4, r5, pc} 7151 .LVL632: 7152 .L343: 3003:Src/main.c **** if (test == 0) //0 - suc 7153 .loc 1 3003 3 is_stmt 1 view .LVU2275 3003:Src/main.c **** if (test == 0) //0 - suc 7154 .loc 1 3003 10 is_stmt 0 view .LVU2276 7155 0012 0B48 ldr r0, .L345+4 7156 0014 FFF7FEFF bl Mount_SD 7157 .LVL633: 3004:Src/main.c **** { 7158 .loc 1 3004 3 is_stmt 1 view .LVU2277 ARM GAS /tmp/ccYgfTud.s page 502 3004:Src/main.c **** { 7159 .loc 1 3004 6 is_stmt 0 view .LVU2278 7160 0018 08B1 cbz r0, .L344 3014:Src/main.c **** } 7161 .loc 1 3014 11 view .LVU2279 7162 001a 0120 movs r0, #1 7163 .LVL634: 3014:Src/main.c **** } 7164 .loc 1 3014 11 view .LVU2280 7165 001c F8E7 b .L338 7166 .LVL635: 7167 .L344: 3007:Src/main.c **** fgoto+=DL_8; 7168 .loc 1 3007 4 is_stmt 1 view .LVU2281 3007:Src/main.c **** fgoto+=DL_8; 7169 .loc 1 3007 11 is_stmt 0 view .LVU2282 7170 001e 094D ldr r5, .L345+8 7171 0020 2B68 ldr r3, [r5] 7172 0022 1E22 movs r2, #30 7173 0024 2146 mov r1, r4 7174 0026 0848 ldr r0, .L345+12 7175 .LVL636: 3007:Src/main.c **** fgoto+=DL_8; 7176 .loc 1 3007 11 view .LVU2283 7177 0028 FFF7FEFF bl Seek_Read_File 7178 .LVL637: 3008:Src/main.c **** test = Unmount_SD("/"); // 0 - succ 7179 .loc 1 3008 4 is_stmt 1 view .LVU2284 3008:Src/main.c **** test = Unmount_SD("/"); // 0 - succ 7180 .loc 1 3008 9 is_stmt 0 view .LVU2285 7181 002c 2B68 ldr r3, [r5] 7182 002e 1E33 adds r3, r3, #30 7183 0030 2B60 str r3, [r5] 3009:Src/main.c **** return test; 7184 .loc 1 3009 4 is_stmt 1 view .LVU2286 3009:Src/main.c **** return test; 7185 .loc 1 3009 11 is_stmt 0 view .LVU2287 7186 0032 0348 ldr r0, .L345+4 7187 0034 FFF7FEFF bl Unmount_SD 7188 .LVL638: 3010:Src/main.c **** } 7189 .loc 1 3010 4 is_stmt 1 view .LVU2288 3010:Src/main.c **** } 7190 .loc 1 3010 11 is_stmt 0 view .LVU2289 7191 0038 EAE7 b .L338 7192 .L346: 7193 003a 00BF .align 2 7194 .L345: 7195 003c 000C0240 .word 1073875968 7196 0040 00000000 .word .LC0 7197 0044 00000000 .word fgoto 7198 0048 00000000 .word .LC2 7199 .cfi_endproc 7200 .LFE1225: 7202 .section .text.SD_REMOVE,"ax",%progbits 7203 .align 1 7204 .global SD_REMOVE ARM GAS /tmp/ccYgfTud.s page 503 7205 .syntax unified 7206 .thumb 7207 .thumb_func 7209 SD_REMOVE: 7210 .LFB1226: 3038:Src/main.c **** int test=0; 7211 .loc 1 3038 1 is_stmt 1 view -0 7212 .cfi_startproc 7213 @ args = 0, pretend = 0, frame = 0 7214 @ frame_needed = 0, uses_anonymous_args = 0 7215 0000 10B5 push {r4, lr} 7216 .LCFI64: 7217 .cfi_def_cfa_offset 8 7218 .cfi_offset 4, -8 7219 .cfi_offset 14, -4 3039:Src/main.c **** if (HAL_GPIO_ReadPin(SDMMC1_EN_GPIO_Port, SDMMC1_EN_Pin)==GPIO_PIN_RESET) 7220 .loc 1 3039 2 view .LVU2291 7221 .LVL639: 3040:Src/main.c **** { 7222 .loc 1 3040 2 view .LVU2292 3040:Src/main.c **** { 7223 .loc 1 3040 6 is_stmt 0 view .LVU2293 7224 0002 0121 movs r1, #1 7225 0004 0B48 ldr r0, .L354 7226 0006 FFF7FEFF bl HAL_GPIO_ReadPin 7227 .LVL640: 3040:Src/main.c **** { 7228 .loc 1 3040 5 discriminator 1 view .LVU2294 7229 000a 08B1 cbz r0, .L352 3058:Src/main.c **** } 7230 .loc 1 3058 10 view .LVU2295 7231 000c 0120 movs r0, #1 7232 .LVL641: 7233 .L347: 3060:Src/main.c **** 7234 .loc 1 3060 1 view .LVU2296 7235 000e 10BD pop {r4, pc} 7236 .LVL642: 7237 .L352: 3042:Src/main.c **** if (test==FR_OK) 7238 .loc 1 3042 3 is_stmt 1 view .LVU2297 3042:Src/main.c **** if (test==FR_OK) 7239 .loc 1 3042 10 is_stmt 0 view .LVU2298 7240 0010 0948 ldr r0, .L354+4 7241 0012 FFF7FEFF bl Mount_SD 7242 .LVL643: 3043:Src/main.c **** { 7243 .loc 1 3043 3 is_stmt 1 view .LVU2299 3043:Src/main.c **** { 7244 .loc 1 3043 6 is_stmt 0 view .LVU2300 7245 0016 08B1 cbz r0, .L353 3053:Src/main.c **** } 7246 .loc 1 3053 11 view .LVU2301 7247 0018 0120 movs r0, #1 7248 .LVL644: 3053:Src/main.c **** } 7249 .loc 1 3053 11 view .LVU2302 ARM GAS /tmp/ccYgfTud.s page 504 7250 001a F8E7 b .L347 7251 .LVL645: 7252 .L353: 3045:Src/main.c **** test = Create_File("FILE1.TXT"); // 0 -suc 7253 .loc 1 3045 4 is_stmt 1 view .LVU2303 3045:Src/main.c **** test = Create_File("FILE1.TXT"); // 0 -suc 7254 .loc 1 3045 11 is_stmt 0 view .LVU2304 7255 001c 074C ldr r4, .L354+8 7256 001e 2046 mov r0, r4 7257 .LVL646: 3045:Src/main.c **** test = Create_File("FILE1.TXT"); // 0 -suc 7258 .loc 1 3045 11 view .LVU2305 7259 0020 FFF7FEFF bl Remove_File 7260 .LVL647: 3046:Src/main.c **** //test = Write_File ("FILE1.TXT", "____OSGG main borad information. Program made by Kazakov Vikt 7261 .loc 1 3046 4 is_stmt 1 view .LVU2306 3046:Src/main.c **** //test = Write_File ("FILE1.TXT", "____OSGG main borad information. Program made by Kazakov Vikt 7262 .loc 1 3046 11 is_stmt 0 view .LVU2307 7263 0024 2046 mov r0, r4 7264 0026 FFF7FEFF bl Create_File 7265 .LVL648: 3048:Src/main.c **** return test; 7266 .loc 1 3048 4 is_stmt 1 view .LVU2308 3048:Src/main.c **** return test; 7267 .loc 1 3048 11 is_stmt 0 view .LVU2309 7268 002a 0348 ldr r0, .L354+4 7269 002c FFF7FEFF bl Unmount_SD 7270 .LVL649: 3049:Src/main.c **** } 7271 .loc 1 3049 4 is_stmt 1 view .LVU2310 3049:Src/main.c **** } 7272 .loc 1 3049 11 is_stmt 0 view .LVU2311 7273 0030 EDE7 b .L347 7274 .L355: 7275 0032 00BF .align 2 7276 .L354: 7277 0034 000C0240 .word 1073875968 7278 0038 00000000 .word .LC0 7279 003c 00000000 .word .LC2 7280 .cfi_endproc 7281 .LFE1226: 7283 .section .text.USART_TX,"ax",%progbits 7284 .align 1 7285 .global USART_TX 7286 .syntax unified 7287 .thumb 7288 .thumb_func 7290 USART_TX: 7291 .LVL650: 7292 .LFB1227: 3064:Src/main.c **** uint16_t ind = 0; 7293 .loc 1 3064 1 is_stmt 1 view -0 7294 .cfi_startproc 7295 @ args = 0, pretend = 0, frame = 0 7296 @ frame_needed = 0, uses_anonymous_args = 0 7297 @ link register save eliminated. 3064:Src/main.c **** uint16_t ind = 0; ARM GAS /tmp/ccYgfTud.s page 505 7298 .loc 1 3064 1 is_stmt 0 view .LVU2313 7299 0000 8C46 mov ip, r1 3065:Src/main.c **** while (indCR3, USART_CR3_DMAT); 3570:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 3571:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3572:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 3573:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if DMA Mode is enabled for transmission 3574:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 DMAT LL_USART_IsEnabledDMAReq_TX 3575:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 3576:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). 3577:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3578:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_TX(const USART_TypeDef *USARTx) 3579:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 3580:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->CR3, USART_CR3_DMAT) == (USART_CR3_DMAT)) ? 1UL : 0UL); 3581:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 3582:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3583:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 3584:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Enable DMA Disabling on Reception Error 3585:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 DDRE LL_USART_EnableDMADeactOnRxErr 3586:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 3587:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 3588:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3589:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableDMADeactOnRxErr(USART_TypeDef *USARTx) 3590:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 3591:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** SET_BIT(USARTx->CR3, USART_CR3_DDRE); 3592:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 3593:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3594:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 3595:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Disable DMA Disabling on Reception Error 3596:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 DDRE LL_USART_DisableDMADeactOnRxErr 3597:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 3598:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 3599:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3600:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableDMADeactOnRxErr(USART_TypeDef *USARTx) 3601:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 3602:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** CLEAR_BIT(USARTx->CR3, USART_CR3_DDRE); 3603:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 3604:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3605:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 3606:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Indicate if DMA Disabling on Reception Error is disabled 3607:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 DDRE LL_USART_IsEnabledDMADeactOnRxErr 3608:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 3609:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). 3610:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3611:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledDMADeactOnRxErr(const USART_TypeDef *USARTx) 3612:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 3613:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->CR3, USART_CR3_DDRE) == (USART_CR3_DDRE)) ? 1UL : 0UL); 3614:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 3615:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3616:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 3617:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Get the data register address used for DMA transfer ARM GAS /tmp/ccYgfTud.s page 507 3618:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll RDR RDR LL_USART_DMA_GetRegAddr\n 3619:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll TDR TDR LL_USART_DMA_GetRegAddr 3620:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 3621:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param Direction This parameter can be one of the following values: 3622:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_DMA_REG_DATA_TRANSMIT 3623:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_DMA_REG_DATA_RECEIVE 3624:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Address of data register 3625:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3626:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_DMA_GetRegAddr(const USART_TypeDef *USARTx, uint32_t Direction) 3627:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 3628:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** uint32_t data_reg_addr; 3629:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3630:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** if (Direction == LL_USART_DMA_REG_DATA_TRANSMIT) 3631:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 3632:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* return address of TDR register */ 3633:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** data_reg_addr = (uint32_t) &(USARTx->TDR); 3634:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 3635:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** else 3636:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 3637:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* return address of RDR register */ 3638:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** data_reg_addr = (uint32_t) &(USARTx->RDR); 3639:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 3640:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3641:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return data_reg_addr; 3642:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 3643:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3644:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 3645:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} 3646:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3647:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3648:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EF_Data_Management Data_Management 3649:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ 3650:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3651:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3652:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 3653:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Read Receiver Data register (Receive Data value, 8 bits) 3654:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll RDR RDR LL_USART_ReceiveData8 3655:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 3656:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Value between Min_Data=0x00 and Max_Data=0xFF 3657:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3658:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint8_t LL_USART_ReceiveData8(const USART_TypeDef *USARTx) 3659:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 3660:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return (uint8_t)(READ_BIT(USARTx->RDR, USART_RDR_RDR) & 0xFFU); 3661:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 3662:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3663:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 3664:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Read Receiver Data register (Receive Data value, 9 bits) 3665:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll RDR RDR LL_USART_ReceiveData9 3666:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 3667:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Value between Min_Data=0x00 and Max_Data=0x1FF 3668:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3669:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint16_t LL_USART_ReceiveData9(const USART_TypeDef *USARTx) 3670:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 3671:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return (uint16_t)(READ_BIT(USARTx->RDR, USART_RDR_RDR)); 3672:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 3673:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3674:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** ARM GAS /tmp/ccYgfTud.s page 508 3675:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Write in Transmitter Data Register (Transmit Data value, 8 bits) 3676:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll TDR TDR LL_USART_TransmitData8 3677:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 3678:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param Value between Min_Data=0x00 and Max_Data=0xFF 3679:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 3680:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3681:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_TransmitData8(USART_TypeDef *USARTx, uint8_t Value) 7339 .loc 7 3681 22 view .LVU2328 7340 .LBB577: 3682:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 3683:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** USARTx->TDR = Value; 7341 .loc 7 3683 3 view .LVU2329 7342 .loc 7 3683 15 is_stmt 0 view .LVU2330 7343 0018 034B ldr r3, .L361 7344 001a 9962 str r1, [r3, #40] 7345 .LVL656: 7346 .loc 7 3683 15 view .LVU2331 7347 .LBE577: 7348 .LBE576: 3070:Src/main.c **** } 7349 .loc 1 3070 5 is_stmt 1 view .LVU2332 3070:Src/main.c **** } 7350 .loc 1 3070 8 is_stmt 0 view .LVU2333 7351 001c 0132 adds r2, r2, #1 7352 .LVL657: 3070:Src/main.c **** } 7353 .loc 1 3070 8 view .LVU2334 7354 001e 92B2 uxth r2, r2 7355 .LVL658: 7356 .L357: 3066:Src/main.c **** { 7357 .loc 1 3066 13 is_stmt 1 view .LVU2335 7358 0020 6245 cmp r2, ip 7359 0022 F1D3 bcc .L359 3072:Src/main.c **** 7360 .loc 1 3072 1 is_stmt 0 view .LVU2336 7361 0024 7047 bx lr 7362 .L362: 7363 0026 00BF .align 2 7364 .L361: 7365 0028 00100140 .word 1073811456 7366 .cfi_endproc 7367 .LFE1227: 7369 .section .text.USART_TX_DMA,"ax",%progbits 7370 .align 1 7371 .global USART_TX_DMA 7372 .syntax unified 7373 .thumb 7374 .thumb_func 7376 USART_TX_DMA: 7377 .LFB1228: 3075:Src/main.c **** while (u_tx_flg) {}//Wait until previous transfer not complete. u_tx_flg is resetting in DMA inter 7378 .loc 1 3075 1 is_stmt 1 view -0 7379 .cfi_startproc 7380 @ args = 0, pretend = 0, frame = 0 7381 @ frame_needed = 0, uses_anonymous_args = 0 7382 @ link register save eliminated. ARM GAS /tmp/ccYgfTud.s page 509 7383 .LVL659: 7384 .L364: 3076:Src/main.c **** LL_DMA_DisableStream(DMA2, LL_DMA_STREAM_7); 7385 .loc 1 3076 20 discriminator 1 view .LVU2338 3076:Src/main.c **** LL_DMA_DisableStream(DMA2, LL_DMA_STREAM_7); 7386 .loc 1 3076 9 discriminator 1 view .LVU2339 7387 0000 0D4B ldr r3, .L365 7388 0002 1B78 ldrb r3, [r3] @ zero_extendqisi2 7389 0004 002B cmp r3, #0 7390 0006 FBD1 bne .L364 3077:Src/main.c **** LL_DMA_SetDataLength(DMA2, LL_DMA_STREAM_7, sz); 7391 .loc 1 3077 2 view .LVU2340 7392 .LVL660: 7393 .LBB578: 7394 .LBI578: 517:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 7395 .loc 6 517 22 view .LVU2341 7396 .LBB579: 519:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 7397 .loc 6 519 3 view .LVU2342 7398 0008 0C4B ldr r3, .L365+4 7399 000a D3F8B820 ldr r2, [r3, #184] 7400 000e 22F00102 bic r2, r2, #1 7401 0012 C3F8B820 str r2, [r3, #184] 7402 .LVL661: 519:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 7403 .loc 6 519 3 is_stmt 0 view .LVU2343 7404 .LBE579: 7405 .LBE578: 3078:Src/main.c **** LL_DMA_EnableStream(DMA2, LL_DMA_STREAM_7); 7406 .loc 1 3078 3 is_stmt 1 view .LVU2344 7407 .LBB580: 7408 .LBI580: 971:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 7409 .loc 6 971 22 view .LVU2345 7410 .LBB581: 973:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 7411 .loc 6 973 3 view .LVU2346 7412 0016 D3F8BC20 ldr r2, [r3, #188] 7413 001a 6FF30F02 bfc r2, #0, #16 7414 001e 1043 orrs r0, r0, r2 7415 .LVL662: 973:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 7416 .loc 6 973 3 is_stmt 0 view .LVU2347 7417 0020 C3F8BC00 str r0, [r3, #188] 7418 .LVL663: 973:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 7419 .loc 6 973 3 view .LVU2348 7420 .LBE581: 7421 .LBE580: 3079:Src/main.c **** u_tx_flg = 1;//indicate that transfer begin 7422 .loc 1 3079 3 is_stmt 1 view .LVU2349 7423 .LBB582: 7424 .LBI582: 497:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 7425 .loc 6 497 22 view .LVU2350 7426 .LBB583: ARM GAS /tmp/ccYgfTud.s page 510 499:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 7427 .loc 6 499 3 view .LVU2351 7428 0024 D3F8B820 ldr r2, [r3, #184] 7429 0028 42F00102 orr r2, r2, #1 7430 002c C3F8B820 str r2, [r3, #184] 7431 .LVL664: 499:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 7432 .loc 6 499 3 is_stmt 0 view .LVU2352 7433 .LBE583: 7434 .LBE582: 3080:Src/main.c **** } 7435 .loc 1 3080 2 is_stmt 1 view .LVU2353 3080:Src/main.c **** } 7436 .loc 1 3080 11 is_stmt 0 view .LVU2354 7437 0030 014B ldr r3, .L365 7438 0032 0122 movs r2, #1 7439 0034 1A70 strb r2, [r3] 3081:Src/main.c **** 7440 .loc 1 3081 1 view .LVU2355 7441 0036 7047 bx lr 7442 .L366: 7443 .align 2 7444 .L365: 7445 0038 00000000 .word u_tx_flg 7446 003c 00640240 .word 1073898496 7447 .cfi_endproc 7448 .LFE1228: 7450 .section .text.Error_Handler,"ax",%progbits 7451 .align 1 7452 .global Error_Handler 7453 .syntax unified 7454 .thumb 7455 .thumb_func 7457 Error_Handler: 7458 .LFB1230: 3089:Src/main.c **** //------------------------------------------------------- 3090:Src/main.c **** /* USER CODE END 4 */ 3091:Src/main.c **** 3092:Src/main.c **** /** 3093:Src/main.c **** * @brief This function is executed in case of error occurrence. 3094:Src/main.c **** * @retval None 3095:Src/main.c **** */ 3096:Src/main.c **** void Error_Handler(void) 3097:Src/main.c **** { 7459 .loc 1 3097 1 is_stmt 1 view -0 7460 .cfi_startproc 7461 @ Volatile: function does not return. 7462 @ args = 0, pretend = 0, frame = 0 7463 @ frame_needed = 0, uses_anonymous_args = 0 7464 @ link register save eliminated. 3098:Src/main.c **** /* USER CODE BEGIN Error_Handler_Debug */ 3099:Src/main.c **** /* User can add his own implementation to report the HAL error return state */ 3100:Src/main.c **** __disable_irq(); 7465 .loc 1 3100 3 view .LVU2357 7466 .LBB584: 7467 .LBI584: 140:Drivers/CMSIS/Include/cmsis_gcc.h **** { ARM GAS /tmp/ccYgfTud.s page 511 7468 .loc 8 140 27 view .LVU2358 7469 .LBB585: 142:Drivers/CMSIS/Include/cmsis_gcc.h **** } 7470 .loc 8 142 3 view .LVU2359 7471 .syntax unified 7472 @ 142 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 7473 0000 72B6 cpsid i 7474 @ 0 "" 2 7475 .thumb 7476 .syntax unified 7477 .L368: 7478 .LBE585: 7479 .LBE584: 3101:Src/main.c **** while (1) 7480 .loc 1 3101 3 view .LVU2360 3102:Src/main.c **** { 3103:Src/main.c **** } 7481 .loc 1 3103 3 view .LVU2361 3101:Src/main.c **** while (1) 7482 .loc 1 3101 9 view .LVU2362 7483 0002 FEE7 b .L368 7484 .cfi_endproc 7485 .LFE1230: 7487 .section .text.MX_ADC1_Init,"ax",%progbits 7488 .align 1 7489 .syntax unified 7490 .thumb 7491 .thumb_func 7493 MX_ADC1_Init: 7494 .LFB1188: 939:Src/main.c **** 7495 .loc 1 939 1 view -0 7496 .cfi_startproc 7497 @ args = 0, pretend = 0, frame = 16 7498 @ frame_needed = 0, uses_anonymous_args = 0 7499 0000 00B5 push {lr} 7500 .LCFI65: 7501 .cfi_def_cfa_offset 4 7502 .cfi_offset 14, -4 7503 0002 85B0 sub sp, sp, #20 7504 .LCFI66: 7505 .cfi_def_cfa_offset 24 945:Src/main.c **** 7506 .loc 1 945 3 view .LVU2364 945:Src/main.c **** 7507 .loc 1 945 26 is_stmt 0 view .LVU2365 7508 0004 0023 movs r3, #0 7509 0006 0093 str r3, [sp] 7510 0008 0193 str r3, [sp, #4] 7511 000a 0293 str r3, [sp, #8] 7512 000c 0393 str r3, [sp, #12] 953:Src/main.c **** hadc1.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV8; 7513 .loc 1 953 3 is_stmt 1 view .LVU2366 953:Src/main.c **** hadc1.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV8; 7514 .loc 1 953 18 is_stmt 0 view .LVU2367 7515 000e 2B48 ldr r0, .L383 7516 0010 2B4A ldr r2, .L383+4 ARM GAS /tmp/ccYgfTud.s page 512 7517 0012 0260 str r2, [r0] 954:Src/main.c **** hadc1.Init.Resolution = ADC_RESOLUTION_12B; 7518 .loc 1 954 3 is_stmt 1 view .LVU2368 954:Src/main.c **** hadc1.Init.Resolution = ADC_RESOLUTION_12B; 7519 .loc 1 954 29 is_stmt 0 view .LVU2369 7520 0014 4FF44032 mov r2, #196608 7521 0018 4260 str r2, [r0, #4] 955:Src/main.c **** hadc1.Init.ScanConvMode = ADC_SCAN_ENABLE; 7522 .loc 1 955 3 is_stmt 1 view .LVU2370 955:Src/main.c **** hadc1.Init.ScanConvMode = ADC_SCAN_ENABLE; 7523 .loc 1 955 25 is_stmt 0 view .LVU2371 7524 001a 8360 str r3, [r0, #8] 956:Src/main.c **** hadc1.Init.ContinuousConvMode = DISABLE; 7525 .loc 1 956 3 is_stmt 1 view .LVU2372 956:Src/main.c **** hadc1.Init.ContinuousConvMode = DISABLE; 7526 .loc 1 956 27 is_stmt 0 view .LVU2373 7527 001c 0122 movs r2, #1 7528 001e 0261 str r2, [r0, #16] 957:Src/main.c **** hadc1.Init.DiscontinuousConvMode = DISABLE; 7529 .loc 1 957 3 is_stmt 1 view .LVU2374 957:Src/main.c **** hadc1.Init.DiscontinuousConvMode = DISABLE; 7530 .loc 1 957 33 is_stmt 0 view .LVU2375 7531 0020 8361 str r3, [r0, #24] 958:Src/main.c **** hadc1.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE; 7532 .loc 1 958 3 is_stmt 1 view .LVU2376 958:Src/main.c **** hadc1.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE; 7533 .loc 1 958 36 is_stmt 0 view .LVU2377 7534 0022 80F82030 strb r3, [r0, #32] 959:Src/main.c **** hadc1.Init.ExternalTrigConv = ADC_SOFTWARE_START; 7535 .loc 1 959 3 is_stmt 1 view .LVU2378 959:Src/main.c **** hadc1.Init.ExternalTrigConv = ADC_SOFTWARE_START; 7536 .loc 1 959 35 is_stmt 0 view .LVU2379 7537 0026 C362 str r3, [r0, #44] 960:Src/main.c **** hadc1.Init.DataAlign = ADC_DATAALIGN_RIGHT; 7538 .loc 1 960 3 is_stmt 1 view .LVU2380 960:Src/main.c **** hadc1.Init.DataAlign = ADC_DATAALIGN_RIGHT; 7539 .loc 1 960 31 is_stmt 0 view .LVU2381 7540 0028 2649 ldr r1, .L383+8 7541 002a 8162 str r1, [r0, #40] 961:Src/main.c **** hadc1.Init.NbrOfConversion = 5; 7542 .loc 1 961 3 is_stmt 1 view .LVU2382 961:Src/main.c **** hadc1.Init.NbrOfConversion = 5; 7543 .loc 1 961 24 is_stmt 0 view .LVU2383 7544 002c C360 str r3, [r0, #12] 962:Src/main.c **** hadc1.Init.DMAContinuousRequests = DISABLE; 7545 .loc 1 962 3 is_stmt 1 view .LVU2384 962:Src/main.c **** hadc1.Init.DMAContinuousRequests = DISABLE; 7546 .loc 1 962 30 is_stmt 0 view .LVU2385 7547 002e 0521 movs r1, #5 7548 0030 C161 str r1, [r0, #28] 963:Src/main.c **** hadc1.Init.EOCSelection = ADC_EOC_SINGLE_CONV; 7549 .loc 1 963 3 is_stmt 1 view .LVU2386 963:Src/main.c **** hadc1.Init.EOCSelection = ADC_EOC_SINGLE_CONV; 7550 .loc 1 963 36 is_stmt 0 view .LVU2387 7551 0032 80F83030 strb r3, [r0, #48] 964:Src/main.c **** if (HAL_ADC_Init(&hadc1) != HAL_OK) 7552 .loc 1 964 3 is_stmt 1 view .LVU2388 ARM GAS /tmp/ccYgfTud.s page 513 964:Src/main.c **** if (HAL_ADC_Init(&hadc1) != HAL_OK) 7553 .loc 1 964 27 is_stmt 0 view .LVU2389 7554 0036 4261 str r2, [r0, #20] 965:Src/main.c **** { 7555 .loc 1 965 3 is_stmt 1 view .LVU2390 965:Src/main.c **** { 7556 .loc 1 965 7 is_stmt 0 view .LVU2391 7557 0038 FFF7FEFF bl HAL_ADC_Init 7558 .LVL665: 965:Src/main.c **** { 7559 .loc 1 965 6 discriminator 1 view .LVU2392 7560 003c 0028 cmp r0, #0 7561 003e 31D1 bne .L377 972:Src/main.c **** sConfig.Rank = ADC_REGULAR_RANK_1; 7562 .loc 1 972 3 is_stmt 1 view .LVU2393 972:Src/main.c **** sConfig.Rank = ADC_REGULAR_RANK_1; 7563 .loc 1 972 19 is_stmt 0 view .LVU2394 7564 0040 0923 movs r3, #9 7565 0042 0093 str r3, [sp] 973:Src/main.c **** sConfig.SamplingTime = ADC_SAMPLETIME_480CYCLES; 7566 .loc 1 973 3 is_stmt 1 view .LVU2395 973:Src/main.c **** sConfig.SamplingTime = ADC_SAMPLETIME_480CYCLES; 7567 .loc 1 973 16 is_stmt 0 view .LVU2396 7568 0044 0123 movs r3, #1 7569 0046 0193 str r3, [sp, #4] 974:Src/main.c **** if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 7570 .loc 1 974 3 is_stmt 1 view .LVU2397 974:Src/main.c **** if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 7571 .loc 1 974 24 is_stmt 0 view .LVU2398 7572 0048 0723 movs r3, #7 7573 004a 0293 str r3, [sp, #8] 975:Src/main.c **** { 7574 .loc 1 975 3 is_stmt 1 view .LVU2399 975:Src/main.c **** { 7575 .loc 1 975 7 is_stmt 0 view .LVU2400 7576 004c 6946 mov r1, sp 7577 004e 1B48 ldr r0, .L383 7578 0050 FFF7FEFF bl HAL_ADC_ConfigChannel 7579 .LVL666: 975:Src/main.c **** { 7580 .loc 1 975 6 discriminator 1 view .LVU2401 7581 0054 40BB cbnz r0, .L378 982:Src/main.c **** sConfig.Rank = ADC_REGULAR_RANK_2; 7582 .loc 1 982 3 is_stmt 1 view .LVU2402 982:Src/main.c **** sConfig.Rank = ADC_REGULAR_RANK_2; 7583 .loc 1 982 19 is_stmt 0 view .LVU2403 7584 0056 0823 movs r3, #8 7585 0058 0093 str r3, [sp] 983:Src/main.c **** if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 7586 .loc 1 983 3 is_stmt 1 view .LVU2404 983:Src/main.c **** if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 7587 .loc 1 983 16 is_stmt 0 view .LVU2405 7588 005a 0223 movs r3, #2 7589 005c 0193 str r3, [sp, #4] 984:Src/main.c **** { 7590 .loc 1 984 3 is_stmt 1 view .LVU2406 984:Src/main.c **** { ARM GAS /tmp/ccYgfTud.s page 514 7591 .loc 1 984 7 is_stmt 0 view .LVU2407 7592 005e 6946 mov r1, sp 7593 0060 1648 ldr r0, .L383 7594 0062 FFF7FEFF bl HAL_ADC_ConfigChannel 7595 .LVL667: 984:Src/main.c **** { 7596 .loc 1 984 6 discriminator 1 view .LVU2408 7597 0066 08BB cbnz r0, .L379 991:Src/main.c **** sConfig.Rank = ADC_REGULAR_RANK_3; 7598 .loc 1 991 3 is_stmt 1 view .LVU2409 991:Src/main.c **** sConfig.Rank = ADC_REGULAR_RANK_3; 7599 .loc 1 991 19 is_stmt 0 view .LVU2410 7600 0068 0223 movs r3, #2 7601 006a 0093 str r3, [sp] 992:Src/main.c **** if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 7602 .loc 1 992 3 is_stmt 1 view .LVU2411 992:Src/main.c **** if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 7603 .loc 1 992 16 is_stmt 0 view .LVU2412 7604 006c 0323 movs r3, #3 7605 006e 0193 str r3, [sp, #4] 993:Src/main.c **** { 7606 .loc 1 993 3 is_stmt 1 view .LVU2413 993:Src/main.c **** { 7607 .loc 1 993 7 is_stmt 0 view .LVU2414 7608 0070 6946 mov r1, sp 7609 0072 1248 ldr r0, .L383 7610 0074 FFF7FEFF bl HAL_ADC_ConfigChannel 7611 .LVL668: 993:Src/main.c **** { 7612 .loc 1 993 6 discriminator 1 view .LVU2415 7613 0078 D0B9 cbnz r0, .L380 1000:Src/main.c **** sConfig.Rank = ADC_REGULAR_RANK_4; 7614 .loc 1 1000 3 is_stmt 1 view .LVU2416 1000:Src/main.c **** sConfig.Rank = ADC_REGULAR_RANK_4; 7615 .loc 1 1000 19 is_stmt 0 view .LVU2417 7616 007a 0A23 movs r3, #10 7617 007c 0093 str r3, [sp] 1001:Src/main.c **** if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 7618 .loc 1 1001 3 is_stmt 1 view .LVU2418 1001:Src/main.c **** if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 7619 .loc 1 1001 16 is_stmt 0 view .LVU2419 7620 007e 0423 movs r3, #4 7621 0080 0193 str r3, [sp, #4] 1002:Src/main.c **** { 7622 .loc 1 1002 3 is_stmt 1 view .LVU2420 1002:Src/main.c **** { 7623 .loc 1 1002 7 is_stmt 0 view .LVU2421 7624 0082 6946 mov r1, sp 7625 0084 0D48 ldr r0, .L383 7626 0086 FFF7FEFF bl HAL_ADC_ConfigChannel 7627 .LVL669: 1002:Src/main.c **** { 7628 .loc 1 1002 6 discriminator 1 view .LVU2422 7629 008a 98B9 cbnz r0, .L381 1009:Src/main.c **** sConfig.Rank = ADC_REGULAR_RANK_5; 7630 .loc 1 1009 3 is_stmt 1 view .LVU2423 1009:Src/main.c **** sConfig.Rank = ADC_REGULAR_RANK_5; ARM GAS /tmp/ccYgfTud.s page 515 7631 .loc 1 1009 19 is_stmt 0 view .LVU2424 7632 008c 0B23 movs r3, #11 7633 008e 0093 str r3, [sp] 1010:Src/main.c **** if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 7634 .loc 1 1010 3 is_stmt 1 view .LVU2425 1010:Src/main.c **** if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 7635 .loc 1 1010 16 is_stmt 0 view .LVU2426 7636 0090 0523 movs r3, #5 7637 0092 0193 str r3, [sp, #4] 1011:Src/main.c **** { 7638 .loc 1 1011 3 is_stmt 1 view .LVU2427 1011:Src/main.c **** { 7639 .loc 1 1011 7 is_stmt 0 view .LVU2428 7640 0094 6946 mov r1, sp 7641 0096 0948 ldr r0, .L383 7642 0098 FFF7FEFF bl HAL_ADC_ConfigChannel 7643 .LVL670: 1011:Src/main.c **** { 7644 .loc 1 1011 6 discriminator 1 view .LVU2429 7645 009c 60B9 cbnz r0, .L382 1019:Src/main.c **** 7646 .loc 1 1019 1 view .LVU2430 7647 009e 05B0 add sp, sp, #20 7648 .LCFI67: 7649 .cfi_remember_state 7650 .cfi_def_cfa_offset 4 7651 @ sp needed 7652 00a0 5DF804FB ldr pc, [sp], #4 7653 .L377: 7654 .LCFI68: 7655 .cfi_restore_state 967:Src/main.c **** } 7656 .loc 1 967 5 is_stmt 1 view .LVU2431 7657 00a4 FFF7FEFF bl Error_Handler 7658 .LVL671: 7659 .L378: 977:Src/main.c **** } 7660 .loc 1 977 5 view .LVU2432 7661 00a8 FFF7FEFF bl Error_Handler 7662 .LVL672: 7663 .L379: 986:Src/main.c **** } 7664 .loc 1 986 5 view .LVU2433 7665 00ac FFF7FEFF bl Error_Handler 7666 .LVL673: 7667 .L380: 995:Src/main.c **** } 7668 .loc 1 995 5 view .LVU2434 7669 00b0 FFF7FEFF bl Error_Handler 7670 .LVL674: 7671 .L381: 1004:Src/main.c **** } 7672 .loc 1 1004 5 view .LVU2435 7673 00b4 FFF7FEFF bl Error_Handler 7674 .LVL675: 7675 .L382: 1013:Src/main.c **** } ARM GAS /tmp/ccYgfTud.s page 516 7676 .loc 1 1013 5 view .LVU2436 7677 00b8 FFF7FEFF bl Error_Handler 7678 .LVL676: 7679 .L384: 7680 .align 2 7681 .L383: 7682 00bc 00000000 .word hadc1 7683 00c0 00200140 .word 1073815552 7684 00c4 0100000F .word 251658241 7685 .cfi_endproc 7686 .LFE1188: 7688 .section .text.MX_ADC3_Init,"ax",%progbits 7689 .align 1 7690 .syntax unified 7691 .thumb 7692 .thumb_func 7694 MX_ADC3_Init: 7695 .LFB1189: 1027:Src/main.c **** 7696 .loc 1 1027 1 view -0 7697 .cfi_startproc 7698 @ args = 0, pretend = 0, frame = 16 7699 @ frame_needed = 0, uses_anonymous_args = 0 7700 0000 00B5 push {lr} 7701 .LCFI69: 7702 .cfi_def_cfa_offset 4 7703 .cfi_offset 14, -4 7704 0002 85B0 sub sp, sp, #20 7705 .LCFI70: 7706 .cfi_def_cfa_offset 24 1033:Src/main.c **** 7707 .loc 1 1033 3 view .LVU2438 1033:Src/main.c **** 7708 .loc 1 1033 26 is_stmt 0 view .LVU2439 7709 0004 0023 movs r3, #0 7710 0006 0093 str r3, [sp] 7711 0008 0193 str r3, [sp, #4] 7712 000a 0293 str r3, [sp, #8] 7713 000c 0393 str r3, [sp, #12] 1041:Src/main.c **** hadc3.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV8; 7714 .loc 1 1041 3 is_stmt 1 view .LVU2440 1041:Src/main.c **** hadc3.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV8; 7715 .loc 1 1041 18 is_stmt 0 view .LVU2441 7716 000e 1448 ldr r0, .L391 7717 0010 144A ldr r2, .L391+4 7718 0012 0260 str r2, [r0] 1042:Src/main.c **** hadc3.Init.Resolution = ADC_RESOLUTION_12B; 7719 .loc 1 1042 3 is_stmt 1 view .LVU2442 1042:Src/main.c **** hadc3.Init.Resolution = ADC_RESOLUTION_12B; 7720 .loc 1 1042 29 is_stmt 0 view .LVU2443 7721 0014 4FF44032 mov r2, #196608 7722 0018 4260 str r2, [r0, #4] 1043:Src/main.c **** hadc3.Init.ScanConvMode = ADC_SCAN_DISABLE; 7723 .loc 1 1043 3 is_stmt 1 view .LVU2444 1043:Src/main.c **** hadc3.Init.ScanConvMode = ADC_SCAN_DISABLE; 7724 .loc 1 1043 25 is_stmt 0 view .LVU2445 7725 001a 8360 str r3, [r0, #8] ARM GAS /tmp/ccYgfTud.s page 517 1044:Src/main.c **** hadc3.Init.ContinuousConvMode = DISABLE; 7726 .loc 1 1044 3 is_stmt 1 view .LVU2446 1044:Src/main.c **** hadc3.Init.ContinuousConvMode = DISABLE; 7727 .loc 1 1044 27 is_stmt 0 view .LVU2447 7728 001c 0361 str r3, [r0, #16] 1045:Src/main.c **** hadc3.Init.DiscontinuousConvMode = DISABLE; 7729 .loc 1 1045 3 is_stmt 1 view .LVU2448 1045:Src/main.c **** hadc3.Init.DiscontinuousConvMode = DISABLE; 7730 .loc 1 1045 33 is_stmt 0 view .LVU2449 7731 001e 8361 str r3, [r0, #24] 1046:Src/main.c **** hadc3.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE; 7732 .loc 1 1046 3 is_stmt 1 view .LVU2450 1046:Src/main.c **** hadc3.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE; 7733 .loc 1 1046 36 is_stmt 0 view .LVU2451 7734 0020 80F82030 strb r3, [r0, #32] 1047:Src/main.c **** hadc3.Init.ExternalTrigConv = ADC_SOFTWARE_START; 7735 .loc 1 1047 3 is_stmt 1 view .LVU2452 1047:Src/main.c **** hadc3.Init.ExternalTrigConv = ADC_SOFTWARE_START; 7736 .loc 1 1047 35 is_stmt 0 view .LVU2453 7737 0024 C362 str r3, [r0, #44] 1048:Src/main.c **** hadc3.Init.DataAlign = ADC_DATAALIGN_RIGHT; 7738 .loc 1 1048 3 is_stmt 1 view .LVU2454 1048:Src/main.c **** hadc3.Init.DataAlign = ADC_DATAALIGN_RIGHT; 7739 .loc 1 1048 31 is_stmt 0 view .LVU2455 7740 0026 104A ldr r2, .L391+8 7741 0028 8262 str r2, [r0, #40] 1049:Src/main.c **** hadc3.Init.NbrOfConversion = 1; 7742 .loc 1 1049 3 is_stmt 1 view .LVU2456 1049:Src/main.c **** hadc3.Init.NbrOfConversion = 1; 7743 .loc 1 1049 24 is_stmt 0 view .LVU2457 7744 002a C360 str r3, [r0, #12] 1050:Src/main.c **** hadc3.Init.DMAContinuousRequests = DISABLE; 7745 .loc 1 1050 3 is_stmt 1 view .LVU2458 1050:Src/main.c **** hadc3.Init.DMAContinuousRequests = DISABLE; 7746 .loc 1 1050 30 is_stmt 0 view .LVU2459 7747 002c 0122 movs r2, #1 7748 002e C261 str r2, [r0, #28] 1051:Src/main.c **** hadc3.Init.EOCSelection = ADC_EOC_SINGLE_CONV; 7749 .loc 1 1051 3 is_stmt 1 view .LVU2460 1051:Src/main.c **** hadc3.Init.EOCSelection = ADC_EOC_SINGLE_CONV; 7750 .loc 1 1051 36 is_stmt 0 view .LVU2461 7751 0030 80F83030 strb r3, [r0, #48] 1052:Src/main.c **** if (HAL_ADC_Init(&hadc3) != HAL_OK) 7752 .loc 1 1052 3 is_stmt 1 view .LVU2462 1052:Src/main.c **** if (HAL_ADC_Init(&hadc3) != HAL_OK) 7753 .loc 1 1052 27 is_stmt 0 view .LVU2463 7754 0034 4261 str r2, [r0, #20] 1053:Src/main.c **** { 7755 .loc 1 1053 3 is_stmt 1 view .LVU2464 1053:Src/main.c **** { 7756 .loc 1 1053 7 is_stmt 0 view .LVU2465 7757 0036 FFF7FEFF bl HAL_ADC_Init 7758 .LVL677: 1053:Src/main.c **** { 7759 .loc 1 1053 6 discriminator 1 view .LVU2466 7760 003a 68B9 cbnz r0, .L389 1060:Src/main.c **** sConfig.Rank = ADC_REGULAR_RANK_1; ARM GAS /tmp/ccYgfTud.s page 518 7761 .loc 1 1060 3 is_stmt 1 view .LVU2467 1060:Src/main.c **** sConfig.Rank = ADC_REGULAR_RANK_1; 7762 .loc 1 1060 19 is_stmt 0 view .LVU2468 7763 003c 0F23 movs r3, #15 7764 003e 0093 str r3, [sp] 1061:Src/main.c **** sConfig.SamplingTime = ADC_SAMPLETIME_480CYCLES; 7765 .loc 1 1061 3 is_stmt 1 view .LVU2469 1061:Src/main.c **** sConfig.SamplingTime = ADC_SAMPLETIME_480CYCLES; 7766 .loc 1 1061 16 is_stmt 0 view .LVU2470 7767 0040 0123 movs r3, #1 7768 0042 0193 str r3, [sp, #4] 1062:Src/main.c **** if (HAL_ADC_ConfigChannel(&hadc3, &sConfig) != HAL_OK) 7769 .loc 1 1062 3 is_stmt 1 view .LVU2471 1062:Src/main.c **** if (HAL_ADC_ConfigChannel(&hadc3, &sConfig) != HAL_OK) 7770 .loc 1 1062 24 is_stmt 0 view .LVU2472 7771 0044 0723 movs r3, #7 7772 0046 0293 str r3, [sp, #8] 1063:Src/main.c **** { 7773 .loc 1 1063 3 is_stmt 1 view .LVU2473 1063:Src/main.c **** { 7774 .loc 1 1063 7 is_stmt 0 view .LVU2474 7775 0048 6946 mov r1, sp 7776 004a 0548 ldr r0, .L391 7777 004c FFF7FEFF bl HAL_ADC_ConfigChannel 7778 .LVL678: 1063:Src/main.c **** { 7779 .loc 1 1063 6 discriminator 1 view .LVU2475 7780 0050 20B9 cbnz r0, .L390 1071:Src/main.c **** 7781 .loc 1 1071 1 view .LVU2476 7782 0052 05B0 add sp, sp, #20 7783 .LCFI71: 7784 .cfi_remember_state 7785 .cfi_def_cfa_offset 4 7786 @ sp needed 7787 0054 5DF804FB ldr pc, [sp], #4 7788 .L389: 7789 .LCFI72: 7790 .cfi_restore_state 1055:Src/main.c **** } 7791 .loc 1 1055 5 is_stmt 1 view .LVU2477 7792 0058 FFF7FEFF bl Error_Handler 7793 .LVL679: 7794 .L390: 1065:Src/main.c **** } 7795 .loc 1 1065 5 view .LVU2478 7796 005c FFF7FEFF bl Error_Handler 7797 .LVL680: 7798 .L392: 7799 .align 2 7800 .L391: 7801 0060 00000000 .word hadc3 7802 0064 00220140 .word 1073816064 7803 0068 0100000F .word 251658241 7804 .cfi_endproc 7805 .LFE1189: 7807 .section .text.MX_USART1_UART_Init,"ax",%progbits ARM GAS /tmp/ccYgfTud.s page 519 7808 .align 1 7809 .syntax unified 7810 .thumb 7811 .thumb_func 7813 MX_USART1_UART_Init: 7814 .LFB1204: 1738:Src/main.c **** 7815 .loc 1 1738 1 view -0 7816 .cfi_startproc 7817 @ args = 0, pretend = 0, frame = 208 7818 @ frame_needed = 0, uses_anonymous_args = 0 7819 0000 2DE9F041 push {r4, r5, r6, r7, r8, lr} 7820 .LCFI73: 7821 .cfi_def_cfa_offset 24 7822 .cfi_offset 4, -24 7823 .cfi_offset 5, -20 7824 .cfi_offset 6, -16 7825 .cfi_offset 7, -12 7826 .cfi_offset 8, -8 7827 .cfi_offset 14, -4 7828 0004 B4B0 sub sp, sp, #208 7829 .LCFI74: 7830 .cfi_def_cfa_offset 232 1744:Src/main.c **** 7831 .loc 1 1744 3 view .LVU2480 1744:Src/main.c **** 7832 .loc 1 1744 24 is_stmt 0 view .LVU2481 7833 0006 0021 movs r1, #0 7834 0008 2D91 str r1, [sp, #180] 7835 000a 2E91 str r1, [sp, #184] 7836 000c 2F91 str r1, [sp, #188] 7837 000e 3091 str r1, [sp, #192] 7838 0010 3191 str r1, [sp, #196] 7839 0012 3291 str r1, [sp, #200] 7840 0014 3391 str r1, [sp, #204] 1746:Src/main.c **** RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; 7841 .loc 1 1746 3 is_stmt 1 view .LVU2482 1746:Src/main.c **** RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; 7842 .loc 1 1746 23 is_stmt 0 view .LVU2483 7843 0016 2791 str r1, [sp, #156] 7844 0018 2891 str r1, [sp, #160] 7845 001a 2991 str r1, [sp, #164] 7846 001c 2A91 str r1, [sp, #168] 7847 001e 2B91 str r1, [sp, #172] 7848 0020 2C91 str r1, [sp, #176] 1747:Src/main.c **** 7849 .loc 1 1747 3 is_stmt 1 view .LVU2484 1747:Src/main.c **** 7850 .loc 1 1747 28 is_stmt 0 view .LVU2485 7851 0022 9022 movs r2, #144 7852 0024 03A8 add r0, sp, #12 7853 0026 FFF7FEFF bl memset 7854 .LVL681: 1751:Src/main.c **** PeriphClkInitStruct.Usart1ClockSelection = RCC_USART1CLKSOURCE_PCLK2; 7855 .loc 1 1751 3 is_stmt 1 view .LVU2486 1751:Src/main.c **** PeriphClkInitStruct.Usart1ClockSelection = RCC_USART1CLKSOURCE_PCLK2; 7856 .loc 1 1751 44 is_stmt 0 view .LVU2487 ARM GAS /tmp/ccYgfTud.s page 520 7857 002a 4023 movs r3, #64 7858 002c 0393 str r3, [sp, #12] 1752:Src/main.c **** if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) 7859 .loc 1 1752 3 is_stmt 1 view .LVU2488 1753:Src/main.c **** { 7860 .loc 1 1753 3 view .LVU2489 1753:Src/main.c **** { 7861 .loc 1 1753 7 is_stmt 0 view .LVU2490 7862 002e 03A8 add r0, sp, #12 7863 0030 FFF7FEFF bl HAL_RCCEx_PeriphCLKConfig 7864 .LVL682: 1753:Src/main.c **** { 7865 .loc 1 1753 6 discriminator 1 view .LVU2491 7866 0034 0028 cmp r0, #0 7867 0036 40F09E80 bne .L396 1759:Src/main.c **** 7868 .loc 1 1759 3 is_stmt 1 view .LVU2492 7869 .LVL683: 7870 .LBB586: 7871 .LBI586: 1587:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { 7872 .loc 3 1587 22 view .LVU2493 7873 .LBB587: 1589:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** SET_BIT(RCC->APB2ENR, Periphs); 7874 .loc 3 1589 3 view .LVU2494 1590:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Delay after an RCC peripheral clock enabling */ 7875 .loc 3 1590 3 view .LVU2495 7876 003a 504B ldr r3, .L397 7877 003c 5A6C ldr r2, [r3, #68] 7878 003e 42F01002 orr r2, r2, #16 7879 0042 5A64 str r2, [r3, #68] 1592:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; 7880 .loc 3 1592 3 view .LVU2496 1592:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; 7881 .loc 3 1592 12 is_stmt 0 view .LVU2497 7882 0044 5A6C ldr r2, [r3, #68] 7883 0046 02F01002 and r2, r2, #16 1592:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; 7884 .loc 3 1592 10 view .LVU2498 7885 004a 0292 str r2, [sp, #8] 7886 .loc 3 1593 3 is_stmt 1 view .LVU2499 7887 004c 029A ldr r2, [sp, #8] 7888 .LVL684: 7889 .loc 3 1593 3 is_stmt 0 view .LVU2500 7890 .LBE587: 7891 .LBE586: 1761:Src/main.c **** /**USART1 GPIO Configuration 7892 .loc 1 1761 3 is_stmt 1 view .LVU2501 7893 .LBB588: 7894 .LBI588: 309:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { 7895 .loc 3 309 22 view .LVU2502 7896 .LBB589: 311:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** SET_BIT(RCC->AHB1ENR, Periphs); 7897 .loc 3 311 3 view .LVU2503 312:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Delay after an RCC peripheral clock enabling */ 7898 .loc 3 312 3 view .LVU2504 ARM GAS /tmp/ccYgfTud.s page 521 7899 004e 1A6B ldr r2, [r3, #48] 7900 0050 42F00102 orr r2, r2, #1 7901 0054 1A63 str r2, [r3, #48] 314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; 7902 .loc 3 314 3 view .LVU2505 314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; 7903 .loc 3 314 12 is_stmt 0 view .LVU2506 7904 0056 1B6B ldr r3, [r3, #48] 7905 0058 03F00103 and r3, r3, #1 314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; 7906 .loc 3 314 10 view .LVU2507 7907 005c 0193 str r3, [sp, #4] 315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } 7908 .loc 3 315 3 is_stmt 1 view .LVU2508 7909 005e 019B ldr r3, [sp, #4] 7910 .LVL685: 315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } 7911 .loc 3 315 3 is_stmt 0 view .LVU2509 7912 .LBE589: 7913 .LBE588: 1766:Src/main.c **** GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE; 7914 .loc 1 1766 3 is_stmt 1 view .LVU2510 1766:Src/main.c **** GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE; 7915 .loc 1 1766 23 is_stmt 0 view .LVU2511 7916 0060 4FF40073 mov r3, #512 7917 0064 2793 str r3, [sp, #156] 1767:Src/main.c **** GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH; 7918 .loc 1 1767 3 is_stmt 1 view .LVU2512 1767:Src/main.c **** GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH; 7919 .loc 1 1767 24 is_stmt 0 view .LVU2513 7920 0066 4FF00208 mov r8, #2 7921 006a CDF8A080 str r8, [sp, #160] 1768:Src/main.c **** GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; 7922 .loc 1 1768 3 is_stmt 1 view .LVU2514 1768:Src/main.c **** GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; 7923 .loc 1 1768 25 is_stmt 0 view .LVU2515 7924 006e 0327 movs r7, #3 7925 0070 2997 str r7, [sp, #164] 1769:Src/main.c **** GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; 7926 .loc 1 1769 3 is_stmt 1 view .LVU2516 1769:Src/main.c **** GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; 7927 .loc 1 1769 30 is_stmt 0 view .LVU2517 7928 0072 0024 movs r4, #0 7929 0074 2A94 str r4, [sp, #168] 1770:Src/main.c **** GPIO_InitStruct.Alternate = LL_GPIO_AF_7; 7930 .loc 1 1770 3 is_stmt 1 view .LVU2518 1770:Src/main.c **** GPIO_InitStruct.Alternate = LL_GPIO_AF_7; 7931 .loc 1 1770 24 is_stmt 0 view .LVU2519 7932 0076 2B94 str r4, [sp, #172] 1771:Src/main.c **** LL_GPIO_Init(GPIOA, &GPIO_InitStruct); 7933 .loc 1 1771 3 is_stmt 1 view .LVU2520 1771:Src/main.c **** LL_GPIO_Init(GPIOA, &GPIO_InitStruct); 7934 .loc 1 1771 29 is_stmt 0 view .LVU2521 7935 0078 0726 movs r6, #7 7936 007a 2C96 str r6, [sp, #176] 1772:Src/main.c **** 7937 .loc 1 1772 3 is_stmt 1 view .LVU2522 ARM GAS /tmp/ccYgfTud.s page 522 7938 007c 404D ldr r5, .L397+4 7939 007e 27A9 add r1, sp, #156 7940 0080 2846 mov r0, r5 7941 0082 FFF7FEFF bl LL_GPIO_Init 7942 .LVL686: 1774:Src/main.c **** GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE; 7943 .loc 1 1774 3 view .LVU2523 1774:Src/main.c **** GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE; 7944 .loc 1 1774 23 is_stmt 0 view .LVU2524 7945 0086 4FF48063 mov r3, #1024 7946 008a 2793 str r3, [sp, #156] 1775:Src/main.c **** GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH; 7947 .loc 1 1775 3 is_stmt 1 view .LVU2525 1775:Src/main.c **** GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH; 7948 .loc 1 1775 24 is_stmt 0 view .LVU2526 7949 008c CDF8A080 str r8, [sp, #160] 1776:Src/main.c **** GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; 7950 .loc 1 1776 3 is_stmt 1 view .LVU2527 1776:Src/main.c **** GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; 7951 .loc 1 1776 25 is_stmt 0 view .LVU2528 7952 0090 2997 str r7, [sp, #164] 1777:Src/main.c **** GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; 7953 .loc 1 1777 3 is_stmt 1 view .LVU2529 1777:Src/main.c **** GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; 7954 .loc 1 1777 30 is_stmt 0 view .LVU2530 7955 0092 2A94 str r4, [sp, #168] 1778:Src/main.c **** GPIO_InitStruct.Alternate = LL_GPIO_AF_7; 7956 .loc 1 1778 3 is_stmt 1 view .LVU2531 1778:Src/main.c **** GPIO_InitStruct.Alternate = LL_GPIO_AF_7; 7957 .loc 1 1778 24 is_stmt 0 view .LVU2532 7958 0094 2B94 str r4, [sp, #172] 1779:Src/main.c **** LL_GPIO_Init(GPIOA, &GPIO_InitStruct); 7959 .loc 1 1779 3 is_stmt 1 view .LVU2533 1779:Src/main.c **** LL_GPIO_Init(GPIOA, &GPIO_InitStruct); 7960 .loc 1 1779 29 is_stmt 0 view .LVU2534 7961 0096 2C96 str r6, [sp, #176] 1780:Src/main.c **** 7962 .loc 1 1780 3 is_stmt 1 view .LVU2535 7963 0098 27A9 add r1, sp, #156 7964 009a 2846 mov r0, r5 7965 009c FFF7FEFF bl LL_GPIO_Init 7966 .LVL687: 1785:Src/main.c **** 7967 .loc 1 1785 3 view .LVU2536 7968 .LBB590: 7969 .LBI590: 1032:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 7970 .loc 6 1032 22 view .LVU2537 7971 .LBB591: 1034:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 7972 .loc 6 1034 3 view .LVU2538 7973 00a0 384B ldr r3, .L397+8 7974 00a2 D3F8B820 ldr r2, [r3, #184] 7975 00a6 22F0F052 bic r2, r2, #503316480 7976 00aa 42F00062 orr r2, r2, #134217728 7977 00ae C3F8B820 str r2, [r3, #184] 7978 .LVL688: ARM GAS /tmp/ccYgfTud.s page 523 1034:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 7979 .loc 6 1034 3 is_stmt 0 view .LVU2539 7980 .LBE591: 7981 .LBE590: 1787:Src/main.c **** 7982 .loc 1 1787 3 is_stmt 1 view .LVU2540 7983 .LBB592: 7984 .LBI592: 598:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 7985 .loc 6 598 22 view .LVU2541 7986 .LBB593: 600:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 7987 .loc 6 600 3 view .LVU2542 7988 00b2 D3F8B820 ldr r2, [r3, #184] 7989 00b6 22F0C002 bic r2, r2, #192 7990 00ba 42F04002 orr r2, r2, #64 7991 00be C3F8B820 str r2, [r3, #184] 7992 .LVL689: 600:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 7993 .loc 6 600 3 is_stmt 0 view .LVU2543 7994 .LBE593: 7995 .LBE592: 1789:Src/main.c **** 7996 .loc 1 1789 3 is_stmt 1 view .LVU2544 7997 .LBB594: 7998 .LBI594: 924:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 7999 .loc 6 924 22 view .LVU2545 8000 .LBB595: 926:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 8001 .loc 6 926 3 view .LVU2546 8002 00c2 D3F8B820 ldr r2, [r3, #184] 8003 00c6 42F44032 orr r2, r2, #196608 8004 00ca C3F8B820 str r2, [r3, #184] 8005 .LVL690: 926:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 8006 .loc 6 926 3 is_stmt 0 view .LVU2547 8007 .LBE595: 8008 .LBE594: 1791:Src/main.c **** 8009 .loc 1 1791 3 is_stmt 1 view .LVU2548 8010 .LBB596: 8011 .LBI596: 646:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 8012 .loc 6 646 22 view .LVU2549 8013 .LBB597: 648:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 8014 .loc 6 648 3 view .LVU2550 8015 00ce D3F8B820 ldr r2, [r3, #184] 8016 00d2 22F49072 bic r2, r2, #288 8017 00d6 C3F8B820 str r2, [r3, #184] 8018 .LVL691: 648:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 8019 .loc 6 648 3 is_stmt 0 view .LVU2551 8020 .LBE597: 8021 .LBE596: 1793:Src/main.c **** ARM GAS /tmp/ccYgfTud.s page 524 8022 .loc 1 1793 3 is_stmt 1 view .LVU2552 8023 .LBB598: 8024 .LBI598: 693:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 8025 .loc 6 693 22 view .LVU2553 8026 .LBB599: 695:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 8027 .loc 6 695 3 view .LVU2554 8028 00da D3F8B820 ldr r2, [r3, #184] 8029 00de 22F40072 bic r2, r2, #512 8030 00e2 C3F8B820 str r2, [r3, #184] 8031 .LVL692: 695:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 8032 .loc 6 695 3 is_stmt 0 view .LVU2555 8033 .LBE599: 8034 .LBE598: 1795:Src/main.c **** 8035 .loc 1 1795 3 is_stmt 1 view .LVU2556 8036 .LBB600: 8037 .LBI600: 738:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 8038 .loc 6 738 22 view .LVU2557 8039 .LBB601: 740:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 8040 .loc 6 740 3 view .LVU2558 8041 00e6 D3F8B820 ldr r2, [r3, #184] 8042 00ea 42F48062 orr r2, r2, #1024 8043 00ee C3F8B820 str r2, [r3, #184] 8044 .LVL693: 740:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 8045 .loc 6 740 3 is_stmt 0 view .LVU2559 8046 .LBE601: 8047 .LBE600: 1797:Src/main.c **** 8048 .loc 1 1797 3 is_stmt 1 view .LVU2560 8049 .LBB602: 8050 .LBI602: 784:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 8051 .loc 6 784 22 view .LVU2561 8052 .LBB603: 786:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 8053 .loc 6 786 3 view .LVU2562 8054 00f2 D3F8B820 ldr r2, [r3, #184] 8055 00f6 22F4C052 bic r2, r2, #6144 8056 00fa C3F8B820 str r2, [r3, #184] 8057 .LVL694: 786:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 8058 .loc 6 786 3 is_stmt 0 view .LVU2563 8059 .LBE603: 8060 .LBE602: 1799:Src/main.c **** 8061 .loc 1 1799 3 is_stmt 1 view .LVU2564 8062 .LBB604: 8063 .LBI604: 831:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 8064 .loc 6 831 22 view .LVU2565 8065 .LBB605: ARM GAS /tmp/ccYgfTud.s page 525 833:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 8066 .loc 6 833 3 view .LVU2566 8067 00fe D3F8B820 ldr r2, [r3, #184] 8068 0102 22F4C042 bic r2, r2, #24576 8069 0106 C3F8B820 str r2, [r3, #184] 8070 .LVL695: 833:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 8071 .loc 6 833 3 is_stmt 0 view .LVU2567 8072 .LBE605: 8073 .LBE604: 1801:Src/main.c **** 8074 .loc 1 1801 3 is_stmt 1 view .LVU2568 8075 .LBB606: 8076 .LBI606: 1299:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 8077 .loc 6 1299 22 view .LVU2569 8078 .LBB607: 1301:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 8079 .loc 6 1301 3 view .LVU2570 8080 010a D3F8CC20 ldr r2, [r3, #204] 8081 010e 22F00402 bic r2, r2, #4 8082 0112 C3F8CC20 str r2, [r3, #204] 8083 .LVL696: 1301:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 8084 .loc 6 1301 3 is_stmt 0 view .LVU2571 8085 .LBE607: 8086 .LBE606: 1804:Src/main.c **** NVIC_EnableIRQ(USART1_IRQn); 8087 .loc 1 1804 3 is_stmt 1 view .LVU2572 8088 .LBB608: 8089 .LBI608: 1884:Drivers/CMSIS/Include/core_cm7.h **** { 8090 .loc 2 1884 26 view .LVU2573 8091 .LBB609: 1886:Drivers/CMSIS/Include/core_cm7.h **** } 8092 .loc 2 1886 3 view .LVU2574 1886:Drivers/CMSIS/Include/core_cm7.h **** } 8093 .loc 2 1886 26 is_stmt 0 view .LVU2575 8094 0116 1C4B ldr r3, .L397+12 8095 0118 D868 ldr r0, [r3, #12] 8096 .LBE609: 8097 .LBE608: 1804:Src/main.c **** NVIC_EnableIRQ(USART1_IRQn); 8098 .loc 1 1804 3 discriminator 1 view .LVU2576 8099 011a 2246 mov r2, r4 8100 011c 2146 mov r1, r4 8101 011e C0F30220 ubfx r0, r0, #8, #3 8102 0122 FFF7FEFF bl NVIC_EncodePriority 8103 .LVL697: 8104 .LBB610: 8105 .LBI610: 2024:Drivers/CMSIS/Include/core_cm7.h **** { 8106 .loc 2 2024 22 is_stmt 1 view .LVU2577 8107 .LBB611: 2026:Drivers/CMSIS/Include/core_cm7.h **** { 8108 .loc 2 2026 3 view .LVU2578 2028:Drivers/CMSIS/Include/core_cm7.h **** } ARM GAS /tmp/ccYgfTud.s page 526 8109 .loc 2 2028 5 view .LVU2579 2028:Drivers/CMSIS/Include/core_cm7.h **** } 8110 .loc 2 2028 49 is_stmt 0 view .LVU2580 8111 0126 0001 lsls r0, r0, #4 8112 .LVL698: 2028:Drivers/CMSIS/Include/core_cm7.h **** } 8113 .loc 2 2028 49 view .LVU2581 8114 0128 C0B2 uxtb r0, r0 2028:Drivers/CMSIS/Include/core_cm7.h **** } 8115 .loc 2 2028 47 view .LVU2582 8116 012a 184B ldr r3, .L397+16 8117 012c 83F82503 strb r0, [r3, #805] 8118 .LVL699: 2028:Drivers/CMSIS/Include/core_cm7.h **** } 8119 .loc 2 2028 47 view .LVU2583 8120 .LBE611: 8121 .LBE610: 1805:Src/main.c **** 8122 .loc 1 1805 3 is_stmt 1 view .LVU2584 8123 .LBB612: 8124 .LBI612: 1896:Drivers/CMSIS/Include/core_cm7.h **** { 8125 .loc 2 1896 22 view .LVU2585 8126 .LBB613: 1898:Drivers/CMSIS/Include/core_cm7.h **** { 8127 .loc 2 1898 3 view .LVU2586 1900:Drivers/CMSIS/Include/core_cm7.h **** } 8128 .loc 2 1900 5 view .LVU2587 1900:Drivers/CMSIS/Include/core_cm7.h **** } 8129 .loc 2 1900 43 is_stmt 0 view .LVU2588 8130 0130 2022 movs r2, #32 8131 0132 5A60 str r2, [r3, #4] 8132 .LVL700: 1900:Drivers/CMSIS/Include/core_cm7.h **** } 8133 .loc 2 1900 43 view .LVU2589 8134 .LBE613: 8135 .LBE612: 1810:Src/main.c **** USART_InitStruct.DataWidth = LL_USART_DATAWIDTH_8B; 8136 .loc 1 1810 3 is_stmt 1 view .LVU2590 1810:Src/main.c **** USART_InitStruct.DataWidth = LL_USART_DATAWIDTH_8B; 8137 .loc 1 1810 29 is_stmt 0 view .LVU2591 8138 0134 4FF4E133 mov r3, #115200 8139 0138 2D93 str r3, [sp, #180] 1811:Src/main.c **** USART_InitStruct.StopBits = LL_USART_STOPBITS_1; 8140 .loc 1 1811 3 is_stmt 1 view .LVU2592 1811:Src/main.c **** USART_InitStruct.StopBits = LL_USART_STOPBITS_1; 8141 .loc 1 1811 30 is_stmt 0 view .LVU2593 8142 013a 2E94 str r4, [sp, #184] 1812:Src/main.c **** USART_InitStruct.Parity = LL_USART_PARITY_NONE; 8143 .loc 1 1812 3 is_stmt 1 view .LVU2594 1812:Src/main.c **** USART_InitStruct.Parity = LL_USART_PARITY_NONE; 8144 .loc 1 1812 29 is_stmt 0 view .LVU2595 8145 013c 2F94 str r4, [sp, #188] 1813:Src/main.c **** USART_InitStruct.TransferDirection = LL_USART_DIRECTION_TX_RX; 8146 .loc 1 1813 3 is_stmt 1 view .LVU2596 1813:Src/main.c **** USART_InitStruct.TransferDirection = LL_USART_DIRECTION_TX_RX; 8147 .loc 1 1813 27 is_stmt 0 view .LVU2597 ARM GAS /tmp/ccYgfTud.s page 527 8148 013e 3094 str r4, [sp, #192] 1814:Src/main.c **** USART_InitStruct.HardwareFlowControl = LL_USART_HWCONTROL_NONE; 8149 .loc 1 1814 3 is_stmt 1 view .LVU2598 1814:Src/main.c **** USART_InitStruct.HardwareFlowControl = LL_USART_HWCONTROL_NONE; 8150 .loc 1 1814 38 is_stmt 0 view .LVU2599 8151 0140 0C23 movs r3, #12 8152 0142 3193 str r3, [sp, #196] 1815:Src/main.c **** USART_InitStruct.OverSampling = LL_USART_OVERSAMPLING_16; 8153 .loc 1 1815 3 is_stmt 1 view .LVU2600 1815:Src/main.c **** USART_InitStruct.OverSampling = LL_USART_OVERSAMPLING_16; 8154 .loc 1 1815 40 is_stmt 0 view .LVU2601 8155 0144 3294 str r4, [sp, #200] 1816:Src/main.c **** LL_USART_Init(USART1, &USART_InitStruct); 8156 .loc 1 1816 3 is_stmt 1 view .LVU2602 1816:Src/main.c **** LL_USART_Init(USART1, &USART_InitStruct); 8157 .loc 1 1816 33 is_stmt 0 view .LVU2603 8158 0146 3394 str r4, [sp, #204] 1817:Src/main.c **** LL_USART_ConfigAsyncMode(USART1); 8159 .loc 1 1817 3 is_stmt 1 view .LVU2604 8160 0148 04F18044 add r4, r4, #1073741824 8161 014c 04F58834 add r4, r4, #69632 8162 0150 2DA9 add r1, sp, #180 8163 0152 2046 mov r0, r4 8164 0154 FFF7FEFF bl LL_USART_Init 8165 .LVL701: 1818:Src/main.c **** LL_USART_Enable(USART1); 8166 .loc 1 1818 3 view .LVU2605 8167 .LBB614: 8168 .LBI614: 2320:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 8169 .loc 7 2320 22 view .LVU2606 8170 .LBB615: 2326:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN | USART_CR3_HDSEL)); 8171 .loc 7 2326 3 view .LVU2607 8172 0158 6368 ldr r3, [r4, #4] 8173 015a 23F49043 bic r3, r3, #18432 8174 015e 6360 str r3, [r4, #4] 2327:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 8175 .loc 7 2327 3 view .LVU2608 8176 0160 A368 ldr r3, [r4, #8] 8177 0162 23F02A03 bic r3, r3, #42 8178 0166 A360 str r3, [r4, #8] 8179 .LVL702: 2327:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 8180 .loc 7 2327 3 is_stmt 0 view .LVU2609 8181 .LBE615: 8182 .LBE614: 1819:Src/main.c **** /* USER CODE BEGIN USART1_Init 2 */ 8183 .loc 1 1819 3 is_stmt 1 view .LVU2610 8184 .LBB616: 8185 .LBI616: 560:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 8186 .loc 7 560 22 view .LVU2611 8187 .LBB617: 562:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 8188 .loc 7 562 3 view .LVU2612 8189 0168 2368 ldr r3, [r4] ARM GAS /tmp/ccYgfTud.s page 528 8190 016a 43F00103 orr r3, r3, #1 8191 016e 2360 str r3, [r4] 8192 .LVL703: 562:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 8193 .loc 7 562 3 is_stmt 0 view .LVU2613 8194 .LBE617: 8195 .LBE616: 1824:Src/main.c **** 8196 .loc 1 1824 1 view .LVU2614 8197 0170 34B0 add sp, sp, #208 8198 .LCFI75: 8199 .cfi_remember_state 8200 .cfi_def_cfa_offset 24 8201 @ sp needed 8202 0172 BDE8F081 pop {r4, r5, r6, r7, r8, pc} 8203 .L396: 8204 .LCFI76: 8205 .cfi_restore_state 1755:Src/main.c **** } 8206 .loc 1 1755 5 is_stmt 1 view .LVU2615 8207 0176 FFF7FEFF bl Error_Handler 8208 .LVL704: 8209 .L398: 8210 017a 00BF .align 2 8211 .L397: 8212 017c 00380240 .word 1073887232 8213 0180 00000240 .word 1073872896 8214 0184 00640240 .word 1073898496 8215 0188 00ED00E0 .word -536810240 8216 018c 00E100E0 .word -536813312 8217 .cfi_endproc 8218 .LFE1204: 8220 .section .text.MX_TIM10_Init,"ax",%progbits 8221 .align 1 8222 .syntax unified 8223 .thumb 8224 .thumb_func 8226 MX_TIM10_Init: 8227 .LFB1201: 1626:Src/main.c **** 8228 .loc 1 1626 1 view -0 8229 .cfi_startproc 8230 @ args = 0, pretend = 0, frame = 0 8231 @ frame_needed = 0, uses_anonymous_args = 0 8232 0000 08B5 push {r3, lr} 8233 .LCFI77: 8234 .cfi_def_cfa_offset 8 8235 .cfi_offset 3, -8 8236 .cfi_offset 14, -4 1635:Src/main.c **** htim10.Init.Prescaler = 183; 8237 .loc 1 1635 3 view .LVU2617 1635:Src/main.c **** htim10.Init.Prescaler = 183; 8238 .loc 1 1635 19 is_stmt 0 view .LVU2618 8239 0002 0848 ldr r0, .L403 8240 0004 084B ldr r3, .L403+4 8241 0006 0360 str r3, [r0] 1636:Src/main.c **** htim10.Init.CounterMode = TIM_COUNTERMODE_UP; ARM GAS /tmp/ccYgfTud.s page 529 8242 .loc 1 1636 3 is_stmt 1 view .LVU2619 1636:Src/main.c **** htim10.Init.CounterMode = TIM_COUNTERMODE_UP; 8243 .loc 1 1636 25 is_stmt 0 view .LVU2620 8244 0008 B723 movs r3, #183 8245 000a 4360 str r3, [r0, #4] 1637:Src/main.c **** htim10.Init.Period = 9; 8246 .loc 1 1637 3 is_stmt 1 view .LVU2621 1637:Src/main.c **** htim10.Init.Period = 9; 8247 .loc 1 1637 27 is_stmt 0 view .LVU2622 8248 000c 0023 movs r3, #0 8249 000e 8360 str r3, [r0, #8] 1638:Src/main.c **** htim10.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; 8250 .loc 1 1638 3 is_stmt 1 view .LVU2623 1638:Src/main.c **** htim10.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; 8251 .loc 1 1638 22 is_stmt 0 view .LVU2624 8252 0010 0922 movs r2, #9 8253 0012 C260 str r2, [r0, #12] 1639:Src/main.c **** htim10.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; 8254 .loc 1 1639 3 is_stmt 1 view .LVU2625 1639:Src/main.c **** htim10.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; 8255 .loc 1 1639 29 is_stmt 0 view .LVU2626 8256 0014 0361 str r3, [r0, #16] 1640:Src/main.c **** if (HAL_TIM_Base_Init(&htim10) != HAL_OK) 8257 .loc 1 1640 3 is_stmt 1 view .LVU2627 1640:Src/main.c **** if (HAL_TIM_Base_Init(&htim10) != HAL_OK) 8258 .loc 1 1640 33 is_stmt 0 view .LVU2628 8259 0016 8361 str r3, [r0, #24] 1641:Src/main.c **** { 8260 .loc 1 1641 3 is_stmt 1 view .LVU2629 1641:Src/main.c **** { 8261 .loc 1 1641 7 is_stmt 0 view .LVU2630 8262 0018 FFF7FEFF bl HAL_TIM_Base_Init 8263 .LVL705: 1641:Src/main.c **** { 8264 .loc 1 1641 6 discriminator 1 view .LVU2631 8265 001c 00B9 cbnz r0, .L402 1649:Src/main.c **** 8266 .loc 1 1649 1 view .LVU2632 8267 001e 08BD pop {r3, pc} 8268 .L402: 1643:Src/main.c **** } 8269 .loc 1 1643 5 is_stmt 1 view .LVU2633 8270 0020 FFF7FEFF bl Error_Handler 8271 .LVL706: 8272 .L404: 8273 .align 2 8274 .L403: 8275 0024 00000000 .word htim10 8276 0028 00440140 .word 1073824768 8277 .cfi_endproc 8278 .LFE1201: 8280 .section .text.MX_UART8_Init,"ax",%progbits 8281 .align 1 8282 .syntax unified 8283 .thumb 8284 .thumb_func 8286 MX_UART8_Init: ARM GAS /tmp/ccYgfTud.s page 530 8287 .LFB1203: 1703:Src/main.c **** 8288 .loc 1 1703 1 view -0 8289 .cfi_startproc 8290 @ args = 0, pretend = 0, frame = 0 8291 @ frame_needed = 0, uses_anonymous_args = 0 8292 0000 08B5 push {r3, lr} 8293 .LCFI78: 8294 .cfi_def_cfa_offset 8 8295 .cfi_offset 3, -8 8296 .cfi_offset 14, -4 1712:Src/main.c **** huart8.Init.BaudRate = 115200; 8297 .loc 1 1712 3 view .LVU2635 1712:Src/main.c **** huart8.Init.BaudRate = 115200; 8298 .loc 1 1712 19 is_stmt 0 view .LVU2636 8299 0002 0B48 ldr r0, .L409 8300 0004 0B4B ldr r3, .L409+4 8301 0006 0360 str r3, [r0] 1713:Src/main.c **** huart8.Init.WordLength = UART_WORDLENGTH_8B; 8302 .loc 1 1713 3 is_stmt 1 view .LVU2637 1713:Src/main.c **** huart8.Init.WordLength = UART_WORDLENGTH_8B; 8303 .loc 1 1713 24 is_stmt 0 view .LVU2638 8304 0008 4FF4E133 mov r3, #115200 8305 000c 4360 str r3, [r0, #4] 1714:Src/main.c **** huart8.Init.StopBits = UART_STOPBITS_1; 8306 .loc 1 1714 3 is_stmt 1 view .LVU2639 1714:Src/main.c **** huart8.Init.StopBits = UART_STOPBITS_1; 8307 .loc 1 1714 26 is_stmt 0 view .LVU2640 8308 000e 0023 movs r3, #0 8309 0010 8360 str r3, [r0, #8] 1715:Src/main.c **** huart8.Init.Parity = UART_PARITY_NONE; 8310 .loc 1 1715 3 is_stmt 1 view .LVU2641 1715:Src/main.c **** huart8.Init.Parity = UART_PARITY_NONE; 8311 .loc 1 1715 24 is_stmt 0 view .LVU2642 8312 0012 C360 str r3, [r0, #12] 1716:Src/main.c **** huart8.Init.Mode = UART_MODE_TX_RX; 8313 .loc 1 1716 3 is_stmt 1 view .LVU2643 1716:Src/main.c **** huart8.Init.Mode = UART_MODE_TX_RX; 8314 .loc 1 1716 22 is_stmt 0 view .LVU2644 8315 0014 0361 str r3, [r0, #16] 1717:Src/main.c **** huart8.Init.HwFlowCtl = UART_HWCONTROL_NONE; 8316 .loc 1 1717 3 is_stmt 1 view .LVU2645 1717:Src/main.c **** huart8.Init.HwFlowCtl = UART_HWCONTROL_NONE; 8317 .loc 1 1717 20 is_stmt 0 view .LVU2646 8318 0016 0C22 movs r2, #12 8319 0018 4261 str r2, [r0, #20] 1718:Src/main.c **** huart8.Init.OverSampling = UART_OVERSAMPLING_16; 8320 .loc 1 1718 3 is_stmt 1 view .LVU2647 1718:Src/main.c **** huart8.Init.OverSampling = UART_OVERSAMPLING_16; 8321 .loc 1 1718 25 is_stmt 0 view .LVU2648 8322 001a 8361 str r3, [r0, #24] 1719:Src/main.c **** huart8.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE; 8323 .loc 1 1719 3 is_stmt 1 view .LVU2649 1719:Src/main.c **** huart8.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE; 8324 .loc 1 1719 28 is_stmt 0 view .LVU2650 8325 001c C361 str r3, [r0, #28] 1720:Src/main.c **** huart8.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT; ARM GAS /tmp/ccYgfTud.s page 531 8326 .loc 1 1720 3 is_stmt 1 view .LVU2651 1720:Src/main.c **** huart8.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT; 8327 .loc 1 1720 30 is_stmt 0 view .LVU2652 8328 001e 0362 str r3, [r0, #32] 1721:Src/main.c **** if (HAL_UART_Init(&huart8) != HAL_OK) 8329 .loc 1 1721 3 is_stmt 1 view .LVU2653 1721:Src/main.c **** if (HAL_UART_Init(&huart8) != HAL_OK) 8330 .loc 1 1721 38 is_stmt 0 view .LVU2654 8331 0020 4362 str r3, [r0, #36] 1722:Src/main.c **** { 8332 .loc 1 1722 3 is_stmt 1 view .LVU2655 1722:Src/main.c **** { 8333 .loc 1 1722 7 is_stmt 0 view .LVU2656 8334 0022 FFF7FEFF bl HAL_UART_Init 8335 .LVL707: 1722:Src/main.c **** { 8336 .loc 1 1722 6 discriminator 1 view .LVU2657 8337 0026 00B9 cbnz r0, .L408 1730:Src/main.c **** 8338 .loc 1 1730 1 view .LVU2658 8339 0028 08BD pop {r3, pc} 8340 .L408: 1724:Src/main.c **** } 8341 .loc 1 1724 5 is_stmt 1 view .LVU2659 8342 002a FFF7FEFF bl Error_Handler 8343 .LVL708: 8344 .L410: 8345 002e 00BF .align 2 8346 .L409: 8347 0030 00000000 .word huart8 8348 0034 007C0040 .word 1073773568 8349 .cfi_endproc 8350 .LFE1203: 8352 .section .text.MX_TIM8_Init,"ax",%progbits 8353 .align 1 8354 .syntax unified 8355 .thumb 8356 .thumb_func 8358 MX_TIM8_Init: 8359 .LFB1200: 1579:Src/main.c **** 8360 .loc 1 1579 1 view -0 8361 .cfi_startproc 8362 @ args = 0, pretend = 0, frame = 32 8363 @ frame_needed = 0, uses_anonymous_args = 0 8364 0000 00B5 push {lr} 8365 .LCFI79: 8366 .cfi_def_cfa_offset 4 8367 .cfi_offset 14, -4 8368 0002 89B0 sub sp, sp, #36 8369 .LCFI80: 8370 .cfi_def_cfa_offset 40 1585:Src/main.c **** TIM_MasterConfigTypeDef sMasterConfig = {0}; 8371 .loc 1 1585 3 view .LVU2661 1585:Src/main.c **** TIM_MasterConfigTypeDef sMasterConfig = {0}; 8372 .loc 1 1585 26 is_stmt 0 view .LVU2662 8373 0004 0023 movs r3, #0 ARM GAS /tmp/ccYgfTud.s page 532 8374 0006 0493 str r3, [sp, #16] 8375 0008 0593 str r3, [sp, #20] 8376 000a 0693 str r3, [sp, #24] 8377 000c 0793 str r3, [sp, #28] 1586:Src/main.c **** 8378 .loc 1 1586 3 is_stmt 1 view .LVU2663 1586:Src/main.c **** 8379 .loc 1 1586 27 is_stmt 0 view .LVU2664 8380 000e 0193 str r3, [sp, #4] 8381 0010 0293 str r3, [sp, #8] 8382 0012 0393 str r3, [sp, #12] 1591:Src/main.c **** htim8.Init.Prescaler = 0; 8383 .loc 1 1591 3 is_stmt 1 view .LVU2665 1591:Src/main.c **** htim8.Init.Prescaler = 0; 8384 .loc 1 1591 18 is_stmt 0 view .LVU2666 8385 0014 1348 ldr r0, .L419 8386 0016 144A ldr r2, .L419+4 8387 0018 0260 str r2, [r0] 1592:Src/main.c **** htim8.Init.CounterMode = TIM_COUNTERMODE_UP; 8388 .loc 1 1592 3 is_stmt 1 view .LVU2667 1592:Src/main.c **** htim8.Init.CounterMode = TIM_COUNTERMODE_UP; 8389 .loc 1 1592 24 is_stmt 0 view .LVU2668 8390 001a 4360 str r3, [r0, #4] 1593:Src/main.c **** htim8.Init.Period = 91; 8391 .loc 1 1593 3 is_stmt 1 view .LVU2669 1593:Src/main.c **** htim8.Init.Period = 91; 8392 .loc 1 1593 26 is_stmt 0 view .LVU2670 8393 001c 8360 str r3, [r0, #8] 1594:Src/main.c **** htim8.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; 8394 .loc 1 1594 3 is_stmt 1 view .LVU2671 1594:Src/main.c **** htim8.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; 8395 .loc 1 1594 21 is_stmt 0 view .LVU2672 8396 001e 5B22 movs r2, #91 8397 0020 C260 str r2, [r0, #12] 1595:Src/main.c **** htim8.Init.RepetitionCounter = 0; 8398 .loc 1 1595 3 is_stmt 1 view .LVU2673 1595:Src/main.c **** htim8.Init.RepetitionCounter = 0; 8399 .loc 1 1595 28 is_stmt 0 view .LVU2674 8400 0022 0361 str r3, [r0, #16] 1596:Src/main.c **** htim8.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; 8401 .loc 1 1596 3 is_stmt 1 view .LVU2675 1596:Src/main.c **** htim8.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; 8402 .loc 1 1596 32 is_stmt 0 view .LVU2676 8403 0024 4361 str r3, [r0, #20] 1597:Src/main.c **** if (HAL_TIM_Base_Init(&htim8) != HAL_OK) 8404 .loc 1 1597 3 is_stmt 1 view .LVU2677 1597:Src/main.c **** if (HAL_TIM_Base_Init(&htim8) != HAL_OK) 8405 .loc 1 1597 32 is_stmt 0 view .LVU2678 8406 0026 8361 str r3, [r0, #24] 1598:Src/main.c **** { 8407 .loc 1 1598 3 is_stmt 1 view .LVU2679 1598:Src/main.c **** { 8408 .loc 1 1598 7 is_stmt 0 view .LVU2680 8409 0028 FFF7FEFF bl HAL_TIM_Base_Init 8410 .LVL709: 1598:Src/main.c **** { 8411 .loc 1 1598 6 discriminator 1 view .LVU2681 ARM GAS /tmp/ccYgfTud.s page 533 8412 002c 98B9 cbnz r0, .L416 1602:Src/main.c **** if (HAL_TIM_ConfigClockSource(&htim8, &sClockSourceConfig) != HAL_OK) 8413 .loc 1 1602 3 is_stmt 1 view .LVU2682 1602:Src/main.c **** if (HAL_TIM_ConfigClockSource(&htim8, &sClockSourceConfig) != HAL_OK) 8414 .loc 1 1602 34 is_stmt 0 view .LVU2683 8415 002e 4FF48053 mov r3, #4096 8416 0032 0493 str r3, [sp, #16] 1603:Src/main.c **** { 8417 .loc 1 1603 3 is_stmt 1 view .LVU2684 1603:Src/main.c **** { 8418 .loc 1 1603 7 is_stmt 0 view .LVU2685 8419 0034 04A9 add r1, sp, #16 8420 0036 0B48 ldr r0, .L419 8421 0038 FFF7FEFF bl HAL_TIM_ConfigClockSource 8422 .LVL710: 1603:Src/main.c **** { 8423 .loc 1 1603 6 discriminator 1 view .LVU2686 8424 003c 68B9 cbnz r0, .L417 1607:Src/main.c **** sMasterConfig.MasterOutputTrigger2 = TIM_TRGO2_RESET; 8425 .loc 1 1607 3 is_stmt 1 view .LVU2687 1607:Src/main.c **** sMasterConfig.MasterOutputTrigger2 = TIM_TRGO2_RESET; 8426 .loc 1 1607 37 is_stmt 0 view .LVU2688 8427 003e 0023 movs r3, #0 8428 0040 0193 str r3, [sp, #4] 1608:Src/main.c **** sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; 8429 .loc 1 1608 3 is_stmt 1 view .LVU2689 1608:Src/main.c **** sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; 8430 .loc 1 1608 38 is_stmt 0 view .LVU2690 8431 0042 0293 str r3, [sp, #8] 1609:Src/main.c **** if (HAL_TIMEx_MasterConfigSynchronization(&htim8, &sMasterConfig) != HAL_OK) 8432 .loc 1 1609 3 is_stmt 1 view .LVU2691 1609:Src/main.c **** if (HAL_TIMEx_MasterConfigSynchronization(&htim8, &sMasterConfig) != HAL_OK) 8433 .loc 1 1609 33 is_stmt 0 view .LVU2692 8434 0044 0393 str r3, [sp, #12] 1610:Src/main.c **** { 8435 .loc 1 1610 3 is_stmt 1 view .LVU2693 1610:Src/main.c **** { 8436 .loc 1 1610 7 is_stmt 0 view .LVU2694 8437 0046 01A9 add r1, sp, #4 8438 0048 0648 ldr r0, .L419 8439 004a FFF7FEFF bl HAL_TIMEx_MasterConfigSynchronization 8440 .LVL711: 1610:Src/main.c **** { 8441 .loc 1 1610 6 discriminator 1 view .LVU2695 8442 004e 30B9 cbnz r0, .L418 1618:Src/main.c **** 8443 .loc 1 1618 1 view .LVU2696 8444 0050 09B0 add sp, sp, #36 8445 .LCFI81: 8446 .cfi_remember_state 8447 .cfi_def_cfa_offset 4 8448 @ sp needed 8449 0052 5DF804FB ldr pc, [sp], #4 8450 .L416: 8451 .LCFI82: 8452 .cfi_restore_state 1600:Src/main.c **** } ARM GAS /tmp/ccYgfTud.s page 534 8453 .loc 1 1600 5 is_stmt 1 view .LVU2697 8454 0056 FFF7FEFF bl Error_Handler 8455 .LVL712: 8456 .L417: 1605:Src/main.c **** } 8457 .loc 1 1605 5 view .LVU2698 8458 005a FFF7FEFF bl Error_Handler 8459 .LVL713: 8460 .L418: 1612:Src/main.c **** } 8461 .loc 1 1612 5 view .LVU2699 8462 005e FFF7FEFF bl Error_Handler 8463 .LVL714: 8464 .L420: 8465 0062 00BF .align 2 8466 .L419: 8467 0064 00000000 .word htim8 8468 0068 00040140 .word 1073808384 8469 .cfi_endproc 8470 .LFE1200: 8472 .section .text.MX_TIM11_Init,"ax",%progbits 8473 .align 1 8474 .syntax unified 8475 .thumb 8476 .thumb_func 8478 MX_TIM11_Init: 8479 .LFB1202: 1657:Src/main.c **** 8480 .loc 1 1657 1 view -0 8481 .cfi_startproc 8482 @ args = 0, pretend = 0, frame = 32 8483 @ frame_needed = 0, uses_anonymous_args = 0 8484 0000 00B5 push {lr} 8485 .LCFI83: 8486 .cfi_def_cfa_offset 4 8487 .cfi_offset 14, -4 8488 0002 89B0 sub sp, sp, #36 8489 .LCFI84: 8490 .cfi_def_cfa_offset 40 1663:Src/main.c **** 8491 .loc 1 1663 3 view .LVU2701 1663:Src/main.c **** 8492 .loc 1 1663 22 is_stmt 0 view .LVU2702 8493 0004 0023 movs r3, #0 8494 0006 0193 str r3, [sp, #4] 8495 0008 0293 str r3, [sp, #8] 8496 000a 0393 str r3, [sp, #12] 8497 000c 0493 str r3, [sp, #16] 8498 000e 0593 str r3, [sp, #20] 8499 0010 0693 str r3, [sp, #24] 8500 0012 0793 str r3, [sp, #28] 1668:Src/main.c **** htim11.Init.Prescaler = 1; 8501 .loc 1 1668 3 is_stmt 1 view .LVU2703 1668:Src/main.c **** htim11.Init.Prescaler = 1; 8502 .loc 1 1668 19 is_stmt 0 view .LVU2704 8503 0014 1448 ldr r0, .L429 8504 0016 154A ldr r2, .L429+4 ARM GAS /tmp/ccYgfTud.s page 535 8505 0018 0260 str r2, [r0] 1669:Src/main.c **** htim11.Init.CounterMode = TIM_COUNTERMODE_UP; 8506 .loc 1 1669 3 is_stmt 1 view .LVU2705 1669:Src/main.c **** htim11.Init.CounterMode = TIM_COUNTERMODE_UP; 8507 .loc 1 1669 25 is_stmt 0 view .LVU2706 8508 001a 0122 movs r2, #1 8509 001c 4260 str r2, [r0, #4] 1670:Src/main.c **** htim11.Init.Period = 91; 8510 .loc 1 1670 3 is_stmt 1 view .LVU2707 1670:Src/main.c **** htim11.Init.Period = 91; 8511 .loc 1 1670 27 is_stmt 0 view .LVU2708 8512 001e 8360 str r3, [r0, #8] 1671:Src/main.c **** htim11.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; 8513 .loc 1 1671 3 is_stmt 1 view .LVU2709 1671:Src/main.c **** htim11.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; 8514 .loc 1 1671 22 is_stmt 0 view .LVU2710 8515 0020 5B22 movs r2, #91 8516 0022 C260 str r2, [r0, #12] 1672:Src/main.c **** htim11.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_ENABLE; 8517 .loc 1 1672 3 is_stmt 1 view .LVU2711 1672:Src/main.c **** htim11.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_ENABLE; 8518 .loc 1 1672 29 is_stmt 0 view .LVU2712 8519 0024 0361 str r3, [r0, #16] 1673:Src/main.c **** if (HAL_TIM_Base_Init(&htim11) != HAL_OK) 8520 .loc 1 1673 3 is_stmt 1 view .LVU2713 1673:Src/main.c **** if (HAL_TIM_Base_Init(&htim11) != HAL_OK) 8521 .loc 1 1673 33 is_stmt 0 view .LVU2714 8522 0026 8023 movs r3, #128 8523 0028 8361 str r3, [r0, #24] 1674:Src/main.c **** { 8524 .loc 1 1674 3 is_stmt 1 view .LVU2715 1674:Src/main.c **** { 8525 .loc 1 1674 7 is_stmt 0 view .LVU2716 8526 002a FFF7FEFF bl HAL_TIM_Base_Init 8527 .LVL715: 1674:Src/main.c **** { 8528 .loc 1 1674 6 discriminator 1 view .LVU2717 8529 002e A8B9 cbnz r0, .L426 1678:Src/main.c **** { 8530 .loc 1 1678 3 is_stmt 1 view .LVU2718 1678:Src/main.c **** { 8531 .loc 1 1678 7 is_stmt 0 view .LVU2719 8532 0030 0D48 ldr r0, .L429 8533 0032 FFF7FEFF bl HAL_TIM_PWM_Init 8534 .LVL716: 1678:Src/main.c **** { 8535 .loc 1 1678 6 discriminator 1 view .LVU2720 8536 0036 98B9 cbnz r0, .L427 1682:Src/main.c **** sConfigOC.Pulse = 91; 8537 .loc 1 1682 3 is_stmt 1 view .LVU2721 1682:Src/main.c **** sConfigOC.Pulse = 91; 8538 .loc 1 1682 20 is_stmt 0 view .LVU2722 8539 0038 6023 movs r3, #96 8540 003a 0193 str r3, [sp, #4] 1683:Src/main.c **** sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH; 8541 .loc 1 1683 3 is_stmt 1 view .LVU2723 1683:Src/main.c **** sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH; ARM GAS /tmp/ccYgfTud.s page 536 8542 .loc 1 1683 19 is_stmt 0 view .LVU2724 8543 003c 5B23 movs r3, #91 8544 003e 0293 str r3, [sp, #8] 1684:Src/main.c **** sConfigOC.OCFastMode = TIM_OCFAST_DISABLE; 8545 .loc 1 1684 3 is_stmt 1 view .LVU2725 1684:Src/main.c **** sConfigOC.OCFastMode = TIM_OCFAST_DISABLE; 8546 .loc 1 1684 24 is_stmt 0 view .LVU2726 8547 0040 0022 movs r2, #0 8548 0042 0392 str r2, [sp, #12] 1685:Src/main.c **** if (HAL_TIM_PWM_ConfigChannel(&htim11, &sConfigOC, TIM_CHANNEL_1) != HAL_OK) 8549 .loc 1 1685 3 is_stmt 1 view .LVU2727 1685:Src/main.c **** if (HAL_TIM_PWM_ConfigChannel(&htim11, &sConfigOC, TIM_CHANNEL_1) != HAL_OK) 8550 .loc 1 1685 24 is_stmt 0 view .LVU2728 8551 0044 0592 str r2, [sp, #20] 1686:Src/main.c **** { 8552 .loc 1 1686 3 is_stmt 1 view .LVU2729 1686:Src/main.c **** { 8553 .loc 1 1686 7 is_stmt 0 view .LVU2730 8554 0046 01A9 add r1, sp, #4 8555 0048 0748 ldr r0, .L429 8556 004a FFF7FEFF bl HAL_TIM_PWM_ConfigChannel 8557 .LVL717: 1686:Src/main.c **** { 8558 .loc 1 1686 6 discriminator 1 view .LVU2731 8559 004e 48B9 cbnz r0, .L428 1693:Src/main.c **** 8560 .loc 1 1693 3 is_stmt 1 view .LVU2732 8561 0050 0548 ldr r0, .L429 8562 0052 FFF7FEFF bl HAL_TIM_MspPostInit 8563 .LVL718: 1695:Src/main.c **** 8564 .loc 1 1695 1 is_stmt 0 view .LVU2733 8565 0056 09B0 add sp, sp, #36 8566 .LCFI85: 8567 .cfi_remember_state 8568 .cfi_def_cfa_offset 4 8569 @ sp needed 8570 0058 5DF804FB ldr pc, [sp], #4 8571 .L426: 8572 .LCFI86: 8573 .cfi_restore_state 1676:Src/main.c **** } 8574 .loc 1 1676 5 is_stmt 1 view .LVU2734 8575 005c FFF7FEFF bl Error_Handler 8576 .LVL719: 8577 .L427: 1680:Src/main.c **** } 8578 .loc 1 1680 5 view .LVU2735 8579 0060 FFF7FEFF bl Error_Handler 8580 .LVL720: 8581 .L428: 1688:Src/main.c **** } 8582 .loc 1 1688 5 view .LVU2736 8583 0064 FFF7FEFF bl Error_Handler 8584 .LVL721: 8585 .L430: 8586 .align 2 ARM GAS /tmp/ccYgfTud.s page 537 8587 .L429: 8588 0068 00000000 .word htim11 8589 006c 00480140 .word 1073825792 8590 .cfi_endproc 8591 .LFE1202: 8593 .section .text.MX_TIM4_Init,"ax",%progbits 8594 .align 1 8595 .syntax unified 8596 .thumb 8597 .thumb_func 8599 MX_TIM4_Init: 8600 .LFB1196: 1407:Src/main.c **** 8601 .loc 1 1407 1 view -0 8602 .cfi_startproc 8603 @ args = 0, pretend = 0, frame = 56 8604 @ frame_needed = 0, uses_anonymous_args = 0 8605 0000 00B5 push {lr} 8606 .LCFI87: 8607 .cfi_def_cfa_offset 4 8608 .cfi_offset 14, -4 8609 0002 8FB0 sub sp, sp, #60 8610 .LCFI88: 8611 .cfi_def_cfa_offset 64 1413:Src/main.c **** TIM_MasterConfigTypeDef sMasterConfig = {0}; 8612 .loc 1 1413 3 view .LVU2738 1413:Src/main.c **** TIM_MasterConfigTypeDef sMasterConfig = {0}; 8613 .loc 1 1413 26 is_stmt 0 view .LVU2739 8614 0004 0023 movs r3, #0 8615 0006 0A93 str r3, [sp, #40] 8616 0008 0B93 str r3, [sp, #44] 8617 000a 0C93 str r3, [sp, #48] 8618 000c 0D93 str r3, [sp, #52] 1414:Src/main.c **** TIM_OC_InitTypeDef sConfigOC = {0}; 8619 .loc 1 1414 3 is_stmt 1 view .LVU2740 1414:Src/main.c **** TIM_OC_InitTypeDef sConfigOC = {0}; 8620 .loc 1 1414 27 is_stmt 0 view .LVU2741 8621 000e 0793 str r3, [sp, #28] 8622 0010 0893 str r3, [sp, #32] 8623 0012 0993 str r3, [sp, #36] 1415:Src/main.c **** 8624 .loc 1 1415 3 is_stmt 1 view .LVU2742 1415:Src/main.c **** 8625 .loc 1 1415 22 is_stmt 0 view .LVU2743 8626 0014 0093 str r3, [sp] 8627 0016 0193 str r3, [sp, #4] 8628 0018 0293 str r3, [sp, #8] 8629 001a 0393 str r3, [sp, #12] 8630 001c 0493 str r3, [sp, #16] 8631 001e 0593 str r3, [sp, #20] 8632 0020 0693 str r3, [sp, #24] 1420:Src/main.c **** htim4.Init.Prescaler = 0; 8633 .loc 1 1420 3 is_stmt 1 view .LVU2744 1420:Src/main.c **** htim4.Init.Prescaler = 0; 8634 .loc 1 1420 18 is_stmt 0 view .LVU2745 8635 0022 1E48 ldr r0, .L443 8636 0024 1E4A ldr r2, .L443+4 ARM GAS /tmp/ccYgfTud.s page 538 8637 0026 0260 str r2, [r0] 1421:Src/main.c **** htim4.Init.CounterMode = TIM_COUNTERMODE_UP; 8638 .loc 1 1421 3 is_stmt 1 view .LVU2746 1421:Src/main.c **** htim4.Init.CounterMode = TIM_COUNTERMODE_UP; 8639 .loc 1 1421 24 is_stmt 0 view .LVU2747 8640 0028 4360 str r3, [r0, #4] 1422:Src/main.c **** htim4.Init.Period = 45; 8641 .loc 1 1422 3 is_stmt 1 view .LVU2748 1422:Src/main.c **** htim4.Init.Period = 45; 8642 .loc 1 1422 26 is_stmt 0 view .LVU2749 8643 002a 8360 str r3, [r0, #8] 1423:Src/main.c **** htim4.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; 8644 .loc 1 1423 3 is_stmt 1 view .LVU2750 1423:Src/main.c **** htim4.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; 8645 .loc 1 1423 21 is_stmt 0 view .LVU2751 8646 002c 2D22 movs r2, #45 8647 002e C260 str r2, [r0, #12] 1424:Src/main.c **** htim4.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; 8648 .loc 1 1424 3 is_stmt 1 view .LVU2752 1424:Src/main.c **** htim4.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; 8649 .loc 1 1424 28 is_stmt 0 view .LVU2753 8650 0030 0361 str r3, [r0, #16] 1425:Src/main.c **** if (HAL_TIM_Base_Init(&htim4) != HAL_OK) 8651 .loc 1 1425 3 is_stmt 1 view .LVU2754 1425:Src/main.c **** if (HAL_TIM_Base_Init(&htim4) != HAL_OK) 8652 .loc 1 1425 32 is_stmt 0 view .LVU2755 8653 0032 8361 str r3, [r0, #24] 1426:Src/main.c **** { 8654 .loc 1 1426 3 is_stmt 1 view .LVU2756 1426:Src/main.c **** { 8655 .loc 1 1426 7 is_stmt 0 view .LVU2757 8656 0034 FFF7FEFF bl HAL_TIM_Base_Init 8657 .LVL722: 1426:Src/main.c **** { 8658 .loc 1 1426 6 discriminator 1 view .LVU2758 8659 0038 30BB cbnz r0, .L438 1430:Src/main.c **** if (HAL_TIM_ConfigClockSource(&htim4, &sClockSourceConfig) != HAL_OK) 8660 .loc 1 1430 3 is_stmt 1 view .LVU2759 1430:Src/main.c **** if (HAL_TIM_ConfigClockSource(&htim4, &sClockSourceConfig) != HAL_OK) 8661 .loc 1 1430 34 is_stmt 0 view .LVU2760 8662 003a 4FF48053 mov r3, #4096 8663 003e 0A93 str r3, [sp, #40] 1431:Src/main.c **** { 8664 .loc 1 1431 3 is_stmt 1 view .LVU2761 1431:Src/main.c **** { 8665 .loc 1 1431 7 is_stmt 0 view .LVU2762 8666 0040 0AA9 add r1, sp, #40 8667 0042 1648 ldr r0, .L443 8668 0044 FFF7FEFF bl HAL_TIM_ConfigClockSource 8669 .LVL723: 1431:Src/main.c **** { 8670 .loc 1 1431 6 discriminator 1 view .LVU2763 8671 0048 00BB cbnz r0, .L439 1435:Src/main.c **** { 8672 .loc 1 1435 3 is_stmt 1 view .LVU2764 1435:Src/main.c **** { 8673 .loc 1 1435 7 is_stmt 0 view .LVU2765 ARM GAS /tmp/ccYgfTud.s page 539 8674 004a 1448 ldr r0, .L443 8675 004c FFF7FEFF bl HAL_TIM_PWM_Init 8676 .LVL724: 1435:Src/main.c **** { 8677 .loc 1 1435 6 discriminator 1 view .LVU2766 8678 0050 F0B9 cbnz r0, .L440 1439:Src/main.c **** sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; 8679 .loc 1 1439 3 is_stmt 1 view .LVU2767 1439:Src/main.c **** sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; 8680 .loc 1 1439 37 is_stmt 0 view .LVU2768 8681 0052 0023 movs r3, #0 8682 0054 0793 str r3, [sp, #28] 1440:Src/main.c **** if (HAL_TIMEx_MasterConfigSynchronization(&htim4, &sMasterConfig) != HAL_OK) 8683 .loc 1 1440 3 is_stmt 1 view .LVU2769 1440:Src/main.c **** if (HAL_TIMEx_MasterConfigSynchronization(&htim4, &sMasterConfig) != HAL_OK) 8684 .loc 1 1440 33 is_stmt 0 view .LVU2770 8685 0056 0993 str r3, [sp, #36] 1441:Src/main.c **** { 8686 .loc 1 1441 3 is_stmt 1 view .LVU2771 1441:Src/main.c **** { 8687 .loc 1 1441 7 is_stmt 0 view .LVU2772 8688 0058 07A9 add r1, sp, #28 8689 005a 1048 ldr r0, .L443 8690 005c FFF7FEFF bl HAL_TIMEx_MasterConfigSynchronization 8691 .LVL725: 1441:Src/main.c **** { 8692 .loc 1 1441 6 discriminator 1 view .LVU2773 8693 0060 C0B9 cbnz r0, .L441 1445:Src/main.c **** sConfigOC.Pulse = 22; 8694 .loc 1 1445 3 is_stmt 1 view .LVU2774 1445:Src/main.c **** sConfigOC.Pulse = 22; 8695 .loc 1 1445 20 is_stmt 0 view .LVU2775 8696 0062 6023 movs r3, #96 8697 0064 0093 str r3, [sp] 1446:Src/main.c **** sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH; 8698 .loc 1 1446 3 is_stmt 1 view .LVU2776 1446:Src/main.c **** sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH; 8699 .loc 1 1446 19 is_stmt 0 view .LVU2777 8700 0066 1623 movs r3, #22 8701 0068 0193 str r3, [sp, #4] 1447:Src/main.c **** sConfigOC.OCFastMode = TIM_OCFAST_DISABLE; 8702 .loc 1 1447 3 is_stmt 1 view .LVU2778 1447:Src/main.c **** sConfigOC.OCFastMode = TIM_OCFAST_DISABLE; 8703 .loc 1 1447 24 is_stmt 0 view .LVU2779 8704 006a 0023 movs r3, #0 8705 006c 0293 str r3, [sp, #8] 1448:Src/main.c **** if (HAL_TIM_PWM_ConfigChannel(&htim4, &sConfigOC, TIM_CHANNEL_3) != HAL_OK) 8706 .loc 1 1448 3 is_stmt 1 view .LVU2780 1448:Src/main.c **** if (HAL_TIM_PWM_ConfigChannel(&htim4, &sConfigOC, TIM_CHANNEL_3) != HAL_OK) 8707 .loc 1 1448 24 is_stmt 0 view .LVU2781 8708 006e 0493 str r3, [sp, #16] 1449:Src/main.c **** { 8709 .loc 1 1449 3 is_stmt 1 view .LVU2782 1449:Src/main.c **** { 8710 .loc 1 1449 7 is_stmt 0 view .LVU2783 8711 0070 0822 movs r2, #8 8712 0072 6946 mov r1, sp ARM GAS /tmp/ccYgfTud.s page 540 8713 0074 0948 ldr r0, .L443 8714 0076 FFF7FEFF bl HAL_TIM_PWM_ConfigChannel 8715 .LVL726: 1449:Src/main.c **** { 8716 .loc 1 1449 6 discriminator 1 view .LVU2784 8717 007a 68B9 cbnz r0, .L442 1456:Src/main.c **** 8718 .loc 1 1456 3 is_stmt 1 view .LVU2785 8719 007c 0748 ldr r0, .L443 8720 007e FFF7FEFF bl HAL_TIM_MspPostInit 8721 .LVL727: 1458:Src/main.c **** 8722 .loc 1 1458 1 is_stmt 0 view .LVU2786 8723 0082 0FB0 add sp, sp, #60 8724 .LCFI89: 8725 .cfi_remember_state 8726 .cfi_def_cfa_offset 4 8727 @ sp needed 8728 0084 5DF804FB ldr pc, [sp], #4 8729 .L438: 8730 .LCFI90: 8731 .cfi_restore_state 1428:Src/main.c **** } 8732 .loc 1 1428 5 is_stmt 1 view .LVU2787 8733 0088 FFF7FEFF bl Error_Handler 8734 .LVL728: 8735 .L439: 1433:Src/main.c **** } 8736 .loc 1 1433 5 view .LVU2788 8737 008c FFF7FEFF bl Error_Handler 8738 .LVL729: 8739 .L440: 1437:Src/main.c **** } 8740 .loc 1 1437 5 view .LVU2789 8741 0090 FFF7FEFF bl Error_Handler 8742 .LVL730: 8743 .L441: 1443:Src/main.c **** } 8744 .loc 1 1443 5 view .LVU2790 8745 0094 FFF7FEFF bl Error_Handler 8746 .LVL731: 8747 .L442: 1451:Src/main.c **** } 8748 .loc 1 1451 5 view .LVU2791 8749 0098 FFF7FEFF bl Error_Handler 8750 .LVL732: 8751 .L444: 8752 .align 2 8753 .L443: 8754 009c 00000000 .word htim4 8755 00a0 00080040 .word 1073743872 8756 .cfi_endproc 8757 .LFE1196: 8759 .section .text.SystemClock_Config,"ax",%progbits 8760 .align 1 8761 .global SystemClock_Config 8762 .syntax unified ARM GAS /tmp/ccYgfTud.s page 541 8763 .thumb 8764 .thumb_func 8766 SystemClock_Config: 8767 .LFB1187: 885:Src/main.c **** RCC_OscInitTypeDef RCC_OscInitStruct = {0}; 8768 .loc 1 885 1 view -0 8769 .cfi_startproc 8770 @ args = 0, pretend = 0, frame = 80 8771 @ frame_needed = 0, uses_anonymous_args = 0 8772 0000 00B5 push {lr} 8773 .LCFI91: 8774 .cfi_def_cfa_offset 4 8775 .cfi_offset 14, -4 8776 0002 95B0 sub sp, sp, #84 8777 .LCFI92: 8778 .cfi_def_cfa_offset 88 886:Src/main.c **** RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; 8779 .loc 1 886 3 view .LVU2793 886:Src/main.c **** RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; 8780 .loc 1 886 22 is_stmt 0 view .LVU2794 8781 0004 3422 movs r2, #52 8782 0006 0021 movs r1, #0 8783 0008 07A8 add r0, sp, #28 8784 000a FFF7FEFF bl memset 8785 .LVL733: 887:Src/main.c **** 8786 .loc 1 887 3 is_stmt 1 view .LVU2795 887:Src/main.c **** 8787 .loc 1 887 22 is_stmt 0 view .LVU2796 8788 000e 0023 movs r3, #0 8789 0010 0293 str r3, [sp, #8] 8790 0012 0393 str r3, [sp, #12] 8791 0014 0493 str r3, [sp, #16] 8792 0016 0593 str r3, [sp, #20] 8793 0018 0693 str r3, [sp, #24] 891:Src/main.c **** __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); 8794 .loc 1 891 3 is_stmt 1 view .LVU2797 8795 .LBB618: 891:Src/main.c **** __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); 8796 .loc 1 891 3 view .LVU2798 891:Src/main.c **** __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); 8797 .loc 1 891 3 view .LVU2799 8798 001a 244B ldr r3, .L453 8799 001c 1A6C ldr r2, [r3, #64] 8800 001e 42F08052 orr r2, r2, #268435456 8801 0022 1A64 str r2, [r3, #64] 891:Src/main.c **** __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); 8802 .loc 1 891 3 view .LVU2800 8803 0024 1B6C ldr r3, [r3, #64] 8804 0026 03F08053 and r3, r3, #268435456 8805 002a 0093 str r3, [sp] 891:Src/main.c **** __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); 8806 .loc 1 891 3 view .LVU2801 8807 002c 009B ldr r3, [sp] 8808 .LBE618: 891:Src/main.c **** __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); 8809 .loc 1 891 3 view .LVU2802 ARM GAS /tmp/ccYgfTud.s page 542 892:Src/main.c **** 8810 .loc 1 892 3 view .LVU2803 8811 .LBB619: 892:Src/main.c **** 8812 .loc 1 892 3 view .LVU2804 892:Src/main.c **** 8813 .loc 1 892 3 view .LVU2805 8814 002e 204B ldr r3, .L453+4 8815 0030 1A68 ldr r2, [r3] 8816 0032 42F44042 orr r2, r2, #49152 8817 0036 1A60 str r2, [r3] 892:Src/main.c **** 8818 .loc 1 892 3 view .LVU2806 8819 0038 1B68 ldr r3, [r3] 8820 003a 03F44043 and r3, r3, #49152 8821 003e 0193 str r3, [sp, #4] 892:Src/main.c **** 8822 .loc 1 892 3 view .LVU2807 8823 0040 019B ldr r3, [sp, #4] 8824 .LBE619: 892:Src/main.c **** 8825 .loc 1 892 3 view .LVU2808 897:Src/main.c **** RCC_OscInitStruct.HSEState = RCC_HSE_ON; 8826 .loc 1 897 3 view .LVU2809 897:Src/main.c **** RCC_OscInitStruct.HSEState = RCC_HSE_ON; 8827 .loc 1 897 36 is_stmt 0 view .LVU2810 8828 0042 0123 movs r3, #1 8829 0044 0793 str r3, [sp, #28] 898:Src/main.c **** RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; 8830 .loc 1 898 3 is_stmt 1 view .LVU2811 898:Src/main.c **** RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; 8831 .loc 1 898 30 is_stmt 0 view .LVU2812 8832 0046 4FF48033 mov r3, #65536 8833 004a 0893 str r3, [sp, #32] 899:Src/main.c **** RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; 8834 .loc 1 899 3 is_stmt 1 view .LVU2813 899:Src/main.c **** RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; 8835 .loc 1 899 34 is_stmt 0 view .LVU2814 8836 004c 0223 movs r3, #2 8837 004e 0D93 str r3, [sp, #52] 900:Src/main.c **** RCC_OscInitStruct.PLL.PLLM = 25; 8838 .loc 1 900 3 is_stmt 1 view .LVU2815 900:Src/main.c **** RCC_OscInitStruct.PLL.PLLM = 25; 8839 .loc 1 900 35 is_stmt 0 view .LVU2816 8840 0050 4FF48002 mov r2, #4194304 8841 0054 0E92 str r2, [sp, #56] 901:Src/main.c **** RCC_OscInitStruct.PLL.PLLN = 368; 8842 .loc 1 901 3 is_stmt 1 view .LVU2817 901:Src/main.c **** RCC_OscInitStruct.PLL.PLLN = 368; 8843 .loc 1 901 30 is_stmt 0 view .LVU2818 8844 0056 1922 movs r2, #25 8845 0058 0F92 str r2, [sp, #60] 902:Src/main.c **** RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; 8846 .loc 1 902 3 is_stmt 1 view .LVU2819 902:Src/main.c **** RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; 8847 .loc 1 902 30 is_stmt 0 view .LVU2820 8848 005a 4FF4B872 mov r2, #368 ARM GAS /tmp/ccYgfTud.s page 543 8849 005e 1092 str r2, [sp, #64] 903:Src/main.c **** RCC_OscInitStruct.PLL.PLLQ = 8; 8850 .loc 1 903 3 is_stmt 1 view .LVU2821 903:Src/main.c **** RCC_OscInitStruct.PLL.PLLQ = 8; 8851 .loc 1 903 30 is_stmt 0 view .LVU2822 8852 0060 1193 str r3, [sp, #68] 904:Src/main.c **** RCC_OscInitStruct.PLL.PLLR = 2; 8853 .loc 1 904 3 is_stmt 1 view .LVU2823 904:Src/main.c **** RCC_OscInitStruct.PLL.PLLR = 2; 8854 .loc 1 904 30 is_stmt 0 view .LVU2824 8855 0062 0822 movs r2, #8 8856 0064 1292 str r2, [sp, #72] 905:Src/main.c **** if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) 8857 .loc 1 905 3 is_stmt 1 view .LVU2825 905:Src/main.c **** if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) 8858 .loc 1 905 30 is_stmt 0 view .LVU2826 8859 0066 1393 str r3, [sp, #76] 906:Src/main.c **** { 8860 .loc 1 906 3 is_stmt 1 view .LVU2827 906:Src/main.c **** { 8861 .loc 1 906 7 is_stmt 0 view .LVU2828 8862 0068 07A8 add r0, sp, #28 8863 006a FFF7FEFF bl HAL_RCC_OscConfig 8864 .LVL734: 906:Src/main.c **** { 8865 .loc 1 906 6 discriminator 1 view .LVU2829 8866 006e B0B9 cbnz r0, .L450 913:Src/main.c **** { 8867 .loc 1 913 3 is_stmt 1 view .LVU2830 913:Src/main.c **** { 8868 .loc 1 913 7 is_stmt 0 view .LVU2831 8869 0070 FFF7FEFF bl HAL_PWREx_EnableOverDrive 8870 .LVL735: 913:Src/main.c **** { 8871 .loc 1 913 6 discriminator 1 view .LVU2832 8872 0074 A8B9 cbnz r0, .L451 920:Src/main.c **** |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; 8873 .loc 1 920 3 is_stmt 1 view .LVU2833 920:Src/main.c **** |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; 8874 .loc 1 920 31 is_stmt 0 view .LVU2834 8875 0076 0F23 movs r3, #15 8876 0078 0293 str r3, [sp, #8] 922:Src/main.c **** RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; 8877 .loc 1 922 3 is_stmt 1 view .LVU2835 922:Src/main.c **** RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; 8878 .loc 1 922 34 is_stmt 0 view .LVU2836 8879 007a 0223 movs r3, #2 8880 007c 0393 str r3, [sp, #12] 923:Src/main.c **** RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4; 8881 .loc 1 923 3 is_stmt 1 view .LVU2837 923:Src/main.c **** RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4; 8882 .loc 1 923 35 is_stmt 0 view .LVU2838 8883 007e 0023 movs r3, #0 8884 0080 0493 str r3, [sp, #16] 924:Src/main.c **** RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; 8885 .loc 1 924 3 is_stmt 1 view .LVU2839 924:Src/main.c **** RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; ARM GAS /tmp/ccYgfTud.s page 544 8886 .loc 1 924 36 is_stmt 0 view .LVU2840 8887 0082 4FF4A053 mov r3, #5120 8888 0086 0593 str r3, [sp, #20] 925:Src/main.c **** 8889 .loc 1 925 3 is_stmt 1 view .LVU2841 925:Src/main.c **** 8890 .loc 1 925 36 is_stmt 0 view .LVU2842 8891 0088 4FF48053 mov r3, #4096 8892 008c 0693 str r3, [sp, #24] 927:Src/main.c **** { 8893 .loc 1 927 3 is_stmt 1 view .LVU2843 927:Src/main.c **** { 8894 .loc 1 927 7 is_stmt 0 view .LVU2844 8895 008e 0621 movs r1, #6 8896 0090 02A8 add r0, sp, #8 8897 0092 FFF7FEFF bl HAL_RCC_ClockConfig 8898 .LVL736: 927:Src/main.c **** { 8899 .loc 1 927 6 discriminator 1 view .LVU2845 8900 0096 30B9 cbnz r0, .L452 931:Src/main.c **** 8901 .loc 1 931 1 view .LVU2846 8902 0098 15B0 add sp, sp, #84 8903 .LCFI93: 8904 .cfi_remember_state 8905 .cfi_def_cfa_offset 4 8906 @ sp needed 8907 009a 5DF804FB ldr pc, [sp], #4 8908 .L450: 8909 .LCFI94: 8910 .cfi_restore_state 908:Src/main.c **** } 8911 .loc 1 908 5 is_stmt 1 view .LVU2847 8912 009e FFF7FEFF bl Error_Handler 8913 .LVL737: 8914 .L451: 915:Src/main.c **** } 8915 .loc 1 915 5 view .LVU2848 8916 00a2 FFF7FEFF bl Error_Handler 8917 .LVL738: 8918 .L452: 929:Src/main.c **** } 8919 .loc 1 929 5 view .LVU2849 8920 00a6 FFF7FEFF bl Error_Handler 8921 .LVL739: 8922 .L454: 8923 00aa 00BF .align 2 8924 .L453: 8925 00ac 00380240 .word 1073887232 8926 00b0 00700040 .word 1073770496 8927 .cfi_endproc 8928 .LFE1187: 8930 .section .text.main,"ax",%progbits 8931 .align 1 8932 .global main 8933 .syntax unified 8934 .thumb ARM GAS /tmp/ccYgfTud.s page 545 8935 .thumb_func 8937 main: 8938 .LFB1186: 202:Src/main.c **** 8939 .loc 1 202 1 view -0 8940 .cfi_startproc 8941 @ args = 0, pretend = 0, frame = 8 8942 @ frame_needed = 0, uses_anonymous_args = 0 8943 0000 2DE9F043 push {r4, r5, r6, r7, r8, r9, lr} 8944 .LCFI95: 8945 .cfi_def_cfa_offset 28 8946 .cfi_offset 4, -28 8947 .cfi_offset 5, -24 8948 .cfi_offset 6, -20 8949 .cfi_offset 7, -16 8950 .cfi_offset 8, -12 8951 .cfi_offset 9, -8 8952 .cfi_offset 14, -4 8953 0004 85B0 sub sp, sp, #20 8954 .LCFI96: 8955 .cfi_def_cfa_offset 48 205:Src/main.c **** /* USER CODE END 1 */ 8956 .loc 1 205 2 view .LVU2851 211:Src/main.c **** 8957 .loc 1 211 3 view .LVU2852 8958 0006 FFF7FEFF bl HAL_Init 8959 .LVL740: 218:Src/main.c **** 8960 .loc 1 218 3 view .LVU2853 8961 000a FFF7FEFF bl SystemClock_Config 8962 .LVL741: 225:Src/main.c **** MX_DMA_Init(); 8963 .loc 1 225 3 view .LVU2854 8964 000e FFF7FEFF bl MX_GPIO_Init 8965 .LVL742: 226:Src/main.c **** MX_SPI4_Init(); 8966 .loc 1 226 3 view .LVU2855 8967 0012 FFF7FEFF bl MX_DMA_Init 8968 .LVL743: 227:Src/main.c **** MX_FATFS_Init(); 8969 .loc 1 227 3 view .LVU2856 8970 0016 FFF7FEFF bl MX_SPI4_Init 8971 .LVL744: 228:Src/main.c **** MX_TIM2_Init(); 8972 .loc 1 228 3 view .LVU2857 8973 001a FFF7FEFF bl MX_FATFS_Init 8974 .LVL745: 229:Src/main.c **** MX_TIM5_Init(); 8975 .loc 1 229 3 view .LVU2858 8976 001e FFF7FEFF bl MX_TIM2_Init 8977 .LVL746: 230:Src/main.c **** MX_ADC1_Init(); 8978 .loc 1 230 3 view .LVU2859 8979 0022 FFF7FEFF bl MX_TIM5_Init 8980 .LVL747: 231:Src/main.c **** MX_ADC3_Init(); 8981 .loc 1 231 3 view .LVU2860 ARM GAS /tmp/ccYgfTud.s page 546 8982 0026 FFF7FEFF bl MX_ADC1_Init 8983 .LVL748: 232:Src/main.c **** MX_SPI2_Init(); 8984 .loc 1 232 3 view .LVU2861 8985 002a FFF7FEFF bl MX_ADC3_Init 8986 .LVL749: 233:Src/main.c **** MX_SPI5_Init(); 8987 .loc 1 233 3 view .LVU2862 8988 002e FFF7FEFF bl MX_SPI2_Init 8989 .LVL750: 234:Src/main.c **** MX_SPI6_Init(); 8990 .loc 1 234 3 view .LVU2863 8991 0032 FFF7FEFF bl MX_SPI5_Init 8992 .LVL751: 235:Src/main.c **** MX_USART1_UART_Init(); 8993 .loc 1 235 3 view .LVU2864 8994 0036 FFF7FEFF bl MX_SPI6_Init 8995 .LVL752: 236:Src/main.c **** MX_SDMMC1_SD_Init(); 8996 .loc 1 236 3 view .LVU2865 8997 003a FFF7FEFF bl MX_USART1_UART_Init 8998 .LVL753: 237:Src/main.c **** MX_TIM7_Init(); 8999 .loc 1 237 3 view .LVU2866 9000 003e FFF7FEFF bl MX_SDMMC1_SD_Init 9001 .LVL754: 238:Src/main.c **** MX_TIM6_Init(); 9002 .loc 1 238 3 view .LVU2867 9003 0042 FFF7FEFF bl MX_TIM7_Init 9004 .LVL755: 239:Src/main.c **** MX_TIM10_Init(); 9005 .loc 1 239 3 view .LVU2868 9006 0046 FFF7FEFF bl MX_TIM6_Init 9007 .LVL756: 240:Src/main.c **** MX_UART8_Init(); 9008 .loc 1 240 3 view .LVU2869 9009 004a FFF7FEFF bl MX_TIM10_Init 9010 .LVL757: 241:Src/main.c **** MX_TIM8_Init(); 9011 .loc 1 241 3 view .LVU2870 9012 004e FFF7FEFF bl MX_UART8_Init 9013 .LVL758: 242:Src/main.c **** MX_TIM11_Init(); 9014 .loc 1 242 3 view .LVU2871 9015 0052 FFF7FEFF bl MX_TIM8_Init 9016 .LVL759: 243:Src/main.c **** MX_TIM4_Init(); 9017 .loc 1 243 3 view .LVU2872 9018 0056 FFF7FEFF bl MX_TIM11_Init 9019 .LVL760: 244:Src/main.c **** /* USER CODE BEGIN 2 */ 9020 .loc 1 244 3 view .LVU2873 9021 005a FFF7FEFF bl MX_TIM4_Init 9022 .LVL761: 246:Src/main.c **** //HAL_TIM_Base_Start(&htim11); 9023 .loc 1 246 2 view .LVU2874 9024 005e FFF7FEFF bl Init_params ARM GAS /tmp/ccYgfTud.s page 547 9025 .LVL762: 257:Src/main.c **** 9026 .loc 1 257 2 view .LVU2875 257:Src/main.c **** 9027 .loc 1 257 14 is_stmt 0 view .LVU2876 9028 0062 854A ldr r2, .L531 9029 0064 3523 movs r3, #53 9030 0066 D362 str r3, [r2, #44] 259:Src/main.c **** 9031 .loc 1 259 2 is_stmt 1 view .LVU2877 259:Src/main.c **** 9032 .loc 1 259 23 is_stmt 0 view .LVU2878 9033 0068 D36A ldr r3, [r2, #44] 259:Src/main.c **** 9034 .loc 1 259 30 view .LVU2879 9035 006a 0133 adds r3, r3, #1 259:Src/main.c **** 9036 .loc 1 259 33 view .LVU2880 9037 006c 5B08 lsrs r3, r3, #1 259:Src/main.c **** 9038 .loc 1 259 36 view .LVU2881 9039 006e 013B subs r3, r3, #1 259:Src/main.c **** 9040 .loc 1 259 15 view .LVU2882 9041 0070 D363 str r3, [r2, #60] 264:Src/main.c **** TIM11 -> CCR1 = (TIM11 -> ARR +1)/2 - 1; 9042 .loc 1 264 2 is_stmt 1 view .LVU2883 264:Src/main.c **** TIM11 -> CCR1 = (TIM11 -> ARR +1)/2 - 1; 9043 .loc 1 264 23 is_stmt 0 view .LVU2884 9044 0072 D36A ldr r3, [r2, #44] 264:Src/main.c **** TIM11 -> CCR1 = (TIM11 -> ARR +1)/2 - 1; 9045 .loc 1 264 36 view .LVU2885 9046 0074 9B00 lsls r3, r3, #2 9047 0076 0333 adds r3, r3, #3 264:Src/main.c **** TIM11 -> CCR1 = (TIM11 -> ARR +1)/2 - 1; 9048 .loc 1 264 15 view .LVU2886 9049 0078 02F5A032 add r2, r2, #81920 9050 007c D362 str r3, [r2, #44] 265:Src/main.c **** 9051 .loc 1 265 2 is_stmt 1 view .LVU2887 265:Src/main.c **** 9052 .loc 1 265 25 is_stmt 0 view .LVU2888 9053 007e D36A ldr r3, [r2, #44] 265:Src/main.c **** 9054 .loc 1 265 32 view .LVU2889 9055 0080 0133 adds r3, r3, #1 265:Src/main.c **** 9056 .loc 1 265 35 view .LVU2890 9057 0082 5B08 lsrs r3, r3, #1 265:Src/main.c **** 9058 .loc 1 265 38 view .LVU2891 9059 0084 013B subs r3, r3, #1 265:Src/main.c **** 9060 .loc 1 265 16 view .LVU2892 9061 0086 5363 str r3, [r2, #52] 9062 0088 4CE0 b .L456 9063 .L522: ARM GAS /tmp/ccYgfTud.s page 548 279:Src/main.c **** { 9064 .loc 1 279 85 discriminator 1 view .LVU2893 9065 008a 7C4B ldr r3, .L531+4 9066 008c 1B78 ldrb r3, [r3] @ zero_extendqisi2 279:Src/main.c **** { 9067 .loc 1 279 73 discriminator 1 view .LVU2894 9068 008e 002B cmp r3, #0 9069 0090 4FD1 bne .L457 9070 .L458: 9071 .LBB620: 3073:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 9072 .loc 7 3073 3 is_stmt 1 discriminator 1 view .LVU2895 9073 .LBB621: 3073:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 9074 .loc 7 3073 3 discriminator 1 view .LVU2896 3073:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 9075 .loc 7 3073 3 discriminator 1 view .LVU2897 3073:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 9076 .loc 7 3073 3 discriminator 1 view .LVU2898 9077 .LVL763: 9078 .LBB622: 9079 .LBI622: 1068:Drivers/CMSIS/Include/cmsis_gcc.h **** { 9080 .loc 8 1068 31 view .LVU2899 9081 .LBB623: 1070:Drivers/CMSIS/Include/cmsis_gcc.h **** 9082 .loc 8 1070 5 view .LVU2900 1072:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 9083 .loc 8 1072 4 view .LVU2901 9084 0092 7B4A ldr r2, .L531+8 9085 .syntax unified 9086 @ 1072 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 9087 0094 52E8003F ldrex r3, [r2] 9088 @ 0 "" 2 9089 .LVL764: 1073:Drivers/CMSIS/Include/cmsis_gcc.h **** } 9090 .loc 8 1073 4 view .LVU2902 1073:Drivers/CMSIS/Include/cmsis_gcc.h **** } 9091 .loc 8 1073 4 is_stmt 0 view .LVU2903 9092 .thumb 9093 .syntax unified 9094 .LBE623: 9095 .LBE622: 3073:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 9096 .loc 7 3073 3 discriminator 1 view .LVU2904 9097 0098 43F48073 orr r3, r3, #256 9098 .LVL765: 3073:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 9099 .loc 7 3073 3 is_stmt 1 discriminator 1 view .LVU2905 9100 .LBB624: 9101 .LBI624: 1119:Drivers/CMSIS/Include/cmsis_gcc.h **** { 9102 .loc 8 1119 31 view .LVU2906 9103 .LBB625: 1121:Drivers/CMSIS/Include/cmsis_gcc.h **** 9104 .loc 8 1121 4 view .LVU2907 1123:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); ARM GAS /tmp/ccYgfTud.s page 549 9105 .loc 8 1123 4 view .LVU2908 9106 .syntax unified 9107 @ 1123 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 9108 009c 42E80031 strex r1, r3, [r2] 9109 @ 0 "" 2 9110 .LVL766: 9111 .loc 8 1124 4 view .LVU2909 9112 .loc 8 1124 4 is_stmt 0 view .LVU2910 9113 .thumb 9114 .syntax unified 9115 .LBE625: 9116 .LBE624: 3073:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 9117 .loc 7 3073 3 discriminator 1 view .LVU2911 9118 00a0 0029 cmp r1, #0 9119 00a2 F6D1 bne .L458 9120 .LVL767: 9121 .L459: 3073:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 9122 .loc 7 3073 3 discriminator 1 view .LVU2912 9123 .LBE621: 9124 .LBE620: 9125 .LBB626: 3040:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 9126 .loc 7 3040 3 is_stmt 1 discriminator 1 view .LVU2913 9127 .LBB627: 3040:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 9128 .loc 7 3040 3 discriminator 1 view .LVU2914 3040:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 9129 .loc 7 3040 3 discriminator 1 view .LVU2915 3040:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 9130 .loc 7 3040 3 discriminator 1 view .LVU2916 9131 .LBB628: 9132 .LBI628: 1068:Drivers/CMSIS/Include/cmsis_gcc.h **** { 9133 .loc 8 1068 31 view .LVU2917 9134 .LBB629: 1070:Drivers/CMSIS/Include/cmsis_gcc.h **** 9135 .loc 8 1070 5 view .LVU2918 1072:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 9136 .loc 8 1072 4 view .LVU2919 9137 00a4 764A ldr r2, .L531+8 9138 .syntax unified 9139 @ 1072 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 9140 00a6 52E8003F ldrex r3, [r2] 9141 @ 0 "" 2 9142 .LVL768: 1073:Drivers/CMSIS/Include/cmsis_gcc.h **** } 9143 .loc 8 1073 4 view .LVU2920 1073:Drivers/CMSIS/Include/cmsis_gcc.h **** } 9144 .loc 8 1073 4 is_stmt 0 view .LVU2921 9145 .thumb 9146 .syntax unified 9147 .LBE629: 9148 .LBE628: 3040:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 9149 .loc 7 3040 3 discriminator 1 view .LVU2922 ARM GAS /tmp/ccYgfTud.s page 550 9150 00aa 43F02003 orr r3, r3, #32 9151 .LVL769: 3040:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 9152 .loc 7 3040 3 is_stmt 1 discriminator 1 view .LVU2923 9153 .LBB630: 9154 .LBI630: 1119:Drivers/CMSIS/Include/cmsis_gcc.h **** { 9155 .loc 8 1119 31 view .LVU2924 9156 .LBB631: 1121:Drivers/CMSIS/Include/cmsis_gcc.h **** 9157 .loc 8 1121 4 view .LVU2925 1123:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 9158 .loc 8 1123 4 view .LVU2926 9159 .syntax unified 9160 @ 1123 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 9161 00ae 42E80031 strex r1, r3, [r2] 9162 @ 0 "" 2 9163 .LVL770: 9164 .loc 8 1124 4 view .LVU2927 9165 .loc 8 1124 4 is_stmt 0 view .LVU2928 9166 .thumb 9167 .syntax unified 9168 .LBE631: 9169 .LBE630: 3040:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 9170 .loc 7 3040 3 discriminator 1 view .LVU2929 9171 00b2 0029 cmp r1, #0 9172 00b4 F6D1 bne .L459 9173 .LVL771: 9174 .L460: 3040:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 9175 .loc 7 3040 3 discriminator 1 view .LVU2930 9176 .LBE627: 9177 .LBE626: 9178 .LBB632: 3136:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 9179 .loc 7 3136 3 is_stmt 1 discriminator 1 view .LVU2931 9180 .LBB633: 3136:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 9181 .loc 7 3136 3 discriminator 1 view .LVU2932 3136:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 9182 .loc 7 3136 3 discriminator 1 view .LVU2933 3136:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 9183 .loc 7 3136 3 discriminator 1 view .LVU2934 9184 .LBB634: 9185 .LBI634: 1068:Drivers/CMSIS/Include/cmsis_gcc.h **** { 9186 .loc 8 1068 31 view .LVU2935 9187 .LBB635: 1070:Drivers/CMSIS/Include/cmsis_gcc.h **** 9188 .loc 8 1070 5 view .LVU2936 1072:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 9189 .loc 8 1072 4 view .LVU2937 9190 00b6 724A ldr r2, .L531+8 9191 00b8 02F10803 add r3, r2, #8 9192 .syntax unified 9193 @ 1072 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 ARM GAS /tmp/ccYgfTud.s page 551 9194 00bc 53E8003F ldrex r3, [r3] 9195 @ 0 "" 2 9196 .LVL772: 1073:Drivers/CMSIS/Include/cmsis_gcc.h **** } 9197 .loc 8 1073 4 view .LVU2938 1073:Drivers/CMSIS/Include/cmsis_gcc.h **** } 9198 .loc 8 1073 4 is_stmt 0 view .LVU2939 9199 .thumb 9200 .syntax unified 9201 .LBE635: 9202 .LBE634: 3136:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 9203 .loc 7 3136 3 discriminator 1 view .LVU2940 9204 00c0 43F00103 orr r3, r3, #1 9205 .LVL773: 3136:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 9206 .loc 7 3136 3 is_stmt 1 discriminator 1 view .LVU2941 9207 .LBB636: 9208 .LBI636: 1119:Drivers/CMSIS/Include/cmsis_gcc.h **** { 9209 .loc 8 1119 31 view .LVU2942 9210 .LBB637: 1121:Drivers/CMSIS/Include/cmsis_gcc.h **** 9211 .loc 8 1121 4 view .LVU2943 1123:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 9212 .loc 8 1123 4 view .LVU2944 9213 00c4 0832 adds r2, r2, #8 9214 .syntax unified 9215 @ 1123 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 9216 00c6 42E80031 strex r1, r3, [r2] 9217 @ 0 "" 2 9218 .LVL774: 9219 .loc 8 1124 4 view .LVU2945 9220 .loc 8 1124 4 is_stmt 0 view .LVU2946 9221 .thumb 9222 .syntax unified 9223 .LBE637: 9224 .LBE636: 3136:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 9225 .loc 7 3136 3 discriminator 1 view .LVU2947 9226 00ca 0029 cmp r1, #0 9227 00cc F3D1 bne .L460 9228 .LBE633: 3136:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 9229 .loc 7 3136 3 is_stmt 1 discriminator 2 view .LVU2948 9230 .LVL775: 3136:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 9231 .loc 7 3136 3 is_stmt 0 discriminator 2 view .LVU2949 9232 .LBE632: 285:Src/main.c **** NVIC_EnableIRQ(USART1_IRQn);//In other case you have FE error flag... 9233 .loc 1 285 4 is_stmt 1 view .LVU2950 9234 .LBB638: 9235 .LBI638: 2024:Drivers/CMSIS/Include/core_cm7.h **** { 9236 .loc 2 2024 22 view .LVU2951 9237 .LBB639: 2026:Drivers/CMSIS/Include/core_cm7.h **** { ARM GAS /tmp/ccYgfTud.s page 552 9238 .loc 2 2026 3 view .LVU2952 2028:Drivers/CMSIS/Include/core_cm7.h **** } 9239 .loc 2 2028 5 view .LVU2953 2028:Drivers/CMSIS/Include/core_cm7.h **** } 9240 .loc 2 2028 47 is_stmt 0 view .LVU2954 9241 00ce 6D4B ldr r3, .L531+12 9242 00d0 0022 movs r2, #0 9243 00d2 83F82523 strb r2, [r3, #805] 9244 .LVL776: 2028:Drivers/CMSIS/Include/core_cm7.h **** } 9245 .loc 2 2028 47 view .LVU2955 9246 .LBE639: 9247 .LBE638: 286:Src/main.c **** u_rx_flg = 1; 9248 .loc 1 286 4 is_stmt 1 view .LVU2956 9249 .LBB640: 9250 .LBI640: 1896:Drivers/CMSIS/Include/core_cm7.h **** { 9251 .loc 2 1896 22 view .LVU2957 9252 .LBB641: 1898:Drivers/CMSIS/Include/core_cm7.h **** { 9253 .loc 2 1898 3 view .LVU2958 1900:Drivers/CMSIS/Include/core_cm7.h **** } 9254 .loc 2 1900 5 view .LVU2959 1900:Drivers/CMSIS/Include/core_cm7.h **** } 9255 .loc 2 1900 43 is_stmt 0 view .LVU2960 9256 00d6 2022 movs r2, #32 9257 00d8 5A60 str r2, [r3, #4] 9258 .LVL777: 1900:Drivers/CMSIS/Include/core_cm7.h **** } 9259 .loc 2 1900 43 view .LVU2961 9260 .LBE641: 9261 .LBE640: 287:Src/main.c **** } 9262 .loc 1 287 4 is_stmt 1 view .LVU2962 287:Src/main.c **** } 9263 .loc 1 287 13 is_stmt 0 view .LVU2963 9264 00da 684B ldr r3, .L531+4 9265 00dc 0122 movs r2, #1 9266 00de 1A70 strb r2, [r3] 9267 00e0 27E0 b .L457 9268 .L473: 297:Src/main.c **** task.current_param = task.min_param; 9269 .loc 1 297 6 is_stmt 1 view .LVU2964 297:Src/main.c **** task.current_param = task.min_param; 9270 .loc 1 297 20 is_stmt 0 view .LVU2965 9271 00e2 694B ldr r3, .L531+16 9272 00e4 0022 movs r2, #0 9273 00e6 1A70 strb r2, [r3] 298:Src/main.c **** Stop_TIM10(); 9274 .loc 1 298 6 is_stmt 1 view .LVU2966 298:Src/main.c **** Stop_TIM10(); 9275 .loc 1 298 31 is_stmt 0 view .LVU2967 9276 00e8 684B ldr r3, .L531+20 9277 00ea 5A68 ldr r2, [r3, #4] @ float 298:Src/main.c **** Stop_TIM10(); 9278 .loc 1 298 25 view .LVU2968 ARM GAS /tmp/ccYgfTud.s page 553 9279 00ec 1A61 str r2, [r3, #16] @ float 299:Src/main.c **** break; 9280 .loc 1 299 6 is_stmt 1 view .LVU2969 9281 00ee FFF7FEFF bl Stop_TIM10 9282 .LVL778: 300:Src/main.c **** case DECODE_ENABLE://1 - Decode rec. message 9283 .loc 1 300 5 view .LVU2970 9284 .L461: 824:Src/main.c **** { 9285 .loc 1 824 3 view .LVU2971 9286 00f2 674B ldr r3, .L531+24 9287 00f4 1B78 ldrb r3, [r3] @ zero_extendqisi2 9288 00f6 022B cmp r3, #2 9289 00f8 00F06884 beq .L507 9290 00fc 032B cmp r3, #3 9291 00fe 00F09B84 beq .L518 9292 0102 012B cmp r3, #1 9293 0104 09D1 bne .L509 827:Src/main.c **** //HAL_UART_Transmit(&huart1, State_Data, 2, 10); 9294 .loc 1 827 5 view .LVU2972 9295 0106 634C ldr r4, .L531+28 9296 0108 0221 movs r1, #2 9297 010a 2046 mov r0, r4 9298 010c FFF7FEFF bl USART_TX 9299 .LVL779: 829:Src/main.c **** State_Data[1]=0;//All OK! 9300 .loc 1 829 5 view .LVU2973 829:Src/main.c **** State_Data[1]=0;//All OK! 9301 .loc 1 829 18 is_stmt 0 view .LVU2974 9302 0110 0023 movs r3, #0 9303 0112 2370 strb r3, [r4] 830:Src/main.c **** UART_transmission_request = NO_MESS; 9304 .loc 1 830 5 is_stmt 1 view .LVU2975 830:Src/main.c **** UART_transmission_request = NO_MESS; 9305 .loc 1 830 18 is_stmt 0 view .LVU2976 9306 0114 6370 strb r3, [r4, #1] 831:Src/main.c **** break; 9307 .loc 1 831 5 is_stmt 1 view .LVU2977 831:Src/main.c **** break; 9308 .loc 1 831 31 is_stmt 0 view .LVU2978 9309 0116 5E4A ldr r2, .L531+24 9310 0118 1370 strb r3, [r2] 832:Src/main.c **** case MESS_02://Transmith packet 9311 .loc 1 832 4 is_stmt 1 view .LVU2979 9312 .L509: 866:Src/main.c **** { 9313 .loc 1 866 5 view .LVU2980 866:Src/main.c **** { 9314 .loc 1 866 17 is_stmt 0 view .LVU2981 9315 011a 5F4B ldr r3, .L531+32 9316 011c 1B78 ldrb r3, [r3] @ zero_extendqisi2 866:Src/main.c **** { 9317 .loc 1 866 8 view .LVU2982 9318 011e 012B cmp r3, #1 9319 0120 00F08C84 beq .L521 9320 .L456: 277:Src/main.c **** { ARM GAS /tmp/ccYgfTud.s page 554 9321 .loc 1 277 3 is_stmt 1 view .LVU2983 279:Src/main.c **** { 9322 .loc 1 279 3 view .LVU2984 279:Src/main.c **** { 9323 .loc 1 279 8 is_stmt 0 view .LVU2985 9324 0124 4FF48071 mov r1, #256 9325 0128 5C48 ldr r0, .L531+36 9326 012a FFF7FEFF bl HAL_GPIO_ReadPin 9327 .LVL780: 279:Src/main.c **** { 9328 .loc 1 279 6 discriminator 1 view .LVU2986 9329 012e 0128 cmp r0, #1 9330 0130 ABD0 beq .L522 9331 .L457: 294:Src/main.c **** { 9332 .loc 1 294 4 is_stmt 1 view .LVU2987 9333 0132 5B4B ldr r3, .L531+40 9334 0134 1B78 ldrb r3, [r3] @ zero_extendqisi2 9335 0136 0A2B cmp r3, #10 9336 0138 DBD8 bhi .L461 9337 013a 01A2 adr r2, .L463 9338 013c 52F823F0 ldr pc, [r2, r3, lsl #2] 9339 .p2align 2 9340 .L463: 9341 0140 E3000000 .word .L473+1 9342 0144 6D010000 .word .L472+1 9343 0148 D7010000 .word .L471+1 9344 014c 0D020000 .word .L470+1 9345 0150 3D020000 .word .L469+1 9346 0154 4D020000 .word .L468+1 9347 0158 69020000 .word .L467+1 9348 015c CD020000 .word .L466+1 9349 0160 B7040000 .word .L465+1 9350 0164 FD040000 .word .L464+1 9351 0168 21040000 .word .L462+1 9352 .p2align 1 9353 .L472: 302:Src/main.c **** if (CheckChecksum(COMMAND)) 9354 .loc 1 302 6 view .LVU2988 302:Src/main.c **** if (CheckChecksum(COMMAND)) 9355 .loc 1 302 18 is_stmt 0 view .LVU2989 9356 016c 4D4C ldr r4, .L531+44 9357 016e 0D21 movs r1, #13 9358 0170 2046 mov r0, r4 9359 0172 FFF7FEFF bl CalculateChecksum 9360 .LVL781: 302:Src/main.c **** if (CheckChecksum(COMMAND)) 9361 .loc 1 302 16 discriminator 1 view .LVU2990 9362 0176 4C4B ldr r3, .L531+48 9363 0178 1880 strh r0, [r3] @ movhi 303:Src/main.c **** { 9364 .loc 1 303 6 is_stmt 1 view .LVU2991 303:Src/main.c **** { 9365 .loc 1 303 10 is_stmt 0 view .LVU2992 9366 017a 2046 mov r0, r4 9367 017c FFF7FEFF bl CheckChecksum 9368 .LVL782: ARM GAS /tmp/ccYgfTud.s page 555 303:Src/main.c **** { 9369 .loc 1 303 9 discriminator 1 view .LVU2993 9370 0180 70B9 cbnz r0, .L523 316:Src/main.c **** CPU_state = DEFAULT_ENABLE; 9371 .loc 1 316 7 is_stmt 1 view .LVU2994 316:Src/main.c **** CPU_state = DEFAULT_ENABLE; 9372 .loc 1 316 17 is_stmt 0 view .LVU2995 9373 0182 444A ldr r2, .L531+28 9374 0184 1378 ldrb r3, [r2] @ zero_extendqisi2 316:Src/main.c **** CPU_state = DEFAULT_ENABLE; 9375 .loc 1 316 21 view .LVU2996 9376 0186 43F00403 orr r3, r3, #4 9377 018a 1370 strb r3, [r2] 317:Src/main.c **** CPU_state_old = HALT;//Save main current cycle 9378 .loc 1 317 7 is_stmt 1 view .LVU2997 317:Src/main.c **** CPU_state_old = HALT;//Save main current cycle 9379 .loc 1 317 17 is_stmt 0 view .LVU2998 9380 018c 444B ldr r3, .L531+40 9381 018e 0222 movs r2, #2 9382 0190 1A70 strb r2, [r3] 318:Src/main.c **** } 9383 .loc 1 318 7 is_stmt 1 view .LVU2999 318:Src/main.c **** } 9384 .loc 1 318 21 is_stmt 0 view .LVU3000 9385 0192 3D4B ldr r3, .L531+16 9386 0194 0022 movs r2, #0 9387 0196 1A70 strb r2, [r3] 9388 .L475: 320:Src/main.c **** break; 9389 .loc 1 320 6 is_stmt 1 view .LVU3001 320:Src/main.c **** break; 9390 .loc 1 320 32 is_stmt 0 view .LVU3002 9391 0198 3D4B ldr r3, .L531+24 9392 019a 0122 movs r2, #1 9393 019c 1A70 strb r2, [r3] 321:Src/main.c **** case DEFAULT_ENABLE://2 - Go to HALT 9394 .loc 1 321 5 is_stmt 1 view .LVU3003 9395 019e A8E7 b .L461 9396 .L523: 305:Src/main.c **** LL_SPI_Enable(SPI6);//Enable SPI for Laser2 DAC & TEC2 9397 .loc 1 305 7 view .LVU3004 9398 .LVL783: 9399 .LBB642: 9400 .LBI642: 358:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 9401 .loc 4 358 22 view .LVU3005 9402 .LBB643: 360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 9403 .loc 4 360 3 view .LVU3006 9404 01a0 424A ldr r2, .L531+52 9405 01a2 1368 ldr r3, [r2] 9406 01a4 43F04003 orr r3, r3, #64 9407 01a8 1360 str r3, [r2] 9408 .LVL784: 360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 9409 .loc 4 360 3 is_stmt 0 view .LVU3007 9410 .LBE643: ARM GAS /tmp/ccYgfTud.s page 556 9411 .LBE642: 306:Src/main.c **** Decode_uart(COMMAND, &LD1_curr_setup, &LD2_curr_setup, &Curr_setup); 9412 .loc 1 306 7 is_stmt 1 view .LVU3008 9413 .LBB644: 9414 .LBI644: 358:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 9415 .loc 4 358 22 view .LVU3009 9416 .LBB645: 360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 9417 .loc 4 360 3 view .LVU3010 9418 01aa 02F58E32 add r2, r2, #72704 9419 01ae 1368 ldr r3, [r2] 9420 01b0 43F04003 orr r3, r3, #64 9421 01b4 1360 str r3, [r2] 9422 .LVL785: 360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 9423 .loc 4 360 3 is_stmt 0 view .LVU3011 9424 .LBE645: 9425 .LBE644: 307:Src/main.c **** TO6_before = TO6; 9426 .loc 1 307 7 is_stmt 1 view .LVU3012 9427 01b6 3E4B ldr r3, .L531+56 9428 01b8 3E4A ldr r2, .L531+60 9429 01ba 3F49 ldr r1, .L531+64 9430 01bc 2046 mov r0, r4 9431 01be FFF7FEFF bl Decode_uart 9432 .LVL786: 308:Src/main.c **** //LD1_param.LD_TEMP_Before = LD1_param.LD_TEMP; 9433 .loc 1 308 7 view .LVU3013 308:Src/main.c **** //LD1_param.LD_TEMP_Before = LD1_param.LD_TEMP; 9434 .loc 1 308 18 is_stmt 0 view .LVU3014 9435 01c2 3E4B ldr r3, .L531+68 9436 01c4 1A68 ldr r2, [r3] 9437 01c6 3E4B ldr r3, .L531+72 9438 01c8 1A60 str r2, [r3] 311:Src/main.c **** CPU_state_old = WORK_ENABLE;//Save main current cycle 9439 .loc 1 311 7 is_stmt 1 view .LVU3015 311:Src/main.c **** CPU_state_old = WORK_ENABLE;//Save main current cycle 9440 .loc 1 311 17 is_stmt 0 view .LVU3016 9441 01ca 0723 movs r3, #7 9442 01cc 344A ldr r2, .L531+40 9443 01ce 1370 strb r3, [r2] 312:Src/main.c **** } 9444 .loc 1 312 7 is_stmt 1 view .LVU3017 312:Src/main.c **** } 9445 .loc 1 312 21 is_stmt 0 view .LVU3018 9446 01d0 2D4A ldr r2, .L531+16 9447 01d2 1370 strb r3, [r2] 9448 01d4 E0E7 b .L475 9449 .L471: 324:Src/main.c **** Stop_TIM10(); 9450 .loc 1 324 6 is_stmt 1 view .LVU3019 324:Src/main.c **** Stop_TIM10(); 9451 .loc 1 324 31 is_stmt 0 view .LVU3020 9452 01d6 2D4B ldr r3, .L531+20 9453 01d8 5A68 ldr r2, [r3, #4] @ float 324:Src/main.c **** Stop_TIM10(); ARM GAS /tmp/ccYgfTud.s page 557 9454 .loc 1 324 25 view .LVU3021 9455 01da 1A61 str r2, [r3, #16] @ float 325:Src/main.c **** Init_params(); 9456 .loc 1 325 6 is_stmt 1 view .LVU3022 9457 01dc FFF7FEFF bl Stop_TIM10 9458 .LVL787: 326:Src/main.c **** LL_SPI_Disable(SPI2);//Disable SPI for Laser1 DAC & TEC1 9459 .loc 1 326 6 view .LVU3023 9460 01e0 FFF7FEFF bl Init_params 9461 .LVL788: 327:Src/main.c **** LL_SPI_Disable(SPI6);//Disable SPI for Laser2 DAC & TEC2 9462 .loc 1 327 6 view .LVU3024 9463 .LBB646: 9464 .LBI646: 370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 9465 .loc 4 370 22 view .LVU3025 9466 .LBB647: 372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 9467 .loc 4 372 3 view .LVU3026 9468 01e4 314A ldr r2, .L531+52 9469 01e6 1368 ldr r3, [r2] 9470 01e8 23F04003 bic r3, r3, #64 9471 01ec 1360 str r3, [r2] 9472 .LVL789: 372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 9473 .loc 4 372 3 is_stmt 0 view .LVU3027 9474 .LBE647: 9475 .LBE646: 328:Src/main.c **** CPU_state = HALT; 9476 .loc 1 328 6 is_stmt 1 view .LVU3028 9477 .LBB648: 9478 .LBI648: 370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 9479 .loc 4 370 22 view .LVU3029 9480 .LBB649: 372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 9481 .loc 4 372 3 view .LVU3030 9482 01ee 02F58E32 add r2, r2, #72704 9483 01f2 1368 ldr r3, [r2] 9484 01f4 23F04003 bic r3, r3, #64 9485 01f8 1360 str r3, [r2] 9486 .LVL790: 372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 9487 .loc 4 372 3 is_stmt 0 view .LVU3031 9488 .LBE649: 9489 .LBE648: 329:Src/main.c **** CPU_state_old = HALT;//Save main current cycle 9490 .loc 1 329 6 is_stmt 1 view .LVU3032 329:Src/main.c **** CPU_state_old = HALT;//Save main current cycle 9491 .loc 1 329 16 is_stmt 0 view .LVU3033 9492 01fa 0023 movs r3, #0 9493 01fc 284A ldr r2, .L531+40 9494 01fe 1370 strb r3, [r2] 330:Src/main.c **** UART_transmission_request = MESS_01; 9495 .loc 1 330 6 is_stmt 1 view .LVU3034 330:Src/main.c **** UART_transmission_request = MESS_01; 9496 .loc 1 330 20 is_stmt 0 view .LVU3035 ARM GAS /tmp/ccYgfTud.s page 558 9497 0200 214A ldr r2, .L531+16 9498 0202 1370 strb r3, [r2] 331:Src/main.c **** break; 9499 .loc 1 331 6 is_stmt 1 view .LVU3036 331:Src/main.c **** break; 9500 .loc 1 331 32 is_stmt 0 view .LVU3037 9501 0204 224B ldr r3, .L531+24 9502 0206 0122 movs r2, #1 9503 0208 1A70 strb r2, [r3] 332:Src/main.c **** case TRANS_S_ENABLE://3 - Transmith saved packet Before this operation must to be defaulting! 9504 .loc 1 332 5 is_stmt 1 view .LVU3038 9505 020a 72E7 b .L461 9506 .L470: 334:Src/main.c **** State_Data[0]|=temp16&0xff; 9507 .loc 1 334 6 view .LVU3039 334:Src/main.c **** State_Data[0]|=temp16&0xff; 9508 .loc 1 334 15 is_stmt 0 view .LVU3040 9509 020c 2D48 ldr r0, .L531+76 9510 020e FFF7FEFF bl SD_READ 9511 .LVL791: 334:Src/main.c **** State_Data[0]|=temp16&0xff; 9512 .loc 1 334 13 discriminator 1 view .LVU3041 9513 0212 82B2 uxth r2, r0 9514 0214 2C4B ldr r3, .L531+80 9515 0216 1A80 strh r2, [r3] @ movhi 335:Src/main.c **** if (temp16==0) 9516 .loc 1 335 6 is_stmt 1 view .LVU3042 335:Src/main.c **** if (temp16==0) 9517 .loc 1 335 16 is_stmt 0 view .LVU3043 9518 0218 1E49 ldr r1, .L531+28 9519 021a 0B78 ldrb r3, [r1] @ zero_extendqisi2 335:Src/main.c **** if (temp16==0) 9520 .loc 1 335 19 view .LVU3044 9521 021c 0343 orrs r3, r3, r0 9522 021e 0B70 strb r3, [r1] 336:Src/main.c **** { 9523 .loc 1 336 6 is_stmt 1 view .LVU3045 336:Src/main.c **** { 9524 .loc 1 336 9 is_stmt 0 view .LVU3046 9525 0220 42B9 cbnz r2, .L476 338:Src/main.c **** } 9526 .loc 1 338 7 is_stmt 1 view .LVU3047 338:Src/main.c **** } 9527 .loc 1 338 33 is_stmt 0 view .LVU3048 9528 0222 1B4B ldr r3, .L531+24 9529 0224 0322 movs r2, #3 9530 0226 1A70 strb r2, [r3] 9531 .L477: 344:Src/main.c **** CPU_state = CPU_state_old;//Return to main current cycle 9532 .loc 1 344 6 is_stmt 1 view .LVU3049 344:Src/main.c **** CPU_state = CPU_state_old;//Return to main current cycle 9533 .loc 1 344 20 is_stmt 0 view .LVU3050 9534 0228 0023 movs r3, #0 9535 022a 174A ldr r2, .L531+16 9536 022c 1370 strb r3, [r2] 345:Src/main.c **** break; 9537 .loc 1 345 6 is_stmt 1 view .LVU3051 ARM GAS /tmp/ccYgfTud.s page 559 345:Src/main.c **** break; 9538 .loc 1 345 16 is_stmt 0 view .LVU3052 9539 022e 1C4A ldr r2, .L531+40 9540 0230 1370 strb r3, [r2] 346:Src/main.c **** case TRANS_ENABLE://4 - Transmith current packet 9541 .loc 1 346 5 is_stmt 1 view .LVU3053 9542 0232 5EE7 b .L461 9543 .L476: 342:Src/main.c **** } 9544 .loc 1 342 7 view .LVU3054 342:Src/main.c **** } 9545 .loc 1 342 33 is_stmt 0 view .LVU3055 9546 0234 164B ldr r3, .L531+24 9547 0236 0122 movs r2, #1 9548 0238 1A70 strb r2, [r3] 9549 023a F5E7 b .L477 9550 .L469: 348:Src/main.c **** CPU_state = CPU_state_old;//Return to main current cycle 9551 .loc 1 348 6 is_stmt 1 view .LVU3056 348:Src/main.c **** CPU_state = CPU_state_old;//Return to main current cycle 9552 .loc 1 348 32 is_stmt 0 view .LVU3057 9553 023c 144B ldr r3, .L531+24 9554 023e 0222 movs r2, #2 9555 0240 1A70 strb r2, [r3] 349:Src/main.c **** break; 9556 .loc 1 349 6 is_stmt 1 view .LVU3058 349:Src/main.c **** break; 9557 .loc 1 349 16 is_stmt 0 view .LVU3059 9558 0242 114B ldr r3, .L531+16 9559 0244 1A78 ldrb r2, [r3] @ zero_extendqisi2 9560 0246 164B ldr r3, .L531+40 9561 0248 1A70 strb r2, [r3] 350:Src/main.c **** case REMOVE_FILE://5 - Remove file from SD 9562 .loc 1 350 5 is_stmt 1 view .LVU3060 9563 024a 52E7 b .L461 9564 .L468: 352:Src/main.c **** UART_transmission_request = MESS_01; 9565 .loc 1 352 6 view .LVU3061 352:Src/main.c **** UART_transmission_request = MESS_01; 9566 .loc 1 352 21 is_stmt 0 view .LVU3062 9567 024c FFF7FEFF bl SD_REMOVE 9568 .LVL792: 352:Src/main.c **** UART_transmission_request = MESS_01; 9569 .loc 1 352 16 discriminator 1 view .LVU3063 9570 0250 104A ldr r2, .L531+28 9571 0252 1378 ldrb r3, [r2] @ zero_extendqisi2 352:Src/main.c **** UART_transmission_request = MESS_01; 9572 .loc 1 352 19 discriminator 1 view .LVU3064 9573 0254 0343 orrs r3, r3, r0 9574 0256 1370 strb r3, [r2] 353:Src/main.c **** CPU_state = CPU_state_old; 9575 .loc 1 353 6 is_stmt 1 view .LVU3065 353:Src/main.c **** CPU_state = CPU_state_old; 9576 .loc 1 353 32 is_stmt 0 view .LVU3066 9577 0258 0D4B ldr r3, .L531+24 9578 025a 0122 movs r2, #1 9579 025c 1A70 strb r2, [r3] ARM GAS /tmp/ccYgfTud.s page 560 354:Src/main.c **** break; 9580 .loc 1 354 6 is_stmt 1 view .LVU3067 354:Src/main.c **** break; 9581 .loc 1 354 16 is_stmt 0 view .LVU3068 9582 025e 0A4B ldr r3, .L531+16 9583 0260 1A78 ldrb r2, [r3] @ zero_extendqisi2 9584 0262 0F4B ldr r3, .L531+40 9585 0264 1A70 strb r2, [r3] 355:Src/main.c **** case STATE://6 - Transmith state message 9586 .loc 1 355 5 is_stmt 1 view .LVU3069 9587 0266 44E7 b .L461 9588 .L467: 357:Src/main.c **** CPU_state = CPU_state_old;//Return to main current cycle 9589 .loc 1 357 6 view .LVU3070 357:Src/main.c **** CPU_state = CPU_state_old;//Return to main current cycle 9590 .loc 1 357 32 is_stmt 0 view .LVU3071 9591 0268 094B ldr r3, .L531+24 9592 026a 0122 movs r2, #1 9593 026c 1A70 strb r2, [r3] 358:Src/main.c **** break; 9594 .loc 1 358 6 is_stmt 1 view .LVU3072 358:Src/main.c **** break; 9595 .loc 1 358 16 is_stmt 0 view .LVU3073 9596 026e 064B ldr r3, .L531+16 9597 0270 1A78 ldrb r2, [r3] @ zero_extendqisi2 9598 0272 0B4B ldr r3, .L531+40 9599 0274 1A70 strb r2, [r3] 359:Src/main.c **** case WORK_ENABLE://7 - Main work cycle 9600 .loc 1 359 5 is_stmt 1 view .LVU3074 9601 0276 3CE7 b .L461 9602 .L532: 9603 .align 2 9604 .L531: 9605 0278 00080040 .word 1073743872 9606 027c 00000000 .word u_rx_flg 9607 0280 00100140 .word 1073811456 9608 0284 00E100E0 .word -536813312 9609 0288 00000000 .word CPU_state_old 9610 028c 00000000 .word task 9611 0290 00000000 .word UART_transmission_request 9612 0294 00000000 .word State_Data 9613 0298 00000000 .word flg_tmt 9614 029c 00000240 .word 1073872896 9615 02a0 00000000 .word CPU_state 9616 02a4 00000000 .word COMMAND 9617 02a8 00000000 .word CS_result 9618 02ac 00380040 .word 1073756160 9619 02b0 00000000 .word Curr_setup 9620 02b4 00000000 .word LD2_curr_setup 9621 02b8 00000000 .word LD1_curr_setup 9622 02bc 00000000 .word TO6 9623 02c0 00000000 .word TO6_before 9624 02c4 00000000 .word Long_Data 9625 02c8 00000000 .word temp16 9626 .L466: 361:Src/main.c **** Stop_TIM10(); 9627 .loc 1 361 6 view .LVU3075 ARM GAS /tmp/ccYgfTud.s page 561 361:Src/main.c **** Stop_TIM10(); 9628 .loc 1 361 31 is_stmt 0 view .LVU3076 9629 02cc 9F4B ldr r3, .L533 9630 02ce 5A68 ldr r2, [r3, #4] @ float 361:Src/main.c **** Stop_TIM10(); 9631 .loc 1 361 25 view .LVU3077 9632 02d0 1A61 str r2, [r3, #16] @ float 362:Src/main.c **** if (TO7>TO7_before)//Main work cycle go with the timer 7 (1000 us or 1 kHz) 9633 .loc 1 362 6 is_stmt 1 view .LVU3078 9634 02d2 FFF7FEFF bl Stop_TIM10 9635 .LVL793: 363:Src/main.c **** { 9636 .loc 1 363 6 view .LVU3079 363:Src/main.c **** { 9637 .loc 1 363 13 is_stmt 0 view .LVU3080 9638 02d6 9E4B ldr r3, .L533+4 9639 02d8 1B68 ldr r3, [r3] 9640 02da 9E4A ldr r2, .L533+8 9641 02dc 1268 ldr r2, [r2] 363:Src/main.c **** { 9642 .loc 1 363 9 view .LVU3081 9643 02de 9342 cmp r3, r2 9644 02e0 7FF607AF bls .L461 365:Src/main.c **** LD1_param.POWER = MPhD_T(1);//Get Data from monitor photodiode of LD1 9645 .loc 1 365 7 is_stmt 1 view .LVU3082 365:Src/main.c **** LD1_param.POWER = MPhD_T(1);//Get Data from monitor photodiode of LD1 9646 .loc 1 365 18 is_stmt 0 view .LVU3083 9647 02e4 9B4A ldr r2, .L533+8 9648 02e6 1360 str r3, [r2] 366:Src/main.c **** LD1_param.POWER = MPhD_T(1);//Get Data from monitor photodiode of LD1 9649 .loc 1 366 7 is_stmt 1 view .LVU3084 366:Src/main.c **** LD1_param.POWER = MPhD_T(1);//Get Data from monitor photodiode of LD1 9650 .loc 1 366 25 is_stmt 0 view .LVU3085 9651 02e8 0120 movs r0, #1 9652 02ea FFF7FEFF bl MPhD_T 9653 .LVL794: 366:Src/main.c **** LD1_param.POWER = MPhD_T(1);//Get Data from monitor photodiode of LD1 9654 .loc 1 366 23 discriminator 1 view .LVU3086 9655 02ee 9A4F ldr r7, .L533+12 9656 02f0 3881 strh r0, [r7, #8] @ movhi 367:Src/main.c **** LD2_param.POWER = MPhD_T(2);//Get Data from monitor photodiode of LD2 9657 .loc 1 367 7 is_stmt 1 view .LVU3087 367:Src/main.c **** LD2_param.POWER = MPhD_T(2);//Get Data from monitor photodiode of LD2 9658 .loc 1 367 25 is_stmt 0 view .LVU3088 9659 02f2 0120 movs r0, #1 9660 02f4 FFF7FEFF bl MPhD_T 9661 .LVL795: 367:Src/main.c **** LD2_param.POWER = MPhD_T(2);//Get Data from monitor photodiode of LD2 9662 .loc 1 367 23 discriminator 1 view .LVU3089 9663 02f8 3881 strh r0, [r7, #8] @ movhi 368:Src/main.c **** LD2_param.POWER = MPhD_T(2);//Get Data from monitor photodiode of LD2 9664 .loc 1 368 7 is_stmt 1 view .LVU3090 368:Src/main.c **** LD2_param.POWER = MPhD_T(2);//Get Data from monitor photodiode of LD2 9665 .loc 1 368 25 is_stmt 0 view .LVU3091 9666 02fa 0220 movs r0, #2 9667 02fc FFF7FEFF bl MPhD_T 9668 .LVL796: ARM GAS /tmp/ccYgfTud.s page 562 368:Src/main.c **** LD2_param.POWER = MPhD_T(2);//Get Data from monitor photodiode of LD2 9669 .loc 1 368 23 discriminator 1 view .LVU3092 9670 0300 964E ldr r6, .L533+16 9671 0302 3081 strh r0, [r6, #8] @ movhi 369:Src/main.c **** 9672 .loc 1 369 7 is_stmt 1 view .LVU3093 369:Src/main.c **** 9673 .loc 1 369 25 is_stmt 0 view .LVU3094 9674 0304 0220 movs r0, #2 9675 0306 FFF7FEFF bl MPhD_T 9676 .LVL797: 369:Src/main.c **** 9677 .loc 1 369 23 discriminator 1 view .LVU3095 9678 030a 3081 strh r0, [r6, #8] @ movhi 372:Src/main.c **** LD1_param.LD_CURR_TEMP = MPhD_T(3); 9679 .loc 1 372 7 is_stmt 1 view .LVU3096 372:Src/main.c **** LD1_param.LD_CURR_TEMP = MPhD_T(3); 9680 .loc 1 372 14 is_stmt 0 view .LVU3097 9681 030c 0320 movs r0, #3 9682 030e FFF7FEFF bl MPhD_T 9683 .LVL798: 373:Src/main.c **** (void) MPhD_T(4); 9684 .loc 1 373 7 is_stmt 1 view .LVU3098 373:Src/main.c **** (void) MPhD_T(4); 9685 .loc 1 373 32 is_stmt 0 view .LVU3099 9686 0312 0320 movs r0, #3 9687 0314 FFF7FEFF bl MPhD_T 9688 .LVL799: 373:Src/main.c **** (void) MPhD_T(4); 9689 .loc 1 373 30 discriminator 1 view .LVU3100 9690 0318 3880 strh r0, [r7] @ movhi 374:Src/main.c **** LD2_param.LD_CURR_TEMP = MPhD_T(4); 9691 .loc 1 374 7 is_stmt 1 view .LVU3101 374:Src/main.c **** LD2_param.LD_CURR_TEMP = MPhD_T(4); 9692 .loc 1 374 14 is_stmt 0 view .LVU3102 9693 031a 0420 movs r0, #4 9694 031c FFF7FEFF bl MPhD_T 9695 .LVL800: 375:Src/main.c **** temp16=PID_Controller_Temp(&LD1_curr_setup, &LD1_param, 1); 9696 .loc 1 375 7 is_stmt 1 view .LVU3103 375:Src/main.c **** temp16=PID_Controller_Temp(&LD1_curr_setup, &LD1_param, 1); 9697 .loc 1 375 32 is_stmt 0 view .LVU3104 9698 0320 0420 movs r0, #4 9699 0322 FFF7FEFF bl MPhD_T 9700 .LVL801: 375:Src/main.c **** temp16=PID_Controller_Temp(&LD1_curr_setup, &LD1_param, 1); 9701 .loc 1 375 30 discriminator 1 view .LVU3105 9702 0326 3080 strh r0, [r6] @ movhi 376:Src/main.c **** Set_LTEC(3, temp16);//Drive Laser TEC 1 9703 .loc 1 376 7 is_stmt 1 view .LVU3106 376:Src/main.c **** Set_LTEC(3, temp16);//Drive Laser TEC 1 9704 .loc 1 376 14 is_stmt 0 view .LVU3107 9705 0328 DFF86482 ldr r8, .L533+68 9706 032c 0122 movs r2, #1 9707 032e 3946 mov r1, r7 9708 0330 4046 mov r0, r8 9709 0332 FFF7FEFF bl PID_Controller_Temp ARM GAS /tmp/ccYgfTud.s page 563 9710 .LVL802: 9711 0336 0146 mov r1, r0 376:Src/main.c **** Set_LTEC(3, temp16);//Drive Laser TEC 1 9712 .loc 1 376 13 discriminator 1 view .LVU3108 9713 0338 894D ldr r5, .L533+20 9714 033a 2880 strh r0, [r5] @ movhi 377:Src/main.c **** temp16=PID_Controller_Temp(&LD2_curr_setup, &LD2_param, 2); 9715 .loc 1 377 7 is_stmt 1 view .LVU3109 9716 033c 0320 movs r0, #3 9717 033e FFF7FEFF bl Set_LTEC 9718 .LVL803: 378:Src/main.c **** Set_LTEC(4, temp16);//Drive Laser TEC 2 9719 .loc 1 378 7 view .LVU3110 378:Src/main.c **** Set_LTEC(4, temp16);//Drive Laser TEC 2 9720 .loc 1 378 14 is_stmt 0 view .LVU3111 9721 0342 DFF84892 ldr r9, .L533+64 9722 0346 0222 movs r2, #2 9723 0348 3146 mov r1, r6 9724 034a 4846 mov r0, r9 9725 034c FFF7FEFF bl PID_Controller_Temp 9726 .LVL804: 9727 0350 0146 mov r1, r0 378:Src/main.c **** Set_LTEC(4, temp16);//Drive Laser TEC 2 9728 .loc 1 378 13 discriminator 1 view .LVU3112 9729 0352 2880 strh r0, [r5] @ movhi 379:Src/main.c **** 9730 .loc 1 379 7 is_stmt 1 view .LVU3113 9731 0354 0420 movs r0, #4 9732 0356 FFF7FEFF bl Set_LTEC 9733 .LVL805: 381:Src/main.c **** Long_Data[2] = LD2_param.POWER;//Translate Data from monitor photodiode of LD2 to Long_Data 9734 .loc 1 381 7 view .LVU3114 381:Src/main.c **** Long_Data[2] = LD2_param.POWER;//Translate Data from monitor photodiode of LD2 to Long_Data 9735 .loc 1 381 31 is_stmt 0 view .LVU3115 9736 035a 3B89 ldrh r3, [r7, #8] 381:Src/main.c **** Long_Data[2] = LD2_param.POWER;//Translate Data from monitor photodiode of LD2 to Long_Data 9737 .loc 1 381 20 view .LVU3116 9738 035c 814C ldr r4, .L533+24 9739 035e 6380 strh r3, [r4, #2] @ movhi 382:Src/main.c **** 9740 .loc 1 382 7 is_stmt 1 view .LVU3117 382:Src/main.c **** 9741 .loc 1 382 31 is_stmt 0 view .LVU3118 9742 0360 3389 ldrh r3, [r6, #8] 382:Src/main.c **** 9743 .loc 1 382 20 view .LVU3119 9744 0362 A380 strh r3, [r4, #4] @ movhi 384:Src/main.c **** Set_LTEC(2,LD2_curr_setup.CURRENT);//Drive Laser diode 2 9745 .loc 1 384 7 is_stmt 1 view .LVU3120 9746 0364 B8F80C10 ldrh r1, [r8, #12] 9747 0368 0120 movs r0, #1 9748 036a FFF7FEFF bl Set_LTEC 9749 .LVL806: 385:Src/main.c **** 9750 .loc 1 385 7 view .LVU3121 9751 036e B9F80C10 ldrh r1, [r9, #12] 9752 0372 0220 movs r0, #2 ARM GAS /tmp/ccYgfTud.s page 564 9753 0374 FFF7FEFF bl Set_LTEC 9754 .LVL807: 389:Src/main.c **** temp16 = Get_ADC(1); 9755 .loc 1 389 7 view .LVU3122 389:Src/main.c **** temp16 = Get_ADC(1); 9756 .loc 1 389 16 is_stmt 0 view .LVU3123 9757 0378 0020 movs r0, #0 9758 037a FFF7FEFF bl Get_ADC 9759 .LVL808: 389:Src/main.c **** temp16 = Get_ADC(1); 9760 .loc 1 389 14 discriminator 1 view .LVU3124 9761 037e 2880 strh r0, [r5] @ movhi 390:Src/main.c **** Long_Data[7] = temp16; // PA2 -- 3V_monitor // PB1 -- U_Rt1_ext_Gain 9762 .loc 1 390 7 is_stmt 1 view .LVU3125 390:Src/main.c **** Long_Data[7] = temp16; // PA2 -- 3V_monitor // PB1 -- U_Rt1_ext_Gain 9763 .loc 1 390 16 is_stmt 0 view .LVU3126 9764 0380 0120 movs r0, #1 9765 0382 FFF7FEFF bl Get_ADC 9766 .LVL809: 390:Src/main.c **** Long_Data[7] = temp16; // PA2 -- 3V_monitor // PB1 -- U_Rt1_ext_Gain 9767 .loc 1 390 14 discriminator 1 view .LVU3127 9768 0386 2880 strh r0, [r5] @ movhi 391:Src/main.c **** 9769 .loc 1 391 7 is_stmt 1 view .LVU3128 391:Src/main.c **** 9770 .loc 1 391 20 is_stmt 0 view .LVU3129 9771 0388 E081 strh r0, [r4, #14] @ movhi 394:Src/main.c **** Long_Data[8] = temp16; // PB0 -- U_Rt2_ext_Gain // PB0 -- U_Rt2_ext_Gain 9772 .loc 1 394 7 is_stmt 1 view .LVU3130 394:Src/main.c **** Long_Data[8] = temp16; // PB0 -- U_Rt2_ext_Gain // PB0 -- U_Rt2_ext_Gain 9773 .loc 1 394 16 is_stmt 0 view .LVU3131 9774 038a 0120 movs r0, #1 9775 038c FFF7FEFF bl Get_ADC 9776 .LVL810: 394:Src/main.c **** Long_Data[8] = temp16; // PB0 -- U_Rt2_ext_Gain // PB0 -- U_Rt2_ext_Gain 9777 .loc 1 394 14 discriminator 1 view .LVU3132 9778 0390 2880 strh r0, [r5] @ movhi 395:Src/main.c **** 9779 .loc 1 395 7 is_stmt 1 view .LVU3133 395:Src/main.c **** 9780 .loc 1 395 20 is_stmt 0 view .LVU3134 9781 0392 2082 strh r0, [r4, #16] @ movhi 398:Src/main.c **** Long_Data[9] = temp16; // PB1 -- U_Rt1_ext_Gain // PA2 -- 3V_monitor 9782 .loc 1 398 7 is_stmt 1 view .LVU3135 398:Src/main.c **** Long_Data[9] = temp16; // PB1 -- U_Rt1_ext_Gain // PA2 -- 3V_monitor 9783 .loc 1 398 16 is_stmt 0 view .LVU3136 9784 0394 0120 movs r0, #1 9785 0396 FFF7FEFF bl Get_ADC 9786 .LVL811: 398:Src/main.c **** Long_Data[9] = temp16; // PB1 -- U_Rt1_ext_Gain // PA2 -- 3V_monitor 9787 .loc 1 398 14 discriminator 1 view .LVU3137 9788 039a 2880 strh r0, [r5] @ movhi 399:Src/main.c **** 9789 .loc 1 399 7 is_stmt 1 view .LVU3138 399:Src/main.c **** 9790 .loc 1 399 20 is_stmt 0 view .LVU3139 9791 039c 6082 strh r0, [r4, #18] @ movhi ARM GAS /tmp/ccYgfTud.s page 565 402:Src/main.c **** Long_Data[10] = temp16; // PC0 -- 5V1_monitor // PC0 -- 5V1_monitor 9792 .loc 1 402 7 is_stmt 1 view .LVU3140 402:Src/main.c **** Long_Data[10] = temp16; // PC0 -- 5V1_monitor // PC0 -- 5V1_monitor 9793 .loc 1 402 16 is_stmt 0 view .LVU3141 9794 039e 0120 movs r0, #1 9795 03a0 FFF7FEFF bl Get_ADC 9796 .LVL812: 402:Src/main.c **** Long_Data[10] = temp16; // PC0 -- 5V1_monitor // PC0 -- 5V1_monitor 9797 .loc 1 402 14 discriminator 1 view .LVU3142 9798 03a4 2880 strh r0, [r5] @ movhi 403:Src/main.c **** 9799 .loc 1 403 7 is_stmt 1 view .LVU3143 403:Src/main.c **** 9800 .loc 1 403 21 is_stmt 0 view .LVU3144 9801 03a6 A082 strh r0, [r4, #20] @ movhi 406:Src/main.c **** Long_Data[11] = temp16; // PC1 -- 5V2_monitor // PC1 -- 5V2_monitor 9802 .loc 1 406 7 is_stmt 1 view .LVU3145 406:Src/main.c **** Long_Data[11] = temp16; // PC1 -- 5V2_monitor // PC1 -- 5V2_monitor 9803 .loc 1 406 16 is_stmt 0 view .LVU3146 9804 03a8 0120 movs r0, #1 9805 03aa FFF7FEFF bl Get_ADC 9806 .LVL813: 406:Src/main.c **** Long_Data[11] = temp16; // PC1 -- 5V2_monitor // PC1 -- 5V2_monitor 9807 .loc 1 406 14 discriminator 1 view .LVU3147 9808 03ae 2880 strh r0, [r5] @ movhi 407:Src/main.c **** temp16 = Get_ADC(2); 9809 .loc 1 407 7 is_stmt 1 view .LVU3148 407:Src/main.c **** temp16 = Get_ADC(2); 9810 .loc 1 407 21 is_stmt 0 view .LVU3149 9811 03b0 E082 strh r0, [r4, #22] @ movhi 408:Src/main.c **** 9812 .loc 1 408 7 is_stmt 1 view .LVU3150 408:Src/main.c **** 9813 .loc 1 408 16 is_stmt 0 view .LVU3151 9814 03b2 0220 movs r0, #2 9815 03b4 FFF7FEFF bl Get_ADC 9816 .LVL814: 408:Src/main.c **** 9817 .loc 1 408 14 discriminator 1 view .LVU3152 9818 03b8 2880 strh r0, [r5] @ movhi 411:Src/main.c **** temp16 = Get_ADC(4); 9819 .loc 1 411 7 is_stmt 1 view .LVU3153 411:Src/main.c **** temp16 = Get_ADC(4); 9820 .loc 1 411 16 is_stmt 0 view .LVU3154 9821 03ba 0320 movs r0, #3 9822 03bc FFF7FEFF bl Get_ADC 9823 .LVL815: 411:Src/main.c **** temp16 = Get_ADC(4); 9824 .loc 1 411 14 discriminator 1 view .LVU3155 9825 03c0 2880 strh r0, [r5] @ movhi 412:Src/main.c **** Long_Data[12] = temp16; 9826 .loc 1 412 7 is_stmt 1 view .LVU3156 412:Src/main.c **** Long_Data[12] = temp16; 9827 .loc 1 412 16 is_stmt 0 view .LVU3157 9828 03c2 0420 movs r0, #4 9829 03c4 FFF7FEFF bl Get_ADC 9830 .LVL816: ARM GAS /tmp/ccYgfTud.s page 566 412:Src/main.c **** Long_Data[12] = temp16; 9831 .loc 1 412 14 discriminator 1 view .LVU3158 9832 03c8 2880 strh r0, [r5] @ movhi 413:Src/main.c **** temp16 = Get_ADC(5); 9833 .loc 1 413 7 is_stmt 1 view .LVU3159 413:Src/main.c **** temp16 = Get_ADC(5); 9834 .loc 1 413 21 is_stmt 0 view .LVU3160 9835 03ca 2083 strh r0, [r4, #24] @ movhi 414:Src/main.c **** 9836 .loc 1 414 7 is_stmt 1 view .LVU3161 414:Src/main.c **** 9837 .loc 1 414 16 is_stmt 0 view .LVU3162 9838 03cc 0520 movs r0, #5 9839 03ce FFF7FEFF bl Get_ADC 9840 .LVL817: 414:Src/main.c **** 9841 .loc 1 414 14 discriminator 1 view .LVU3163 9842 03d2 2880 strh r0, [r5] @ movhi 417:Src/main.c **** Long_Data[3] = (TO6_stop)&0xffff; 9843 .loc 1 417 7 is_stmt 1 view .LVU3164 417:Src/main.c **** Long_Data[3] = (TO6_stop)&0xffff; 9844 .loc 1 417 16 is_stmt 0 view .LVU3165 9845 03d4 644B ldr r3, .L533+28 9846 03d6 1B68 ldr r3, [r3] 9847 03d8 644A ldr r2, .L533+32 9848 03da 1360 str r3, [r2] 418:Src/main.c **** Long_Data[4] = (TO6_stop>>16)&0xffff; 9849 .loc 1 418 7 is_stmt 1 view .LVU3166 418:Src/main.c **** Long_Data[4] = (TO6_stop>>16)&0xffff; 9850 .loc 1 418 20 is_stmt 0 view .LVU3167 9851 03dc E380 strh r3, [r4, #6] @ movhi 419:Src/main.c **** 9852 .loc 1 419 7 is_stmt 1 view .LVU3168 419:Src/main.c **** 9853 .loc 1 419 31 is_stmt 0 view .LVU3169 9854 03de 1B0C lsrs r3, r3, #16 419:Src/main.c **** 9855 .loc 1 419 20 view .LVU3170 9856 03e0 2381 strh r3, [r4, #8] @ movhi 422:Src/main.c **** 9857 .loc 1 422 7 is_stmt 1 view .LVU3171 422:Src/main.c **** 9858 .loc 1 422 31 is_stmt 0 view .LVU3172 9859 03e2 3B88 ldrh r3, [r7] 422:Src/main.c **** 9860 .loc 1 422 20 view .LVU3173 9861 03e4 6381 strh r3, [r4, #10] @ movhi 425:Src/main.c **** 9862 .loc 1 425 7 is_stmt 1 view .LVU3174 425:Src/main.c **** 9863 .loc 1 425 31 is_stmt 0 view .LVU3175 9864 03e6 3388 ldrh r3, [r6] 425:Src/main.c **** 9865 .loc 1 425 20 view .LVU3176 9866 03e8 A381 strh r3, [r4, #12] @ movhi 427:Src/main.c **** { 9867 .loc 1 427 7 is_stmt 1 view .LVU3177 ARM GAS /tmp/ccYgfTud.s page 567 427:Src/main.c **** { 9868 .loc 1 427 21 is_stmt 0 view .LVU3178 9869 03ea 614B ldr r3, .L533+36 9870 03ec DB7A ldrb r3, [r3, #11] @ zero_extendqisi2 427:Src/main.c **** { 9871 .loc 1 427 10 view .LVU3179 9872 03ee 012B cmp r3, #1 9873 03f0 03D0 beq .L524 9874 .L478: 434:Src/main.c **** } 9875 .loc 1 434 7 is_stmt 1 view .LVU3180 434:Src/main.c **** } 9876 .loc 1 434 21 is_stmt 0 view .LVU3181 9877 03f2 604B ldr r3, .L533+40 9878 03f4 0722 movs r2, #7 9879 03f6 1A70 strb r2, [r3] 9880 03f8 7BE6 b .L461 9881 .L524: 429:Src/main.c **** Long_Data[DL_16-1] = CS_result; 9882 .loc 1 429 8 is_stmt 1 view .LVU3182 429:Src/main.c **** Long_Data[DL_16-1] = CS_result; 9883 .loc 1 429 20 is_stmt 0 view .LVU3183 9884 03fa 0234 adds r4, r4, #2 9885 03fc 0D21 movs r1, #13 9886 03fe 2046 mov r0, r4 9887 0400 FFF7FEFF bl CalculateChecksum 9888 .LVL818: 9889 0404 0346 mov r3, r0 429:Src/main.c **** Long_Data[DL_16-1] = CS_result; 9890 .loc 1 429 18 discriminator 1 view .LVU3184 9891 0406 5C4A ldr r2, .L533+44 9892 0408 1080 strh r0, [r2] @ movhi 430:Src/main.c **** temp16 = SD_SAVE(&Long_Data[0]); 9893 .loc 1 430 8 is_stmt 1 view .LVU3185 430:Src/main.c **** temp16 = SD_SAVE(&Long_Data[0]); 9894 .loc 1 430 27 is_stmt 0 view .LVU3186 9895 040a A01E subs r0, r4, #2 9896 040c 8383 strh r3, [r0, #28] @ movhi 431:Src/main.c **** State_Data[0]|=temp16&0xff; 9897 .loc 1 431 8 is_stmt 1 view .LVU3187 431:Src/main.c **** State_Data[0]|=temp16&0xff; 9898 .loc 1 431 17 is_stmt 0 view .LVU3188 9899 040e FFF7FEFF bl SD_SAVE 9900 .LVL819: 9901 0412 0346 mov r3, r0 431:Src/main.c **** State_Data[0]|=temp16&0xff; 9902 .loc 1 431 15 discriminator 1 view .LVU3189 9903 0414 2880 strh r0, [r5] @ movhi 432:Src/main.c **** } 9904 .loc 1 432 8 is_stmt 1 view .LVU3190 432:Src/main.c **** } 9905 .loc 1 432 18 is_stmt 0 view .LVU3191 9906 0416 5949 ldr r1, .L533+48 9907 0418 0A78 ldrb r2, [r1] @ zero_extendqisi2 432:Src/main.c **** } 9908 .loc 1 432 21 view .LVU3192 9909 041a 1343 orrs r3, r3, r2 ARM GAS /tmp/ccYgfTud.s page 568 9910 041c 0B70 strb r3, [r1] 9911 041e E8E7 b .L478 9912 .L462: 438:Src/main.c **** { 9913 .loc 1 438 6 is_stmt 1 view .LVU3193 438:Src/main.c **** { 9914 .loc 1 438 10 is_stmt 0 view .LVU3194 9915 0420 574C ldr r4, .L533+52 9916 0422 0321 movs r1, #3 9917 0424 2046 mov r0, r4 9918 0426 FFF7FEFF bl CalculateChecksum 9919 .LVL820: 438:Src/main.c **** { 9920 .loc 1 438 69 discriminator 1 view .LVU3195 9921 042a E388 ldrh r3, [r4, #6] 438:Src/main.c **** { 9922 .loc 1 438 9 discriminator 1 view .LVU3196 9923 042c 9842 cmp r0, r3 9924 042e 0CD0 beq .L525 481:Src/main.c **** } 9925 .loc 1 481 7 is_stmt 1 view .LVU3197 481:Src/main.c **** } 9926 .loc 1 481 17 is_stmt 0 view .LVU3198 9927 0430 524A ldr r2, .L533+48 9928 0432 1378 ldrb r3, [r2] @ zero_extendqisi2 481:Src/main.c **** } 9929 .loc 1 481 21 view .LVU3199 9930 0434 43F00403 orr r3, r3, #4 9931 0438 1370 strb r3, [r2] 9932 .L483: 483:Src/main.c **** CPU_state = CPU_state_old; 9933 .loc 1 483 6 is_stmt 1 view .LVU3200 483:Src/main.c **** CPU_state = CPU_state_old; 9934 .loc 1 483 32 is_stmt 0 view .LVU3201 9935 043a 524B ldr r3, .L533+56 9936 043c 0122 movs r2, #1 9937 043e 1A70 strb r2, [r3] 484:Src/main.c **** break; 9938 .loc 1 484 6 is_stmt 1 view .LVU3202 484:Src/main.c **** break; 9939 .loc 1 484 16 is_stmt 0 view .LVU3203 9940 0440 4C4B ldr r3, .L533+40 9941 0442 1A78 ldrb r2, [r3] @ zero_extendqisi2 9942 0444 504B ldr r3, .L533+60 9943 0446 1A70 strb r2, [r3] 485:Src/main.c **** case DECODE_TASK: 9944 .loc 1 485 5 is_stmt 1 view .LVU3204 9945 0448 53E6 b .L461 9946 .L525: 9947 .LBB650: 440:Src/main.c **** uint16_t param0 = COMMAND[1]; 9948 .loc 1 440 7 view .LVU3205 440:Src/main.c **** uint16_t param0 = COMMAND[1]; 9949 .loc 1 440 16 is_stmt 0 view .LVU3206 9950 044a 2288 ldrh r2, [r4] 9951 .LVL821: 441:Src/main.c **** uint16_t param1 = COMMAND[2]; ARM GAS /tmp/ccYgfTud.s page 569 9952 .loc 1 441 7 is_stmt 1 view .LVU3207 441:Src/main.c **** uint16_t param1 = COMMAND[2]; 9953 .loc 1 441 16 is_stmt 0 view .LVU3208 9954 044c 6388 ldrh r3, [r4, #2] 9955 .LVL822: 442:Src/main.c **** uint8_t enable = (flags & AD9102_FLAG_ENABLE) ? 1u : 0u; 9956 .loc 1 442 7 is_stmt 1 view .LVU3209 442:Src/main.c **** uint8_t enable = (flags & AD9102_FLAG_ENABLE) ? 1u : 0u; 9957 .loc 1 442 16 is_stmt 0 view .LVU3210 9958 044e A488 ldrh r4, [r4, #4] 9959 .LVL823: 443:Src/main.c **** uint8_t triangle = (flags & AD9102_FLAG_TRIANGLE) ? 1u : 0u; 9960 .loc 1 443 7 is_stmt 1 view .LVU3211 443:Src/main.c **** uint8_t triangle = (flags & AD9102_FLAG_TRIANGLE) ? 1u : 0u; 9961 .loc 1 443 15 is_stmt 0 view .LVU3212 9962 0450 02F00108 and r8, r2, #1 9963 .LVL824: 444:Src/main.c **** uint8_t saw_type = triangle ? AD9102_SAW_TYPE_TRI : AD9102_SAW_TYPE_UP; 9964 .loc 1 444 7 is_stmt 1 view .LVU3213 444:Src/main.c **** uint8_t saw_type = triangle ? AD9102_SAW_TYPE_TRI : AD9102_SAW_TYPE_UP; 9965 .loc 1 444 15 is_stmt 0 view .LVU3214 9966 0454 C2F34006 ubfx r6, r2, #1, #1 9967 .LVL825: 445:Src/main.c **** uint8_t saw_step = (uint8_t)(param0 & 0x00FFu); 9968 .loc 1 445 7 is_stmt 1 view .LVU3215 445:Src/main.c **** uint8_t saw_step = (uint8_t)(param0 & 0x00FFu); 9969 .loc 1 445 15 is_stmt 0 view .LVU3216 9970 0458 12F0020F tst r2, #2 9971 045c 00D0 beq .L480 445:Src/main.c **** uint8_t saw_step = (uint8_t)(param0 & 0x00FFu); 9972 .loc 1 445 15 discriminator 1 view .LVU3217 9973 045e 0226 movs r6, #2 9974 .LVL826: 9975 .L480: 446:Src/main.c **** uint8_t pat_base = (uint8_t)((param0 >> 8) & 0x0Fu); 9976 .loc 1 446 7 is_stmt 1 view .LVU3218 446:Src/main.c **** uint8_t pat_base = (uint8_t)((param0 >> 8) & 0x0Fu); 9977 .loc 1 446 15 is_stmt 0 view .LVU3219 9978 0460 DDB2 uxtb r5, r3 9979 .LVL827: 447:Src/main.c **** uint16_t pat_period = param1; 9980 .loc 1 447 7 is_stmt 1 view .LVU3220 447:Src/main.c **** uint16_t pat_period = param1; 9981 .loc 1 447 15 is_stmt 0 view .LVU3221 9982 0462 C3F30327 ubfx r7, r3, #8, #4 9983 .LVL828: 448:Src/main.c **** 9984 .loc 1 448 7 is_stmt 1 view .LVU3222 450:Src/main.c **** { 9985 .loc 1 450 7 view .LVU3223 450:Src/main.c **** { 9986 .loc 1 450 10 is_stmt 0 view .LVU3224 9987 0466 2343 orrs r3, r3, r4 9988 .LVL829: 450:Src/main.c **** { 9989 .loc 1 450 10 view .LVU3225 9990 0468 09D0 beq .L514 ARM GAS /tmp/ccYgfTud.s page 570 458:Src/main.c **** { 9991 .loc 1 458 8 is_stmt 1 view .LVU3226 458:Src/main.c **** { 9992 .loc 1 458 11 is_stmt 0 view .LVU3227 9993 046a 1DB1 cbz r5, .L515 462:Src/main.c **** { 9994 .loc 1 462 13 is_stmt 1 view .LVU3228 462:Src/main.c **** { 9995 .loc 1 462 16 is_stmt 0 view .LVU3229 9996 046c 3F2D cmp r5, #63 9997 046e 02D9 bls .L482 464:Src/main.c **** } 9998 .loc 1 464 18 view .LVU3230 9999 0470 3F25 movs r5, #63 10000 .LVL830: 464:Src/main.c **** } 10001 .loc 1 464 18 view .LVU3231 10002 0472 00E0 b .L482 10003 .LVL831: 10004 .L515: 460:Src/main.c **** } 10005 .loc 1 460 18 view .LVU3232 10006 0474 0125 movs r5, #1 10007 .LVL832: 10008 .L482: 466:Src/main.c **** { 10009 .loc 1 466 8 is_stmt 1 view .LVU3233 466:Src/main.c **** { 10010 .loc 1 466 11 is_stmt 0 view .LVU3234 10011 0476 34B9 cbnz r4, .L481 468:Src/main.c **** } 10012 .loc 1 468 20 view .LVU3235 10013 0478 4FF6FF74 movw r4, #65535 10014 .LVL833: 468:Src/main.c **** } 10015 .loc 1 468 20 view .LVU3236 10016 047c 03E0 b .L481 10017 .LVL834: 10018 .L514: 454:Src/main.c **** } 10019 .loc 1 454 19 view .LVU3237 10020 047e 4FF6FF74 movw r4, #65535 10021 .LVL835: 453:Src/main.c **** pat_period = AD9102_PAT_PERIOD_DEFAULT; 10022 .loc 1 453 17 view .LVU3238 10023 0482 0227 movs r7, #2 10024 .LVL836: 452:Src/main.c **** pat_base = AD9102_PAT_PERIOD_BASE_DEFAULT; 10025 .loc 1 452 17 view .LVU3239 10026 0484 0125 movs r5, #1 10027 .LVL837: 10028 .L481: 472:Src/main.c **** State_Data[1] = (uint8_t)(pat_status & 0x00FFu); 10029 .loc 1 472 7 is_stmt 1 view .LVU3240 472:Src/main.c **** State_Data[1] = (uint8_t)(pat_status & 0x00FFu); 10030 .loc 1 472 29 is_stmt 0 view .LVU3241 10031 0486 0094 str r4, [sp] ARM GAS /tmp/ccYgfTud.s page 571 10032 0488 3B46 mov r3, r7 10033 048a 2A46 mov r2, r5 10034 .LVL838: 472:Src/main.c **** State_Data[1] = (uint8_t)(pat_status & 0x00FFu); 10035 .loc 1 472 29 view .LVU3242 10036 048c 4146 mov r1, r8 10037 048e 3046 mov r0, r6 10038 0490 FFF7FEFF bl AD9102_Apply 10039 .LVL839: 473:Src/main.c **** if (AD9102_CheckFlags(pat_status, enable, saw_type, saw_step, pat_base, pat_period)) 10040 .loc 1 473 7 is_stmt 1 view .LVU3243 473:Src/main.c **** if (AD9102_CheckFlags(pat_status, enable, saw_type, saw_step, pat_base, pat_period)) 10041 .loc 1 473 21 is_stmt 0 view .LVU3244 10042 0494 394B ldr r3, .L533+48 10043 0496 5870 strb r0, [r3, #1] 474:Src/main.c **** { 10044 .loc 1 474 7 is_stmt 1 view .LVU3245 474:Src/main.c **** { 10045 .loc 1 474 11 is_stmt 0 view .LVU3246 10046 0498 0194 str r4, [sp, #4] 10047 049a 0097 str r7, [sp] 10048 049c 2B46 mov r3, r5 10049 049e 3246 mov r2, r6 10050 04a0 4146 mov r1, r8 10051 04a2 FFF7FEFF bl AD9102_CheckFlags 10052 .LVL840: 474:Src/main.c **** { 10053 .loc 1 474 10 discriminator 1 view .LVU3247 10054 04a6 0028 cmp r0, #0 10055 04a8 C7D0 beq .L483 476:Src/main.c **** } 10056 .loc 1 476 8 is_stmt 1 view .LVU3248 476:Src/main.c **** } 10057 .loc 1 476 18 is_stmt 0 view .LVU3249 10058 04aa 344A ldr r2, .L533+48 10059 04ac 1378 ldrb r3, [r2] @ zero_extendqisi2 476:Src/main.c **** } 10060 .loc 1 476 22 view .LVU3250 10061 04ae 63F07F03 orn r3, r3, #127 10062 04b2 1370 strb r3, [r2] 10063 04b4 C1E7 b .L483 10064 .LVL841: 10065 .L465: 476:Src/main.c **** } 10066 .loc 1 476 22 view .LVU3251 10067 .LBE650: 487:Src/main.c **** { 10068 .loc 1 487 6 is_stmt 1 view .LVU3252 487:Src/main.c **** { 10069 .loc 1 487 10 is_stmt 0 view .LVU3253 10070 04b6 3248 ldr r0, .L533+52 10071 04b8 FFF7FEFF bl CheckChecksum 10072 .LVL842: 487:Src/main.c **** { 10073 .loc 1 487 9 discriminator 1 view .LVU3254 10074 04bc 70B9 cbnz r0, .L526 496:Src/main.c **** CPU_state = DEFAULT_ENABLE; ARM GAS /tmp/ccYgfTud.s page 572 10075 .loc 1 496 7 is_stmt 1 view .LVU3255 496:Src/main.c **** CPU_state = DEFAULT_ENABLE; 10076 .loc 1 496 17 is_stmt 0 view .LVU3256 10077 04be 2F4A ldr r2, .L533+48 10078 04c0 1378 ldrb r3, [r2] @ zero_extendqisi2 496:Src/main.c **** CPU_state = DEFAULT_ENABLE; 10079 .loc 1 496 21 view .LVU3257 10080 04c2 43F00403 orr r3, r3, #4 10081 04c6 1370 strb r3, [r2] 497:Src/main.c **** CPU_state_old = HALT;//Save main current cycle 10082 .loc 1 497 7 is_stmt 1 view .LVU3258 497:Src/main.c **** CPU_state_old = HALT;//Save main current cycle 10083 .loc 1 497 17 is_stmt 0 view .LVU3259 10084 04c8 2F4B ldr r3, .L533+60 10085 04ca 0222 movs r2, #2 10086 04cc 1A70 strb r2, [r3] 498:Src/main.c **** } 10087 .loc 1 498 7 is_stmt 1 view .LVU3260 498:Src/main.c **** } 10088 .loc 1 498 21 is_stmt 0 view .LVU3261 10089 04ce 294B ldr r3, .L533+40 10090 04d0 0022 movs r2, #0 10091 04d2 1A70 strb r2, [r3] 10092 .L485: 500:Src/main.c **** break; 10093 .loc 1 500 6 is_stmt 1 view .LVU3262 500:Src/main.c **** break; 10094 .loc 1 500 32 is_stmt 0 view .LVU3263 10095 04d4 2B4B ldr r3, .L533+56 10096 04d6 0122 movs r2, #1 10097 04d8 1A70 strb r2, [r3] 501:Src/main.c **** case RUN_TASK: 10098 .loc 1 501 5 is_stmt 1 view .LVU3264 10099 04da 0AE6 b .L461 10100 .L526: 489:Src/main.c **** TO6_before = TO6; 10101 .loc 1 489 7 view .LVU3265 10102 04dc 244B ldr r3, .L533+36 10103 04de 2B4A ldr r2, .L533+64 10104 04e0 2B49 ldr r1, .L533+68 10105 04e2 2748 ldr r0, .L533+52 10106 04e4 FFF7FEFF bl Decode_task 10107 .LVL843: 490:Src/main.c **** CPU_state = RUN_TASK; 10108 .loc 1 490 7 view .LVU3266 490:Src/main.c **** CPU_state = RUN_TASK; 10109 .loc 1 490 18 is_stmt 0 view .LVU3267 10110 04e8 1F4B ldr r3, .L533+28 10111 04ea 1A68 ldr r2, [r3] 10112 04ec 294B ldr r3, .L533+72 10113 04ee 1A60 str r2, [r3] 491:Src/main.c **** CPU_state_old = RUN_TASK;//Save main current cycle 10114 .loc 1 491 7 is_stmt 1 view .LVU3268 491:Src/main.c **** CPU_state_old = RUN_TASK;//Save main current cycle 10115 .loc 1 491 17 is_stmt 0 view .LVU3269 10116 04f0 0923 movs r3, #9 10117 04f2 254A ldr r2, .L533+60 ARM GAS /tmp/ccYgfTud.s page 573 10118 04f4 1370 strb r3, [r2] 492:Src/main.c **** } 10119 .loc 1 492 7 is_stmt 1 view .LVU3270 492:Src/main.c **** } 10120 .loc 1 492 21 is_stmt 0 view .LVU3271 10121 04f6 1F4A ldr r2, .L533+40 10122 04f8 1370 strb r3, [r2] 10123 04fa EBE7 b .L485 10124 .L464: 503:Src/main.c **** { 10125 .loc 1 503 6 is_stmt 1 view .LVU3272 503:Src/main.c **** { 10126 .loc 1 503 18 is_stmt 0 view .LVU3273 10127 04fc 134B ldr r3, .L533 10128 04fe 1B78 ldrb r3, [r3] @ zero_extendqisi2 10129 0500 012B cmp r3, #1 10130 0502 53D0 beq .L486 10131 0504 022B cmp r3, #2 10132 0506 00F03681 beq .L487 10133 .L488: 758:Src/main.c **** { 10134 .loc 1 758 6 is_stmt 1 view .LVU3274 758:Src/main.c **** { 10135 .loc 1 758 13 is_stmt 0 view .LVU3275 10136 050a 114B ldr r3, .L533+4 10137 050c 1B68 ldr r3, [r3] 10138 050e 114A ldr r2, .L533+8 10139 0510 1268 ldr r2, [r2] 758:Src/main.c **** { 10140 .loc 1 758 9 view .LVU3276 10141 0512 9342 cmp r3, r2 10142 0514 00F20782 bhi .L527 10143 .L505: 810:Src/main.c **** 10144 .loc 1 810 13 is_stmt 1 discriminator 1 view .LVU3277 10145 0518 1F4B ldr r3, .L533+76 10146 051a 1B78 ldrb r3, [r3] @ zero_extendqisi2 10147 051c 002B cmp r3, #0 10148 051e FBD0 beq .L505 812:Src/main.c **** 10149 .loc 1 812 6 view .LVU3278 10150 0520 FFF7FEFF bl Stop_TIM10 10151 .LVL844: 814:Src/main.c **** { 10152 .loc 1 814 6 view .LVU3279 814:Src/main.c **** { 10153 .loc 1 814 14 is_stmt 0 view .LVU3280 10154 0524 094B ldr r3, .L533 10155 0526 DB8A ldrh r3, [r3, #22] 814:Src/main.c **** { 10156 .loc 1 814 9 view .LVU3281 10157 0528 032B cmp r3, #3 10158 052a 0BD9 bls .L506 816:Src/main.c **** TO10_counter = task.dt / 10; 10159 .loc 1 816 7 is_stmt 1 view .LVU3282 816:Src/main.c **** TO10_counter = task.dt / 10; 10160 .loc 1 816 26 is_stmt 0 view .LVU3283 ARM GAS /tmp/ccYgfTud.s page 574 10161 052c 1B4B ldr r3, .L533+80 10162 052e 1A68 ldr r2, [r3] 10163 0530 1B4B ldr r3, .L533+84 10164 0532 DA60 str r2, [r3, #12] 817:Src/main.c **** } 10165 .loc 1 817 7 is_stmt 1 view .LVU3284 817:Src/main.c **** } 10166 .loc 1 817 26 is_stmt 0 view .LVU3285 10167 0534 054B ldr r3, .L533 10168 0536 1B7D ldrb r3, [r3, #20] @ zero_extendqisi2 817:Src/main.c **** } 10169 .loc 1 817 30 view .LVU3286 10170 0538 1A4A ldr r2, .L533+88 10171 053a A2FB0323 umull r2, r3, r2, r3 10172 053e DB08 lsrs r3, r3, #3 817:Src/main.c **** } 10173 .loc 1 817 20 view .LVU3287 10174 0540 194A ldr r2, .L533+92 10175 0542 1360 str r3, [r2] 10176 .L506: 820:Src/main.c **** break; 10177 .loc 1 820 6 is_stmt 1 view .LVU3288 820:Src/main.c **** break; 10178 .loc 1 820 20 is_stmt 0 view .LVU3289 10179 0544 0B4B ldr r3, .L533+40 10180 0546 0922 movs r2, #9 10181 0548 1A70 strb r2, [r3] 821:Src/main.c **** } 10182 .loc 1 821 9 is_stmt 1 view .LVU3290 10183 054a D2E5 b .L461 10184 .L534: 10185 .align 2 10186 .L533: 10187 054c 00000000 .word task 10188 0550 00000000 .word TO7 10189 0554 00000000 .word TO7_before 10190 0558 00000000 .word LD1_param 10191 055c 00000000 .word LD2_param 10192 0560 00000000 .word temp16 10193 0564 00000000 .word Long_Data 10194 0568 00000000 .word TO6 10195 056c 00000000 .word TO6_stop 10196 0570 00000000 .word Curr_setup 10197 0574 00000000 .word CPU_state_old 10198 0578 00000000 .word CS_result 10199 057c 00000000 .word State_Data 10200 0580 00000000 .word COMMAND 10201 0584 00000000 .word UART_transmission_request 10202 0588 00000000 .word CPU_state 10203 058c 00000000 .word LD2_curr_setup 10204 0590 00000000 .word LD1_curr_setup 10205 0594 00000000 .word TO6_before 10206 0598 00000000 .word TIM10_coflag 10207 059c 00000000 .word TIM10_period 10208 05a0 00000000 .word htim10 10209 05a4 CDCCCCCC .word -858993459 10210 05a8 00000000 .word TO10_counter ARM GAS /tmp/ccYgfTud.s page 575 10211 .L486: 10212 .LBB651: 525:Src/main.c **** (void) MPhD_T(TT_CHANGE_TEMP_1); 10213 .loc 1 525 7 view .LVU3291 525:Src/main.c **** (void) MPhD_T(TT_CHANGE_TEMP_1); 10214 .loc 1 525 38 is_stmt 0 view .LVU3292 10215 05ac AD4B ldr r3, .L535 10216 05ae D3ED077A vldr.32 s15, [r3, #28] 525:Src/main.c **** (void) MPhD_T(TT_CHANGE_TEMP_1); 10217 .loc 1 525 7 view .LVU3293 10218 05b2 FCEEE77A vcvt.u32.f32 s15, s15 10219 05b6 17EE903A vmov r3, s15 @ int 10220 05ba 99B2 uxth r1, r3 10221 05bc 0220 movs r0, #2 10222 05be FFF7FEFF bl Set_LTEC 10223 .LVL845: 526:Src/main.c **** LD1_param.LD_CURR_TEMP = MPhD_T(TT_CHANGE_TEMP_1); 10224 .loc 1 526 7 is_stmt 1 view .LVU3294 526:Src/main.c **** LD1_param.LD_CURR_TEMP = MPhD_T(TT_CHANGE_TEMP_1); 10225 .loc 1 526 14 is_stmt 0 view .LVU3295 10226 05c2 0320 movs r0, #3 10227 05c4 FFF7FEFF bl MPhD_T 10228 .LVL846: 527:Src/main.c **** (void) MPhD_T(TT_CHANGE_TEMP_2); 10229 .loc 1 527 7 is_stmt 1 view .LVU3296 527:Src/main.c **** (void) MPhD_T(TT_CHANGE_TEMP_2); 10230 .loc 1 527 32 is_stmt 0 view .LVU3297 10231 05c8 0320 movs r0, #3 10232 05ca FFF7FEFF bl MPhD_T 10233 .LVL847: 527:Src/main.c **** (void) MPhD_T(TT_CHANGE_TEMP_2); 10234 .loc 1 527 30 discriminator 1 view .LVU3298 10235 05ce A64C ldr r4, .L535+4 10236 05d0 2080 strh r0, [r4] @ movhi 528:Src/main.c **** LD2_param.LD_CURR_TEMP = MPhD_T(TT_CHANGE_TEMP_2); 10237 .loc 1 528 7 is_stmt 1 view .LVU3299 528:Src/main.c **** LD2_param.LD_CURR_TEMP = MPhD_T(TT_CHANGE_TEMP_2); 10238 .loc 1 528 14 is_stmt 0 view .LVU3300 10239 05d2 0420 movs r0, #4 10240 05d4 FFF7FEFF bl MPhD_T 10241 .LVL848: 529:Src/main.c **** temp16=PID_Controller_Temp(&LD1_curr_setup, &LD1_param, 1); 10242 .loc 1 529 7 is_stmt 1 view .LVU3301 529:Src/main.c **** temp16=PID_Controller_Temp(&LD1_curr_setup, &LD1_param, 1); 10243 .loc 1 529 32 is_stmt 0 view .LVU3302 10244 05d8 0420 movs r0, #4 10245 05da FFF7FEFF bl MPhD_T 10246 .LVL849: 529:Src/main.c **** temp16=PID_Controller_Temp(&LD1_curr_setup, &LD1_param, 1); 10247 .loc 1 529 30 discriminator 1 view .LVU3303 10248 05de A34D ldr r5, .L535+8 10249 05e0 2880 strh r0, [r5] @ movhi 530:Src/main.c **** Set_LTEC(TT_CHANGE_TEMP_1, temp16);//Drive Laser TEC 1 10250 .loc 1 530 7 is_stmt 1 view .LVU3304 530:Src/main.c **** Set_LTEC(TT_CHANGE_TEMP_1, temp16);//Drive Laser TEC 1 10251 .loc 1 530 14 is_stmt 0 view .LVU3305 10252 05e2 0122 movs r2, #1 ARM GAS /tmp/ccYgfTud.s page 576 10253 05e4 2146 mov r1, r4 10254 05e6 A248 ldr r0, .L535+12 10255 05e8 FFF7FEFF bl PID_Controller_Temp 10256 .LVL850: 10257 05ec 0146 mov r1, r0 530:Src/main.c **** Set_LTEC(TT_CHANGE_TEMP_1, temp16);//Drive Laser TEC 1 10258 .loc 1 530 13 discriminator 1 view .LVU3306 10259 05ee A14C ldr r4, .L535+16 10260 05f0 2080 strh r0, [r4] @ movhi 531:Src/main.c **** temp16=PID_Controller_Temp(&LD2_curr_setup, &LD2_param, 2); 10261 .loc 1 531 7 is_stmt 1 view .LVU3307 10262 05f2 0320 movs r0, #3 10263 05f4 FFF7FEFF bl Set_LTEC 10264 .LVL851: 532:Src/main.c **** Set_LTEC(TT_CHANGE_TEMP_2, temp16);//Drive Laser TEC 2 10265 .loc 1 532 7 view .LVU3308 532:Src/main.c **** Set_LTEC(TT_CHANGE_TEMP_2, temp16);//Drive Laser TEC 2 10266 .loc 1 532 14 is_stmt 0 view .LVU3309 10267 05f8 0222 movs r2, #2 10268 05fa 2946 mov r1, r5 10269 05fc 9E48 ldr r0, .L535+20 10270 05fe FFF7FEFF bl PID_Controller_Temp 10271 .LVL852: 10272 0602 0146 mov r1, r0 532:Src/main.c **** Set_LTEC(TT_CHANGE_TEMP_2, temp16);//Drive Laser TEC 2 10273 .loc 1 532 13 discriminator 1 view .LVU3310 10274 0604 2080 strh r0, [r4] @ movhi 533:Src/main.c **** 10275 .loc 1 533 7 is_stmt 1 view .LVU3311 10276 0606 0420 movs r0, #4 10277 0608 FFF7FEFF bl Set_LTEC 10278 .LVL853: 536:Src/main.c **** HAL_GPIO_WritePin(GPIOD, GPIO_PIN_7, GPIO_PIN_RESET); 10279 .loc 1 536 7 view .LVU3312 10280 060c 9B4C ldr r4, .L535+24 10281 060e 0122 movs r2, #1 10282 0610 8021 movs r1, #128 10283 0612 2046 mov r0, r4 10284 0614 FFF7FEFF bl HAL_GPIO_WritePin 10285 .LVL854: 537:Src/main.c **** 10286 .loc 1 537 7 view .LVU3313 10287 0618 0022 movs r2, #0 10288 061a 8021 movs r1, #128 10289 061c 2046 mov r0, r4 10290 061e FFF7FEFF bl HAL_GPIO_WritePin 10291 .LVL855: 539:Src/main.c **** if (st != HAL_OK) 10292 .loc 1 539 7 view .LVU3314 539:Src/main.c **** if (st != HAL_OK) 10293 .loc 1 539 12 is_stmt 0 view .LVU3315 10294 0622 9748 ldr r0, .L535+28 10295 0624 FFF7FEFF bl HAL_TIM_Base_Start_IT 10296 .LVL856: 540:Src/main.c **** while(1); 10297 .loc 1 540 7 is_stmt 1 view .LVU3316 540:Src/main.c **** while(1); ARM GAS /tmp/ccYgfTud.s page 577 10298 .loc 1 540 10 is_stmt 0 view .LVU3317 10299 0628 0028 cmp r0, #0 10300 062a 75D1 bne .L490 543:Src/main.c **** uint16_t trigger_counter = 0; 10301 .loc 1 543 7 is_stmt 1 view .LVU3318 10302 .LVL857: 544:Src/main.c **** uint16_t trigger_step = (uint8_t )((task.max_param - task.current_param)/task.delta_param * 1 10303 .loc 1 544 7 view .LVU3319 545:Src/main.c **** uint16_t task_sheduler = 0; 10304 .loc 1 545 7 view .LVU3320 545:Src/main.c **** uint16_t task_sheduler = 0; 10305 .loc 1 545 47 is_stmt 0 view .LVU3321 10306 062c 8D4B ldr r3, .L535 10307 062e 93ED027A vldr.32 s14, [r3, #8] 545:Src/main.c **** uint16_t task_sheduler = 0; 10308 .loc 1 545 64 view .LVU3322 10309 0632 D3ED047A vldr.32 s15, [r3, #16] 545:Src/main.c **** uint16_t task_sheduler = 0; 10310 .loc 1 545 58 view .LVU3323 10311 0636 37EE677A vsub.f32 s14, s14, s15 545:Src/main.c **** uint16_t task_sheduler = 0; 10312 .loc 1 545 84 view .LVU3324 10313 063a D3ED036A vldr.32 s13, [r3, #12] 545:Src/main.c **** uint16_t task_sheduler = 0; 10314 .loc 1 545 79 view .LVU3325 10315 063e C7EE267A vdiv.f32 s15, s14, s13 545:Src/main.c **** uint16_t task_sheduler = 0; 10316 .loc 1 545 97 view .LVU3326 10317 0642 B2EE047A vmov.f32 s14, #1.0e+1 10318 0646 67EE877A vmul.f32 s15, s15, s14 545:Src/main.c **** uint16_t task_sheduler = 0; 10319 .loc 1 545 31 view .LVU3327 10320 064a FCEEE77A vcvt.u32.f32 s15, s15 10321 064e CDED037A vstr.32 s15, [sp, #12] @ int 10322 0652 9DF80C60 ldrb r6, [sp, #12] @ zero_extendqisi2 10323 .LVL858: 546:Src/main.c **** 10324 .loc 1 546 7 is_stmt 1 view .LVU3328 550:Src/main.c **** HAL_TIM_PWM_Stop(&htim4, TIM_CHANNEL_3); //start ADC clock 10325 .loc 1 550 7 view .LVU3329 10326 0656 DFF85492 ldr r9, .L535+72 10327 065a 0021 movs r1, #0 10328 065c 4846 mov r0, r9 10329 .LVL859: 550:Src/main.c **** HAL_TIM_PWM_Stop(&htim4, TIM_CHANNEL_3); //start ADC clock 10330 .loc 1 550 7 is_stmt 0 view .LVU3330 10331 065e FFF7FEFF bl HAL_TIM_PWM_Stop 10332 .LVL860: 551:Src/main.c **** TIM11 -> CR1 &= ~(1 << 3); //disables one-pulse mode 10333 .loc 1 551 7 is_stmt 1 view .LVU3331 10334 0662 DFF84C82 ldr r8, .L535+76 10335 0666 0821 movs r1, #8 10336 0668 4046 mov r0, r8 10337 066a FFF7FEFF bl HAL_TIM_PWM_Stop 10338 .LVL861: 552:Src/main.c **** TIM4 -> CR1 &= ~(1 << 3); //disables one-pulse mode 10339 .loc 1 552 7 view .LVU3332 ARM GAS /tmp/ccYgfTud.s page 578 552:Src/main.c **** TIM4 -> CR1 &= ~(1 << 3); //disables one-pulse mode 10340 .loc 1 552 13 is_stmt 0 view .LVU3333 10341 066e 854F ldr r7, .L535+32 10342 0670 3B68 ldr r3, [r7] 552:Src/main.c **** TIM4 -> CR1 &= ~(1 << 3); //disables one-pulse mode 10343 .loc 1 552 20 view .LVU3334 10344 0672 23F00803 bic r3, r3, #8 10345 0676 3B60 str r3, [r7] 553:Src/main.c **** 10346 .loc 1 553 7 is_stmt 1 view .LVU3335 553:Src/main.c **** 10347 .loc 1 553 12 is_stmt 0 view .LVU3336 10348 0678 834D ldr r5, .L535+36 10349 067a 2B68 ldr r3, [r5] 553:Src/main.c **** 10350 .loc 1 553 19 view .LVU3337 10351 067c 23F00803 bic r3, r3, #8 10352 0680 2B60 str r3, [r5] 557:Src/main.c **** TIM4 -> CNT = 0; 10353 .loc 1 557 7 is_stmt 1 view .LVU3338 557:Src/main.c **** TIM4 -> CNT = 0; 10354 .loc 1 557 20 is_stmt 0 view .LVU3339 10355 0682 0024 movs r4, #0 10356 0684 7C62 str r4, [r7, #36] 558:Src/main.c **** 10357 .loc 1 558 7 is_stmt 1 view .LVU3340 558:Src/main.c **** 10358 .loc 1 558 19 is_stmt 0 view .LVU3341 10359 0686 6C62 str r4, [r5, #36] 560:Src/main.c **** HAL_TIM_PWM_Start(&htim4, TIM_CHANNEL_3); //start ADC clock 10360 .loc 1 560 7 is_stmt 1 view .LVU3342 10361 0688 2146 mov r1, r4 10362 068a 4846 mov r0, r9 10363 068c FFF7FEFF bl HAL_TIM_PWM_Start 10364 .LVL862: 561:Src/main.c **** //TIM4 -> CNT = 0; 10365 .loc 1 561 7 view .LVU3343 10366 0690 0821 movs r1, #8 10367 0692 4046 mov r0, r8 10368 0694 FFF7FEFF bl HAL_TIM_PWM_Start 10369 .LVL863: 564:Src/main.c **** TIM11 -> CNT = 0; 10370 .loc 1 564 7 view .LVU3344 564:Src/main.c **** TIM11 -> CNT = 0; 10371 .loc 1 564 26 is_stmt 0 view .LVU3345 10372 0698 EB6A ldr r3, [r5, #44] 564:Src/main.c **** TIM11 -> CNT = 0; 10373 .loc 1 564 33 view .LVU3346 10374 069a 143B subs r3, r3, #20 564:Src/main.c **** TIM11 -> CNT = 0; 10375 .loc 1 564 19 view .LVU3347 10376 069c 6B62 str r3, [r5, #36] 565:Src/main.c **** 10377 .loc 1 565 7 is_stmt 1 view .LVU3348 565:Src/main.c **** 10378 .loc 1 565 20 is_stmt 0 view .LVU3349 10379 069e 7C62 str r4, [r7, #36] ARM GAS /tmp/ccYgfTud.s page 579 568:Src/main.c **** { 10380 .loc 1 568 7 is_stmt 1 view .LVU3350 544:Src/main.c **** uint16_t trigger_step = (uint8_t )((task.max_param - task.current_param)/task.delta_param * 1 10381 .loc 1 544 16 is_stmt 0 view .LVU3351 10382 06a0 2546 mov r5, r4 10383 .LVL864: 10384 .L492: 568:Src/main.c **** { 10385 .loc 1 568 33 is_stmt 1 view .LVU3352 568:Src/main.c **** { 10386 .loc 1 568 18 is_stmt 0 view .LVU3353 10387 06a2 704B ldr r3, .L535 10388 06a4 D3ED047A vldr.32 s15, [r3, #16] 568:Src/main.c **** { 10389 .loc 1 568 39 view .LVU3354 10390 06a8 93ED027A vldr.32 s14, [r3, #8] 568:Src/main.c **** { 10391 .loc 1 568 33 view .LVU3355 10392 06ac F4EEC77A vcmpe.f32 s15, s14 10393 06b0 F1EE10FA vmrs APSR_nzcv, FPSCR 10394 06b4 37D5 bpl .L528 570:Src/main.c **** { 10395 .loc 1 570 8 is_stmt 1 view .LVU3356 570:Src/main.c **** { 10396 .loc 1 570 12 is_stmt 0 view .LVU3357 10397 06b6 754B ldr r3, .L535+40 10398 06b8 1B78 ldrb r3, [r3] @ zero_extendqisi2 570:Src/main.c **** { 10399 .loc 1 570 11 view .LVU3358 10400 06ba 002B cmp r3, #0 10401 06bc F1D0 beq .L492 572:Src/main.c **** //TIM11 -> CNT = 0; // to link modulator phase 10402 .loc 1 572 9 is_stmt 1 view .LVU3359 10403 06be FCEEE77A vcvt.u32.f32 s15, s15 10404 06c2 17EE903A vmov r3, s15 @ int 10405 06c6 99B2 uxth r1, r3 10406 06c8 0120 movs r0, #1 10407 06ca FFF7FEFF bl Set_LTEC 10408 .LVL865: 575:Src/main.c **** TO10 = 0; 10409 .loc 1 575 9 view .LVU3360 575:Src/main.c **** TO10 = 0; 10410 .loc 1 575 13 is_stmt 0 view .LVU3361 10411 06ce 654B ldr r3, .L535 10412 06d0 D3ED047A vldr.32 s15, [r3, #16] 575:Src/main.c **** TO10 = 0; 10413 .loc 1 575 35 view .LVU3362 10414 06d4 93ED037A vldr.32 s14, [r3, #12] 575:Src/main.c **** TO10 = 0; 10415 .loc 1 575 28 view .LVU3363 10416 06d8 77EE877A vadd.f32 s15, s15, s14 10417 06dc C3ED047A vstr.32 s15, [r3, #16] 576:Src/main.c **** TIM10_coflag = 0; 10418 .loc 1 576 9 is_stmt 1 view .LVU3364 576:Src/main.c **** TIM10_coflag = 0; 10419 .loc 1 576 14 is_stmt 0 view .LVU3365 10420 06e0 0027 movs r7, #0 ARM GAS /tmp/ccYgfTud.s page 580 10421 06e2 6B4B ldr r3, .L535+44 10422 06e4 1F60 str r7, [r3] 577:Src/main.c **** 10423 .loc 1 577 9 is_stmt 1 view .LVU3366 577:Src/main.c **** 10424 .loc 1 577 22 is_stmt 0 view .LVU3367 10425 06e6 694B ldr r3, .L535+40 10426 06e8 1F70 strb r7, [r3] 579:Src/main.c **** HAL_GPIO_WritePin(GPIOG, GPIO_PIN_9, GPIO_PIN_RESET); 10427 .loc 1 579 9 is_stmt 1 view .LVU3368 10428 06ea DFF8C881 ldr r8, .L535+80 10429 06ee 0122 movs r2, #1 10430 06f0 4FF40071 mov r1, #512 10431 06f4 4046 mov r0, r8 10432 06f6 FFF7FEFF bl HAL_GPIO_WritePin 10433 .LVL866: 580:Src/main.c **** //* 10434 .loc 1 580 9 view .LVU3369 10435 06fa 3A46 mov r2, r7 10436 06fc 4FF40071 mov r1, #512 10437 0700 4046 mov r0, r8 10438 0702 FFF7FEFF bl HAL_GPIO_WritePin 10439 .LVL867: 582:Src/main.c **** OUT_trigger(trigger_counter); 10440 .loc 1 582 9 view .LVU3370 582:Src/main.c **** OUT_trigger(trigger_counter); 10441 .loc 1 582 41 is_stmt 0 view .LVU3371 10442 0706 B4FBF6F3 udiv r3, r4, r6 10443 070a 06FB1343 mls r3, r6, r3, r4 10444 070e 9BB2 uxth r3, r3 582:Src/main.c **** OUT_trigger(trigger_counter); 10445 .loc 1 582 12 view .LVU3372 10446 0710 1BB1 cbz r3, .L529 10447 .L493: 586:Src/main.c **** //*/ 10448 .loc 1 586 9 is_stmt 1 view .LVU3373 10449 0712 0134 adds r4, r4, #1 10450 .LVL868: 586:Src/main.c **** //*/ 10451 .loc 1 586 9 is_stmt 0 view .LVU3374 10452 0714 A4B2 uxth r4, r4 10453 .LVL869: 586:Src/main.c **** //*/ 10454 .loc 1 586 9 view .LVU3375 10455 0716 C4E7 b .L492 10456 .LVL870: 10457 .L490: 541:Src/main.c **** 10458 .loc 1 541 8 is_stmt 1 view .LVU3376 541:Src/main.c **** 10459 .loc 1 541 13 view .LVU3377 10460 0718 FEE7 b .L490 10461 .LVL871: 10462 .L529: 583:Src/main.c **** ++trigger_counter; 10463 .loc 1 583 10 view .LVU3378 10464 071a E8B2 uxtb r0, r5 ARM GAS /tmp/ccYgfTud.s page 581 10465 071c FFF7FEFF bl OUT_trigger 10466 .LVL872: 584:Src/main.c **** } 10467 .loc 1 584 10 view .LVU3379 10468 0720 0135 adds r5, r5, #1 10469 .LVL873: 584:Src/main.c **** } 10470 .loc 1 584 10 is_stmt 0 view .LVU3380 10471 0722 ADB2 uxth r5, r5 10472 .LVL874: 584:Src/main.c **** } 10473 .loc 1 584 10 view .LVU3381 10474 0724 F5E7 b .L493 10475 .L528: 611:Src/main.c **** //TIM11 -> CR1 |= 1 << 3; //sets timer to one-pulse mode. So it will turn off at the next Upd 10476 .loc 1 611 7 is_stmt 1 view .LVU3382 611:Src/main.c **** //TIM11 -> CR1 |= 1 << 3; //sets timer to one-pulse mode. So it will turn off at the next Upd 10477 .loc 1 611 13 is_stmt 0 view .LVU3383 10478 0726 574A ldr r2, .L535+32 10479 0728 D368 ldr r3, [r2, #12] 611:Src/main.c **** //TIM11 -> CR1 |= 1 << 3; //sets timer to one-pulse mode. So it will turn off at the next Upd 10480 .loc 1 611 21 view .LVU3384 10481 072a 43F00103 orr r3, r3, #1 10482 072e D360 str r3, [r2, #12] 621:Src/main.c **** 10483 .loc 1 621 7 is_stmt 1 view .LVU3385 10484 0730 FFF7FEFF bl Stop_TIM10 10485 .LVL875: 623:Src/main.c **** Set_LTEC(TT_CHANGE_CURR_1, task.current_param); 10486 .loc 1 623 7 view .LVU3386 623:Src/main.c **** Set_LTEC(TT_CHANGE_CURR_1, task.current_param); 10487 .loc 1 623 32 is_stmt 0 view .LVU3387 10488 0734 4B4C ldr r4, .L535 10489 .LVL876: 623:Src/main.c **** Set_LTEC(TT_CHANGE_CURR_1, task.current_param); 10490 .loc 1 623 32 view .LVU3388 10491 0736 D4ED017A vldr.32 s15, [r4, #4] 623:Src/main.c **** Set_LTEC(TT_CHANGE_CURR_1, task.current_param); 10492 .loc 1 623 26 view .LVU3389 10493 073a C4ED047A vstr.32 s15, [r4, #16] 624:Src/main.c **** if (task.tau > 3) 10494 .loc 1 624 7 is_stmt 1 view .LVU3390 10495 073e FCEEE77A vcvt.u32.f32 s15, s15 10496 0742 17EE903A vmov r3, s15 @ int 10497 0746 99B2 uxth r1, r3 10498 0748 0120 movs r0, #1 10499 074a FFF7FEFF bl Set_LTEC 10500 .LVL877: 625:Src/main.c **** { 10501 .loc 1 625 7 view .LVU3391 625:Src/main.c **** { 10502 .loc 1 625 15 is_stmt 0 view .LVU3392 10503 074e E38A ldrh r3, [r4, #22] 625:Src/main.c **** { 10504 .loc 1 625 10 view .LVU3393 10505 0750 032B cmp r3, #3 10506 0752 0CD9 bls .L495 ARM GAS /tmp/ccYgfTud.s page 582 627:Src/main.c **** htim10.Init.Period = 9999; 10507 .loc 1 627 8 is_stmt 1 view .LVU3394 627:Src/main.c **** htim10.Init.Period = 9999; 10508 .loc 1 627 34 is_stmt 0 view .LVU3395 10509 0754 4A4A ldr r2, .L535+28 10510 0756 D068 ldr r0, [r2, #12] 627:Src/main.c **** htim10.Init.Period = 9999; 10511 .loc 1 627 21 view .LVU3396 10512 0758 4E49 ldr r1, .L535+48 10513 075a 0860 str r0, [r1] 628:Src/main.c **** TO10_counter = (task.tau - 1) * 100; 10514 .loc 1 628 8 is_stmt 1 view .LVU3397 628:Src/main.c **** TO10_counter = (task.tau - 1) * 100; 10515 .loc 1 628 27 is_stmt 0 view .LVU3398 10516 075c 42F20F71 movw r1, #9999 10517 0760 D160 str r1, [r2, #12] 629:Src/main.c **** } 10518 .loc 1 629 8 is_stmt 1 view .LVU3399 629:Src/main.c **** } 10519 .loc 1 629 33 is_stmt 0 view .LVU3400 10520 0762 013B subs r3, r3, #1 629:Src/main.c **** } 10521 .loc 1 629 38 view .LVU3401 10522 0764 6422 movs r2, #100 10523 0766 02FB03F3 mul r3, r2, r3 629:Src/main.c **** } 10524 .loc 1 629 21 view .LVU3402 10525 076a 4B4A ldr r2, .L535+52 10526 076c 1360 str r3, [r2] 10527 .L495: 631:Src/main.c **** break; 10528 .loc 1 631 7 is_stmt 1 view .LVU3403 10529 076e 4448 ldr r0, .L535+28 10530 0770 FFF7FEFF bl HAL_TIM_Base_Start_IT 10531 .LVL878: 632:Src/main.c **** case TT_CHANGE_CURR_2: 10532 .loc 1 632 6 view .LVU3404 10533 0774 C9E6 b .L488 10534 .LVL879: 10535 .L487: 636:Src/main.c **** (void) MPhD_T(TT_CHANGE_TEMP_1); 10536 .loc 1 636 7 view .LVU3405 636:Src/main.c **** (void) MPhD_T(TT_CHANGE_TEMP_1); 10537 .loc 1 636 38 is_stmt 0 view .LVU3406 10538 0776 3B4B ldr r3, .L535 10539 0778 D3ED077A vldr.32 s15, [r3, #28] 636:Src/main.c **** (void) MPhD_T(TT_CHANGE_TEMP_1); 10540 .loc 1 636 7 view .LVU3407 10541 077c FCEEE77A vcvt.u32.f32 s15, s15 10542 0780 17EE903A vmov r3, s15 @ int 10543 0784 99B2 uxth r1, r3 10544 0786 0120 movs r0, #1 10545 0788 FFF7FEFF bl Set_LTEC 10546 .LVL880: 637:Src/main.c **** LD1_param.LD_CURR_TEMP = MPhD_T(TT_CHANGE_TEMP_1); 10547 .loc 1 637 7 is_stmt 1 view .LVU3408 637:Src/main.c **** LD1_param.LD_CURR_TEMP = MPhD_T(TT_CHANGE_TEMP_1); ARM GAS /tmp/ccYgfTud.s page 583 10548 .loc 1 637 14 is_stmt 0 view .LVU3409 10549 078c 0320 movs r0, #3 10550 078e FFF7FEFF bl MPhD_T 10551 .LVL881: 638:Src/main.c **** (void) MPhD_T(TT_CHANGE_TEMP_2); 10552 .loc 1 638 7 is_stmt 1 view .LVU3410 638:Src/main.c **** (void) MPhD_T(TT_CHANGE_TEMP_2); 10553 .loc 1 638 32 is_stmt 0 view .LVU3411 10554 0792 0320 movs r0, #3 10555 0794 FFF7FEFF bl MPhD_T 10556 .LVL882: 638:Src/main.c **** (void) MPhD_T(TT_CHANGE_TEMP_2); 10557 .loc 1 638 30 discriminator 1 view .LVU3412 10558 0798 334C ldr r4, .L535+4 10559 079a 2080 strh r0, [r4] @ movhi 639:Src/main.c **** LD2_param.LD_CURR_TEMP = MPhD_T(TT_CHANGE_TEMP_2); 10560 .loc 1 639 7 is_stmt 1 view .LVU3413 639:Src/main.c **** LD2_param.LD_CURR_TEMP = MPhD_T(TT_CHANGE_TEMP_2); 10561 .loc 1 639 14 is_stmt 0 view .LVU3414 10562 079c 0420 movs r0, #4 10563 079e FFF7FEFF bl MPhD_T 10564 .LVL883: 640:Src/main.c **** temp16=PID_Controller_Temp(&LD1_curr_setup, &LD1_param, 1); 10565 .loc 1 640 7 is_stmt 1 view .LVU3415 640:Src/main.c **** temp16=PID_Controller_Temp(&LD1_curr_setup, &LD1_param, 1); 10566 .loc 1 640 32 is_stmt 0 view .LVU3416 10567 07a2 0420 movs r0, #4 10568 07a4 FFF7FEFF bl MPhD_T 10569 .LVL884: 640:Src/main.c **** temp16=PID_Controller_Temp(&LD1_curr_setup, &LD1_param, 1); 10570 .loc 1 640 30 discriminator 1 view .LVU3417 10571 07a8 304D ldr r5, .L535+8 10572 07aa 2880 strh r0, [r5] @ movhi 641:Src/main.c **** Set_LTEC(TT_CHANGE_TEMP_1, temp16);//Drive Laser TEC 1 10573 .loc 1 641 7 is_stmt 1 view .LVU3418 641:Src/main.c **** Set_LTEC(TT_CHANGE_TEMP_1, temp16);//Drive Laser TEC 1 10574 .loc 1 641 14 is_stmt 0 view .LVU3419 10575 07ac 0122 movs r2, #1 10576 07ae 2146 mov r1, r4 10577 07b0 2F48 ldr r0, .L535+12 10578 07b2 FFF7FEFF bl PID_Controller_Temp 10579 .LVL885: 10580 07b6 0146 mov r1, r0 641:Src/main.c **** Set_LTEC(TT_CHANGE_TEMP_1, temp16);//Drive Laser TEC 1 10581 .loc 1 641 13 discriminator 1 view .LVU3420 10582 07b8 2E4C ldr r4, .L535+16 10583 07ba 2080 strh r0, [r4] @ movhi 642:Src/main.c **** temp16=PID_Controller_Temp(&LD2_curr_setup, &LD2_param, 2); 10584 .loc 1 642 7 is_stmt 1 view .LVU3421 10585 07bc 0320 movs r0, #3 10586 07be FFF7FEFF bl Set_LTEC 10587 .LVL886: 643:Src/main.c **** Set_LTEC(TT_CHANGE_TEMP_2, temp16);//Drive Laser TEC 2 10588 .loc 1 643 7 view .LVU3422 643:Src/main.c **** Set_LTEC(TT_CHANGE_TEMP_2, temp16);//Drive Laser TEC 2 10589 .loc 1 643 14 is_stmt 0 view .LVU3423 10590 07c2 0222 movs r2, #2 ARM GAS /tmp/ccYgfTud.s page 584 10591 07c4 2946 mov r1, r5 10592 07c6 2C48 ldr r0, .L535+20 10593 07c8 FFF7FEFF bl PID_Controller_Temp 10594 .LVL887: 10595 07cc 0146 mov r1, r0 643:Src/main.c **** Set_LTEC(TT_CHANGE_TEMP_2, temp16);//Drive Laser TEC 2 10596 .loc 1 643 13 discriminator 1 view .LVU3424 10597 07ce 2080 strh r0, [r4] @ movhi 644:Src/main.c **** 10598 .loc 1 644 7 is_stmt 1 view .LVU3425 10599 07d0 0420 movs r0, #4 10600 07d2 FFF7FEFF bl Set_LTEC 10601 .LVL888: 646:Src/main.c **** LD_blinker.state = 0; // 0 -- disabled (do nothing); 1 -- update LD current; 2 -- blinking, L 10602 .loc 1 646 7 view .LVU3426 646:Src/main.c **** LD_blinker.state = 0; // 0 -- disabled (do nothing); 1 -- update LD current; 2 -- blinking, L 10603 .loc 1 646 28 is_stmt 0 view .LVU3427 10604 07d6 314B ldr r3, .L535+56 10605 07d8 0222 movs r2, #2 10606 07da 1A70 strb r2, [r3] 647:Src/main.c **** //LD_blinker.param = task.current_param; 10607 .loc 1 647 7 is_stmt 1 view .LVU3428 647:Src/main.c **** //LD_blinker.param = task.current_param; 10608 .loc 1 647 24 is_stmt 0 view .LVU3429 10609 07dc 0022 movs r2, #0 10610 07de 9A72 strb r2, [r3, #10] 649:Src/main.c **** LD_blinker.param = 1000; // LD2 current (in unspecified units) 10611 .loc 1 649 7 is_stmt 1 view .LVU3430 649:Src/main.c **** LD_blinker.param = 1000; // LD2 current (in unspecified units) 10612 .loc 1 649 24 is_stmt 0 view .LVU3431 10613 07e0 1A81 strh r2, [r3, #8] @ movhi 650:Src/main.c **** LD_blinker.signal_port = OUT_9_GPIO_Port; 10614 .loc 1 650 7 is_stmt 1 view .LVU3432 650:Src/main.c **** LD_blinker.signal_port = OUT_9_GPIO_Port; 10615 .loc 1 650 24 is_stmt 0 view .LVU3433 10616 07e2 4FF47A72 mov r2, #1000 10617 07e6 1A81 strh r2, [r3, #8] @ movhi 651:Src/main.c **** LD_blinker.signal_pin = OUT_9_Pin; 10618 .loc 1 651 7 is_stmt 1 view .LVU3434 651:Src/main.c **** LD_blinker.signal_pin = OUT_9_Pin; 10619 .loc 1 651 30 is_stmt 0 view .LVU3435 10620 07e8 2D4A ldr r2, .L535+60 10621 07ea 5A60 str r2, [r3, #4] 652:Src/main.c **** 10622 .loc 1 652 7 is_stmt 1 view .LVU3436 652:Src/main.c **** 10623 .loc 1 652 29 is_stmt 0 view .LVU3437 10624 07ec 8022 movs r2, #128 10625 07ee 5A80 strh r2, [r3, #2] @ movhi 654:Src/main.c **** //When it is too low -- Desktop app crashes (there is not so much compute sources on MCU 10626 .loc 1 654 7 is_stmt 1 view .LVU3438 654:Src/main.c **** //When it is too low -- Desktop app crashes (there is not so much compute sources on MCU 10627 .loc 1 654 17 is_stmt 0 view .LVU3439 10628 07f0 2C4B ldr r3, .L535+64 10629 07f2 42F21072 movw r2, #10000 10630 07f6 DA62 str r2, [r3, #44] 656:Src/main.c **** if (st != HAL_OK) ARM GAS /tmp/ccYgfTud.s page 585 10631 .loc 1 656 7 is_stmt 1 view .LVU3440 656:Src/main.c **** if (st != HAL_OK) 10632 .loc 1 656 12 is_stmt 0 view .LVU3441 10633 07f8 2B48 ldr r0, .L535+68 10634 07fa FFF7FEFF bl HAL_TIM_Base_Start_IT 10635 .LVL889: 657:Src/main.c **** while(1); 10636 .loc 1 657 7 is_stmt 1 view .LVU3442 657:Src/main.c **** while(1); 10637 .loc 1 657 10 is_stmt 0 view .LVU3443 10638 07fe 78BB cbnz r0, .L497 662:Src/main.c **** uint32_t i = 10000; while (--i){} 10639 .loc 1 662 7 is_stmt 1 view .LVU3444 10640 0800 0122 movs r2, #1 10641 0802 8021 movs r1, #128 10642 0804 1D48 ldr r0, .L535+24 10643 .LVL890: 662:Src/main.c **** uint32_t i = 10000; while (--i){} 10644 .loc 1 662 7 is_stmt 0 view .LVU3445 10645 0806 FFF7FEFF bl HAL_GPIO_WritePin 10646 .LVL891: 663:Src/main.c **** HAL_GPIO_WritePin(GPIOD, GPIO_PIN_7, GPIO_PIN_RESET); 10647 .loc 1 663 7 is_stmt 1 view .LVU3446 663:Src/main.c **** HAL_GPIO_WritePin(GPIOD, GPIO_PIN_7, GPIO_PIN_RESET); 10648 .loc 1 663 27 view .LVU3447 663:Src/main.c **** HAL_GPIO_WritePin(GPIOD, GPIO_PIN_7, GPIO_PIN_RESET); 10649 .loc 1 663 16 is_stmt 0 view .LVU3448 10650 080a 42F21073 movw r3, #10000 10651 .LVL892: 10652 .L498: 663:Src/main.c **** HAL_GPIO_WritePin(GPIOD, GPIO_PIN_7, GPIO_PIN_RESET); 10653 .loc 1 663 39 is_stmt 1 discriminator 2 view .LVU3449 663:Src/main.c **** HAL_GPIO_WritePin(GPIOD, GPIO_PIN_7, GPIO_PIN_RESET); 10654 .loc 1 663 34 discriminator 2 view .LVU3450 663:Src/main.c **** HAL_GPIO_WritePin(GPIOD, GPIO_PIN_7, GPIO_PIN_RESET); 10655 .loc 1 663 34 is_stmt 0 discriminator 2 view .LVU3451 10656 080e 013B subs r3, r3, #1 10657 .LVL893: 663:Src/main.c **** HAL_GPIO_WritePin(GPIOD, GPIO_PIN_7, GPIO_PIN_RESET); 10658 .loc 1 663 34 discriminator 2 view .LVU3452 10659 0810 FDD1 bne .L498 664:Src/main.c **** LD_blinker.state = 2; 10660 .loc 1 664 7 is_stmt 1 view .LVU3453 10661 0812 0022 movs r2, #0 10662 0814 8021 movs r1, #128 10663 0816 1948 ldr r0, .L535+24 10664 0818 FFF7FEFF bl HAL_GPIO_WritePin 10665 .LVL894: 665:Src/main.c **** 10666 .loc 1 665 7 view .LVU3454 665:Src/main.c **** 10667 .loc 1 665 24 is_stmt 0 view .LVU3455 10668 081c 1F4B ldr r3, .L535+56 10669 081e 0222 movs r2, #2 10670 0820 9A72 strb r2, [r3, #10] 667:Src/main.c **** if (st != HAL_OK) 10671 .loc 1 667 7 is_stmt 1 view .LVU3456 ARM GAS /tmp/ccYgfTud.s page 586 667:Src/main.c **** if (st != HAL_OK) 10672 .loc 1 667 12 is_stmt 0 view .LVU3457 10673 0822 1748 ldr r0, .L535+28 10674 0824 FFF7FEFF bl HAL_TIM_Base_Start_IT 10675 .LVL895: 668:Src/main.c **** while(1); 10676 .loc 1 668 7 is_stmt 1 view .LVU3458 668:Src/main.c **** while(1); 10677 .loc 1 668 10 is_stmt 0 view .LVU3459 10678 0828 D8B9 cbnz r0, .L500 10679 .L501: 670:Src/main.c **** { 10680 .loc 1 670 33 is_stmt 1 view .LVU3460 670:Src/main.c **** { 10681 .loc 1 670 18 is_stmt 0 view .LVU3461 10682 082a 0E4B ldr r3, .L535 10683 082c D3ED047A vldr.32 s15, [r3, #16] 670:Src/main.c **** { 10684 .loc 1 670 39 view .LVU3462 10685 0830 93ED027A vldr.32 s14, [r3, #8] 670:Src/main.c **** { 10686 .loc 1 670 33 view .LVU3463 10687 0834 F4EEC77A vcmpe.f32 s15, s14 10688 0838 F1EE10FA vmrs APSR_nzcv, FPSCR 10689 083c 3CD5 bpl .L530 672:Src/main.c **** { 10690 .loc 1 672 8 is_stmt 1 view .LVU3464 672:Src/main.c **** { 10691 .loc 1 672 12 is_stmt 0 view .LVU3465 10692 083e 134B ldr r3, .L535+40 10693 0840 1B78 ldrb r3, [r3] @ zero_extendqisi2 672:Src/main.c **** { 10694 .loc 1 672 11 view .LVU3466 10695 0842 002B cmp r3, #0 10696 0844 F1D0 beq .L501 677:Src/main.c **** TO10 = 0; 10697 .loc 1 677 9 is_stmt 1 view .LVU3467 677:Src/main.c **** TO10 = 0; 10698 .loc 1 677 35 is_stmt 0 view .LVU3468 10699 0846 074B ldr r3, .L535 10700 0848 93ED037A vldr.32 s14, [r3, #12] 677:Src/main.c **** TO10 = 0; 10701 .loc 1 677 28 view .LVU3469 10702 084c 77EE277A vadd.f32 s15, s14, s15 10703 0850 C3ED047A vstr.32 s15, [r3, #16] 678:Src/main.c **** TIM10_coflag = 0; 10704 .loc 1 678 9 is_stmt 1 view .LVU3470 678:Src/main.c **** TIM10_coflag = 0; 10705 .loc 1 678 14 is_stmt 0 view .LVU3471 10706 0854 0023 movs r3, #0 10707 0856 0E4A ldr r2, .L535+44 10708 0858 1360 str r3, [r2] 679:Src/main.c **** 10709 .loc 1 679 9 is_stmt 1 view .LVU3472 679:Src/main.c **** 10710 .loc 1 679 22 is_stmt 0 view .LVU3473 10711 085a 0C4A ldr r2, .L535+40 ARM GAS /tmp/ccYgfTud.s page 587 10712 085c 1370 strb r3, [r2] 10713 085e E4E7 b .L501 10714 .LVL896: 10715 .L497: 658:Src/main.c **** // */ 10716 .loc 1 658 8 is_stmt 1 view .LVU3474 658:Src/main.c **** // */ 10717 .loc 1 658 13 view .LVU3475 10718 0860 FEE7 b .L497 10719 .LVL897: 10720 .L500: 669:Src/main.c **** while (task.current_param < task.max_param) 10721 .loc 1 669 8 view .LVU3476 669:Src/main.c **** while (task.current_param < task.max_param) 10722 .loc 1 669 13 view .LVU3477 10723 0862 FEE7 b .L500 10724 .L536: 10725 .align 2 10726 .L535: 10727 0864 00000000 .word task 10728 0868 00000000 .word LD1_param 10729 086c 00000000 .word LD2_param 10730 0870 00000000 .word LD1_curr_setup 10731 0874 00000000 .word temp16 10732 0878 00000000 .word LD2_curr_setup 10733 087c 000C0240 .word 1073875968 10734 0880 00000000 .word htim10 10735 0884 00480140 .word 1073825792 10736 0888 00080040 .word 1073743872 10737 088c 00000000 .word TIM10_coflag 10738 0890 00000000 .word TO10 10739 0894 00000000 .word TIM10_period 10740 0898 00000000 .word TO10_counter 10741 089c 00000000 .word LD_blinker 10742 08a0 00040240 .word 1073873920 10743 08a4 00040140 .word 1073808384 10744 08a8 00000000 .word htim8 10745 08ac 00000000 .word htim11 10746 08b0 00000000 .word htim4 10747 08b4 00180240 .word 1073879040 10748 .L530: 684:Src/main.c **** HAL_GPIO_WritePin(GPIOD, GPIO_PIN_7, GPIO_PIN_SET); 10749 .loc 1 684 7 view .LVU3478 10750 08b8 6C48 ldr r0, .L537 10751 .LVL898: 684:Src/main.c **** HAL_GPIO_WritePin(GPIOD, GPIO_PIN_7, GPIO_PIN_SET); 10752 .loc 1 684 7 is_stmt 0 view .LVU3479 10753 08ba FFF7FEFF bl HAL_TIM_Base_Stop 10754 .LVL899: 685:Src/main.c **** 10755 .loc 1 685 7 is_stmt 1 view .LVU3480 10756 08be 6C4C ldr r4, .L537+4 10757 08c0 0122 movs r2, #1 10758 08c2 8021 movs r1, #128 10759 08c4 2046 mov r0, r4 10760 08c6 FFF7FEFF bl HAL_GPIO_WritePin 10761 .LVL900: ARM GAS /tmp/ccYgfTud.s page 588 687:Src/main.c **** 10762 .loc 1 687 7 view .LVU3481 10763 08ca 0022 movs r2, #0 10764 08cc 8021 movs r1, #128 10765 08ce 2046 mov r0, r4 10766 08d0 FFF7FEFF bl HAL_GPIO_WritePin 10767 .LVL901: 689:Src/main.c **** TIM8->CNT = 0; 10768 .loc 1 689 7 view .LVU3482 10769 08d4 6748 ldr r0, .L537+8 10770 08d6 FFF7FEFF bl HAL_TIM_Base_Stop_IT 10771 .LVL902: 690:Src/main.c **** 10772 .loc 1 690 7 view .LVU3483 690:Src/main.c **** 10773 .loc 1 690 17 is_stmt 0 view .LVU3484 10774 08da 674B ldr r3, .L537+12 10775 08dc 0022 movs r2, #0 10776 08de 5A62 str r2, [r3, #36] 692:Src/main.c **** task.current_param = task.min_param; 10777 .loc 1 692 7 is_stmt 1 view .LVU3485 10778 08e0 FFF7FEFF bl Stop_TIM10 10779 .LVL903: 693:Src/main.c **** Set_LTEC(TT_CHANGE_CURR_2, task.current_param); 10780 .loc 1 693 7 view .LVU3486 693:Src/main.c **** Set_LTEC(TT_CHANGE_CURR_2, task.current_param); 10781 .loc 1 693 32 is_stmt 0 view .LVU3487 10782 08e4 654C ldr r4, .L537+16 10783 08e6 D4ED017A vldr.32 s15, [r4, #4] 693:Src/main.c **** Set_LTEC(TT_CHANGE_CURR_2, task.current_param); 10784 .loc 1 693 26 view .LVU3488 10785 08ea C4ED047A vstr.32 s15, [r4, #16] 694:Src/main.c **** if (task.tau > 3) 10786 .loc 1 694 7 is_stmt 1 view .LVU3489 10787 08ee FCEEE77A vcvt.u32.f32 s15, s15 10788 08f2 17EE903A vmov r3, s15 @ int 10789 08f6 99B2 uxth r1, r3 10790 08f8 0220 movs r0, #2 10791 08fa FFF7FEFF bl Set_LTEC 10792 .LVL904: 695:Src/main.c **** { 10793 .loc 1 695 7 view .LVU3490 695:Src/main.c **** { 10794 .loc 1 695 15 is_stmt 0 view .LVU3491 10795 08fe E38A ldrh r3, [r4, #22] 695:Src/main.c **** { 10796 .loc 1 695 10 view .LVU3492 10797 0900 032B cmp r3, #3 10798 0902 0CD9 bls .L503 697:Src/main.c **** htim10.Init.Period = 9999; 10799 .loc 1 697 8 is_stmt 1 view .LVU3493 697:Src/main.c **** htim10.Init.Period = 9999; 10800 .loc 1 697 34 is_stmt 0 view .LVU3494 10801 0904 594A ldr r2, .L537 10802 0906 D068 ldr r0, [r2, #12] 697:Src/main.c **** htim10.Init.Period = 9999; 10803 .loc 1 697 21 view .LVU3495 ARM GAS /tmp/ccYgfTud.s page 589 10804 0908 5D49 ldr r1, .L537+20 10805 090a 0860 str r0, [r1] 698:Src/main.c **** TO10_counter = (task.tau - 1) * 100; 10806 .loc 1 698 8 is_stmt 1 view .LVU3496 698:Src/main.c **** TO10_counter = (task.tau - 1) * 100; 10807 .loc 1 698 27 is_stmt 0 view .LVU3497 10808 090c 42F20F71 movw r1, #9999 10809 0910 D160 str r1, [r2, #12] 699:Src/main.c **** } 10810 .loc 1 699 8 is_stmt 1 view .LVU3498 699:Src/main.c **** } 10811 .loc 1 699 33 is_stmt 0 view .LVU3499 10812 0912 013B subs r3, r3, #1 699:Src/main.c **** } 10813 .loc 1 699 38 view .LVU3500 10814 0914 6422 movs r2, #100 10815 0916 02FB03F3 mul r3, r2, r3 699:Src/main.c **** } 10816 .loc 1 699 21 view .LVU3501 10817 091a 5A4A ldr r2, .L537+24 10818 091c 1360 str r3, [r2] 10819 .L503: 701:Src/main.c **** 10820 .loc 1 701 7 is_stmt 1 view .LVU3502 10821 091e 5348 ldr r0, .L537 10822 0920 FFF7FEFF bl HAL_TIM_Base_Start_IT 10823 .LVL905: 749:Src/main.c **** case TT_CHANGE_TEMP_1: 10824 .loc 1 749 6 view .LVU3503 10825 0924 F1E5 b .L488 10826 .LVL906: 10827 .L527: 749:Src/main.c **** case TT_CHANGE_TEMP_1: 10828 .loc 1 749 6 is_stmt 0 view .LVU3504 10829 .LBE651: 760:Src/main.c **** 10830 .loc 1 760 7 is_stmt 1 view .LVU3505 760:Src/main.c **** 10831 .loc 1 760 18 is_stmt 0 view .LVU3506 10832 0926 584A ldr r2, .L537+28 10833 0928 1360 str r3, [r2] 762:Src/main.c **** LD1_param.POWER = MPhD_T(1);//Get Data from monitor photodiode of LD1 10834 .loc 1 762 7 is_stmt 1 view .LVU3507 762:Src/main.c **** LD1_param.POWER = MPhD_T(1);//Get Data from monitor photodiode of LD1 10835 .loc 1 762 25 is_stmt 0 view .LVU3508 10836 092a 0120 movs r0, #1 10837 092c FFF7FEFF bl MPhD_T 10838 .LVL907: 762:Src/main.c **** LD1_param.POWER = MPhD_T(1);//Get Data from monitor photodiode of LD1 10839 .loc 1 762 23 discriminator 1 view .LVU3509 10840 0930 564E ldr r6, .L537+32 10841 0932 3081 strh r0, [r6, #8] @ movhi 763:Src/main.c **** LD2_param.POWER = MPhD_T(2);//Get Data from monitor photodiode of LD2 10842 .loc 1 763 7 is_stmt 1 view .LVU3510 763:Src/main.c **** LD2_param.POWER = MPhD_T(2);//Get Data from monitor photodiode of LD2 10843 .loc 1 763 25 is_stmt 0 view .LVU3511 10844 0934 0120 movs r0, #1 ARM GAS /tmp/ccYgfTud.s page 590 10845 0936 FFF7FEFF bl MPhD_T 10846 .LVL908: 763:Src/main.c **** LD2_param.POWER = MPhD_T(2);//Get Data from monitor photodiode of LD2 10847 .loc 1 763 23 discriminator 1 view .LVU3512 10848 093a 3081 strh r0, [r6, #8] @ movhi 764:Src/main.c **** LD2_param.POWER = MPhD_T(2);//Get Data from monitor photodiode of LD2 10849 .loc 1 764 7 is_stmt 1 view .LVU3513 764:Src/main.c **** LD2_param.POWER = MPhD_T(2);//Get Data from monitor photodiode of LD2 10850 .loc 1 764 25 is_stmt 0 view .LVU3514 10851 093c 0220 movs r0, #2 10852 093e FFF7FEFF bl MPhD_T 10853 .LVL909: 764:Src/main.c **** LD2_param.POWER = MPhD_T(2);//Get Data from monitor photodiode of LD2 10854 .loc 1 764 23 discriminator 1 view .LVU3515 10855 0942 534F ldr r7, .L537+36 10856 0944 3881 strh r0, [r7, #8] @ movhi 765:Src/main.c **** 10857 .loc 1 765 7 is_stmt 1 view .LVU3516 765:Src/main.c **** 10858 .loc 1 765 25 is_stmt 0 view .LVU3517 10859 0946 0220 movs r0, #2 10860 0948 FFF7FEFF bl MPhD_T 10861 .LVL910: 765:Src/main.c **** 10862 .loc 1 765 23 discriminator 1 view .LVU3518 10863 094c 3881 strh r0, [r7, #8] @ movhi 767:Src/main.c **** Long_Data[2] = LD2_param.POWER;//Translate Data from monitor photodiode of LD2 to Long_Data 10864 .loc 1 767 7 is_stmt 1 view .LVU3519 767:Src/main.c **** Long_Data[2] = LD2_param.POWER;//Translate Data from monitor photodiode of LD2 to Long_Data 10865 .loc 1 767 31 is_stmt 0 view .LVU3520 10866 094e 3389 ldrh r3, [r6, #8] 767:Src/main.c **** Long_Data[2] = LD2_param.POWER;//Translate Data from monitor photodiode of LD2 to Long_Data 10867 .loc 1 767 20 view .LVU3521 10868 0950 504C ldr r4, .L537+40 10869 0952 6380 strh r3, [r4, #2] @ movhi 768:Src/main.c **** 10870 .loc 1 768 7 is_stmt 1 view .LVU3522 768:Src/main.c **** 10871 .loc 1 768 20 is_stmt 0 view .LVU3523 10872 0954 A080 strh r0, [r4, #4] @ movhi 772:Src/main.c **** temp16 = Get_ADC(1); 10873 .loc 1 772 7 is_stmt 1 view .LVU3524 772:Src/main.c **** temp16 = Get_ADC(1); 10874 .loc 1 772 16 is_stmt 0 view .LVU3525 10875 0956 0020 movs r0, #0 10876 0958 FFF7FEFF bl Get_ADC 10877 .LVL911: 772:Src/main.c **** temp16 = Get_ADC(1); 10878 .loc 1 772 14 discriminator 1 view .LVU3526 10879 095c 4E4D ldr r5, .L537+44 10880 095e 2880 strh r0, [r5] @ movhi 773:Src/main.c **** Long_Data[7] = temp16; 10881 .loc 1 773 7 is_stmt 1 view .LVU3527 773:Src/main.c **** Long_Data[7] = temp16; 10882 .loc 1 773 16 is_stmt 0 view .LVU3528 10883 0960 0120 movs r0, #1 10884 0962 FFF7FEFF bl Get_ADC ARM GAS /tmp/ccYgfTud.s page 591 10885 .LVL912: 773:Src/main.c **** Long_Data[7] = temp16; 10886 .loc 1 773 14 discriminator 1 view .LVU3529 10887 0966 2880 strh r0, [r5] @ movhi 774:Src/main.c **** 10888 .loc 1 774 7 is_stmt 1 view .LVU3530 774:Src/main.c **** 10889 .loc 1 774 20 is_stmt 0 view .LVU3531 10890 0968 E081 strh r0, [r4, #14] @ movhi 777:Src/main.c **** Long_Data[8] = temp16; 10891 .loc 1 777 7 is_stmt 1 view .LVU3532 777:Src/main.c **** Long_Data[8] = temp16; 10892 .loc 1 777 16 is_stmt 0 view .LVU3533 10893 096a 0120 movs r0, #1 10894 096c FFF7FEFF bl Get_ADC 10895 .LVL913: 777:Src/main.c **** Long_Data[8] = temp16; 10896 .loc 1 777 14 discriminator 1 view .LVU3534 10897 0970 2880 strh r0, [r5] @ movhi 778:Src/main.c **** 10898 .loc 1 778 7 is_stmt 1 view .LVU3535 778:Src/main.c **** 10899 .loc 1 778 20 is_stmt 0 view .LVU3536 10900 0972 2082 strh r0, [r4, #16] @ movhi 781:Src/main.c **** Long_Data[9] = temp16; 10901 .loc 1 781 7 is_stmt 1 view .LVU3537 781:Src/main.c **** Long_Data[9] = temp16; 10902 .loc 1 781 16 is_stmt 0 view .LVU3538 10903 0974 0120 movs r0, #1 10904 0976 FFF7FEFF bl Get_ADC 10905 .LVL914: 781:Src/main.c **** Long_Data[9] = temp16; 10906 .loc 1 781 14 discriminator 1 view .LVU3539 10907 097a 2880 strh r0, [r5] @ movhi 782:Src/main.c **** 10908 .loc 1 782 7 is_stmt 1 view .LVU3540 782:Src/main.c **** 10909 .loc 1 782 20 is_stmt 0 view .LVU3541 10910 097c 6082 strh r0, [r4, #18] @ movhi 785:Src/main.c **** Long_Data[10] = temp16; 10911 .loc 1 785 7 is_stmt 1 view .LVU3542 785:Src/main.c **** Long_Data[10] = temp16; 10912 .loc 1 785 16 is_stmt 0 view .LVU3543 10913 097e 0120 movs r0, #1 10914 0980 FFF7FEFF bl Get_ADC 10915 .LVL915: 785:Src/main.c **** Long_Data[10] = temp16; 10916 .loc 1 785 14 discriminator 1 view .LVU3544 10917 0984 2880 strh r0, [r5] @ movhi 786:Src/main.c **** 10918 .loc 1 786 7 is_stmt 1 view .LVU3545 786:Src/main.c **** 10919 .loc 1 786 21 is_stmt 0 view .LVU3546 10920 0986 A082 strh r0, [r4, #20] @ movhi 789:Src/main.c **** Long_Data[11] = temp16; 10921 .loc 1 789 7 is_stmt 1 view .LVU3547 789:Src/main.c **** Long_Data[11] = temp16; ARM GAS /tmp/ccYgfTud.s page 592 10922 .loc 1 789 16 is_stmt 0 view .LVU3548 10923 0988 0120 movs r0, #1 10924 098a FFF7FEFF bl Get_ADC 10925 .LVL916: 789:Src/main.c **** Long_Data[11] = temp16; 10926 .loc 1 789 14 discriminator 1 view .LVU3549 10927 098e 2880 strh r0, [r5] @ movhi 790:Src/main.c **** temp16 = Get_ADC(2); 10928 .loc 1 790 7 is_stmt 1 view .LVU3550 790:Src/main.c **** temp16 = Get_ADC(2); 10929 .loc 1 790 21 is_stmt 0 view .LVU3551 10930 0990 E082 strh r0, [r4, #22] @ movhi 791:Src/main.c **** 10931 .loc 1 791 7 is_stmt 1 view .LVU3552 791:Src/main.c **** 10932 .loc 1 791 16 is_stmt 0 view .LVU3553 10933 0992 0220 movs r0, #2 10934 0994 FFF7FEFF bl Get_ADC 10935 .LVL917: 791:Src/main.c **** 10936 .loc 1 791 14 discriminator 1 view .LVU3554 10937 0998 2880 strh r0, [r5] @ movhi 794:Src/main.c **** temp16 = Get_ADC(4); 10938 .loc 1 794 7 is_stmt 1 view .LVU3555 794:Src/main.c **** temp16 = Get_ADC(4); 10939 .loc 1 794 16 is_stmt 0 view .LVU3556 10940 099a 0320 movs r0, #3 10941 099c FFF7FEFF bl Get_ADC 10942 .LVL918: 794:Src/main.c **** temp16 = Get_ADC(4); 10943 .loc 1 794 14 discriminator 1 view .LVU3557 10944 09a0 2880 strh r0, [r5] @ movhi 795:Src/main.c **** Long_Data[12] = temp16; 10945 .loc 1 795 7 is_stmt 1 view .LVU3558 795:Src/main.c **** Long_Data[12] = temp16; 10946 .loc 1 795 16 is_stmt 0 view .LVU3559 10947 09a2 0420 movs r0, #4 10948 09a4 FFF7FEFF bl Get_ADC 10949 .LVL919: 795:Src/main.c **** Long_Data[12] = temp16; 10950 .loc 1 795 14 discriminator 1 view .LVU3560 10951 09a8 2880 strh r0, [r5] @ movhi 796:Src/main.c **** temp16 = Get_ADC(5); 10952 .loc 1 796 7 is_stmt 1 view .LVU3561 796:Src/main.c **** temp16 = Get_ADC(5); 10953 .loc 1 796 21 is_stmt 0 view .LVU3562 10954 09aa 2083 strh r0, [r4, #24] @ movhi 797:Src/main.c **** 10955 .loc 1 797 7 is_stmt 1 view .LVU3563 797:Src/main.c **** 10956 .loc 1 797 16 is_stmt 0 view .LVU3564 10957 09ac 0520 movs r0, #5 10958 09ae FFF7FEFF bl Get_ADC 10959 .LVL920: 797:Src/main.c **** 10960 .loc 1 797 14 discriminator 1 view .LVU3565 10961 09b2 2880 strh r0, [r5] @ movhi ARM GAS /tmp/ccYgfTud.s page 593 800:Src/main.c **** Long_Data[3] = (TO6_stop)&0xffff; 10962 .loc 1 800 7 is_stmt 1 view .LVU3566 800:Src/main.c **** Long_Data[3] = (TO6_stop)&0xffff; 10963 .loc 1 800 16 is_stmt 0 view .LVU3567 10964 09b4 394B ldr r3, .L537+48 10965 09b6 1B68 ldr r3, [r3] 10966 09b8 394A ldr r2, .L537+52 10967 09ba 1360 str r3, [r2] 801:Src/main.c **** Long_Data[4] = (TO6_stop>>16)&0xffff; 10968 .loc 1 801 7 is_stmt 1 view .LVU3568 801:Src/main.c **** Long_Data[4] = (TO6_stop>>16)&0xffff; 10969 .loc 1 801 20 is_stmt 0 view .LVU3569 10970 09bc E380 strh r3, [r4, #6] @ movhi 802:Src/main.c **** 10971 .loc 1 802 7 is_stmt 1 view .LVU3570 802:Src/main.c **** 10972 .loc 1 802 31 is_stmt 0 view .LVU3571 10973 09be 1B0C lsrs r3, r3, #16 802:Src/main.c **** 10974 .loc 1 802 20 view .LVU3572 10975 09c0 2381 strh r3, [r4, #8] @ movhi 805:Src/main.c **** 10976 .loc 1 805 7 is_stmt 1 view .LVU3573 805:Src/main.c **** 10977 .loc 1 805 31 is_stmt 0 view .LVU3574 10978 09c2 3388 ldrh r3, [r6] 805:Src/main.c **** 10979 .loc 1 805 20 view .LVU3575 10980 09c4 6381 strh r3, [r4, #10] @ movhi 808:Src/main.c **** } 10981 .loc 1 808 7 is_stmt 1 view .LVU3576 808:Src/main.c **** } 10982 .loc 1 808 31 is_stmt 0 view .LVU3577 10983 09c6 3B88 ldrh r3, [r7] 808:Src/main.c **** } 10984 .loc 1 808 20 view .LVU3578 10985 09c8 A381 strh r3, [r4, #12] @ movhi 10986 09ca A5E5 b .L505 10987 .L507: 836:Src/main.c **** Long_Data[DL_16-1] = CS_result; 10988 .loc 1 836 5 is_stmt 1 view .LVU3579 836:Src/main.c **** Long_Data[DL_16-1] = CS_result; 10989 .loc 1 836 17 is_stmt 0 view .LVU3580 10990 09cc 354C ldr r4, .L537+56 10991 09ce 0D21 movs r1, #13 10992 09d0 2046 mov r0, r4 10993 09d2 FFF7FEFF bl CalculateChecksum 10994 .LVL921: 836:Src/main.c **** Long_Data[DL_16-1] = CS_result; 10995 .loc 1 836 15 discriminator 1 view .LVU3581 10996 09d6 344B ldr r3, .L537+60 10997 09d8 1880 strh r0, [r3] @ movhi 837:Src/main.c **** 10998 .loc 1 837 5 is_stmt 1 view .LVU3582 837:Src/main.c **** 10999 .loc 1 837 24 is_stmt 0 view .LVU3583 11000 09da 6083 strh r0, [r4, #26] @ movhi ARM GAS /tmp/ccYgfTud.s page 594 839:Src/main.c **** { 11001 .loc 1 839 5 is_stmt 1 view .LVU3584 11002 .LBB652: 839:Src/main.c **** { 11003 .loc 1 839 10 view .LVU3585 11004 .LVL922: 839:Src/main.c **** { 11005 .loc 1 839 19 is_stmt 0 view .LVU3586 11006 09dc 0023 movs r3, #0 839:Src/main.c **** { 11007 .loc 1 839 5 view .LVU3587 11008 09de 0BE0 b .L510 11009 .LVL923: 11010 .L511: 841:Src/main.c **** UART_DATA[i*2+1] = (Long_Data[i]>>8)&0xff; 11011 .loc 1 841 6 is_stmt 1 view .LVU3588 841:Src/main.c **** UART_DATA[i*2+1] = (Long_Data[i]>>8)&0xff; 11012 .loc 1 841 33 is_stmt 0 view .LVU3589 11013 09e0 2C4A ldr r2, .L537+40 11014 09e2 32F81320 ldrh r2, [r2, r3, lsl #1] 841:Src/main.c **** UART_DATA[i*2+1] = (Long_Data[i]>>8)&0xff; 11015 .loc 1 841 17 view .LVU3590 11016 09e6 5900 lsls r1, r3, #1 841:Src/main.c **** UART_DATA[i*2+1] = (Long_Data[i]>>8)&0xff; 11017 .loc 1 841 21 view .LVU3591 11018 09e8 3048 ldr r0, .L537+64 11019 09ea 00F81320 strb r2, [r0, r3, lsl #1] 842:Src/main.c **** } 11020 .loc 1 842 6 is_stmt 1 view .LVU3592 842:Src/main.c **** } 11021 .loc 1 842 19 is_stmt 0 view .LVU3593 11022 09ee 0131 adds r1, r1, #1 842:Src/main.c **** } 11023 .loc 1 842 23 view .LVU3594 11024 09f0 120A lsrs r2, r2, #8 11025 09f2 4254 strb r2, [r0, r1] 839:Src/main.c **** { 11026 .loc 1 839 38 is_stmt 1 discriminator 3 view .LVU3595 11027 09f4 0133 adds r3, r3, #1 11028 .LVL924: 839:Src/main.c **** { 11029 .loc 1 839 38 is_stmt 0 discriminator 3 view .LVU3596 11030 09f6 9BB2 uxth r3, r3 11031 .LVL925: 11032 .L510: 839:Src/main.c **** { 11033 .loc 1 839 28 is_stmt 1 discriminator 1 view .LVU3597 11034 09f8 0E2B cmp r3, #14 11035 09fa F1D9 bls .L511 11036 .LBE652: 849:Src/main.c **** UART_transmission_request = NO_MESS; 11037 .loc 1 849 5 view .LVU3598 11038 09fc 1E20 movs r0, #30 11039 09fe FFF7FEFF bl USART_TX_DMA 11040 .LVL926: 850:Src/main.c **** break; 11041 .loc 1 850 5 view .LVU3599 ARM GAS /tmp/ccYgfTud.s page 595 850:Src/main.c **** break; 11042 .loc 1 850 31 is_stmt 0 view .LVU3600 11043 0a02 2B4B ldr r3, .L537+68 11044 0a04 0022 movs r2, #0 11045 0a06 1A70 strb r2, [r3] 851:Src/main.c **** case MESS_03://Transmith saved packet 11046 .loc 1 851 4 is_stmt 1 view .LVU3601 11047 0a08 FFF787BB b .L509 11048 .LVL927: 11049 .L512: 11050 .LBB653: 855:Src/main.c **** UART_DATA[i*2+1] = (Long_Data[i]>>8)&0xff; 11051 .loc 1 855 6 view .LVU3602 855:Src/main.c **** UART_DATA[i*2+1] = (Long_Data[i]>>8)&0xff; 11052 .loc 1 855 33 is_stmt 0 view .LVU3603 11053 0a0c 214A ldr r2, .L537+40 11054 0a0e 32F81320 ldrh r2, [r2, r3, lsl #1] 855:Src/main.c **** UART_DATA[i*2+1] = (Long_Data[i]>>8)&0xff; 11055 .loc 1 855 17 view .LVU3604 11056 0a12 5900 lsls r1, r3, #1 855:Src/main.c **** UART_DATA[i*2+1] = (Long_Data[i]>>8)&0xff; 11057 .loc 1 855 21 view .LVU3605 11058 0a14 2548 ldr r0, .L537+64 11059 0a16 00F81320 strb r2, [r0, r3, lsl #1] 856:Src/main.c **** } 11060 .loc 1 856 6 is_stmt 1 view .LVU3606 856:Src/main.c **** } 11061 .loc 1 856 19 is_stmt 0 view .LVU3607 11062 0a1a 0131 adds r1, r1, #1 856:Src/main.c **** } 11063 .loc 1 856 23 view .LVU3608 11064 0a1c 120A lsrs r2, r2, #8 11065 0a1e 4254 strb r2, [r0, r1] 853:Src/main.c **** { 11066 .loc 1 853 38 is_stmt 1 discriminator 3 view .LVU3609 11067 0a20 0133 adds r3, r3, #1 11068 .LVL928: 853:Src/main.c **** { 11069 .loc 1 853 38 is_stmt 0 discriminator 3 view .LVU3610 11070 0a22 9BB2 uxth r3, r3 11071 .LVL929: 11072 .L508: 853:Src/main.c **** { 11073 .loc 1 853 28 is_stmt 1 discriminator 1 view .LVU3611 11074 0a24 0E2B cmp r3, #14 11075 0a26 F1D9 bls .L512 11076 .LBE653: 862:Src/main.c **** UART_transmission_request = NO_MESS; 11077 .loc 1 862 5 view .LVU3612 11078 0a28 1E20 movs r0, #30 11079 0a2a FFF7FEFF bl USART_TX_DMA 11080 .LVL930: 863:Src/main.c **** break; 11081 .loc 1 863 5 view .LVU3613 863:Src/main.c **** break; 11082 .loc 1 863 31 is_stmt 0 view .LVU3614 11083 0a2e 204B ldr r3, .L537+68 ARM GAS /tmp/ccYgfTud.s page 596 11084 0a30 0022 movs r2, #0 11085 0a32 1A70 strb r2, [r3] 864:Src/main.c **** } 11086 .loc 1 864 4 is_stmt 1 view .LVU3615 11087 0a34 FFF771BB b .L509 11088 .LVL931: 11089 .L518: 824:Src/main.c **** { 11090 .loc 1 824 3 is_stmt 0 view .LVU3616 11091 0a38 0023 movs r3, #0 11092 0a3a F3E7 b .L508 11093 .L521: 866:Src/main.c **** { 11094 .loc 1 866 28 discriminator 1 view .LVU3617 11095 0a3c 174B ldr r3, .L537+48 11096 0a3e 1B68 ldr r3, [r3] 11097 0a40 1C4A ldr r2, .L537+72 11098 0a42 1268 ldr r2, [r2] 11099 0a44 9B1A subs r3, r3, r2 866:Src/main.c **** { 11100 .loc 1 866 21 discriminator 1 view .LVU3618 11101 0a46 642B cmp r3, #100 11102 0a48 7FF66CAB bls .L456 868:Src/main.c **** State_Data[0] |= UART_ERR;//timeout error! 11103 .loc 1 868 4 is_stmt 1 view .LVU3619 868:Src/main.c **** State_Data[0] |= UART_ERR;//timeout error! 11104 .loc 1 868 18 is_stmt 0 view .LVU3620 11105 0a4c 0022 movs r2, #0 11106 0a4e 1A4B ldr r3, .L537+76 11107 0a50 1A80 strh r2, [r3] @ movhi 869:Src/main.c **** UART_transmission_request = MESS_01;//Send status 11108 .loc 1 869 4 is_stmt 1 view .LVU3621 869:Src/main.c **** UART_transmission_request = MESS_01;//Send status 11109 .loc 1 869 14 is_stmt 0 view .LVU3622 11110 0a52 1A49 ldr r1, .L537+80 11111 0a54 0B78 ldrb r3, [r1] @ zero_extendqisi2 869:Src/main.c **** UART_transmission_request = MESS_01;//Send status 11112 .loc 1 869 18 view .LVU3623 11113 0a56 43F00203 orr r3, r3, #2 11114 0a5a 0B70 strb r3, [r1] 870:Src/main.c **** flg_tmt = 0;//Reset timeout flag 11115 .loc 1 870 4 is_stmt 1 view .LVU3624 870:Src/main.c **** flg_tmt = 0;//Reset timeout flag 11116 .loc 1 870 30 is_stmt 0 view .LVU3625 11117 0a5c 144B ldr r3, .L537+68 11118 0a5e 0121 movs r1, #1 11119 0a60 1970 strb r1, [r3] 871:Src/main.c **** } 11120 .loc 1 871 4 is_stmt 1 view .LVU3626 871:Src/main.c **** } 11121 .loc 1 871 12 is_stmt 0 view .LVU3627 11122 0a62 174B ldr r3, .L537+84 11123 0a64 1A70 strb r2, [r3] 11124 0a66 FFF75DBB b .L456 11125 .L538: 11126 0a6a 00BF .align 2 11127 .L537: ARM GAS /tmp/ccYgfTud.s page 597 11128 0a6c 00000000 .word htim10 11129 0a70 000C0240 .word 1073875968 11130 0a74 00000000 .word htim8 11131 0a78 00040140 .word 1073808384 11132 0a7c 00000000 .word task 11133 0a80 00000000 .word TIM10_period 11134 0a84 00000000 .word TO10_counter 11135 0a88 00000000 .word TO7_before 11136 0a8c 00000000 .word LD1_param 11137 0a90 00000000 .word LD2_param 11138 0a94 00000000 .word Long_Data 11139 0a98 00000000 .word temp16 11140 0a9c 00000000 .word TO6 11141 0aa0 00000000 .word TO6_stop 11142 0aa4 02000000 .word Long_Data+2 11143 0aa8 00000000 .word CS_result 11144 0aac 00000000 .word UART_DATA 11145 0ab0 00000000 .word UART_transmission_request 11146 0ab4 00000000 .word TO6_uart 11147 0ab8 00000000 .word UART_rec_incr 11148 0abc 00000000 .word State_Data 11149 0ac0 00000000 .word flg_tmt 11150 .cfi_endproc 11151 .LFE1186: 11153 .section .rodata.ad9102_example4_regval,"a" 11154 .align 2 11157 ad9102_example4_regval: 11158 0000 0000 .short 0 11159 0002 0000 .short 0 11160 0004 0000 .short 0 11161 0006 0000 .short 0 11162 0008 0000 .short 0 11163 000a 0000 .short 0 11164 000c 0000 .short 0 11165 000e 0040 .short 16384 11166 0010 0000 .short 0 11167 0012 0000 .short 0 11168 0014 0000 .short 0 11169 0016 0000 .short 0 11170 0018 001F .short 7936 11171 001a 0000 .short 0 11172 001c 0000 .short 0 11173 001e 0000 .short 0 11174 0020 0E00 .short 14 11175 0022 0000 .short 0 11176 0024 0000 .short 0 11177 0026 0000 .short 0 11178 0028 0000 .short 0 11179 002a 0000 .short 0 11180 002c 1232 .short 12818 11181 002e 2101 .short 289 11182 0030 FFFF .short -1 11183 0032 0000 .short 0 11184 0034 0101 .short 257 11185 0036 0300 .short 3 11186 0038 0000 .short 0 11187 003a 0000 .short 0 ARM GAS /tmp/ccYgfTud.s page 598 11188 003c 0000 .short 0 11189 003e 0000 .short 0 11190 0040 0000 .short 0 11191 0042 0000 .short 0 11192 0044 0000 .short 0 11193 0046 0000 .short 0 11194 0048 0040 .short 16384 11195 004a 0000 .short 0 11196 004c 0606 .short 1542 11197 004e 9919 .short 6553 11198 0050 009A .short -26112 11199 0052 0000 .short 0 11200 0054 0000 .short 0 11201 0056 0000 .short 0 11202 0058 0000 .short 0 11203 005a 0000 .short 0 11204 005c 0000 .short 0 11205 005e 0000 .short 0 11206 0060 A00F .short 4000 11207 0062 0000 .short 0 11208 0064 0000 .short 0 11209 0066 0000 .short 0 11210 0068 0000 .short 0 11211 006a 0000 .short 0 11212 006c 0000 .short 0 11213 006e 0000 .short 0 11214 0070 0000 .short 0 11215 0072 0000 .short 0 11216 0074 0000 .short 0 11217 0076 0000 .short 0 11218 0078 0000 .short 0 11219 007a 0000 .short 0 11220 007c 0000 .short 0 11221 007e FF16 .short 5887 11222 0080 0100 .short 1 11223 0082 0100 .short 1 11224 .section .rodata.ad9102_reg_addr,"a" 11225 .align 2 11228 ad9102_reg_addr: 11229 0000 0000 .short 0 11230 0002 0100 .short 1 11231 0004 0200 .short 2 11232 0006 0300 .short 3 11233 0008 0400 .short 4 11234 000a 0500 .short 5 11235 000c 0600 .short 6 11236 000e 0700 .short 7 11237 0010 0800 .short 8 11238 0012 0900 .short 9 11239 0014 0A00 .short 10 11240 0016 0B00 .short 11 11241 0018 0C00 .short 12 11242 001a 0D00 .short 13 11243 001c 0E00 .short 14 11244 001e 1F00 .short 31 11245 0020 2000 .short 32 11246 0022 2200 .short 34 ARM GAS /tmp/ccYgfTud.s page 599 11247 0024 2300 .short 35 11248 0026 2400 .short 36 11249 0028 2500 .short 37 11250 002a 2600 .short 38 11251 002c 2700 .short 39 11252 002e 2800 .short 40 11253 0030 2900 .short 41 11254 0032 2A00 .short 42 11255 0034 2B00 .short 43 11256 0036 2C00 .short 44 11257 0038 2D00 .short 45 11258 003a 2E00 .short 46 11259 003c 2F00 .short 47 11260 003e 3000 .short 48 11261 0040 3100 .short 49 11262 0042 3200 .short 50 11263 0044 3300 .short 51 11264 0046 3400 .short 52 11265 0048 3500 .short 53 11266 004a 3600 .short 54 11267 004c 3700 .short 55 11268 004e 3E00 .short 62 11269 0050 3F00 .short 63 11270 0052 4000 .short 64 11271 0054 4100 .short 65 11272 0056 4200 .short 66 11273 0058 4300 .short 67 11274 005a 4400 .short 68 11275 005c 4500 .short 69 11276 005e 4700 .short 71 11277 0060 5000 .short 80 11278 0062 5100 .short 81 11279 0064 5200 .short 82 11280 0066 5300 .short 83 11281 0068 5400 .short 84 11282 006a 5500 .short 85 11283 006c 5600 .short 86 11284 006e 5700 .short 87 11285 0070 5800 .short 88 11286 0072 5900 .short 89 11287 0074 5A00 .short 90 11288 0076 5B00 .short 91 11289 0078 5C00 .short 92 11290 007a 5D00 .short 93 11291 007c 5E00 .short 94 11292 007e 5F00 .short 95 11293 0080 1E00 .short 30 11294 0082 1D00 .short 29 11295 .global task 11296 .section .bss.task,"aw",%nobits 11297 .align 2 11300 task: 11301 0000 00000000 .space 52 11301 00000000 11301 00000000 11301 00000000 11301 00000000 ARM GAS /tmp/ccYgfTud.s page 600 11302 .global LD_blinker 11303 .section .bss.LD_blinker,"aw",%nobits 11304 .align 2 11307 LD_blinker: 11308 0000 00000000 .space 12 11308 00000000 11308 00000000 11309 .global LD2_param 11310 .section .bss.LD2_param,"aw",%nobits 11311 .align 2 11314 LD2_param: 11315 0000 00000000 .space 12 11315 00000000 11315 00000000 11316 .global LD1_param 11317 .section .bss.LD1_param,"aw",%nobits 11318 .align 2 11321 LD1_param: 11322 0000 00000000 .space 12 11322 00000000 11322 00000000 11323 .global Def_setup 11324 .section .bss.Def_setup,"aw",%nobits 11325 .align 2 11328 Def_setup: 11329 0000 00000000 .space 18 11329 00000000 11329 00000000 11329 00000000 11329 0000 11330 .global Curr_setup 11331 .section .bss.Curr_setup,"aw",%nobits 11332 .align 2 11335 Curr_setup: 11336 0000 00000000 .space 18 11336 00000000 11336 00000000 11336 00000000 11336 0000 11337 .global LD2_def_setup 11338 .section .bss.LD2_def_setup,"aw",%nobits 11339 .align 2 11342 LD2_def_setup: 11343 0000 00000000 .space 16 11343 00000000 11343 00000000 11343 00000000 11344 .global LD1_def_setup 11345 .section .bss.LD1_def_setup,"aw",%nobits 11346 .align 2 11349 LD1_def_setup: 11350 0000 00000000 .space 16 11350 00000000 11350 00000000 11350 00000000 11351 .global LD2_curr_setup 11352 .section .bss.LD2_curr_setup,"aw",%nobits ARM GAS /tmp/ccYgfTud.s page 601 11353 .align 2 11356 LD2_curr_setup: 11357 0000 00000000 .space 16 11357 00000000 11357 00000000 11357 00000000 11358 .global LD1_curr_setup 11359 .section .bss.LD1_curr_setup,"aw",%nobits 11360 .align 2 11363 LD1_curr_setup: 11364 0000 00000000 .space 16 11364 00000000 11364 00000000 11364 00000000 11365 .global sizeoffile 11366 .section .bss.sizeoffile,"aw",%nobits 11367 .align 2 11370 sizeoffile: 11371 0000 00000000 .space 4 11372 .global fgoto 11373 .section .bss.fgoto,"aw",%nobits 11374 .align 2 11377 fgoto: 11378 0000 00000000 .space 4 11379 .global test 11380 .section .bss.test,"aw",%nobits 11381 .align 2 11384 test: 11385 0000 00000000 .space 4 11386 .global fresult 11387 .section .bss.fresult,"aw",%nobits 11390 fresult: 11391 0000 00 .space 1 11392 .global COMMAND 11393 .section .bss.COMMAND,"aw",%nobits 11394 .align 2 11397 COMMAND: 11398 0000 00000000 .space 30 11398 00000000 11398 00000000 11398 00000000 11398 00000000 11399 .global Long_Data 11400 .section .bss.Long_Data,"aw",%nobits 11401 .align 2 11404 Long_Data: 11405 0000 00000000 .space 30 11405 00000000 11405 00000000 11405 00000000 11405 00000000 11406 .global temp16 11407 .section .bss.temp16,"aw",%nobits 11408 .align 1 11411 temp16: 11412 0000 0000 .space 2 11413 .global CS_result ARM GAS /tmp/ccYgfTud.s page 602 11414 .section .bss.CS_result,"aw",%nobits 11415 .align 1 11418 CS_result: 11419 0000 0000 .space 2 11420 .global UART_header 11421 .section .bss.UART_header,"aw",%nobits 11422 .align 1 11425 UART_header: 11426 0000 0000 .space 2 11427 .global UART_rec_incr 11428 .section .bss.UART_rec_incr,"aw",%nobits 11429 .align 1 11432 UART_rec_incr: 11433 0000 0000 .space 2 11434 .global TIM10_coflag 11435 .section .bss.TIM10_coflag,"aw",%nobits 11438 TIM10_coflag: 11439 0000 00 .space 1 11440 .global u_rx_flg 11441 .section .bss.u_rx_flg,"aw",%nobits 11444 u_rx_flg: 11445 0000 00 .space 1 11446 .global u_tx_flg 11447 .section .bss.u_tx_flg,"aw",%nobits 11450 u_tx_flg: 11451 0000 00 .space 1 11452 .global flg_tmt 11453 .section .bss.flg_tmt,"aw",%nobits 11456 flg_tmt: 11457 0000 00 .space 1 11458 .global UART_DATA 11459 .section .bss.UART_DATA,"aw",%nobits 11460 .align 2 11463 UART_DATA: 11464 0000 00000000 .space 30 11464 00000000 11464 00000000 11464 00000000 11464 00000000 11465 .global State_Data 11466 .section .bss.State_Data,"aw",%nobits 11467 .align 2 11470 State_Data: 11471 0000 0000 .space 2 11472 .global UART_transmission_request 11473 .section .bss.UART_transmission_request,"aw",%nobits 11476 UART_transmission_request: 11477 0000 00 .space 1 11478 .global CPU_state_old 11479 .section .bss.CPU_state_old,"aw",%nobits 11482 CPU_state_old: 11483 0000 00 .space 1 11484 .global CPU_state 11485 .section .bss.CPU_state,"aw",%nobits 11488 CPU_state: 11489 0000 00 .space 1 11490 .global uart_buf ARM GAS /tmp/ccYgfTud.s page 603 11491 .section .bss.uart_buf,"aw",%nobits 11494 uart_buf: 11495 0000 00 .space 1 11496 .global TIM10_period 11497 .section .bss.TIM10_period,"aw",%nobits 11498 .align 2 11501 TIM10_period: 11502 0000 00000000 .space 4 11503 .global TO10_counter 11504 .section .bss.TO10_counter,"aw",%nobits 11505 .align 2 11508 TO10_counter: 11509 0000 00000000 .space 4 11510 .global TO10 11511 .section .bss.TO10,"aw",%nobits 11512 .align 2 11515 TO10: 11516 0000 00000000 .space 4 11517 .global TO7_PID 11518 .section .bss.TO7_PID,"aw",%nobits 11519 .align 2 11522 TO7_PID: 11523 0000 00000000 .space 4 11524 .global TO7_before 11525 .section .bss.TO7_before,"aw",%nobits 11526 .align 2 11529 TO7_before: 11530 0000 00000000 .space 4 11531 .global TO7 11532 .section .bss.TO7,"aw",%nobits 11533 .align 2 11536 TO7: 11537 0000 00000000 .space 4 11538 .global temp32 11539 .section .bss.temp32,"aw",%nobits 11540 .align 2 11543 temp32: 11544 0000 00000000 .space 4 11545 .global SD_SLIDE 11546 .section .bss.SD_SLIDE,"aw",%nobits 11547 .align 2 11550 SD_SLIDE: 11551 0000 00000000 .space 4 11552 .global SD_SEEK 11553 .section .bss.SD_SEEK,"aw",%nobits 11554 .align 2 11557 SD_SEEK: 11558 0000 00000000 .space 4 11559 .global TO6_uart 11560 .section .bss.TO6_uart,"aw",%nobits 11561 .align 2 11564 TO6_uart: 11565 0000 00000000 .space 4 11566 .global TO6_stop 11567 .section .bss.TO6_stop,"aw",%nobits 11568 .align 2 11571 TO6_stop: ARM GAS /tmp/ccYgfTud.s page 604 11572 0000 00000000 .space 4 11573 .global TO6_before 11574 .section .bss.TO6_before,"aw",%nobits 11575 .align 2 11578 TO6_before: 11579 0000 00000000 .space 4 11580 .global TO6 11581 .section .bss.TO6,"aw",%nobits 11582 .align 2 11585 TO6: 11586 0000 00000000 .space 4 11587 .global huart8 11588 .section .bss.huart8,"aw",%nobits 11589 .align 2 11592 huart8: 11593 0000 00000000 .space 136 11593 00000000 11593 00000000 11593 00000000 11593 00000000 11594 .global htim11 11595 .section .bss.htim11,"aw",%nobits 11596 .align 2 11599 htim11: 11600 0000 00000000 .space 76 11600 00000000 11600 00000000 11600 00000000 11600 00000000 11601 .global htim10 11602 .section .bss.htim10,"aw",%nobits 11603 .align 2 11606 htim10: 11607 0000 00000000 .space 76 11607 00000000 11607 00000000 11607 00000000 11607 00000000 11608 .global htim8 11609 .section .bss.htim8,"aw",%nobits 11610 .align 2 11613 htim8: 11614 0000 00000000 .space 76 11614 00000000 11614 00000000 11614 00000000 11614 00000000 11615 .global htim4 11616 .section .bss.htim4,"aw",%nobits 11617 .align 2 11620 htim4: 11621 0000 00000000 .space 76 11621 00000000 11621 00000000 11621 00000000 11621 00000000 11622 .global hsd1 ARM GAS /tmp/ccYgfTud.s page 605 11623 .section .bss.hsd1,"aw",%nobits 11624 .align 2 11627 hsd1: 11628 0000 00000000 .space 132 11628 00000000 11628 00000000 11628 00000000 11628 00000000 11629 .global hadc3 11630 .section .bss.hadc3,"aw",%nobits 11631 .align 2 11634 hadc3: 11635 0000 00000000 .space 72 11635 00000000 11635 00000000 11635 00000000 11635 00000000 11636 .global hadc1 11637 .section .bss.hadc1,"aw",%nobits 11638 .align 2 11641 hadc1: 11642 0000 00000000 .space 72 11642 00000000 11642 00000000 11642 00000000 11642 00000000 11643 .text 11644 .Letext0: 11645 .file 9 "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h" 11646 .file 10 "/usr/lib/gcc/arm-none-eabi/13.2.1/include/stdint.h" 11647 .file 11 "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h" 11648 .file 12 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h" 11649 .file 13 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h" 11650 .file 14 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h" 11651 .file 15 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h" 11652 .file 16 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h" 11653 .file 17 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h" 11654 .file 18 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_sdmmc.h" 11655 .file 19 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sd.h" 11656 .file 20 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h" 11657 .file 21 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h" 11658 .file 22 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h" 11659 .file 23 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h" 11660 .file 24 "Inc/main.h" 11661 .file 25 "Middlewares/Third_Party/FatFs/src/ff.h" 11662 .file 26 "Inc/File_Handling.h" 11663 .file 27 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h" 11664 .file 28 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h" 11665 .file 29 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h" 11666 .file 30 "Inc/fatfs.h" 11667 .file 31 "" ARM GAS /tmp/ccYgfTud.s page 606 DEFINED SYMBOLS *ABS*:00000000 main.c /tmp/ccYgfTud.s:20 .text.NVIC_EncodePriority:00000000 $t /tmp/ccYgfTud.s:25 .text.NVIC_EncodePriority:00000000 NVIC_EncodePriority /tmp/ccYgfTud.s:88 .text.MX_SDMMC1_SD_Init:00000000 $t /tmp/ccYgfTud.s:93 .text.MX_SDMMC1_SD_Init:00000000 MX_SDMMC1_SD_Init /tmp/ccYgfTud.s:131 .text.MX_SDMMC1_SD_Init:0000001c $d /tmp/ccYgfTud.s:11627 .bss.hsd1:00000000 hsd1 /tmp/ccYgfTud.s:137 .text.MX_DMA_Init:00000000 $t /tmp/ccYgfTud.s:142 .text.MX_DMA_Init:00000000 MX_DMA_Init /tmp/ccYgfTud.s:238 .text.MX_DMA_Init:0000003c $d /tmp/ccYgfTud.s:245 .text.Decode_task:00000000 $t /tmp/ccYgfTud.s:250 .text.Decode_task:00000000 Decode_task /tmp/ccYgfTud.s:527 .text.Decode_task:00000150 $d /tmp/ccYgfTud.s:11300 .bss.task:00000000 task /tmp/ccYgfTud.s:11508 .bss.TO10_counter:00000000 TO10_counter /tmp/ccYgfTud.s:537 .text.PID_Controller_Temp:00000000 $t /tmp/ccYgfTud.s:542 .text.PID_Controller_Temp:00000000 PID_Controller_Temp /tmp/ccYgfTud.s:711 .text.PID_Controller_Temp:000000cc $d /tmp/ccYgfTud.s:11536 .bss.TO7:00000000 TO7 /tmp/ccYgfTud.s:11522 .bss.TO7_PID:00000000 TO7_PID /tmp/ccYgfTud.s:721 .text.AD9102_WriteReg:00000000 $t /tmp/ccYgfTud.s:726 .text.AD9102_WriteReg:00000000 AD9102_WriteReg /tmp/ccYgfTud.s:973 .text.AD9102_WriteReg:000000a8 $d /tmp/ccYgfTud.s:979 .text.AD9102_WriteRegTable:00000000 $t /tmp/ccYgfTud.s:984 .text.AD9102_WriteRegTable:00000000 AD9102_WriteRegTable /tmp/ccYgfTud.s:1035 .text.AD9102_WriteRegTable:00000024 $d /tmp/ccYgfTud.s:11228 .rodata.ad9102_reg_addr:00000000 ad9102_reg_addr /tmp/ccYgfTud.s:1040 .text.AD9102_Init:00000000 $t /tmp/ccYgfTud.s:1045 .text.AD9102_Init:00000000 AD9102_Init /tmp/ccYgfTud.s:1126 .text.AD9102_Init:00000064 $d /tmp/ccYgfTud.s:11157 .rodata.ad9102_example4_regval:00000000 ad9102_example4_regval /tmp/ccYgfTud.s:1134 .text.AD9102_ReadReg:00000000 $t /tmp/ccYgfTud.s:1139 .text.AD9102_ReadReg:00000000 AD9102_ReadReg /tmp/ccYgfTud.s:1394 .text.AD9102_ReadReg:000000a8 $d /tmp/ccYgfTud.s:1400 .text.AD9102_CheckFlags:00000000 $t /tmp/ccYgfTud.s:1405 .text.AD9102_CheckFlags:00000000 AD9102_CheckFlags /tmp/ccYgfTud.s:1635 .text.AD9102_Apply:00000000 $t /tmp/ccYgfTud.s:1640 .text.AD9102_Apply:00000000 AD9102_Apply /tmp/ccYgfTud.s:1811 .text.AD9102_Apply:000000b4 $d /tmp/ccYgfTud.s:1816 .text.OUT_trigger:00000000 $t /tmp/ccYgfTud.s:1821 .text.OUT_trigger:00000000 OUT_trigger /tmp/ccYgfTud.s:1839 .text.OUT_trigger:0000000a $d /tmp/ccYgfTud.s:1849 .text.OUT_trigger:00000014 $t /tmp/ccYgfTud.s:2045 .text.OUT_trigger:0000011c $d /tmp/ccYgfTud.s:2051 .text.MPhD_T:00000000 $t /tmp/ccYgfTud.s:2056 .text.MPhD_T:00000000 MPhD_T /tmp/ccYgfTud.s:2140 .text.MPhD_T:00000056 $d /tmp/ccYgfTud.s:2144 .text.MPhD_T:0000005a $t /tmp/ccYgfTud.s:2687 .text.MPhD_T:00000210 $d /tmp/ccYgfTud.s:2697 .text.Stop_TIM10:00000000 $t /tmp/ccYgfTud.s:2702 .text.Stop_TIM10:00000000 Stop_TIM10 /tmp/ccYgfTud.s:2731 .text.Stop_TIM10:00000014 $d /tmp/ccYgfTud.s:11606 .bss.htim10:00000000 htim10 /tmp/ccYgfTud.s:11438 .bss.TIM10_coflag:00000000 TIM10_coflag /tmp/ccYgfTud.s:11515 .bss.TO10:00000000 TO10 /tmp/ccYgfTud.s:2738 .text.MX_GPIO_Init:00000000 $t ARM GAS /tmp/ccYgfTud.s page 607 /tmp/ccYgfTud.s:2743 .text.MX_GPIO_Init:00000000 MX_GPIO_Init /tmp/ccYgfTud.s:3204 .text.MX_GPIO_Init:0000023c $d /tmp/ccYgfTud.s:3216 .text.MX_SPI4_Init:00000000 $t /tmp/ccYgfTud.s:3221 .text.MX_SPI4_Init:00000000 MX_SPI4_Init /tmp/ccYgfTud.s:3426 .text.MX_SPI4_Init:000000c8 $d /tmp/ccYgfTud.s:3433 .text.MX_SPI2_Init:00000000 $t /tmp/ccYgfTud.s:3438 .text.MX_SPI2_Init:00000000 MX_SPI2_Init /tmp/ccYgfTud.s:3666 .text.MX_SPI2_Init:000000dc $d /tmp/ccYgfTud.s:3673 .text.MX_SPI5_Init:00000000 $t /tmp/ccYgfTud.s:3678 .text.MX_SPI5_Init:00000000 MX_SPI5_Init /tmp/ccYgfTud.s:3883 .text.MX_SPI5_Init:000000c4 $d /tmp/ccYgfTud.s:3890 .text.MX_SPI6_Init:00000000 $t /tmp/ccYgfTud.s:3895 .text.MX_SPI6_Init:00000000 MX_SPI6_Init /tmp/ccYgfTud.s:4100 .text.MX_SPI6_Init:000000c4 $d /tmp/ccYgfTud.s:4107 .text.MX_TIM2_Init:00000000 $t /tmp/ccYgfTud.s:4112 .text.MX_TIM2_Init:00000000 MX_TIM2_Init /tmp/ccYgfTud.s:4290 .text.MX_TIM2_Init:00000088 $d /tmp/ccYgfTud.s:4299 .text.MX_TIM5_Init:00000000 $t /tmp/ccYgfTud.s:4304 .text.MX_TIM5_Init:00000000 MX_TIM5_Init /tmp/ccYgfTud.s:4481 .text.MX_TIM5_Init:00000084 $d /tmp/ccYgfTud.s:4490 .text.MX_TIM7_Init:00000000 $t /tmp/ccYgfTud.s:4495 .text.MX_TIM7_Init:00000000 MX_TIM7_Init /tmp/ccYgfTud.s:4656 .text.MX_TIM7_Init:0000007c $d /tmp/ccYgfTud.s:4664 .text.MX_TIM6_Init:00000000 $t /tmp/ccYgfTud.s:4669 .text.MX_TIM6_Init:00000000 MX_TIM6_Init /tmp/ccYgfTud.s:4830 .text.MX_TIM6_Init:0000007c $d /tmp/ccYgfTud.s:4838 .rodata.Init_params.str1.4:00000000 $d /tmp/ccYgfTud.s:4845 .text.Init_params:00000000 $t /tmp/ccYgfTud.s:4850 .text.Init_params:00000000 Init_params /tmp/ccYgfTud.s:5486 .text.Init_params:00000284 $d /tmp/ccYgfTud.s:11585 .bss.TO6:00000000 TO6 /tmp/ccYgfTud.s:11529 .bss.TO7_before:00000000 TO7_before /tmp/ccYgfTud.s:11578 .bss.TO6_before:00000000 TO6_before /tmp/ccYgfTud.s:11564 .bss.TO6_uart:00000000 TO6_uart /tmp/ccYgfTud.s:11456 .bss.flg_tmt:00000000 flg_tmt /tmp/ccYgfTud.s:11432 .bss.UART_rec_incr:00000000 UART_rec_incr /tmp/ccYgfTud.s:11377 .bss.fgoto:00000000 fgoto /tmp/ccYgfTud.s:11370 .bss.sizeoffile:00000000 sizeoffile /tmp/ccYgfTud.s:11450 .bss.u_tx_flg:00000000 u_tx_flg /tmp/ccYgfTud.s:11444 .bss.u_rx_flg:00000000 u_rx_flg /tmp/ccYgfTud.s:11404 .bss.Long_Data:00000000 Long_Data /tmp/ccYgfTud.s:11328 .bss.Def_setup:00000000 Def_setup /tmp/ccYgfTud.s:11349 .bss.LD1_def_setup:00000000 LD1_def_setup /tmp/ccYgfTud.s:11342 .bss.LD2_def_setup:00000000 LD2_def_setup /tmp/ccYgfTud.s:11335 .bss.Curr_setup:00000000 Curr_setup /tmp/ccYgfTud.s:11363 .bss.LD1_curr_setup:00000000 LD1_curr_setup /tmp/ccYgfTud.s:11356 .bss.LD2_curr_setup:00000000 LD2_curr_setup /tmp/ccYgfTud.s:11463 .bss.UART_DATA:00000000 UART_DATA /tmp/ccYgfTud.s:11557 .bss.SD_SEEK:00000000 SD_SEEK /tmp/ccYgfTud.s:11550 .bss.SD_SLIDE:00000000 SD_SLIDE /tmp/ccYgfTud.s:11384 .bss.test:00000000 test /tmp/ccYgfTud.s:11488 .bss.CPU_state:00000000 CPU_state /tmp/ccYgfTud.s:11397 .bss.COMMAND:00000000 COMMAND /tmp/ccYgfTud.s:5525 .text.Get_ADC:00000000 $t /tmp/ccYgfTud.s:5530 .text.Get_ADC:00000000 Get_ADC /tmp/ccYgfTud.s:5550 .text.Get_ADC:0000000c $d /tmp/ccYgfTud.s:5556 .text.Get_ADC:00000012 $t ARM GAS /tmp/ccYgfTud.s page 608 /tmp/ccYgfTud.s:5654 .text.Get_ADC:00000068 $d /tmp/ccYgfTud.s:11641 .bss.hadc1:00000000 hadc1 /tmp/ccYgfTud.s:11634 .bss.hadc3:00000000 hadc3 /tmp/ccYgfTud.s:5660 .text.Set_LTEC:00000000 $t /tmp/ccYgfTud.s:5666 .text.Set_LTEC:00000000 Set_LTEC /tmp/ccYgfTud.s:5697 .text.Set_LTEC:00000018 $d /tmp/ccYgfTud.s:5701 .text.Set_LTEC:0000001c $t /tmp/ccYgfTud.s:6123 .text.Set_LTEC:00000154 $d /tmp/ccYgfTud.s:6131 .text.Decode_uart:00000000 $t /tmp/ccYgfTud.s:6136 .text.Decode_uart:00000000 Decode_uart /tmp/ccYgfTud.s:6699 .text.Decode_uart:000002cc $d /tmp/ccYgfTud.s:6714 .text.Advanced_Controller_Temp:00000000 $t /tmp/ccYgfTud.s:6720 .text.Advanced_Controller_Temp:00000000 Advanced_Controller_Temp /tmp/ccYgfTud.s:6889 .text.Advanced_Controller_Temp:000000cc $d /tmp/ccYgfTud.s:6899 .text.CalculateChecksum:00000000 $t /tmp/ccYgfTud.s:6905 .text.CalculateChecksum:00000000 CalculateChecksum /tmp/ccYgfTud.s:6950 .text.CheckChecksum:00000000 $t /tmp/ccYgfTud.s:6956 .text.CheckChecksum:00000000 CheckChecksum /tmp/ccYgfTud.s:7018 .text.CheckChecksum:0000003c $d /tmp/ccYgfTud.s:11425 .bss.UART_header:00000000 UART_header /tmp/ccYgfTud.s:11418 .bss.CS_result:00000000 CS_result /tmp/ccYgfTud.s:7025 .rodata.SD_SAVE.str1.4:00000000 $d /tmp/ccYgfTud.s:7029 .text.SD_SAVE:00000000 $t /tmp/ccYgfTud.s:7035 .text.SD_SAVE:00000000 SD_SAVE /tmp/ccYgfTud.s:7104 .text.SD_SAVE:00000030 $d /tmp/ccYgfTud.s:7111 .text.SD_READ:00000000 $t /tmp/ccYgfTud.s:7117 .text.SD_READ:00000000 SD_READ /tmp/ccYgfTud.s:7195 .text.SD_READ:0000003c $d /tmp/ccYgfTud.s:7203 .text.SD_REMOVE:00000000 $t /tmp/ccYgfTud.s:7209 .text.SD_REMOVE:00000000 SD_REMOVE /tmp/ccYgfTud.s:7277 .text.SD_REMOVE:00000034 $d /tmp/ccYgfTud.s:7284 .text.USART_TX:00000000 $t /tmp/ccYgfTud.s:7290 .text.USART_TX:00000000 USART_TX /tmp/ccYgfTud.s:7365 .text.USART_TX:00000028 $d /tmp/ccYgfTud.s:7370 .text.USART_TX_DMA:00000000 $t /tmp/ccYgfTud.s:7376 .text.USART_TX_DMA:00000000 USART_TX_DMA /tmp/ccYgfTud.s:7445 .text.USART_TX_DMA:00000038 $d /tmp/ccYgfTud.s:7451 .text.Error_Handler:00000000 $t /tmp/ccYgfTud.s:7457 .text.Error_Handler:00000000 Error_Handler /tmp/ccYgfTud.s:7488 .text.MX_ADC1_Init:00000000 $t /tmp/ccYgfTud.s:7493 .text.MX_ADC1_Init:00000000 MX_ADC1_Init /tmp/ccYgfTud.s:7682 .text.MX_ADC1_Init:000000bc $d /tmp/ccYgfTud.s:7689 .text.MX_ADC3_Init:00000000 $t /tmp/ccYgfTud.s:7694 .text.MX_ADC3_Init:00000000 MX_ADC3_Init /tmp/ccYgfTud.s:7801 .text.MX_ADC3_Init:00000060 $d /tmp/ccYgfTud.s:7808 .text.MX_USART1_UART_Init:00000000 $t /tmp/ccYgfTud.s:7813 .text.MX_USART1_UART_Init:00000000 MX_USART1_UART_Init /tmp/ccYgfTud.s:8212 .text.MX_USART1_UART_Init:0000017c $d /tmp/ccYgfTud.s:8221 .text.MX_TIM10_Init:00000000 $t /tmp/ccYgfTud.s:8226 .text.MX_TIM10_Init:00000000 MX_TIM10_Init /tmp/ccYgfTud.s:8275 .text.MX_TIM10_Init:00000024 $d /tmp/ccYgfTud.s:8281 .text.MX_UART8_Init:00000000 $t /tmp/ccYgfTud.s:8286 .text.MX_UART8_Init:00000000 MX_UART8_Init /tmp/ccYgfTud.s:8347 .text.MX_UART8_Init:00000030 $d /tmp/ccYgfTud.s:11592 .bss.huart8:00000000 huart8 /tmp/ccYgfTud.s:8353 .text.MX_TIM8_Init:00000000 $t /tmp/ccYgfTud.s:8358 .text.MX_TIM8_Init:00000000 MX_TIM8_Init ARM GAS /tmp/ccYgfTud.s page 609 /tmp/ccYgfTud.s:8467 .text.MX_TIM8_Init:00000064 $d /tmp/ccYgfTud.s:11613 .bss.htim8:00000000 htim8 /tmp/ccYgfTud.s:8473 .text.MX_TIM11_Init:00000000 $t /tmp/ccYgfTud.s:8478 .text.MX_TIM11_Init:00000000 MX_TIM11_Init /tmp/ccYgfTud.s:8588 .text.MX_TIM11_Init:00000068 $d /tmp/ccYgfTud.s:11599 .bss.htim11:00000000 htim11 /tmp/ccYgfTud.s:8594 .text.MX_TIM4_Init:00000000 $t /tmp/ccYgfTud.s:8599 .text.MX_TIM4_Init:00000000 MX_TIM4_Init /tmp/ccYgfTud.s:8754 .text.MX_TIM4_Init:0000009c $d /tmp/ccYgfTud.s:11620 .bss.htim4:00000000 htim4 /tmp/ccYgfTud.s:8760 .text.SystemClock_Config:00000000 $t /tmp/ccYgfTud.s:8766 .text.SystemClock_Config:00000000 SystemClock_Config /tmp/ccYgfTud.s:8925 .text.SystemClock_Config:000000ac $d /tmp/ccYgfTud.s:8931 .text.main:00000000 $t /tmp/ccYgfTud.s:8937 .text.main:00000000 main /tmp/ccYgfTud.s:9341 .text.main:00000140 $d /tmp/ccYgfTud.s:9352 .text.main:0000016c $t /tmp/ccYgfTud.s:9605 .text.main:00000278 $d /tmp/ccYgfTud.s:11482 .bss.CPU_state_old:00000000 CPU_state_old /tmp/ccYgfTud.s:11476 .bss.UART_transmission_request:00000000 UART_transmission_request /tmp/ccYgfTud.s:11470 .bss.State_Data:00000000 State_Data /tmp/ccYgfTud.s:11411 .bss.temp16:00000000 temp16 /tmp/ccYgfTud.s:9629 .text.main:000002cc $t /tmp/ccYgfTud.s:10187 .text.main:0000054c $d /tmp/ccYgfTud.s:11321 .bss.LD1_param:00000000 LD1_param /tmp/ccYgfTud.s:11314 .bss.LD2_param:00000000 LD2_param /tmp/ccYgfTud.s:11571 .bss.TO6_stop:00000000 TO6_stop /tmp/ccYgfTud.s:11501 .bss.TIM10_period:00000000 TIM10_period /tmp/ccYgfTud.s:10215 .text.main:000005ac $t /tmp/ccYgfTud.s:10727 .text.main:00000864 $d /tmp/ccYgfTud.s:11307 .bss.LD_blinker:00000000 LD_blinker /tmp/ccYgfTud.s:10750 .text.main:000008b8 $t /tmp/ccYgfTud.s:11128 .text.main:00000a6c $d /tmp/ccYgfTud.s:11154 .rodata.ad9102_example4_regval:00000000 $d /tmp/ccYgfTud.s:11225 .rodata.ad9102_reg_addr:00000000 $d /tmp/ccYgfTud.s:11297 .bss.task:00000000 $d /tmp/ccYgfTud.s:11304 .bss.LD_blinker:00000000 $d /tmp/ccYgfTud.s:11311 .bss.LD2_param:00000000 $d /tmp/ccYgfTud.s:11318 .bss.LD1_param:00000000 $d /tmp/ccYgfTud.s:11325 .bss.Def_setup:00000000 $d /tmp/ccYgfTud.s:11332 .bss.Curr_setup:00000000 $d /tmp/ccYgfTud.s:11339 .bss.LD2_def_setup:00000000 $d /tmp/ccYgfTud.s:11346 .bss.LD1_def_setup:00000000 $d /tmp/ccYgfTud.s:11353 .bss.LD2_curr_setup:00000000 $d /tmp/ccYgfTud.s:11360 .bss.LD1_curr_setup:00000000 $d /tmp/ccYgfTud.s:11367 .bss.sizeoffile:00000000 $d /tmp/ccYgfTud.s:11374 .bss.fgoto:00000000 $d /tmp/ccYgfTud.s:11381 .bss.test:00000000 $d /tmp/ccYgfTud.s:11390 .bss.fresult:00000000 fresult /tmp/ccYgfTud.s:11391 .bss.fresult:00000000 $d /tmp/ccYgfTud.s:11394 .bss.COMMAND:00000000 $d /tmp/ccYgfTud.s:11401 .bss.Long_Data:00000000 $d /tmp/ccYgfTud.s:11408 .bss.temp16:00000000 $d /tmp/ccYgfTud.s:11415 .bss.CS_result:00000000 $d /tmp/ccYgfTud.s:11422 .bss.UART_header:00000000 $d /tmp/ccYgfTud.s:11429 .bss.UART_rec_incr:00000000 $d /tmp/ccYgfTud.s:11439 .bss.TIM10_coflag:00000000 $d ARM GAS /tmp/ccYgfTud.s page 610 /tmp/ccYgfTud.s:11445 .bss.u_rx_flg:00000000 $d /tmp/ccYgfTud.s:11451 .bss.u_tx_flg:00000000 $d /tmp/ccYgfTud.s:11457 .bss.flg_tmt:00000000 $d /tmp/ccYgfTud.s:11460 .bss.UART_DATA:00000000 $d /tmp/ccYgfTud.s:11467 .bss.State_Data:00000000 $d /tmp/ccYgfTud.s:11477 .bss.UART_transmission_request:00000000 $d /tmp/ccYgfTud.s:11483 .bss.CPU_state_old:00000000 $d /tmp/ccYgfTud.s:11489 .bss.CPU_state:00000000 $d /tmp/ccYgfTud.s:11494 .bss.uart_buf:00000000 uart_buf /tmp/ccYgfTud.s:11495 .bss.uart_buf:00000000 $d /tmp/ccYgfTud.s:11498 .bss.TIM10_period:00000000 $d /tmp/ccYgfTud.s:11505 .bss.TO10_counter:00000000 $d /tmp/ccYgfTud.s:11512 .bss.TO10:00000000 $d /tmp/ccYgfTud.s:11519 .bss.TO7_PID:00000000 $d /tmp/ccYgfTud.s:11526 .bss.TO7_before:00000000 $d /tmp/ccYgfTud.s:11533 .bss.TO7:00000000 $d /tmp/ccYgfTud.s:11543 .bss.temp32:00000000 temp32 /tmp/ccYgfTud.s:11540 .bss.temp32:00000000 $d /tmp/ccYgfTud.s:11547 .bss.SD_SLIDE:00000000 $d /tmp/ccYgfTud.s:11554 .bss.SD_SEEK:00000000 $d /tmp/ccYgfTud.s:11561 .bss.TO6_uart:00000000 $d /tmp/ccYgfTud.s:11568 .bss.TO6_stop:00000000 $d /tmp/ccYgfTud.s:11575 .bss.TO6_before:00000000 $d /tmp/ccYgfTud.s:11582 .bss.TO6:00000000 $d /tmp/ccYgfTud.s:11589 .bss.huart8:00000000 $d /tmp/ccYgfTud.s:11596 .bss.htim11:00000000 $d /tmp/ccYgfTud.s:11603 .bss.htim10:00000000 $d /tmp/ccYgfTud.s:11610 .bss.htim8:00000000 $d /tmp/ccYgfTud.s:11617 .bss.htim4:00000000 $d /tmp/ccYgfTud.s:11624 .bss.hsd1:00000000 $d /tmp/ccYgfTud.s:11631 .bss.hadc3:00000000 $d /tmp/ccYgfTud.s:11638 .bss.hadc1:00000000 $d UNDEFINED SYMBOLS HAL_GPIO_WritePin HAL_TIM_Base_Stop_IT HAL_GPIO_Init memset LL_GPIO_Init LL_SPI_Init LL_TIM_Init HAL_GPIO_ReadPin Mount_SD Seek_Read_File Unmount_SD HAL_ADC_Start HAL_ADC_PollForConversion HAL_ADC_GetValue HAL_ADC_Stop Remove_File Create_File Write_File_byte Update_File_byte HAL_ADC_Init HAL_ADC_ConfigChannel HAL_RCCEx_PeriphCLKConfig LL_USART_Init ARM GAS /tmp/ccYgfTud.s page 611 HAL_TIM_Base_Init HAL_UART_Init HAL_TIM_ConfigClockSource HAL_TIMEx_MasterConfigSynchronization HAL_TIM_PWM_Init HAL_TIM_PWM_ConfigChannel HAL_TIM_MspPostInit HAL_RCC_OscConfig HAL_PWREx_EnableOverDrive HAL_RCC_ClockConfig HAL_Init MX_FATFS_Init HAL_TIM_Base_Start_IT HAL_TIM_PWM_Stop HAL_TIM_PWM_Start HAL_TIM_Base_Stop