ARM GAS /tmp/ccqopZd5.s page 1 1 .cpu cortex-m7 2 .eabi_attribute 28, 1 3 .eabi_attribute 20, 1 4 .eabi_attribute 21, 1 5 .eabi_attribute 23, 3 6 .eabi_attribute 24, 1 7 .eabi_attribute 25, 1 8 .eabi_attribute 26, 1 9 .eabi_attribute 30, 1 10 .eabi_attribute 34, 1 11 .eabi_attribute 18, 4 12 .file "main.c" 13 .text 14 .Ltext0: 15 .cfi_sections .debug_frame 16 .section .text.NVIC_EncodePriority,"ax",%progbits 17 .align 1 18 .arch armv7e-m 19 .syntax unified 20 .thumb 21 .thumb_func 22 .fpu fpv5-d16 24 NVIC_EncodePriority: 25 .LVL0: 26 .LFB113: 27 .file 1 "Drivers/CMSIS/Include/core_cm7.h" 1:Drivers/CMSIS/Include/core_cm7.h **** /**************************************************************************//** 2:Drivers/CMSIS/Include/core_cm7.h **** * @file core_cm7.h 3:Drivers/CMSIS/Include/core_cm7.h **** * @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File 4:Drivers/CMSIS/Include/core_cm7.h **** * @version V5.0.8 5:Drivers/CMSIS/Include/core_cm7.h **** * @date 04. June 2018 6:Drivers/CMSIS/Include/core_cm7.h **** ******************************************************************************/ 7:Drivers/CMSIS/Include/core_cm7.h **** /* 8:Drivers/CMSIS/Include/core_cm7.h **** * Copyright (c) 2009-2018 Arm Limited. All rights reserved. 9:Drivers/CMSIS/Include/core_cm7.h **** * 10:Drivers/CMSIS/Include/core_cm7.h **** * SPDX-License-Identifier: Apache-2.0 11:Drivers/CMSIS/Include/core_cm7.h **** * 12:Drivers/CMSIS/Include/core_cm7.h **** * Licensed under the Apache License, Version 2.0 (the License); you may 13:Drivers/CMSIS/Include/core_cm7.h **** * not use this file except in compliance with the License. 14:Drivers/CMSIS/Include/core_cm7.h **** * You may obtain a copy of the License at 15:Drivers/CMSIS/Include/core_cm7.h **** * 16:Drivers/CMSIS/Include/core_cm7.h **** * www.apache.org/licenses/LICENSE-2.0 17:Drivers/CMSIS/Include/core_cm7.h **** * 18:Drivers/CMSIS/Include/core_cm7.h **** * Unless required by applicable law or agreed to in writing, software 19:Drivers/CMSIS/Include/core_cm7.h **** * distributed under the License is distributed on an AS IS BASIS, WITHOUT 20:Drivers/CMSIS/Include/core_cm7.h **** * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 21:Drivers/CMSIS/Include/core_cm7.h **** * See the License for the specific language governing permissions and 22:Drivers/CMSIS/Include/core_cm7.h **** * limitations under the License. 23:Drivers/CMSIS/Include/core_cm7.h **** */ 24:Drivers/CMSIS/Include/core_cm7.h **** 25:Drivers/CMSIS/Include/core_cm7.h **** #if defined ( __ICCARM__ ) 26:Drivers/CMSIS/Include/core_cm7.h **** #pragma system_include /* treat file as system include file for MISRA check */ 27:Drivers/CMSIS/Include/core_cm7.h **** #elif defined (__clang__) 28:Drivers/CMSIS/Include/core_cm7.h **** #pragma clang system_header /* treat file as system include file */ 29:Drivers/CMSIS/Include/core_cm7.h **** #endif 30:Drivers/CMSIS/Include/core_cm7.h **** 31:Drivers/CMSIS/Include/core_cm7.h **** #ifndef __CORE_CM7_H_GENERIC ARM GAS /tmp/ccqopZd5.s page 2 32:Drivers/CMSIS/Include/core_cm7.h **** #define __CORE_CM7_H_GENERIC 33:Drivers/CMSIS/Include/core_cm7.h **** 34:Drivers/CMSIS/Include/core_cm7.h **** #include 35:Drivers/CMSIS/Include/core_cm7.h **** 36:Drivers/CMSIS/Include/core_cm7.h **** #ifdef __cplusplus 37:Drivers/CMSIS/Include/core_cm7.h **** extern "C" { 38:Drivers/CMSIS/Include/core_cm7.h **** #endif 39:Drivers/CMSIS/Include/core_cm7.h **** 40:Drivers/CMSIS/Include/core_cm7.h **** /** 41:Drivers/CMSIS/Include/core_cm7.h **** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions 42:Drivers/CMSIS/Include/core_cm7.h **** CMSIS violates the following MISRA-C:2004 rules: 43:Drivers/CMSIS/Include/core_cm7.h **** 44:Drivers/CMSIS/Include/core_cm7.h **** \li Required Rule 8.5, object/function definition in header file.
45:Drivers/CMSIS/Include/core_cm7.h **** Function definitions in header files are used to allow 'inlining'. 46:Drivers/CMSIS/Include/core_cm7.h **** 47:Drivers/CMSIS/Include/core_cm7.h **** \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
48:Drivers/CMSIS/Include/core_cm7.h **** Unions are used for effective representation of core registers. 49:Drivers/CMSIS/Include/core_cm7.h **** 50:Drivers/CMSIS/Include/core_cm7.h **** \li Advisory Rule 19.7, Function-like macro defined.
51:Drivers/CMSIS/Include/core_cm7.h **** Function-like macros are used to allow more efficient code. 52:Drivers/CMSIS/Include/core_cm7.h **** */ 53:Drivers/CMSIS/Include/core_cm7.h **** 54:Drivers/CMSIS/Include/core_cm7.h **** 55:Drivers/CMSIS/Include/core_cm7.h **** /******************************************************************************* 56:Drivers/CMSIS/Include/core_cm7.h **** * CMSIS definitions 57:Drivers/CMSIS/Include/core_cm7.h **** ******************************************************************************/ 58:Drivers/CMSIS/Include/core_cm7.h **** /** 59:Drivers/CMSIS/Include/core_cm7.h **** \ingroup Cortex_M7 60:Drivers/CMSIS/Include/core_cm7.h **** @{ 61:Drivers/CMSIS/Include/core_cm7.h **** */ 62:Drivers/CMSIS/Include/core_cm7.h **** 63:Drivers/CMSIS/Include/core_cm7.h **** #include "cmsis_version.h" 64:Drivers/CMSIS/Include/core_cm7.h **** 65:Drivers/CMSIS/Include/core_cm7.h **** /* CMSIS CM7 definitions */ 66:Drivers/CMSIS/Include/core_cm7.h **** #define __CM7_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:1 67:Drivers/CMSIS/Include/core_cm7.h **** #define __CM7_CMSIS_VERSION_SUB ( __CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0 68:Drivers/CMSIS/Include/core_cm7.h **** #define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16U) | \ 69:Drivers/CMSIS/Include/core_cm7.h **** __CM7_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS 70:Drivers/CMSIS/Include/core_cm7.h **** 71:Drivers/CMSIS/Include/core_cm7.h **** #define __CORTEX_M (7U) /*!< Cortex-M Core */ 72:Drivers/CMSIS/Include/core_cm7.h **** 73:Drivers/CMSIS/Include/core_cm7.h **** /** __FPU_USED indicates whether an FPU is used or not. 74:Drivers/CMSIS/Include/core_cm7.h **** For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and fun 75:Drivers/CMSIS/Include/core_cm7.h **** */ 76:Drivers/CMSIS/Include/core_cm7.h **** #if defined ( __CC_ARM ) 77:Drivers/CMSIS/Include/core_cm7.h **** #if defined __TARGET_FPU_VFP 78:Drivers/CMSIS/Include/core_cm7.h **** #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) 79:Drivers/CMSIS/Include/core_cm7.h **** #define __FPU_USED 1U 80:Drivers/CMSIS/Include/core_cm7.h **** #else 81:Drivers/CMSIS/Include/core_cm7.h **** #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT) 82:Drivers/CMSIS/Include/core_cm7.h **** #define __FPU_USED 0U 83:Drivers/CMSIS/Include/core_cm7.h **** #endif 84:Drivers/CMSIS/Include/core_cm7.h **** #else 85:Drivers/CMSIS/Include/core_cm7.h **** #define __FPU_USED 0U 86:Drivers/CMSIS/Include/core_cm7.h **** #endif 87:Drivers/CMSIS/Include/core_cm7.h **** 88:Drivers/CMSIS/Include/core_cm7.h **** #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) ARM GAS /tmp/ccqopZd5.s page 3 89:Drivers/CMSIS/Include/core_cm7.h **** #if defined __ARM_PCS_VFP 90:Drivers/CMSIS/Include/core_cm7.h **** #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) 91:Drivers/CMSIS/Include/core_cm7.h **** #define __FPU_USED 1U 92:Drivers/CMSIS/Include/core_cm7.h **** #else 93:Drivers/CMSIS/Include/core_cm7.h **** #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESEN 94:Drivers/CMSIS/Include/core_cm7.h **** #define __FPU_USED 0U 95:Drivers/CMSIS/Include/core_cm7.h **** #endif 96:Drivers/CMSIS/Include/core_cm7.h **** #else 97:Drivers/CMSIS/Include/core_cm7.h **** #define __FPU_USED 0U 98:Drivers/CMSIS/Include/core_cm7.h **** #endif 99:Drivers/CMSIS/Include/core_cm7.h **** 100:Drivers/CMSIS/Include/core_cm7.h **** #elif defined ( __GNUC__ ) 101:Drivers/CMSIS/Include/core_cm7.h **** #if defined (__VFP_FP__) && !defined(__SOFTFP__) 102:Drivers/CMSIS/Include/core_cm7.h **** #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) 103:Drivers/CMSIS/Include/core_cm7.h **** #define __FPU_USED 1U 104:Drivers/CMSIS/Include/core_cm7.h **** #else 105:Drivers/CMSIS/Include/core_cm7.h **** #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT) 106:Drivers/CMSIS/Include/core_cm7.h **** #define __FPU_USED 0U 107:Drivers/CMSIS/Include/core_cm7.h **** #endif 108:Drivers/CMSIS/Include/core_cm7.h **** #else 109:Drivers/CMSIS/Include/core_cm7.h **** #define __FPU_USED 0U 110:Drivers/CMSIS/Include/core_cm7.h **** #endif 111:Drivers/CMSIS/Include/core_cm7.h **** 112:Drivers/CMSIS/Include/core_cm7.h **** #elif defined ( __ICCARM__ ) 113:Drivers/CMSIS/Include/core_cm7.h **** #if defined __ARMVFP__ 114:Drivers/CMSIS/Include/core_cm7.h **** #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) 115:Drivers/CMSIS/Include/core_cm7.h **** #define __FPU_USED 1U 116:Drivers/CMSIS/Include/core_cm7.h **** #else 117:Drivers/CMSIS/Include/core_cm7.h **** #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT) 118:Drivers/CMSIS/Include/core_cm7.h **** #define __FPU_USED 0U 119:Drivers/CMSIS/Include/core_cm7.h **** #endif 120:Drivers/CMSIS/Include/core_cm7.h **** #else 121:Drivers/CMSIS/Include/core_cm7.h **** #define __FPU_USED 0U 122:Drivers/CMSIS/Include/core_cm7.h **** #endif 123:Drivers/CMSIS/Include/core_cm7.h **** 124:Drivers/CMSIS/Include/core_cm7.h **** #elif defined ( __TI_ARM__ ) 125:Drivers/CMSIS/Include/core_cm7.h **** #if defined __TI_VFP_SUPPORT__ 126:Drivers/CMSIS/Include/core_cm7.h **** #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) 127:Drivers/CMSIS/Include/core_cm7.h **** #define __FPU_USED 1U 128:Drivers/CMSIS/Include/core_cm7.h **** #else 129:Drivers/CMSIS/Include/core_cm7.h **** #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT) 130:Drivers/CMSIS/Include/core_cm7.h **** #define __FPU_USED 0U 131:Drivers/CMSIS/Include/core_cm7.h **** #endif 132:Drivers/CMSIS/Include/core_cm7.h **** #else 133:Drivers/CMSIS/Include/core_cm7.h **** #define __FPU_USED 0U 134:Drivers/CMSIS/Include/core_cm7.h **** #endif 135:Drivers/CMSIS/Include/core_cm7.h **** 136:Drivers/CMSIS/Include/core_cm7.h **** #elif defined ( __TASKING__ ) 137:Drivers/CMSIS/Include/core_cm7.h **** #if defined __FPU_VFP__ 138:Drivers/CMSIS/Include/core_cm7.h **** #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) 139:Drivers/CMSIS/Include/core_cm7.h **** #define __FPU_USED 1U 140:Drivers/CMSIS/Include/core_cm7.h **** #else 141:Drivers/CMSIS/Include/core_cm7.h **** #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT) 142:Drivers/CMSIS/Include/core_cm7.h **** #define __FPU_USED 0U 143:Drivers/CMSIS/Include/core_cm7.h **** #endif 144:Drivers/CMSIS/Include/core_cm7.h **** #else 145:Drivers/CMSIS/Include/core_cm7.h **** #define __FPU_USED 0U ARM GAS /tmp/ccqopZd5.s page 4 146:Drivers/CMSIS/Include/core_cm7.h **** #endif 147:Drivers/CMSIS/Include/core_cm7.h **** 148:Drivers/CMSIS/Include/core_cm7.h **** #elif defined ( __CSMC__ ) 149:Drivers/CMSIS/Include/core_cm7.h **** #if ( __CSMC__ & 0x400U) 150:Drivers/CMSIS/Include/core_cm7.h **** #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) 151:Drivers/CMSIS/Include/core_cm7.h **** #define __FPU_USED 1U 152:Drivers/CMSIS/Include/core_cm7.h **** #else 153:Drivers/CMSIS/Include/core_cm7.h **** #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT) 154:Drivers/CMSIS/Include/core_cm7.h **** #define __FPU_USED 0U 155:Drivers/CMSIS/Include/core_cm7.h **** #endif 156:Drivers/CMSIS/Include/core_cm7.h **** #else 157:Drivers/CMSIS/Include/core_cm7.h **** #define __FPU_USED 0U 158:Drivers/CMSIS/Include/core_cm7.h **** #endif 159:Drivers/CMSIS/Include/core_cm7.h **** 160:Drivers/CMSIS/Include/core_cm7.h **** #endif 161:Drivers/CMSIS/Include/core_cm7.h **** 162:Drivers/CMSIS/Include/core_cm7.h **** #include "cmsis_compiler.h" /* CMSIS compiler specific defines */ 163:Drivers/CMSIS/Include/core_cm7.h **** 164:Drivers/CMSIS/Include/core_cm7.h **** 165:Drivers/CMSIS/Include/core_cm7.h **** #ifdef __cplusplus 166:Drivers/CMSIS/Include/core_cm7.h **** } 167:Drivers/CMSIS/Include/core_cm7.h **** #endif 168:Drivers/CMSIS/Include/core_cm7.h **** 169:Drivers/CMSIS/Include/core_cm7.h **** #endif /* __CORE_CM7_H_GENERIC */ 170:Drivers/CMSIS/Include/core_cm7.h **** 171:Drivers/CMSIS/Include/core_cm7.h **** #ifndef __CMSIS_GENERIC 172:Drivers/CMSIS/Include/core_cm7.h **** 173:Drivers/CMSIS/Include/core_cm7.h **** #ifndef __CORE_CM7_H_DEPENDANT 174:Drivers/CMSIS/Include/core_cm7.h **** #define __CORE_CM7_H_DEPENDANT 175:Drivers/CMSIS/Include/core_cm7.h **** 176:Drivers/CMSIS/Include/core_cm7.h **** #ifdef __cplusplus 177:Drivers/CMSIS/Include/core_cm7.h **** extern "C" { 178:Drivers/CMSIS/Include/core_cm7.h **** #endif 179:Drivers/CMSIS/Include/core_cm7.h **** 180:Drivers/CMSIS/Include/core_cm7.h **** /* check device defines and use defaults */ 181:Drivers/CMSIS/Include/core_cm7.h **** #if defined __CHECK_DEVICE_DEFINES 182:Drivers/CMSIS/Include/core_cm7.h **** #ifndef __CM7_REV 183:Drivers/CMSIS/Include/core_cm7.h **** #define __CM7_REV 0x0000U 184:Drivers/CMSIS/Include/core_cm7.h **** #warning "__CM7_REV not defined in device header file; using default!" 185:Drivers/CMSIS/Include/core_cm7.h **** #endif 186:Drivers/CMSIS/Include/core_cm7.h **** 187:Drivers/CMSIS/Include/core_cm7.h **** #ifndef __FPU_PRESENT 188:Drivers/CMSIS/Include/core_cm7.h **** #define __FPU_PRESENT 0U 189:Drivers/CMSIS/Include/core_cm7.h **** #warning "__FPU_PRESENT not defined in device header file; using default!" 190:Drivers/CMSIS/Include/core_cm7.h **** #endif 191:Drivers/CMSIS/Include/core_cm7.h **** 192:Drivers/CMSIS/Include/core_cm7.h **** #ifndef __MPU_PRESENT 193:Drivers/CMSIS/Include/core_cm7.h **** #define __MPU_PRESENT 0U 194:Drivers/CMSIS/Include/core_cm7.h **** #warning "__MPU_PRESENT not defined in device header file; using default!" 195:Drivers/CMSIS/Include/core_cm7.h **** #endif 196:Drivers/CMSIS/Include/core_cm7.h **** 197:Drivers/CMSIS/Include/core_cm7.h **** #ifndef __ICACHE_PRESENT 198:Drivers/CMSIS/Include/core_cm7.h **** #define __ICACHE_PRESENT 0U 199:Drivers/CMSIS/Include/core_cm7.h **** #warning "__ICACHE_PRESENT not defined in device header file; using default!" 200:Drivers/CMSIS/Include/core_cm7.h **** #endif 201:Drivers/CMSIS/Include/core_cm7.h **** 202:Drivers/CMSIS/Include/core_cm7.h **** #ifndef __DCACHE_PRESENT ARM GAS /tmp/ccqopZd5.s page 5 203:Drivers/CMSIS/Include/core_cm7.h **** #define __DCACHE_PRESENT 0U 204:Drivers/CMSIS/Include/core_cm7.h **** #warning "__DCACHE_PRESENT not defined in device header file; using default!" 205:Drivers/CMSIS/Include/core_cm7.h **** #endif 206:Drivers/CMSIS/Include/core_cm7.h **** 207:Drivers/CMSIS/Include/core_cm7.h **** #ifndef __DTCM_PRESENT 208:Drivers/CMSIS/Include/core_cm7.h **** #define __DTCM_PRESENT 0U 209:Drivers/CMSIS/Include/core_cm7.h **** #warning "__DTCM_PRESENT not defined in device header file; using default!" 210:Drivers/CMSIS/Include/core_cm7.h **** #endif 211:Drivers/CMSIS/Include/core_cm7.h **** 212:Drivers/CMSIS/Include/core_cm7.h **** #ifndef __NVIC_PRIO_BITS 213:Drivers/CMSIS/Include/core_cm7.h **** #define __NVIC_PRIO_BITS 3U 214:Drivers/CMSIS/Include/core_cm7.h **** #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" 215:Drivers/CMSIS/Include/core_cm7.h **** #endif 216:Drivers/CMSIS/Include/core_cm7.h **** 217:Drivers/CMSIS/Include/core_cm7.h **** #ifndef __Vendor_SysTickConfig 218:Drivers/CMSIS/Include/core_cm7.h **** #define __Vendor_SysTickConfig 0U 219:Drivers/CMSIS/Include/core_cm7.h **** #warning "__Vendor_SysTickConfig not defined in device header file; using default!" 220:Drivers/CMSIS/Include/core_cm7.h **** #endif 221:Drivers/CMSIS/Include/core_cm7.h **** #endif 222:Drivers/CMSIS/Include/core_cm7.h **** 223:Drivers/CMSIS/Include/core_cm7.h **** /* IO definitions (access restrictions to peripheral registers) */ 224:Drivers/CMSIS/Include/core_cm7.h **** /** 225:Drivers/CMSIS/Include/core_cm7.h **** \defgroup CMSIS_glob_defs CMSIS Global Defines 226:Drivers/CMSIS/Include/core_cm7.h **** 227:Drivers/CMSIS/Include/core_cm7.h **** IO Type Qualifiers are used 228:Drivers/CMSIS/Include/core_cm7.h **** \li to specify the access to peripheral variables. 229:Drivers/CMSIS/Include/core_cm7.h **** \li for automatic generation of peripheral register debug information. 230:Drivers/CMSIS/Include/core_cm7.h **** */ 231:Drivers/CMSIS/Include/core_cm7.h **** #ifdef __cplusplus 232:Drivers/CMSIS/Include/core_cm7.h **** #define __I volatile /*!< Defines 'read only' permissions */ 233:Drivers/CMSIS/Include/core_cm7.h **** #else 234:Drivers/CMSIS/Include/core_cm7.h **** #define __I volatile const /*!< Defines 'read only' permissions */ 235:Drivers/CMSIS/Include/core_cm7.h **** #endif 236:Drivers/CMSIS/Include/core_cm7.h **** #define __O volatile /*!< Defines 'write only' permissions */ 237:Drivers/CMSIS/Include/core_cm7.h **** #define __IO volatile /*!< Defines 'read / write' permissions */ 238:Drivers/CMSIS/Include/core_cm7.h **** 239:Drivers/CMSIS/Include/core_cm7.h **** /* following defines should be used for structure members */ 240:Drivers/CMSIS/Include/core_cm7.h **** #define __IM volatile const /*! Defines 'read only' structure member permissions */ 241:Drivers/CMSIS/Include/core_cm7.h **** #define __OM volatile /*! Defines 'write only' structure member permissions */ 242:Drivers/CMSIS/Include/core_cm7.h **** #define __IOM volatile /*! Defines 'read / write' structure member permissions */ 243:Drivers/CMSIS/Include/core_cm7.h **** 244:Drivers/CMSIS/Include/core_cm7.h **** /*@} end of group Cortex_M7 */ 245:Drivers/CMSIS/Include/core_cm7.h **** 246:Drivers/CMSIS/Include/core_cm7.h **** 247:Drivers/CMSIS/Include/core_cm7.h **** 248:Drivers/CMSIS/Include/core_cm7.h **** /******************************************************************************* 249:Drivers/CMSIS/Include/core_cm7.h **** * Register Abstraction 250:Drivers/CMSIS/Include/core_cm7.h **** Core Register contain: 251:Drivers/CMSIS/Include/core_cm7.h **** - Core Register 252:Drivers/CMSIS/Include/core_cm7.h **** - Core NVIC Register 253:Drivers/CMSIS/Include/core_cm7.h **** - Core SCB Register 254:Drivers/CMSIS/Include/core_cm7.h **** - Core SysTick Register 255:Drivers/CMSIS/Include/core_cm7.h **** - Core Debug Register 256:Drivers/CMSIS/Include/core_cm7.h **** - Core MPU Register 257:Drivers/CMSIS/Include/core_cm7.h **** - Core FPU Register 258:Drivers/CMSIS/Include/core_cm7.h **** ******************************************************************************/ 259:Drivers/CMSIS/Include/core_cm7.h **** /** ARM GAS /tmp/ccqopZd5.s page 6 260:Drivers/CMSIS/Include/core_cm7.h **** \defgroup CMSIS_core_register Defines and Type Definitions 261:Drivers/CMSIS/Include/core_cm7.h **** \brief Type definitions and defines for Cortex-M processor based devices. 262:Drivers/CMSIS/Include/core_cm7.h **** */ 263:Drivers/CMSIS/Include/core_cm7.h **** 264:Drivers/CMSIS/Include/core_cm7.h **** /** 265:Drivers/CMSIS/Include/core_cm7.h **** \ingroup CMSIS_core_register 266:Drivers/CMSIS/Include/core_cm7.h **** \defgroup CMSIS_CORE Status and Control Registers 267:Drivers/CMSIS/Include/core_cm7.h **** \brief Core Register type definitions. 268:Drivers/CMSIS/Include/core_cm7.h **** @{ 269:Drivers/CMSIS/Include/core_cm7.h **** */ 270:Drivers/CMSIS/Include/core_cm7.h **** 271:Drivers/CMSIS/Include/core_cm7.h **** /** 272:Drivers/CMSIS/Include/core_cm7.h **** \brief Union type to access the Application Program Status Register (APSR). 273:Drivers/CMSIS/Include/core_cm7.h **** */ 274:Drivers/CMSIS/Include/core_cm7.h **** typedef union 275:Drivers/CMSIS/Include/core_cm7.h **** { 276:Drivers/CMSIS/Include/core_cm7.h **** struct 277:Drivers/CMSIS/Include/core_cm7.h **** { 278:Drivers/CMSIS/Include/core_cm7.h **** uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ 279:Drivers/CMSIS/Include/core_cm7.h **** uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ 280:Drivers/CMSIS/Include/core_cm7.h **** uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ 281:Drivers/CMSIS/Include/core_cm7.h **** uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ 282:Drivers/CMSIS/Include/core_cm7.h **** uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ 283:Drivers/CMSIS/Include/core_cm7.h **** uint32_t C:1; /*!< bit: 29 Carry condition code flag */ 284:Drivers/CMSIS/Include/core_cm7.h **** uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ 285:Drivers/CMSIS/Include/core_cm7.h **** uint32_t N:1; /*!< bit: 31 Negative condition code flag */ 286:Drivers/CMSIS/Include/core_cm7.h **** } b; /*!< Structure used for bit access */ 287:Drivers/CMSIS/Include/core_cm7.h **** uint32_t w; /*!< Type used for word access */ 288:Drivers/CMSIS/Include/core_cm7.h **** } APSR_Type; 289:Drivers/CMSIS/Include/core_cm7.h **** 290:Drivers/CMSIS/Include/core_cm7.h **** /* APSR Register Definitions */ 291:Drivers/CMSIS/Include/core_cm7.h **** #define APSR_N_Pos 31U /*!< APSR 292:Drivers/CMSIS/Include/core_cm7.h **** #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR 293:Drivers/CMSIS/Include/core_cm7.h **** 294:Drivers/CMSIS/Include/core_cm7.h **** #define APSR_Z_Pos 30U /*!< APSR 295:Drivers/CMSIS/Include/core_cm7.h **** #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR 296:Drivers/CMSIS/Include/core_cm7.h **** 297:Drivers/CMSIS/Include/core_cm7.h **** #define APSR_C_Pos 29U /*!< APSR 298:Drivers/CMSIS/Include/core_cm7.h **** #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR 299:Drivers/CMSIS/Include/core_cm7.h **** 300:Drivers/CMSIS/Include/core_cm7.h **** #define APSR_V_Pos 28U /*!< APSR 301:Drivers/CMSIS/Include/core_cm7.h **** #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR 302:Drivers/CMSIS/Include/core_cm7.h **** 303:Drivers/CMSIS/Include/core_cm7.h **** #define APSR_Q_Pos 27U /*!< APSR 304:Drivers/CMSIS/Include/core_cm7.h **** #define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR 305:Drivers/CMSIS/Include/core_cm7.h **** 306:Drivers/CMSIS/Include/core_cm7.h **** #define APSR_GE_Pos 16U /*!< APSR 307:Drivers/CMSIS/Include/core_cm7.h **** #define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR 308:Drivers/CMSIS/Include/core_cm7.h **** 309:Drivers/CMSIS/Include/core_cm7.h **** 310:Drivers/CMSIS/Include/core_cm7.h **** /** 311:Drivers/CMSIS/Include/core_cm7.h **** \brief Union type to access the Interrupt Program Status Register (IPSR). 312:Drivers/CMSIS/Include/core_cm7.h **** */ 313:Drivers/CMSIS/Include/core_cm7.h **** typedef union 314:Drivers/CMSIS/Include/core_cm7.h **** { 315:Drivers/CMSIS/Include/core_cm7.h **** struct 316:Drivers/CMSIS/Include/core_cm7.h **** { ARM GAS /tmp/ccqopZd5.s page 7 317:Drivers/CMSIS/Include/core_cm7.h **** uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ 318:Drivers/CMSIS/Include/core_cm7.h **** uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ 319:Drivers/CMSIS/Include/core_cm7.h **** } b; /*!< Structure used for bit access */ 320:Drivers/CMSIS/Include/core_cm7.h **** uint32_t w; /*!< Type used for word access */ 321:Drivers/CMSIS/Include/core_cm7.h **** } IPSR_Type; 322:Drivers/CMSIS/Include/core_cm7.h **** 323:Drivers/CMSIS/Include/core_cm7.h **** /* IPSR Register Definitions */ 324:Drivers/CMSIS/Include/core_cm7.h **** #define IPSR_ISR_Pos 0U /*!< IPSR 325:Drivers/CMSIS/Include/core_cm7.h **** #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR 326:Drivers/CMSIS/Include/core_cm7.h **** 327:Drivers/CMSIS/Include/core_cm7.h **** 328:Drivers/CMSIS/Include/core_cm7.h **** /** 329:Drivers/CMSIS/Include/core_cm7.h **** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). 330:Drivers/CMSIS/Include/core_cm7.h **** */ 331:Drivers/CMSIS/Include/core_cm7.h **** typedef union 332:Drivers/CMSIS/Include/core_cm7.h **** { 333:Drivers/CMSIS/Include/core_cm7.h **** struct 334:Drivers/CMSIS/Include/core_cm7.h **** { 335:Drivers/CMSIS/Include/core_cm7.h **** uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ 336:Drivers/CMSIS/Include/core_cm7.h **** uint32_t _reserved0:1; /*!< bit: 9 Reserved */ 337:Drivers/CMSIS/Include/core_cm7.h **** uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ 338:Drivers/CMSIS/Include/core_cm7.h **** uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ 339:Drivers/CMSIS/Include/core_cm7.h **** uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ 340:Drivers/CMSIS/Include/core_cm7.h **** uint32_t T:1; /*!< bit: 24 Thumb bit */ 341:Drivers/CMSIS/Include/core_cm7.h **** uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ 342:Drivers/CMSIS/Include/core_cm7.h **** uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ 343:Drivers/CMSIS/Include/core_cm7.h **** uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ 344:Drivers/CMSIS/Include/core_cm7.h **** uint32_t C:1; /*!< bit: 29 Carry condition code flag */ 345:Drivers/CMSIS/Include/core_cm7.h **** uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ 346:Drivers/CMSIS/Include/core_cm7.h **** uint32_t N:1; /*!< bit: 31 Negative condition code flag */ 347:Drivers/CMSIS/Include/core_cm7.h **** } b; /*!< Structure used for bit access */ 348:Drivers/CMSIS/Include/core_cm7.h **** uint32_t w; /*!< Type used for word access */ 349:Drivers/CMSIS/Include/core_cm7.h **** } xPSR_Type; 350:Drivers/CMSIS/Include/core_cm7.h **** 351:Drivers/CMSIS/Include/core_cm7.h **** /* xPSR Register Definitions */ 352:Drivers/CMSIS/Include/core_cm7.h **** #define xPSR_N_Pos 31U /*!< xPSR 353:Drivers/CMSIS/Include/core_cm7.h **** #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR 354:Drivers/CMSIS/Include/core_cm7.h **** 355:Drivers/CMSIS/Include/core_cm7.h **** #define xPSR_Z_Pos 30U /*!< xPSR 356:Drivers/CMSIS/Include/core_cm7.h **** #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR 357:Drivers/CMSIS/Include/core_cm7.h **** 358:Drivers/CMSIS/Include/core_cm7.h **** #define xPSR_C_Pos 29U /*!< xPSR 359:Drivers/CMSIS/Include/core_cm7.h **** #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR 360:Drivers/CMSIS/Include/core_cm7.h **** 361:Drivers/CMSIS/Include/core_cm7.h **** #define xPSR_V_Pos 28U /*!< xPSR 362:Drivers/CMSIS/Include/core_cm7.h **** #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR 363:Drivers/CMSIS/Include/core_cm7.h **** 364:Drivers/CMSIS/Include/core_cm7.h **** #define xPSR_Q_Pos 27U /*!< xPSR 365:Drivers/CMSIS/Include/core_cm7.h **** #define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR 366:Drivers/CMSIS/Include/core_cm7.h **** 367:Drivers/CMSIS/Include/core_cm7.h **** #define xPSR_ICI_IT_2_Pos 25U /*!< xPSR 368:Drivers/CMSIS/Include/core_cm7.h **** #define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR 369:Drivers/CMSIS/Include/core_cm7.h **** 370:Drivers/CMSIS/Include/core_cm7.h **** #define xPSR_T_Pos 24U /*!< xPSR 371:Drivers/CMSIS/Include/core_cm7.h **** #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR 372:Drivers/CMSIS/Include/core_cm7.h **** 373:Drivers/CMSIS/Include/core_cm7.h **** #define xPSR_GE_Pos 16U /*!< xPSR ARM GAS /tmp/ccqopZd5.s page 8 374:Drivers/CMSIS/Include/core_cm7.h **** #define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR 375:Drivers/CMSIS/Include/core_cm7.h **** 376:Drivers/CMSIS/Include/core_cm7.h **** #define xPSR_ICI_IT_1_Pos 10U /*!< xPSR 377:Drivers/CMSIS/Include/core_cm7.h **** #define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR 378:Drivers/CMSIS/Include/core_cm7.h **** 379:Drivers/CMSIS/Include/core_cm7.h **** #define xPSR_ISR_Pos 0U /*!< xPSR 380:Drivers/CMSIS/Include/core_cm7.h **** #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR 381:Drivers/CMSIS/Include/core_cm7.h **** 382:Drivers/CMSIS/Include/core_cm7.h **** 383:Drivers/CMSIS/Include/core_cm7.h **** /** 384:Drivers/CMSIS/Include/core_cm7.h **** \brief Union type to access the Control Registers (CONTROL). 385:Drivers/CMSIS/Include/core_cm7.h **** */ 386:Drivers/CMSIS/Include/core_cm7.h **** typedef union 387:Drivers/CMSIS/Include/core_cm7.h **** { 388:Drivers/CMSIS/Include/core_cm7.h **** struct 389:Drivers/CMSIS/Include/core_cm7.h **** { 390:Drivers/CMSIS/Include/core_cm7.h **** uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ 391:Drivers/CMSIS/Include/core_cm7.h **** uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ 392:Drivers/CMSIS/Include/core_cm7.h **** uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ 393:Drivers/CMSIS/Include/core_cm7.h **** uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ 394:Drivers/CMSIS/Include/core_cm7.h **** } b; /*!< Structure used for bit access */ 395:Drivers/CMSIS/Include/core_cm7.h **** uint32_t w; /*!< Type used for word access */ 396:Drivers/CMSIS/Include/core_cm7.h **** } CONTROL_Type; 397:Drivers/CMSIS/Include/core_cm7.h **** 398:Drivers/CMSIS/Include/core_cm7.h **** /* CONTROL Register Definitions */ 399:Drivers/CMSIS/Include/core_cm7.h **** #define CONTROL_FPCA_Pos 2U /*!< CONT 400:Drivers/CMSIS/Include/core_cm7.h **** #define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONT 401:Drivers/CMSIS/Include/core_cm7.h **** 402:Drivers/CMSIS/Include/core_cm7.h **** #define CONTROL_SPSEL_Pos 1U /*!< CONT 403:Drivers/CMSIS/Include/core_cm7.h **** #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONT 404:Drivers/CMSIS/Include/core_cm7.h **** 405:Drivers/CMSIS/Include/core_cm7.h **** #define CONTROL_nPRIV_Pos 0U /*!< CONT 406:Drivers/CMSIS/Include/core_cm7.h **** #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONT 407:Drivers/CMSIS/Include/core_cm7.h **** 408:Drivers/CMSIS/Include/core_cm7.h **** /*@} end of group CMSIS_CORE */ 409:Drivers/CMSIS/Include/core_cm7.h **** 410:Drivers/CMSIS/Include/core_cm7.h **** 411:Drivers/CMSIS/Include/core_cm7.h **** /** 412:Drivers/CMSIS/Include/core_cm7.h **** \ingroup CMSIS_core_register 413:Drivers/CMSIS/Include/core_cm7.h **** \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) 414:Drivers/CMSIS/Include/core_cm7.h **** \brief Type definitions for the NVIC Registers 415:Drivers/CMSIS/Include/core_cm7.h **** @{ 416:Drivers/CMSIS/Include/core_cm7.h **** */ 417:Drivers/CMSIS/Include/core_cm7.h **** 418:Drivers/CMSIS/Include/core_cm7.h **** /** 419:Drivers/CMSIS/Include/core_cm7.h **** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). 420:Drivers/CMSIS/Include/core_cm7.h **** */ 421:Drivers/CMSIS/Include/core_cm7.h **** typedef struct 422:Drivers/CMSIS/Include/core_cm7.h **** { 423:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ 424:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED0[24U]; 425:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register 426:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RSERVED1[24U]; 427:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register * 428:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED2[24U]; 429:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register 430:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED3[24U]; ARM GAS /tmp/ccqopZd5.s page 9 431:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ 432:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED4[56U]; 433:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bi 434:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED5[644U]; 435:Drivers/CMSIS/Include/core_cm7.h **** __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Regis 436:Drivers/CMSIS/Include/core_cm7.h **** } NVIC_Type; 437:Drivers/CMSIS/Include/core_cm7.h **** 438:Drivers/CMSIS/Include/core_cm7.h **** /* Software Triggered Interrupt Register Definitions */ 439:Drivers/CMSIS/Include/core_cm7.h **** #define NVIC_STIR_INTID_Pos 0U /*!< STIR: I 440:Drivers/CMSIS/Include/core_cm7.h **** #define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: I 441:Drivers/CMSIS/Include/core_cm7.h **** 442:Drivers/CMSIS/Include/core_cm7.h **** /*@} end of group CMSIS_NVIC */ 443:Drivers/CMSIS/Include/core_cm7.h **** 444:Drivers/CMSIS/Include/core_cm7.h **** 445:Drivers/CMSIS/Include/core_cm7.h **** /** 446:Drivers/CMSIS/Include/core_cm7.h **** \ingroup CMSIS_core_register 447:Drivers/CMSIS/Include/core_cm7.h **** \defgroup CMSIS_SCB System Control Block (SCB) 448:Drivers/CMSIS/Include/core_cm7.h **** \brief Type definitions for the System Control Block Registers 449:Drivers/CMSIS/Include/core_cm7.h **** @{ 450:Drivers/CMSIS/Include/core_cm7.h **** */ 451:Drivers/CMSIS/Include/core_cm7.h **** 452:Drivers/CMSIS/Include/core_cm7.h **** /** 453:Drivers/CMSIS/Include/core_cm7.h **** \brief Structure type to access the System Control Block (SCB). 454:Drivers/CMSIS/Include/core_cm7.h **** */ 455:Drivers/CMSIS/Include/core_cm7.h **** typedef struct 456:Drivers/CMSIS/Include/core_cm7.h **** { 457:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ 458:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Regi 459:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ 460:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset 461:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ 462:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register * 463:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registe 464:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State 465:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Regist 466:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ 467:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ 468:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register 469:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ 470:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register 471:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ 472:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ 473:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ 474:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t ID_MFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ 475:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t ID_ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Regis 476:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED0[1U]; 477:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ 478:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ 479:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ 480:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ 481:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Regis 482:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED3[93U]; 483:Drivers/CMSIS/Include/core_cm7.h **** __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Reg 484:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED4[15U]; 485:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 486:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 487:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 ARM GAS /tmp/ccqopZd5.s page 10 488:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED5[1U]; 489:Drivers/CMSIS/Include/core_cm7.h **** __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ 490:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED6[1U]; 491:Drivers/CMSIS/Include/core_cm7.h **** __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU 492:Drivers/CMSIS/Include/core_cm7.h **** __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC 493:Drivers/CMSIS/Include/core_cm7.h **** __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ 494:Drivers/CMSIS/Include/core_cm7.h **** __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ 495:Drivers/CMSIS/Include/core_cm7.h **** __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ 496:Drivers/CMSIS/Include/core_cm7.h **** __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ 497:Drivers/CMSIS/Include/core_cm7.h **** __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by 498:Drivers/CMSIS/Include/core_cm7.h **** __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by 499:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED7[6U]; 500:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memo 501:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Cont 502:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ 503:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ 504:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ 505:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED8[1U]; 506:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Regis 507:Drivers/CMSIS/Include/core_cm7.h **** } SCB_Type; 508:Drivers/CMSIS/Include/core_cm7.h **** 509:Drivers/CMSIS/Include/core_cm7.h **** /* SCB CPUID Register Definitions */ 510:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB 511:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB 512:Drivers/CMSIS/Include/core_cm7.h **** 513:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB 514:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB 515:Drivers/CMSIS/Include/core_cm7.h **** 516:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB 517:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB 518:Drivers/CMSIS/Include/core_cm7.h **** 519:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB 520:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB 521:Drivers/CMSIS/Include/core_cm7.h **** 522:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CPUID_REVISION_Pos 0U /*!< SCB 523:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB 524:Drivers/CMSIS/Include/core_cm7.h **** 525:Drivers/CMSIS/Include/core_cm7.h **** /* SCB Interrupt Control State Register Definitions */ 526:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB 527:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB 528:Drivers/CMSIS/Include/core_cm7.h **** 529:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB 530:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB 531:Drivers/CMSIS/Include/core_cm7.h **** 532:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB 533:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB 534:Drivers/CMSIS/Include/core_cm7.h **** 535:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB 536:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB 537:Drivers/CMSIS/Include/core_cm7.h **** 538:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB 539:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB 540:Drivers/CMSIS/Include/core_cm7.h **** 541:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB 542:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB 543:Drivers/CMSIS/Include/core_cm7.h **** 544:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ARM GAS /tmp/ccqopZd5.s page 11 545:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB 546:Drivers/CMSIS/Include/core_cm7.h **** 547:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB 548:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB 549:Drivers/CMSIS/Include/core_cm7.h **** 550:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB 551:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB 552:Drivers/CMSIS/Include/core_cm7.h **** 553:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB 554:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB 555:Drivers/CMSIS/Include/core_cm7.h **** 556:Drivers/CMSIS/Include/core_cm7.h **** /* SCB Vector Table Offset Register Definitions */ 557:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB 558:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB 559:Drivers/CMSIS/Include/core_cm7.h **** 560:Drivers/CMSIS/Include/core_cm7.h **** /* SCB Application Interrupt and Reset Control Register Definitions */ 561:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB 562:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB 563:Drivers/CMSIS/Include/core_cm7.h **** 564:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB 565:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB 566:Drivers/CMSIS/Include/core_cm7.h **** 567:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB 568:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB 569:Drivers/CMSIS/Include/core_cm7.h **** 570:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB 571:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB 572:Drivers/CMSIS/Include/core_cm7.h **** 573:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB 574:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB 575:Drivers/CMSIS/Include/core_cm7.h **** 576:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB 577:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB 578:Drivers/CMSIS/Include/core_cm7.h **** 579:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB 580:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB 581:Drivers/CMSIS/Include/core_cm7.h **** 582:Drivers/CMSIS/Include/core_cm7.h **** /* SCB System Control Register Definitions */ 583:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB 584:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB 585:Drivers/CMSIS/Include/core_cm7.h **** 586:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB 587:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB 588:Drivers/CMSIS/Include/core_cm7.h **** 589:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB 590:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB 591:Drivers/CMSIS/Include/core_cm7.h **** 592:Drivers/CMSIS/Include/core_cm7.h **** /* SCB Configuration Control Register Definitions */ 593:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCR_BP_Pos 18U /*!< SCB 594:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB 595:Drivers/CMSIS/Include/core_cm7.h **** 596:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCR_IC_Pos 17U /*!< SCB 597:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB 598:Drivers/CMSIS/Include/core_cm7.h **** 599:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCR_DC_Pos 16U /*!< SCB 600:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB 601:Drivers/CMSIS/Include/core_cm7.h **** ARM GAS /tmp/ccqopZd5.s page 12 602:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCR_STKALIGN_Pos 9U /*!< SCB 603:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB 604:Drivers/CMSIS/Include/core_cm7.h **** 605:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB 606:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB 607:Drivers/CMSIS/Include/core_cm7.h **** 608:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB 609:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB 610:Drivers/CMSIS/Include/core_cm7.h **** 611:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB 612:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB 613:Drivers/CMSIS/Include/core_cm7.h **** 614:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB 615:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB 616:Drivers/CMSIS/Include/core_cm7.h **** 617:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB 618:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB 619:Drivers/CMSIS/Include/core_cm7.h **** 620:Drivers/CMSIS/Include/core_cm7.h **** /* SCB System Handler Control and State Register Definitions */ 621:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB 622:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB 623:Drivers/CMSIS/Include/core_cm7.h **** 624:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB 625:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB 626:Drivers/CMSIS/Include/core_cm7.h **** 627:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB 628:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB 629:Drivers/CMSIS/Include/core_cm7.h **** 630:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB 631:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB 632:Drivers/CMSIS/Include/core_cm7.h **** 633:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB 634:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB 635:Drivers/CMSIS/Include/core_cm7.h **** 636:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB 637:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB 638:Drivers/CMSIS/Include/core_cm7.h **** 639:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB 640:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB 641:Drivers/CMSIS/Include/core_cm7.h **** 642:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB 643:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB 644:Drivers/CMSIS/Include/core_cm7.h **** 645:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB 646:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB 647:Drivers/CMSIS/Include/core_cm7.h **** 648:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB 649:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB 650:Drivers/CMSIS/Include/core_cm7.h **** 651:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB 652:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB 653:Drivers/CMSIS/Include/core_cm7.h **** 654:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB 655:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB 656:Drivers/CMSIS/Include/core_cm7.h **** 657:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB 658:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB ARM GAS /tmp/ccqopZd5.s page 13 659:Drivers/CMSIS/Include/core_cm7.h **** 660:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB 661:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB 662:Drivers/CMSIS/Include/core_cm7.h **** 663:Drivers/CMSIS/Include/core_cm7.h **** /* SCB Configurable Fault Status Register Definitions */ 664:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB 665:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB 666:Drivers/CMSIS/Include/core_cm7.h **** 667:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB 668:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB 669:Drivers/CMSIS/Include/core_cm7.h **** 670:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB 671:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB 672:Drivers/CMSIS/Include/core_cm7.h **** 673:Drivers/CMSIS/Include/core_cm7.h **** /* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ 674:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB 675:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB 676:Drivers/CMSIS/Include/core_cm7.h **** 677:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB 678:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB 679:Drivers/CMSIS/Include/core_cm7.h **** 680:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB 681:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB 682:Drivers/CMSIS/Include/core_cm7.h **** 683:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB 684:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB 685:Drivers/CMSIS/Include/core_cm7.h **** 686:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB 687:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB 688:Drivers/CMSIS/Include/core_cm7.h **** 689:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB 690:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB 691:Drivers/CMSIS/Include/core_cm7.h **** 692:Drivers/CMSIS/Include/core_cm7.h **** /* BusFault Status Register (part of SCB Configurable Fault Status Register) */ 693:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB 694:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB 695:Drivers/CMSIS/Include/core_cm7.h **** 696:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB 697:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB 698:Drivers/CMSIS/Include/core_cm7.h **** 699:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB 700:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB 701:Drivers/CMSIS/Include/core_cm7.h **** 702:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB 703:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB 704:Drivers/CMSIS/Include/core_cm7.h **** 705:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB 706:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB 707:Drivers/CMSIS/Include/core_cm7.h **** 708:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB 709:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB 710:Drivers/CMSIS/Include/core_cm7.h **** 711:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB 712:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB 713:Drivers/CMSIS/Include/core_cm7.h **** 714:Drivers/CMSIS/Include/core_cm7.h **** /* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ 715:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB ARM GAS /tmp/ccqopZd5.s page 14 716:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB 717:Drivers/CMSIS/Include/core_cm7.h **** 718:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB 719:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB 720:Drivers/CMSIS/Include/core_cm7.h **** 721:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB 722:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB 723:Drivers/CMSIS/Include/core_cm7.h **** 724:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB 725:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB 726:Drivers/CMSIS/Include/core_cm7.h **** 727:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB 728:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB 729:Drivers/CMSIS/Include/core_cm7.h **** 730:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB 731:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB 732:Drivers/CMSIS/Include/core_cm7.h **** 733:Drivers/CMSIS/Include/core_cm7.h **** /* SCB Hard Fault Status Register Definitions */ 734:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB 735:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB 736:Drivers/CMSIS/Include/core_cm7.h **** 737:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_HFSR_FORCED_Pos 30U /*!< SCB 738:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB 739:Drivers/CMSIS/Include/core_cm7.h **** 740:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB 741:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB 742:Drivers/CMSIS/Include/core_cm7.h **** 743:Drivers/CMSIS/Include/core_cm7.h **** /* SCB Debug Fault Status Register Definitions */ 744:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB 745:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB 746:Drivers/CMSIS/Include/core_cm7.h **** 747:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DFSR_VCATCH_Pos 3U /*!< SCB 748:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB 749:Drivers/CMSIS/Include/core_cm7.h **** 750:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB 751:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB 752:Drivers/CMSIS/Include/core_cm7.h **** 753:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DFSR_BKPT_Pos 1U /*!< SCB 754:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB 755:Drivers/CMSIS/Include/core_cm7.h **** 756:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DFSR_HALTED_Pos 0U /*!< SCB 757:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB 758:Drivers/CMSIS/Include/core_cm7.h **** 759:Drivers/CMSIS/Include/core_cm7.h **** /* SCB Cache Level ID Register Definitions */ 760:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CLIDR_LOUU_Pos 27U /*!< SCB 761:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB 762:Drivers/CMSIS/Include/core_cm7.h **** 763:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CLIDR_LOC_Pos 24U /*!< SCB 764:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB 765:Drivers/CMSIS/Include/core_cm7.h **** 766:Drivers/CMSIS/Include/core_cm7.h **** /* SCB Cache Type Register Definitions */ 767:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CTR_FORMAT_Pos 29U /*!< SCB 768:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB 769:Drivers/CMSIS/Include/core_cm7.h **** 770:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CTR_CWG_Pos 24U /*!< SCB 771:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB 772:Drivers/CMSIS/Include/core_cm7.h **** ARM GAS /tmp/ccqopZd5.s page 15 773:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CTR_ERG_Pos 20U /*!< SCB 774:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB 775:Drivers/CMSIS/Include/core_cm7.h **** 776:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CTR_DMINLINE_Pos 16U /*!< SCB 777:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB 778:Drivers/CMSIS/Include/core_cm7.h **** 779:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CTR_IMINLINE_Pos 0U /*!< SCB 780:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB 781:Drivers/CMSIS/Include/core_cm7.h **** 782:Drivers/CMSIS/Include/core_cm7.h **** /* SCB Cache Size ID Register Definitions */ 783:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCSIDR_WT_Pos 31U /*!< SCB 784:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB 785:Drivers/CMSIS/Include/core_cm7.h **** 786:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCSIDR_WB_Pos 30U /*!< SCB 787:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB 788:Drivers/CMSIS/Include/core_cm7.h **** 789:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCSIDR_RA_Pos 29U /*!< SCB 790:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB 791:Drivers/CMSIS/Include/core_cm7.h **** 792:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCSIDR_WA_Pos 28U /*!< SCB 793:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB 794:Drivers/CMSIS/Include/core_cm7.h **** 795:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB 796:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB 797:Drivers/CMSIS/Include/core_cm7.h **** 798:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB 799:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB 800:Drivers/CMSIS/Include/core_cm7.h **** 801:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB 802:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB 803:Drivers/CMSIS/Include/core_cm7.h **** 804:Drivers/CMSIS/Include/core_cm7.h **** /* SCB Cache Size Selection Register Definitions */ 805:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB 806:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB 807:Drivers/CMSIS/Include/core_cm7.h **** 808:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CSSELR_IND_Pos 0U /*!< SCB 809:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB 810:Drivers/CMSIS/Include/core_cm7.h **** 811:Drivers/CMSIS/Include/core_cm7.h **** /* SCB Software Triggered Interrupt Register Definitions */ 812:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_STIR_INTID_Pos 0U /*!< SCB 813:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB 814:Drivers/CMSIS/Include/core_cm7.h **** 815:Drivers/CMSIS/Include/core_cm7.h **** /* SCB D-Cache Invalidate by Set-way Register Definitions */ 816:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DCISW_WAY_Pos 30U /*!< SCB 817:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB 818:Drivers/CMSIS/Include/core_cm7.h **** 819:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DCISW_SET_Pos 5U /*!< SCB 820:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB 821:Drivers/CMSIS/Include/core_cm7.h **** 822:Drivers/CMSIS/Include/core_cm7.h **** /* SCB D-Cache Clean by Set-way Register Definitions */ 823:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DCCSW_WAY_Pos 30U /*!< SCB 824:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB 825:Drivers/CMSIS/Include/core_cm7.h **** 826:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DCCSW_SET_Pos 5U /*!< SCB 827:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB 828:Drivers/CMSIS/Include/core_cm7.h **** 829:Drivers/CMSIS/Include/core_cm7.h **** /* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ ARM GAS /tmp/ccqopZd5.s page 16 830:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DCCISW_WAY_Pos 30U /*!< SCB 831:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB 832:Drivers/CMSIS/Include/core_cm7.h **** 833:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DCCISW_SET_Pos 5U /*!< SCB 834:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB 835:Drivers/CMSIS/Include/core_cm7.h **** 836:Drivers/CMSIS/Include/core_cm7.h **** /* Instruction Tightly-Coupled Memory Control Register Definitions */ 837:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ITCMCR_SZ_Pos 3U /*!< SCB 838:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB 839:Drivers/CMSIS/Include/core_cm7.h **** 840:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB 841:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB 842:Drivers/CMSIS/Include/core_cm7.h **** 843:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ITCMCR_RMW_Pos 1U /*!< SCB 844:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB 845:Drivers/CMSIS/Include/core_cm7.h **** 846:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ITCMCR_EN_Pos 0U /*!< SCB 847:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB 848:Drivers/CMSIS/Include/core_cm7.h **** 849:Drivers/CMSIS/Include/core_cm7.h **** /* Data Tightly-Coupled Memory Control Register Definitions */ 850:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DTCMCR_SZ_Pos 3U /*!< SCB 851:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB 852:Drivers/CMSIS/Include/core_cm7.h **** 853:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB 854:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB 855:Drivers/CMSIS/Include/core_cm7.h **** 856:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DTCMCR_RMW_Pos 1U /*!< SCB 857:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB 858:Drivers/CMSIS/Include/core_cm7.h **** 859:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DTCMCR_EN_Pos 0U /*!< SCB 860:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB 861:Drivers/CMSIS/Include/core_cm7.h **** 862:Drivers/CMSIS/Include/core_cm7.h **** /* AHBP Control Register Definitions */ 863:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AHBPCR_SZ_Pos 1U /*!< SCB 864:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB 865:Drivers/CMSIS/Include/core_cm7.h **** 866:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AHBPCR_EN_Pos 0U /*!< SCB 867:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB 868:Drivers/CMSIS/Include/core_cm7.h **** 869:Drivers/CMSIS/Include/core_cm7.h **** /* L1 Cache Control Register Definitions */ 870:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CACR_FORCEWT_Pos 2U /*!< SCB 871:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB 872:Drivers/CMSIS/Include/core_cm7.h **** 873:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CACR_ECCEN_Pos 1U /*!< SCB 874:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB 875:Drivers/CMSIS/Include/core_cm7.h **** 876:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CACR_SIWT_Pos 0U /*!< SCB 877:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB 878:Drivers/CMSIS/Include/core_cm7.h **** 879:Drivers/CMSIS/Include/core_cm7.h **** /* AHBS Control Register Definitions */ 880:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB 881:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB 882:Drivers/CMSIS/Include/core_cm7.h **** 883:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB 884:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB 885:Drivers/CMSIS/Include/core_cm7.h **** 886:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AHBSCR_CTL_Pos 0U /*!< SCB ARM GAS /tmp/ccqopZd5.s page 17 887:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB 888:Drivers/CMSIS/Include/core_cm7.h **** 889:Drivers/CMSIS/Include/core_cm7.h **** /* Auxiliary Bus Fault Status Register Definitions */ 890:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB 891:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB 892:Drivers/CMSIS/Include/core_cm7.h **** 893:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ABFSR_EPPB_Pos 4U /*!< SCB 894:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB 895:Drivers/CMSIS/Include/core_cm7.h **** 896:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ABFSR_AXIM_Pos 3U /*!< SCB 897:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB 898:Drivers/CMSIS/Include/core_cm7.h **** 899:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ABFSR_AHBP_Pos 2U /*!< SCB 900:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB 901:Drivers/CMSIS/Include/core_cm7.h **** 902:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ABFSR_DTCM_Pos 1U /*!< SCB 903:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB 904:Drivers/CMSIS/Include/core_cm7.h **** 905:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ABFSR_ITCM_Pos 0U /*!< SCB 906:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB 907:Drivers/CMSIS/Include/core_cm7.h **** 908:Drivers/CMSIS/Include/core_cm7.h **** /*@} end of group CMSIS_SCB */ 909:Drivers/CMSIS/Include/core_cm7.h **** 910:Drivers/CMSIS/Include/core_cm7.h **** 911:Drivers/CMSIS/Include/core_cm7.h **** /** 912:Drivers/CMSIS/Include/core_cm7.h **** \ingroup CMSIS_core_register 913:Drivers/CMSIS/Include/core_cm7.h **** \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) 914:Drivers/CMSIS/Include/core_cm7.h **** \brief Type definitions for the System Control and ID Register not in the SCB 915:Drivers/CMSIS/Include/core_cm7.h **** @{ 916:Drivers/CMSIS/Include/core_cm7.h **** */ 917:Drivers/CMSIS/Include/core_cm7.h **** 918:Drivers/CMSIS/Include/core_cm7.h **** /** 919:Drivers/CMSIS/Include/core_cm7.h **** \brief Structure type to access the System Control and ID Register not in the SCB. 920:Drivers/CMSIS/Include/core_cm7.h **** */ 921:Drivers/CMSIS/Include/core_cm7.h **** typedef struct 922:Drivers/CMSIS/Include/core_cm7.h **** { 923:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED0[1U]; 924:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Regist 925:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ 926:Drivers/CMSIS/Include/core_cm7.h **** } SCnSCB_Type; 927:Drivers/CMSIS/Include/core_cm7.h **** 928:Drivers/CMSIS/Include/core_cm7.h **** /* Interrupt Controller Type Register Definitions */ 929:Drivers/CMSIS/Include/core_cm7.h **** #define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: I 930:Drivers/CMSIS/Include/core_cm7.h **** #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: I 931:Drivers/CMSIS/Include/core_cm7.h **** 932:Drivers/CMSIS/Include/core_cm7.h **** /* Auxiliary Control Register Definitions */ 933:Drivers/CMSIS/Include/core_cm7.h **** #define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12U /*!< ACTLR: 934:Drivers/CMSIS/Include/core_cm7.h **** #define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: 935:Drivers/CMSIS/Include/core_cm7.h **** 936:Drivers/CMSIS/Include/core_cm7.h **** #define SCnSCB_ACTLR_DISRAMODE_Pos 11U /*!< ACTLR: 937:Drivers/CMSIS/Include/core_cm7.h **** #define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) /*!< ACTLR: 938:Drivers/CMSIS/Include/core_cm7.h **** 939:Drivers/CMSIS/Include/core_cm7.h **** #define SCnSCB_ACTLR_FPEXCODIS_Pos 10U /*!< ACTLR: 940:Drivers/CMSIS/Include/core_cm7.h **** #define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: 941:Drivers/CMSIS/Include/core_cm7.h **** 942:Drivers/CMSIS/Include/core_cm7.h **** #define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: 943:Drivers/CMSIS/Include/core_cm7.h **** #define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: ARM GAS /tmp/ccqopZd5.s page 18 944:Drivers/CMSIS/Include/core_cm7.h **** 945:Drivers/CMSIS/Include/core_cm7.h **** #define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: 946:Drivers/CMSIS/Include/core_cm7.h **** #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: 947:Drivers/CMSIS/Include/core_cm7.h **** 948:Drivers/CMSIS/Include/core_cm7.h **** /*@} end of group CMSIS_SCnotSCB */ 949:Drivers/CMSIS/Include/core_cm7.h **** 950:Drivers/CMSIS/Include/core_cm7.h **** 951:Drivers/CMSIS/Include/core_cm7.h **** /** 952:Drivers/CMSIS/Include/core_cm7.h **** \ingroup CMSIS_core_register 953:Drivers/CMSIS/Include/core_cm7.h **** \defgroup CMSIS_SysTick System Tick Timer (SysTick) 954:Drivers/CMSIS/Include/core_cm7.h **** \brief Type definitions for the System Timer Registers. 955:Drivers/CMSIS/Include/core_cm7.h **** @{ 956:Drivers/CMSIS/Include/core_cm7.h **** */ 957:Drivers/CMSIS/Include/core_cm7.h **** 958:Drivers/CMSIS/Include/core_cm7.h **** /** 959:Drivers/CMSIS/Include/core_cm7.h **** \brief Structure type to access the System Timer (SysTick). 960:Drivers/CMSIS/Include/core_cm7.h **** */ 961:Drivers/CMSIS/Include/core_cm7.h **** typedef struct 962:Drivers/CMSIS/Include/core_cm7.h **** { 963:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Regis 964:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ 965:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register * 966:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ 967:Drivers/CMSIS/Include/core_cm7.h **** } SysTick_Type; 968:Drivers/CMSIS/Include/core_cm7.h **** 969:Drivers/CMSIS/Include/core_cm7.h **** /* SysTick Control / Status Register Definitions */ 970:Drivers/CMSIS/Include/core_cm7.h **** #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysT 971:Drivers/CMSIS/Include/core_cm7.h **** #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysT 972:Drivers/CMSIS/Include/core_cm7.h **** 973:Drivers/CMSIS/Include/core_cm7.h **** #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysT 974:Drivers/CMSIS/Include/core_cm7.h **** #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysT 975:Drivers/CMSIS/Include/core_cm7.h **** 976:Drivers/CMSIS/Include/core_cm7.h **** #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysT 977:Drivers/CMSIS/Include/core_cm7.h **** #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysT 978:Drivers/CMSIS/Include/core_cm7.h **** 979:Drivers/CMSIS/Include/core_cm7.h **** #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysT 980:Drivers/CMSIS/Include/core_cm7.h **** #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysT 981:Drivers/CMSIS/Include/core_cm7.h **** 982:Drivers/CMSIS/Include/core_cm7.h **** /* SysTick Reload Register Definitions */ 983:Drivers/CMSIS/Include/core_cm7.h **** #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysT 984:Drivers/CMSIS/Include/core_cm7.h **** #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysT 985:Drivers/CMSIS/Include/core_cm7.h **** 986:Drivers/CMSIS/Include/core_cm7.h **** /* SysTick Current Register Definitions */ 987:Drivers/CMSIS/Include/core_cm7.h **** #define SysTick_VAL_CURRENT_Pos 0U /*!< SysT 988:Drivers/CMSIS/Include/core_cm7.h **** #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysT 989:Drivers/CMSIS/Include/core_cm7.h **** 990:Drivers/CMSIS/Include/core_cm7.h **** /* SysTick Calibration Register Definitions */ 991:Drivers/CMSIS/Include/core_cm7.h **** #define SysTick_CALIB_NOREF_Pos 31U /*!< SysT 992:Drivers/CMSIS/Include/core_cm7.h **** #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysT 993:Drivers/CMSIS/Include/core_cm7.h **** 994:Drivers/CMSIS/Include/core_cm7.h **** #define SysTick_CALIB_SKEW_Pos 30U /*!< SysT 995:Drivers/CMSIS/Include/core_cm7.h **** #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysT 996:Drivers/CMSIS/Include/core_cm7.h **** 997:Drivers/CMSIS/Include/core_cm7.h **** #define SysTick_CALIB_TENMS_Pos 0U /*!< SysT 998:Drivers/CMSIS/Include/core_cm7.h **** #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysT 999:Drivers/CMSIS/Include/core_cm7.h **** 1000:Drivers/CMSIS/Include/core_cm7.h **** /*@} end of group CMSIS_SysTick */ ARM GAS /tmp/ccqopZd5.s page 19 1001:Drivers/CMSIS/Include/core_cm7.h **** 1002:Drivers/CMSIS/Include/core_cm7.h **** 1003:Drivers/CMSIS/Include/core_cm7.h **** /** 1004:Drivers/CMSIS/Include/core_cm7.h **** \ingroup CMSIS_core_register 1005:Drivers/CMSIS/Include/core_cm7.h **** \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) 1006:Drivers/CMSIS/Include/core_cm7.h **** \brief Type definitions for the Instrumentation Trace Macrocell (ITM) 1007:Drivers/CMSIS/Include/core_cm7.h **** @{ 1008:Drivers/CMSIS/Include/core_cm7.h **** */ 1009:Drivers/CMSIS/Include/core_cm7.h **** 1010:Drivers/CMSIS/Include/core_cm7.h **** /** 1011:Drivers/CMSIS/Include/core_cm7.h **** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). 1012:Drivers/CMSIS/Include/core_cm7.h **** */ 1013:Drivers/CMSIS/Include/core_cm7.h **** typedef struct 1014:Drivers/CMSIS/Include/core_cm7.h **** { 1015:Drivers/CMSIS/Include/core_cm7.h **** __OM union 1016:Drivers/CMSIS/Include/core_cm7.h **** { 1017:Drivers/CMSIS/Include/core_cm7.h **** __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ 1018:Drivers/CMSIS/Include/core_cm7.h **** __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ 1019:Drivers/CMSIS/Include/core_cm7.h **** __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ 1020:Drivers/CMSIS/Include/core_cm7.h **** } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ 1021:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED0[864U]; 1022:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ 1023:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED1[15U]; 1024:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ 1025:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED2[15U]; 1026:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ 1027:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED3[29U]; 1028:Drivers/CMSIS/Include/core_cm7.h **** __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register * 1029:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ 1030:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Reg 1031:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED4[43U]; 1032:Drivers/CMSIS/Include/core_cm7.h **** __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ 1033:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ 1034:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED5[6U]; 1035:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Re 1036:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Re 1037:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Re 1038:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Re 1039:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Re 1040:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Re 1041:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Re 1042:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Re 1043:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Re 1044:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Re 1045:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Re 1046:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Re 1047:Drivers/CMSIS/Include/core_cm7.h **** } ITM_Type; 1048:Drivers/CMSIS/Include/core_cm7.h **** 1049:Drivers/CMSIS/Include/core_cm7.h **** /* ITM Trace Privilege Register Definitions */ 1050:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM 1051:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM 1052:Drivers/CMSIS/Include/core_cm7.h **** 1053:Drivers/CMSIS/Include/core_cm7.h **** /* ITM Trace Control Register Definitions */ 1054:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TCR_BUSY_Pos 23U /*!< ITM 1055:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM 1056:Drivers/CMSIS/Include/core_cm7.h **** 1057:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TCR_TraceBusID_Pos 16U /*!< ITM ARM GAS /tmp/ccqopZd5.s page 20 1058:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM 1059:Drivers/CMSIS/Include/core_cm7.h **** 1060:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM 1061:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM 1062:Drivers/CMSIS/Include/core_cm7.h **** 1063:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TCR_TSPrescale_Pos 8U /*!< ITM 1064:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM 1065:Drivers/CMSIS/Include/core_cm7.h **** 1066:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TCR_SWOENA_Pos 4U /*!< ITM 1067:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM 1068:Drivers/CMSIS/Include/core_cm7.h **** 1069:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TCR_DWTENA_Pos 3U /*!< ITM 1070:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM 1071:Drivers/CMSIS/Include/core_cm7.h **** 1072:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TCR_SYNCENA_Pos 2U /*!< ITM 1073:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM 1074:Drivers/CMSIS/Include/core_cm7.h **** 1075:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TCR_TSENA_Pos 1U /*!< ITM 1076:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM 1077:Drivers/CMSIS/Include/core_cm7.h **** 1078:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TCR_ITMENA_Pos 0U /*!< ITM 1079:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM 1080:Drivers/CMSIS/Include/core_cm7.h **** 1081:Drivers/CMSIS/Include/core_cm7.h **** /* ITM Integration Write Register Definitions */ 1082:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM 1083:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM 1084:Drivers/CMSIS/Include/core_cm7.h **** 1085:Drivers/CMSIS/Include/core_cm7.h **** /* ITM Integration Read Register Definitions */ 1086:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_IRR_ATREADYM_Pos 0U /*!< ITM 1087:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM 1088:Drivers/CMSIS/Include/core_cm7.h **** 1089:Drivers/CMSIS/Include/core_cm7.h **** /* ITM Integration Mode Control Register Definitions */ 1090:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM 1091:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM 1092:Drivers/CMSIS/Include/core_cm7.h **** 1093:Drivers/CMSIS/Include/core_cm7.h **** /* ITM Lock Status Register Definitions */ 1094:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_LSR_ByteAcc_Pos 2U /*!< ITM 1095:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM 1096:Drivers/CMSIS/Include/core_cm7.h **** 1097:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_LSR_Access_Pos 1U /*!< ITM 1098:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM 1099:Drivers/CMSIS/Include/core_cm7.h **** 1100:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_LSR_Present_Pos 0U /*!< ITM 1101:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM 1102:Drivers/CMSIS/Include/core_cm7.h **** 1103:Drivers/CMSIS/Include/core_cm7.h **** /*@}*/ /* end of group CMSIS_ITM */ 1104:Drivers/CMSIS/Include/core_cm7.h **** 1105:Drivers/CMSIS/Include/core_cm7.h **** 1106:Drivers/CMSIS/Include/core_cm7.h **** /** 1107:Drivers/CMSIS/Include/core_cm7.h **** \ingroup CMSIS_core_register 1108:Drivers/CMSIS/Include/core_cm7.h **** \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) 1109:Drivers/CMSIS/Include/core_cm7.h **** \brief Type definitions for the Data Watchpoint and Trace (DWT) 1110:Drivers/CMSIS/Include/core_cm7.h **** @{ 1111:Drivers/CMSIS/Include/core_cm7.h **** */ 1112:Drivers/CMSIS/Include/core_cm7.h **** 1113:Drivers/CMSIS/Include/core_cm7.h **** /** 1114:Drivers/CMSIS/Include/core_cm7.h **** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). ARM GAS /tmp/ccqopZd5.s page 21 1115:Drivers/CMSIS/Include/core_cm7.h **** */ 1116:Drivers/CMSIS/Include/core_cm7.h **** typedef struct 1117:Drivers/CMSIS/Include/core_cm7.h **** { 1118:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ 1119:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ 1120:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ 1121:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Registe 1122:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ 1123:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ 1124:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Registe 1125:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register 1126:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ 1127:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ 1128:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ 1129:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED0[1U]; 1130:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ 1131:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ 1132:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ 1133:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED1[1U]; 1134:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ 1135:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ 1136:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ 1137:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED2[1U]; 1138:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ 1139:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ 1140:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ 1141:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED3[981U]; 1142:Drivers/CMSIS/Include/core_cm7.h **** __OM uint32_t LAR; /*!< Offset: 0xFB0 ( W) Lock Access Register */ 1143:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ 1144:Drivers/CMSIS/Include/core_cm7.h **** } DWT_Type; 1145:Drivers/CMSIS/Include/core_cm7.h **** 1146:Drivers/CMSIS/Include/core_cm7.h **** /* DWT Control Register Definitions */ 1147:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTR 1148:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTR 1149:Drivers/CMSIS/Include/core_cm7.h **** 1150:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTR 1151:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTR 1152:Drivers/CMSIS/Include/core_cm7.h **** 1153:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTR 1154:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTR 1155:Drivers/CMSIS/Include/core_cm7.h **** 1156:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTR 1157:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTR 1158:Drivers/CMSIS/Include/core_cm7.h **** 1159:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTR 1160:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTR 1161:Drivers/CMSIS/Include/core_cm7.h **** 1162:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTR 1163:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTR 1164:Drivers/CMSIS/Include/core_cm7.h **** 1165:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTR 1166:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTR 1167:Drivers/CMSIS/Include/core_cm7.h **** 1168:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTR 1169:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTR 1170:Drivers/CMSIS/Include/core_cm7.h **** 1171:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTR ARM GAS /tmp/ccqopZd5.s page 22 1172:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTR 1173:Drivers/CMSIS/Include/core_cm7.h **** 1174:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTR 1175:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTR 1176:Drivers/CMSIS/Include/core_cm7.h **** 1177:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTR 1178:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTR 1179:Drivers/CMSIS/Include/core_cm7.h **** 1180:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTR 1181:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTR 1182:Drivers/CMSIS/Include/core_cm7.h **** 1183:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTR 1184:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTR 1185:Drivers/CMSIS/Include/core_cm7.h **** 1186:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTR 1187:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTR 1188:Drivers/CMSIS/Include/core_cm7.h **** 1189:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTR 1190:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTR 1191:Drivers/CMSIS/Include/core_cm7.h **** 1192:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTR 1193:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTR 1194:Drivers/CMSIS/Include/core_cm7.h **** 1195:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTR 1196:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTR 1197:Drivers/CMSIS/Include/core_cm7.h **** 1198:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTR 1199:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTR 1200:Drivers/CMSIS/Include/core_cm7.h **** 1201:Drivers/CMSIS/Include/core_cm7.h **** /* DWT CPI Count Register Definitions */ 1202:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPI 1203:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPI 1204:Drivers/CMSIS/Include/core_cm7.h **** 1205:Drivers/CMSIS/Include/core_cm7.h **** /* DWT Exception Overhead Count Register Definitions */ 1206:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXC 1207:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXC 1208:Drivers/CMSIS/Include/core_cm7.h **** 1209:Drivers/CMSIS/Include/core_cm7.h **** /* DWT Sleep Count Register Definitions */ 1210:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLE 1211:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLE 1212:Drivers/CMSIS/Include/core_cm7.h **** 1213:Drivers/CMSIS/Include/core_cm7.h **** /* DWT LSU Count Register Definitions */ 1214:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSU 1215:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSU 1216:Drivers/CMSIS/Include/core_cm7.h **** 1217:Drivers/CMSIS/Include/core_cm7.h **** /* DWT Folded-instruction Count Register Definitions */ 1218:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOL 1219:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOL 1220:Drivers/CMSIS/Include/core_cm7.h **** 1221:Drivers/CMSIS/Include/core_cm7.h **** /* DWT Comparator Mask Register Definitions */ 1222:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_MASK_MASK_Pos 0U /*!< DWT MAS 1223:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MAS 1224:Drivers/CMSIS/Include/core_cm7.h **** 1225:Drivers/CMSIS/Include/core_cm7.h **** /* DWT Comparator Function Register Definitions */ 1226:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUN 1227:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUN 1228:Drivers/CMSIS/Include/core_cm7.h **** ARM GAS /tmp/ccqopZd5.s page 23 1229:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUN 1230:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUN 1231:Drivers/CMSIS/Include/core_cm7.h **** 1232:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUN 1233:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUN 1234:Drivers/CMSIS/Include/core_cm7.h **** 1235:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUN 1236:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUN 1237:Drivers/CMSIS/Include/core_cm7.h **** 1238:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUN 1239:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUN 1240:Drivers/CMSIS/Include/core_cm7.h **** 1241:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUN 1242:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUN 1243:Drivers/CMSIS/Include/core_cm7.h **** 1244:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUN 1245:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUN 1246:Drivers/CMSIS/Include/core_cm7.h **** 1247:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUN 1248:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUN 1249:Drivers/CMSIS/Include/core_cm7.h **** 1250:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUN 1251:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUN 1252:Drivers/CMSIS/Include/core_cm7.h **** 1253:Drivers/CMSIS/Include/core_cm7.h **** /*@}*/ /* end of group CMSIS_DWT */ 1254:Drivers/CMSIS/Include/core_cm7.h **** 1255:Drivers/CMSIS/Include/core_cm7.h **** 1256:Drivers/CMSIS/Include/core_cm7.h **** /** 1257:Drivers/CMSIS/Include/core_cm7.h **** \ingroup CMSIS_core_register 1258:Drivers/CMSIS/Include/core_cm7.h **** \defgroup CMSIS_TPI Trace Port Interface (TPI) 1259:Drivers/CMSIS/Include/core_cm7.h **** \brief Type definitions for the Trace Port Interface (TPI) 1260:Drivers/CMSIS/Include/core_cm7.h **** @{ 1261:Drivers/CMSIS/Include/core_cm7.h **** */ 1262:Drivers/CMSIS/Include/core_cm7.h **** 1263:Drivers/CMSIS/Include/core_cm7.h **** /** 1264:Drivers/CMSIS/Include/core_cm7.h **** \brief Structure type to access the Trace Port Interface Register (TPI). 1265:Drivers/CMSIS/Include/core_cm7.h **** */ 1266:Drivers/CMSIS/Include/core_cm7.h **** typedef struct 1267:Drivers/CMSIS/Include/core_cm7.h **** { 1268:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Reg 1269:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Regis 1270:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED0[2U]; 1271:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Reg 1272:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED1[55U]; 1273:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register * 1274:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED2[131U]; 1275:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Regis 1276:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Regi 1277:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counte 1278:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED3[759U]; 1279:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ 1280:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ 1281:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ 1282:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED4[1U]; 1283:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ 1284:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ 1285:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ ARM GAS /tmp/ccqopZd5.s page 24 1286:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED5[39U]; 1287:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ 1288:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ 1289:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED7[8U]; 1290:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ 1291:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ 1292:Drivers/CMSIS/Include/core_cm7.h **** } TPI_Type; 1293:Drivers/CMSIS/Include/core_cm7.h **** 1294:Drivers/CMSIS/Include/core_cm7.h **** /* TPI Asynchronous Clock Prescaler Register Definitions */ 1295:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACP 1296:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACP 1297:Drivers/CMSIS/Include/core_cm7.h **** 1298:Drivers/CMSIS/Include/core_cm7.h **** /* TPI Selected Pin Protocol Register Definitions */ 1299:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPP 1300:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPP 1301:Drivers/CMSIS/Include/core_cm7.h **** 1302:Drivers/CMSIS/Include/core_cm7.h **** /* TPI Formatter and Flush Status Register Definitions */ 1303:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFS 1304:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFS 1305:Drivers/CMSIS/Include/core_cm7.h **** 1306:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFS 1307:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFS 1308:Drivers/CMSIS/Include/core_cm7.h **** 1309:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFS 1310:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFS 1311:Drivers/CMSIS/Include/core_cm7.h **** 1312:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFS 1313:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFS 1314:Drivers/CMSIS/Include/core_cm7.h **** 1315:Drivers/CMSIS/Include/core_cm7.h **** /* TPI Formatter and Flush Control Register Definitions */ 1316:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFC 1317:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFC 1318:Drivers/CMSIS/Include/core_cm7.h **** 1319:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFC 1320:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFC 1321:Drivers/CMSIS/Include/core_cm7.h **** 1322:Drivers/CMSIS/Include/core_cm7.h **** /* TPI TRIGGER Register Definitions */ 1323:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRI 1324:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRI 1325:Drivers/CMSIS/Include/core_cm7.h **** 1326:Drivers/CMSIS/Include/core_cm7.h **** /* TPI Integration ETM Data Register Definitions (FIFO0) */ 1327:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIF 1328:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIF 1329:Drivers/CMSIS/Include/core_cm7.h **** 1330:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIF 1331:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIF 1332:Drivers/CMSIS/Include/core_cm7.h **** 1333:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIF 1334:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIF 1335:Drivers/CMSIS/Include/core_cm7.h **** 1336:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIF 1337:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIF 1338:Drivers/CMSIS/Include/core_cm7.h **** 1339:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIF 1340:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIF 1341:Drivers/CMSIS/Include/core_cm7.h **** 1342:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIF ARM GAS /tmp/ccqopZd5.s page 25 1343:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIF 1344:Drivers/CMSIS/Include/core_cm7.h **** 1345:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIF 1346:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIF 1347:Drivers/CMSIS/Include/core_cm7.h **** 1348:Drivers/CMSIS/Include/core_cm7.h **** /* TPI ITATBCTR2 Register Definitions */ 1349:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITA 1350:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITA 1351:Drivers/CMSIS/Include/core_cm7.h **** 1352:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITA 1353:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITA 1354:Drivers/CMSIS/Include/core_cm7.h **** 1355:Drivers/CMSIS/Include/core_cm7.h **** /* TPI Integration ITM Data Register Definitions (FIFO1) */ 1356:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIF 1357:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIF 1358:Drivers/CMSIS/Include/core_cm7.h **** 1359:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIF 1360:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIF 1361:Drivers/CMSIS/Include/core_cm7.h **** 1362:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIF 1363:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIF 1364:Drivers/CMSIS/Include/core_cm7.h **** 1365:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIF 1366:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIF 1367:Drivers/CMSIS/Include/core_cm7.h **** 1368:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIF 1369:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIF 1370:Drivers/CMSIS/Include/core_cm7.h **** 1371:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIF 1372:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIF 1373:Drivers/CMSIS/Include/core_cm7.h **** 1374:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIF 1375:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIF 1376:Drivers/CMSIS/Include/core_cm7.h **** 1377:Drivers/CMSIS/Include/core_cm7.h **** /* TPI ITATBCTR0 Register Definitions */ 1378:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITA 1379:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITA 1380:Drivers/CMSIS/Include/core_cm7.h **** 1381:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITA 1382:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITA 1383:Drivers/CMSIS/Include/core_cm7.h **** 1384:Drivers/CMSIS/Include/core_cm7.h **** /* TPI Integration Mode Control Register Definitions */ 1385:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITC 1386:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITC 1387:Drivers/CMSIS/Include/core_cm7.h **** 1388:Drivers/CMSIS/Include/core_cm7.h **** /* TPI DEVID Register Definitions */ 1389:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEV 1390:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEV 1391:Drivers/CMSIS/Include/core_cm7.h **** 1392:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEV 1393:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEV 1394:Drivers/CMSIS/Include/core_cm7.h **** 1395:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEV 1396:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEV 1397:Drivers/CMSIS/Include/core_cm7.h **** 1398:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEV 1399:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEV ARM GAS /tmp/ccqopZd5.s page 26 1400:Drivers/CMSIS/Include/core_cm7.h **** 1401:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEV 1402:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEV 1403:Drivers/CMSIS/Include/core_cm7.h **** 1404:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEV 1405:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEV 1406:Drivers/CMSIS/Include/core_cm7.h **** 1407:Drivers/CMSIS/Include/core_cm7.h **** /* TPI DEVTYPE Register Definitions */ 1408:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEV 1409:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEV 1410:Drivers/CMSIS/Include/core_cm7.h **** 1411:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEV 1412:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEV 1413:Drivers/CMSIS/Include/core_cm7.h **** 1414:Drivers/CMSIS/Include/core_cm7.h **** /*@}*/ /* end of group CMSIS_TPI */ 1415:Drivers/CMSIS/Include/core_cm7.h **** 1416:Drivers/CMSIS/Include/core_cm7.h **** 1417:Drivers/CMSIS/Include/core_cm7.h **** #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) 1418:Drivers/CMSIS/Include/core_cm7.h **** /** 1419:Drivers/CMSIS/Include/core_cm7.h **** \ingroup CMSIS_core_register 1420:Drivers/CMSIS/Include/core_cm7.h **** \defgroup CMSIS_MPU Memory Protection Unit (MPU) 1421:Drivers/CMSIS/Include/core_cm7.h **** \brief Type definitions for the Memory Protection Unit (MPU) 1422:Drivers/CMSIS/Include/core_cm7.h **** @{ 1423:Drivers/CMSIS/Include/core_cm7.h **** */ 1424:Drivers/CMSIS/Include/core_cm7.h **** 1425:Drivers/CMSIS/Include/core_cm7.h **** /** 1426:Drivers/CMSIS/Include/core_cm7.h **** \brief Structure type to access the Memory Protection Unit (MPU). 1427:Drivers/CMSIS/Include/core_cm7.h **** */ 1428:Drivers/CMSIS/Include/core_cm7.h **** typedef struct 1429:Drivers/CMSIS/Include/core_cm7.h **** { 1430:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ 1431:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ 1432:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ 1433:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register 1434:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Re 1435:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address 1436:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and 1437:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address 1438:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and 1439:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address 1440:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and 1441:Drivers/CMSIS/Include/core_cm7.h **** } MPU_Type; 1442:Drivers/CMSIS/Include/core_cm7.h **** 1443:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_TYPE_RALIASES 4U 1444:Drivers/CMSIS/Include/core_cm7.h **** 1445:Drivers/CMSIS/Include/core_cm7.h **** /* MPU Type Register Definitions */ 1446:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_TYPE_IREGION_Pos 16U /*!< MPU 1447:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU 1448:Drivers/CMSIS/Include/core_cm7.h **** 1449:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_TYPE_DREGION_Pos 8U /*!< MPU 1450:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU 1451:Drivers/CMSIS/Include/core_cm7.h **** 1452:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU 1453:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU 1454:Drivers/CMSIS/Include/core_cm7.h **** 1455:Drivers/CMSIS/Include/core_cm7.h **** /* MPU Control Register Definitions */ 1456:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU ARM GAS /tmp/ccqopZd5.s page 27 1457:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU 1458:Drivers/CMSIS/Include/core_cm7.h **** 1459:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU 1460:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU 1461:Drivers/CMSIS/Include/core_cm7.h **** 1462:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU 1463:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU 1464:Drivers/CMSIS/Include/core_cm7.h **** 1465:Drivers/CMSIS/Include/core_cm7.h **** /* MPU Region Number Register Definitions */ 1466:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RNR_REGION_Pos 0U /*!< MPU 1467:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU 1468:Drivers/CMSIS/Include/core_cm7.h **** 1469:Drivers/CMSIS/Include/core_cm7.h **** /* MPU Region Base Address Register Definitions */ 1470:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RBAR_ADDR_Pos 5U /*!< MPU 1471:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU 1472:Drivers/CMSIS/Include/core_cm7.h **** 1473:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RBAR_VALID_Pos 4U /*!< MPU 1474:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU 1475:Drivers/CMSIS/Include/core_cm7.h **** 1476:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RBAR_REGION_Pos 0U /*!< MPU 1477:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU 1478:Drivers/CMSIS/Include/core_cm7.h **** 1479:Drivers/CMSIS/Include/core_cm7.h **** /* MPU Region Attribute and Size Register Definitions */ 1480:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RASR_ATTRS_Pos 16U /*!< MPU 1481:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU 1482:Drivers/CMSIS/Include/core_cm7.h **** 1483:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RASR_XN_Pos 28U /*!< MPU 1484:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU 1485:Drivers/CMSIS/Include/core_cm7.h **** 1486:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RASR_AP_Pos 24U /*!< MPU 1487:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU 1488:Drivers/CMSIS/Include/core_cm7.h **** 1489:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RASR_TEX_Pos 19U /*!< MPU 1490:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU 1491:Drivers/CMSIS/Include/core_cm7.h **** 1492:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RASR_S_Pos 18U /*!< MPU 1493:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU 1494:Drivers/CMSIS/Include/core_cm7.h **** 1495:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RASR_C_Pos 17U /*!< MPU 1496:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU 1497:Drivers/CMSIS/Include/core_cm7.h **** 1498:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RASR_B_Pos 16U /*!< MPU 1499:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU 1500:Drivers/CMSIS/Include/core_cm7.h **** 1501:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RASR_SRD_Pos 8U /*!< MPU 1502:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU 1503:Drivers/CMSIS/Include/core_cm7.h **** 1504:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RASR_SIZE_Pos 1U /*!< MPU 1505:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU 1506:Drivers/CMSIS/Include/core_cm7.h **** 1507:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RASR_ENABLE_Pos 0U /*!< MPU 1508:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU 1509:Drivers/CMSIS/Include/core_cm7.h **** 1510:Drivers/CMSIS/Include/core_cm7.h **** /*@} end of group CMSIS_MPU */ 1511:Drivers/CMSIS/Include/core_cm7.h **** #endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */ 1512:Drivers/CMSIS/Include/core_cm7.h **** 1513:Drivers/CMSIS/Include/core_cm7.h **** ARM GAS /tmp/ccqopZd5.s page 28 1514:Drivers/CMSIS/Include/core_cm7.h **** /** 1515:Drivers/CMSIS/Include/core_cm7.h **** \ingroup CMSIS_core_register 1516:Drivers/CMSIS/Include/core_cm7.h **** \defgroup CMSIS_FPU Floating Point Unit (FPU) 1517:Drivers/CMSIS/Include/core_cm7.h **** \brief Type definitions for the Floating Point Unit (FPU) 1518:Drivers/CMSIS/Include/core_cm7.h **** @{ 1519:Drivers/CMSIS/Include/core_cm7.h **** */ 1520:Drivers/CMSIS/Include/core_cm7.h **** 1521:Drivers/CMSIS/Include/core_cm7.h **** /** 1522:Drivers/CMSIS/Include/core_cm7.h **** \brief Structure type to access the Floating Point Unit (FPU). 1523:Drivers/CMSIS/Include/core_cm7.h **** */ 1524:Drivers/CMSIS/Include/core_cm7.h **** typedef struct 1525:Drivers/CMSIS/Include/core_cm7.h **** { 1526:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED0[1U]; 1527:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control R 1528:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address R 1529:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Co 1530:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 1531:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 1532:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 1533:Drivers/CMSIS/Include/core_cm7.h **** } FPU_Type; 1534:Drivers/CMSIS/Include/core_cm7.h **** 1535:Drivers/CMSIS/Include/core_cm7.h **** /* Floating-Point Context Control Register Definitions */ 1536:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCC 1537:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCC 1538:Drivers/CMSIS/Include/core_cm7.h **** 1539:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCC 1540:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCC 1541:Drivers/CMSIS/Include/core_cm7.h **** 1542:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCC 1543:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCC 1544:Drivers/CMSIS/Include/core_cm7.h **** 1545:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCC 1546:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCC 1547:Drivers/CMSIS/Include/core_cm7.h **** 1548:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCC 1549:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCC 1550:Drivers/CMSIS/Include/core_cm7.h **** 1551:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCC 1552:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCC 1553:Drivers/CMSIS/Include/core_cm7.h **** 1554:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPCCR_THREAD_Pos 3U /*!< FPCC 1555:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCC 1556:Drivers/CMSIS/Include/core_cm7.h **** 1557:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPCCR_USER_Pos 1U /*!< FPCC 1558:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCC 1559:Drivers/CMSIS/Include/core_cm7.h **** 1560:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCC 1561:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCC 1562:Drivers/CMSIS/Include/core_cm7.h **** 1563:Drivers/CMSIS/Include/core_cm7.h **** /* Floating-Point Context Address Register Definitions */ 1564:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCA 1565:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCA 1566:Drivers/CMSIS/Include/core_cm7.h **** 1567:Drivers/CMSIS/Include/core_cm7.h **** /* Floating-Point Default Status Control Register Definitions */ 1568:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPDSCR_AHP_Pos 26U /*!< FPDS 1569:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDS 1570:Drivers/CMSIS/Include/core_cm7.h **** ARM GAS /tmp/ccqopZd5.s page 29 1571:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPDSCR_DN_Pos 25U /*!< FPDS 1572:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDS 1573:Drivers/CMSIS/Include/core_cm7.h **** 1574:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPDSCR_FZ_Pos 24U /*!< FPDS 1575:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDS 1576:Drivers/CMSIS/Include/core_cm7.h **** 1577:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPDSCR_RMode_Pos 22U /*!< FPDS 1578:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDS 1579:Drivers/CMSIS/Include/core_cm7.h **** 1580:Drivers/CMSIS/Include/core_cm7.h **** /* Media and FP Feature Register 0 Definitions */ 1581:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR 1582:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR 1583:Drivers/CMSIS/Include/core_cm7.h **** 1584:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR 1585:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR 1586:Drivers/CMSIS/Include/core_cm7.h **** 1587:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR 1588:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR 1589:Drivers/CMSIS/Include/core_cm7.h **** 1590:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR0_Divide_Pos 16U /*!< MVFR 1591:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR 1592:Drivers/CMSIS/Include/core_cm7.h **** 1593:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR 1594:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR 1595:Drivers/CMSIS/Include/core_cm7.h **** 1596:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR 1597:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR 1598:Drivers/CMSIS/Include/core_cm7.h **** 1599:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR 1600:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR 1601:Drivers/CMSIS/Include/core_cm7.h **** 1602:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR 1603:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR 1604:Drivers/CMSIS/Include/core_cm7.h **** 1605:Drivers/CMSIS/Include/core_cm7.h **** /* Media and FP Feature Register 1 Definitions */ 1606:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR 1607:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR 1608:Drivers/CMSIS/Include/core_cm7.h **** 1609:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR 1610:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR 1611:Drivers/CMSIS/Include/core_cm7.h **** 1612:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR 1613:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR 1614:Drivers/CMSIS/Include/core_cm7.h **** 1615:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR 1616:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR 1617:Drivers/CMSIS/Include/core_cm7.h **** 1618:Drivers/CMSIS/Include/core_cm7.h **** /* Media and FP Feature Register 2 Definitions */ 1619:Drivers/CMSIS/Include/core_cm7.h **** 1620:Drivers/CMSIS/Include/core_cm7.h **** /*@} end of group CMSIS_FPU */ 1621:Drivers/CMSIS/Include/core_cm7.h **** 1622:Drivers/CMSIS/Include/core_cm7.h **** 1623:Drivers/CMSIS/Include/core_cm7.h **** /** 1624:Drivers/CMSIS/Include/core_cm7.h **** \ingroup CMSIS_core_register 1625:Drivers/CMSIS/Include/core_cm7.h **** \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) 1626:Drivers/CMSIS/Include/core_cm7.h **** \brief Type definitions for the Core Debug Registers 1627:Drivers/CMSIS/Include/core_cm7.h **** @{ ARM GAS /tmp/ccqopZd5.s page 30 1628:Drivers/CMSIS/Include/core_cm7.h **** */ 1629:Drivers/CMSIS/Include/core_cm7.h **** 1630:Drivers/CMSIS/Include/core_cm7.h **** /** 1631:Drivers/CMSIS/Include/core_cm7.h **** \brief Structure type to access the Core Debug Register (CoreDebug). 1632:Drivers/CMSIS/Include/core_cm7.h **** */ 1633:Drivers/CMSIS/Include/core_cm7.h **** typedef struct 1634:Drivers/CMSIS/Include/core_cm7.h **** { 1635:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status 1636:Drivers/CMSIS/Include/core_cm7.h **** __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Reg 1637:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Registe 1638:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Cont 1639:Drivers/CMSIS/Include/core_cm7.h **** } CoreDebug_Type; 1640:Drivers/CMSIS/Include/core_cm7.h **** 1641:Drivers/CMSIS/Include/core_cm7.h **** /* Debug Halting Control and Status Register Definitions */ 1642:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< Core 1643:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< Core 1644:Drivers/CMSIS/Include/core_cm7.h **** 1645:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< Core 1646:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< Core 1647:Drivers/CMSIS/Include/core_cm7.h **** 1648:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< Core 1649:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< Core 1650:Drivers/CMSIS/Include/core_cm7.h **** 1651:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< Core 1652:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< Core 1653:Drivers/CMSIS/Include/core_cm7.h **** 1654:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< Core 1655:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< Core 1656:Drivers/CMSIS/Include/core_cm7.h **** 1657:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< Core 1658:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< Core 1659:Drivers/CMSIS/Include/core_cm7.h **** 1660:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< Core 1661:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< Core 1662:Drivers/CMSIS/Include/core_cm7.h **** 1663:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< Core 1664:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< Core 1665:Drivers/CMSIS/Include/core_cm7.h **** 1666:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< Core 1667:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< Core 1668:Drivers/CMSIS/Include/core_cm7.h **** 1669:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< Core 1670:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< Core 1671:Drivers/CMSIS/Include/core_cm7.h **** 1672:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< Core 1673:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< Core 1674:Drivers/CMSIS/Include/core_cm7.h **** 1675:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< Core 1676:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< Core 1677:Drivers/CMSIS/Include/core_cm7.h **** 1678:Drivers/CMSIS/Include/core_cm7.h **** /* Debug Core Register Selector Register Definitions */ 1679:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< Core 1680:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< Core 1681:Drivers/CMSIS/Include/core_cm7.h **** 1682:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< Core 1683:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< Core 1684:Drivers/CMSIS/Include/core_cm7.h **** ARM GAS /tmp/ccqopZd5.s page 31 1685:Drivers/CMSIS/Include/core_cm7.h **** /* Debug Exception and Monitor Control Register Definitions */ 1686:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< Core 1687:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< Core 1688:Drivers/CMSIS/Include/core_cm7.h **** 1689:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< Core 1690:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< Core 1691:Drivers/CMSIS/Include/core_cm7.h **** 1692:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< Core 1693:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< Core 1694:Drivers/CMSIS/Include/core_cm7.h **** 1695:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< Core 1696:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< Core 1697:Drivers/CMSIS/Include/core_cm7.h **** 1698:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< Core 1699:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< Core 1700:Drivers/CMSIS/Include/core_cm7.h **** 1701:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< Core 1702:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< Core 1703:Drivers/CMSIS/Include/core_cm7.h **** 1704:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< Core 1705:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< Core 1706:Drivers/CMSIS/Include/core_cm7.h **** 1707:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< Core 1708:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< Core 1709:Drivers/CMSIS/Include/core_cm7.h **** 1710:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< Core 1711:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< Core 1712:Drivers/CMSIS/Include/core_cm7.h **** 1713:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< Core 1714:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< Core 1715:Drivers/CMSIS/Include/core_cm7.h **** 1716:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< Core 1717:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< Core 1718:Drivers/CMSIS/Include/core_cm7.h **** 1719:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< Core 1720:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< Core 1721:Drivers/CMSIS/Include/core_cm7.h **** 1722:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< Core 1723:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< Core 1724:Drivers/CMSIS/Include/core_cm7.h **** 1725:Drivers/CMSIS/Include/core_cm7.h **** /*@} end of group CMSIS_CoreDebug */ 1726:Drivers/CMSIS/Include/core_cm7.h **** 1727:Drivers/CMSIS/Include/core_cm7.h **** 1728:Drivers/CMSIS/Include/core_cm7.h **** /** 1729:Drivers/CMSIS/Include/core_cm7.h **** \ingroup CMSIS_core_register 1730:Drivers/CMSIS/Include/core_cm7.h **** \defgroup CMSIS_core_bitfield Core register bit field macros 1731:Drivers/CMSIS/Include/core_cm7.h **** \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). 1732:Drivers/CMSIS/Include/core_cm7.h **** @{ 1733:Drivers/CMSIS/Include/core_cm7.h **** */ 1734:Drivers/CMSIS/Include/core_cm7.h **** 1735:Drivers/CMSIS/Include/core_cm7.h **** /** 1736:Drivers/CMSIS/Include/core_cm7.h **** \brief Mask and shift a bit field value for use in a register bit range. 1737:Drivers/CMSIS/Include/core_cm7.h **** \param[in] field Name of the register bit field. 1738:Drivers/CMSIS/Include/core_cm7.h **** \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. 1739:Drivers/CMSIS/Include/core_cm7.h **** \return Masked and shifted value. 1740:Drivers/CMSIS/Include/core_cm7.h **** */ 1741:Drivers/CMSIS/Include/core_cm7.h **** #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) ARM GAS /tmp/ccqopZd5.s page 32 1742:Drivers/CMSIS/Include/core_cm7.h **** 1743:Drivers/CMSIS/Include/core_cm7.h **** /** 1744:Drivers/CMSIS/Include/core_cm7.h **** \brief Mask and shift a register value to extract a bit filed value. 1745:Drivers/CMSIS/Include/core_cm7.h **** \param[in] field Name of the register bit field. 1746:Drivers/CMSIS/Include/core_cm7.h **** \param[in] value Value of register. This parameter is interpreted as an uint32_t type. 1747:Drivers/CMSIS/Include/core_cm7.h **** \return Masked and shifted bit field value. 1748:Drivers/CMSIS/Include/core_cm7.h **** */ 1749:Drivers/CMSIS/Include/core_cm7.h **** #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) 1750:Drivers/CMSIS/Include/core_cm7.h **** 1751:Drivers/CMSIS/Include/core_cm7.h **** /*@} end of group CMSIS_core_bitfield */ 1752:Drivers/CMSIS/Include/core_cm7.h **** 1753:Drivers/CMSIS/Include/core_cm7.h **** 1754:Drivers/CMSIS/Include/core_cm7.h **** /** 1755:Drivers/CMSIS/Include/core_cm7.h **** \ingroup CMSIS_core_register 1756:Drivers/CMSIS/Include/core_cm7.h **** \defgroup CMSIS_core_base Core Definitions 1757:Drivers/CMSIS/Include/core_cm7.h **** \brief Definitions for base addresses, unions, and structures. 1758:Drivers/CMSIS/Include/core_cm7.h **** @{ 1759:Drivers/CMSIS/Include/core_cm7.h **** */ 1760:Drivers/CMSIS/Include/core_cm7.h **** 1761:Drivers/CMSIS/Include/core_cm7.h **** /* Memory mapping of Core Hardware */ 1762:Drivers/CMSIS/Include/core_cm7.h **** #define SCS_BASE (0xE000E000UL) /*!< System Control Space Bas 1763:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ 1764:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ 1765:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ 1766:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address 1767:Drivers/CMSIS/Include/core_cm7.h **** #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ 1768:Drivers/CMSIS/Include/core_cm7.h **** #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ 1769:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Bas 1770:Drivers/CMSIS/Include/core_cm7.h **** 1771:Drivers/CMSIS/Include/core_cm7.h **** #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register 1772:Drivers/CMSIS/Include/core_cm7.h **** #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct 1773:Drivers/CMSIS/Include/core_cm7.h **** #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration st 1774:Drivers/CMSIS/Include/core_cm7.h **** #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struc 1775:Drivers/CMSIS/Include/core_cm7.h **** #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct 1776:Drivers/CMSIS/Include/core_cm7.h **** #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct 1777:Drivers/CMSIS/Include/core_cm7.h **** #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct 1778:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration 1779:Drivers/CMSIS/Include/core_cm7.h **** 1780:Drivers/CMSIS/Include/core_cm7.h **** #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) 1781:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit * 1782:Drivers/CMSIS/Include/core_cm7.h **** #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit * 1783:Drivers/CMSIS/Include/core_cm7.h **** #endif 1784:Drivers/CMSIS/Include/core_cm7.h **** 1785:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ 1786:Drivers/CMSIS/Include/core_cm7.h **** #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ 1787:Drivers/CMSIS/Include/core_cm7.h **** 1788:Drivers/CMSIS/Include/core_cm7.h **** /*@} */ 1789:Drivers/CMSIS/Include/core_cm7.h **** 1790:Drivers/CMSIS/Include/core_cm7.h **** 1791:Drivers/CMSIS/Include/core_cm7.h **** 1792:Drivers/CMSIS/Include/core_cm7.h **** /******************************************************************************* 1793:Drivers/CMSIS/Include/core_cm7.h **** * Hardware Abstraction Layer 1794:Drivers/CMSIS/Include/core_cm7.h **** Core Function Interface contains: 1795:Drivers/CMSIS/Include/core_cm7.h **** - Core NVIC Functions 1796:Drivers/CMSIS/Include/core_cm7.h **** - Core SysTick Functions 1797:Drivers/CMSIS/Include/core_cm7.h **** - Core Debug Functions 1798:Drivers/CMSIS/Include/core_cm7.h **** - Core Register Access Functions ARM GAS /tmp/ccqopZd5.s page 33 1799:Drivers/CMSIS/Include/core_cm7.h **** ******************************************************************************/ 1800:Drivers/CMSIS/Include/core_cm7.h **** /** 1801:Drivers/CMSIS/Include/core_cm7.h **** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference 1802:Drivers/CMSIS/Include/core_cm7.h **** */ 1803:Drivers/CMSIS/Include/core_cm7.h **** 1804:Drivers/CMSIS/Include/core_cm7.h **** 1805:Drivers/CMSIS/Include/core_cm7.h **** 1806:Drivers/CMSIS/Include/core_cm7.h **** /* ########################## NVIC functions #################################### */ 1807:Drivers/CMSIS/Include/core_cm7.h **** /** 1808:Drivers/CMSIS/Include/core_cm7.h **** \ingroup CMSIS_Core_FunctionInterface 1809:Drivers/CMSIS/Include/core_cm7.h **** \defgroup CMSIS_Core_NVICFunctions NVIC Functions 1810:Drivers/CMSIS/Include/core_cm7.h **** \brief Functions that manage interrupts and exceptions via the NVIC. 1811:Drivers/CMSIS/Include/core_cm7.h **** @{ 1812:Drivers/CMSIS/Include/core_cm7.h **** */ 1813:Drivers/CMSIS/Include/core_cm7.h **** 1814:Drivers/CMSIS/Include/core_cm7.h **** #ifdef CMSIS_NVIC_VIRTUAL 1815:Drivers/CMSIS/Include/core_cm7.h **** #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE 1816:Drivers/CMSIS/Include/core_cm7.h **** #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" 1817:Drivers/CMSIS/Include/core_cm7.h **** #endif 1818:Drivers/CMSIS/Include/core_cm7.h **** #include CMSIS_NVIC_VIRTUAL_HEADER_FILE 1819:Drivers/CMSIS/Include/core_cm7.h **** #else 1820:Drivers/CMSIS/Include/core_cm7.h **** #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping 1821:Drivers/CMSIS/Include/core_cm7.h **** #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping 1822:Drivers/CMSIS/Include/core_cm7.h **** #define NVIC_EnableIRQ __NVIC_EnableIRQ 1823:Drivers/CMSIS/Include/core_cm7.h **** #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ 1824:Drivers/CMSIS/Include/core_cm7.h **** #define NVIC_DisableIRQ __NVIC_DisableIRQ 1825:Drivers/CMSIS/Include/core_cm7.h **** #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ 1826:Drivers/CMSIS/Include/core_cm7.h **** #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ 1827:Drivers/CMSIS/Include/core_cm7.h **** #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ 1828:Drivers/CMSIS/Include/core_cm7.h **** #define NVIC_GetActive __NVIC_GetActive 1829:Drivers/CMSIS/Include/core_cm7.h **** #define NVIC_SetPriority __NVIC_SetPriority 1830:Drivers/CMSIS/Include/core_cm7.h **** #define NVIC_GetPriority __NVIC_GetPriority 1831:Drivers/CMSIS/Include/core_cm7.h **** #define NVIC_SystemReset __NVIC_SystemReset 1832:Drivers/CMSIS/Include/core_cm7.h **** #endif /* CMSIS_NVIC_VIRTUAL */ 1833:Drivers/CMSIS/Include/core_cm7.h **** 1834:Drivers/CMSIS/Include/core_cm7.h **** #ifdef CMSIS_VECTAB_VIRTUAL 1835:Drivers/CMSIS/Include/core_cm7.h **** #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE 1836:Drivers/CMSIS/Include/core_cm7.h **** #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" 1837:Drivers/CMSIS/Include/core_cm7.h **** #endif 1838:Drivers/CMSIS/Include/core_cm7.h **** #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE 1839:Drivers/CMSIS/Include/core_cm7.h **** #else 1840:Drivers/CMSIS/Include/core_cm7.h **** #define NVIC_SetVector __NVIC_SetVector 1841:Drivers/CMSIS/Include/core_cm7.h **** #define NVIC_GetVector __NVIC_GetVector 1842:Drivers/CMSIS/Include/core_cm7.h **** #endif /* (CMSIS_VECTAB_VIRTUAL) */ 1843:Drivers/CMSIS/Include/core_cm7.h **** 1844:Drivers/CMSIS/Include/core_cm7.h **** #define NVIC_USER_IRQ_OFFSET 16 1845:Drivers/CMSIS/Include/core_cm7.h **** 1846:Drivers/CMSIS/Include/core_cm7.h **** 1847:Drivers/CMSIS/Include/core_cm7.h **** /* The following EXC_RETURN values are saved the LR on exception entry */ 1848:Drivers/CMSIS/Include/core_cm7.h **** #define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after ret 1849:Drivers/CMSIS/Include/core_cm7.h **** #define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after retu 1850:Drivers/CMSIS/Include/core_cm7.h **** #define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after retu 1851:Drivers/CMSIS/Include/core_cm7.h **** #define EXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after ret 1852:Drivers/CMSIS/Include/core_cm7.h **** #define EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after retu 1853:Drivers/CMSIS/Include/core_cm7.h **** #define EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after retu 1854:Drivers/CMSIS/Include/core_cm7.h **** 1855:Drivers/CMSIS/Include/core_cm7.h **** ARM GAS /tmp/ccqopZd5.s page 34 1856:Drivers/CMSIS/Include/core_cm7.h **** /** 1857:Drivers/CMSIS/Include/core_cm7.h **** \brief Set Priority Grouping 1858:Drivers/CMSIS/Include/core_cm7.h **** \details Sets the priority grouping field using the required unlock sequence. 1859:Drivers/CMSIS/Include/core_cm7.h **** The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. 1860:Drivers/CMSIS/Include/core_cm7.h **** Only values from 0..7 are used. 1861:Drivers/CMSIS/Include/core_cm7.h **** In case of a conflict between priority grouping and available 1862:Drivers/CMSIS/Include/core_cm7.h **** priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. 1863:Drivers/CMSIS/Include/core_cm7.h **** \param [in] PriorityGroup Priority grouping field. 1864:Drivers/CMSIS/Include/core_cm7.h **** */ 1865:Drivers/CMSIS/Include/core_cm7.h **** __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) 1866:Drivers/CMSIS/Include/core_cm7.h **** { 1867:Drivers/CMSIS/Include/core_cm7.h **** uint32_t reg_value; 1868:Drivers/CMSIS/Include/core_cm7.h **** uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 a 1869:Drivers/CMSIS/Include/core_cm7.h **** 1870:Drivers/CMSIS/Include/core_cm7.h **** reg_value = SCB->AIRCR; /* read old register 1871:Drivers/CMSIS/Include/core_cm7.h **** reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to chan 1872:Drivers/CMSIS/Include/core_cm7.h **** reg_value = (reg_value | 1873:Drivers/CMSIS/Include/core_cm7.h **** ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | 1874:Drivers/CMSIS/Include/core_cm7.h **** (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key a 1875:Drivers/CMSIS/Include/core_cm7.h **** SCB->AIRCR = reg_value; 1876:Drivers/CMSIS/Include/core_cm7.h **** } 1877:Drivers/CMSIS/Include/core_cm7.h **** 1878:Drivers/CMSIS/Include/core_cm7.h **** 1879:Drivers/CMSIS/Include/core_cm7.h **** /** 1880:Drivers/CMSIS/Include/core_cm7.h **** \brief Get Priority Grouping 1881:Drivers/CMSIS/Include/core_cm7.h **** \details Reads the priority grouping field from the NVIC Interrupt Controller. 1882:Drivers/CMSIS/Include/core_cm7.h **** \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). 1883:Drivers/CMSIS/Include/core_cm7.h **** */ 1884:Drivers/CMSIS/Include/core_cm7.h **** __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) 1885:Drivers/CMSIS/Include/core_cm7.h **** { 1886:Drivers/CMSIS/Include/core_cm7.h **** return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); 1887:Drivers/CMSIS/Include/core_cm7.h **** } 1888:Drivers/CMSIS/Include/core_cm7.h **** 1889:Drivers/CMSIS/Include/core_cm7.h **** 1890:Drivers/CMSIS/Include/core_cm7.h **** /** 1891:Drivers/CMSIS/Include/core_cm7.h **** \brief Enable Interrupt 1892:Drivers/CMSIS/Include/core_cm7.h **** \details Enables a device specific interrupt in the NVIC interrupt controller. 1893:Drivers/CMSIS/Include/core_cm7.h **** \param [in] IRQn Device specific interrupt number. 1894:Drivers/CMSIS/Include/core_cm7.h **** \note IRQn must not be negative. 1895:Drivers/CMSIS/Include/core_cm7.h **** */ 1896:Drivers/CMSIS/Include/core_cm7.h **** __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) 1897:Drivers/CMSIS/Include/core_cm7.h **** { 1898:Drivers/CMSIS/Include/core_cm7.h **** if ((int32_t)(IRQn) >= 0) 1899:Drivers/CMSIS/Include/core_cm7.h **** { 1900:Drivers/CMSIS/Include/core_cm7.h **** NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 1901:Drivers/CMSIS/Include/core_cm7.h **** } 1902:Drivers/CMSIS/Include/core_cm7.h **** } 1903:Drivers/CMSIS/Include/core_cm7.h **** 1904:Drivers/CMSIS/Include/core_cm7.h **** 1905:Drivers/CMSIS/Include/core_cm7.h **** /** 1906:Drivers/CMSIS/Include/core_cm7.h **** \brief Get Interrupt Enable status 1907:Drivers/CMSIS/Include/core_cm7.h **** \details Returns a device specific interrupt enable status from the NVIC interrupt controller. 1908:Drivers/CMSIS/Include/core_cm7.h **** \param [in] IRQn Device specific interrupt number. 1909:Drivers/CMSIS/Include/core_cm7.h **** \return 0 Interrupt is not enabled. 1910:Drivers/CMSIS/Include/core_cm7.h **** \return 1 Interrupt is enabled. 1911:Drivers/CMSIS/Include/core_cm7.h **** \note IRQn must not be negative. 1912:Drivers/CMSIS/Include/core_cm7.h **** */ ARM GAS /tmp/ccqopZd5.s page 35 1913:Drivers/CMSIS/Include/core_cm7.h **** __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) 1914:Drivers/CMSIS/Include/core_cm7.h **** { 1915:Drivers/CMSIS/Include/core_cm7.h **** if ((int32_t)(IRQn) >= 0) 1916:Drivers/CMSIS/Include/core_cm7.h **** { 1917:Drivers/CMSIS/Include/core_cm7.h **** return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL) 1918:Drivers/CMSIS/Include/core_cm7.h **** } 1919:Drivers/CMSIS/Include/core_cm7.h **** else 1920:Drivers/CMSIS/Include/core_cm7.h **** { 1921:Drivers/CMSIS/Include/core_cm7.h **** return(0U); 1922:Drivers/CMSIS/Include/core_cm7.h **** } 1923:Drivers/CMSIS/Include/core_cm7.h **** } 1924:Drivers/CMSIS/Include/core_cm7.h **** 1925:Drivers/CMSIS/Include/core_cm7.h **** 1926:Drivers/CMSIS/Include/core_cm7.h **** /** 1927:Drivers/CMSIS/Include/core_cm7.h **** \brief Disable Interrupt 1928:Drivers/CMSIS/Include/core_cm7.h **** \details Disables a device specific interrupt in the NVIC interrupt controller. 1929:Drivers/CMSIS/Include/core_cm7.h **** \param [in] IRQn Device specific interrupt number. 1930:Drivers/CMSIS/Include/core_cm7.h **** \note IRQn must not be negative. 1931:Drivers/CMSIS/Include/core_cm7.h **** */ 1932:Drivers/CMSIS/Include/core_cm7.h **** __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) 1933:Drivers/CMSIS/Include/core_cm7.h **** { 1934:Drivers/CMSIS/Include/core_cm7.h **** if ((int32_t)(IRQn) >= 0) 1935:Drivers/CMSIS/Include/core_cm7.h **** { 1936:Drivers/CMSIS/Include/core_cm7.h **** NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 1937:Drivers/CMSIS/Include/core_cm7.h **** __DSB(); 1938:Drivers/CMSIS/Include/core_cm7.h **** __ISB(); 1939:Drivers/CMSIS/Include/core_cm7.h **** } 1940:Drivers/CMSIS/Include/core_cm7.h **** } 1941:Drivers/CMSIS/Include/core_cm7.h **** 1942:Drivers/CMSIS/Include/core_cm7.h **** 1943:Drivers/CMSIS/Include/core_cm7.h **** /** 1944:Drivers/CMSIS/Include/core_cm7.h **** \brief Get Pending Interrupt 1945:Drivers/CMSIS/Include/core_cm7.h **** \details Reads the NVIC pending register and returns the pending bit for the specified device spe 1946:Drivers/CMSIS/Include/core_cm7.h **** \param [in] IRQn Device specific interrupt number. 1947:Drivers/CMSIS/Include/core_cm7.h **** \return 0 Interrupt status is not pending. 1948:Drivers/CMSIS/Include/core_cm7.h **** \return 1 Interrupt status is pending. 1949:Drivers/CMSIS/Include/core_cm7.h **** \note IRQn must not be negative. 1950:Drivers/CMSIS/Include/core_cm7.h **** */ 1951:Drivers/CMSIS/Include/core_cm7.h **** __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) 1952:Drivers/CMSIS/Include/core_cm7.h **** { 1953:Drivers/CMSIS/Include/core_cm7.h **** if ((int32_t)(IRQn) >= 0) 1954:Drivers/CMSIS/Include/core_cm7.h **** { 1955:Drivers/CMSIS/Include/core_cm7.h **** return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL) 1956:Drivers/CMSIS/Include/core_cm7.h **** } 1957:Drivers/CMSIS/Include/core_cm7.h **** else 1958:Drivers/CMSIS/Include/core_cm7.h **** { 1959:Drivers/CMSIS/Include/core_cm7.h **** return(0U); 1960:Drivers/CMSIS/Include/core_cm7.h **** } 1961:Drivers/CMSIS/Include/core_cm7.h **** } 1962:Drivers/CMSIS/Include/core_cm7.h **** 1963:Drivers/CMSIS/Include/core_cm7.h **** 1964:Drivers/CMSIS/Include/core_cm7.h **** /** 1965:Drivers/CMSIS/Include/core_cm7.h **** \brief Set Pending Interrupt 1966:Drivers/CMSIS/Include/core_cm7.h **** \details Sets the pending bit of a device specific interrupt in the NVIC pending register. 1967:Drivers/CMSIS/Include/core_cm7.h **** \param [in] IRQn Device specific interrupt number. 1968:Drivers/CMSIS/Include/core_cm7.h **** \note IRQn must not be negative. 1969:Drivers/CMSIS/Include/core_cm7.h **** */ ARM GAS /tmp/ccqopZd5.s page 36 1970:Drivers/CMSIS/Include/core_cm7.h **** __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) 1971:Drivers/CMSIS/Include/core_cm7.h **** { 1972:Drivers/CMSIS/Include/core_cm7.h **** if ((int32_t)(IRQn) >= 0) 1973:Drivers/CMSIS/Include/core_cm7.h **** { 1974:Drivers/CMSIS/Include/core_cm7.h **** NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 1975:Drivers/CMSIS/Include/core_cm7.h **** } 1976:Drivers/CMSIS/Include/core_cm7.h **** } 1977:Drivers/CMSIS/Include/core_cm7.h **** 1978:Drivers/CMSIS/Include/core_cm7.h **** 1979:Drivers/CMSIS/Include/core_cm7.h **** /** 1980:Drivers/CMSIS/Include/core_cm7.h **** \brief Clear Pending Interrupt 1981:Drivers/CMSIS/Include/core_cm7.h **** \details Clears the pending bit of a device specific interrupt in the NVIC pending register. 1982:Drivers/CMSIS/Include/core_cm7.h **** \param [in] IRQn Device specific interrupt number. 1983:Drivers/CMSIS/Include/core_cm7.h **** \note IRQn must not be negative. 1984:Drivers/CMSIS/Include/core_cm7.h **** */ 1985:Drivers/CMSIS/Include/core_cm7.h **** __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) 1986:Drivers/CMSIS/Include/core_cm7.h **** { 1987:Drivers/CMSIS/Include/core_cm7.h **** if ((int32_t)(IRQn) >= 0) 1988:Drivers/CMSIS/Include/core_cm7.h **** { 1989:Drivers/CMSIS/Include/core_cm7.h **** NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 1990:Drivers/CMSIS/Include/core_cm7.h **** } 1991:Drivers/CMSIS/Include/core_cm7.h **** } 1992:Drivers/CMSIS/Include/core_cm7.h **** 1993:Drivers/CMSIS/Include/core_cm7.h **** 1994:Drivers/CMSIS/Include/core_cm7.h **** /** 1995:Drivers/CMSIS/Include/core_cm7.h **** \brief Get Active Interrupt 1996:Drivers/CMSIS/Include/core_cm7.h **** \details Reads the active register in the NVIC and returns the active bit for the device specific 1997:Drivers/CMSIS/Include/core_cm7.h **** \param [in] IRQn Device specific interrupt number. 1998:Drivers/CMSIS/Include/core_cm7.h **** \return 0 Interrupt status is not active. 1999:Drivers/CMSIS/Include/core_cm7.h **** \return 1 Interrupt status is active. 2000:Drivers/CMSIS/Include/core_cm7.h **** \note IRQn must not be negative. 2001:Drivers/CMSIS/Include/core_cm7.h **** */ 2002:Drivers/CMSIS/Include/core_cm7.h **** __STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) 2003:Drivers/CMSIS/Include/core_cm7.h **** { 2004:Drivers/CMSIS/Include/core_cm7.h **** if ((int32_t)(IRQn) >= 0) 2005:Drivers/CMSIS/Include/core_cm7.h **** { 2006:Drivers/CMSIS/Include/core_cm7.h **** return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL) 2007:Drivers/CMSIS/Include/core_cm7.h **** } 2008:Drivers/CMSIS/Include/core_cm7.h **** else 2009:Drivers/CMSIS/Include/core_cm7.h **** { 2010:Drivers/CMSIS/Include/core_cm7.h **** return(0U); 2011:Drivers/CMSIS/Include/core_cm7.h **** } 2012:Drivers/CMSIS/Include/core_cm7.h **** } 2013:Drivers/CMSIS/Include/core_cm7.h **** 2014:Drivers/CMSIS/Include/core_cm7.h **** 2015:Drivers/CMSIS/Include/core_cm7.h **** /** 2016:Drivers/CMSIS/Include/core_cm7.h **** \brief Set Interrupt Priority 2017:Drivers/CMSIS/Include/core_cm7.h **** \details Sets the priority of a device specific interrupt or a processor exception. 2018:Drivers/CMSIS/Include/core_cm7.h **** The interrupt number can be positive to specify a device specific interrupt, 2019:Drivers/CMSIS/Include/core_cm7.h **** or negative to specify a processor exception. 2020:Drivers/CMSIS/Include/core_cm7.h **** \param [in] IRQn Interrupt number. 2021:Drivers/CMSIS/Include/core_cm7.h **** \param [in] priority Priority to set. 2022:Drivers/CMSIS/Include/core_cm7.h **** \note The priority cannot be set for every processor exception. 2023:Drivers/CMSIS/Include/core_cm7.h **** */ 2024:Drivers/CMSIS/Include/core_cm7.h **** __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) 2025:Drivers/CMSIS/Include/core_cm7.h **** { 2026:Drivers/CMSIS/Include/core_cm7.h **** if ((int32_t)(IRQn) >= 0) ARM GAS /tmp/ccqopZd5.s page 37 2027:Drivers/CMSIS/Include/core_cm7.h **** { 2028:Drivers/CMSIS/Include/core_cm7.h **** NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & ( 2029:Drivers/CMSIS/Include/core_cm7.h **** } 2030:Drivers/CMSIS/Include/core_cm7.h **** else 2031:Drivers/CMSIS/Include/core_cm7.h **** { 2032:Drivers/CMSIS/Include/core_cm7.h **** SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & ( 2033:Drivers/CMSIS/Include/core_cm7.h **** } 2034:Drivers/CMSIS/Include/core_cm7.h **** } 2035:Drivers/CMSIS/Include/core_cm7.h **** 2036:Drivers/CMSIS/Include/core_cm7.h **** 2037:Drivers/CMSIS/Include/core_cm7.h **** /** 2038:Drivers/CMSIS/Include/core_cm7.h **** \brief Get Interrupt Priority 2039:Drivers/CMSIS/Include/core_cm7.h **** \details Reads the priority of a device specific interrupt or a processor exception. 2040:Drivers/CMSIS/Include/core_cm7.h **** The interrupt number can be positive to specify a device specific interrupt, 2041:Drivers/CMSIS/Include/core_cm7.h **** or negative to specify a processor exception. 2042:Drivers/CMSIS/Include/core_cm7.h **** \param [in] IRQn Interrupt number. 2043:Drivers/CMSIS/Include/core_cm7.h **** \return Interrupt Priority. 2044:Drivers/CMSIS/Include/core_cm7.h **** Value is aligned automatically to the implemented priority bits of the microc 2045:Drivers/CMSIS/Include/core_cm7.h **** */ 2046:Drivers/CMSIS/Include/core_cm7.h **** __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) 2047:Drivers/CMSIS/Include/core_cm7.h **** { 2048:Drivers/CMSIS/Include/core_cm7.h **** 2049:Drivers/CMSIS/Include/core_cm7.h **** if ((int32_t)(IRQn) >= 0) 2050:Drivers/CMSIS/Include/core_cm7.h **** { 2051:Drivers/CMSIS/Include/core_cm7.h **** return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); 2052:Drivers/CMSIS/Include/core_cm7.h **** } 2053:Drivers/CMSIS/Include/core_cm7.h **** else 2054:Drivers/CMSIS/Include/core_cm7.h **** { 2055:Drivers/CMSIS/Include/core_cm7.h **** return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); 2056:Drivers/CMSIS/Include/core_cm7.h **** } 2057:Drivers/CMSIS/Include/core_cm7.h **** } 2058:Drivers/CMSIS/Include/core_cm7.h **** 2059:Drivers/CMSIS/Include/core_cm7.h **** 2060:Drivers/CMSIS/Include/core_cm7.h **** /** 2061:Drivers/CMSIS/Include/core_cm7.h **** \brief Encode Priority 2062:Drivers/CMSIS/Include/core_cm7.h **** \details Encodes the priority for an interrupt with the given priority group, 2063:Drivers/CMSIS/Include/core_cm7.h **** preemptive priority value, and subpriority value. 2064:Drivers/CMSIS/Include/core_cm7.h **** In case of a conflict between priority grouping and available 2065:Drivers/CMSIS/Include/core_cm7.h **** priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. 2066:Drivers/CMSIS/Include/core_cm7.h **** \param [in] PriorityGroup Used priority group. 2067:Drivers/CMSIS/Include/core_cm7.h **** \param [in] PreemptPriority Preemptive priority value (starting from 0). 2068:Drivers/CMSIS/Include/core_cm7.h **** \param [in] SubPriority Subpriority value (starting from 0). 2069:Drivers/CMSIS/Include/core_cm7.h **** \return Encoded priority. Value can be used in the function \ref NVIC_SetP 2070:Drivers/CMSIS/Include/core_cm7.h **** */ 2071:Drivers/CMSIS/Include/core_cm7.h **** __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uin 2072:Drivers/CMSIS/Include/core_cm7.h **** { 28 .loc 1 2072 1 view -0 29 .cfi_startproc 30 @ args = 0, pretend = 0, frame = 0 31 @ frame_needed = 0, uses_anonymous_args = 0 32 @ link register save eliminated. 2073:Drivers/CMSIS/Include/core_cm7.h **** uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used 33 .loc 1 2073 3 view .LVU1 34 .loc 1 2073 12 is_stmt 0 view .LVU2 35 0000 00F00700 and r0, r0, #7 36 .LVL1: 2074:Drivers/CMSIS/Include/core_cm7.h **** uint32_t PreemptPriorityBits; ARM GAS /tmp/ccqopZd5.s page 38 37 .loc 1 2074 3 is_stmt 1 view .LVU3 2075:Drivers/CMSIS/Include/core_cm7.h **** uint32_t SubPriorityBits; 38 .loc 1 2075 3 view .LVU4 2076:Drivers/CMSIS/Include/core_cm7.h **** 2077:Drivers/CMSIS/Include/core_cm7.h **** PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NV 39 .loc 1 2077 3 view .LVU5 40 .loc 1 2077 31 is_stmt 0 view .LVU6 41 0004 C0F1070C rsb ip, r0, #7 42 .loc 1 2077 23 view .LVU7 43 0008 BCF1040F cmp ip, #4 44 000c 28BF it cs 45 000e 4FF0040C movcs ip, #4 46 .LVL2: 2078:Drivers/CMSIS/Include/core_cm7.h **** SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint 47 .loc 1 2078 3 is_stmt 1 view .LVU8 48 .loc 1 2078 44 is_stmt 0 view .LVU9 49 0012 031D adds r3, r0, #4 50 .loc 1 2078 109 view .LVU10 51 0014 062B cmp r3, #6 52 0016 0CD9 bls .L3 53 .loc 1 2078 109 discriminator 1 view .LVU11 54 0018 C31E subs r3, r0, #3 55 .L2: 56 .LVL3: 2079:Drivers/CMSIS/Include/core_cm7.h **** 2080:Drivers/CMSIS/Include/core_cm7.h **** return ( 57 .loc 1 2080 3 is_stmt 1 discriminator 4 view .LVU12 2081:Drivers/CMSIS/Include/core_cm7.h **** ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits 58 .loc 1 2081 30 is_stmt 0 discriminator 4 view .LVU13 59 001a 4FF0FF30 mov r0, #-1 60 .LVL4: 61 .loc 1 2081 30 discriminator 4 view .LVU14 62 001e 00FA0CFC lsl ip, r0, ip 63 .LVL5: 64 .loc 1 2081 30 discriminator 4 view .LVU15 65 0022 21EA0C01 bic r1, r1, ip 66 .LVL6: 67 .loc 1 2081 82 discriminator 4 view .LVU16 68 0026 9940 lsls r1, r1, r3 2082:Drivers/CMSIS/Include/core_cm7.h **** ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) 69 .loc 1 2082 30 discriminator 4 view .LVU17 70 0028 9840 lsls r0, r0, r3 71 002a 22EA0000 bic r0, r2, r0 2083:Drivers/CMSIS/Include/core_cm7.h **** ); 2084:Drivers/CMSIS/Include/core_cm7.h **** } 72 .loc 1 2084 1 discriminator 4 view .LVU18 73 002e 0843 orrs r0, r0, r1 74 0030 7047 bx lr 75 .LVL7: 76 .L3: 2078:Drivers/CMSIS/Include/core_cm7.h **** 77 .loc 1 2078 109 view .LVU19 78 0032 0023 movs r3, #0 79 0034 F1E7 b .L2 80 .cfi_endproc 81 .LFE113: 83 .section .text.MX_SDMMC1_SD_Init,"ax",%progbits ARM GAS /tmp/ccqopZd5.s page 39 84 .align 1 85 .syntax unified 86 .thumb 87 .thumb_func 88 .fpu fpv5-d16 90 MX_SDMMC1_SD_Init: 91 .LFB1190: 92 .file 2 "Src/main.c" 1:Src/main.c **** /* USER CODE BEGIN Header */ 2:Src/main.c **** /** 3:Src/main.c **** ****************************************************************************** 4:Src/main.c **** * @file : main.c 5:Src/main.c **** * @brief : Main program body 6:Src/main.c **** ****************************************************************************** 7:Src/main.c **** * @attention 8:Src/main.c **** * 9:Src/main.c **** * Copyright (c) 2023 STMicroelectronics. 10:Src/main.c **** * All rights reserved. 11:Src/main.c **** * 12:Src/main.c **** * This software is licensed under terms that can be found in the LICENSE file 13:Src/main.c **** * in the root directory of this software component. 14:Src/main.c **** * If no LICENSE file comes with this software, it is provided AS-IS. 15:Src/main.c **** * 16:Src/main.c **** ****************************************************************************** 17:Src/main.c **** */ 18:Src/main.c **** /* USER CODE END Header */ 19:Src/main.c **** /* Includes ------------------------------------------------------------------*/ 20:Src/main.c **** #include "main.h" 21:Src/main.c **** #include "fatfs.h" 22:Src/main.c **** 23:Src/main.c **** /* Private includes ----------------------------------------------------------*/ 24:Src/main.c **** /* USER CODE BEGIN Includes */ 25:Src/main.c **** // #include "math.h" 26:Src/main.c **** #include "File_Handling.h" 27:Src/main.c **** #include 28:Src/main.c **** /* USER CODE END Includes */ 29:Src/main.c **** 30:Src/main.c **** /* Private typedef -----------------------------------------------------------*/ 31:Src/main.c **** /* USER CODE BEGIN PTD */ 32:Src/main.c **** 33:Src/main.c **** /* USER CODE END PTD */ 34:Src/main.c **** 35:Src/main.c **** /* Private define ------------------------------------------------------------*/ 36:Src/main.c **** /* USER CODE BEGIN PD */ 37:Src/main.c **** /* USER CODE END PD */ 38:Src/main.c **** 39:Src/main.c **** /* Private macro -------------------------------------------------------------*/ 40:Src/main.c **** /* USER CODE BEGIN PM */ 41:Src/main.c **** 42:Src/main.c **** /* USER CODE END PM */ 43:Src/main.c **** 44:Src/main.c **** /* Private variables ---------------------------------------------------------*/ 45:Src/main.c **** ADC_HandleTypeDef hadc1; 46:Src/main.c **** ADC_HandleTypeDef hadc3; 47:Src/main.c **** 48:Src/main.c **** SD_HandleTypeDef hsd1; 49:Src/main.c **** ARM GAS /tmp/ccqopZd5.s page 40 50:Src/main.c **** TIM_HandleTypeDef htim8; 51:Src/main.c **** TIM_HandleTypeDef htim10; 52:Src/main.c **** TIM_HandleTypeDef htim11; 53:Src/main.c **** 54:Src/main.c **** UART_HandleTypeDef huart8; 55:Src/main.c **** 56:Src/main.c **** /* USER CODE BEGIN PV */ 57:Src/main.c **** uint32_t TO6, TO6_before, TO6_stop, TO6_uart, SD_SEEK, SD_SLIDE, temp32, TO7, TO7_before, TO7_PID, 58:Src/main.c **** uint8_t uart_buf, CPU_state, CPU_state_old, UART_transmission_request, State_Data[2], UART_DATA[DL_ 59:Src/main.c **** uint16_t UART_rec_incr, UART_header, CS_result, temp16, Long_Data[DL_16], COMMAND[CL_16];//, SD_mat 60:Src/main.c **** FRESULT fresult; // result 61:Src/main.c **** int test; 62:Src/main.c **** unsigned long fgoto, sizeoffile;//file pointer of the file object & size of file FPGA_RECEIVE_DATA_ 63:Src/main.c **** 64:Src/main.c **** LDx_SetupTypeDef LD1_curr_setup, LD2_curr_setup, LD1_def_setup, LD2_def_setup; 65:Src/main.c **** Work_SetupTypeDef Curr_setup, Def_setup; 66:Src/main.c **** LDx_ParamTypeDef LD1_param, LD2_param; 67:Src/main.c **** 68:Src/main.c **** LD_Blinker_StateTypeDef LD_blinker; 69:Src/main.c **** 70:Src/main.c **** task_t task; 71:Src/main.c **** 72:Src/main.c **** 73:Src/main.c **** 74:Src/main.c **** /* USER CODE END PV */ 75:Src/main.c **** 76:Src/main.c **** /* Private function prototypes -----------------------------------------------*/ 77:Src/main.c **** void SystemClock_Config(void); 78:Src/main.c **** static void MX_GPIO_Init(void); 79:Src/main.c **** static void MX_DMA_Init(void); 80:Src/main.c **** static void MX_SPI4_Init(void); 81:Src/main.c **** static void MX_TIM2_Init(void); 82:Src/main.c **** static void MX_TIM5_Init(void); 83:Src/main.c **** static void MX_ADC1_Init(void); 84:Src/main.c **** static void MX_ADC3_Init(void); 85:Src/main.c **** static void MX_SPI2_Init(void); 86:Src/main.c **** static void MX_SPI5_Init(void); 87:Src/main.c **** static void MX_SPI6_Init(void); 88:Src/main.c **** static void MX_USART1_UART_Init(void); 89:Src/main.c **** static void MX_SDMMC1_SD_Init(void); 90:Src/main.c **** static void MX_TIM7_Init(void); 91:Src/main.c **** static void MX_TIM6_Init(void); 92:Src/main.c **** static void MX_TIM10_Init(void); 93:Src/main.c **** static void MX_UART8_Init(void); 94:Src/main.c **** static void MX_TIM8_Init(void); 95:Src/main.c **** static void MX_TIM11_Init(void); 96:Src/main.c **** /* USER CODE BEGIN PFP */ 97:Src/main.c **** static void Init_params(void); 98:Src/main.c **** static void Decode_uart(uint16_t *Command, LDx_SetupTypeDef *LD1_curr_setup, LDx_SetupTypeDef *LD2_ 99:Src/main.c **** static void Decode_task(uint16_t *Command, LDx_SetupTypeDef *LD1_curr_setup, LDx_SetupTypeDef *LD2_ 100:Src/main.c **** void Set_LTEC(uint8_t num, uint16_t DATA); 101:Src/main.c **** static uint16_t MPhD_T(uint8_t num); 102:Src/main.c **** static uint16_t Get_ADC(uint8_t num); 103:Src/main.c **** static uint16_t PID_Controller_Temp(LDx_SetupTypeDef * LDx_curr_setup, LDx_ParamTypeDef * LDx_resul 104:Src/main.c **** uint8_t CheckChecksum(uint16_t *pbuff); 105:Src/main.c **** uint16_t CalculateChecksum(uint16_t *pbuff, uint16_t len); 106:Src/main.c **** //int SD_Init(void); ARM GAS /tmp/ccqopZd5.s page 41 107:Src/main.c **** int SD_SAVE(uint16_t *pbuff); 108:Src/main.c **** //uint32_t Get_Length(void); 109:Src/main.c **** int SD_READ(uint16_t *pbuff); 110:Src/main.c **** int SD_REMOVE(void); 111:Src/main.c **** void USART_TX (uint8_t* dt, uint16_t sz); 112:Src/main.c **** void USART_TX_DMA (uint16_t sz); 113:Src/main.c **** static void Stop_TIM10(); 114:Src/main.c **** static void OUT_trigger(uint8_t); 115:Src/main.c **** /* USER CODE END PFP */ 116:Src/main.c **** 117:Src/main.c **** /* Private user code ---------------------------------------------------------*/ 118:Src/main.c **** /* USER CODE BEGIN 0 */ 119:Src/main.c **** 120:Src/main.c **** /* USER CODE END 0 */ 121:Src/main.c **** 122:Src/main.c **** /** 123:Src/main.c **** * @brief The application entry point. 124:Src/main.c **** * @retval int 125:Src/main.c **** */ 126:Src/main.c **** int main(void) 127:Src/main.c **** { 128:Src/main.c **** 129:Src/main.c **** /* USER CODE BEGIN 1 */ 130:Src/main.c **** HAL_StatusTypeDef st; 131:Src/main.c **** /* USER CODE END 1 */ 132:Src/main.c **** 133:Src/main.c **** /* MCU Configuration--------------------------------------------------------*/ 134:Src/main.c **** 135:Src/main.c **** /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ 136:Src/main.c **** HAL_Init(); 137:Src/main.c **** 138:Src/main.c **** /* USER CODE BEGIN Init */ 139:Src/main.c **** /*I hope you don't forget that first - MX_DMA_Init(); and than - MX_USART1_UART_Init();*/ 140:Src/main.c **** /* USER CODE END Init */ 141:Src/main.c **** 142:Src/main.c **** /* Configure the system clock */ 143:Src/main.c **** SystemClock_Config(); 144:Src/main.c **** 145:Src/main.c **** /* USER CODE BEGIN SysInit */ 146:Src/main.c **** 147:Src/main.c **** /* USER CODE END SysInit */ 148:Src/main.c **** 149:Src/main.c **** /* Initialize all configured peripherals */ 150:Src/main.c **** MX_GPIO_Init(); 151:Src/main.c **** MX_DMA_Init(); 152:Src/main.c **** MX_SPI4_Init(); 153:Src/main.c **** MX_FATFS_Init(); 154:Src/main.c **** MX_TIM2_Init(); 155:Src/main.c **** MX_TIM5_Init(); 156:Src/main.c **** MX_ADC1_Init(); 157:Src/main.c **** MX_ADC3_Init(); 158:Src/main.c **** MX_SPI2_Init(); 159:Src/main.c **** MX_SPI5_Init(); 160:Src/main.c **** MX_SPI6_Init(); 161:Src/main.c **** MX_USART1_UART_Init(); 162:Src/main.c **** MX_SDMMC1_SD_Init(); 163:Src/main.c **** MX_TIM7_Init(); ARM GAS /tmp/ccqopZd5.s page 42 164:Src/main.c **** MX_TIM6_Init(); 165:Src/main.c **** MX_TIM10_Init(); 166:Src/main.c **** MX_UART8_Init(); 167:Src/main.c **** MX_TIM8_Init(); 168:Src/main.c **** MX_TIM11_Init(); 169:Src/main.c **** /* USER CODE BEGIN 2 */ 170:Src/main.c **** Init_params(); 171:Src/main.c **** HAL_TIM_Base_Start(&htim11); 172:Src/main.c **** HAL_TIM_PWM_Start(&htim11, TIM_CHANNEL_1); //start modulating by Mach-Zander modulator 173:Src/main.c **** /* 174:Src/main.c **** if (HAL_GPIO_ReadPin(INP_0_GPIO_Port, INP_0_Pin) == 0){ 175:Src/main.c **** 176:Src/main.c **** CPU_state = DECODE_ENABLE; 177:Src/main.c **** } 178:Src/main.c **** */ 179:Src/main.c **** /* USER CODE END 2 */ 180:Src/main.c **** 181:Src/main.c **** /* Infinite loop */ 182:Src/main.c **** /* USER CODE BEGIN WHILE */ 183:Src/main.c **** while (1) 184:Src/main.c **** { 185:Src/main.c **** if ((HAL_GPIO_ReadPin(USB_FLAG_GPIO_Port, USB_FLAG_Pin)==GPIO_PIN_SET)&&(u_rx_flg == 0)) 186:Src/main.c **** { 187:Src/main.c **** //NVIC_DisableIRQ(USART1_IRQn); 188:Src/main.c **** LL_USART_EnableIT_PE(USART1); 189:Src/main.c **** LL_USART_EnableIT_RXNE(USART1); 190:Src/main.c **** LL_USART_EnableIT_ERROR(USART1); 191:Src/main.c **** NVIC_SetPriority(USART1_IRQn, 0); 192:Src/main.c **** NVIC_EnableIRQ(USART1_IRQn);//In other case you have FE error flag... 193:Src/main.c **** u_rx_flg = 1; 194:Src/main.c **** } 195:Src/main.c **** // else 196:Src/main.c **** // { 197:Src/main.c **** // //NVIC_DisableIRQ(USART1_IRQn); 198:Src/main.c **** // u_rx_flg = 0; 199:Src/main.c **** // } 200:Src/main.c **** switch (CPU_state) 201:Src/main.c **** { 202:Src/main.c **** case HALT://0 - Default state 203:Src/main.c **** CPU_state_old = HALT;//Save main current cycle 204:Src/main.c **** task.current_param = task.min_param; 205:Src/main.c **** Stop_TIM10(); 206:Src/main.c **** break; 207:Src/main.c **** case DECODE_ENABLE://1 - Decode rec. message 208:Src/main.c **** CS_result = CalculateChecksum(COMMAND, CL_16-2); 209:Src/main.c **** if (CheckChecksum(COMMAND)) 210:Src/main.c **** { 211:Src/main.c **** LL_SPI_Enable(SPI2);//Enable SPI for Laser1 DAC & TEC1 212:Src/main.c **** LL_SPI_Enable(SPI6);//Enable SPI for Laser2 DAC & TEC2 213:Src/main.c **** Decode_uart(COMMAND, &LD1_curr_setup, &LD2_curr_setup, &Curr_setup); 214:Src/main.c **** TO6_before = TO6; 215:Src/main.c **** //LD1_param.LD_TEMP_Before = LD1_param.LD_TEMP; 216:Src/main.c **** //LD2_param.LD_TEMP_Before = LD2_param.LD_TEMP; 217:Src/main.c **** CPU_state = WORK_ENABLE; 218:Src/main.c **** CPU_state_old = WORK_ENABLE;//Save main current cycle 219:Src/main.c **** } 220:Src/main.c **** else ARM GAS /tmp/ccqopZd5.s page 43 221:Src/main.c **** { 222:Src/main.c **** State_Data[0] |= UART_DECODE_ERR; 223:Src/main.c **** CPU_state = DEFAULT_ENABLE; 224:Src/main.c **** CPU_state_old = HALT;//Save main current cycle 225:Src/main.c **** } 226:Src/main.c **** UART_transmission_request = MESS_01; 227:Src/main.c **** break; 228:Src/main.c **** case DEFAULT_ENABLE://2 - Go to HALT 229:Src/main.c **** //Set current setup to default 230:Src/main.c **** task.current_param = task.min_param; 231:Src/main.c **** Stop_TIM10(); 232:Src/main.c **** Init_params(); 233:Src/main.c **** LL_SPI_Disable(SPI2);//Disable SPI for Laser1 DAC & TEC1 234:Src/main.c **** LL_SPI_Disable(SPI6);//Disable SPI for Laser2 DAC & TEC2 235:Src/main.c **** CPU_state = HALT; 236:Src/main.c **** CPU_state_old = HALT;//Save main current cycle 237:Src/main.c **** UART_transmission_request = MESS_01; 238:Src/main.c **** break; 239:Src/main.c **** case TRANS_S_ENABLE://3 - Transmith saved packet Before this operation must to be defaulting! 240:Src/main.c **** temp16 = SD_READ(&Long_Data[0]); 241:Src/main.c **** State_Data[0]|=temp16&0xff; 242:Src/main.c **** if (temp16==0) 243:Src/main.c **** { 244:Src/main.c **** UART_transmission_request = MESS_03; 245:Src/main.c **** } 246:Src/main.c **** else 247:Src/main.c **** { 248:Src/main.c **** UART_transmission_request = MESS_01; 249:Src/main.c **** } 250:Src/main.c **** CPU_state_old = HALT; 251:Src/main.c **** CPU_state = CPU_state_old;//Return to main current cycle 252:Src/main.c **** break; 253:Src/main.c **** case TRANS_ENABLE://4 - Transmith current packet 254:Src/main.c **** UART_transmission_request = MESS_02; 255:Src/main.c **** CPU_state = CPU_state_old;//Return to main current cycle 256:Src/main.c **** break; 257:Src/main.c **** case REMOVE_FILE://5 - Remove file from SD 258:Src/main.c **** State_Data[0]|=SD_REMOVE()&0xff; 259:Src/main.c **** UART_transmission_request = MESS_01; 260:Src/main.c **** CPU_state = CPU_state_old; 261:Src/main.c **** break; 262:Src/main.c **** case STATE://6 - Transmith state message 263:Src/main.c **** UART_transmission_request = MESS_01; 264:Src/main.c **** CPU_state = CPU_state_old;//Return to main current cycle 265:Src/main.c **** break; 266:Src/main.c **** case WORK_ENABLE://7 - Main work cycle 267:Src/main.c **** task.current_param = task.min_param; 268:Src/main.c **** Stop_TIM10(); 269:Src/main.c **** if (TO7>TO7_before)//Main work cycle go with the timer 7 (1000 us or 1 kHz) 270:Src/main.c **** { 271:Src/main.c **** TO7_before = TO7; 272:Src/main.c **** LD1_param.POWER = MPhD_T(1);//Get Data from monitor photodiode of LD1 273:Src/main.c **** LD1_param.POWER = MPhD_T(1);//Get Data from monitor photodiode of LD1 274:Src/main.c **** LD2_param.POWER = MPhD_T(2);//Get Data from monitor photodiode of LD2 275:Src/main.c **** LD2_param.POWER = MPhD_T(2);//Get Data from monitor photodiode of LD2 276:Src/main.c **** 277:Src/main.c **** //Correct temperature in all pulses ARM GAS /tmp/ccqopZd5.s page 44 278:Src/main.c **** (void) MPhD_T(3); 279:Src/main.c **** LD1_param.LD_CURR_TEMP = MPhD_T(3); 280:Src/main.c **** (void) MPhD_T(4); 281:Src/main.c **** LD2_param.LD_CURR_TEMP = MPhD_T(4); 282:Src/main.c **** temp16=PID_Controller_Temp(&LD1_curr_setup, &LD1_param, 1); 283:Src/main.c **** Set_LTEC(3, temp16);//Drive Laser TEC 1 284:Src/main.c **** temp16=PID_Controller_Temp(&LD2_curr_setup, &LD2_param, 2); 285:Src/main.c **** Set_LTEC(4, temp16);//Drive Laser TEC 2 286:Src/main.c **** 287:Src/main.c **** Long_Data[1] = LD1_param.POWER;//Translate Data from monitor photodiode of LD1 to Long_Data 288:Src/main.c **** Long_Data[2] = LD2_param.POWER;//Translate Data from monitor photodiode of LD2 to Long_Data 289:Src/main.c **** 290:Src/main.c **** Set_LTEC(1,LD1_curr_setup.CURRENT);//Drive Laser diode 1 291:Src/main.c **** Set_LTEC(2,LD2_curr_setup.CURRENT);//Drive Laser diode 2 292:Src/main.c **** 293:Src/main.c **** //Prepare DATA of internals ADCs 294:Src/main.c **** //Put the temperature of LD2 to Long_Data: 295:Src/main.c **** temp16 = Get_ADC(0); 296:Src/main.c **** temp16 = Get_ADC(1); 297:Src/main.c **** Long_Data[7] = temp16; // PA2 -- 3V_monitor // PB1 -- U_Rt1_ext_Gain 298:Src/main.c **** 299:Src/main.c **** //Put the temperature of LD2 to Long_Data: 300:Src/main.c **** temp16 = Get_ADC(1); 301:Src/main.c **** Long_Data[8] = temp16; // PB0 -- U_Rt2_ext_Gain // PB0 -- U_Rt2_ext_Gain 302:Src/main.c **** 303:Src/main.c **** //Put the temperature of LD2 to Long_Data: 304:Src/main.c **** temp16 = Get_ADC(1); 305:Src/main.c **** Long_Data[9] = temp16; // PB1 -- U_Rt1_ext_Gain // PA2 -- 3V_monitor 306:Src/main.c **** 307:Src/main.c **** //Put the temperature of LD2 to Long_Data: 308:Src/main.c **** temp16 = Get_ADC(1); 309:Src/main.c **** Long_Data[10] = temp16; // PC0 -- 5V1_monitor // PC0 -- 5V1_monitor 310:Src/main.c **** 311:Src/main.c **** //Put the temperature of LD2 to Long_Data: 312:Src/main.c **** temp16 = Get_ADC(1); 313:Src/main.c **** Long_Data[11] = temp16; // PC1 -- 5V2_monitor // PC1 -- 5V2_monitor 314:Src/main.c **** temp16 = Get_ADC(2); 315:Src/main.c **** 316:Src/main.c **** //Put the temperature of LD2 to Long_Data: 317:Src/main.c **** temp16 = Get_ADC(3); 318:Src/main.c **** temp16 = Get_ADC(4); 319:Src/main.c **** Long_Data[12] = temp16; 320:Src/main.c **** temp16 = Get_ADC(5); 321:Src/main.c **** 322:Src/main.c **** //Put the timer tick to Long_Data: 323:Src/main.c **** TO6_stop = TO6; 324:Src/main.c **** Long_Data[3] = (TO6_stop)&0xffff; 325:Src/main.c **** Long_Data[4] = (TO6_stop>>16)&0xffff; 326:Src/main.c **** 327:Src/main.c **** //Put the average temperature of LD1 to Long_Data: 328:Src/main.c **** Long_Data[5] = LD1_param.LD_CURR_TEMP; 329:Src/main.c **** 330:Src/main.c **** //Put the average temperature of LD2 to Long_Data: 331:Src/main.c **** Long_Data[6] = LD2_param.LD_CURR_TEMP; 332:Src/main.c **** 333:Src/main.c **** if (Curr_setup.SD_EN==1) 334:Src/main.c **** { ARM GAS /tmp/ccqopZd5.s page 45 335:Src/main.c **** CS_result = CalculateChecksum(&Long_Data[1], DL_16-2); 336:Src/main.c **** Long_Data[DL_16-1] = CS_result; 337:Src/main.c **** temp16 = SD_SAVE(&Long_Data[0]); 338:Src/main.c **** State_Data[0]|=temp16&0xff; 339:Src/main.c **** } 340:Src/main.c **** CPU_state_old = WORK_ENABLE;//Save main current cycle 341:Src/main.c **** } 342:Src/main.c **** break; 343:Src/main.c **** case DECODE_TASK: 344:Src/main.c **** if (CheckChecksum(COMMAND)) 345:Src/main.c **** { 346:Src/main.c **** Decode_task(COMMAND, &LD1_curr_setup, &LD2_curr_setup, &Curr_setup); 347:Src/main.c **** TO6_before = TO6; 348:Src/main.c **** CPU_state = RUN_TASK; 349:Src/main.c **** CPU_state_old = RUN_TASK;//Save main current cycle 350:Src/main.c **** } 351:Src/main.c **** else 352:Src/main.c **** { 353:Src/main.c **** State_Data[0] |= UART_DECODE_ERR; 354:Src/main.c **** CPU_state = DEFAULT_ENABLE; 355:Src/main.c **** CPU_state_old = HALT;//Save main current cycle 356:Src/main.c **** } 357:Src/main.c **** UART_transmission_request = MESS_01; 358:Src/main.c **** break; 359:Src/main.c **** case RUN_TASK: 360:Src/main.c **** switch (task.task_type) 361:Src/main.c **** { 362:Src/main.c **** case TT_CHANGE_CURR_1: 363:Src/main.c **** Set_LTEC(TT_CHANGE_CURR_2, task.curr); 364:Src/main.c **** (void) MPhD_T(TT_CHANGE_TEMP_1); 365:Src/main.c **** LD1_param.LD_CURR_TEMP = MPhD_T(TT_CHANGE_TEMP_1); 366:Src/main.c **** (void) MPhD_T(TT_CHANGE_TEMP_2); 367:Src/main.c **** LD2_param.LD_CURR_TEMP = MPhD_T(TT_CHANGE_TEMP_2); 368:Src/main.c **** temp16=PID_Controller_Temp(&LD1_curr_setup, &LD1_param, 1); 369:Src/main.c **** Set_LTEC(TT_CHANGE_TEMP_1, temp16);//Drive Laser TEC 1 370:Src/main.c **** temp16=PID_Controller_Temp(&LD2_curr_setup, &LD2_param, 2); 371:Src/main.c **** Set_LTEC(TT_CHANGE_TEMP_2, temp16);//Drive Laser TEC 2 372:Src/main.c **** 373:Src/main.c **** // Toggle pin for oscilloscope 374:Src/main.c **** HAL_GPIO_WritePin(GPIOD, GPIO_PIN_7, GPIO_PIN_SET); //start of the whole frequency sweep proc 375:Src/main.c **** HAL_GPIO_WritePin(GPIOD, GPIO_PIN_7, GPIO_PIN_RESET); 376:Src/main.c **** 377:Src/main.c **** st = HAL_TIM_Base_Start_IT(&htim10); 378:Src/main.c **** if (st != HAL_OK) 379:Src/main.c **** while(1); 380:Src/main.c **** 381:Src/main.c **** uint16_t step_counter = 0; 382:Src/main.c **** uint16_t trigger_counter = 0; 383:Src/main.c **** uint16_t trigger_step = (uint8_t )((task.max_param - task.current_param)/task.delta_param * 1 384:Src/main.c **** uint16_t task_sheduler = 0; 385:Src/main.c **** HAL_TIM_PWM_Start(&htim11, TIM_CHANNEL_1); //start modulating by Mach-Zander modulator 386:Src/main.c **** while (task.current_param < task.max_param) 387:Src/main.c **** { 388:Src/main.c **** if (TIM10_coflag) 389:Src/main.c **** { 390:Src/main.c **** Set_LTEC(TT_CHANGE_CURR_1, task.current_param); 391:Src/main.c **** TIM11 -> CNT = 0; // to link modulator phase ARM GAS /tmp/ccqopZd5.s page 46 392:Src/main.c **** task.current_param += task.delta_param; 393:Src/main.c **** TO10 = 0; 394:Src/main.c **** TIM10_coflag = 0; 395:Src/main.c **** 396:Src/main.c **** HAL_GPIO_WritePin(GPIOG, GPIO_PIN_9, GPIO_PIN_SET); // set the current step laser current t 397:Src/main.c **** HAL_GPIO_WritePin(GPIOG, GPIO_PIN_9, GPIO_PIN_RESET); 398:Src/main.c **** //* 399:Src/main.c **** if (step_counter % trigger_step == 0){ //trigger at every 60 step 400:Src/main.c **** OUT_trigger(trigger_counter); 401:Src/main.c **** ++trigger_counter; 402:Src/main.c **** } 403:Src/main.c **** ++step_counter; 404:Src/main.c **** //*/ 405:Src/main.c **** /* 406:Src/main.c **** ++task_sheduler; 407:Src/main.c **** if (task_sheduler >= 10){ 408:Src/main.c **** task_sheduler = 0; 409:Src/main.c **** } 410:Src/main.c **** //maintain stable temperature of laser 2 411:Src/main.c **** if (task_sheduler == 0){ 412:Src/main.c **** (void) MPhD_T(TT_CHANGE_TEMP_2); 413:Src/main.c **** LD2_param.LD_CURR_TEMP = MPhD_T(TT_CHANGE_TEMP_2); 414:Src/main.c **** temp16=PID_Controller_Temp(&LD2_curr_setup, &LD2_param, 2); 415:Src/main.c **** Set_LTEC(TT_CHANGE_TEMP_2, temp16);//Drive Laser TEC 2 416:Src/main.c **** } 417:Src/main.c **** //maintain stable temperature of laser 1 418:Src/main.c **** //* 419:Src/main.c **** if (task_sheduler == 5){ 420:Src/main.c **** (void) MPhD_T(TT_CHANGE_TEMP_1); 421:Src/main.c **** LD1_param.LD_CURR_TEMP = MPhD_T(TT_CHANGE_TEMP_1); 422:Src/main.c **** temp16=PID_Controller_Temp(&LD1_curr_setup, &LD1_param, 1); 423:Src/main.c **** Set_LTEC(TT_CHANGE_TEMP_1, temp16);//Drive Laser TEC 1 424:Src/main.c **** } 425:Src/main.c **** //*/ 426:Src/main.c **** } 427:Src/main.c **** } 428:Src/main.c **** HAL_TIM_PWM_Stop(&htim11, TIM_CHANNEL_1); //start modulating by Mach-Zander modulator 429:Src/main.c **** 430:Src/main.c **** Stop_TIM10(); 431:Src/main.c **** task.current_param = task.min_param; 432:Src/main.c **** Set_LTEC(TT_CHANGE_CURR_1, task.current_param); 433:Src/main.c **** if (task.tau > 3) 434:Src/main.c **** { 435:Src/main.c **** TIM10_period = htim10.Init.Period; 436:Src/main.c **** htim10.Init.Period = 9999; 437:Src/main.c **** TO10_counter = (task.tau - 1) * 100; 438:Src/main.c **** } 439:Src/main.c **** HAL_TIM_Base_Start_IT(&htim10); 440:Src/main.c **** break; 441:Src/main.c **** case TT_CHANGE_CURR_2: 442:Src/main.c **** //Blink laser 2 443:Src/main.c **** //* 444:Src/main.c **** Set_LTEC(TT_CHANGE_CURR_1, task.curr); 445:Src/main.c **** (void) MPhD_T(TT_CHANGE_TEMP_1); 446:Src/main.c **** LD1_param.LD_CURR_TEMP = MPhD_T(TT_CHANGE_TEMP_1); 447:Src/main.c **** (void) MPhD_T(TT_CHANGE_TEMP_2); 448:Src/main.c **** LD2_param.LD_CURR_TEMP = MPhD_T(TT_CHANGE_TEMP_2); ARM GAS /tmp/ccqopZd5.s page 47 449:Src/main.c **** temp16=PID_Controller_Temp(&LD1_curr_setup, &LD1_param, 1); 450:Src/main.c **** Set_LTEC(TT_CHANGE_TEMP_1, temp16);//Drive Laser TEC 1 451:Src/main.c **** temp16=PID_Controller_Temp(&LD2_curr_setup, &LD2_param, 2); 452:Src/main.c **** Set_LTEC(TT_CHANGE_TEMP_2, temp16);//Drive Laser TEC 2 453:Src/main.c **** 454:Src/main.c **** LD_blinker.task_type = 2; 455:Src/main.c **** LD_blinker.state = 0; // 0 -- disabled (do nothing); 1 -- update LD current; 2 -- blinking, L 456:Src/main.c **** //LD_blinker.param = task.current_param; 457:Src/main.c **** LD_blinker.param = 0; 458:Src/main.c **** LD_blinker.param = 1000; // LD2 current (in unspecified units) 459:Src/main.c **** LD_blinker.signal_port = OUT_10_GPIO_Port; 460:Src/main.c **** LD_blinker.signal_pin = OUT_10_Pin; 461:Src/main.c **** 462:Src/main.c **** TIM8->ARR = 10000; //zero to LD_blinker.param change frequency (also in unspecified units). 463:Src/main.c **** //When it is too low -- Desktop app crashes (there is not so much compute sources on MCU 464:Src/main.c **** st = HAL_TIM_Base_Start_IT(&htim8); 465:Src/main.c **** if (st != HAL_OK) 466:Src/main.c **** while(1); 467:Src/main.c **** // */ 468:Src/main.c **** 469:Src/main.c **** // Toggle pin for oscilloscope 470:Src/main.c **** HAL_GPIO_WritePin(GPIOD, GPIO_PIN_7, GPIO_PIN_SET); 471:Src/main.c **** uint32_t i = 10000; while (--i){} 472:Src/main.c **** HAL_GPIO_WritePin(GPIOD, GPIO_PIN_7, GPIO_PIN_RESET); 473:Src/main.c **** LD_blinker.state = 2; 474:Src/main.c **** 475:Src/main.c **** st = HAL_TIM_Base_Start_IT(&htim10); 476:Src/main.c **** if (st != HAL_OK) 477:Src/main.c **** while(1); 478:Src/main.c **** while (task.current_param < task.max_param) 479:Src/main.c **** { 480:Src/main.c **** if (TIM10_coflag) 481:Src/main.c **** { 482:Src/main.c **** //Set_LTEC(TT_CHANGE_CURR_2, task.current_param); 483:Src/main.c **** //LD_blinker.param = task.current_param; 484:Src/main.c **** //++LD_blinker.param; 485:Src/main.c **** task.current_param += task.delta_param; 486:Src/main.c **** TO10 = 0; 487:Src/main.c **** TIM10_coflag = 0; 488:Src/main.c **** 489:Src/main.c **** 490:Src/main.c **** } 491:Src/main.c **** } 492:Src/main.c **** HAL_TIM_Base_Stop(&htim10); 493:Src/main.c **** HAL_GPIO_WritePin(GPIOD, GPIO_PIN_7, GPIO_PIN_SET); 494:Src/main.c **** 495:Src/main.c **** HAL_GPIO_WritePin(GPIOD, GPIO_PIN_7, GPIO_PIN_RESET); 496:Src/main.c **** 497:Src/main.c **** HAL_TIM_Base_Stop_IT(&htim8); 498:Src/main.c **** TIM8->CNT = 0; 499:Src/main.c **** 500:Src/main.c **** Stop_TIM10(); 501:Src/main.c **** task.current_param = task.min_param; 502:Src/main.c **** Set_LTEC(TT_CHANGE_CURR_2, task.current_param); 503:Src/main.c **** if (task.tau > 3) 504:Src/main.c **** { 505:Src/main.c **** TIM10_period = htim10.Init.Period; ARM GAS /tmp/ccqopZd5.s page 48 506:Src/main.c **** htim10.Init.Period = 9999; 507:Src/main.c **** TO10_counter = (task.tau - 1) * 100; 508:Src/main.c **** } 509:Src/main.c **** HAL_TIM_Base_Start_IT(&htim10); 510:Src/main.c **** 511:Src/main.c **** 512:Src/main.c **** //*/ 513:Src/main.c **** 514:Src/main.c **** /* // Backup 515:Src/main.c **** Set_LTEC(TT_CHANGE_CURR_1, task.curr); 516:Src/main.c **** (void) MPhD_T(TT_CHANGE_TEMP_1); 517:Src/main.c **** LD1_param.LD_CURR_TEMP = MPhD_T(TT_CHANGE_TEMP_1); 518:Src/main.c **** (void) MPhD_T(TT_CHANGE_TEMP_2); 519:Src/main.c **** LD2_param.LD_CURR_TEMP = MPhD_T(TT_CHANGE_TEMP_2); 520:Src/main.c **** temp16=PID_Controller_Temp(&LD1_curr_setup, &LD1_param, 1); 521:Src/main.c **** Set_LTEC(TT_CHANGE_TEMP_1, temp16);//Drive Laser TEC 1 522:Src/main.c **** temp16=PID_Controller_Temp(&LD2_curr_setup, &LD2_param, 2); 523:Src/main.c **** Set_LTEC(TT_CHANGE_TEMP_2, temp16);//Drive Laser TEC 2 524:Src/main.c **** 525:Src/main.c **** // Toggle pin for oscilloscope 526:Src/main.c **** HAL_GPIO_WritePin(GPIOD, GPIO_PIN_7, GPIO_PIN_SET); 527:Src/main.c **** HAL_GPIO_WritePin(GPIOD, GPIO_PIN_7, GPIO_PIN_RESET); 528:Src/main.c **** 529:Src/main.c **** st = HAL_TIM_Base_Start_IT(&htim10); 530:Src/main.c **** if (st != HAL_OK) 531:Src/main.c **** while(1); 532:Src/main.c **** while (task.current_param < task.max_param) 533:Src/main.c **** { 534:Src/main.c **** if (TIM10_coflag) 535:Src/main.c **** { 536:Src/main.c **** Set_LTEC(TT_CHANGE_CURR_2, task.current_param); 537:Src/main.c **** task.current_param += task.delta_param; 538:Src/main.c **** TO10 = 0; 539:Src/main.c **** TIM10_coflag = 0; 540:Src/main.c **** 541:Src/main.c **** 542:Src/main.c **** } 543:Src/main.c **** } 544:Src/main.c **** Stop_TIM10(); 545:Src/main.c **** task.current_param = task.min_param; 546:Src/main.c **** Set_LTEC(TT_CHANGE_CURR_2, task.current_param); 547:Src/main.c **** if (task.tau > 3) 548:Src/main.c **** { 549:Src/main.c **** TIM10_period = htim10.Init.Period; 550:Src/main.c **** htim10.Init.Period = 9999; 551:Src/main.c **** TO10_counter = (task.tau - 1) * 100; 552:Src/main.c **** } 553:Src/main.c **** HAL_TIM_Base_Start_IT(&htim10); 554:Src/main.c **** */ 555:Src/main.c **** 556:Src/main.c **** 557:Src/main.c **** break; 558:Src/main.c **** case TT_CHANGE_TEMP_1: 559:Src/main.c **** // isn't implemented 560:Src/main.c **** break; 561:Src/main.c **** case TT_CHANGE_TEMP_2: 562:Src/main.c **** // isn't implemented ARM GAS /tmp/ccqopZd5.s page 49 563:Src/main.c **** break; 564:Src/main.c **** } 565:Src/main.c **** 566:Src/main.c **** if (TO7>TO7_before) 567:Src/main.c **** { 568:Src/main.c **** TO7_before = TO7; 569:Src/main.c **** 570:Src/main.c **** LD1_param.POWER = MPhD_T(1);//Get Data from monitor photodiode of LD1 571:Src/main.c **** LD1_param.POWER = MPhD_T(1);//Get Data from monitor photodiode of LD1 572:Src/main.c **** LD2_param.POWER = MPhD_T(2);//Get Data from monitor photodiode of LD2 573:Src/main.c **** LD2_param.POWER = MPhD_T(2);//Get Data from monitor photodiode of LD2 574:Src/main.c **** 575:Src/main.c **** Long_Data[1] = LD1_param.POWER;//Translate Data from monitor photodiode of LD1 to Long_Data 576:Src/main.c **** Long_Data[2] = LD2_param.POWER;//Translate Data from monitor photodiode of LD2 to Long_Data 577:Src/main.c **** 578:Src/main.c **** //Prepare DATA of internals ADCs 579:Src/main.c **** //Put the temperature of LD2 to Long_Data: 580:Src/main.c **** temp16 = Get_ADC(0); 581:Src/main.c **** temp16 = Get_ADC(1); 582:Src/main.c **** Long_Data[7] = temp16; 583:Src/main.c **** 584:Src/main.c **** //Put the temperature of LD2 to Long_Data: 585:Src/main.c **** temp16 = Get_ADC(1); 586:Src/main.c **** Long_Data[8] = temp16; 587:Src/main.c **** 588:Src/main.c **** //Put the temperature of LD2 to Long_Data: 589:Src/main.c **** temp16 = Get_ADC(1); 590:Src/main.c **** Long_Data[9] = temp16; 591:Src/main.c **** 592:Src/main.c **** //Put the temperature of LD2 to Long_Data: 593:Src/main.c **** temp16 = Get_ADC(1); 594:Src/main.c **** Long_Data[10] = temp16; 595:Src/main.c **** 596:Src/main.c **** //Put the temperature of LD2 to Long_Data: 597:Src/main.c **** temp16 = Get_ADC(1); 598:Src/main.c **** Long_Data[11] = temp16; 599:Src/main.c **** temp16 = Get_ADC(2); 600:Src/main.c **** 601:Src/main.c **** //Put the temperature of LD2 to Long_Data: 602:Src/main.c **** temp16 = Get_ADC(3); 603:Src/main.c **** temp16 = Get_ADC(4); 604:Src/main.c **** Long_Data[12] = temp16; 605:Src/main.c **** temp16 = Get_ADC(5); 606:Src/main.c **** 607:Src/main.c **** //Put the timer tick to Long_Data: 608:Src/main.c **** TO6_stop = TO6; 609:Src/main.c **** Long_Data[3] = (TO6_stop)&0xffff; 610:Src/main.c **** Long_Data[4] = (TO6_stop>>16)&0xffff; 611:Src/main.c **** 612:Src/main.c **** //Put the average temperature of LD1 to Long_Data: 613:Src/main.c **** Long_Data[5] = LD1_param.LD_CURR_TEMP; 614:Src/main.c **** 615:Src/main.c **** //Put the average temperature of LD2 to Long_Data: 616:Src/main.c **** Long_Data[6] = LD2_param.LD_CURR_TEMP; 617:Src/main.c **** } 618:Src/main.c **** while (!TIM10_coflag); 619:Src/main.c **** ARM GAS /tmp/ccqopZd5.s page 50 620:Src/main.c **** Stop_TIM10(); 621:Src/main.c **** 622:Src/main.c **** if (task.tau > 3) 623:Src/main.c **** { 624:Src/main.c **** htim10.Init.Period = TIM10_period; 625:Src/main.c **** TO10_counter = task.dt / 10; 626:Src/main.c **** } 627:Src/main.c **** 628:Src/main.c **** CPU_state_old = RUN_TASK; 629:Src/main.c **** break; 630:Src/main.c **** } 631:Src/main.c **** 632:Src/main.c **** switch (UART_transmission_request) 633:Src/main.c **** { 634:Src/main.c **** case MESS_01://Default state 635:Src/main.c **** USART_TX(State_Data,2); 636:Src/main.c **** //HAL_UART_Transmit(&huart1, State_Data, 2, 10); 637:Src/main.c **** State_Data[0]=0; 638:Src/main.c **** State_Data[1]=0;//All OK! 639:Src/main.c **** UART_transmission_request = NO_MESS; 640:Src/main.c **** break; 641:Src/main.c **** case MESS_02://Transmith packet 642:Src/main.c **** 643:Src/main.c **** //Find CS and put to Long_Data: 644:Src/main.c **** CS_result = CalculateChecksum(&Long_Data[1], DL_16-2); 645:Src/main.c **** Long_Data[DL_16-1] = CS_result; 646:Src/main.c **** 647:Src/main.c **** for (uint16_t i = 0; i < DL_16; i++) 648:Src/main.c **** { 649:Src/main.c **** UART_DATA[i*2] = (Long_Data[i])&0xff; 650:Src/main.c **** UART_DATA[i*2+1] = (Long_Data[i]>>8)&0xff; 651:Src/main.c **** } 652:Src/main.c **** //HAL_NVIC_SetPriority(DMA2_Stream7_IRQn, 0, 0); 653:Src/main.c **** //HAL_NVIC_EnableIRQ(DMA2_Stream7_IRQn); 654:Src/main.c **** //HAL_UART_Transmit_DMA(&huart1, UART_DATA, DL_8); 655:Src/main.c **** //huart1.gState = HAL_UART_STATE_READY; 656:Src/main.c **** //hdma_usart1_tx.State=HAL_DMA_STATE_BUSY; 657:Src/main.c **** USART_TX_DMA (DL_8);//Send data by USART using DMA 658:Src/main.c **** UART_transmission_request = NO_MESS; 659:Src/main.c **** break; 660:Src/main.c **** case MESS_03://Transmith saved packet 661:Src/main.c **** for (uint16_t i = 0; i < DL_16; i++) 662:Src/main.c **** { 663:Src/main.c **** UART_DATA[i*2] = (Long_Data[i])&0xff; 664:Src/main.c **** UART_DATA[i*2+1] = (Long_Data[i]>>8)&0xff; 665:Src/main.c **** } 666:Src/main.c **** //HAL_NVIC_EnableIRQ(DMA2_Stream7_IRQn); 667:Src/main.c **** //HAL_UART_Transmit_DMA(&huart1, UART_DATA, DL_8); 668:Src/main.c **** //huart1.gState = HAL_UART_STATE_READY; 669:Src/main.c **** //hdma_usart1_tx.State=HAL_DMA_STATE_BUSY; 670:Src/main.c **** USART_TX_DMA (DL_8);//Send data by USART using DMA 671:Src/main.c **** UART_transmission_request = NO_MESS; 672:Src/main.c **** break; 673:Src/main.c **** } 674:Src/main.c **** if ((flg_tmt==1)&&((TO6-TO6_uart)>100))//Uart timeout handle. if timeout beetween zero byte of 675:Src/main.c **** { 676:Src/main.c **** UART_rec_incr = 0;//Reset uart command counter ARM GAS /tmp/ccqopZd5.s page 51 677:Src/main.c **** State_Data[0] |= UART_ERR;//timeout error! 678:Src/main.c **** UART_transmission_request = MESS_01;//Send status 679:Src/main.c **** flg_tmt = 0;//Reset timeout flag 680:Src/main.c **** } 681:Src/main.c **** /* USER CODE END WHILE */ 682:Src/main.c **** 683:Src/main.c **** /* USER CODE BEGIN 3 */ 684:Src/main.c **** } 685:Src/main.c **** /* USER CODE END 3 */ 686:Src/main.c **** } 687:Src/main.c **** 688:Src/main.c **** /** 689:Src/main.c **** * @brief System Clock Configuration 690:Src/main.c **** * @retval None 691:Src/main.c **** */ 692:Src/main.c **** void SystemClock_Config(void) 693:Src/main.c **** { 694:Src/main.c **** RCC_OscInitTypeDef RCC_OscInitStruct = {0}; 695:Src/main.c **** RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; 696:Src/main.c **** 697:Src/main.c **** /** Configure the main internal regulator output voltage 698:Src/main.c **** */ 699:Src/main.c **** __HAL_RCC_PWR_CLK_ENABLE(); 700:Src/main.c **** __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); 701:Src/main.c **** 702:Src/main.c **** /** Initializes the RCC Oscillators according to the specified parameters 703:Src/main.c **** * in the RCC_OscInitTypeDef structure. 704:Src/main.c **** */ 705:Src/main.c **** RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; 706:Src/main.c **** RCC_OscInitStruct.HSEState = RCC_HSE_ON; 707:Src/main.c **** RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; 708:Src/main.c **** RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; 709:Src/main.c **** RCC_OscInitStruct.PLL.PLLM = 25; 710:Src/main.c **** RCC_OscInitStruct.PLL.PLLN = 368; 711:Src/main.c **** RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; 712:Src/main.c **** RCC_OscInitStruct.PLL.PLLQ = 8; 713:Src/main.c **** RCC_OscInitStruct.PLL.PLLR = 2; 714:Src/main.c **** if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) 715:Src/main.c **** { 716:Src/main.c **** Error_Handler(); 717:Src/main.c **** } 718:Src/main.c **** 719:Src/main.c **** /** Activate the Over-Drive mode 720:Src/main.c **** */ 721:Src/main.c **** if (HAL_PWREx_EnableOverDrive() != HAL_OK) 722:Src/main.c **** { 723:Src/main.c **** Error_Handler(); 724:Src/main.c **** } 725:Src/main.c **** 726:Src/main.c **** /** Initializes the CPU, AHB and APB buses clocks 727:Src/main.c **** */ 728:Src/main.c **** RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK 729:Src/main.c **** |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; 730:Src/main.c **** RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; 731:Src/main.c **** RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; 732:Src/main.c **** RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4; 733:Src/main.c **** RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; ARM GAS /tmp/ccqopZd5.s page 52 734:Src/main.c **** 735:Src/main.c **** if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_6) != HAL_OK) 736:Src/main.c **** { 737:Src/main.c **** Error_Handler(); 738:Src/main.c **** } 739:Src/main.c **** } 740:Src/main.c **** 741:Src/main.c **** /** 742:Src/main.c **** * @brief ADC1 Initialization Function 743:Src/main.c **** * @param None 744:Src/main.c **** * @retval None 745:Src/main.c **** */ 746:Src/main.c **** static void MX_ADC1_Init(void) 747:Src/main.c **** { 748:Src/main.c **** 749:Src/main.c **** /* USER CODE BEGIN ADC1_Init 0 */ 750:Src/main.c **** 751:Src/main.c **** /* USER CODE END ADC1_Init 0 */ 752:Src/main.c **** 753:Src/main.c **** ADC_ChannelConfTypeDef sConfig = {0}; 754:Src/main.c **** 755:Src/main.c **** /* USER CODE BEGIN ADC1_Init 1 */ 756:Src/main.c **** 757:Src/main.c **** /* USER CODE END ADC1_Init 1 */ 758:Src/main.c **** 759:Src/main.c **** /** Configure the global features of the ADC (Clock, Resolution, Data Alignment and number of con 760:Src/main.c **** */ 761:Src/main.c **** hadc1.Instance = ADC1; 762:Src/main.c **** hadc1.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV8; 763:Src/main.c **** hadc1.Init.Resolution = ADC_RESOLUTION_12B; 764:Src/main.c **** hadc1.Init.ScanConvMode = ADC_SCAN_ENABLE; 765:Src/main.c **** hadc1.Init.ContinuousConvMode = DISABLE; 766:Src/main.c **** hadc1.Init.DiscontinuousConvMode = DISABLE; 767:Src/main.c **** hadc1.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE; 768:Src/main.c **** hadc1.Init.ExternalTrigConv = ADC_SOFTWARE_START; 769:Src/main.c **** hadc1.Init.DataAlign = ADC_DATAALIGN_RIGHT; 770:Src/main.c **** hadc1.Init.NbrOfConversion = 5; 771:Src/main.c **** hadc1.Init.DMAContinuousRequests = DISABLE; 772:Src/main.c **** hadc1.Init.EOCSelection = ADC_EOC_SINGLE_CONV; 773:Src/main.c **** if (HAL_ADC_Init(&hadc1) != HAL_OK) 774:Src/main.c **** { 775:Src/main.c **** Error_Handler(); 776:Src/main.c **** } 777:Src/main.c **** 778:Src/main.c **** /** Configure for the selected ADC regular channel its corresponding rank in the sequencer and it 779:Src/main.c **** */ 780:Src/main.c **** sConfig.Channel = ADC_CHANNEL_9; 781:Src/main.c **** sConfig.Rank = ADC_REGULAR_RANK_1; 782:Src/main.c **** sConfig.SamplingTime = ADC_SAMPLETIME_480CYCLES; 783:Src/main.c **** if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 784:Src/main.c **** { 785:Src/main.c **** Error_Handler(); 786:Src/main.c **** } 787:Src/main.c **** 788:Src/main.c **** /** Configure for the selected ADC regular channel its corresponding rank in the sequencer and it 789:Src/main.c **** */ 790:Src/main.c **** sConfig.Channel = ADC_CHANNEL_8; ARM GAS /tmp/ccqopZd5.s page 53 791:Src/main.c **** sConfig.Rank = ADC_REGULAR_RANK_2; 792:Src/main.c **** if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 793:Src/main.c **** { 794:Src/main.c **** Error_Handler(); 795:Src/main.c **** } 796:Src/main.c **** 797:Src/main.c **** /** Configure for the selected ADC regular channel its corresponding rank in the sequencer and it 798:Src/main.c **** */ 799:Src/main.c **** sConfig.Channel = ADC_CHANNEL_2; 800:Src/main.c **** sConfig.Rank = ADC_REGULAR_RANK_3; 801:Src/main.c **** if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 802:Src/main.c **** { 803:Src/main.c **** Error_Handler(); 804:Src/main.c **** } 805:Src/main.c **** 806:Src/main.c **** /** Configure for the selected ADC regular channel its corresponding rank in the sequencer and it 807:Src/main.c **** */ 808:Src/main.c **** sConfig.Channel = ADC_CHANNEL_10; 809:Src/main.c **** sConfig.Rank = ADC_REGULAR_RANK_4; 810:Src/main.c **** if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 811:Src/main.c **** { 812:Src/main.c **** Error_Handler(); 813:Src/main.c **** } 814:Src/main.c **** 815:Src/main.c **** /** Configure for the selected ADC regular channel its corresponding rank in the sequencer and it 816:Src/main.c **** */ 817:Src/main.c **** sConfig.Channel = ADC_CHANNEL_11; 818:Src/main.c **** sConfig.Rank = ADC_REGULAR_RANK_5; 819:Src/main.c **** if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 820:Src/main.c **** { 821:Src/main.c **** Error_Handler(); 822:Src/main.c **** } 823:Src/main.c **** /* USER CODE BEGIN ADC1_Init 2 */ 824:Src/main.c **** 825:Src/main.c **** /* USER CODE END ADC1_Init 2 */ 826:Src/main.c **** 827:Src/main.c **** } 828:Src/main.c **** 829:Src/main.c **** /** 830:Src/main.c **** * @brief ADC3 Initialization Function 831:Src/main.c **** * @param None 832:Src/main.c **** * @retval None 833:Src/main.c **** */ 834:Src/main.c **** static void MX_ADC3_Init(void) 835:Src/main.c **** { 836:Src/main.c **** 837:Src/main.c **** /* USER CODE BEGIN ADC3_Init 0 */ 838:Src/main.c **** 839:Src/main.c **** /* USER CODE END ADC3_Init 0 */ 840:Src/main.c **** 841:Src/main.c **** ADC_ChannelConfTypeDef sConfig = {0}; 842:Src/main.c **** 843:Src/main.c **** /* USER CODE BEGIN ADC3_Init 1 */ 844:Src/main.c **** 845:Src/main.c **** /* USER CODE END ADC3_Init 1 */ 846:Src/main.c **** 847:Src/main.c **** /** Configure the global features of the ADC (Clock, Resolution, Data Alignment and number of con ARM GAS /tmp/ccqopZd5.s page 54 848:Src/main.c **** */ 849:Src/main.c **** hadc3.Instance = ADC3; 850:Src/main.c **** hadc3.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV8; 851:Src/main.c **** hadc3.Init.Resolution = ADC_RESOLUTION_12B; 852:Src/main.c **** hadc3.Init.ScanConvMode = ADC_SCAN_DISABLE; 853:Src/main.c **** hadc3.Init.ContinuousConvMode = DISABLE; 854:Src/main.c **** hadc3.Init.DiscontinuousConvMode = DISABLE; 855:Src/main.c **** hadc3.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE; 856:Src/main.c **** hadc3.Init.ExternalTrigConv = ADC_SOFTWARE_START; 857:Src/main.c **** hadc3.Init.DataAlign = ADC_DATAALIGN_RIGHT; 858:Src/main.c **** hadc3.Init.NbrOfConversion = 1; 859:Src/main.c **** hadc3.Init.DMAContinuousRequests = DISABLE; 860:Src/main.c **** hadc3.Init.EOCSelection = ADC_EOC_SINGLE_CONV; 861:Src/main.c **** if (HAL_ADC_Init(&hadc3) != HAL_OK) 862:Src/main.c **** { 863:Src/main.c **** Error_Handler(); 864:Src/main.c **** } 865:Src/main.c **** 866:Src/main.c **** /** Configure for the selected ADC regular channel its corresponding rank in the sequencer and it 867:Src/main.c **** */ 868:Src/main.c **** sConfig.Channel = ADC_CHANNEL_15; 869:Src/main.c **** sConfig.Rank = ADC_REGULAR_RANK_1; 870:Src/main.c **** sConfig.SamplingTime = ADC_SAMPLETIME_480CYCLES; 871:Src/main.c **** if (HAL_ADC_ConfigChannel(&hadc3, &sConfig) != HAL_OK) 872:Src/main.c **** { 873:Src/main.c **** Error_Handler(); 874:Src/main.c **** } 875:Src/main.c **** /* USER CODE BEGIN ADC3_Init 2 */ 876:Src/main.c **** 877:Src/main.c **** /* USER CODE END ADC3_Init 2 */ 878:Src/main.c **** 879:Src/main.c **** } 880:Src/main.c **** 881:Src/main.c **** /** 882:Src/main.c **** * @brief SDMMC1 Initialization Function 883:Src/main.c **** * @param None 884:Src/main.c **** * @retval None 885:Src/main.c **** */ 886:Src/main.c **** static void MX_SDMMC1_SD_Init(void) 887:Src/main.c **** { 93 .loc 2 887 1 is_stmt 1 view -0 94 .cfi_startproc 95 @ args = 0, pretend = 0, frame = 0 96 @ frame_needed = 0, uses_anonymous_args = 0 97 @ link register save eliminated. 888:Src/main.c **** 889:Src/main.c **** /* USER CODE BEGIN SDMMC1_Init 0 */ 890:Src/main.c **** 891:Src/main.c **** /* USER CODE END SDMMC1_Init 0 */ 892:Src/main.c **** 893:Src/main.c **** /* USER CODE BEGIN SDMMC1_Init 1 */ 894:Src/main.c **** 895:Src/main.c **** /* USER CODE END SDMMC1_Init 1 */ 896:Src/main.c **** hsd1.Instance = SDMMC1; 98 .loc 2 896 3 view .LVU21 99 .loc 2 896 17 is_stmt 0 view .LVU22 100 0000 064B ldr r3, .L5 ARM GAS /tmp/ccqopZd5.s page 55 101 0002 074A ldr r2, .L5+4 102 0004 1A60 str r2, [r3] 897:Src/main.c **** hsd1.Init.ClockEdge = SDMMC_CLOCK_EDGE_RISING; 103 .loc 2 897 3 is_stmt 1 view .LVU23 104 .loc 2 897 23 is_stmt 0 view .LVU24 105 0006 0022 movs r2, #0 106 0008 5A60 str r2, [r3, #4] 898:Src/main.c **** hsd1.Init.ClockBypass = SDMMC_CLOCK_BYPASS_DISABLE; 107 .loc 2 898 3 is_stmt 1 view .LVU25 108 .loc 2 898 25 is_stmt 0 view .LVU26 109 000a 9A60 str r2, [r3, #8] 899:Src/main.c **** hsd1.Init.ClockPowerSave = SDMMC_CLOCK_POWER_SAVE_DISABLE; 110 .loc 2 899 3 is_stmt 1 view .LVU27 111 .loc 2 899 28 is_stmt 0 view .LVU28 112 000c DA60 str r2, [r3, #12] 900:Src/main.c **** hsd1.Init.BusWide = SDMMC_BUS_WIDE_4B; 113 .loc 2 900 3 is_stmt 1 view .LVU29 114 .loc 2 900 21 is_stmt 0 view .LVU30 115 000e 4FF40061 mov r1, #2048 116 0012 1961 str r1, [r3, #16] 901:Src/main.c **** hsd1.Init.HardwareFlowControl = SDMMC_HARDWARE_FLOW_CONTROL_DISABLE; 117 .loc 2 901 3 is_stmt 1 view .LVU31 118 .loc 2 901 33 is_stmt 0 view .LVU32 119 0014 5A61 str r2, [r3, #20] 902:Src/main.c **** hsd1.Init.ClockDiv = 20; 120 .loc 2 902 3 is_stmt 1 view .LVU33 121 .loc 2 902 22 is_stmt 0 view .LVU34 122 0016 1422 movs r2, #20 123 0018 9A61 str r2, [r3, #24] 903:Src/main.c **** /* USER CODE BEGIN SDMMC1_Init 2 */ 904:Src/main.c **** 905:Src/main.c **** /* USER CODE END SDMMC1_Init 2 */ 906:Src/main.c **** 907:Src/main.c **** } 124 .loc 2 907 1 view .LVU35 125 001a 7047 bx lr 126 .L6: 127 .align 2 128 .L5: 129 001c 00000000 .word .LANCHOR0 130 0020 002C0140 .word 1073818624 131 .cfi_endproc 132 .LFE1190: 134 .section .text.MX_DMA_Init,"ax",%progbits 135 .align 1 136 .syntax unified 137 .thumb 138 .thumb_func 139 .fpu fpv5-d16 141 MX_DMA_Init: 142 .LFB1204: 908:Src/main.c **** 909:Src/main.c **** /** 910:Src/main.c **** * @brief SPI2 Initialization Function 911:Src/main.c **** * @param None 912:Src/main.c **** * @retval None 913:Src/main.c **** */ ARM GAS /tmp/ccqopZd5.s page 56 914:Src/main.c **** static void MX_SPI2_Init(void) 915:Src/main.c **** { 916:Src/main.c **** 917:Src/main.c **** /* USER CODE BEGIN SPI2_Init 0 */ 918:Src/main.c **** 919:Src/main.c **** /* USER CODE END SPI2_Init 0 */ 920:Src/main.c **** 921:Src/main.c **** LL_SPI_InitTypeDef SPI_InitStruct = {0}; 922:Src/main.c **** 923:Src/main.c **** LL_GPIO_InitTypeDef GPIO_InitStruct = {0}; 924:Src/main.c **** 925:Src/main.c **** /* Peripheral clock enable */ 926:Src/main.c **** LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_SPI2); 927:Src/main.c **** 928:Src/main.c **** LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_GPIOB); 929:Src/main.c **** /**SPI2 GPIO Configuration 930:Src/main.c **** PB13 ------> SPI2_SCK 931:Src/main.c **** PB15 ------> SPI2_MOSI 932:Src/main.c **** */ 933:Src/main.c **** GPIO_InitStruct.Pin = LL_GPIO_PIN_13; 934:Src/main.c **** GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE; 935:Src/main.c **** GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH; 936:Src/main.c **** GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; 937:Src/main.c **** GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; 938:Src/main.c **** GPIO_InitStruct.Alternate = LL_GPIO_AF_5; 939:Src/main.c **** LL_GPIO_Init(GPIOB, &GPIO_InitStruct); 940:Src/main.c **** 941:Src/main.c **** GPIO_InitStruct.Pin = LL_GPIO_PIN_15; 942:Src/main.c **** GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE; 943:Src/main.c **** GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH; 944:Src/main.c **** GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; 945:Src/main.c **** GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; 946:Src/main.c **** GPIO_InitStruct.Alternate = LL_GPIO_AF_5; 947:Src/main.c **** LL_GPIO_Init(GPIOB, &GPIO_InitStruct); 948:Src/main.c **** 949:Src/main.c **** /* USER CODE BEGIN SPI2_Init 1 */ 950:Src/main.c **** 951:Src/main.c **** /* USER CODE END SPI2_Init 1 */ 952:Src/main.c **** /* SPI2 parameter configuration*/ 953:Src/main.c **** SPI_InitStruct.TransferDirection = LL_SPI_FULL_DUPLEX; 954:Src/main.c **** SPI_InitStruct.Mode = LL_SPI_MODE_MASTER; 955:Src/main.c **** SPI_InitStruct.DataWidth = LL_SPI_DATAWIDTH_16BIT; 956:Src/main.c **** SPI_InitStruct.ClockPolarity = LL_SPI_POLARITY_HIGH; 957:Src/main.c **** SPI_InitStruct.ClockPhase = LL_SPI_PHASE_2EDGE; 958:Src/main.c **** SPI_InitStruct.NSS = LL_SPI_NSS_SOFT; 959:Src/main.c **** SPI_InitStruct.BaudRate = LL_SPI_BAUDRATEPRESCALER_DIV8; 960:Src/main.c **** SPI_InitStruct.BitOrder = LL_SPI_MSB_FIRST; 961:Src/main.c **** SPI_InitStruct.CRCCalculation = LL_SPI_CRCCALCULATION_DISABLE; 962:Src/main.c **** SPI_InitStruct.CRCPoly = 7; 963:Src/main.c **** LL_SPI_Init(SPI2, &SPI_InitStruct); 964:Src/main.c **** LL_SPI_SetStandard(SPI2, LL_SPI_PROTOCOL_MOTOROLA); 965:Src/main.c **** LL_SPI_DisableNSSPulseMgt(SPI2); 966:Src/main.c **** /* USER CODE BEGIN SPI2_Init 2 */ 967:Src/main.c **** 968:Src/main.c **** /* USER CODE END SPI2_Init 2 */ 969:Src/main.c **** 970:Src/main.c **** } ARM GAS /tmp/ccqopZd5.s page 57 971:Src/main.c **** 972:Src/main.c **** /** 973:Src/main.c **** * @brief SPI4 Initialization Function 974:Src/main.c **** * @param None 975:Src/main.c **** * @retval None 976:Src/main.c **** */ 977:Src/main.c **** static void MX_SPI4_Init(void) 978:Src/main.c **** { 979:Src/main.c **** 980:Src/main.c **** /* USER CODE BEGIN SPI4_Init 0 */ 981:Src/main.c **** 982:Src/main.c **** /* USER CODE END SPI4_Init 0 */ 983:Src/main.c **** 984:Src/main.c **** LL_SPI_InitTypeDef SPI_InitStruct = {0}; 985:Src/main.c **** 986:Src/main.c **** LL_GPIO_InitTypeDef GPIO_InitStruct = {0}; 987:Src/main.c **** 988:Src/main.c **** /* Peripheral clock enable */ 989:Src/main.c **** LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_SPI4); 990:Src/main.c **** 991:Src/main.c **** LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_GPIOE); 992:Src/main.c **** /**SPI4 GPIO Configuration 993:Src/main.c **** PE12 ------> SPI4_SCK 994:Src/main.c **** PE13 ------> SPI4_MISO 995:Src/main.c **** */ 996:Src/main.c **** GPIO_InitStruct.Pin = LL_GPIO_PIN_12; 997:Src/main.c **** GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE; 998:Src/main.c **** GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH; 999:Src/main.c **** GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; 1000:Src/main.c **** GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; 1001:Src/main.c **** GPIO_InitStruct.Alternate = LL_GPIO_AF_5; 1002:Src/main.c **** LL_GPIO_Init(GPIOE, &GPIO_InitStruct); 1003:Src/main.c **** 1004:Src/main.c **** GPIO_InitStruct.Pin = LL_GPIO_PIN_13; 1005:Src/main.c **** GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE; 1006:Src/main.c **** GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH; 1007:Src/main.c **** GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; 1008:Src/main.c **** GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; 1009:Src/main.c **** GPIO_InitStruct.Alternate = LL_GPIO_AF_5; 1010:Src/main.c **** LL_GPIO_Init(GPIOE, &GPIO_InitStruct); 1011:Src/main.c **** 1012:Src/main.c **** /* USER CODE BEGIN SPI4_Init 1 */ 1013:Src/main.c **** 1014:Src/main.c **** /* USER CODE END SPI4_Init 1 */ 1015:Src/main.c **** /* SPI4 parameter configuration*/ 1016:Src/main.c **** SPI_InitStruct.TransferDirection = LL_SPI_SIMPLEX_RX; 1017:Src/main.c **** SPI_InitStruct.Mode = LL_SPI_MODE_MASTER; 1018:Src/main.c **** SPI_InitStruct.DataWidth = LL_SPI_DATAWIDTH_16BIT; 1019:Src/main.c **** SPI_InitStruct.ClockPolarity = LL_SPI_POLARITY_HIGH; 1020:Src/main.c **** SPI_InitStruct.ClockPhase = LL_SPI_PHASE_1EDGE; 1021:Src/main.c **** SPI_InitStruct.NSS = LL_SPI_NSS_SOFT; 1022:Src/main.c **** SPI_InitStruct.BaudRate = LL_SPI_BAUDRATEPRESCALER_DIV16; 1023:Src/main.c **** SPI_InitStruct.BitOrder = LL_SPI_MSB_FIRST; 1024:Src/main.c **** SPI_InitStruct.CRCCalculation = LL_SPI_CRCCALCULATION_DISABLE; 1025:Src/main.c **** SPI_InitStruct.CRCPoly = 7; 1026:Src/main.c **** LL_SPI_Init(SPI4, &SPI_InitStruct); 1027:Src/main.c **** LL_SPI_SetStandard(SPI4, LL_SPI_PROTOCOL_MOTOROLA); ARM GAS /tmp/ccqopZd5.s page 58 1028:Src/main.c **** LL_SPI_DisableNSSPulseMgt(SPI4); 1029:Src/main.c **** /* USER CODE BEGIN SPI4_Init 2 */ 1030:Src/main.c **** 1031:Src/main.c **** /* USER CODE END SPI4_Init 2 */ 1032:Src/main.c **** 1033:Src/main.c **** } 1034:Src/main.c **** 1035:Src/main.c **** /** 1036:Src/main.c **** * @brief SPI5 Initialization Function 1037:Src/main.c **** * @param None 1038:Src/main.c **** * @retval None 1039:Src/main.c **** */ 1040:Src/main.c **** static void MX_SPI5_Init(void) 1041:Src/main.c **** { 1042:Src/main.c **** 1043:Src/main.c **** /* USER CODE BEGIN SPI5_Init 0 */ 1044:Src/main.c **** 1045:Src/main.c **** /* USER CODE END SPI5_Init 0 */ 1046:Src/main.c **** 1047:Src/main.c **** LL_SPI_InitTypeDef SPI_InitStruct = {0}; 1048:Src/main.c **** 1049:Src/main.c **** LL_GPIO_InitTypeDef GPIO_InitStruct = {0}; 1050:Src/main.c **** 1051:Src/main.c **** /* Peripheral clock enable */ 1052:Src/main.c **** LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_SPI5); 1053:Src/main.c **** 1054:Src/main.c **** LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_GPIOF); 1055:Src/main.c **** /**SPI5 GPIO Configuration 1056:Src/main.c **** PF7 ------> SPI5_SCK 1057:Src/main.c **** PF8 ------> SPI5_MISO 1058:Src/main.c **** */ 1059:Src/main.c **** GPIO_InitStruct.Pin = LL_GPIO_PIN_7; 1060:Src/main.c **** GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE; 1061:Src/main.c **** GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH; 1062:Src/main.c **** GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; 1063:Src/main.c **** GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; 1064:Src/main.c **** GPIO_InitStruct.Alternate = LL_GPIO_AF_5; 1065:Src/main.c **** LL_GPIO_Init(GPIOF, &GPIO_InitStruct); 1066:Src/main.c **** 1067:Src/main.c **** GPIO_InitStruct.Pin = LL_GPIO_PIN_8; 1068:Src/main.c **** GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE; 1069:Src/main.c **** GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH; 1070:Src/main.c **** GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; 1071:Src/main.c **** GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; 1072:Src/main.c **** GPIO_InitStruct.Alternate = LL_GPIO_AF_5; 1073:Src/main.c **** LL_GPIO_Init(GPIOF, &GPIO_InitStruct); 1074:Src/main.c **** 1075:Src/main.c **** /* USER CODE BEGIN SPI5_Init 1 */ 1076:Src/main.c **** 1077:Src/main.c **** /* USER CODE END SPI5_Init 1 */ 1078:Src/main.c **** /* SPI5 parameter configuration*/ 1079:Src/main.c **** SPI_InitStruct.TransferDirection = LL_SPI_SIMPLEX_RX; 1080:Src/main.c **** SPI_InitStruct.Mode = LL_SPI_MODE_MASTER; 1081:Src/main.c **** SPI_InitStruct.DataWidth = LL_SPI_DATAWIDTH_16BIT; 1082:Src/main.c **** SPI_InitStruct.ClockPolarity = LL_SPI_POLARITY_HIGH; 1083:Src/main.c **** SPI_InitStruct.ClockPhase = LL_SPI_PHASE_1EDGE; 1084:Src/main.c **** SPI_InitStruct.NSS = LL_SPI_NSS_SOFT; ARM GAS /tmp/ccqopZd5.s page 59 1085:Src/main.c **** SPI_InitStruct.BaudRate = LL_SPI_BAUDRATEPRESCALER_DIV16; 1086:Src/main.c **** SPI_InitStruct.BitOrder = LL_SPI_MSB_FIRST; 1087:Src/main.c **** SPI_InitStruct.CRCCalculation = LL_SPI_CRCCALCULATION_DISABLE; 1088:Src/main.c **** SPI_InitStruct.CRCPoly = 7; 1089:Src/main.c **** LL_SPI_Init(SPI5, &SPI_InitStruct); 1090:Src/main.c **** LL_SPI_SetStandard(SPI5, LL_SPI_PROTOCOL_MOTOROLA); 1091:Src/main.c **** LL_SPI_DisableNSSPulseMgt(SPI5); 1092:Src/main.c **** /* USER CODE BEGIN SPI5_Init 2 */ 1093:Src/main.c **** 1094:Src/main.c **** /* USER CODE END SPI5_Init 2 */ 1095:Src/main.c **** 1096:Src/main.c **** } 1097:Src/main.c **** 1098:Src/main.c **** /** 1099:Src/main.c **** * @brief SPI6 Initialization Function 1100:Src/main.c **** * @param None 1101:Src/main.c **** * @retval None 1102:Src/main.c **** */ 1103:Src/main.c **** static void MX_SPI6_Init(void) 1104:Src/main.c **** { 1105:Src/main.c **** 1106:Src/main.c **** /* USER CODE BEGIN SPI6_Init 0 */ 1107:Src/main.c **** 1108:Src/main.c **** /* USER CODE END SPI6_Init 0 */ 1109:Src/main.c **** 1110:Src/main.c **** LL_SPI_InitTypeDef SPI_InitStruct = {0}; 1111:Src/main.c **** 1112:Src/main.c **** LL_GPIO_InitTypeDef GPIO_InitStruct = {0}; 1113:Src/main.c **** 1114:Src/main.c **** /* Peripheral clock enable */ 1115:Src/main.c **** LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_SPI6); 1116:Src/main.c **** 1117:Src/main.c **** LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_GPIOA); 1118:Src/main.c **** /**SPI6 GPIO Configuration 1119:Src/main.c **** PA5 ------> SPI6_SCK 1120:Src/main.c **** PA7 ------> SPI6_MOSI 1121:Src/main.c **** */ 1122:Src/main.c **** GPIO_InitStruct.Pin = LL_GPIO_PIN_5; 1123:Src/main.c **** GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE; 1124:Src/main.c **** GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH; 1125:Src/main.c **** GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; 1126:Src/main.c **** GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; 1127:Src/main.c **** GPIO_InitStruct.Alternate = LL_GPIO_AF_8; 1128:Src/main.c **** LL_GPIO_Init(GPIOA, &GPIO_InitStruct); 1129:Src/main.c **** 1130:Src/main.c **** GPIO_InitStruct.Pin = LL_GPIO_PIN_7; 1131:Src/main.c **** GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE; 1132:Src/main.c **** GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH; 1133:Src/main.c **** GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; 1134:Src/main.c **** GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; 1135:Src/main.c **** GPIO_InitStruct.Alternate = LL_GPIO_AF_8; 1136:Src/main.c **** LL_GPIO_Init(GPIOA, &GPIO_InitStruct); 1137:Src/main.c **** 1138:Src/main.c **** /* USER CODE BEGIN SPI6_Init 1 */ 1139:Src/main.c **** 1140:Src/main.c **** /* USER CODE END SPI6_Init 1 */ 1141:Src/main.c **** /* SPI6 parameter configuration*/ ARM GAS /tmp/ccqopZd5.s page 60 1142:Src/main.c **** SPI_InitStruct.TransferDirection = LL_SPI_FULL_DUPLEX; 1143:Src/main.c **** SPI_InitStruct.Mode = LL_SPI_MODE_MASTER; 1144:Src/main.c **** SPI_InitStruct.DataWidth = LL_SPI_DATAWIDTH_16BIT; 1145:Src/main.c **** SPI_InitStruct.ClockPolarity = LL_SPI_POLARITY_HIGH; 1146:Src/main.c **** SPI_InitStruct.ClockPhase = LL_SPI_PHASE_2EDGE; 1147:Src/main.c **** SPI_InitStruct.NSS = LL_SPI_NSS_SOFT; 1148:Src/main.c **** SPI_InitStruct.BaudRate = LL_SPI_BAUDRATEPRESCALER_DIV16; 1149:Src/main.c **** SPI_InitStruct.BitOrder = LL_SPI_MSB_FIRST; 1150:Src/main.c **** SPI_InitStruct.CRCCalculation = LL_SPI_CRCCALCULATION_DISABLE; 1151:Src/main.c **** SPI_InitStruct.CRCPoly = 7; 1152:Src/main.c **** LL_SPI_Init(SPI6, &SPI_InitStruct); 1153:Src/main.c **** LL_SPI_SetStandard(SPI6, LL_SPI_PROTOCOL_MOTOROLA); 1154:Src/main.c **** LL_SPI_DisableNSSPulseMgt(SPI6); 1155:Src/main.c **** /* USER CODE BEGIN SPI6_Init 2 */ 1156:Src/main.c **** 1157:Src/main.c **** /* USER CODE END SPI6_Init 2 */ 1158:Src/main.c **** 1159:Src/main.c **** } 1160:Src/main.c **** 1161:Src/main.c **** /** 1162:Src/main.c **** * @brief TIM2 Initialization Function 1163:Src/main.c **** * @param None 1164:Src/main.c **** * @retval None 1165:Src/main.c **** */ 1166:Src/main.c **** static void MX_TIM2_Init(void) 1167:Src/main.c **** { 1168:Src/main.c **** 1169:Src/main.c **** /* USER CODE BEGIN TIM2_Init 0 */ 1170:Src/main.c **** 1171:Src/main.c **** /* USER CODE END TIM2_Init 0 */ 1172:Src/main.c **** 1173:Src/main.c **** LL_TIM_InitTypeDef TIM_InitStruct = {0}; 1174:Src/main.c **** 1175:Src/main.c **** /* Peripheral clock enable */ 1176:Src/main.c **** LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_TIM2); 1177:Src/main.c **** 1178:Src/main.c **** /* TIM2 interrupt Init */ 1179:Src/main.c **** NVIC_SetPriority(TIM2_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(),0, 0)); 1180:Src/main.c **** NVIC_EnableIRQ(TIM2_IRQn); 1181:Src/main.c **** 1182:Src/main.c **** /* USER CODE BEGIN TIM2_Init 1 */ 1183:Src/main.c **** 1184:Src/main.c **** /* USER CODE END TIM2_Init 1 */ 1185:Src/main.c **** TIM_InitStruct.Prescaler = 1000; 1186:Src/main.c **** TIM_InitStruct.CounterMode = LL_TIM_COUNTERMODE_UP; 1187:Src/main.c **** TIM_InitStruct.Autoreload = 840000; 1188:Src/main.c **** TIM_InitStruct.ClockDivision = LL_TIM_CLOCKDIVISION_DIV1; 1189:Src/main.c **** LL_TIM_Init(TIM2, &TIM_InitStruct); 1190:Src/main.c **** LL_TIM_DisableARRPreload(TIM2); 1191:Src/main.c **** LL_TIM_SetClockSource(TIM2, LL_TIM_CLOCKSOURCE_INTERNAL); 1192:Src/main.c **** LL_TIM_SetTriggerOutput(TIM2, LL_TIM_TRGO_RESET); 1193:Src/main.c **** LL_TIM_DisableMasterSlaveMode(TIM2); 1194:Src/main.c **** /* USER CODE BEGIN TIM2_Init 2 */ 1195:Src/main.c **** 1196:Src/main.c **** /* USER CODE END TIM2_Init 2 */ 1197:Src/main.c **** 1198:Src/main.c **** } ARM GAS /tmp/ccqopZd5.s page 61 1199:Src/main.c **** 1200:Src/main.c **** /** 1201:Src/main.c **** * @brief TIM5 Initialization Function 1202:Src/main.c **** * @param None 1203:Src/main.c **** * @retval None 1204:Src/main.c **** */ 1205:Src/main.c **** static void MX_TIM5_Init(void) 1206:Src/main.c **** { 1207:Src/main.c **** 1208:Src/main.c **** /* USER CODE BEGIN TIM5_Init 0 */ 1209:Src/main.c **** 1210:Src/main.c **** /* USER CODE END TIM5_Init 0 */ 1211:Src/main.c **** 1212:Src/main.c **** LL_TIM_InitTypeDef TIM_InitStruct = {0}; 1213:Src/main.c **** 1214:Src/main.c **** /* Peripheral clock enable */ 1215:Src/main.c **** LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_TIM5); 1216:Src/main.c **** 1217:Src/main.c **** /* TIM5 interrupt Init */ 1218:Src/main.c **** NVIC_SetPriority(TIM5_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(),0, 0)); 1219:Src/main.c **** NVIC_EnableIRQ(TIM5_IRQn); 1220:Src/main.c **** 1221:Src/main.c **** /* USER CODE BEGIN TIM5_Init 1 */ 1222:Src/main.c **** 1223:Src/main.c **** /* USER CODE END TIM5_Init 1 */ 1224:Src/main.c **** TIM_InitStruct.Prescaler = 10000; 1225:Src/main.c **** TIM_InitStruct.CounterMode = LL_TIM_COUNTERMODE_UP; 1226:Src/main.c **** TIM_InitStruct.Autoreload = 560; 1227:Src/main.c **** TIM_InitStruct.ClockDivision = LL_TIM_CLOCKDIVISION_DIV1; 1228:Src/main.c **** LL_TIM_Init(TIM5, &TIM_InitStruct); 1229:Src/main.c **** LL_TIM_DisableARRPreload(TIM5); 1230:Src/main.c **** LL_TIM_SetClockSource(TIM5, LL_TIM_CLOCKSOURCE_INTERNAL); 1231:Src/main.c **** LL_TIM_SetTriggerOutput(TIM5, LL_TIM_TRGO_RESET); 1232:Src/main.c **** LL_TIM_DisableMasterSlaveMode(TIM5); 1233:Src/main.c **** /* USER CODE BEGIN TIM5_Init 2 */ 1234:Src/main.c **** 1235:Src/main.c **** /* USER CODE END TIM5_Init 2 */ 1236:Src/main.c **** 1237:Src/main.c **** } 1238:Src/main.c **** 1239:Src/main.c **** /** 1240:Src/main.c **** * @brief TIM6 Initialization Function 1241:Src/main.c **** * @param None 1242:Src/main.c **** * @retval None 1243:Src/main.c **** */ 1244:Src/main.c **** static void MX_TIM6_Init(void) 1245:Src/main.c **** { 1246:Src/main.c **** 1247:Src/main.c **** /* USER CODE BEGIN TIM6_Init 0 */ 1248:Src/main.c **** 1249:Src/main.c **** /* USER CODE END TIM6_Init 0 */ 1250:Src/main.c **** 1251:Src/main.c **** LL_TIM_InitTypeDef TIM_InitStruct = {0}; 1252:Src/main.c **** 1253:Src/main.c **** /* Peripheral clock enable */ 1254:Src/main.c **** LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_TIM6); 1255:Src/main.c **** ARM GAS /tmp/ccqopZd5.s page 62 1256:Src/main.c **** /* TIM6 interrupt Init */ 1257:Src/main.c **** NVIC_SetPriority(TIM6_DAC_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(),0, 0)); 1258:Src/main.c **** NVIC_EnableIRQ(TIM6_DAC_IRQn); 1259:Src/main.c **** 1260:Src/main.c **** /* USER CODE BEGIN TIM6_Init 1 */ 1261:Src/main.c **** 1262:Src/main.c **** /* USER CODE END TIM6_Init 1 */ 1263:Src/main.c **** TIM_InitStruct.Prescaler = 45999; 1264:Src/main.c **** TIM_InitStruct.CounterMode = LL_TIM_COUNTERMODE_UP; 1265:Src/main.c **** TIM_InitStruct.Autoreload = 19; 1266:Src/main.c **** LL_TIM_Init(TIM6, &TIM_InitStruct); 1267:Src/main.c **** LL_TIM_DisableARRPreload(TIM6); 1268:Src/main.c **** LL_TIM_SetTriggerOutput(TIM6, LL_TIM_TRGO_ENABLE); 1269:Src/main.c **** LL_TIM_DisableMasterSlaveMode(TIM6); 1270:Src/main.c **** /* USER CODE BEGIN TIM6_Init 2 */ 1271:Src/main.c **** 1272:Src/main.c **** /* USER CODE END TIM6_Init 2 */ 1273:Src/main.c **** 1274:Src/main.c **** } 1275:Src/main.c **** 1276:Src/main.c **** /** 1277:Src/main.c **** * @brief TIM7 Initialization Function 1278:Src/main.c **** * @param None 1279:Src/main.c **** * @retval None 1280:Src/main.c **** */ 1281:Src/main.c **** static void MX_TIM7_Init(void) 1282:Src/main.c **** { 1283:Src/main.c **** 1284:Src/main.c **** /* USER CODE BEGIN TIM7_Init 0 */ 1285:Src/main.c **** 1286:Src/main.c **** /* USER CODE END TIM7_Init 0 */ 1287:Src/main.c **** 1288:Src/main.c **** LL_TIM_InitTypeDef TIM_InitStruct = {0}; 1289:Src/main.c **** 1290:Src/main.c **** /* Peripheral clock enable */ 1291:Src/main.c **** LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_TIM7); 1292:Src/main.c **** 1293:Src/main.c **** /* TIM7 interrupt Init */ 1294:Src/main.c **** NVIC_SetPriority(TIM7_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(),0, 0)); 1295:Src/main.c **** NVIC_EnableIRQ(TIM7_IRQn); 1296:Src/main.c **** 1297:Src/main.c **** /* USER CODE BEGIN TIM7_Init 1 */ 1298:Src/main.c **** 1299:Src/main.c **** /* USER CODE END TIM7_Init 1 */ 1300:Src/main.c **** TIM_InitStruct.Prescaler = 919; 1301:Src/main.c **** TIM_InitStruct.CounterMode = LL_TIM_COUNTERMODE_UP; 1302:Src/main.c **** TIM_InitStruct.Autoreload = 99; 1303:Src/main.c **** LL_TIM_Init(TIM7, &TIM_InitStruct); 1304:Src/main.c **** LL_TIM_DisableARRPreload(TIM7); 1305:Src/main.c **** LL_TIM_SetTriggerOutput(TIM7, LL_TIM_TRGO_ENABLE); 1306:Src/main.c **** LL_TIM_DisableMasterSlaveMode(TIM7); 1307:Src/main.c **** /* USER CODE BEGIN TIM7_Init 2 */ 1308:Src/main.c **** 1309:Src/main.c **** /* USER CODE END TIM7_Init 2 */ 1310:Src/main.c **** 1311:Src/main.c **** } 1312:Src/main.c **** ARM GAS /tmp/ccqopZd5.s page 63 1313:Src/main.c **** /** 1314:Src/main.c **** * @brief TIM8 Initialization Function 1315:Src/main.c **** * @param None 1316:Src/main.c **** * @retval None 1317:Src/main.c **** */ 1318:Src/main.c **** static void MX_TIM8_Init(void) 1319:Src/main.c **** { 1320:Src/main.c **** 1321:Src/main.c **** /* USER CODE BEGIN TIM8_Init 0 */ 1322:Src/main.c **** 1323:Src/main.c **** /* USER CODE END TIM8_Init 0 */ 1324:Src/main.c **** 1325:Src/main.c **** TIM_ClockConfigTypeDef sClockSourceConfig = {0}; 1326:Src/main.c **** TIM_MasterConfigTypeDef sMasterConfig = {0}; 1327:Src/main.c **** 1328:Src/main.c **** /* USER CODE BEGIN TIM8_Init 1 */ 1329:Src/main.c **** 1330:Src/main.c **** /* USER CODE END TIM8_Init 1 */ 1331:Src/main.c **** htim8.Instance = TIM8; 1332:Src/main.c **** htim8.Init.Prescaler = 0; 1333:Src/main.c **** htim8.Init.CounterMode = TIM_COUNTERMODE_UP; 1334:Src/main.c **** htim8.Init.Period = 91; 1335:Src/main.c **** htim8.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; 1336:Src/main.c **** htim8.Init.RepetitionCounter = 0; 1337:Src/main.c **** htim8.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; 1338:Src/main.c **** if (HAL_TIM_Base_Init(&htim8) != HAL_OK) 1339:Src/main.c **** { 1340:Src/main.c **** Error_Handler(); 1341:Src/main.c **** } 1342:Src/main.c **** sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL; 1343:Src/main.c **** if (HAL_TIM_ConfigClockSource(&htim8, &sClockSourceConfig) != HAL_OK) 1344:Src/main.c **** { 1345:Src/main.c **** Error_Handler(); 1346:Src/main.c **** } 1347:Src/main.c **** sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; 1348:Src/main.c **** sMasterConfig.MasterOutputTrigger2 = TIM_TRGO2_RESET; 1349:Src/main.c **** sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; 1350:Src/main.c **** if (HAL_TIMEx_MasterConfigSynchronization(&htim8, &sMasterConfig) != HAL_OK) 1351:Src/main.c **** { 1352:Src/main.c **** Error_Handler(); 1353:Src/main.c **** } 1354:Src/main.c **** /* USER CODE BEGIN TIM8_Init 2 */ 1355:Src/main.c **** 1356:Src/main.c **** /* USER CODE END TIM8_Init 2 */ 1357:Src/main.c **** 1358:Src/main.c **** } 1359:Src/main.c **** 1360:Src/main.c **** /** 1361:Src/main.c **** * @brief TIM10 Initialization Function 1362:Src/main.c **** * @param None 1363:Src/main.c **** * @retval None 1364:Src/main.c **** */ 1365:Src/main.c **** static void MX_TIM10_Init(void) 1366:Src/main.c **** { 1367:Src/main.c **** 1368:Src/main.c **** /* USER CODE BEGIN TIM10_Init 0 */ 1369:Src/main.c **** ARM GAS /tmp/ccqopZd5.s page 64 1370:Src/main.c **** /* USER CODE END TIM10_Init 0 */ 1371:Src/main.c **** 1372:Src/main.c **** /* USER CODE BEGIN TIM10_Init 1 */ 1373:Src/main.c **** 1374:Src/main.c **** /* USER CODE END TIM10_Init 1 */ 1375:Src/main.c **** htim10.Instance = TIM10; 1376:Src/main.c **** htim10.Init.Prescaler = 183; 1377:Src/main.c **** htim10.Init.CounterMode = TIM_COUNTERMODE_UP; 1378:Src/main.c **** htim10.Init.Period = 9; 1379:Src/main.c **** htim10.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; 1380:Src/main.c **** htim10.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; 1381:Src/main.c **** if (HAL_TIM_Base_Init(&htim10) != HAL_OK) 1382:Src/main.c **** { 1383:Src/main.c **** Error_Handler(); 1384:Src/main.c **** } 1385:Src/main.c **** /* USER CODE BEGIN TIM10_Init 2 */ 1386:Src/main.c **** 1387:Src/main.c **** /* USER CODE END TIM10_Init 2 */ 1388:Src/main.c **** 1389:Src/main.c **** } 1390:Src/main.c **** 1391:Src/main.c **** /** 1392:Src/main.c **** * @brief TIM11 Initialization Function 1393:Src/main.c **** * @param None 1394:Src/main.c **** * @retval None 1395:Src/main.c **** */ 1396:Src/main.c **** static void MX_TIM11_Init(void) 1397:Src/main.c **** { 1398:Src/main.c **** 1399:Src/main.c **** /* USER CODE BEGIN TIM11_Init 0 */ 1400:Src/main.c **** 1401:Src/main.c **** /* USER CODE END TIM11_Init 0 */ 1402:Src/main.c **** 1403:Src/main.c **** TIM_OC_InitTypeDef sConfigOC = {0}; 1404:Src/main.c **** 1405:Src/main.c **** /* USER CODE BEGIN TIM11_Init 1 */ 1406:Src/main.c **** 1407:Src/main.c **** /* USER CODE END TIM11_Init 1 */ 1408:Src/main.c **** htim11.Instance = TIM11; 1409:Src/main.c **** htim11.Init.Prescaler = 0; 1410:Src/main.c **** htim11.Init.CounterMode = TIM_COUNTERMODE_UP; 1411:Src/main.c **** htim11.Init.Period = 183; 1412:Src/main.c **** htim11.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; 1413:Src/main.c **** htim11.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_ENABLE; 1414:Src/main.c **** if (HAL_TIM_Base_Init(&htim11) != HAL_OK) 1415:Src/main.c **** { 1416:Src/main.c **** Error_Handler(); 1417:Src/main.c **** } 1418:Src/main.c **** if (HAL_TIM_PWM_Init(&htim11) != HAL_OK) 1419:Src/main.c **** { 1420:Src/main.c **** Error_Handler(); 1421:Src/main.c **** } 1422:Src/main.c **** sConfigOC.OCMode = TIM_OCMODE_PWM1; 1423:Src/main.c **** sConfigOC.Pulse = 91; 1424:Src/main.c **** sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH; 1425:Src/main.c **** sConfigOC.OCFastMode = TIM_OCFAST_ENABLE; 1426:Src/main.c **** if (HAL_TIM_PWM_ConfigChannel(&htim11, &sConfigOC, TIM_CHANNEL_1) != HAL_OK) ARM GAS /tmp/ccqopZd5.s page 65 1427:Src/main.c **** { 1428:Src/main.c **** Error_Handler(); 1429:Src/main.c **** } 1430:Src/main.c **** /* USER CODE BEGIN TIM11_Init 2 */ 1431:Src/main.c **** 1432:Src/main.c **** /* USER CODE END TIM11_Init 2 */ 1433:Src/main.c **** HAL_TIM_MspPostInit(&htim11); 1434:Src/main.c **** 1435:Src/main.c **** } 1436:Src/main.c **** 1437:Src/main.c **** /** 1438:Src/main.c **** * @brief UART8 Initialization Function 1439:Src/main.c **** * @param None 1440:Src/main.c **** * @retval None 1441:Src/main.c **** */ 1442:Src/main.c **** static void MX_UART8_Init(void) 1443:Src/main.c **** { 1444:Src/main.c **** 1445:Src/main.c **** /* USER CODE BEGIN UART8_Init 0 */ 1446:Src/main.c **** 1447:Src/main.c **** /* USER CODE END UART8_Init 0 */ 1448:Src/main.c **** 1449:Src/main.c **** /* USER CODE BEGIN UART8_Init 1 */ 1450:Src/main.c **** 1451:Src/main.c **** /* USER CODE END UART8_Init 1 */ 1452:Src/main.c **** huart8.Instance = UART8; 1453:Src/main.c **** huart8.Init.BaudRate = 115200; 1454:Src/main.c **** huart8.Init.WordLength = UART_WORDLENGTH_8B; 1455:Src/main.c **** huart8.Init.StopBits = UART_STOPBITS_1; 1456:Src/main.c **** huart8.Init.Parity = UART_PARITY_NONE; 1457:Src/main.c **** huart8.Init.Mode = UART_MODE_TX_RX; 1458:Src/main.c **** huart8.Init.HwFlowCtl = UART_HWCONTROL_NONE; 1459:Src/main.c **** huart8.Init.OverSampling = UART_OVERSAMPLING_16; 1460:Src/main.c **** huart8.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE; 1461:Src/main.c **** huart8.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT; 1462:Src/main.c **** if (HAL_UART_Init(&huart8) != HAL_OK) 1463:Src/main.c **** { 1464:Src/main.c **** Error_Handler(); 1465:Src/main.c **** } 1466:Src/main.c **** /* USER CODE BEGIN UART8_Init 2 */ 1467:Src/main.c **** 1468:Src/main.c **** /* USER CODE END UART8_Init 2 */ 1469:Src/main.c **** 1470:Src/main.c **** } 1471:Src/main.c **** 1472:Src/main.c **** /** 1473:Src/main.c **** * @brief USART1 Initialization Function 1474:Src/main.c **** * @param None 1475:Src/main.c **** * @retval None 1476:Src/main.c **** */ 1477:Src/main.c **** static void MX_USART1_UART_Init(void) 1478:Src/main.c **** { 1479:Src/main.c **** 1480:Src/main.c **** /* USER CODE BEGIN USART1_Init 0 */ 1481:Src/main.c **** 1482:Src/main.c **** /* USER CODE END USART1_Init 0 */ 1483:Src/main.c **** ARM GAS /tmp/ccqopZd5.s page 66 1484:Src/main.c **** LL_USART_InitTypeDef USART_InitStruct = {0}; 1485:Src/main.c **** 1486:Src/main.c **** LL_GPIO_InitTypeDef GPIO_InitStruct = {0}; 1487:Src/main.c **** RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; 1488:Src/main.c **** 1489:Src/main.c **** /** Initializes the peripherals clock 1490:Src/main.c **** */ 1491:Src/main.c **** PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USART1; 1492:Src/main.c **** PeriphClkInitStruct.Usart1ClockSelection = RCC_USART1CLKSOURCE_PCLK2; 1493:Src/main.c **** if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) 1494:Src/main.c **** { 1495:Src/main.c **** Error_Handler(); 1496:Src/main.c **** } 1497:Src/main.c **** 1498:Src/main.c **** /* Peripheral clock enable */ 1499:Src/main.c **** LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_USART1); 1500:Src/main.c **** 1501:Src/main.c **** LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_GPIOA); 1502:Src/main.c **** /**USART1 GPIO Configuration 1503:Src/main.c **** PA9 ------> USART1_TX 1504:Src/main.c **** PA10 ------> USART1_RX 1505:Src/main.c **** */ 1506:Src/main.c **** GPIO_InitStruct.Pin = LL_GPIO_PIN_9; 1507:Src/main.c **** GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE; 1508:Src/main.c **** GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH; 1509:Src/main.c **** GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; 1510:Src/main.c **** GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; 1511:Src/main.c **** GPIO_InitStruct.Alternate = LL_GPIO_AF_7; 1512:Src/main.c **** LL_GPIO_Init(GPIOA, &GPIO_InitStruct); 1513:Src/main.c **** 1514:Src/main.c **** GPIO_InitStruct.Pin = LL_GPIO_PIN_10; 1515:Src/main.c **** GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE; 1516:Src/main.c **** GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH; 1517:Src/main.c **** GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; 1518:Src/main.c **** GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; 1519:Src/main.c **** GPIO_InitStruct.Alternate = LL_GPIO_AF_7; 1520:Src/main.c **** LL_GPIO_Init(GPIOA, &GPIO_InitStruct); 1521:Src/main.c **** 1522:Src/main.c **** /* USART1 DMA Init */ 1523:Src/main.c **** 1524:Src/main.c **** /* USART1_TX Init */ 1525:Src/main.c **** LL_DMA_SetChannelSelection(DMA2, LL_DMA_STREAM_7, LL_DMA_CHANNEL_4); 1526:Src/main.c **** 1527:Src/main.c **** LL_DMA_SetDataTransferDirection(DMA2, LL_DMA_STREAM_7, LL_DMA_DIRECTION_MEMORY_TO_PERIPH); 1528:Src/main.c **** 1529:Src/main.c **** LL_DMA_SetStreamPriorityLevel(DMA2, LL_DMA_STREAM_7, LL_DMA_PRIORITY_VERYHIGH); 1530:Src/main.c **** 1531:Src/main.c **** LL_DMA_SetMode(DMA2, LL_DMA_STREAM_7, LL_DMA_MODE_NORMAL); 1532:Src/main.c **** 1533:Src/main.c **** LL_DMA_SetPeriphIncMode(DMA2, LL_DMA_STREAM_7, LL_DMA_PERIPH_NOINCREMENT); 1534:Src/main.c **** 1535:Src/main.c **** LL_DMA_SetMemoryIncMode(DMA2, LL_DMA_STREAM_7, LL_DMA_MEMORY_INCREMENT); 1536:Src/main.c **** 1537:Src/main.c **** LL_DMA_SetPeriphSize(DMA2, LL_DMA_STREAM_7, LL_DMA_PDATAALIGN_BYTE); 1538:Src/main.c **** 1539:Src/main.c **** LL_DMA_SetMemorySize(DMA2, LL_DMA_STREAM_7, LL_DMA_MDATAALIGN_BYTE); 1540:Src/main.c **** ARM GAS /tmp/ccqopZd5.s page 67 1541:Src/main.c **** LL_DMA_DisableFifoMode(DMA2, LL_DMA_STREAM_7); 1542:Src/main.c **** 1543:Src/main.c **** /* USART1 interrupt Init */ 1544:Src/main.c **** NVIC_SetPriority(USART1_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(),0, 0)); 1545:Src/main.c **** NVIC_EnableIRQ(USART1_IRQn); 1546:Src/main.c **** 1547:Src/main.c **** /* USER CODE BEGIN USART1_Init 1 */ 1548:Src/main.c **** 1549:Src/main.c **** /* USER CODE END USART1_Init 1 */ 1550:Src/main.c **** USART_InitStruct.BaudRate = 115200; 1551:Src/main.c **** USART_InitStruct.DataWidth = LL_USART_DATAWIDTH_8B; 1552:Src/main.c **** USART_InitStruct.StopBits = LL_USART_STOPBITS_1; 1553:Src/main.c **** USART_InitStruct.Parity = LL_USART_PARITY_NONE; 1554:Src/main.c **** USART_InitStruct.TransferDirection = LL_USART_DIRECTION_TX_RX; 1555:Src/main.c **** USART_InitStruct.HardwareFlowControl = LL_USART_HWCONTROL_NONE; 1556:Src/main.c **** USART_InitStruct.OverSampling = LL_USART_OVERSAMPLING_16; 1557:Src/main.c **** LL_USART_Init(USART1, &USART_InitStruct); 1558:Src/main.c **** LL_USART_ConfigAsyncMode(USART1); 1559:Src/main.c **** LL_USART_Enable(USART1); 1560:Src/main.c **** /* USER CODE BEGIN USART1_Init 2 */ 1561:Src/main.c **** 1562:Src/main.c **** /* USER CODE END USART1_Init 2 */ 1563:Src/main.c **** 1564:Src/main.c **** } 1565:Src/main.c **** 1566:Src/main.c **** /** 1567:Src/main.c **** * Enable DMA controller clock 1568:Src/main.c **** */ 1569:Src/main.c **** static void MX_DMA_Init(void) 1570:Src/main.c **** { 143 .loc 2 1570 1 is_stmt 1 view -0 144 .cfi_startproc 145 @ args = 0, pretend = 0, frame = 8 146 @ frame_needed = 0, uses_anonymous_args = 0 147 0000 00B5 push {lr} 148 .LCFI0: 149 .cfi_def_cfa_offset 4 150 .cfi_offset 14, -4 151 0002 83B0 sub sp, sp, #12 152 .LCFI1: 153 .cfi_def_cfa_offset 16 1571:Src/main.c **** 1572:Src/main.c **** /* Init with LL driver */ 1573:Src/main.c **** /* DMA controller clock enable */ 1574:Src/main.c **** LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_DMA2); 154 .loc 2 1574 3 view .LVU37 155 .LVL8: 156 .LBB294: 157 .LBI294: 158 .file 3 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h" 1:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** 2:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** ****************************************************************************** 3:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @file stm32f7xx_ll_bus.h 4:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @author MCD Application Team 5:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Header file of BUS LL module. 6:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 7:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** @verbatim ARM GAS /tmp/ccqopZd5.s page 68 8:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** ##### RCC Limitations ##### 9:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** ============================================================================== 10:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** [..] 11:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** A delay between an RCC peripheral clock enable and the effective peripheral 12:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** enabling should be taken into account in order to manage the peripheral read/write 13:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** from/to registers. 14:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (+) This delay depends on the peripheral mapping. 15:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (++) AHB & APB peripherals, 1 dummy read is necessary 16:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 17:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** [..] 18:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** Workarounds: 19:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (#) For AHB & APB peripherals, a dummy read to the peripheral register has been 20:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** inserted in each LL_{BUS}_GRP{x}_EnableClock() function. 21:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 22:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** @endverbatim 23:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** ****************************************************************************** 24:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @attention 25:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * 26:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * Copyright (c) 2017 STMicroelectronics. 27:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * All rights reserved. 28:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * 29:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * This software is licensed under terms that can be found in the LICENSE file in 30:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * the root directory of this software component. 31:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * If no LICENSE file comes with this software, it is provided AS-IS. 32:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** ****************************************************************************** 33:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ 34:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 35:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Define to prevent recursive inclusion -------------------------------------*/ 36:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #ifndef __STM32F7xx_LL_BUS_H 37:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define __STM32F7xx_LL_BUS_H 38:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 39:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #ifdef __cplusplus 40:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** extern "C" { 41:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif 42:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 43:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Includes ------------------------------------------------------------------*/ 44:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #include "stm32f7xx.h" 45:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 46:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** @addtogroup STM32F7xx_LL_Driver 47:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @{ 48:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ 49:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 50:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(RCC) 51:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 52:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** @defgroup BUS_LL BUS 53:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @{ 54:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ 55:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 56:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Private types -------------------------------------------------------------*/ 57:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Private variables ---------------------------------------------------------*/ 58:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Private constants ---------------------------------------------------------*/ 59:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Private macros ------------------------------------------------------------*/ 60:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Exported types ------------------------------------------------------------*/ 61:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Exported constants --------------------------------------------------------*/ 62:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** @defgroup BUS_LL_Exported_Constants BUS Exported Constants 63:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @{ 64:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ ARM GAS /tmp/ccqopZd5.s page 69 65:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 66:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** @defgroup BUS_LL_EC_AHB1_GRP1_PERIPH AHB1 GRP1 PERIPH 67:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @{ 68:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ 69:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_ALL 0xFFFFFFFFU 70:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_GPIOA RCC_AHB1ENR_GPIOAEN 71:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_GPIOB RCC_AHB1ENR_GPIOBEN 72:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_GPIOC RCC_AHB1ENR_GPIOCEN 73:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_GPIOD RCC_AHB1ENR_GPIODEN 74:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_GPIOE RCC_AHB1ENR_GPIOEEN 75:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_GPIOF RCC_AHB1ENR_GPIOFEN 76:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_GPIOG RCC_AHB1ENR_GPIOGEN 77:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_GPIOH RCC_AHB1ENR_GPIOHEN 78:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_GPIOI RCC_AHB1ENR_GPIOIEN 79:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(GPIOJ) 80:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_GPIOJ RCC_AHB1ENR_GPIOJEN 81:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* GPIOJ */ 82:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(GPIOK) 83:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_GPIOK RCC_AHB1ENR_GPIOKEN 84:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* GPIOK */ 85:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_CRC RCC_AHB1ENR_CRCEN 86:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_BKPSRAM RCC_AHB1ENR_BKPSRAMEN 87:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_DTCMRAM RCC_AHB1ENR_DTCMRAMEN 88:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_DMA1 RCC_AHB1ENR_DMA1EN 89:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_DMA2 RCC_AHB1ENR_DMA2EN 90:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(DMA2D) 91:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_DMA2D RCC_AHB1ENR_DMA2DEN 92:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* DMA2D */ 93:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(ETH) 94:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_ETHMAC RCC_AHB1ENR_ETHMACEN 95:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_ETHMACTX RCC_AHB1ENR_ETHMACTXEN 96:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_ETHMACRX RCC_AHB1ENR_ETHMACRXEN 97:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_ETHMACPTP RCC_AHB1ENR_ETHMACPTPEN 98:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* ETH */ 99:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_OTGHS RCC_AHB1ENR_OTGHSEN 100:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_OTGHSULPI RCC_AHB1ENR_OTGHSULPIEN 101:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_AXI RCC_AHB1LPENR_AXILPEN 102:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_FLITF RCC_AHB1LPENR_FLITFLPEN 103:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_SRAM1 RCC_AHB1LPENR_SRAM1LPEN 104:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_SRAM2 RCC_AHB1LPENR_SRAM2LPEN 105:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** 106:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @} 107:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ 108:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 109:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** @defgroup BUS_LL_EC_AHB2_GRP1_PERIPH AHB2 GRP1 PERIPH 110:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @{ 111:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ 112:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB2_GRP1_PERIPH_ALL 0xFFFFFFFFU 113:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(DCMI) 114:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB2_GRP1_PERIPH_DCMI RCC_AHB2ENR_DCMIEN 115:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* DCMI */ 116:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(JPEG) 117:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB2_GRP1_PERIPH_JPEG RCC_AHB2ENR_JPEGEN 118:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* JPEG */ 119:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(CRYP) 120:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB2_GRP1_PERIPH_CRYP RCC_AHB2ENR_CRYPEN 121:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* CRYP */ ARM GAS /tmp/ccqopZd5.s page 70 122:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(AES) 123:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB2_GRP1_PERIPH_AES RCC_AHB2ENR_AESEN 124:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* AES */ 125:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(HASH) 126:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB2_GRP1_PERIPH_HASH RCC_AHB2ENR_HASHEN 127:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* HASH */ 128:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB2_GRP1_PERIPH_RNG RCC_AHB2ENR_RNGEN 129:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB2_GRP1_PERIPH_OTGFS RCC_AHB2ENR_OTGFSEN 130:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** 131:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @} 132:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ 133:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 134:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** @defgroup BUS_LL_EC_AHB3_GRP1_PERIPH AHB3 GRP1 PERIPH 135:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @{ 136:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ 137:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB3_GRP1_PERIPH_ALL 0xFFFFFFFFU 138:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB3_GRP1_PERIPH_FMC RCC_AHB3ENR_FMCEN 139:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB3_GRP1_PERIPH_QSPI RCC_AHB3ENR_QSPIEN 140:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** 141:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @} 142:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ 143:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 144:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** @defgroup BUS_LL_EC_APB1_GRP1_PERIPH APB1 GRP1 PERIPH 145:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @{ 146:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ 147:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_ALL 0xFFFFFFFFU 148:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_TIM2 RCC_APB1ENR_TIM2EN 149:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_TIM3 RCC_APB1ENR_TIM3EN 150:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_TIM4 RCC_APB1ENR_TIM4EN 151:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_TIM5 RCC_APB1ENR_TIM5EN 152:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_TIM6 RCC_APB1ENR_TIM6EN 153:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_TIM7 RCC_APB1ENR_TIM7EN 154:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_TIM12 RCC_APB1ENR_TIM12EN 155:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_TIM13 RCC_APB1ENR_TIM13EN 156:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_TIM14 RCC_APB1ENR_TIM14EN 157:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_LPTIM1 RCC_APB1ENR_LPTIM1EN 158:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_WWDG RCC_APB1ENR_WWDGEN 159:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_SPI2 RCC_APB1ENR_SPI2EN 160:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_SPI3 RCC_APB1ENR_SPI3EN 161:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(SPDIFRX) 162:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_SPDIFRX RCC_APB1ENR_SPDIFRXEN 163:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* SPDIFRX */ 164:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_USART2 RCC_APB1ENR_USART2EN 165:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_USART3 RCC_APB1ENR_USART3EN 166:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_UART4 RCC_APB1ENR_UART4EN 167:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_UART5 RCC_APB1ENR_UART5EN 168:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_I2C1 RCC_APB1ENR_I2C1EN 169:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_I2C2 RCC_APB1ENR_I2C2EN 170:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_I2C3 RCC_APB1ENR_I2C3EN 171:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(I2C4) 172:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_I2C4 RCC_APB1ENR_I2C4EN 173:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* I2C4 */ 174:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_CAN1 RCC_APB1ENR_CAN1EN 175:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(CAN2) 176:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_CAN2 RCC_APB1ENR_CAN2EN 177:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* CAN2 */ 178:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(CAN3) ARM GAS /tmp/ccqopZd5.s page 71 179:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_CAN3 RCC_APB1ENR_CAN3EN 180:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* CAN3 */ 181:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(CEC) 182:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_CEC RCC_APB1ENR_CECEN 183:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* CEC */ 184:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_PWR RCC_APB1ENR_PWREN 185:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_DAC1 RCC_APB1ENR_DACEN 186:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_UART7 RCC_APB1ENR_UART7EN 187:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_UART8 RCC_APB1ENR_UART8EN 188:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(RCC_APB1ENR_RTCEN) 189:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_RTCAPB RCC_APB1ENR_RTCEN 190:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* RCC_APB1ENR_RTCEN */ 191:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** 192:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @} 193:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ 194:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 195:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** @defgroup BUS_LL_EC_APB2_GRP1_PERIPH APB2 GRP1 PERIPH 196:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @{ 197:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ 198:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_ALL 0xFFFFFFFFU 199:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_TIM1 RCC_APB2ENR_TIM1EN 200:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_TIM8 RCC_APB2ENR_TIM8EN 201:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_USART1 RCC_APB2ENR_USART1EN 202:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_USART6 RCC_APB2ENR_USART6EN 203:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_ADC1 RCC_APB2ENR_ADC1EN 204:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_ADC2 RCC_APB2ENR_ADC2EN 205:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_ADC3 RCC_APB2ENR_ADC3EN 206:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_SDMMC1 RCC_APB2ENR_SDMMC1EN 207:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(SDMMC2) 208:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_SDMMC2 RCC_APB2ENR_SDMMC2EN 209:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* SDMMC2 */ 210:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_SPI1 RCC_APB2ENR_SPI1EN 211:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_SPI4 RCC_APB2ENR_SPI4EN 212:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_SYSCFG RCC_APB2ENR_SYSCFGEN 213:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_TIM9 RCC_APB2ENR_TIM9EN 214:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_TIM10 RCC_APB2ENR_TIM10EN 215:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_TIM11 RCC_APB2ENR_TIM11EN 216:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_SPI5 RCC_APB2ENR_SPI5EN 217:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(SPI6) 218:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_SPI6 RCC_APB2ENR_SPI6EN 219:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* SPI6 */ 220:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_SAI1 RCC_APB2ENR_SAI1EN 221:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_SAI2 RCC_APB2ENR_SAI2EN 222:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(LTDC) 223:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_LTDC RCC_APB2ENR_LTDCEN 224:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* LTDC */ 225:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(DSI) 226:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_DSI RCC_APB2ENR_DSIEN 227:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* DSI */ 228:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(DFSDM1_Channel0) 229:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_DFSDM1 RCC_APB2ENR_DFSDM1EN 230:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* DFSDM1_Channel0 */ 231:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(MDIOS) 232:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_MDIO RCC_APB2ENR_MDIOEN 233:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* MDIOS */ 234:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(USB_HS_PHYC) 235:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_OTGPHYC RCC_APB2ENR_OTGPHYCEN ARM GAS /tmp/ccqopZd5.s page 72 236:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* USB_HS_PHYC */ 237:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_ADC RCC_APB2RSTR_ADCRST 238:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** 239:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @} 240:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ 241:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 242:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** 243:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @} 244:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ 245:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 246:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Exported macro ------------------------------------------------------------*/ 247:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Exported functions --------------------------------------------------------*/ 248:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** @defgroup BUS_LL_Exported_Functions BUS Exported Functions 249:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @{ 250:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ 251:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 252:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** @defgroup BUS_LL_EF_AHB1 AHB1 253:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @{ 254:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ 255:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 256:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** 257:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Enable AHB1 peripherals clock. 258:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll AHB1ENR GPIOAEN LL_AHB1_GRP1_EnableClock\n 259:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOBEN LL_AHB1_GRP1_EnableClock\n 260:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOCEN LL_AHB1_GRP1_EnableClock\n 261:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIODEN LL_AHB1_GRP1_EnableClock\n 262:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOEEN LL_AHB1_GRP1_EnableClock\n 263:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOFEN LL_AHB1_GRP1_EnableClock\n 264:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOGEN LL_AHB1_GRP1_EnableClock\n 265:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOHEN LL_AHB1_GRP1_EnableClock\n 266:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOIEN LL_AHB1_GRP1_EnableClock\n 267:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOJEN LL_AHB1_GRP1_EnableClock\n 268:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOKEN LL_AHB1_GRP1_EnableClock\n 269:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR CRCEN LL_AHB1_GRP1_EnableClock\n 270:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR BKPSRAMEN LL_AHB1_GRP1_EnableClock\n 271:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR DTCMRAMEN LL_AHB1_GRP1_EnableClock\n 272:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR DMA1EN LL_AHB1_GRP1_EnableClock\n 273:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR DMA2EN LL_AHB1_GRP1_EnableClock\n 274:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR DMA2DEN LL_AHB1_GRP1_EnableClock\n 275:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR ETHMACEN LL_AHB1_GRP1_EnableClock\n 276:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR ETHMACTXEN LL_AHB1_GRP1_EnableClock\n 277:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR ETHMACRXEN LL_AHB1_GRP1_EnableClock\n 278:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR ETHMACPTPEN LL_AHB1_GRP1_EnableClock\n 279:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR OTGHSEN LL_AHB1_GRP1_EnableClock\n 280:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR OTGHSULPIEN LL_AHB1_GRP1_EnableClock 281:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: 282:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA 283:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB 284:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC 285:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD 286:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE 287:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF 288:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG 289:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH 290:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI 291:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*) 292:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*) ARM GAS /tmp/ccqopZd5.s page 73 293:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRC 294:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM 295:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DTCMRAM 296:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 298:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*) 299:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*) 300:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*) 301:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*) 302:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACPTP (*) 303:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS 304:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHSULPI 305:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * 306:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. 307:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval None 308:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ 309:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs) 159 .loc 3 309 22 view .LVU38 160 .LBB295: 310:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { 311:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __IO uint32_t tmpreg; 161 .loc 3 311 3 view .LVU39 312:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** SET_BIT(RCC->AHB1ENR, Periphs); 162 .loc 3 312 3 view .LVU40 163 0004 0D4B ldr r3, .L9 164 0006 1A6B ldr r2, [r3, #48] 165 0008 42F48002 orr r2, r2, #4194304 166 000c 1A63 str r2, [r3, #48] 313:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Delay after an RCC peripheral clock enabling */ 314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** tmpreg = READ_BIT(RCC->AHB1ENR, Periphs); 167 .loc 3 314 3 view .LVU41 168 .loc 3 314 12 is_stmt 0 view .LVU42 169 000e 1B6B ldr r3, [r3, #48] 170 0010 03F48003 and r3, r3, #4194304 171 .loc 3 314 10 view .LVU43 172 0014 0193 str r3, [sp, #4] 315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; 173 .loc 3 315 3 is_stmt 1 view .LVU44 174 0016 019B ldr r3, [sp, #4] 175 .LVL9: 176 .loc 3 315 3 is_stmt 0 view .LVU45 177 .LBE295: 178 .LBE294: 1575:Src/main.c **** 1576:Src/main.c **** /* DMA interrupt init */ 1577:Src/main.c **** /* DMA2_Stream7_IRQn interrupt configuration */ 1578:Src/main.c **** NVIC_SetPriority(DMA2_Stream7_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(),0, 0)); 179 .loc 2 1578 3 is_stmt 1 view .LVU46 180 .LBB296: 181 .LBI296: 1884:Drivers/CMSIS/Include/core_cm7.h **** { 182 .loc 1 1884 26 view .LVU47 183 .LBB297: 1886:Drivers/CMSIS/Include/core_cm7.h **** } 184 .loc 1 1886 3 view .LVU48 1886:Drivers/CMSIS/Include/core_cm7.h **** } 185 .loc 1 1886 26 is_stmt 0 view .LVU49 ARM GAS /tmp/ccqopZd5.s page 74 186 0018 094B ldr r3, .L9+4 187 001a D868 ldr r0, [r3, #12] 188 .LBE297: 189 .LBE296: 190 .loc 2 1578 3 view .LVU50 191 001c 0022 movs r2, #0 192 001e 1146 mov r1, r2 193 0020 C0F30220 ubfx r0, r0, #8, #3 194 0024 FFF7FEFF bl NVIC_EncodePriority 195 .LVL10: 196 .LBB298: 197 .LBI298: 2024:Drivers/CMSIS/Include/core_cm7.h **** { 198 .loc 1 2024 22 is_stmt 1 view .LVU51 199 .LBB299: 2026:Drivers/CMSIS/Include/core_cm7.h **** { 200 .loc 1 2026 3 view .LVU52 2028:Drivers/CMSIS/Include/core_cm7.h **** } 201 .loc 1 2028 5 view .LVU53 2028:Drivers/CMSIS/Include/core_cm7.h **** } 202 .loc 1 2028 49 is_stmt 0 view .LVU54 203 0028 0001 lsls r0, r0, #4 204 .LVL11: 2028:Drivers/CMSIS/Include/core_cm7.h **** } 205 .loc 1 2028 49 view .LVU55 206 002a C0B2 uxtb r0, r0 2028:Drivers/CMSIS/Include/core_cm7.h **** } 207 .loc 1 2028 47 view .LVU56 208 002c 054B ldr r3, .L9+8 209 002e 83F84603 strb r0, [r3, #838] 210 .LVL12: 2028:Drivers/CMSIS/Include/core_cm7.h **** } 211 .loc 1 2028 47 view .LVU57 212 .LBE299: 213 .LBE298: 1579:Src/main.c **** NVIC_EnableIRQ(DMA2_Stream7_IRQn); 214 .loc 2 1579 3 is_stmt 1 view .LVU58 215 .LBB300: 216 .LBI300: 1896:Drivers/CMSIS/Include/core_cm7.h **** { 217 .loc 1 1896 22 view .LVU59 218 .LBB301: 1898:Drivers/CMSIS/Include/core_cm7.h **** { 219 .loc 1 1898 3 view .LVU60 1900:Drivers/CMSIS/Include/core_cm7.h **** } 220 .loc 1 1900 5 view .LVU61 1900:Drivers/CMSIS/Include/core_cm7.h **** } 221 .loc 1 1900 43 is_stmt 0 view .LVU62 222 0032 4022 movs r2, #64 223 0034 9A60 str r2, [r3, #8] 224 .LVL13: 1900:Drivers/CMSIS/Include/core_cm7.h **** } 225 .loc 1 1900 43 view .LVU63 226 .LBE301: 227 .LBE300: 1580:Src/main.c **** 1581:Src/main.c **** } ARM GAS /tmp/ccqopZd5.s page 75 228 .loc 2 1581 1 view .LVU64 229 0036 03B0 add sp, sp, #12 230 .LCFI2: 231 .cfi_def_cfa_offset 4 232 @ sp needed 233 0038 5DF804FB ldr pc, [sp], #4 234 .L10: 235 .align 2 236 .L9: 237 003c 00380240 .word 1073887232 238 0040 00ED00E0 .word -536810240 239 0044 00E100E0 .word -536813312 240 .cfi_endproc 241 .LFE1204: 243 .section .text.Decode_task,"ax",%progbits 244 .align 1 245 .syntax unified 246 .thumb 247 .thumb_func 248 .fpu fpv5-d16 250 Decode_task: 251 .LVL14: 252 .LFB1208: 1582:Src/main.c **** 1583:Src/main.c **** /** 1584:Src/main.c **** * @brief GPIO Initialization Function 1585:Src/main.c **** * @param None 1586:Src/main.c **** * @retval None 1587:Src/main.c **** */ 1588:Src/main.c **** static void MX_GPIO_Init(void) 1589:Src/main.c **** { 1590:Src/main.c **** GPIO_InitTypeDef GPIO_InitStruct = {0}; 1591:Src/main.c **** /* USER CODE BEGIN MX_GPIO_Init_1 */ 1592:Src/main.c **** /* USER CODE END MX_GPIO_Init_1 */ 1593:Src/main.c **** 1594:Src/main.c **** /* GPIO Ports Clock Enable */ 1595:Src/main.c **** __HAL_RCC_GPIOF_CLK_ENABLE(); 1596:Src/main.c **** __HAL_RCC_GPIOH_CLK_ENABLE(); 1597:Src/main.c **** __HAL_RCC_GPIOC_CLK_ENABLE(); 1598:Src/main.c **** __HAL_RCC_GPIOA_CLK_ENABLE(); 1599:Src/main.c **** __HAL_RCC_GPIOB_CLK_ENABLE(); 1600:Src/main.c **** __HAL_RCC_GPIOE_CLK_ENABLE(); 1601:Src/main.c **** __HAL_RCC_GPIOD_CLK_ENABLE(); 1602:Src/main.c **** __HAL_RCC_GPIOG_CLK_ENABLE(); 1603:Src/main.c **** 1604:Src/main.c **** /*Configure GPIO pin Output Level */ 1605:Src/main.c **** HAL_GPIO_WritePin(GPIOF, ADC_MPD2_CS_Pin|SPI5_CNV_Pin|ADC_ThrLD2_CS_Pin, GPIO_PIN_RESET); 1606:Src/main.c **** 1607:Src/main.c **** /*Configure GPIO pin Output Level */ 1608:Src/main.c **** HAL_GPIO_WritePin(GPIOC, EN_5V2_Pin|EN_5V1_Pin|LD2_EN_Pin|TEC2_PD_Pin, GPIO_PIN_RESET); 1609:Src/main.c **** 1610:Src/main.c **** /*Configure GPIO pin Output Level */ 1611:Src/main.c **** HAL_GPIO_WritePin(GPIOA, TECEN1_Pin|TECEN2_Pin|REF2_ON_Pin|DAC_LD2_CS_Pin, GPIO_PIN_RESET); 1612:Src/main.c **** 1613:Src/main.c **** /*Configure GPIO pin Output Level */ 1614:Src/main.c **** HAL_GPIO_WritePin(DAC_TEC2_CS_GPIO_Port, DAC_TEC2_CS_Pin, GPIO_PIN_SET); 1615:Src/main.c **** ARM GAS /tmp/ccqopZd5.s page 76 1616:Src/main.c **** /*Configure GPIO pin Output Level */ 1617:Src/main.c **** HAL_GPIO_WritePin(GPIOE, ADC_MPD1_CS_Pin|ADC_ThrLD1_CS_Pin, GPIO_PIN_RESET); 1618:Src/main.c **** 1619:Src/main.c **** /*Configure GPIO pin Output Level */ 1620:Src/main.c **** HAL_GPIO_WritePin(SPI4_CNV_GPIO_Port, SPI4_CNV_Pin, GPIO_PIN_SET); 1621:Src/main.c **** 1622:Src/main.c **** /*Configure GPIO pin Output Level */ 1623:Src/main.c **** HAL_GPIO_WritePin(GPIOB, REF0_EN_Pin|TEC1_PD_Pin|DAC_LD1_CS_Pin|OUT_6_Pin 1624:Src/main.c **** |OUT_7_Pin|OUT_8_Pin|OUT_9_Pin|OUT_10_Pin, GPIO_PIN_RESET); 1625:Src/main.c **** 1626:Src/main.c **** /*Configure GPIO pin Output Level */ 1627:Src/main.c **** HAL_GPIO_WritePin(DAC_TEC1_CS_GPIO_Port, DAC_TEC1_CS_Pin, GPIO_PIN_SET); 1628:Src/main.c **** 1629:Src/main.c **** /*Configure GPIO pin Output Level */ 1630:Src/main.c **** HAL_GPIO_WritePin(GPIOD, LD1_EN_Pin|TEST_01_Pin|GPIO_PIN_7, GPIO_PIN_RESET); 1631:Src/main.c **** 1632:Src/main.c **** /*Configure GPIO pin Output Level */ 1633:Src/main.c **** HAL_GPIO_WritePin(GPIOG, GPIO_PIN_9|OUT_0_Pin|OUT_1_Pin|OUT_2_Pin 1634:Src/main.c **** |OUT_3_Pin|OUT_4_Pin|OUT_5_Pin, GPIO_PIN_RESET); 1635:Src/main.c **** 1636:Src/main.c **** /*Configure GPIO pins : INP_0_Pin INP_1_Pin */ 1637:Src/main.c **** GPIO_InitStruct.Pin = INP_0_Pin|INP_1_Pin; 1638:Src/main.c **** GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 1639:Src/main.c **** GPIO_InitStruct.Pull = GPIO_PULLUP; 1640:Src/main.c **** HAL_GPIO_Init(GPIOF, &GPIO_InitStruct); 1641:Src/main.c **** 1642:Src/main.c **** /*Configure GPIO pins : ADC_MPD2_CS_Pin SPI5_CNV_Pin ADC_ThrLD2_CS_Pin */ 1643:Src/main.c **** GPIO_InitStruct.Pin = ADC_MPD2_CS_Pin|SPI5_CNV_Pin|ADC_ThrLD2_CS_Pin; 1644:Src/main.c **** GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 1645:Src/main.c **** GPIO_InitStruct.Pull = GPIO_NOPULL; 1646:Src/main.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 1647:Src/main.c **** HAL_GPIO_Init(GPIOF, &GPIO_InitStruct); 1648:Src/main.c **** 1649:Src/main.c **** /*Configure GPIO pins : EN_5V2_Pin LD2_EN_Pin TEC2_PD_Pin */ 1650:Src/main.c **** GPIO_InitStruct.Pin = EN_5V2_Pin|LD2_EN_Pin|TEC2_PD_Pin; 1651:Src/main.c **** GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 1652:Src/main.c **** GPIO_InitStruct.Pull = GPIO_NOPULL; 1653:Src/main.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 1654:Src/main.c **** HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); 1655:Src/main.c **** 1656:Src/main.c **** /*Configure GPIO pin : EN_5V1_Pin */ 1657:Src/main.c **** GPIO_InitStruct.Pin = EN_5V1_Pin; 1658:Src/main.c **** GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 1659:Src/main.c **** GPIO_InitStruct.Pull = GPIO_NOPULL; 1660:Src/main.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; 1661:Src/main.c **** HAL_GPIO_Init(EN_5V1_GPIO_Port, &GPIO_InitStruct); 1662:Src/main.c **** 1663:Src/main.c **** /*Configure GPIO pins : TECEN1_Pin TECEN2_Pin REF2_ON_Pin DAC_TEC2_CS_Pin 1664:Src/main.c **** DAC_LD2_CS_Pin */ 1665:Src/main.c **** GPIO_InitStruct.Pin = TECEN1_Pin|TECEN2_Pin|REF2_ON_Pin|DAC_TEC2_CS_Pin 1666:Src/main.c **** |DAC_LD2_CS_Pin; 1667:Src/main.c **** GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 1668:Src/main.c **** GPIO_InitStruct.Pull = GPIO_NOPULL; 1669:Src/main.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 1670:Src/main.c **** HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 1671:Src/main.c **** 1672:Src/main.c **** /*Configure GPIO pins : TEC2_FLAG1_Pin TEC2_FLAG2_Pin TEC1_FLAG1_Pin TEC1_FLAG2_Pin */ ARM GAS /tmp/ccqopZd5.s page 77 1673:Src/main.c **** GPIO_InitStruct.Pin = TEC2_FLAG1_Pin|TEC2_FLAG2_Pin|TEC1_FLAG1_Pin|TEC1_FLAG2_Pin; 1674:Src/main.c **** GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 1675:Src/main.c **** GPIO_InitStruct.Pull = GPIO_NOPULL; 1676:Src/main.c **** HAL_GPIO_Init(GPIOF, &GPIO_InitStruct); 1677:Src/main.c **** 1678:Src/main.c **** /*Configure GPIO pins : ADC_MPD1_CS_Pin ADC_ThrLD1_CS_Pin */ 1679:Src/main.c **** GPIO_InitStruct.Pin = ADC_MPD1_CS_Pin|ADC_ThrLD1_CS_Pin; 1680:Src/main.c **** GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 1681:Src/main.c **** GPIO_InitStruct.Pull = GPIO_NOPULL; 1682:Src/main.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 1683:Src/main.c **** HAL_GPIO_Init(GPIOE, &GPIO_InitStruct); 1684:Src/main.c **** 1685:Src/main.c **** /*Configure GPIO pin : SPI4_CNV_Pin */ 1686:Src/main.c **** GPIO_InitStruct.Pin = SPI4_CNV_Pin; 1687:Src/main.c **** GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 1688:Src/main.c **** GPIO_InitStruct.Pull = GPIO_NOPULL; 1689:Src/main.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; 1690:Src/main.c **** HAL_GPIO_Init(SPI4_CNV_GPIO_Port, &GPIO_InitStruct); 1691:Src/main.c **** 1692:Src/main.c **** /*Configure GPIO pins : REF0_EN_Pin TEC1_PD_Pin DAC_TEC1_CS_Pin DAC_LD1_CS_Pin 1693:Src/main.c **** OUT_6_Pin OUT_7_Pin OUT_8_Pin OUT_9_Pin 1694:Src/main.c **** OUT_10_Pin */ 1695:Src/main.c **** GPIO_InitStruct.Pin = REF0_EN_Pin|TEC1_PD_Pin|DAC_TEC1_CS_Pin|DAC_LD1_CS_Pin 1696:Src/main.c **** |OUT_6_Pin|OUT_7_Pin|OUT_8_Pin|OUT_9_Pin 1697:Src/main.c **** |OUT_10_Pin; 1698:Src/main.c **** GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 1699:Src/main.c **** GPIO_InitStruct.Pull = GPIO_NOPULL; 1700:Src/main.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 1701:Src/main.c **** HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 1702:Src/main.c **** 1703:Src/main.c **** /*Configure GPIO pins : LD1_EN_Pin TEST_01_Pin PD7 */ 1704:Src/main.c **** GPIO_InitStruct.Pin = LD1_EN_Pin|TEST_01_Pin|GPIO_PIN_7; 1705:Src/main.c **** GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 1706:Src/main.c **** GPIO_InitStruct.Pull = GPIO_NOPULL; 1707:Src/main.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 1708:Src/main.c **** HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); 1709:Src/main.c **** 1710:Src/main.c **** /*Configure GPIO pin : USB_FLAG_Pin */ 1711:Src/main.c **** GPIO_InitStruct.Pin = USB_FLAG_Pin; 1712:Src/main.c **** GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 1713:Src/main.c **** GPIO_InitStruct.Pull = GPIO_NOPULL; 1714:Src/main.c **** HAL_GPIO_Init(USB_FLAG_GPIO_Port, &GPIO_InitStruct); 1715:Src/main.c **** 1716:Src/main.c **** /*Configure GPIO pin : SDMMC1_EN_Pin */ 1717:Src/main.c **** GPIO_InitStruct.Pin = SDMMC1_EN_Pin; 1718:Src/main.c **** GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 1719:Src/main.c **** GPIO_InitStruct.Pull = GPIO_NOPULL; 1720:Src/main.c **** HAL_GPIO_Init(SDMMC1_EN_GPIO_Port, &GPIO_InitStruct); 1721:Src/main.c **** 1722:Src/main.c **** /*Configure GPIO pins : PG9 OUT_0_Pin OUT_1_Pin OUT_2_Pin 1723:Src/main.c **** OUT_3_Pin OUT_4_Pin OUT_5_Pin */ 1724:Src/main.c **** GPIO_InitStruct.Pin = GPIO_PIN_9|OUT_0_Pin|OUT_1_Pin|OUT_2_Pin 1725:Src/main.c **** |OUT_3_Pin|OUT_4_Pin|OUT_5_Pin; 1726:Src/main.c **** GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 1727:Src/main.c **** GPIO_InitStruct.Pull = GPIO_NOPULL; 1728:Src/main.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 1729:Src/main.c **** HAL_GPIO_Init(GPIOG, &GPIO_InitStruct); ARM GAS /tmp/ccqopZd5.s page 78 1730:Src/main.c **** 1731:Src/main.c **** /* USER CODE BEGIN MX_GPIO_Init_2 */ 1732:Src/main.c **** /* USER CODE END MX_GPIO_Init_2 */ 1733:Src/main.c **** } 1734:Src/main.c **** 1735:Src/main.c **** /* USER CODE BEGIN 4 */ 1736:Src/main.c **** 1737:Src/main.c **** //void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart) { 1738:Src/main.c **** 1739:Src/main.c **** // UART_transmission_request = NO_MESS; 1740:Src/main.c **** 1741:Src/main.c **** //} 1742:Src/main.c **** 1743:Src/main.c **** static void Init_params(void) 1744:Src/main.c **** { 1745:Src/main.c **** TO6 = 0; 1746:Src/main.c **** TO7 = 0; 1747:Src/main.c **** TO7_before = 0; 1748:Src/main.c **** TO6_before = 0; 1749:Src/main.c **** TO6_uart = 0; 1750:Src/main.c **** flg_tmt = 0; 1751:Src/main.c **** UART_rec_incr = 0; 1752:Src/main.c **** fgoto = 0; 1753:Src/main.c **** sizeoffile = 0; 1754:Src/main.c **** u_tx_flg = 0; 1755:Src/main.c **** u_rx_flg = 0; 1756:Src/main.c **** //State_Data[0]=0; 1757:Src/main.c **** //State_Data[1]=0;//All OK! 1758:Src/main.c **** for (uint16_t i=0; iWORK_EN = ((uint8_t)((*temp2)>>0))&0x01; 1910:Src/main.c **** Curr_setup->U5V1_EN = ((uint8_t)((*temp2)>>1))&0x01; 1911:Src/main.c **** Curr_setup->U5V2_EN = ((uint8_t)((*temp2)>>2))&0x01; 1912:Src/main.c **** Curr_setup->LD1_EN = ((uint8_t)((*temp2)>>3))&0x01; 1913:Src/main.c **** Curr_setup->LD2_EN = ((uint8_t)((*temp2)>>4))&0x01; 1914:Src/main.c **** Curr_setup->REF1_EN = ((uint8_t)((*temp2)>>5))&0x01; 1915:Src/main.c **** Curr_setup->REF2_EN = ((uint8_t)((*temp2)>>6))&0x01; 1916:Src/main.c **** Curr_setup->TEC1_EN = ((uint8_t)((*temp2)>>7))&0x01; 1917:Src/main.c **** Curr_setup->TEC2_EN = ((uint8_t)((*temp2)>>8))&0x01; 1918:Src/main.c **** Curr_setup->TS1_EN = ((uint8_t)((*temp2)>>9))&0x01; 1919:Src/main.c **** Curr_setup->TS2_EN = ((uint8_t)((*temp2)>>10))&0x01; 1920:Src/main.c **** Curr_setup->SD_EN = ((uint8_t)((*temp2)>>11))&0x01; 1921:Src/main.c **** Curr_setup->PI1_RD = ((uint8_t)((*temp2)>>12))&0x01; 1922:Src/main.c **** Curr_setup->PI2_RD = ((uint8_t)((*temp2)>>13))&0x01; 1923:Src/main.c **** 1924:Src/main.c **** temp2++; 1925:Src/main.c **** LD1_curr_setup->LD_TEMP = (uint16_t)(*temp2); 1926:Src/main.c **** temp2++; 1927:Src/main.c **** LD2_curr_setup->LD_TEMP = (uint16_t)(*temp2); 1928:Src/main.c **** temp2++; 1929:Src/main.c **** temp2++; 1930:Src/main.c **** temp2++; 1931:Src/main.c **** Curr_setup->AVERAGES = (uint16_t)(*temp2); 1932:Src/main.c **** temp2++; 1933:Src/main.c **** LD1_curr_setup->P_coef_temp = (float)((uint16_t)(*temp2))/((float)(256));//(float)(1/(float)((uint 1934:Src/main.c **** temp2++; 1935:Src/main.c **** LD1_curr_setup->I_coef_temp = (float)((uint16_t)(*temp2))/((float)(256));//(float)(1/(float)((uint 1936:Src/main.c **** temp2++; 1937:Src/main.c **** LD2_curr_setup->P_coef_temp = (float)((uint16_t)(*temp2))/((float)(256));//(float)(1/(float)((uint 1938:Src/main.c **** temp2++; 1939:Src/main.c **** LD2_curr_setup->I_coef_temp = (float)((uint16_t)(*temp2))/((float)(256));//(float)(1/(float)((uint 1940:Src/main.c **** temp2++; 1941:Src/main.c **** Long_Data[13] = (uint16_t)(*temp2);//Message ID 1942:Src/main.c **** temp2++; 1943:Src/main.c **** LD1_curr_setup->CURRENT = (uint16_t)(*temp2); 1944:Src/main.c **** temp2++; 1945:Src/main.c **** LD2_curr_setup->CURRENT = (uint16_t)(*temp2); 1946:Src/main.c **** temp2++; 1947:Src/main.c **** 1948:Src/main.c **** if (Curr_setup->U5V1_EN) 1949:Src/main.c **** { 1950:Src/main.c **** HAL_GPIO_WritePin(EN_5V1_GPIO_Port, EN_5V1_Pin, GPIO_PIN_SET); 1951:Src/main.c **** } 1952:Src/main.c **** else 1953:Src/main.c **** { 1954:Src/main.c **** HAL_GPIO_WritePin(EN_5V1_GPIO_Port, EN_5V1_Pin, GPIO_PIN_RESET); 1955:Src/main.c **** } 1956:Src/main.c **** 1957:Src/main.c **** if (Curr_setup->U5V2_EN) ARM GAS /tmp/ccqopZd5.s page 82 1958:Src/main.c **** { 1959:Src/main.c **** HAL_GPIO_WritePin(EN_5V2_GPIO_Port, EN_5V2_Pin, GPIO_PIN_SET); 1960:Src/main.c **** } 1961:Src/main.c **** else 1962:Src/main.c **** { 1963:Src/main.c **** HAL_GPIO_WritePin(EN_5V2_GPIO_Port, EN_5V2_Pin, GPIO_PIN_RESET); 1964:Src/main.c **** } 1965:Src/main.c **** 1966:Src/main.c **** if (Curr_setup->LD1_EN) 1967:Src/main.c **** { 1968:Src/main.c **** HAL_GPIO_WritePin(LD1_EN_GPIO_Port, LD1_EN_Pin, GPIO_PIN_SET); 1969:Src/main.c **** //LL_SPI_Enable(SPI2);//Enable SPI for Laser1 DAC 1970:Src/main.c **** } 1971:Src/main.c **** else 1972:Src/main.c **** { 1973:Src/main.c **** HAL_GPIO_WritePin(LD1_EN_GPIO_Port, LD1_EN_Pin, GPIO_PIN_RESET); 1974:Src/main.c **** //LL_SPI_Disable(SPI2);//Disable SPI for Laser1 DAC 1975:Src/main.c **** } 1976:Src/main.c **** 1977:Src/main.c **** if (Curr_setup->LD2_EN) 1978:Src/main.c **** { 1979:Src/main.c **** HAL_GPIO_WritePin(LD2_EN_GPIO_Port, LD2_EN_Pin, GPIO_PIN_SET); 1980:Src/main.c **** //LL_SPI_Enable(SPI6);//Enable SPI for Laser2 DAC 1981:Src/main.c **** } 1982:Src/main.c **** else 1983:Src/main.c **** { 1984:Src/main.c **** HAL_GPIO_WritePin(LD2_EN_GPIO_Port, LD2_EN_Pin, GPIO_PIN_RESET); 1985:Src/main.c **** //LL_SPI_Disable(SPI6);//Disable SPI for Laser2 DAC 1986:Src/main.c **** } 1987:Src/main.c **** 1988:Src/main.c **** if (Curr_setup->REF1_EN) 1989:Src/main.c **** { 1990:Src/main.c **** HAL_GPIO_WritePin(REF0_EN_GPIO_Port, REF0_EN_Pin, GPIO_PIN_SET); 1991:Src/main.c **** } 1992:Src/main.c **** else 1993:Src/main.c **** { 1994:Src/main.c **** HAL_GPIO_WritePin(REF0_EN_GPIO_Port, REF0_EN_Pin, GPIO_PIN_RESET); 1995:Src/main.c **** } 1996:Src/main.c **** 1997:Src/main.c **** if (Curr_setup->REF2_EN) 1998:Src/main.c **** { 1999:Src/main.c **** HAL_GPIO_WritePin(REF2_ON_GPIO_Port, REF2_ON_Pin, GPIO_PIN_SET); 2000:Src/main.c **** } 2001:Src/main.c **** else 2002:Src/main.c **** { 2003:Src/main.c **** HAL_GPIO_WritePin(REF2_ON_GPIO_Port, REF2_ON_Pin, GPIO_PIN_RESET); 2004:Src/main.c **** } 2005:Src/main.c **** 2006:Src/main.c **** if ((Curr_setup->TS1_EN)&&(Curr_setup->TEC1_EN)) 2007:Src/main.c **** { 2008:Src/main.c **** Set_LTEC(3,32767); 2009:Src/main.c **** Set_LTEC(3,32767); 2010:Src/main.c **** HAL_GPIO_WritePin(TEC1_PD_GPIO_Port, TEC1_PD_Pin, GPIO_PIN_SET); 2011:Src/main.c **** HAL_GPIO_WritePin(TECEN1_GPIO_Port, TECEN1_Pin, GPIO_PIN_SET); 2012:Src/main.c **** } 2013:Src/main.c **** else 2014:Src/main.c **** { ARM GAS /tmp/ccqopZd5.s page 83 2015:Src/main.c **** HAL_GPIO_WritePin(TECEN1_GPIO_Port, TECEN1_Pin, GPIO_PIN_RESET); 2016:Src/main.c **** HAL_GPIO_WritePin(TEC1_PD_GPIO_Port, TEC1_PD_Pin, GPIO_PIN_RESET); 2017:Src/main.c **** } 2018:Src/main.c **** 2019:Src/main.c **** if ((Curr_setup->TS2_EN)&&(Curr_setup->TEC2_EN)) 2020:Src/main.c **** { 2021:Src/main.c **** Set_LTEC(4,32767); 2022:Src/main.c **** Set_LTEC(4,32767); 2023:Src/main.c **** HAL_GPIO_WritePin(TEC2_PD_GPIO_Port, TEC2_PD_Pin, GPIO_PIN_SET); 2024:Src/main.c **** HAL_GPIO_WritePin(TECEN2_GPIO_Port, TECEN2_Pin, GPIO_PIN_SET); 2025:Src/main.c **** } 2026:Src/main.c **** else 2027:Src/main.c **** { 2028:Src/main.c **** HAL_GPIO_WritePin(TECEN2_GPIO_Port, TECEN2_Pin, GPIO_PIN_RESET); 2029:Src/main.c **** HAL_GPIO_WritePin(TEC2_PD_GPIO_Port, TEC2_PD_Pin, GPIO_PIN_RESET); 2030:Src/main.c **** } 2031:Src/main.c **** 2032:Src/main.c **** if (Curr_setup->PI1_RD==0) 2033:Src/main.c **** { 2034:Src/main.c **** LD1_curr_setup->P_coef_temp = 10; 2035:Src/main.c **** LD1_curr_setup->I_coef_temp = 0.01; 2036:Src/main.c **** } 2037:Src/main.c **** 2038:Src/main.c **** if (Curr_setup->PI2_RD==0) 2039:Src/main.c **** { 2040:Src/main.c **** LD2_curr_setup->P_coef_temp = 10; 2041:Src/main.c **** LD2_curr_setup->I_coef_temp = 0.01; 2042:Src/main.c **** } 2043:Src/main.c **** } 2044:Src/main.c **** 2045:Src/main.c **** static void Decode_task(uint16_t *Command, LDx_SetupTypeDef *LD1_curr_setup, LDx_SetupTypeDef *LD2_ 2046:Src/main.c **** { 253 .loc 2 2046 1 is_stmt 1 view -0 254 .cfi_startproc 255 @ args = 0, pretend = 0, frame = 8 256 @ frame_needed = 0, uses_anonymous_args = 0 257 @ link register save eliminated. 258 .loc 2 2046 1 is_stmt 0 view .LVU66 259 0000 82B0 sub sp, sp, #8 260 .LCFI3: 261 .cfi_def_cfa_offset 8 2047:Src/main.c **** uint16_t *temp2; 262 .loc 2 2047 2 is_stmt 1 view .LVU67 2048:Src/main.c **** 2049:Src/main.c **** temp2 = (uint16_t *)Command; 263 .loc 2 2049 2 view .LVU68 264 .LVL15: 2050:Src/main.c **** Curr_setup->WORK_EN = ((uint8_t)((*temp2)>>0))&0x01; 265 .loc 2 2050 2 view .LVU69 266 .loc 2 2050 36 is_stmt 0 view .LVU70 267 0002 0288 ldrh r2, [r0] 268 .LVL16: 269 .loc 2 2050 48 view .LVU71 270 0004 02F00102 and r2, r2, #1 271 .loc 2 2050 22 view .LVU72 272 0008 1A70 strb r2, [r3] 2051:Src/main.c **** Curr_setup->U5V1_EN = ((uint8_t)((*temp2)>>1))&0x01; ARM GAS /tmp/ccqopZd5.s page 84 273 .loc 2 2051 2 is_stmt 1 view .LVU73 274 .loc 2 2051 36 is_stmt 0 view .LVU74 275 000a 0288 ldrh r2, [r0] 276 .loc 2 2051 48 view .LVU75 277 000c C2F34002 ubfx r2, r2, #1, #1 278 .loc 2 2051 22 view .LVU76 279 0010 5A70 strb r2, [r3, #1] 2052:Src/main.c **** Curr_setup->U5V2_EN = ((uint8_t)((*temp2)>>2))&0x01; 280 .loc 2 2052 2 is_stmt 1 view .LVU77 281 .loc 2 2052 36 is_stmt 0 view .LVU78 282 0012 0288 ldrh r2, [r0] 283 .loc 2 2052 48 view .LVU79 284 0014 C2F38002 ubfx r2, r2, #2, #1 285 .loc 2 2052 22 view .LVU80 286 0018 9A70 strb r2, [r3, #2] 2053:Src/main.c **** Curr_setup->LD1_EN = ((uint8_t)((*temp2)>>3))&0x01; 287 .loc 2 2053 2 is_stmt 1 view .LVU81 288 .loc 2 2053 35 is_stmt 0 view .LVU82 289 001a 0288 ldrh r2, [r0] 290 .loc 2 2053 47 view .LVU83 291 001c C2F3C002 ubfx r2, r2, #3, #1 292 .loc 2 2053 21 view .LVU84 293 0020 DA70 strb r2, [r3, #3] 2054:Src/main.c **** Curr_setup->LD2_EN = ((uint8_t)((*temp2)>>4))&0x01; 294 .loc 2 2054 2 is_stmt 1 view .LVU85 295 .loc 2 2054 35 is_stmt 0 view .LVU86 296 0022 0288 ldrh r2, [r0] 297 .loc 2 2054 47 view .LVU87 298 0024 C2F30012 ubfx r2, r2, #4, #1 299 .loc 2 2054 21 view .LVU88 300 0028 1A71 strb r2, [r3, #4] 2055:Src/main.c **** Curr_setup->REF1_EN = ((uint8_t)((*temp2)>>5))&0x01; 301 .loc 2 2055 2 is_stmt 1 view .LVU89 302 .loc 2 2055 36 is_stmt 0 view .LVU90 303 002a 0288 ldrh r2, [r0] 304 .loc 2 2055 48 view .LVU91 305 002c C2F34012 ubfx r2, r2, #5, #1 306 .loc 2 2055 22 view .LVU92 307 0030 5A71 strb r2, [r3, #5] 2056:Src/main.c **** Curr_setup->REF2_EN = ((uint8_t)((*temp2)>>6))&0x01; 308 .loc 2 2056 2 is_stmt 1 view .LVU93 309 .loc 2 2056 36 is_stmt 0 view .LVU94 310 0032 0288 ldrh r2, [r0] 311 .loc 2 2056 48 view .LVU95 312 0034 C2F38012 ubfx r2, r2, #6, #1 313 .loc 2 2056 22 view .LVU96 314 0038 9A71 strb r2, [r3, #6] 2057:Src/main.c **** Curr_setup->TEC1_EN = ((uint8_t)((*temp2)>>7))&0x01; 315 .loc 2 2057 2 is_stmt 1 view .LVU97 316 .loc 2 2057 36 is_stmt 0 view .LVU98 317 003a 0288 ldrh r2, [r0] 318 .loc 2 2057 48 view .LVU99 319 003c C2F3C012 ubfx r2, r2, #7, #1 320 .loc 2 2057 22 view .LVU100 321 0040 DA71 strb r2, [r3, #7] 2058:Src/main.c **** Curr_setup->TEC2_EN = ((uint8_t)((*temp2)>>8))&0x01; 322 .loc 2 2058 2 is_stmt 1 view .LVU101 ARM GAS /tmp/ccqopZd5.s page 85 323 .loc 2 2058 36 is_stmt 0 view .LVU102 324 0042 0288 ldrh r2, [r0] 325 .loc 2 2058 48 view .LVU103 326 0044 C2F30022 ubfx r2, r2, #8, #1 327 .loc 2 2058 22 view .LVU104 328 0048 1A72 strb r2, [r3, #8] 2059:Src/main.c **** Curr_setup->TS1_EN = ((uint8_t)((*temp2)>>9))&0x01; 329 .loc 2 2059 2 is_stmt 1 view .LVU105 330 .loc 2 2059 35 is_stmt 0 view .LVU106 331 004a 0288 ldrh r2, [r0] 332 .loc 2 2059 47 view .LVU107 333 004c C2F34022 ubfx r2, r2, #9, #1 334 .loc 2 2059 21 view .LVU108 335 0050 5A72 strb r2, [r3, #9] 2060:Src/main.c **** Curr_setup->TS2_EN = ((uint8_t)((*temp2)>>10))&0x01; 336 .loc 2 2060 2 is_stmt 1 view .LVU109 337 .loc 2 2060 35 is_stmt 0 view .LVU110 338 0052 0288 ldrh r2, [r0] 339 .loc 2 2060 48 view .LVU111 340 0054 C2F38022 ubfx r2, r2, #10, #1 341 .loc 2 2060 21 view .LVU112 342 0058 9A72 strb r2, [r3, #10] 2061:Src/main.c **** Curr_setup->SD_EN = ((uint8_t)((*temp2)>>11))&0x01; 343 .loc 2 2061 2 is_stmt 1 view .LVU113 344 .loc 2 2061 34 is_stmt 0 view .LVU114 345 005a 0288 ldrh r2, [r0] 346 .loc 2 2061 47 view .LVU115 347 005c C2F3C022 ubfx r2, r2, #11, #1 348 .loc 2 2061 20 view .LVU116 349 0060 DA72 strb r2, [r3, #11] 2062:Src/main.c **** Curr_setup->PI1_RD = ((uint8_t)((*temp2)>>12))&0x01; 350 .loc 2 2062 2 is_stmt 1 view .LVU117 351 .loc 2 2062 35 is_stmt 0 view .LVU118 352 0062 0288 ldrh r2, [r0] 353 .loc 2 2062 48 view .LVU119 354 0064 C2F30032 ubfx r2, r2, #12, #1 355 .loc 2 2062 21 view .LVU120 356 0068 1A73 strb r2, [r3, #12] 2063:Src/main.c **** Curr_setup->PI2_RD = ((uint8_t)((*temp2)>>13))&0x01; 357 .loc 2 2063 2 is_stmt 1 view .LVU121 358 .loc 2 2063 35 is_stmt 0 view .LVU122 359 006a 0288 ldrh r2, [r0] 360 .loc 2 2063 48 view .LVU123 361 006c C2F34032 ubfx r2, r2, #13, #1 362 .loc 2 2063 21 view .LVU124 363 0070 5A73 strb r2, [r3, #13] 2064:Src/main.c **** 2065:Src/main.c **** temp2++; 364 .loc 2 2065 2 is_stmt 1 view .LVU125 365 .LVL17: 2066:Src/main.c **** task.task_type = (uint8_t)(*temp2); temp2++; 366 .loc 2 2066 2 view .LVU126 367 .loc 2 2066 21 is_stmt 0 view .LVU127 368 0072 8278 ldrb r2, [r0, #2] @ zero_extendqisi2 369 .loc 2 2066 19 view .LVU128 370 0074 384B ldr r3, .L13+8 371 .LVL18: ARM GAS /tmp/ccqopZd5.s page 86 372 .loc 2 2066 19 view .LVU129 373 0076 1A70 strb r2, [r3] 374 .loc 2 2066 40 is_stmt 1 view .LVU130 375 .LVL19: 2067:Src/main.c **** task.min_param = (float)(*temp2); temp2++; 376 .loc 2 2067 2 view .LVU131 377 .loc 2 2067 29 is_stmt 0 view .LVU132 378 0078 8288 ldrh r2, [r0, #4] 379 007a 07EE902A vmov s15, r2 @ int 380 .loc 2 2067 21 view .LVU133 381 007e F8EE677A vcvt.f32.u32 s15, s15 382 .loc 2 2067 19 view .LVU134 383 0082 C3ED017A vstr.32 s15, [r3, #4] 384 .loc 2 2067 38 is_stmt 1 view .LVU135 385 .LVL20: 2068:Src/main.c **** task.max_param = (float)(*temp2); temp2++; 386 .loc 2 2068 2 view .LVU136 387 .loc 2 2068 29 is_stmt 0 view .LVU137 388 0086 C288 ldrh r2, [r0, #6] 389 0088 07EE902A vmov s15, r2 @ int 390 .loc 2 2068 21 view .LVU138 391 008c F8EE677A vcvt.f32.u32 s15, s15 392 .loc 2 2068 19 view .LVU139 393 0090 C3ED027A vstr.32 s15, [r3, #8] 394 .loc 2 2068 38 is_stmt 1 view .LVU140 395 .LVL21: 2069:Src/main.c **** task.delta_param = (float)(*temp2); temp2++; 396 .loc 2 2069 2 view .LVU141 397 .loc 2 2069 29 is_stmt 0 view .LVU142 398 0094 0289 ldrh r2, [r0, #8] 399 0096 07EE902A vmov s15, r2 @ int 400 .loc 2 2069 21 view .LVU143 401 009a F8EE677A vcvt.f32.u32 s15, s15 402 .loc 2 2069 19 view .LVU144 403 009e C3ED037A vstr.32 s15, [r3, #12] 404 .loc 2 2069 38 is_stmt 1 view .LVU145 405 .LVL22: 2070:Src/main.c **** task.dt = (float)(*temp2) / 100.0; temp2++; 406 .loc 2 2070 2 view .LVU146 407 .loc 2 2070 29 is_stmt 0 view .LVU147 408 00a2 4289 ldrh r2, [r0, #10] 409 00a4 07EE102A vmov s14, r2 @ int 410 .loc 2 2070 21 view .LVU148 411 00a8 B8EE477B vcvt.f64.u32 d7, s14 412 .loc 2 2070 37 view .LVU149 413 00ac 9FED285B vldr.64 d5, .L13 414 00b0 87EE056B vdiv.f64 d6, d7, d5 415 .loc 2 2070 19 view .LVU150 416 00b4 FCEEC67B vcvt.u32.f64 s15, d6 417 00b8 CDED017A vstr.32 s15, [sp, #4] @ int 418 00bc 9DF80420 ldrb r2, [sp, #4] @ zero_extendqisi2 419 00c0 1A75 strb r2, [r3, #20] 420 .loc 2 2070 46 is_stmt 1 view .LVU151 421 .LVL23: 2071:Src/main.c **** task.sec_param = (float)(*temp2); temp2++; 422 .loc 2 2071 2 view .LVU152 423 .loc 2 2071 29 is_stmt 0 view .LVU153 ARM GAS /tmp/ccqopZd5.s page 87 424 00c2 8189 ldrh r1, [r0, #12] 425 .LVL24: 426 .loc 2 2071 29 view .LVU154 427 00c4 07EE901A vmov s15, r1 @ int 428 .loc 2 2071 21 view .LVU155 429 00c8 F8EE677A vcvt.f32.u32 s15, s15 430 .loc 2 2071 19 view .LVU156 431 00cc C3ED067A vstr.32 s15, [r3, #24] 432 .loc 2 2071 38 is_stmt 1 view .LVU157 433 .LVL25: 2072:Src/main.c **** task.curr = (float)(*temp2); temp2++; 434 .loc 2 2072 2 view .LVU158 435 .loc 2 2072 29 is_stmt 0 view .LVU159 436 00d0 C189 ldrh r1, [r0, #14] 437 00d2 07EE901A vmov s15, r1 @ int 438 .loc 2 2072 21 view .LVU160 439 00d6 F8EE677A vcvt.f32.u32 s15, s15 440 .loc 2 2072 19 view .LVU161 441 00da C3ED077A vstr.32 s15, [r3, #28] 442 .loc 2 2072 38 is_stmt 1 view .LVU162 443 .LVL26: 2073:Src/main.c **** task.temp = (float)(*temp2); temp2++; 444 .loc 2 2073 2 view .LVU163 445 .loc 2 2073 29 is_stmt 0 view .LVU164 446 00de 018A ldrh r1, [r0, #16] 447 00e0 07EE901A vmov s15, r1 @ int 448 .loc 2 2073 21 view .LVU165 449 00e4 F8EE677A vcvt.f32.u32 s15, s15 450 .loc 2 2073 19 view .LVU166 451 00e8 C3ED087A vstr.32 s15, [r3, #32] 452 .loc 2 2073 38 is_stmt 1 view .LVU167 453 .LVL27: 2074:Src/main.c **** task.tau = (float)(*temp2); temp2++; 454 .loc 2 2074 2 view .LVU168 455 .loc 2 2074 29 is_stmt 0 view .LVU169 456 00ec 418A ldrh r1, [r0, #18] 457 .loc 2 2074 19 view .LVU170 458 00ee D982 strh r1, [r3, #22] @ movhi 459 .loc 2 2074 38 is_stmt 1 view .LVU171 460 .LVL28: 2075:Src/main.c **** task.p_coef_1 = (float)(*temp2) * 256.0; temp2++; 461 .loc 2 2075 2 view .LVU172 462 .loc 2 2075 29 is_stmt 0 view .LVU173 463 00f0 818A ldrh r1, [r0, #20] 464 00f2 07EE101A vmov s14, r1 @ int 465 .loc 2 2075 21 view .LVU174 466 00f6 B8EE477A vcvt.f32.u32 s14, s14 467 .loc 2 2075 37 view .LVU175 468 00fa DFED186A vldr.32 s13, .L13+12 469 00fe 27EE267A vmul.f32 s14, s14, s13 470 .loc 2 2075 19 view .LVU176 471 0102 83ED0A7A vstr.32 s14, [r3, #40] 472 .loc 2 2075 46 is_stmt 1 view .LVU177 473 .LVL29: 2076:Src/main.c **** task.i_coef_1 = (float)(*temp2) * 256.0; temp2++; 474 .loc 2 2076 2 view .LVU178 475 .loc 2 2076 29 is_stmt 0 view .LVU179 ARM GAS /tmp/ccqopZd5.s page 88 476 0106 C18A ldrh r1, [r0, #22] 477 0108 07EE101A vmov s14, r1 @ int 478 .loc 2 2076 21 view .LVU180 479 010c B8EE477A vcvt.f32.u32 s14, s14 480 .loc 2 2076 37 view .LVU181 481 0110 27EE267A vmul.f32 s14, s14, s13 482 .loc 2 2076 19 view .LVU182 483 0114 83ED097A vstr.32 s14, [r3, #36] 484 .loc 2 2076 46 is_stmt 1 view .LVU183 485 .LVL30: 2077:Src/main.c **** task.p_coef_2 = (float)(*temp2) * 256.0; temp2++; 486 .loc 2 2077 2 view .LVU184 487 .loc 2 2077 29 is_stmt 0 view .LVU185 488 0118 018B ldrh r1, [r0, #24] 489 011a 07EE101A vmov s14, r1 @ int 490 .loc 2 2077 21 view .LVU186 491 011e B8EE477A vcvt.f32.u32 s14, s14 492 .loc 2 2077 37 view .LVU187 493 0122 27EE267A vmul.f32 s14, s14, s13 494 .loc 2 2077 19 view .LVU188 495 0126 83ED0C7A vstr.32 s14, [r3, #48] 496 .loc 2 2077 46 is_stmt 1 view .LVU189 497 .LVL31: 2078:Src/main.c **** task.i_coef_2 = (float)(*temp2) * 256.0; temp2++; 498 .loc 2 2078 2 view .LVU190 499 .loc 2 2078 29 is_stmt 0 view .LVU191 500 012a 418B ldrh r1, [r0, #26] 501 012c 07EE901A vmov s15, r1 @ int 502 .loc 2 2078 21 view .LVU192 503 0130 F8EE677A vcvt.f32.u32 s15, s15 504 .loc 2 2078 37 view .LVU193 505 0134 67EEA67A vmul.f32 s15, s15, s13 506 .loc 2 2078 19 view .LVU194 507 0138 C3ED0B7A vstr.32 s15, [r3, #44] 508 .loc 2 2078 46 is_stmt 1 view .LVU195 509 .LVL32: 2079:Src/main.c **** 2080:Src/main.c **** TO10_counter = task.dt / 10; 510 .loc 2 2080 2 view .LVU196 511 .loc 2 2080 25 is_stmt 0 view .LVU197 512 013c 084B ldr r3, .L13+16 513 013e A3FB0232 umull r3, r2, r3, r2 514 0142 D208 lsrs r2, r2, #3 515 .loc 2 2080 15 view .LVU198 516 0144 074B ldr r3, .L13+20 517 0146 1A60 str r2, [r3] 2081:Src/main.c **** } 518 .loc 2 2081 1 view .LVU199 519 0148 02B0 add sp, sp, #8 520 .LCFI4: 521 .cfi_def_cfa_offset 0 522 @ sp needed 523 014a 7047 bx lr 524 .L14: 525 014c AFF30080 .align 3 526 .L13: 527 0150 00000000 .word 0 ARM GAS /tmp/ccqopZd5.s page 89 528 0154 00005940 .word 1079574528 529 0158 00000000 .word .LANCHOR1 530 015c 00008043 .word 1132462080 531 0160 CDCCCCCC .word -858993459 532 0164 00000000 .word .LANCHOR2 533 .cfi_endproc 534 .LFE1208: 536 .section .text.PID_Controller_Temp,"ax",%progbits 537 .align 1 538 .syntax unified 539 .thumb 540 .thumb_func 541 .fpu fpv5-d16 543 PID_Controller_Temp: 544 .LVL33: 545 .LFB1214: 2082:Src/main.c **** 2083:Src/main.c **** void OUT_trigger(uint8_t out_n) 2084:Src/main.c **** { 2085:Src/main.c **** switch (out_n) 2086:Src/main.c **** { 2087:Src/main.c **** case 0: 2088:Src/main.c **** HAL_GPIO_WritePin(OUT_0_GPIO_Port, OUT_0_Pin, GPIO_PIN_SET); 2089:Src/main.c **** HAL_GPIO_WritePin(OUT_0_GPIO_Port, OUT_0_Pin, GPIO_PIN_RESET); 2090:Src/main.c **** break; 2091:Src/main.c **** 2092:Src/main.c **** case 1: 2093:Src/main.c **** HAL_GPIO_WritePin(OUT_1_GPIO_Port, OUT_1_Pin, GPIO_PIN_SET); 2094:Src/main.c **** HAL_GPIO_WritePin(OUT_1_GPIO_Port, OUT_1_Pin, GPIO_PIN_RESET); 2095:Src/main.c **** break; 2096:Src/main.c **** 2097:Src/main.c **** case 2: 2098:Src/main.c **** HAL_GPIO_WritePin(OUT_2_GPIO_Port, OUT_2_Pin, GPIO_PIN_SET); 2099:Src/main.c **** HAL_GPIO_WritePin(OUT_2_GPIO_Port, OUT_2_Pin, GPIO_PIN_RESET); 2100:Src/main.c **** break; 2101:Src/main.c **** 2102:Src/main.c **** case 3: 2103:Src/main.c **** HAL_GPIO_WritePin(OUT_3_GPIO_Port, OUT_3_Pin, GPIO_PIN_SET); 2104:Src/main.c **** HAL_GPIO_WritePin(OUT_3_GPIO_Port, OUT_3_Pin, GPIO_PIN_RESET); 2105:Src/main.c **** break; 2106:Src/main.c **** 2107:Src/main.c **** case 4: 2108:Src/main.c **** HAL_GPIO_WritePin(OUT_4_GPIO_Port, OUT_4_Pin, GPIO_PIN_SET); 2109:Src/main.c **** HAL_GPIO_WritePin(OUT_4_GPIO_Port, OUT_4_Pin, GPIO_PIN_RESET); 2110:Src/main.c **** break; 2111:Src/main.c **** 2112:Src/main.c **** case 5: 2113:Src/main.c **** HAL_GPIO_WritePin(OUT_5_GPIO_Port, OUT_5_Pin, GPIO_PIN_SET); 2114:Src/main.c **** HAL_GPIO_WritePin(OUT_5_GPIO_Port, OUT_5_Pin, GPIO_PIN_RESET); 2115:Src/main.c **** break; 2116:Src/main.c **** 2117:Src/main.c **** case 6: 2118:Src/main.c **** HAL_GPIO_WritePin(OUT_6_GPIO_Port, OUT_6_Pin, GPIO_PIN_SET); 2119:Src/main.c **** HAL_GPIO_WritePin(OUT_6_GPIO_Port, OUT_6_Pin, GPIO_PIN_RESET); 2120:Src/main.c **** break; 2121:Src/main.c **** 2122:Src/main.c **** case 7: ARM GAS /tmp/ccqopZd5.s page 90 2123:Src/main.c **** HAL_GPIO_WritePin(OUT_7_GPIO_Port, OUT_7_Pin, GPIO_PIN_SET); 2124:Src/main.c **** HAL_GPIO_WritePin(OUT_7_GPIO_Port, OUT_7_Pin, GPIO_PIN_RESET); 2125:Src/main.c **** break; 2126:Src/main.c **** 2127:Src/main.c **** case 8: 2128:Src/main.c **** HAL_GPIO_WritePin(OUT_8_GPIO_Port, OUT_8_Pin, GPIO_PIN_SET); 2129:Src/main.c **** HAL_GPIO_WritePin(OUT_8_GPIO_Port, OUT_8_Pin, GPIO_PIN_RESET); 2130:Src/main.c **** break; 2131:Src/main.c **** 2132:Src/main.c **** case 9: 2133:Src/main.c **** HAL_GPIO_WritePin(OUT_9_GPIO_Port, OUT_9_Pin, GPIO_PIN_SET); 2134:Src/main.c **** HAL_GPIO_WritePin(OUT_9_GPIO_Port, OUT_9_Pin, GPIO_PIN_RESET); 2135:Src/main.c **** break; 2136:Src/main.c **** } 2137:Src/main.c **** } 2138:Src/main.c **** 2139:Src/main.c **** void Set_LTEC(uint8_t num, uint16_t DATA) 2140:Src/main.c **** { 2141:Src/main.c **** uint32_t tmp32; 2142:Src/main.c **** 2143:Src/main.c **** switch (num) 2144:Src/main.c **** { 2145:Src/main.c **** case 1: 2146:Src/main.c **** HAL_GPIO_WritePin(DAC_LD1_CS_GPIO_Port, DAC_LD1_CS_Pin, GPIO_PIN_RESET);//Start operation with L 2147:Src/main.c **** //tmp32=0; 2148:Src/main.c **** //while(tmp32<500){tmp32++;} 2149:Src/main.c **** tmp32 = 0; 2150:Src/main.c **** while((!LL_SPI_IsActiveFlag_TXE(SPI2))&&(tmp32<=500)) {tmp32++;}//When trans. last data cycle wi 2151:Src/main.c **** LL_SPI_TransmitData16(SPI2, DATA);//Transmit word to Laser1 DAC 2152:Src/main.c **** tmp32 = 0; 2153:Src/main.c **** while((!LL_SPI_IsActiveFlag_RXNE(SPI2))&&(tmp32<=500)) {tmp32++;}//When trans. last data cycle w 2154:Src/main.c **** (void) SPI2->DR; 2155:Src/main.c **** break; 2156:Src/main.c **** case 2: 2157:Src/main.c **** //HAL_GPIO_TogglePin(OUT_11_GPIO_Port, OUT_11_Pin); //for debug purposes 2158:Src/main.c **** HAL_GPIO_WritePin(DAC_LD2_CS_GPIO_Port, DAC_LD2_CS_Pin, GPIO_PIN_RESET);//Start operation with L 2159:Src/main.c **** //tmp32=0; 2160:Src/main.c **** //while(tmp32<500){tmp32++;} 2161:Src/main.c **** tmp32 = 0; 2162:Src/main.c **** while((!LL_SPI_IsActiveFlag_TXE(SPI6))&&(tmp32<=500)) {tmp32++;}//When trans. last data cycle wi 2163:Src/main.c **** LL_SPI_TransmitData16(SPI6, DATA);//Transmit word to Laser1 DAC 2164:Src/main.c **** tmp32 = 0; 2165:Src/main.c **** while((!LL_SPI_IsActiveFlag_RXNE(SPI6))&&(tmp32<=500)) {tmp32++;}//When trans. last data cycle w 2166:Src/main.c **** (void) SPI6->DR; 2167:Src/main.c **** break; 2168:Src/main.c **** case 3: 2169:Src/main.c **** HAL_GPIO_WritePin(DAC_TEC1_CS_GPIO_Port, DAC_TEC1_CS_Pin, GPIO_PIN_RESET);//Start operation with 2170:Src/main.c **** //tmp32=0; 2171:Src/main.c **** //while(tmp32<500){tmp32++;} 2172:Src/main.c **** tmp32 = 0; 2173:Src/main.c **** while((!LL_SPI_IsActiveFlag_TXE(SPI2))&&(tmp32<=500)) {tmp32++;}//When trans. last data cycle wi 2174:Src/main.c **** LL_SPI_TransmitData16(SPI2, DATA);//Transmit word to Laser1 DAC 2175:Src/main.c **** tmp32 = 0; 2176:Src/main.c **** while((!LL_SPI_IsActiveFlag_RXNE(SPI2))&&(tmp32<=500)) {tmp32++;}//When trans. last data cycle w 2177:Src/main.c **** (void) SPI2->DR; 2178:Src/main.c **** break; 2179:Src/main.c **** case 4: ARM GAS /tmp/ccqopZd5.s page 91 2180:Src/main.c **** HAL_GPIO_WritePin(DAC_TEC2_CS_GPIO_Port, DAC_TEC2_CS_Pin, GPIO_PIN_RESET);//Start operation with 2181:Src/main.c **** //tmp32=0; 2182:Src/main.c **** //while(tmp32<500){tmp32++;} 2183:Src/main.c **** tmp32 = 0; 2184:Src/main.c **** while((!LL_SPI_IsActiveFlag_TXE(SPI6))&&(tmp32<=500)) {tmp32++;}//When trans. last data cycle wi 2185:Src/main.c **** LL_SPI_TransmitData16(SPI6, DATA);//Transmit word to Laser1 DAC 2186:Src/main.c **** tmp32 = 0; 2187:Src/main.c **** while((!LL_SPI_IsActiveFlag_RXNE(SPI6))&&(tmp32<=500)) {tmp32++;}//When trans. last data cycle w 2188:Src/main.c **** (void) SPI6->DR; 2189:Src/main.c **** break; 2190:Src/main.c **** } 2191:Src/main.c **** HAL_GPIO_WritePin(DAC_LD1_CS_GPIO_Port, DAC_LD1_CS_Pin, GPIO_PIN_SET);//End operation with LDAC1 2192:Src/main.c **** HAL_GPIO_WritePin(DAC_LD2_CS_GPIO_Port, DAC_LD2_CS_Pin, GPIO_PIN_SET);//End operation with LDAC2 2193:Src/main.c **** HAL_GPIO_WritePin(DAC_TEC1_CS_GPIO_Port, DAC_TEC1_CS_Pin, GPIO_PIN_SET);//End operation with TEC1 2194:Src/main.c **** HAL_GPIO_WritePin(DAC_TEC2_CS_GPIO_Port, DAC_TEC2_CS_Pin, GPIO_PIN_SET);//End operation with TEC2 2195:Src/main.c **** } 2196:Src/main.c **** static uint16_t MPhD_T(uint8_t num) 2197:Src/main.c **** { 2198:Src/main.c **** uint16_t P; 2199:Src/main.c **** uint32_t tmp32; 2200:Src/main.c **** HAL_GPIO_WritePin(SPI4_CNV_GPIO_Port, SPI4_CNV_Pin, GPIO_PIN_RESET);//Prepare conversion 2201:Src/main.c **** HAL_GPIO_WritePin(SPI5_CNV_GPIO_Port, SPI5_CNV_Pin, GPIO_PIN_RESET);//Prepare conversion 2202:Src/main.c **** tmp32=0; 2203:Src/main.c **** while(tmp32<500){tmp32++;} 2204:Src/main.c **** HAL_GPIO_WritePin(SPI4_CNV_GPIO_Port, SPI4_CNV_Pin, GPIO_PIN_SET);//Stop acqusition & start conver 2205:Src/main.c **** HAL_GPIO_WritePin(SPI5_CNV_GPIO_Port, SPI5_CNV_Pin, GPIO_PIN_SET);//Stop acqusition & start conver 2206:Src/main.c **** tmp32=0; 2207:Src/main.c **** while(tmp32<500){tmp32++;} 2208:Src/main.c **** if (num==1)//MPD1 2209:Src/main.c **** { 2210:Src/main.c **** HAL_GPIO_WritePin(ADC_ThrLD1_CS_GPIO_Port, ADC_ThrLD1_CS_Pin, GPIO_PIN_SET); 2211:Src/main.c **** HAL_GPIO_WritePin(ADC_MPD1_CS_GPIO_Port, ADC_MPD1_CS_Pin, GPIO_PIN_RESET); 2212:Src/main.c **** tmp32=0; 2213:Src/main.c **** while(tmp32<500){tmp32++;} 2214:Src/main.c **** //LL_SPI_TransmitData16(SPI4, 0xFFFF);//We must to clock the CLK output for collect RX data. We c 2215:Src/main.c **** LL_SPI_Enable(SPI4);//Enable SPI for MPhD1 ADC 2216:Src/main.c **** tmp32 = 0; 2217:Src/main.c **** while(((!LL_SPI_IsActiveFlag_RXNE(SPI4))&&(tmp32<=1000))) {tmp32++;}//When rec. last data cycle w 2218:Src/main.c **** LL_SPI_Disable(SPI4);//Enable SPI for MPhD1 ADC 2219:Src/main.c **** while(tmp32<500){tmp32++;} 2220:Src/main.c **** //HAL_SPI_Receive(&hspi4, &P[0], 1, 100); 2221:Src/main.c **** HAL_GPIO_WritePin(ADC_MPD1_CS_GPIO_Port, ADC_MPD1_CS_Pin, GPIO_PIN_SET); 2222:Src/main.c **** P = LL_SPI_ReceiveData16(SPI4); 2223:Src/main.c **** } 2224:Src/main.c **** else if (num==2)//MPD2 2225:Src/main.c **** { 2226:Src/main.c **** HAL_GPIO_WritePin(ADC_ThrLD2_CS_GPIO_Port, ADC_ThrLD2_CS_Pin, GPIO_PIN_SET); 2227:Src/main.c **** HAL_GPIO_WritePin(ADC_MPD2_CS_GPIO_Port, ADC_MPD2_CS_Pin, GPIO_PIN_RESET); 2228:Src/main.c **** tmp32=0; 2229:Src/main.c **** while(tmp32<500){tmp32++;} 2230:Src/main.c **** //LL_SPI_TransmitData16(SPI5, 0xFFFF);//We must to clock the CLK output for collect RX data. We c 2231:Src/main.c **** LL_SPI_Enable(SPI5);//Enable SPI for MPhD2 ADC 2232:Src/main.c **** tmp32 = 0; 2233:Src/main.c **** while(((!LL_SPI_IsActiveFlag_RXNE(SPI5))&&(tmp32<=1000))) {tmp32++;}//When rec. last data cycle w 2234:Src/main.c **** LL_SPI_Disable(SPI5);//Enable SPI for MPhD2 ADC 2235:Src/main.c **** while(tmp32<500){tmp32++;} 2236:Src/main.c **** //HAL_SPI_Receive(&hspi4, &P[0], 1, 100); ARM GAS /tmp/ccqopZd5.s page 92 2237:Src/main.c **** HAL_GPIO_WritePin(ADC_MPD2_CS_GPIO_Port, ADC_MPD2_CS_Pin, GPIO_PIN_SET); 2238:Src/main.c **** P = LL_SPI_ReceiveData16(SPI5); 2239:Src/main.c **** } 2240:Src/main.c **** else if (num==3)//ThrLD1 2241:Src/main.c **** { 2242:Src/main.c **** HAL_GPIO_WritePin(ADC_MPD1_CS_GPIO_Port, ADC_MPD1_CS_Pin, GPIO_PIN_SET); 2243:Src/main.c **** HAL_GPIO_WritePin(ADC_ThrLD1_CS_GPIO_Port, ADC_ThrLD1_CS_Pin, GPIO_PIN_RESET); 2244:Src/main.c **** tmp32=0; 2245:Src/main.c **** while(tmp32<500){tmp32++;} 2246:Src/main.c **** //LL_SPI_TransmitData16(SPI4, 0xFFFF);//We must to clock the CLK output for collect RX data. We c 2247:Src/main.c **** LL_SPI_Enable(SPI4);//Enable SPI for ThrLD1 ADC 2248:Src/main.c **** tmp32 = 0; 2249:Src/main.c **** while(((!LL_SPI_IsActiveFlag_RXNE(SPI4))&&(tmp32<=1000))) {tmp32++;}//When rec. last data cycle w 2250:Src/main.c **** LL_SPI_Disable(SPI4);//Enable SPI for ThrLD1 ADC 2251:Src/main.c **** while(tmp32<500){tmp32++;} 2252:Src/main.c **** //HAL_SPI_Receive(&hspi4, &P[0], 1, 100); 2253:Src/main.c **** HAL_GPIO_WritePin(ADC_ThrLD1_CS_GPIO_Port, ADC_ThrLD1_CS_Pin, GPIO_PIN_SET); 2254:Src/main.c **** P = LL_SPI_ReceiveData16(SPI4); 2255:Src/main.c **** } 2256:Src/main.c **** else if (num==4)//ThrLD2 2257:Src/main.c **** { 2258:Src/main.c **** HAL_GPIO_WritePin(ADC_MPD2_CS_GPIO_Port, ADC_MPD2_CS_Pin, GPIO_PIN_SET); 2259:Src/main.c **** HAL_GPIO_WritePin(ADC_ThrLD2_CS_GPIO_Port, ADC_ThrLD2_CS_Pin, GPIO_PIN_RESET); 2260:Src/main.c **** tmp32=0; 2261:Src/main.c **** while(tmp32<500){tmp32++;} 2262:Src/main.c **** //LL_SPI_TransmitData16(SPI5, 0xFFFF);//We must to clock the CLK output for collect RX data. We c 2263:Src/main.c **** LL_SPI_Enable(SPI5);//Enable SPI for ThrLD2 ADC 2264:Src/main.c **** tmp32 = 0; 2265:Src/main.c **** while(((!LL_SPI_IsActiveFlag_RXNE(SPI5))&&(tmp32<=1000))) {tmp32++;}//When rec. last data cycle w 2266:Src/main.c **** LL_SPI_Disable(SPI5);//Enable SPI for ThrLD2 ADC 2267:Src/main.c **** while(tmp32<500){tmp32++;} 2268:Src/main.c **** //HAL_SPI_Receive(&hspi4, &P[0], 1, 100); 2269:Src/main.c **** HAL_GPIO_WritePin(ADC_ThrLD2_CS_GPIO_Port, ADC_ThrLD2_CS_Pin, GPIO_PIN_SET); 2270:Src/main.c **** P = LL_SPI_ReceiveData16(SPI5); 2271:Src/main.c **** } 2272:Src/main.c **** /*float I_LD, Ith, I0m, T0m, Inorm, Tnorm1, Tnorm2, P, T_C, A, Pnorm; 2273:Src/main.c **** 2274:Src/main.c **** Inorm = (float) (65535) / (float) (100); 2275:Src/main.c **** Tnorm1 = (float) (65535) / (float) (50); 2276:Src/main.c **** Tnorm2 = 4; 2277:Src/main.c **** Pnorm = (float)(65535) / (float)(20); 2278:Src/main.c **** I0m = 8.1568;//@4 C - lowest temperature of system 2279:Src/main.c **** T0m = 48.6282; 2280:Src/main.c **** T_C = (float) (T_LD) / Tnorm1 + Tnorm2; 2281:Src/main.c **** 2282:Src/main.c **** Ith = I0m * expf(T_C/T0m); 2283:Src/main.c **** I_LD = (float) (C_LD) / Inorm; 2284:Src/main.c **** 2285:Src/main.c **** if (I_LD > Ith) 2286:Src/main.c **** { 2287:Src/main.c **** A = (float) (2.24276128270098e-07) * T_C * T_C * T_C - (float) (4.73392579025590e-05) * T_C * T_ 2288:Src/main.c **** P = A * (I_LD - Ith) * Pnorm; 2289:Src/main.c **** } 2290:Src/main.c **** else 2291:Src/main.c **** { 2292:Src/main.c **** P = 0; 2293:Src/main.c **** } */ ARM GAS /tmp/ccqopZd5.s page 93 2294:Src/main.c **** return P; 2295:Src/main.c **** } 2296:Src/main.c **** /*static uint16_t Temp_LD(uint16_t T_LD_before, uint16_t T_LD, uint32_t Timer_before, uint32_t Time 2297:Src/main.c **** { 2298:Src/main.c **** uint16_t Result; 2299:Src/main.c **** // uint8_t randf; 2300:Src/main.c **** 2301:Src/main.c **** randf = 0; 2302:Src/main.c **** for (uint8_t i = 0; i < 32; i++) 2303:Src/main.c **** { 2304:Src/main.c **** randf = ((Timer>>i)&0x0001)^randf; 2305:Src/main.c **** } 2306:Src/main.c **** 2307:Src/main.c **** Result = ((float)(T_LD - T_LD_before))*((float)(1-expf(((float)(Timer_before)-(float)(Timer))/((fl 2308:Src/main.c **** 2309:Src/main.c **** return (uint16_t)(Result); 2310:Src/main.c **** }*/ 2311:Src/main.c **** static uint16_t Get_ADC(uint8_t num) 2312:Src/main.c **** { 2313:Src/main.c **** uint16_t OUT; 2314:Src/main.c **** switch (num) 2315:Src/main.c **** { 2316:Src/main.c **** case 0: 2317:Src/main.c **** HAL_ADC_Start(&hadc1); // Power on 2318:Src/main.c **** break; 2319:Src/main.c **** case 1: 2320:Src/main.c **** HAL_ADC_PollForConversion(&hadc1, 100); // Waiting for conversion 2321:Src/main.c **** OUT = HAL_ADC_GetValue(&hadc1); // Get value adc 2322:Src/main.c **** break; 2323:Src/main.c **** case 2: 2324:Src/main.c **** HAL_ADC_Stop(&hadc1); // Power off 2325:Src/main.c **** break; 2326:Src/main.c **** case 3: 2327:Src/main.c **** HAL_ADC_Start(&hadc3); // Power on 2328:Src/main.c **** break; 2329:Src/main.c **** case 4: 2330:Src/main.c **** HAL_ADC_PollForConversion(&hadc3, 100); // Waiting for conversion 2331:Src/main.c **** OUT = HAL_ADC_GetValue(&hadc3); // Get value adc 2332:Src/main.c **** break; 2333:Src/main.c **** case 5: 2334:Src/main.c **** HAL_ADC_Stop(&hadc3); // Power off 2335:Src/main.c **** break; 2336:Src/main.c **** } 2337:Src/main.c **** return OUT; 2338:Src/main.c **** } 2339:Src/main.c **** 2340:Src/main.c **** uint16_t Advanced_Controller_Temp(LDx_SetupTypeDef * LDx_curr_setup, LDx_ParamTypeDef * LDx_results 2341:Src/main.c **** { 2342:Src/main.c **** // Main idea: 2343:Src/main.c **** // I is responsible to maintaining constant temperature difference between laser and room temperat 2344:Src/main.c **** // As room temperature can be approximated as constant at current-varying time -- I should be kept 2345:Src/main.c **** // As current through laser diode heats it -- we can estimate excessive power on laser diode and t 2346:Src/main.c **** // So, equation should be look like this: 2347:Src/main.c **** // x_output = x_output_original + I(laser)*(a + (t - b)c) 2348:Src/main.c **** // t -- cycle phase 2349:Src/main.c **** // a,b,c -- constants 2350:Src/main.c **** // ARM GAS /tmp/ccqopZd5.s page 94 2351:Src/main.c **** // How can we control laser diode temperature? 2352:Src/main.c **** // -- We can set laser to fixed current at the time we need to measure. 2353:Src/main.c **** // Then we should measure wavelength. 2354:Src/main.c **** // Calibration sequence: 2355:Src/main.c **** // 1) n 2356:Src/main.c **** 2357:Src/main.c **** 2358:Src/main.c **** 2359:Src/main.c **** int e_pid; 2360:Src/main.c **** float P_coef_current;//, I_coef_current; 2361:Src/main.c **** float e_integral; 2362:Src/main.c **** int x_output; 2363:Src/main.c **** 2364:Src/main.c **** e_pid = (int) LDx_results->LD_CURR_TEMP - (int) LDx_curr_setup->LD_TEMP; 2365:Src/main.c **** 2366:Src/main.c **** e_integral = LDx_results->e_integral; 2367:Src/main.c **** 2368:Src/main.c **** if((e_pid < 3000) && (e_pid > - 3000)){ 2369:Src/main.c **** e_integral += LDx_curr_setup->I_coef_temp * (float)(e_pid) * (float)(TO7 - TO7_PID) / (float) 100 2370:Src/main.c **** } 2371:Src/main.c **** P_coef_current = LDx_curr_setup->P_coef_temp; 2372:Src/main.c **** 2373:Src/main.c **** if (e_integral > 32000){ 2374:Src/main.c **** e_integral = 32000; 2375:Src/main.c **** } 2376:Src/main.c **** else if (e_integral < - 32000){ 2377:Src/main.c **** e_integral = -32000; 2378:Src/main.c **** } 2379:Src/main.c **** LDx_results->e_integral = e_integral; 2380:Src/main.c **** 2381:Src/main.c **** x_output = 32768 + P_coef_current * e_pid + (int)e_integral;//32768 - P_coef_current * e_pid - (in 2382:Src/main.c **** 2383:Src/main.c **** if(x_output < 1000){ 2384:Src/main.c **** x_output = 8800; 2385:Src/main.c **** } 2386:Src/main.c **** else if(x_output > 56800){ 2387:Src/main.c **** x_output = 56800; 2388:Src/main.c **** } 2389:Src/main.c **** 2390:Src/main.c **** if (num==2) 2391:Src/main.c **** TO7_PID = TO7;//Save current time only on 2nd laser 2392:Src/main.c **** 2393:Src/main.c **** return (uint16_t)x_output; 2394:Src/main.c **** } 2395:Src/main.c **** 2396:Src/main.c **** 2397:Src/main.c **** uint16_t PID_Controller_Temp(LDx_SetupTypeDef * LDx_curr_setup, LDx_ParamTypeDef * LDx_results, uin 2398:Src/main.c **** { 546 .loc 2 2398 1 is_stmt 1 view -0 547 .cfi_startproc 548 @ args = 0, pretend = 0, frame = 0 549 @ frame_needed = 0, uses_anonymous_args = 0 550 @ link register save eliminated. 551 .loc 2 2398 1 is_stmt 0 view .LVU201 552 0000 30B4 push {r4, r5} 553 .LCFI5: 554 .cfi_def_cfa_offset 8 ARM GAS /tmp/ccqopZd5.s page 95 555 .cfi_offset 4, -8 556 .cfi_offset 5, -4 2399:Src/main.c **** int e_pid; 557 .loc 2 2399 2 is_stmt 1 view .LVU202 2400:Src/main.c **** float P_coef_current;//, I_coef_current; 558 .loc 2 2400 2 view .LVU203 2401:Src/main.c **** float e_integral; 559 .loc 2 2401 2 view .LVU204 2402:Src/main.c **** int x_output; 560 .loc 2 2402 2 view .LVU205 2403:Src/main.c **** 2404:Src/main.c **** e_pid = (int) LDx_results->LD_CURR_TEMP - (int) LDx_curr_setup->LD_TEMP; 561 .loc 2 2404 2 view .LVU206 562 .loc 2 2404 28 is_stmt 0 view .LVU207 563 0002 0B88 ldrh r3, [r1] 564 .loc 2 2404 65 view .LVU208 565 0004 0488 ldrh r4, [r0] 566 .loc 2 2404 8 view .LVU209 567 0006 1B1B subs r3, r3, r4 568 .LVL34: 2405:Src/main.c **** 2406:Src/main.c **** e_integral = LDx_results->e_integral; 569 .loc 2 2406 2 is_stmt 1 view .LVU210 570 .loc 2 2406 13 is_stmt 0 view .LVU211 571 0008 D1ED017A vldr.32 s15, [r1, #4] 572 .LVL35: 2407:Src/main.c **** 2408:Src/main.c **** if((e_pid < 3000) && (e_pid > - 3000)){ 573 .loc 2 2408 2 is_stmt 1 view .LVU212 574 .loc 2 2408 20 is_stmt 0 view .LVU213 575 000c 03F6B73C addw ip, r3, #2999 576 .loc 2 2408 4 view .LVU214 577 0010 41F26E74 movw r4, #5998 578 0014 A445 cmp ip, r4 579 0016 18D8 bhi .L16 2409:Src/main.c **** e_integral += LDx_curr_setup->I_coef_temp * (float)(e_pid) * (float)(TO7 - TO7_PID) / (float) 100 580 .loc 2 2409 3 is_stmt 1 view .LVU215 581 .loc 2 2409 31 is_stmt 0 view .LVU216 582 0018 90ED027A vldr.32 s14, [r0, #8] 583 .loc 2 2409 47 view .LVU217 584 001c 06EE903A vmov s13, r3 @ int 585 0020 F8EEE66A vcvt.f32.s32 s13, s13 586 .loc 2 2409 45 view .LVU218 587 0024 67EE266A vmul.f32 s13, s14, s13 588 .loc 2 2409 76 view .LVU219 589 0028 284C ldr r4, .L26 590 002a 2468 ldr r4, [r4] 591 002c 284D ldr r5, .L26+4 592 002e 2D68 ldr r5, [r5] 593 0030 641B subs r4, r4, r5 594 0032 07EE104A vmov s14, r4 @ int 595 .loc 2 2409 64 view .LVU220 596 0036 B8EE477A vcvt.f32.u32 s14, s14 597 .loc 2 2409 62 view .LVU221 598 003a 26EE877A vmul.f32 s14, s13, s14 599 .loc 2 2409 87 view .LVU222 600 003e 9FED256A vldr.32 s12, .L26+8 ARM GAS /tmp/ccqopZd5.s page 96 601 0042 C7EE066A vdiv.f32 s13, s14, s12 602 .loc 2 2409 14 view .LVU223 603 0046 77EEA67A vadd.f32 s15, s15, s13 604 .LVL36: 605 .L16: 2410:Src/main.c **** } 2411:Src/main.c **** P_coef_current = LDx_curr_setup->P_coef_temp; 606 .loc 2 2411 2 is_stmt 1 view .LVU224 607 .loc 2 2411 17 is_stmt 0 view .LVU225 608 004a D0ED016A vldr.32 s13, [r0, #4] 609 .LVL37: 2412:Src/main.c **** 2413:Src/main.c **** if (e_integral > 32000){ 610 .loc 2 2413 2 is_stmt 1 view .LVU226 611 .loc 2 2413 5 is_stmt 0 view .LVU227 612 004e 9FED227A vldr.32 s14, .L26+12 613 0052 F4EEC77A vcmpe.f32 s15, s14 614 0056 F1EE10FA vmrs APSR_nzcv, FPSCR 615 005a 09DC bgt .L20 2414:Src/main.c **** e_integral = 32000; 2415:Src/main.c **** } 2416:Src/main.c **** else if (e_integral < - 32000){ 616 .loc 2 2416 7 is_stmt 1 view .LVU228 617 .loc 2 2416 10 is_stmt 0 view .LVU229 618 005c 9FED1F7A vldr.32 s14, .L26+16 619 0060 F4EEC77A vcmpe.f32 s15, s14 620 0064 F1EE10FA vmrs APSR_nzcv, FPSCR 621 0068 04D5 bpl .L17 2417:Src/main.c **** e_integral = -32000; 622 .loc 2 2417 15 view .LVU230 623 006a DFED1C7A vldr.32 s15, .L26+16 624 .LVL38: 625 .loc 2 2417 15 view .LVU231 626 006e 01E0 b .L17 627 .LVL39: 628 .L20: 2414:Src/main.c **** e_integral = 32000; 629 .loc 2 2414 15 view .LVU232 630 0070 DFED197A vldr.32 s15, .L26+12 631 .LVL40: 632 .L17: 2418:Src/main.c **** } 2419:Src/main.c **** LDx_results->e_integral = e_integral; 633 .loc 2 2419 2 is_stmt 1 view .LVU233 634 .loc 2 2419 26 is_stmt 0 view .LVU234 635 0074 C1ED017A vstr.32 s15, [r1, #4] 2420:Src/main.c **** 2421:Src/main.c **** x_output = 32768 + P_coef_current * e_pid + (int)e_integral;//32768 - P_coef_current * e_pid - (in 636 .loc 2 2421 2 is_stmt 1 view .LVU235 637 .loc 2 2421 36 is_stmt 0 view .LVU236 638 0078 07EE103A vmov s14, r3 @ int 639 007c B8EEC77A vcvt.f32.s32 s14, s14 640 0080 27EE267A vmul.f32 s14, s14, s13 641 .loc 2 2421 19 view .LVU237 642 0084 DFED166A vldr.32 s13, .L26+20 643 .LVL41: 644 .loc 2 2421 19 view .LVU238 ARM GAS /tmp/ccqopZd5.s page 97 645 0088 37EE267A vadd.f32 s14, s14, s13 646 .loc 2 2421 46 view .LVU239 647 008c FDEEE77A vcvt.s32.f32 s15, s15 648 .LVL42: 649 .loc 2 2421 44 view .LVU240 650 0090 F8EEE77A vcvt.f32.s32 s15, s15 651 0094 77EE877A vadd.f32 s15, s15, s14 652 .loc 2 2421 11 view .LVU241 653 0098 FDEEE77A vcvt.s32.f32 s15, s15 654 009c 17EE900A vmov r0, s15 @ int 655 .LVL43: 2422:Src/main.c **** 2423:Src/main.c **** if(x_output < 1000){ 656 .loc 2 2423 2 is_stmt 1 view .LVU242 657 .loc 2 2423 4 is_stmt 0 view .LVU243 658 00a0 B0F57A7F cmp r0, #1000 659 00a4 06DB blt .L22 2424:Src/main.c **** x_output = 8800; 2425:Src/main.c **** } 2426:Src/main.c **** else if(x_output > 56800){ 660 .loc 2 2426 7 is_stmt 1 view .LVU244 661 .loc 2 2426 9 is_stmt 0 view .LVU245 662 00a6 4DF6E053 movw r3, #56800 663 .LVL44: 664 .loc 2 2426 9 view .LVU246 665 00aa 9842 cmp r0, r3 666 00ac 04DD ble .L18 2427:Src/main.c **** x_output = 56800; 667 .loc 2 2427 12 view .LVU247 668 00ae 4DF6E050 movw r0, #56800 669 .LVL45: 670 .loc 2 2427 12 view .LVU248 671 00b2 01E0 b .L18 672 .LVL46: 673 .L22: 2424:Src/main.c **** x_output = 8800; 674 .loc 2 2424 12 view .LVU249 675 00b4 42F26020 movw r0, #8800 676 .LVL47: 677 .L18: 2428:Src/main.c **** } 2429:Src/main.c **** 2430:Src/main.c **** if (num==2) 678 .loc 2 2430 2 is_stmt 1 view .LVU250 679 .loc 2 2430 5 is_stmt 0 view .LVU251 680 00b8 022A cmp r2, #2 681 00ba 02D0 beq .L25 682 .LVL48: 683 .L19: 2431:Src/main.c **** TO7_PID = TO7;//Save current time only on 2nd laser 2432:Src/main.c **** 2433:Src/main.c **** return (uint16_t)x_output; 684 .loc 2 2433 2 is_stmt 1 view .LVU252 2434:Src/main.c **** } 685 .loc 2 2434 1 is_stmt 0 view .LVU253 686 00bc 80B2 uxth r0, r0 687 .LVL49: ARM GAS /tmp/ccqopZd5.s page 98 688 .loc 2 2434 1 view .LVU254 689 00be 30BC pop {r4, r5} 690 .LCFI6: 691 .cfi_remember_state 692 .cfi_restore 5 693 .cfi_restore 4 694 .cfi_def_cfa_offset 0 695 00c0 7047 bx lr 696 .LVL50: 697 .L25: 698 .LCFI7: 699 .cfi_restore_state 2431:Src/main.c **** TO7_PID = TO7;//Save current time only on 2nd laser 700 .loc 2 2431 3 is_stmt 1 view .LVU255 2431:Src/main.c **** TO7_PID = TO7;//Save current time only on 2nd laser 701 .loc 2 2431 11 is_stmt 0 view .LVU256 702 00c2 024B ldr r3, .L26 703 00c4 1A68 ldr r2, [r3] 704 .LVL51: 2431:Src/main.c **** TO7_PID = TO7;//Save current time only on 2nd laser 705 .loc 2 2431 11 view .LVU257 706 00c6 024B ldr r3, .L26+4 707 00c8 1A60 str r2, [r3] 708 00ca F7E7 b .L19 709 .L27: 710 .align 2 711 .L26: 712 00cc 00000000 .word .LANCHOR3 713 00d0 00000000 .word .LANCHOR4 714 00d4 0000C842 .word 1120403456 715 00d8 0000FA46 .word 1190789120 716 00dc 0000FAC6 .word -956694528 717 00e0 00000047 .word 1191182336 718 .cfi_endproc 719 .LFE1214: 721 .section .text.OUT_trigger,"ax",%progbits 722 .align 1 723 .syntax unified 724 .thumb 725 .thumb_func 726 .fpu fpv5-d16 728 OUT_trigger: 729 .LVL52: 730 .LFB1209: 2084:Src/main.c **** switch (out_n) 731 .loc 2 2084 1 is_stmt 1 view -0 732 .cfi_startproc 733 @ args = 0, pretend = 0, frame = 0 734 @ frame_needed = 0, uses_anonymous_args = 0 2084:Src/main.c **** switch (out_n) 735 .loc 2 2084 1 is_stmt 0 view .LVU259 736 0000 10B5 push {r4, lr} 737 .LCFI8: 738 .cfi_def_cfa_offset 8 739 .cfi_offset 4, -8 740 .cfi_offset 14, -4 2085:Src/main.c **** { ARM GAS /tmp/ccqopZd5.s page 99 741 .loc 2 2085 2 is_stmt 1 view .LVU260 742 0002 0928 cmp r0, #9 743 0004 13D8 bhi .L28 744 0006 DFE800F0 tbb [pc, r0] 745 .L31: 746 000a 05 .byte (.L40-.L31)/2 747 000b 13 .byte (.L39-.L31)/2 748 000c 21 .byte (.L38-.L31)/2 749 000d 2F .byte (.L37-.L31)/2 750 000e 3D .byte (.L36-.L31)/2 751 000f 4B .byte (.L35-.L31)/2 752 0010 59 .byte (.L34-.L31)/2 753 0011 65 .byte (.L33-.L31)/2 754 0012 71 .byte (.L32-.L31)/2 755 0013 7D .byte (.L30-.L31)/2 756 .p2align 1 757 .L40: 2088:Src/main.c **** HAL_GPIO_WritePin(OUT_0_GPIO_Port, OUT_0_Pin, GPIO_PIN_RESET); 758 .loc 2 2088 3 view .LVU261 759 0014 414C ldr r4, .L42 760 0016 0122 movs r2, #1 761 0018 4FF48061 mov r1, #1024 762 001c 2046 mov r0, r4 763 .LVL53: 2088:Src/main.c **** HAL_GPIO_WritePin(OUT_0_GPIO_Port, OUT_0_Pin, GPIO_PIN_RESET); 764 .loc 2 2088 3 is_stmt 0 view .LVU262 765 001e FFF7FEFF bl HAL_GPIO_WritePin 766 .LVL54: 2089:Src/main.c **** break; 767 .loc 2 2089 3 is_stmt 1 view .LVU263 768 0022 0022 movs r2, #0 769 0024 4FF48061 mov r1, #1024 770 0028 2046 mov r0, r4 771 002a FFF7FEFF bl HAL_GPIO_WritePin 772 .LVL55: 2090:Src/main.c **** 773 .loc 2 2090 2 view .LVU264 774 .L28: 2137:Src/main.c **** 775 .loc 2 2137 1 is_stmt 0 view .LVU265 776 002e 10BD pop {r4, pc} 777 .LVL56: 778 .L39: 2093:Src/main.c **** HAL_GPIO_WritePin(OUT_1_GPIO_Port, OUT_1_Pin, GPIO_PIN_RESET); 779 .loc 2 2093 3 is_stmt 1 view .LVU266 780 0030 3A4C ldr r4, .L42 781 0032 0122 movs r2, #1 782 0034 4FF40061 mov r1, #2048 783 0038 2046 mov r0, r4 784 .LVL57: 2093:Src/main.c **** HAL_GPIO_WritePin(OUT_1_GPIO_Port, OUT_1_Pin, GPIO_PIN_RESET); 785 .loc 2 2093 3 is_stmt 0 view .LVU267 786 003a FFF7FEFF bl HAL_GPIO_WritePin 787 .LVL58: 2094:Src/main.c **** break; 788 .loc 2 2094 3 is_stmt 1 view .LVU268 789 003e 0022 movs r2, #0 ARM GAS /tmp/ccqopZd5.s page 100 790 0040 4FF40061 mov r1, #2048 791 0044 2046 mov r0, r4 792 0046 FFF7FEFF bl HAL_GPIO_WritePin 793 .LVL59: 2095:Src/main.c **** 794 .loc 2 2095 2 view .LVU269 795 004a F0E7 b .L28 796 .LVL60: 797 .L38: 2098:Src/main.c **** HAL_GPIO_WritePin(OUT_2_GPIO_Port, OUT_2_Pin, GPIO_PIN_RESET); 798 .loc 2 2098 3 view .LVU270 799 004c 334C ldr r4, .L42 800 004e 0122 movs r2, #1 801 0050 4FF48051 mov r1, #4096 802 0054 2046 mov r0, r4 803 .LVL61: 2098:Src/main.c **** HAL_GPIO_WritePin(OUT_2_GPIO_Port, OUT_2_Pin, GPIO_PIN_RESET); 804 .loc 2 2098 3 is_stmt 0 view .LVU271 805 0056 FFF7FEFF bl HAL_GPIO_WritePin 806 .LVL62: 2099:Src/main.c **** break; 807 .loc 2 2099 3 is_stmt 1 view .LVU272 808 005a 0022 movs r2, #0 809 005c 4FF48051 mov r1, #4096 810 0060 2046 mov r0, r4 811 0062 FFF7FEFF bl HAL_GPIO_WritePin 812 .LVL63: 2100:Src/main.c **** 813 .loc 2 2100 2 view .LVU273 814 0066 E2E7 b .L28 815 .LVL64: 816 .L37: 2103:Src/main.c **** HAL_GPIO_WritePin(OUT_3_GPIO_Port, OUT_3_Pin, GPIO_PIN_RESET); 817 .loc 2 2103 3 view .LVU274 818 0068 2C4C ldr r4, .L42 819 006a 0122 movs r2, #1 820 006c 4FF40051 mov r1, #8192 821 0070 2046 mov r0, r4 822 .LVL65: 2103:Src/main.c **** HAL_GPIO_WritePin(OUT_3_GPIO_Port, OUT_3_Pin, GPIO_PIN_RESET); 823 .loc 2 2103 3 is_stmt 0 view .LVU275 824 0072 FFF7FEFF bl HAL_GPIO_WritePin 825 .LVL66: 2104:Src/main.c **** break; 826 .loc 2 2104 3 is_stmt 1 view .LVU276 827 0076 0022 movs r2, #0 828 0078 4FF40051 mov r1, #8192 829 007c 2046 mov r0, r4 830 007e FFF7FEFF bl HAL_GPIO_WritePin 831 .LVL67: 2105:Src/main.c **** 832 .loc 2 2105 2 view .LVU277 833 0082 D4E7 b .L28 834 .LVL68: 835 .L36: 2108:Src/main.c **** HAL_GPIO_WritePin(OUT_4_GPIO_Port, OUT_4_Pin, GPIO_PIN_RESET); 836 .loc 2 2108 3 view .LVU278 ARM GAS /tmp/ccqopZd5.s page 101 837 0084 254C ldr r4, .L42 838 0086 0122 movs r2, #1 839 0088 4FF48041 mov r1, #16384 840 008c 2046 mov r0, r4 841 .LVL69: 2108:Src/main.c **** HAL_GPIO_WritePin(OUT_4_GPIO_Port, OUT_4_Pin, GPIO_PIN_RESET); 842 .loc 2 2108 3 is_stmt 0 view .LVU279 843 008e FFF7FEFF bl HAL_GPIO_WritePin 844 .LVL70: 2109:Src/main.c **** break; 845 .loc 2 2109 3 is_stmt 1 view .LVU280 846 0092 0022 movs r2, #0 847 0094 4FF48041 mov r1, #16384 848 0098 2046 mov r0, r4 849 009a FFF7FEFF bl HAL_GPIO_WritePin 850 .LVL71: 2110:Src/main.c **** 851 .loc 2 2110 2 view .LVU281 852 009e C6E7 b .L28 853 .LVL72: 854 .L35: 2113:Src/main.c **** HAL_GPIO_WritePin(OUT_5_GPIO_Port, OUT_5_Pin, GPIO_PIN_RESET); 855 .loc 2 2113 3 view .LVU282 856 00a0 1E4C ldr r4, .L42 857 00a2 0122 movs r2, #1 858 00a4 4FF40041 mov r1, #32768 859 00a8 2046 mov r0, r4 860 .LVL73: 2113:Src/main.c **** HAL_GPIO_WritePin(OUT_5_GPIO_Port, OUT_5_Pin, GPIO_PIN_RESET); 861 .loc 2 2113 3 is_stmt 0 view .LVU283 862 00aa FFF7FEFF bl HAL_GPIO_WritePin 863 .LVL74: 2114:Src/main.c **** break; 864 .loc 2 2114 3 is_stmt 1 view .LVU284 865 00ae 0022 movs r2, #0 866 00b0 4FF40041 mov r1, #32768 867 00b4 2046 mov r0, r4 868 00b6 FFF7FEFF bl HAL_GPIO_WritePin 869 .LVL75: 2115:Src/main.c **** 870 .loc 2 2115 2 view .LVU285 871 00ba B8E7 b .L28 872 .LVL76: 873 .L34: 2118:Src/main.c **** HAL_GPIO_WritePin(OUT_6_GPIO_Port, OUT_6_Pin, GPIO_PIN_RESET); 874 .loc 2 2118 3 view .LVU286 875 00bc 184C ldr r4, .L42+4 876 00be 0122 movs r2, #1 877 00c0 1021 movs r1, #16 878 00c2 2046 mov r0, r4 879 .LVL77: 2118:Src/main.c **** HAL_GPIO_WritePin(OUT_6_GPIO_Port, OUT_6_Pin, GPIO_PIN_RESET); 880 .loc 2 2118 3 is_stmt 0 view .LVU287 881 00c4 FFF7FEFF bl HAL_GPIO_WritePin 882 .LVL78: 2119:Src/main.c **** break; 883 .loc 2 2119 3 is_stmt 1 view .LVU288 ARM GAS /tmp/ccqopZd5.s page 102 884 00c8 0022 movs r2, #0 885 00ca 1021 movs r1, #16 886 00cc 2046 mov r0, r4 887 00ce FFF7FEFF bl HAL_GPIO_WritePin 888 .LVL79: 2120:Src/main.c **** 889 .loc 2 2120 2 view .LVU289 890 00d2 ACE7 b .L28 891 .LVL80: 892 .L33: 2123:Src/main.c **** HAL_GPIO_WritePin(OUT_7_GPIO_Port, OUT_7_Pin, GPIO_PIN_RESET); 893 .loc 2 2123 3 view .LVU290 894 00d4 124C ldr r4, .L42+4 895 00d6 0122 movs r2, #1 896 00d8 2021 movs r1, #32 897 00da 2046 mov r0, r4 898 .LVL81: 2123:Src/main.c **** HAL_GPIO_WritePin(OUT_7_GPIO_Port, OUT_7_Pin, GPIO_PIN_RESET); 899 .loc 2 2123 3 is_stmt 0 view .LVU291 900 00dc FFF7FEFF bl HAL_GPIO_WritePin 901 .LVL82: 2124:Src/main.c **** break; 902 .loc 2 2124 3 is_stmt 1 view .LVU292 903 00e0 0022 movs r2, #0 904 00e2 2021 movs r1, #32 905 00e4 2046 mov r0, r4 906 00e6 FFF7FEFF bl HAL_GPIO_WritePin 907 .LVL83: 2125:Src/main.c **** 908 .loc 2 2125 2 view .LVU293 909 00ea A0E7 b .L28 910 .LVL84: 911 .L32: 2128:Src/main.c **** HAL_GPIO_WritePin(OUT_8_GPIO_Port, OUT_8_Pin, GPIO_PIN_RESET); 912 .loc 2 2128 3 view .LVU294 913 00ec 0C4C ldr r4, .L42+4 914 00ee 0122 movs r2, #1 915 00f0 4021 movs r1, #64 916 00f2 2046 mov r0, r4 917 .LVL85: 2128:Src/main.c **** HAL_GPIO_WritePin(OUT_8_GPIO_Port, OUT_8_Pin, GPIO_PIN_RESET); 918 .loc 2 2128 3 is_stmt 0 view .LVU295 919 00f4 FFF7FEFF bl HAL_GPIO_WritePin 920 .LVL86: 2129:Src/main.c **** break; 921 .loc 2 2129 3 is_stmt 1 view .LVU296 922 00f8 0022 movs r2, #0 923 00fa 4021 movs r1, #64 924 00fc 2046 mov r0, r4 925 00fe FFF7FEFF bl HAL_GPIO_WritePin 926 .LVL87: 2130:Src/main.c **** 927 .loc 2 2130 2 view .LVU297 928 0102 94E7 b .L28 929 .LVL88: 930 .L30: 2133:Src/main.c **** HAL_GPIO_WritePin(OUT_9_GPIO_Port, OUT_9_Pin, GPIO_PIN_RESET); ARM GAS /tmp/ccqopZd5.s page 103 931 .loc 2 2133 3 view .LVU298 932 0104 064C ldr r4, .L42+4 933 0106 0122 movs r2, #1 934 0108 8021 movs r1, #128 935 010a 2046 mov r0, r4 936 .LVL89: 2133:Src/main.c **** HAL_GPIO_WritePin(OUT_9_GPIO_Port, OUT_9_Pin, GPIO_PIN_RESET); 937 .loc 2 2133 3 is_stmt 0 view .LVU299 938 010c FFF7FEFF bl HAL_GPIO_WritePin 939 .LVL90: 2134:Src/main.c **** break; 940 .loc 2 2134 3 is_stmt 1 view .LVU300 941 0110 0022 movs r2, #0 942 0112 8021 movs r1, #128 943 0114 2046 mov r0, r4 944 0116 FFF7FEFF bl HAL_GPIO_WritePin 945 .LVL91: 2135:Src/main.c **** } 946 .loc 2 2135 2 view .LVU301 2137:Src/main.c **** 947 .loc 2 2137 1 is_stmt 0 view .LVU302 948 011a 88E7 b .L28 949 .L43: 950 .align 2 951 .L42: 952 011c 00180240 .word 1073879040 953 0120 00040240 .word 1073873920 954 .cfi_endproc 955 .LFE1209: 957 .section .text.MPhD_T,"ax",%progbits 958 .align 1 959 .syntax unified 960 .thumb 961 .thumb_func 962 .fpu fpv5-d16 964 MPhD_T: 965 .LVL92: 966 .LFB1211: 2197:Src/main.c **** uint16_t P; 967 .loc 2 2197 1 is_stmt 1 view -0 968 .cfi_startproc 969 @ args = 0, pretend = 0, frame = 0 970 @ frame_needed = 0, uses_anonymous_args = 0 2197:Src/main.c **** uint16_t P; 971 .loc 2 2197 1 is_stmt 0 view .LVU304 972 0000 38B5 push {r3, r4, r5, lr} 973 .LCFI9: 974 .cfi_def_cfa_offset 16 975 .cfi_offset 3, -16 976 .cfi_offset 4, -12 977 .cfi_offset 5, -8 978 .cfi_offset 14, -4 979 0002 0446 mov r4, r0 2198:Src/main.c **** uint32_t tmp32; 980 .loc 2 2198 2 is_stmt 1 view .LVU305 2199:Src/main.c **** HAL_GPIO_WritePin(SPI4_CNV_GPIO_Port, SPI4_CNV_Pin, GPIO_PIN_RESET);//Prepare conversion 981 .loc 2 2199 2 view .LVU306 ARM GAS /tmp/ccqopZd5.s page 104 2200:Src/main.c **** HAL_GPIO_WritePin(SPI5_CNV_GPIO_Port, SPI5_CNV_Pin, GPIO_PIN_RESET);//Prepare conversion 982 .loc 2 2200 2 view .LVU307 983 0004 0022 movs r2, #0 984 0006 4FF48041 mov r1, #16384 985 000a 8248 ldr r0, .L88 986 .LVL93: 2200:Src/main.c **** HAL_GPIO_WritePin(SPI5_CNV_GPIO_Port, SPI5_CNV_Pin, GPIO_PIN_RESET);//Prepare conversion 987 .loc 2 2200 2 is_stmt 0 view .LVU308 988 000c FFF7FEFF bl HAL_GPIO_WritePin 989 .LVL94: 2201:Src/main.c **** tmp32=0; 990 .loc 2 2201 2 is_stmt 1 view .LVU309 991 0010 0022 movs r2, #0 992 0012 4FF40071 mov r1, #512 993 0016 8048 ldr r0, .L88+4 994 0018 FFF7FEFF bl HAL_GPIO_WritePin 995 .LVL95: 2202:Src/main.c **** while(tmp32<500){tmp32++;} 996 .loc 2 2202 2 view .LVU310 2203:Src/main.c **** HAL_GPIO_WritePin(SPI4_CNV_GPIO_Port, SPI4_CNV_Pin, GPIO_PIN_SET);//Stop acqusition & start conver 997 .loc 2 2203 2 view .LVU311 2202:Src/main.c **** while(tmp32<500){tmp32++;} 998 .loc 2 2202 7 is_stmt 0 view .LVU312 999 001c 0023 movs r3, #0 2203:Src/main.c **** HAL_GPIO_WritePin(SPI4_CNV_GPIO_Port, SPI4_CNV_Pin, GPIO_PIN_SET);//Stop acqusition & start conver 1000 .loc 2 2203 7 view .LVU313 1001 001e 00E0 b .L45 1002 .LVL96: 1003 .L46: 2203:Src/main.c **** HAL_GPIO_WritePin(SPI4_CNV_GPIO_Port, SPI4_CNV_Pin, GPIO_PIN_SET);//Stop acqusition & start conver 1004 .loc 2 2203 19 is_stmt 1 discriminator 2 view .LVU314 2203:Src/main.c **** HAL_GPIO_WritePin(SPI4_CNV_GPIO_Port, SPI4_CNV_Pin, GPIO_PIN_SET);//Stop acqusition & start conver 1005 .loc 2 2203 24 is_stmt 0 discriminator 2 view .LVU315 1006 0020 0133 adds r3, r3, #1 1007 .LVL97: 1008 .L45: 2203:Src/main.c **** HAL_GPIO_WritePin(SPI4_CNV_GPIO_Port, SPI4_CNV_Pin, GPIO_PIN_SET);//Stop acqusition & start conver 1009 .loc 2 2203 7 is_stmt 1 discriminator 1 view .LVU316 1010 0022 B3F5FA7F cmp r3, #500 1011 0026 FBD3 bcc .L46 2204:Src/main.c **** HAL_GPIO_WritePin(SPI5_CNV_GPIO_Port, SPI5_CNV_Pin, GPIO_PIN_SET);//Stop acqusition & start conver 1012 .loc 2 2204 2 view .LVU317 1013 0028 0122 movs r2, #1 1014 002a 4FF48041 mov r1, #16384 1015 002e 7948 ldr r0, .L88 1016 0030 FFF7FEFF bl HAL_GPIO_WritePin 1017 .LVL98: 2205:Src/main.c **** tmp32=0; 1018 .loc 2 2205 2 view .LVU318 1019 0034 0122 movs r2, #1 1020 0036 4FF40071 mov r1, #512 1021 003a 7748 ldr r0, .L88+4 1022 003c FFF7FEFF bl HAL_GPIO_WritePin 1023 .LVL99: 2206:Src/main.c **** while(tmp32<500){tmp32++;} 1024 .loc 2 2206 2 view .LVU319 2207:Src/main.c **** if (num==1)//MPD1 ARM GAS /tmp/ccqopZd5.s page 105 1025 .loc 2 2207 2 view .LVU320 2206:Src/main.c **** while(tmp32<500){tmp32++;} 1026 .loc 2 2206 7 is_stmt 0 view .LVU321 1027 0040 0023 movs r3, #0 2207:Src/main.c **** if (num==1)//MPD1 1028 .loc 2 2207 7 view .LVU322 1029 0042 00E0 b .L47 1030 .LVL100: 1031 .L48: 2207:Src/main.c **** if (num==1)//MPD1 1032 .loc 2 2207 19 is_stmt 1 discriminator 2 view .LVU323 2207:Src/main.c **** if (num==1)//MPD1 1033 .loc 2 2207 24 is_stmt 0 discriminator 2 view .LVU324 1034 0044 0133 adds r3, r3, #1 1035 .LVL101: 1036 .L47: 2207:Src/main.c **** if (num==1)//MPD1 1037 .loc 2 2207 7 is_stmt 1 discriminator 1 view .LVU325 1038 0046 B3F5FA7F cmp r3, #500 1039 004a FBD3 bcc .L48 2208:Src/main.c **** { 1040 .loc 2 2208 2 view .LVU326 2208:Src/main.c **** { 1041 .loc 2 2208 5 is_stmt 0 view .LVU327 1042 004c 012C cmp r4, #1 1043 004e 08D0 beq .L82 2224:Src/main.c **** { 1044 .loc 2 2224 7 is_stmt 1 view .LVU328 2224:Src/main.c **** { 1045 .loc 2 2224 10 is_stmt 0 view .LVU329 1046 0050 022C cmp r4, #2 1047 0052 3DD0 beq .L83 2240:Src/main.c **** { 1048 .loc 2 2240 7 is_stmt 1 view .LVU330 2240:Src/main.c **** { 1049 .loc 2 2240 10 is_stmt 0 view .LVU331 1050 0054 032C cmp r4, #3 1051 0056 70D0 beq .L84 2256:Src/main.c **** { 1052 .loc 2 2256 7 is_stmt 1 view .LVU332 2256:Src/main.c **** { 1053 .loc 2 2256 10 is_stmt 0 view .LVU333 1054 0058 042C cmp r4, #4 1055 005a 00F0A580 beq .L85 1056 .LVL102: 1057 .L57: 2294:Src/main.c **** } 1058 .loc 2 2294 2 is_stmt 1 view .LVU334 2295:Src/main.c **** /*static uint16_t Temp_LD(uint16_t T_LD_before, uint16_t T_LD, uint32_t Timer_before, uint32_t Time 1059 .loc 2 2295 1 is_stmt 0 view .LVU335 1060 005e 2846 mov r0, r5 1061 0060 38BD pop {r3, r4, r5, pc} 1062 .LVL103: 1063 .L82: 2210:Src/main.c **** HAL_GPIO_WritePin(ADC_MPD1_CS_GPIO_Port, ADC_MPD1_CS_Pin, GPIO_PIN_RESET); 1064 .loc 2 2210 3 is_stmt 1 view .LVU336 1065 0062 6C4C ldr r4, .L88 ARM GAS /tmp/ccqopZd5.s page 106 1066 0064 0122 movs r2, #1 1067 0066 4FF40061 mov r1, #2048 1068 006a 2046 mov r0, r4 1069 006c FFF7FEFF bl HAL_GPIO_WritePin 1070 .LVL104: 2211:Src/main.c **** tmp32=0; 1071 .loc 2 2211 3 view .LVU337 1072 0070 0022 movs r2, #0 1073 0072 4FF48061 mov r1, #1024 1074 0076 2046 mov r0, r4 1075 0078 FFF7FEFF bl HAL_GPIO_WritePin 1076 .LVL105: 2212:Src/main.c **** while(tmp32<500){tmp32++;} 1077 .loc 2 2212 3 view .LVU338 2213:Src/main.c **** //LL_SPI_TransmitData16(SPI4, 0xFFFF);//We must to clock the CLK output for collect RX data. We c 1078 .loc 2 2213 3 view .LVU339 2212:Src/main.c **** while(tmp32<500){tmp32++;} 1079 .loc 2 2212 8 is_stmt 0 view .LVU340 1080 007c 0023 movs r3, #0 2213:Src/main.c **** //LL_SPI_TransmitData16(SPI4, 0xFFFF);//We must to clock the CLK output for collect RX data. We c 1081 .loc 2 2213 8 view .LVU341 1082 007e 00E0 b .L50 1083 .LVL106: 1084 .L51: 2213:Src/main.c **** //LL_SPI_TransmitData16(SPI4, 0xFFFF);//We must to clock the CLK output for collect RX data. We c 1085 .loc 2 2213 20 is_stmt 1 discriminator 2 view .LVU342 2213:Src/main.c **** //LL_SPI_TransmitData16(SPI4, 0xFFFF);//We must to clock the CLK output for collect RX data. We c 1086 .loc 2 2213 25 is_stmt 0 discriminator 2 view .LVU343 1087 0080 0133 adds r3, r3, #1 1088 .LVL107: 1089 .L50: 2213:Src/main.c **** //LL_SPI_TransmitData16(SPI4, 0xFFFF);//We must to clock the CLK output for collect RX data. We c 1090 .loc 2 2213 8 is_stmt 1 discriminator 1 view .LVU344 1091 0082 B3F5FA7F cmp r3, #500 1092 0086 FBD3 bcc .L51 2215:Src/main.c **** tmp32 = 0; 1093 .loc 2 2215 3 view .LVU345 1094 .LVL108: 1095 .LBB302: 1096 .LBI302: 1097 .file 4 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h" 1:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 2:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** ****************************************************************************** 3:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @file stm32f7xx_ll_spi.h 4:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @author MCD Application Team 5:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Header file of SPI LL module. 6:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** ****************************************************************************** 7:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @attention 8:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * 9:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * Copyright (c) 2017 STMicroelectronics. 10:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * All rights reserved. 11:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * 12:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * This software is licensed under terms that can be found in the LICENSE file 13:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * in the root directory of this software component. 14:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * If no LICENSE file comes with this software, it is provided AS-IS. 15:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * 16:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** ****************************************************************************** ARM GAS /tmp/ccqopZd5.s page 107 17:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 18:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 19:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /* Define to prevent recursive inclusion -------------------------------------*/ 20:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #ifndef STM32F7xx_LL_SPI_H 21:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define STM32F7xx_LL_SPI_H 22:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 23:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #ifdef __cplusplus 24:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** extern "C" { 25:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #endif 26:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 27:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /* Includes ------------------------------------------------------------------*/ 28:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #include "stm32f7xx.h" 29:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 30:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @addtogroup STM32F7xx_LL_Driver 31:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @{ 32:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 33:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 34:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #if defined (SPI1) || defined (SPI2) || defined (SPI3) || defined (SPI4) || defined (SPI5) || defin 35:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 36:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL SPI 37:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @{ 38:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 39:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 40:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /* Private types -------------------------------------------------------------*/ 41:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /* Private variables ---------------------------------------------------------*/ 42:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /* Private macros ------------------------------------------------------------*/ 43:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 44:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /* Exported types ------------------------------------------------------------*/ 45:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #if defined(USE_FULL_LL_DRIVER) 46:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_ES_INIT SPI Exported Init structure 47:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @{ 48:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 49:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 50:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 51:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief SPI Init structures definition 52:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 53:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** typedef struct 54:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 55:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** uint32_t TransferDirection; /*!< Specifies the SPI unidirectional or bidirectional data mod 56:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** This parameter can be a value of @ref SPI_LL_EC_TRANSFER_M 57:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 58:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** This feature can be modified afterwards using unitary func 59:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 60:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** uint32_t Mode; /*!< Specifies the SPI mode (Master/Slave). 61:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** This parameter can be a value of @ref SPI_LL_EC_MODE. 62:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 63:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** This feature can be modified afterwards using unitary func 64:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 65:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** uint32_t DataWidth; /*!< Specifies the SPI data width. 66:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** This parameter can be a value of @ref SPI_LL_EC_DATAWIDTH. 67:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 68:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** This feature can be modified afterwards using unitary func 69:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 70:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** uint32_t ClockPolarity; /*!< Specifies the serial clock steady state. 71:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** This parameter can be a value of @ref SPI_LL_EC_POLARITY. 72:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 73:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** This feature can be modified afterwards using unitary func ARM GAS /tmp/ccqopZd5.s page 108 74:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 75:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** uint32_t ClockPhase; /*!< Specifies the clock active edge for the bit capture. 76:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** This parameter can be a value of @ref SPI_LL_EC_PHASE. 77:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 78:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** This feature can be modified afterwards using unitary func 79:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 80:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** uint32_t NSS; /*!< Specifies whether the NSS signal is managed by hardware (N 81:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** This parameter can be a value of @ref SPI_LL_EC_NSS_MODE. 82:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 83:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** This feature can be modified afterwards using unitary func 84:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 85:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** uint32_t BaudRate; /*!< Specifies the BaudRate prescaler value which will be used 86:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** This parameter can be a value of @ref SPI_LL_EC_BAUDRATEPR 87:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** @note The communication clock is derived from the master c 88:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 89:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** This feature can be modified afterwards using unitary func 90:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 91:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** uint32_t BitOrder; /*!< Specifies whether data transfers start from MSB or LSB bit 92:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** This parameter can be a value of @ref SPI_LL_EC_BIT_ORDER. 93:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 94:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** This feature can be modified afterwards using unitary func 95:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 96:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** uint32_t CRCCalculation; /*!< Specifies if the CRC calculation is enabled or not. 97:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** This parameter can be a value of @ref SPI_LL_EC_CRC_CALCUL 98:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 99:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** This feature can be modified afterwards using unitary func 100:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 101:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** uint32_t CRCPoly; /*!< Specifies the polynomial used for the CRC calculation. 102:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** This parameter must be a number between Min_Data = 0x00 an 103:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 104:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** This feature can be modified afterwards using unitary func 105:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 106:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } LL_SPI_InitTypeDef; 107:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 108:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 109:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @} 110:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 111:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #endif /* USE_FULL_LL_DRIVER */ 112:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 113:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /* Exported constants --------------------------------------------------------*/ 114:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_Exported_Constants SPI Exported Constants 115:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @{ 116:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 117:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 118:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_EC_GET_FLAG Get Flags Defines 119:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Flags defines which can be used with LL_SPI_ReadReg function 120:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @{ 121:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 122:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_SR_RXNE SPI_SR_RXNE /*!< Rx buffer not empty flag 123:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_SR_TXE SPI_SR_TXE /*!< Tx buffer empty flag 124:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_SR_BSY SPI_SR_BSY /*!< Busy flag 125:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_SR_CRCERR SPI_SR_CRCERR /*!< CRC error flag 126:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_SR_MODF SPI_SR_MODF /*!< Mode fault flag 127:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_SR_OVR SPI_SR_OVR /*!< Overrun flag 128:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_SR_FRE SPI_SR_FRE /*!< TI mode frame format erro 129:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 130:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @} ARM GAS /tmp/ccqopZd5.s page 109 131:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 132:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 133:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_EC_IT IT Defines 134:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief IT defines which can be used with LL_SPI_ReadReg and LL_SPI_WriteReg functions 135:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @{ 136:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 137:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_CR2_RXNEIE SPI_CR2_RXNEIE /*!< Rx buffer not empty inter 138:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_CR2_TXEIE SPI_CR2_TXEIE /*!< Tx buffer empty interrupt 139:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_CR2_ERRIE SPI_CR2_ERRIE /*!< Error interrupt enable 140:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 141:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @} 142:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 143:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 144:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_EC_MODE Operation Mode 145:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @{ 146:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 147:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_MODE_MASTER (SPI_CR1_MSTR | SPI_CR1_SSI) /*!< Master configuratio 148:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_MODE_SLAVE 0x00000000U /*!< Slave configuration 149:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 150:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @} 151:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 152:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 153:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_EC_PROTOCOL Serial Protocol 154:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @{ 155:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 156:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_PROTOCOL_MOTOROLA 0x00000000U /*!< Motorola mode. Used as de 157:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_PROTOCOL_TI (SPI_CR2_FRF) /*!< TI mode 158:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 159:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @} 160:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 161:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 162:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_EC_PHASE Clock Phase 163:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @{ 164:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 165:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_PHASE_1EDGE 0x00000000U /*!< First clock transition is 166:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_PHASE_2EDGE (SPI_CR1_CPHA) /*!< Second clock transition i 167:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 168:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @} 169:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 170:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 171:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_EC_POLARITY Clock Polarity 172:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @{ 173:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 174:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_POLARITY_LOW 0x00000000U /*!< Clock to 0 when idle */ 175:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_POLARITY_HIGH (SPI_CR1_CPOL) /*!< Clock to 1 when idle */ 176:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 177:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @} 178:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 179:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 180:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_EC_BAUDRATEPRESCALER Baud Rate Prescaler 181:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @{ 182:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 183:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_BAUDRATEPRESCALER_DIV2 0x00000000U /*!< Baud 184:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_BAUDRATEPRESCALER_DIV4 (SPI_CR1_BR_0) /*!< Baud 185:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_BAUDRATEPRESCALER_DIV8 (SPI_CR1_BR_1) /*!< Baud 186:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_BAUDRATEPRESCALER_DIV16 (SPI_CR1_BR_1 | SPI_CR1_BR_0) /*!< Baud 187:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_BAUDRATEPRESCALER_DIV32 (SPI_CR1_BR_2) /*!< Baud ARM GAS /tmp/ccqopZd5.s page 110 188:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_BAUDRATEPRESCALER_DIV64 (SPI_CR1_BR_2 | SPI_CR1_BR_0) /*!< Baud 189:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_BAUDRATEPRESCALER_DIV128 (SPI_CR1_BR_2 | SPI_CR1_BR_1) /*!< Baud 190:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_BAUDRATEPRESCALER_DIV256 (SPI_CR1_BR_2 | SPI_CR1_BR_1 | SPI_CR1_BR_0) /*!< Baud 191:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 192:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @} 193:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 194:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 195:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_EC_BIT_ORDER Transmission Bit Order 196:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @{ 197:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 198:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_LSB_FIRST (SPI_CR1_LSBFIRST) /*!< Data is transmitted/recei 199:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_MSB_FIRST 0x00000000U /*!< Data is transmitted/recei 200:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 201:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @} 202:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 203:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 204:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_EC_TRANSFER_MODE Transfer Mode 205:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @{ 206:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 207:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_FULL_DUPLEX 0x00000000U /*!< Full-Duplex mo 208:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_SIMPLEX_RX (SPI_CR1_RXONLY) /*!< Simplex Rx mod 209:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_HALF_DUPLEX_RX (SPI_CR1_BIDIMODE) /*!< Half-Duplex Rx 210:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_HALF_DUPLEX_TX (SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE) /*!< Half-Duplex Tx 211:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 212:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @} 213:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 214:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 215:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_EC_NSS_MODE Slave Select Pin Mode 216:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @{ 217:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 218:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_NSS_SOFT (SPI_CR1_SSM) /*!< NSS managed inter 219:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_NSS_HARD_INPUT 0x00000000U /*!< NSS pin used in I 220:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_NSS_HARD_OUTPUT (((uint32_t)SPI_CR2_SSOE << 16U)) /*!< NSS pin used in O 221:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 222:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @} 223:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 224:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 225:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_EC_DATAWIDTH Datawidth 226:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @{ 227:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 228:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_DATAWIDTH_4BIT (SPI_CR2_DS_0 | SPI_CR2_DS_1) 229:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_DATAWIDTH_5BIT (SPI_CR2_DS_2) 230:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_DATAWIDTH_6BIT (SPI_CR2_DS_2 | SPI_CR2_DS_0) 231:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_DATAWIDTH_7BIT (SPI_CR2_DS_2 | SPI_CR2_DS_1) 232:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_DATAWIDTH_8BIT (SPI_CR2_DS_2 | SPI_CR2_DS_1 | SPI_CR2_DS_0) 233:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_DATAWIDTH_9BIT (SPI_CR2_DS_3) 234:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_DATAWIDTH_10BIT (SPI_CR2_DS_3 | SPI_CR2_DS_0) 235:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_DATAWIDTH_11BIT (SPI_CR2_DS_3 | SPI_CR2_DS_1) 236:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_DATAWIDTH_12BIT (SPI_CR2_DS_3 | SPI_CR2_DS_1 | SPI_CR2_DS_0) 237:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_DATAWIDTH_13BIT (SPI_CR2_DS_3 | SPI_CR2_DS_2) 238:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_DATAWIDTH_14BIT (SPI_CR2_DS_3 | SPI_CR2_DS_2 | SPI_CR2_DS_0) 239:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_DATAWIDTH_15BIT (SPI_CR2_DS_3 | SPI_CR2_DS_2 | SPI_CR2_DS_1) 240:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_DATAWIDTH_16BIT (SPI_CR2_DS_3 | SPI_CR2_DS_2 | SPI_CR2_DS_1 | SPI_CR2_DS 241:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 242:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @} 243:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 244:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #if defined(USE_FULL_LL_DRIVER) ARM GAS /tmp/ccqopZd5.s page 111 245:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 246:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_EC_CRC_CALCULATION CRC Calculation 247:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @{ 248:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 249:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_CRCCALCULATION_DISABLE 0x00000000U /*!< CRC calculation disabled 250:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_CRCCALCULATION_ENABLE (SPI_CR1_CRCEN) /*!< CRC calculation enabled 251:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 252:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @} 253:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 254:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #endif /* USE_FULL_LL_DRIVER */ 255:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 256:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_EC_CRC_LENGTH CRC Length 257:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @{ 258:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 259:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_CRC_8BIT 0x00000000U /*!< 8-bit CRC length */ 260:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_CRC_16BIT (SPI_CR1_CRCL) /*!< 16-bit CRC length */ 261:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 262:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @} 263:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 264:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 265:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_EC_RX_FIFO_TH RX FIFO Threshold 266:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @{ 267:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 268:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_RX_FIFO_TH_HALF 0x00000000U /*!< RXNE event is generated i 269:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_RX_FIFO_TH_QUARTER (SPI_CR2_FRXTH) /*!< RXNE event is generated i 270:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 271:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @} 272:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 273:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 274:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_EC_RX_FIFO RX FIFO Level 275:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @{ 276:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 277:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_RX_FIFO_EMPTY 0x00000000U /*!< FIFO reception em 278:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_RX_FIFO_QUARTER_FULL (SPI_SR_FRLVL_0) /*!< FIFO reception 1/ 279:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_RX_FIFO_HALF_FULL (SPI_SR_FRLVL_1) /*!< FIFO reception 1/ 280:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_RX_FIFO_FULL (SPI_SR_FRLVL_1 | SPI_SR_FRLVL_0) /*!< FIFO reception fu 281:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 282:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @} 283:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 284:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 285:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_EC_TX_FIFO TX FIFO Level 286:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @{ 287:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 288:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_TX_FIFO_EMPTY 0x00000000U /*!< FIFO transmission 289:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_TX_FIFO_QUARTER_FULL (SPI_SR_FTLVL_0) /*!< FIFO transmission 290:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_TX_FIFO_HALF_FULL (SPI_SR_FTLVL_1) /*!< FIFO transmission 291:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_TX_FIFO_FULL (SPI_SR_FTLVL_1 | SPI_SR_FTLVL_0) /*!< FIFO transmission 292:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 293:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @} 294:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 295:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 296:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_EC_DMA_PARITY DMA Parity 297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @{ 298:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 299:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_DMA_PARITY_EVEN 0x00000000U /*!< Select DMA parity Even */ 300:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_DMA_PARITY_ODD 0x00000001U /*!< Select DMA parity Odd */ 301:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** ARM GAS /tmp/ccqopZd5.s page 112 302:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 303:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @} 304:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 305:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 306:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 307:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @} 308:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 309:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 310:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /* Exported macro ------------------------------------------------------------*/ 311:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_Exported_Macros SPI Exported Macros 312:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @{ 313:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_EM_WRITE_READ Common Write and read registers Macros 316:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @{ 317:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 318:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 319:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 320:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Write a value in SPI register 321:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param __INSTANCE__ SPI Instance 322:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param __REG__ Register to be written 323:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param __VALUE__ Value to be written in the register 324:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None 325:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 326:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE 327:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 328:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 329:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Read a value in SPI register 330:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param __INSTANCE__ SPI Instance 331:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param __REG__ Register to be read 332:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval Register value 333:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 334:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) 335:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 336:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @} 337:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 338:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 339:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 340:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @} 341:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 342:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 343:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /* Exported functions --------------------------------------------------------*/ 344:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_Exported_Functions SPI Exported Functions 345:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @{ 346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 347:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 348:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_EF_Configuration Configuration 349:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @{ 350:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 351:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 352:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 353:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Enable SPI peripheral 354:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR1 SPE LL_SPI_Enable 355:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 356:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None 357:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 358:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_Enable(SPI_TypeDef *SPIx) ARM GAS /tmp/ccqopZd5.s page 113 1098 .loc 4 358 22 view .LVU346 1099 .LBB303: 359:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** SET_BIT(SPIx->CR1, SPI_CR1_SPE); 1100 .loc 4 360 3 view .LVU347 1101 0088 644A ldr r2, .L88+8 1102 008a 1368 ldr r3, [r2] 1103 .LVL109: 1104 .loc 4 360 3 is_stmt 0 view .LVU348 1105 008c 43F04003 orr r3, r3, #64 1106 0090 1360 str r3, [r2] 1107 .LVL110: 1108 .loc 4 360 3 view .LVU349 1109 .LBE303: 1110 .LBE302: 2216:Src/main.c **** while(((!LL_SPI_IsActiveFlag_RXNE(SPI4))&&(tmp32<=1000))) {tmp32++;}//When rec. last data cycle w 1111 .loc 2 2216 3 is_stmt 1 view .LVU350 2217:Src/main.c **** LL_SPI_Disable(SPI4);//Enable SPI for MPhD1 ADC 1112 .loc 2 2217 3 view .LVU351 2216:Src/main.c **** while(((!LL_SPI_IsActiveFlag_RXNE(SPI4))&&(tmp32<=1000))) {tmp32++;}//When rec. last data cycle w 1113 .loc 2 2216 9 is_stmt 0 view .LVU352 1114 0092 0023 movs r3, #0 1115 .LVL111: 1116 .L52: 2217:Src/main.c **** LL_SPI_Disable(SPI4);//Enable SPI for MPhD1 ADC 1117 .loc 2 2217 8 is_stmt 1 discriminator 1 view .LVU353 1118 .LBB304: 1119 .LBI304: 361:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 362:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 363:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 364:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Disable SPI peripheral 365:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @note When disabling the SPI, follow the procedure described in the Reference Manual. 366:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR1 SPE LL_SPI_Disable 367:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 368:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None 369:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_Disable(SPI_TypeDef *SPIx) 371:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE); 373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 374:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 375:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 376:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Check if SPI peripheral is enabled 377:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR1 SPE LL_SPI_IsEnabled 378:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 379:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval State of bit (1 or 0). 380:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 381:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_IsEnabled(SPI_TypeDef *SPIx) 382:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 383:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** return ((READ_BIT(SPIx->CR1, SPI_CR1_SPE) == (SPI_CR1_SPE)) ? 1UL : 0UL); 384:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 385:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 386:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 387:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Set SPI operation mode to Master or Slave 388:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @note This bit should not be changed when communication is ongoing. 389:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR1 MSTR LL_SPI_SetMode\n ARM GAS /tmp/ccqopZd5.s page 114 390:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * CR1 SSI LL_SPI_SetMode 391:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 392:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param Mode This parameter can be one of the following values: 393:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_MODE_MASTER 394:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_MODE_SLAVE 395:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None 396:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 397:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_SetMode(SPI_TypeDef *SPIx, uint32_t Mode) 398:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 399:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** MODIFY_REG(SPIx->CR1, SPI_CR1_MSTR | SPI_CR1_SSI, Mode); 400:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 401:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 402:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 403:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Get SPI operation mode (Master or Slave) 404:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR1 MSTR LL_SPI_GetMode\n 405:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * CR1 SSI LL_SPI_GetMode 406:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 407:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval Returned value can be one of the following values: 408:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_MODE_MASTER 409:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_MODE_SLAVE 410:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 411:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_GetMode(SPI_TypeDef *SPIx) 412:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 413:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_MSTR | SPI_CR1_SSI)); 414:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 415:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 416:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 417:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Set serial protocol used 418:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation. 419:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR2 FRF LL_SPI_SetStandard 420:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 421:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param Standard This parameter can be one of the following values: 422:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_PROTOCOL_MOTOROLA 423:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_PROTOCOL_TI 424:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None 425:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 426:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_SetStandard(SPI_TypeDef *SPIx, uint32_t Standard) 427:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** MODIFY_REG(SPIx->CR2, SPI_CR2_FRF, Standard); 429:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 430:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 431:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 432:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Get serial protocol used 433:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR2 FRF LL_SPI_GetStandard 434:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 435:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval Returned value can be one of the following values: 436:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_PROTOCOL_MOTOROLA 437:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_PROTOCOL_TI 438:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 439:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_GetStandard(SPI_TypeDef *SPIx) 440:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 441:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_FRF)); 442:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 443:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 444:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 445:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Set clock phase 446:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @note This bit should not be changed when communication is ongoing. ARM GAS /tmp/ccqopZd5.s page 115 447:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * This bit is not used in SPI TI mode. 448:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR1 CPHA LL_SPI_SetClockPhase 449:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 450:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param ClockPhase This parameter can be one of the following values: 451:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_PHASE_1EDGE 452:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_PHASE_2EDGE 453:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None 454:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 455:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_SetClockPhase(SPI_TypeDef *SPIx, uint32_t ClockPhase) 456:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 457:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** MODIFY_REG(SPIx->CR1, SPI_CR1_CPHA, ClockPhase); 458:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 459:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 460:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 461:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Get clock phase 462:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR1 CPHA LL_SPI_GetClockPhase 463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 464:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval Returned value can be one of the following values: 465:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_PHASE_1EDGE 466:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_PHASE_2EDGE 467:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 468:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_GetClockPhase(SPI_TypeDef *SPIx) 469:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 470:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPHA)); 471:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 472:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 473:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 474:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Set clock polarity 475:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @note This bit should not be changed when communication is ongoing. 476:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * This bit is not used in SPI TI mode. 477:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR1 CPOL LL_SPI_SetClockPolarity 478:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 479:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param ClockPolarity This parameter can be one of the following values: 480:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_POLARITY_LOW 481:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_POLARITY_HIGH 482:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None 483:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 484:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPolarity) 485:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 486:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** MODIFY_REG(SPIx->CR1, SPI_CR1_CPOL, ClockPolarity); 487:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 488:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 489:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 490:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Get clock polarity 491:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR1 CPOL LL_SPI_GetClockPolarity 492:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 493:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval Returned value can be one of the following values: 494:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_POLARITY_LOW 495:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_POLARITY_HIGH 496:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 497:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_GetClockPolarity(SPI_TypeDef *SPIx) 498:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 499:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPOL)); 500:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 501:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 502:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 503:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Set baud rate prescaler ARM GAS /tmp/ccqopZd5.s page 116 504:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @note These bits should not be changed when communication is ongoing. SPI BaudRate = fPCLK/Pr 505:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR1 BR LL_SPI_SetBaudRatePrescaler 506:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 507:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param BaudRate This parameter can be one of the following values: 508:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2 509:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4 510:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8 511:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16 512:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32 513:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64 514:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128 515:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256 516:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None 517:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 518:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_SetBaudRatePrescaler(SPI_TypeDef *SPIx, uint32_t BaudRate) 519:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 520:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** MODIFY_REG(SPIx->CR1, SPI_CR1_BR, BaudRate); 521:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 522:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 523:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 524:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Get baud rate prescaler 525:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR1 BR LL_SPI_GetBaudRatePrescaler 526:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 527:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval Returned value can be one of the following values: 528:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2 529:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4 530:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8 531:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16 532:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32 533:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64 534:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128 535:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256 536:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 537:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_GetBaudRatePrescaler(SPI_TypeDef *SPIx) 538:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 539:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_BR)); 540:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 541:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 542:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 543:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Set transfer bit order 544:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @note This bit should not be changed when communication is ongoing. This bit is not used in S 545:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR1 LSBFIRST LL_SPI_SetTransferBitOrder 546:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 547:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param BitOrder This parameter can be one of the following values: 548:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_LSB_FIRST 549:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_MSB_FIRST 550:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None 551:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 552:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_SetTransferBitOrder(SPI_TypeDef *SPIx, uint32_t BitOrder) 553:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 554:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** MODIFY_REG(SPIx->CR1, SPI_CR1_LSBFIRST, BitOrder); 555:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 556:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 557:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 558:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Get transfer bit order 559:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR1 LSBFIRST LL_SPI_GetTransferBitOrder 560:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance ARM GAS /tmp/ccqopZd5.s page 117 561:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval Returned value can be one of the following values: 562:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_LSB_FIRST 563:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_MSB_FIRST 564:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 565:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_GetTransferBitOrder(SPI_TypeDef *SPIx) 566:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 567:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_LSBFIRST)); 568:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 569:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 570:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 571:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Set transfer direction mode 572:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @note For Half-Duplex mode, Rx Direction is set by default. 573:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * In master mode, the MOSI pin is used and in slave mode, the MISO pin is used for Half-D 574:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR1 RXONLY LL_SPI_SetTransferDirection\n 575:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * CR1 BIDIMODE LL_SPI_SetTransferDirection\n 576:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * CR1 BIDIOE LL_SPI_SetTransferDirection 577:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 578:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param TransferDirection This parameter can be one of the following values: 579:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_FULL_DUPLEX 580:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_SIMPLEX_RX 581:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_HALF_DUPLEX_RX 582:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_HALF_DUPLEX_TX 583:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None 584:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 585:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_SetTransferDirection(SPI_TypeDef *SPIx, uint32_t TransferDirection) 586:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 587:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** MODIFY_REG(SPIx->CR1, SPI_CR1_RXONLY | SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE, TransferDirection); 588:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 589:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 590:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 591:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Get transfer direction mode 592:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR1 RXONLY LL_SPI_GetTransferDirection\n 593:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * CR1 BIDIMODE LL_SPI_GetTransferDirection\n 594:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * CR1 BIDIOE LL_SPI_GetTransferDirection 595:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 596:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval Returned value can be one of the following values: 597:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_FULL_DUPLEX 598:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_SIMPLEX_RX 599:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_HALF_DUPLEX_RX 600:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_HALF_DUPLEX_TX 601:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 602:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_GetTransferDirection(SPI_TypeDef *SPIx) 603:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 604:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_RXONLY | SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE)); 605:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 606:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 607:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 608:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Set frame data width 609:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR2 DS LL_SPI_SetDataWidth 610:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 611:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param DataWidth This parameter can be one of the following values: 612:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_DATAWIDTH_4BIT 613:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_DATAWIDTH_5BIT 614:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_DATAWIDTH_6BIT 615:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_DATAWIDTH_7BIT 616:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_DATAWIDTH_8BIT 617:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_DATAWIDTH_9BIT ARM GAS /tmp/ccqopZd5.s page 118 618:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_DATAWIDTH_10BIT 619:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_DATAWIDTH_11BIT 620:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_DATAWIDTH_12BIT 621:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_DATAWIDTH_13BIT 622:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_DATAWIDTH_14BIT 623:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_DATAWIDTH_15BIT 624:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_DATAWIDTH_16BIT 625:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None 626:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 627:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_SetDataWidth(SPI_TypeDef *SPIx, uint32_t DataWidth) 628:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 629:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** MODIFY_REG(SPIx->CR2, SPI_CR2_DS, DataWidth); 630:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 631:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 632:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 633:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Get frame data width 634:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR2 DS LL_SPI_GetDataWidth 635:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 636:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval Returned value can be one of the following values: 637:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_DATAWIDTH_4BIT 638:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_DATAWIDTH_5BIT 639:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_DATAWIDTH_6BIT 640:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_DATAWIDTH_7BIT 641:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_DATAWIDTH_8BIT 642:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_DATAWIDTH_9BIT 643:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_DATAWIDTH_10BIT 644:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_DATAWIDTH_11BIT 645:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_DATAWIDTH_12BIT 646:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_DATAWIDTH_13BIT 647:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_DATAWIDTH_14BIT 648:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_DATAWIDTH_15BIT 649:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_DATAWIDTH_16BIT 650:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 651:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_GetDataWidth(SPI_TypeDef *SPIx) 652:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 653:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_DS)); 654:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 655:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 656:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 657:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Set threshold of RXFIFO that triggers an RXNE event 658:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR2 FRXTH LL_SPI_SetRxFIFOThreshold 659:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 660:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param Threshold This parameter can be one of the following values: 661:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_RX_FIFO_TH_HALF 662:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_RX_FIFO_TH_QUARTER 663:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None 664:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 665:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_SetRxFIFOThreshold(SPI_TypeDef *SPIx, uint32_t Threshold) 666:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 667:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** MODIFY_REG(SPIx->CR2, SPI_CR2_FRXTH, Threshold); 668:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 669:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 670:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 671:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Get threshold of RXFIFO that triggers an RXNE event 672:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR2 FRXTH LL_SPI_GetRxFIFOThreshold 673:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 674:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval Returned value can be one of the following values: ARM GAS /tmp/ccqopZd5.s page 119 675:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_RX_FIFO_TH_HALF 676:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_RX_FIFO_TH_QUARTER 677:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 678:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_GetRxFIFOThreshold(SPI_TypeDef *SPIx) 679:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 680:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_FRXTH)); 681:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 682:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 683:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 684:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @} 685:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 686:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 687:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_EF_CRC_Management CRC Management 688:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @{ 689:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 690:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 691:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 692:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Enable CRC 693:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation. 694:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR1 CRCEN LL_SPI_EnableCRC 695:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 696:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None 697:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 698:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_EnableCRC(SPI_TypeDef *SPIx) 699:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 700:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** SET_BIT(SPIx->CR1, SPI_CR1_CRCEN); 701:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 702:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 703:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 704:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Disable CRC 705:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation. 706:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR1 CRCEN LL_SPI_DisableCRC 707:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 708:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None 709:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 710:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_DisableCRC(SPI_TypeDef *SPIx) 711:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 712:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** CLEAR_BIT(SPIx->CR1, SPI_CR1_CRCEN); 713:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 714:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 715:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 716:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Check if CRC is enabled 717:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation. 718:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR1 CRCEN LL_SPI_IsEnabledCRC 719:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 720:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval State of bit (1 or 0). 721:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 722:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_IsEnabledCRC(SPI_TypeDef *SPIx) 723:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 724:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** return ((READ_BIT(SPIx->CR1, SPI_CR1_CRCEN) == (SPI_CR1_CRCEN)) ? 1UL : 0UL); 725:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 726:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 727:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 728:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Set CRC Length 729:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation. 730:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR1 CRCL LL_SPI_SetCRCWidth 731:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance ARM GAS /tmp/ccqopZd5.s page 120 732:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param CRCLength This parameter can be one of the following values: 733:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_CRC_8BIT 734:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_CRC_16BIT 735:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None 736:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 737:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_SetCRCWidth(SPI_TypeDef *SPIx, uint32_t CRCLength) 738:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 739:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** MODIFY_REG(SPIx->CR1, SPI_CR1_CRCL, CRCLength); 740:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 741:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 742:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 743:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Get CRC Length 744:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR1 CRCL LL_SPI_GetCRCWidth 745:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 746:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval Returned value can be one of the following values: 747:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_CRC_8BIT 748:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_CRC_16BIT 749:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 750:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_GetCRCWidth(SPI_TypeDef *SPIx) 751:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 752:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CRCL)); 753:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 754:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 755:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 756:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Set CRCNext to transfer CRC on the line 757:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @note This bit has to be written as soon as the last data is written in the SPIx_DR register. 758:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR1 CRCNEXT LL_SPI_SetCRCNext 759:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 760:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None 761:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 762:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_SetCRCNext(SPI_TypeDef *SPIx) 763:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 764:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** SET_BIT(SPIx->CR1, SPI_CR1_CRCNEXT); 765:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 766:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 767:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 768:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Set polynomial for CRC calculation 769:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CRCPR CRCPOLY LL_SPI_SetCRCPolynomial 770:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 771:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param CRCPoly This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFF 772:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None 773:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 774:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_SetCRCPolynomial(SPI_TypeDef *SPIx, uint32_t CRCPoly) 775:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 776:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** WRITE_REG(SPIx->CRCPR, (uint16_t)CRCPoly); 777:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 778:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 779:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 780:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Get polynomial for CRC calculation 781:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CRCPR CRCPOLY LL_SPI_GetCRCPolynomial 782:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 783:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF 784:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 785:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_GetCRCPolynomial(SPI_TypeDef *SPIx) 786:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 787:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** return (uint32_t)(READ_REG(SPIx->CRCPR)); 788:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } ARM GAS /tmp/ccqopZd5.s page 121 789:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 790:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 791:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Get Rx CRC 792:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll RXCRCR RXCRC LL_SPI_GetRxCRC 793:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 794:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF 795:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 796:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_GetRxCRC(SPI_TypeDef *SPIx) 797:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 798:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** return (uint32_t)(READ_REG(SPIx->RXCRCR)); 799:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 800:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 801:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 802:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Get Tx CRC 803:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll TXCRCR TXCRC LL_SPI_GetTxCRC 804:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 805:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF 806:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 807:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_GetTxCRC(SPI_TypeDef *SPIx) 808:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 809:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** return (uint32_t)(READ_REG(SPIx->TXCRCR)); 810:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 811:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 812:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 813:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @} 814:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 815:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 816:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_EF_NSS_Management Slave Select Pin Management 817:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @{ 818:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 819:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 820:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 821:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Set NSS mode 822:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @note LL_SPI_NSS_SOFT Mode is not used in SPI TI mode. 823:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR1 SSM LL_SPI_SetNSSMode\n 824:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR2 SSOE LL_SPI_SetNSSMode 825:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 826:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param NSS This parameter can be one of the following values: 827:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_NSS_SOFT 828:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_NSS_HARD_INPUT 829:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_NSS_HARD_OUTPUT 830:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None 831:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 832:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_SetNSSMode(SPI_TypeDef *SPIx, uint32_t NSS) 833:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 834:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** MODIFY_REG(SPIx->CR1, SPI_CR1_SSM, NSS); 835:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** MODIFY_REG(SPIx->CR2, SPI_CR2_SSOE, ((uint32_t)(NSS >> 16U))); 836:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 837:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 838:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 839:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Get NSS mode 840:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR1 SSM LL_SPI_GetNSSMode\n 841:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR2 SSOE LL_SPI_GetNSSMode 842:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 843:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval Returned value can be one of the following values: 844:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_NSS_SOFT 845:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_NSS_HARD_INPUT ARM GAS /tmp/ccqopZd5.s page 122 846:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_NSS_HARD_OUTPUT 847:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 848:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_GetNSSMode(SPI_TypeDef *SPIx) 849:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 850:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** uint32_t Ssm = (READ_BIT(SPIx->CR1, SPI_CR1_SSM)); 851:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** uint32_t Ssoe = (READ_BIT(SPIx->CR2, SPI_CR2_SSOE) << 16U); 852:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** return (Ssm | Ssoe); 853:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 854:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 855:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 856:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Enable NSS pulse management 857:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @note This bit should not be changed when communication is ongoing. This bit is not used in S 858:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR2 NSSP LL_SPI_EnableNSSPulseMgt 859:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 860:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None 861:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 862:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_EnableNSSPulseMgt(SPI_TypeDef *SPIx) 863:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 864:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** SET_BIT(SPIx->CR2, SPI_CR2_NSSP); 865:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 866:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 867:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 868:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Disable NSS pulse management 869:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @note This bit should not be changed when communication is ongoing. This bit is not used in S 870:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR2 NSSP LL_SPI_DisableNSSPulseMgt 871:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 872:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None 873:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 874:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_DisableNSSPulseMgt(SPI_TypeDef *SPIx) 875:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 876:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** CLEAR_BIT(SPIx->CR2, SPI_CR2_NSSP); 877:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 878:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 879:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 880:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Check if NSS pulse is enabled 881:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @note This bit should not be changed when communication is ongoing. This bit is not used in S 882:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR2 NSSP LL_SPI_IsEnabledNSSPulse 883:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 884:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval State of bit (1 or 0). 885:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 886:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_IsEnabledNSSPulse(SPI_TypeDef *SPIx) 887:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 888:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** return ((READ_BIT(SPIx->CR2, SPI_CR2_NSSP) == (SPI_CR2_NSSP)) ? 1UL : 0UL); 889:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 890:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 891:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 892:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @} 893:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 894:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 895:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_EF_FLAG_Management FLAG Management 896:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @{ 897:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 898:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 899:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 900:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Check if Rx buffer is not empty 901:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll SR RXNE LL_SPI_IsActiveFlag_RXNE 902:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance ARM GAS /tmp/ccqopZd5.s page 123 903:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval State of bit (1 or 0). 904:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 905:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXNE(SPI_TypeDef *SPIx) 1120 .loc 4 905 26 discriminator 1 view .LVU354 1121 .LBB305: 906:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** return ((READ_BIT(SPIx->SR, SPI_SR_RXNE) == (SPI_SR_RXNE)) ? 1UL : 0UL); 1122 .loc 4 907 3 discriminator 1 view .LVU355 1123 .loc 4 907 12 is_stmt 0 discriminator 1 view .LVU356 1124 0094 614A ldr r2, .L88+8 1125 0096 9268 ldr r2, [r2, #8] 1126 .loc 4 907 68 discriminator 1 view .LVU357 1127 0098 12F0010F tst r2, #1 1128 009c 04D1 bne .L53 1129 .LVL112: 1130 .loc 4 907 68 discriminator 1 view .LVU358 1131 .LBE305: 1132 .LBE304: 2217:Src/main.c **** LL_SPI_Disable(SPI4);//Enable SPI for MPhD1 ADC 1133 .loc 2 2217 43 view .LVU359 1134 009e B3F57A7F cmp r3, #1000 1135 00a2 01D8 bhi .L53 2217:Src/main.c **** LL_SPI_Disable(SPI4);//Enable SPI for MPhD1 ADC 1136 .loc 2 2217 62 is_stmt 1 discriminator 3 view .LVU360 2217:Src/main.c **** LL_SPI_Disable(SPI4);//Enable SPI for MPhD1 ADC 1137 .loc 2 2217 67 is_stmt 0 discriminator 3 view .LVU361 1138 00a4 0133 adds r3, r3, #1 1139 .LVL113: 2217:Src/main.c **** LL_SPI_Disable(SPI4);//Enable SPI for MPhD1 ADC 1140 .loc 2 2217 67 discriminator 3 view .LVU362 1141 00a6 F5E7 b .L52 1142 .L53: 2218:Src/main.c **** while(tmp32<500){tmp32++;} 1143 .loc 2 2218 3 is_stmt 1 view .LVU363 1144 .LVL114: 1145 .LBB306: 1146 .LBI306: 370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 1147 .loc 4 370 22 view .LVU364 1148 .LBB307: 372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1149 .loc 4 372 3 view .LVU365 1150 00a8 5C49 ldr r1, .L88+8 1151 00aa 0A68 ldr r2, [r1] 1152 00ac 22F04002 bic r2, r2, #64 1153 00b0 0A60 str r2, [r1] 373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 1154 .loc 4 373 1 is_stmt 0 view .LVU366 1155 00b2 00E0 b .L55 1156 .LVL115: 1157 .L56: 373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 1158 .loc 4 373 1 view .LVU367 1159 .LBE307: 1160 .LBE306: 2219:Src/main.c **** //HAL_SPI_Receive(&hspi4, &P[0], 1, 100); 1161 .loc 2 2219 20 is_stmt 1 discriminator 2 view .LVU368 ARM GAS /tmp/ccqopZd5.s page 124 2219:Src/main.c **** //HAL_SPI_Receive(&hspi4, &P[0], 1, 100); 1162 .loc 2 2219 25 is_stmt 0 discriminator 2 view .LVU369 1163 00b4 0133 adds r3, r3, #1 1164 .LVL116: 1165 .L55: 2219:Src/main.c **** //HAL_SPI_Receive(&hspi4, &P[0], 1, 100); 1166 .loc 2 2219 8 is_stmt 1 discriminator 1 view .LVU370 1167 00b6 B3F5FA7F cmp r3, #500 1168 00ba FBD3 bcc .L56 2221:Src/main.c **** P = LL_SPI_ReceiveData16(SPI4); 1169 .loc 2 2221 3 view .LVU371 1170 00bc 0122 movs r2, #1 1171 00be 4FF48061 mov r1, #1024 1172 00c2 5448 ldr r0, .L88 1173 00c4 FFF7FEFF bl HAL_GPIO_WritePin 1174 .LVL117: 2222:Src/main.c **** } 1175 .loc 2 2222 3 view .LVU372 1176 .LBB308: 1177 .LBI308: 908:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 909:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 910:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 911:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Check if Tx buffer is empty 912:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll SR TXE LL_SPI_IsActiveFlag_TXE 913:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 914:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval State of bit (1 or 0). 915:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 916:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXE(SPI_TypeDef *SPIx) 917:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** return ((READ_BIT(SPIx->SR, SPI_SR_TXE) == (SPI_SR_TXE)) ? 1UL : 0UL); 919:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 920:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 921:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 922:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Get CRC error flag 923:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll SR CRCERR LL_SPI_IsActiveFlag_CRCERR 924:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 925:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval State of bit (1 or 0). 926:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 927:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_CRCERR(SPI_TypeDef *SPIx) 928:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 929:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** return ((READ_BIT(SPIx->SR, SPI_SR_CRCERR) == (SPI_SR_CRCERR)) ? 1UL : 0UL); 930:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 931:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 932:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 933:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Get mode fault error flag 934:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll SR MODF LL_SPI_IsActiveFlag_MODF 935:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 936:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval State of bit (1 or 0). 937:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 938:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_MODF(SPI_TypeDef *SPIx) 939:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 940:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** return ((READ_BIT(SPIx->SR, SPI_SR_MODF) == (SPI_SR_MODF)) ? 1UL : 0UL); 941:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 942:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 943:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 944:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Get overrun error flag ARM GAS /tmp/ccqopZd5.s page 125 945:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll SR OVR LL_SPI_IsActiveFlag_OVR 946:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 947:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval State of bit (1 or 0). 948:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 949:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_OVR(SPI_TypeDef *SPIx) 950:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 951:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** return ((READ_BIT(SPIx->SR, SPI_SR_OVR) == (SPI_SR_OVR)) ? 1UL : 0UL); 952:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 953:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 954:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 955:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Get busy flag 956:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @note The BSY flag is cleared under any one of the following conditions: 957:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * -When the SPI is correctly disabled 958:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * -When a fault is detected in Master mode (MODF bit set to 1) 959:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * -In Master mode, when it finishes a data transmission and no new data is ready to be 960:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * sent 961:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * -In Slave mode, when the BSY flag is set to '0' for at least one SPI clock cycle between 962:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * each data transfer. 963:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll SR BSY LL_SPI_IsActiveFlag_BSY 964:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 965:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval State of bit (1 or 0). 966:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 967:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_BSY(SPI_TypeDef *SPIx) 968:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 969:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** return ((READ_BIT(SPIx->SR, SPI_SR_BSY) == (SPI_SR_BSY)) ? 1UL : 0UL); 970:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 971:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 972:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 973:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Get frame format error flag 974:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll SR FRE LL_SPI_IsActiveFlag_FRE 975:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 976:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval State of bit (1 or 0). 977:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 978:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_FRE(SPI_TypeDef *SPIx) 979:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 980:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** return ((READ_BIT(SPIx->SR, SPI_SR_FRE) == (SPI_SR_FRE)) ? 1UL : 0UL); 981:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 982:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 983:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 984:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Get FIFO reception Level 985:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll SR FRLVL LL_SPI_GetRxFIFOLevel 986:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 987:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval Returned value can be one of the following values: 988:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_RX_FIFO_EMPTY 989:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_RX_FIFO_QUARTER_FULL 990:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_RX_FIFO_HALF_FULL 991:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_RX_FIFO_FULL 992:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 993:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_GetRxFIFOLevel(SPI_TypeDef *SPIx) 994:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 995:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** return (uint32_t)(READ_BIT(SPIx->SR, SPI_SR_FRLVL)); 996:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 997:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 998:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 999:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Get FIFO Transmission Level 1000:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll SR FTLVL LL_SPI_GetTxFIFOLevel 1001:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance ARM GAS /tmp/ccqopZd5.s page 126 1002:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval Returned value can be one of the following values: 1003:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_TX_FIFO_EMPTY 1004:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_TX_FIFO_QUARTER_FULL 1005:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_TX_FIFO_HALF_FULL 1006:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_TX_FIFO_FULL 1007:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 1008:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_GetTxFIFOLevel(SPI_TypeDef *SPIx) 1009:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 1010:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** return (uint32_t)(READ_BIT(SPIx->SR, SPI_SR_FTLVL)); 1011:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1012:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 1013:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 1014:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Clear CRC error flag 1015:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll SR CRCERR LL_SPI_ClearFlag_CRCERR 1016:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 1017:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None 1018:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 1019:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_ClearFlag_CRCERR(SPI_TypeDef *SPIx) 1020:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 1021:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** CLEAR_BIT(SPIx->SR, SPI_SR_CRCERR); 1022:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1023:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 1024:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 1025:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Clear mode fault error flag 1026:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @note Clearing this flag is done by a read access to the SPIx_SR 1027:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * register followed by a write access to the SPIx_CR1 register 1028:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll SR MODF LL_SPI_ClearFlag_MODF 1029:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 1030:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None 1031:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 1032:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_ClearFlag_MODF(SPI_TypeDef *SPIx) 1033:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 1034:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __IO uint32_t tmpreg_sr; 1035:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** tmpreg_sr = SPIx->SR; 1036:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** (void) tmpreg_sr; 1037:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE); 1038:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1039:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 1040:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 1041:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Clear overrun error flag 1042:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @note Clearing this flag is done by a read access to the SPIx_DR 1043:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * register followed by a read access to the SPIx_SR register 1044:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll SR OVR LL_SPI_ClearFlag_OVR 1045:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 1046:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None 1047:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 1048:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_ClearFlag_OVR(SPI_TypeDef *SPIx) 1049:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 1050:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __IO uint32_t tmpreg; 1051:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** tmpreg = SPIx->DR; 1052:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** (void) tmpreg; 1053:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** tmpreg = SPIx->SR; 1054:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** (void) tmpreg; 1055:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1056:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 1057:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 1058:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Clear frame format error flag ARM GAS /tmp/ccqopZd5.s page 127 1059:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @note Clearing this flag is done by reading SPIx_SR register 1060:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll SR FRE LL_SPI_ClearFlag_FRE 1061:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 1062:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None 1063:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 1064:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_ClearFlag_FRE(SPI_TypeDef *SPIx) 1065:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 1066:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __IO uint32_t tmpreg; 1067:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** tmpreg = SPIx->SR; 1068:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** (void) tmpreg; 1069:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1070:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 1071:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 1072:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @} 1073:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 1074:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 1075:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_EF_IT_Management Interrupt Management 1076:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @{ 1077:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 1078:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 1079:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 1080:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Enable error interrupt 1081:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @note This bit controls the generation of an interrupt when an error condition occurs (CRCERR 1082:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR2 ERRIE LL_SPI_EnableIT_ERR 1083:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 1084:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None 1085:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 1086:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_EnableIT_ERR(SPI_TypeDef *SPIx) 1087:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 1088:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** SET_BIT(SPIx->CR2, SPI_CR2_ERRIE); 1089:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1090:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 1091:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 1092:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Enable Rx buffer not empty interrupt 1093:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR2 RXNEIE LL_SPI_EnableIT_RXNE 1094:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 1095:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None 1096:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 1097:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_EnableIT_RXNE(SPI_TypeDef *SPIx) 1098:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 1099:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** SET_BIT(SPIx->CR2, SPI_CR2_RXNEIE); 1100:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1101:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 1102:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 1103:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Enable Tx buffer empty interrupt 1104:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR2 TXEIE LL_SPI_EnableIT_TXE 1105:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 1106:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None 1107:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 1108:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_EnableIT_TXE(SPI_TypeDef *SPIx) 1109:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 1110:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** SET_BIT(SPIx->CR2, SPI_CR2_TXEIE); 1111:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1112:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 1113:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 1114:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Disable error interrupt 1115:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @note This bit controls the generation of an interrupt when an error condition occurs (CRCERR ARM GAS /tmp/ccqopZd5.s page 128 1116:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR2 ERRIE LL_SPI_DisableIT_ERR 1117:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 1118:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None 1119:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 1120:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_DisableIT_ERR(SPI_TypeDef *SPIx) 1121:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 1122:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** CLEAR_BIT(SPIx->CR2, SPI_CR2_ERRIE); 1123:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1124:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 1125:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 1126:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Disable Rx buffer not empty interrupt 1127:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR2 RXNEIE LL_SPI_DisableIT_RXNE 1128:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 1129:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None 1130:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 1131:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_DisableIT_RXNE(SPI_TypeDef *SPIx) 1132:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 1133:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** CLEAR_BIT(SPIx->CR2, SPI_CR2_RXNEIE); 1134:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1135:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 1136:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 1137:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Disable Tx buffer empty interrupt 1138:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR2 TXEIE LL_SPI_DisableIT_TXE 1139:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 1140:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None 1141:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 1142:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_DisableIT_TXE(SPI_TypeDef *SPIx) 1143:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 1144:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** CLEAR_BIT(SPIx->CR2, SPI_CR2_TXEIE); 1145:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1146:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 1147:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 1148:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Check if error interrupt is enabled 1149:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR2 ERRIE LL_SPI_IsEnabledIT_ERR 1150:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 1151:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval State of bit (1 or 0). 1152:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 1153:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_ERR(SPI_TypeDef *SPIx) 1154:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 1155:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** return ((READ_BIT(SPIx->CR2, SPI_CR2_ERRIE) == (SPI_CR2_ERRIE)) ? 1UL : 0UL); 1156:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1157:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 1158:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 1159:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Check if Rx buffer not empty interrupt is enabled 1160:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR2 RXNEIE LL_SPI_IsEnabledIT_RXNE 1161:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 1162:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval State of bit (1 or 0). 1163:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 1164:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_RXNE(SPI_TypeDef *SPIx) 1165:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 1166:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** return ((READ_BIT(SPIx->CR2, SPI_CR2_RXNEIE) == (SPI_CR2_RXNEIE)) ? 1UL : 0UL); 1167:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1168:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 1169:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 1170:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Check if Tx buffer empty interrupt 1171:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR2 TXEIE LL_SPI_IsEnabledIT_TXE 1172:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance ARM GAS /tmp/ccqopZd5.s page 129 1173:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval State of bit (1 or 0). 1174:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 1175:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_TXE(SPI_TypeDef *SPIx) 1176:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 1177:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** return ((READ_BIT(SPIx->CR2, SPI_CR2_TXEIE) == (SPI_CR2_TXEIE)) ? 1UL : 0UL); 1178:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1179:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 1180:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 1181:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @} 1182:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 1183:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 1184:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_EF_DMA_Management DMA Management 1185:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @{ 1186:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 1187:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 1188:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 1189:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Enable DMA Rx 1190:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR2 RXDMAEN LL_SPI_EnableDMAReq_RX 1191:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 1192:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None 1193:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 1194:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_EnableDMAReq_RX(SPI_TypeDef *SPIx) 1195:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 1196:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** SET_BIT(SPIx->CR2, SPI_CR2_RXDMAEN); 1197:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1198:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 1199:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 1200:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Disable DMA Rx 1201:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR2 RXDMAEN LL_SPI_DisableDMAReq_RX 1202:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 1203:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None 1204:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 1205:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_DisableDMAReq_RX(SPI_TypeDef *SPIx) 1206:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 1207:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** CLEAR_BIT(SPIx->CR2, SPI_CR2_RXDMAEN); 1208:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1209:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 1210:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 1211:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Check if DMA Rx is enabled 1212:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR2 RXDMAEN LL_SPI_IsEnabledDMAReq_RX 1213:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 1214:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval State of bit (1 or 0). 1215:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 1216:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_RX(SPI_TypeDef *SPIx) 1217:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 1218:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** return ((READ_BIT(SPIx->CR2, SPI_CR2_RXDMAEN) == (SPI_CR2_RXDMAEN)) ? 1UL : 0UL); 1219:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1220:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 1221:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 1222:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Enable DMA Tx 1223:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR2 TXDMAEN LL_SPI_EnableDMAReq_TX 1224:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 1225:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None 1226:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 1227:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_EnableDMAReq_TX(SPI_TypeDef *SPIx) 1228:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 1229:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** SET_BIT(SPIx->CR2, SPI_CR2_TXDMAEN); ARM GAS /tmp/ccqopZd5.s page 130 1230:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1231:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 1232:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 1233:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Disable DMA Tx 1234:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR2 TXDMAEN LL_SPI_DisableDMAReq_TX 1235:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 1236:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None 1237:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 1238:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_DisableDMAReq_TX(SPI_TypeDef *SPIx) 1239:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 1240:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** CLEAR_BIT(SPIx->CR2, SPI_CR2_TXDMAEN); 1241:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1242:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 1243:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 1244:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Check if DMA Tx is enabled 1245:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR2 TXDMAEN LL_SPI_IsEnabledDMAReq_TX 1246:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 1247:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval State of bit (1 or 0). 1248:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 1249:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx) 1250:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 1251:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** return ((READ_BIT(SPIx->CR2, SPI_CR2_TXDMAEN) == (SPI_CR2_TXDMAEN)) ? 1UL : 0UL); 1252:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1253:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 1254:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 1255:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Set parity of Last DMA reception 1256:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR2 LDMARX LL_SPI_SetDMAParity_RX 1257:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 1258:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param Parity This parameter can be one of the following values: 1259:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_DMA_PARITY_ODD 1260:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_DMA_PARITY_EVEN 1261:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None 1262:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 1263:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_SetDMAParity_RX(SPI_TypeDef *SPIx, uint32_t Parity) 1264:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 1265:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** MODIFY_REG(SPIx->CR2, SPI_CR2_LDMARX, (Parity << SPI_CR2_LDMARX_Pos)); 1266:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1267:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 1268:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 1269:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Get parity configuration for Last DMA reception 1270:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR2 LDMARX LL_SPI_GetDMAParity_RX 1271:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 1272:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval Returned value can be one of the following values: 1273:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_DMA_PARITY_ODD 1274:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_DMA_PARITY_EVEN 1275:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 1276:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_GetDMAParity_RX(SPI_TypeDef *SPIx) 1277:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 1278:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_LDMARX) >> SPI_CR2_LDMARX_Pos); 1279:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1280:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 1281:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 1282:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Set parity of Last DMA transmission 1283:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR2 LDMATX LL_SPI_SetDMAParity_TX 1284:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 1285:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param Parity This parameter can be one of the following values: 1286:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_DMA_PARITY_ODD ARM GAS /tmp/ccqopZd5.s page 131 1287:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_DMA_PARITY_EVEN 1288:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None 1289:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 1290:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_SetDMAParity_TX(SPI_TypeDef *SPIx, uint32_t Parity) 1291:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 1292:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** MODIFY_REG(SPIx->CR2, SPI_CR2_LDMATX, (Parity << SPI_CR2_LDMATX_Pos)); 1293:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1294:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 1295:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 1296:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Get parity configuration for Last DMA transmission 1297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR2 LDMATX LL_SPI_GetDMAParity_TX 1298:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 1299:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval Returned value can be one of the following values: 1300:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_DMA_PARITY_ODD 1301:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_DMA_PARITY_EVEN 1302:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 1303:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_GetDMAParity_TX(SPI_TypeDef *SPIx) 1304:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 1305:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_LDMATX) >> SPI_CR2_LDMATX_Pos); 1306:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1307:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 1308:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 1309:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Get the data register address used for DMA transfer 1310:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll DR DR LL_SPI_DMA_GetRegAddr 1311:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 1312:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval Address of data register 1313:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 1314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_DMA_GetRegAddr(SPI_TypeDef *SPIx) 1315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 1316:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** return (uint32_t) &(SPIx->DR); 1317:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1318:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 1319:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 1320:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @} 1321:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 1322:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 1323:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_EF_DATA_Management DATA Management 1324:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @{ 1325:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 1326:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 1327:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 1328:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Read 8-Bits in the data register 1329:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll DR DR LL_SPI_ReceiveData8 1330:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 1331:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval RxData Value between Min_Data=0x00 and Max_Data=0xFF 1332:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 1333:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint8_t LL_SPI_ReceiveData8(SPI_TypeDef *SPIx) 1334:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 1335:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** return (*((__IO uint8_t *)&SPIx->DR)); 1336:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1337:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 1338:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 1339:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Read 16-Bits in the data register 1340:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll DR DR LL_SPI_ReceiveData16 1341:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 1342:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval RxData Value between Min_Data=0x00 and Max_Data=0xFFFF 1343:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ ARM GAS /tmp/ccqopZd5.s page 132 1344:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint16_t LL_SPI_ReceiveData16(SPI_TypeDef *SPIx) 1178 .loc 4 1344 26 view .LVU373 1179 .LBB309: 1345:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 1346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** return (uint16_t)(READ_REG(SPIx->DR)); 1180 .loc 4 1346 3 view .LVU374 1181 .loc 4 1346 21 is_stmt 0 view .LVU375 1182 00c8 544B ldr r3, .L88+8 1183 00ca DD68 ldr r5, [r3, #12] 1184 .loc 4 1346 10 view .LVU376 1185 00cc ADB2 uxth r5, r5 1186 .LVL118: 1187 .loc 4 1346 10 view .LVU377 1188 .LBE309: 1189 .LBE308: 1190 00ce C6E7 b .L57 1191 .LVL119: 1192 .L83: 2226:Src/main.c **** HAL_GPIO_WritePin(ADC_MPD2_CS_GPIO_Port, ADC_MPD2_CS_Pin, GPIO_PIN_RESET); 1193 .loc 2 2226 3 is_stmt 1 view .LVU378 1194 00d0 514C ldr r4, .L88+4 1195 00d2 0122 movs r2, #1 1196 00d4 4FF48061 mov r1, #1024 1197 00d8 2046 mov r0, r4 1198 00da FFF7FEFF bl HAL_GPIO_WritePin 1199 .LVL120: 2227:Src/main.c **** tmp32=0; 1200 .loc 2 2227 3 view .LVU379 1201 00de 0022 movs r2, #0 1202 00e0 4021 movs r1, #64 1203 00e2 2046 mov r0, r4 1204 00e4 FFF7FEFF bl HAL_GPIO_WritePin 1205 .LVL121: 2228:Src/main.c **** while(tmp32<500){tmp32++;} 1206 .loc 2 2228 3 view .LVU380 2229:Src/main.c **** //LL_SPI_TransmitData16(SPI5, 0xFFFF);//We must to clock the CLK output for collect RX data. We c 1207 .loc 2 2229 3 view .LVU381 2228:Src/main.c **** while(tmp32<500){tmp32++;} 1208 .loc 2 2228 8 is_stmt 0 view .LVU382 1209 00e8 0023 movs r3, #0 2229:Src/main.c **** //LL_SPI_TransmitData16(SPI5, 0xFFFF);//We must to clock the CLK output for collect RX data. We c 1210 .loc 2 2229 8 view .LVU383 1211 00ea 00E0 b .L59 1212 .LVL122: 1213 .L60: 2229:Src/main.c **** //LL_SPI_TransmitData16(SPI5, 0xFFFF);//We must to clock the CLK output for collect RX data. We c 1214 .loc 2 2229 20 is_stmt 1 discriminator 2 view .LVU384 2229:Src/main.c **** //LL_SPI_TransmitData16(SPI5, 0xFFFF);//We must to clock the CLK output for collect RX data. We c 1215 .loc 2 2229 25 is_stmt 0 discriminator 2 view .LVU385 1216 00ec 0133 adds r3, r3, #1 1217 .LVL123: 1218 .L59: 2229:Src/main.c **** //LL_SPI_TransmitData16(SPI5, 0xFFFF);//We must to clock the CLK output for collect RX data. We c 1219 .loc 2 2229 8 is_stmt 1 discriminator 1 view .LVU386 1220 00ee B3F5FA7F cmp r3, #500 1221 00f2 FBD3 bcc .L60 2231:Src/main.c **** tmp32 = 0; ARM GAS /tmp/ccqopZd5.s page 133 1222 .loc 2 2231 3 view .LVU387 1223 .LVL124: 1224 .LBB310: 1225 .LBI310: 358:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 1226 .loc 4 358 22 view .LVU388 1227 .LBB311: 360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1228 .loc 4 360 3 view .LVU389 1229 00f4 4A4A ldr r2, .L88+12 1230 00f6 1368 ldr r3, [r2] 1231 .LVL125: 360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1232 .loc 4 360 3 is_stmt 0 view .LVU390 1233 00f8 43F04003 orr r3, r3, #64 1234 00fc 1360 str r3, [r2] 1235 .LVL126: 360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1236 .loc 4 360 3 view .LVU391 1237 .LBE311: 1238 .LBE310: 2232:Src/main.c **** while(((!LL_SPI_IsActiveFlag_RXNE(SPI5))&&(tmp32<=1000))) {tmp32++;}//When rec. last data cycle w 1239 .loc 2 2232 3 is_stmt 1 view .LVU392 2233:Src/main.c **** LL_SPI_Disable(SPI5);//Enable SPI for MPhD2 ADC 1240 .loc 2 2233 3 view .LVU393 2232:Src/main.c **** while(((!LL_SPI_IsActiveFlag_RXNE(SPI5))&&(tmp32<=1000))) {tmp32++;}//When rec. last data cycle w 1241 .loc 2 2232 9 is_stmt 0 view .LVU394 1242 00fe 0023 movs r3, #0 1243 .LVL127: 1244 .L61: 2233:Src/main.c **** LL_SPI_Disable(SPI5);//Enable SPI for MPhD2 ADC 1245 .loc 2 2233 8 is_stmt 1 discriminator 1 view .LVU395 1246 .LBB312: 1247 .LBI312: 905:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 1248 .loc 4 905 26 discriminator 1 view .LVU396 1249 .LBB313: 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1250 .loc 4 907 3 discriminator 1 view .LVU397 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1251 .loc 4 907 12 is_stmt 0 discriminator 1 view .LVU398 1252 0100 474A ldr r2, .L88+12 1253 0102 9268 ldr r2, [r2, #8] 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1254 .loc 4 907 68 discriminator 1 view .LVU399 1255 0104 12F0010F tst r2, #1 1256 0108 04D1 bne .L62 1257 .LVL128: 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1258 .loc 4 907 68 discriminator 1 view .LVU400 1259 .LBE313: 1260 .LBE312: 2233:Src/main.c **** LL_SPI_Disable(SPI5);//Enable SPI for MPhD2 ADC 1261 .loc 2 2233 43 view .LVU401 1262 010a B3F57A7F cmp r3, #1000 1263 010e 01D8 bhi .L62 2233:Src/main.c **** LL_SPI_Disable(SPI5);//Enable SPI for MPhD2 ADC ARM GAS /tmp/ccqopZd5.s page 134 1264 .loc 2 2233 62 is_stmt 1 discriminator 3 view .LVU402 2233:Src/main.c **** LL_SPI_Disable(SPI5);//Enable SPI for MPhD2 ADC 1265 .loc 2 2233 67 is_stmt 0 discriminator 3 view .LVU403 1266 0110 0133 adds r3, r3, #1 1267 .LVL129: 2233:Src/main.c **** LL_SPI_Disable(SPI5);//Enable SPI for MPhD2 ADC 1268 .loc 2 2233 67 discriminator 3 view .LVU404 1269 0112 F5E7 b .L61 1270 .L62: 2234:Src/main.c **** while(tmp32<500){tmp32++;} 1271 .loc 2 2234 3 is_stmt 1 view .LVU405 1272 .LVL130: 1273 .LBB314: 1274 .LBI314: 370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 1275 .loc 4 370 22 view .LVU406 1276 .LBB315: 372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1277 .loc 4 372 3 view .LVU407 1278 0114 4249 ldr r1, .L88+12 1279 0116 0A68 ldr r2, [r1] 1280 0118 22F04002 bic r2, r2, #64 1281 011c 0A60 str r2, [r1] 373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 1282 .loc 4 373 1 is_stmt 0 view .LVU408 1283 011e 00E0 b .L64 1284 .LVL131: 1285 .L65: 373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 1286 .loc 4 373 1 view .LVU409 1287 .LBE315: 1288 .LBE314: 2235:Src/main.c **** //HAL_SPI_Receive(&hspi4, &P[0], 1, 100); 1289 .loc 2 2235 20 is_stmt 1 discriminator 2 view .LVU410 2235:Src/main.c **** //HAL_SPI_Receive(&hspi4, &P[0], 1, 100); 1290 .loc 2 2235 25 is_stmt 0 discriminator 2 view .LVU411 1291 0120 0133 adds r3, r3, #1 1292 .LVL132: 1293 .L64: 2235:Src/main.c **** //HAL_SPI_Receive(&hspi4, &P[0], 1, 100); 1294 .loc 2 2235 8 is_stmt 1 discriminator 1 view .LVU412 1295 0122 B3F5FA7F cmp r3, #500 1296 0126 FBD3 bcc .L65 2237:Src/main.c **** P = LL_SPI_ReceiveData16(SPI5); 1297 .loc 2 2237 3 view .LVU413 1298 0128 0122 movs r2, #1 1299 012a 4021 movs r1, #64 1300 012c 3A48 ldr r0, .L88+4 1301 012e FFF7FEFF bl HAL_GPIO_WritePin 1302 .LVL133: 2238:Src/main.c **** } 1303 .loc 2 2238 3 view .LVU414 1304 .LBB316: 1305 .LBI316: 1344:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 1306 .loc 4 1344 26 view .LVU415 1307 .LBB317: ARM GAS /tmp/ccqopZd5.s page 135 1308 .loc 4 1346 3 view .LVU416 1309 .loc 4 1346 21 is_stmt 0 view .LVU417 1310 0132 3B4B ldr r3, .L88+12 1311 0134 DD68 ldr r5, [r3, #12] 1312 .loc 4 1346 10 view .LVU418 1313 0136 ADB2 uxth r5, r5 1314 .LVL134: 1315 .loc 4 1346 10 view .LVU419 1316 .LBE317: 1317 .LBE316: 1318 0138 91E7 b .L57 1319 .LVL135: 1320 .L84: 2242:Src/main.c **** HAL_GPIO_WritePin(ADC_ThrLD1_CS_GPIO_Port, ADC_ThrLD1_CS_Pin, GPIO_PIN_RESET); 1321 .loc 2 2242 3 is_stmt 1 view .LVU420 1322 013a 364C ldr r4, .L88 1323 013c 0122 movs r2, #1 1324 013e 4FF48061 mov r1, #1024 1325 0142 2046 mov r0, r4 1326 0144 FFF7FEFF bl HAL_GPIO_WritePin 1327 .LVL136: 2243:Src/main.c **** tmp32=0; 1328 .loc 2 2243 3 view .LVU421 1329 0148 0022 movs r2, #0 1330 014a 4FF40061 mov r1, #2048 1331 014e 2046 mov r0, r4 1332 0150 FFF7FEFF bl HAL_GPIO_WritePin 1333 .LVL137: 2244:Src/main.c **** while(tmp32<500){tmp32++;} 1334 .loc 2 2244 3 view .LVU422 2245:Src/main.c **** //LL_SPI_TransmitData16(SPI4, 0xFFFF);//We must to clock the CLK output for collect RX data. We c 1335 .loc 2 2245 3 view .LVU423 2244:Src/main.c **** while(tmp32<500){tmp32++;} 1336 .loc 2 2244 8 is_stmt 0 view .LVU424 1337 0154 0023 movs r3, #0 2245:Src/main.c **** //LL_SPI_TransmitData16(SPI4, 0xFFFF);//We must to clock the CLK output for collect RX data. We c 1338 .loc 2 2245 8 view .LVU425 1339 0156 00E0 b .L67 1340 .LVL138: 1341 .L68: 2245:Src/main.c **** //LL_SPI_TransmitData16(SPI4, 0xFFFF);//We must to clock the CLK output for collect RX data. We c 1342 .loc 2 2245 20 is_stmt 1 discriminator 2 view .LVU426 2245:Src/main.c **** //LL_SPI_TransmitData16(SPI4, 0xFFFF);//We must to clock the CLK output for collect RX data. We c 1343 .loc 2 2245 25 is_stmt 0 discriminator 2 view .LVU427 1344 0158 0133 adds r3, r3, #1 1345 .LVL139: 1346 .L67: 2245:Src/main.c **** //LL_SPI_TransmitData16(SPI4, 0xFFFF);//We must to clock the CLK output for collect RX data. We c 1347 .loc 2 2245 8 is_stmt 1 discriminator 1 view .LVU428 1348 015a B3F5FA7F cmp r3, #500 1349 015e FBD3 bcc .L68 2247:Src/main.c **** tmp32 = 0; 1350 .loc 2 2247 3 view .LVU429 1351 .LVL140: 1352 .LBB318: 1353 .LBI318: 358:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { ARM GAS /tmp/ccqopZd5.s page 136 1354 .loc 4 358 22 view .LVU430 1355 .LBB319: 360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1356 .loc 4 360 3 view .LVU431 1357 0160 2E4A ldr r2, .L88+8 1358 0162 1368 ldr r3, [r2] 1359 .LVL141: 360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1360 .loc 4 360 3 is_stmt 0 view .LVU432 1361 0164 43F04003 orr r3, r3, #64 1362 0168 1360 str r3, [r2] 1363 .LVL142: 360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1364 .loc 4 360 3 view .LVU433 1365 .LBE319: 1366 .LBE318: 2248:Src/main.c **** while(((!LL_SPI_IsActiveFlag_RXNE(SPI4))&&(tmp32<=1000))) {tmp32++;}//When rec. last data cycle w 1367 .loc 2 2248 3 is_stmt 1 view .LVU434 2249:Src/main.c **** LL_SPI_Disable(SPI4);//Enable SPI for ThrLD1 ADC 1368 .loc 2 2249 3 view .LVU435 2248:Src/main.c **** while(((!LL_SPI_IsActiveFlag_RXNE(SPI4))&&(tmp32<=1000))) {tmp32++;}//When rec. last data cycle w 1369 .loc 2 2248 9 is_stmt 0 view .LVU436 1370 016a 0023 movs r3, #0 1371 .LVL143: 1372 .L69: 2249:Src/main.c **** LL_SPI_Disable(SPI4);//Enable SPI for ThrLD1 ADC 1373 .loc 2 2249 8 is_stmt 1 discriminator 1 view .LVU437 1374 .LBB320: 1375 .LBI320: 905:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 1376 .loc 4 905 26 discriminator 1 view .LVU438 1377 .LBB321: 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1378 .loc 4 907 3 discriminator 1 view .LVU439 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1379 .loc 4 907 12 is_stmt 0 discriminator 1 view .LVU440 1380 016c 2B4A ldr r2, .L88+8 1381 016e 9268 ldr r2, [r2, #8] 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1382 .loc 4 907 68 discriminator 1 view .LVU441 1383 0170 12F0010F tst r2, #1 1384 0174 04D1 bne .L70 1385 .LVL144: 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1386 .loc 4 907 68 discriminator 1 view .LVU442 1387 .LBE321: 1388 .LBE320: 2249:Src/main.c **** LL_SPI_Disable(SPI4);//Enable SPI for ThrLD1 ADC 1389 .loc 2 2249 43 view .LVU443 1390 0176 B3F57A7F cmp r3, #1000 1391 017a 01D8 bhi .L70 2249:Src/main.c **** LL_SPI_Disable(SPI4);//Enable SPI for ThrLD1 ADC 1392 .loc 2 2249 62 is_stmt 1 discriminator 3 view .LVU444 2249:Src/main.c **** LL_SPI_Disable(SPI4);//Enable SPI for ThrLD1 ADC 1393 .loc 2 2249 67 is_stmt 0 discriminator 3 view .LVU445 1394 017c 0133 adds r3, r3, #1 1395 .LVL145: ARM GAS /tmp/ccqopZd5.s page 137 2249:Src/main.c **** LL_SPI_Disable(SPI4);//Enable SPI for ThrLD1 ADC 1396 .loc 2 2249 67 discriminator 3 view .LVU446 1397 017e F5E7 b .L69 1398 .L70: 2250:Src/main.c **** while(tmp32<500){tmp32++;} 1399 .loc 2 2250 3 is_stmt 1 view .LVU447 1400 .LVL146: 1401 .LBB322: 1402 .LBI322: 370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 1403 .loc 4 370 22 view .LVU448 1404 .LBB323: 372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1405 .loc 4 372 3 view .LVU449 1406 0180 2649 ldr r1, .L88+8 1407 0182 0A68 ldr r2, [r1] 1408 0184 22F04002 bic r2, r2, #64 1409 0188 0A60 str r2, [r1] 1410 .LVL147: 1411 .L72: 372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1412 .loc 4 372 3 is_stmt 0 view .LVU450 1413 .LBE323: 1414 .LBE322: 2251:Src/main.c **** //HAL_SPI_Receive(&hspi4, &P[0], 1, 100); 1415 .loc 2 2251 8 is_stmt 1 discriminator 1 view .LVU451 1416 018a B3F5FA7F cmp r3, #500 1417 018e 01D2 bcs .L86 2251:Src/main.c **** //HAL_SPI_Receive(&hspi4, &P[0], 1, 100); 1418 .loc 2 2251 20 discriminator 2 view .LVU452 2251:Src/main.c **** //HAL_SPI_Receive(&hspi4, &P[0], 1, 100); 1419 .loc 2 2251 25 is_stmt 0 discriminator 2 view .LVU453 1420 0190 0133 adds r3, r3, #1 1421 .LVL148: 2251:Src/main.c **** //HAL_SPI_Receive(&hspi4, &P[0], 1, 100); 1422 .loc 2 2251 25 discriminator 2 view .LVU454 1423 0192 FAE7 b .L72 1424 .L86: 2253:Src/main.c **** P = LL_SPI_ReceiveData16(SPI4); 1425 .loc 2 2253 3 is_stmt 1 view .LVU455 1426 0194 0122 movs r2, #1 1427 0196 4FF40061 mov r1, #2048 1428 019a 1E48 ldr r0, .L88 1429 019c FFF7FEFF bl HAL_GPIO_WritePin 1430 .LVL149: 2254:Src/main.c **** } 1431 .loc 2 2254 3 view .LVU456 1432 .LBB324: 1433 .LBI324: 1344:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 1434 .loc 4 1344 26 view .LVU457 1435 .LBB325: 1436 .loc 4 1346 3 view .LVU458 1437 .loc 4 1346 21 is_stmt 0 view .LVU459 1438 01a0 1E4B ldr r3, .L88+8 1439 01a2 DD68 ldr r5, [r3, #12] 1440 .loc 4 1346 10 view .LVU460 ARM GAS /tmp/ccqopZd5.s page 138 1441 01a4 ADB2 uxth r5, r5 1442 .LVL150: 1443 .loc 4 1346 10 view .LVU461 1444 .LBE325: 1445 .LBE324: 1446 01a6 5AE7 b .L57 1447 .LVL151: 1448 .L85: 2258:Src/main.c **** HAL_GPIO_WritePin(ADC_ThrLD2_CS_GPIO_Port, ADC_ThrLD2_CS_Pin, GPIO_PIN_RESET); 1449 .loc 2 2258 3 is_stmt 1 view .LVU462 1450 01a8 1B4C ldr r4, .L88+4 1451 01aa 0122 movs r2, #1 1452 01ac 4021 movs r1, #64 1453 01ae 2046 mov r0, r4 1454 01b0 FFF7FEFF bl HAL_GPIO_WritePin 1455 .LVL152: 2259:Src/main.c **** tmp32=0; 1456 .loc 2 2259 3 view .LVU463 1457 01b4 0022 movs r2, #0 1458 01b6 4FF48061 mov r1, #1024 1459 01ba 2046 mov r0, r4 1460 01bc FFF7FEFF bl HAL_GPIO_WritePin 1461 .LVL153: 2260:Src/main.c **** while(tmp32<500){tmp32++;} 1462 .loc 2 2260 3 view .LVU464 2261:Src/main.c **** //LL_SPI_TransmitData16(SPI5, 0xFFFF);//We must to clock the CLK output for collect RX data. We c 1463 .loc 2 2261 3 view .LVU465 2260:Src/main.c **** while(tmp32<500){tmp32++;} 1464 .loc 2 2260 8 is_stmt 0 view .LVU466 1465 01c0 0023 movs r3, #0 1466 .LVL154: 1467 .L74: 2261:Src/main.c **** //LL_SPI_TransmitData16(SPI5, 0xFFFF);//We must to clock the CLK output for collect RX data. We c 1468 .loc 2 2261 8 is_stmt 1 discriminator 1 view .LVU467 1469 01c2 B3F5FA7F cmp r3, #500 1470 01c6 01D2 bcs .L87 2261:Src/main.c **** //LL_SPI_TransmitData16(SPI5, 0xFFFF);//We must to clock the CLK output for collect RX data. We c 1471 .loc 2 2261 20 discriminator 2 view .LVU468 2261:Src/main.c **** //LL_SPI_TransmitData16(SPI5, 0xFFFF);//We must to clock the CLK output for collect RX data. We c 1472 .loc 2 2261 25 is_stmt 0 discriminator 2 view .LVU469 1473 01c8 0133 adds r3, r3, #1 1474 .LVL155: 2261:Src/main.c **** //LL_SPI_TransmitData16(SPI5, 0xFFFF);//We must to clock the CLK output for collect RX data. We c 1475 .loc 2 2261 25 discriminator 2 view .LVU470 1476 01ca FAE7 b .L74 1477 .L87: 2263:Src/main.c **** tmp32 = 0; 1478 .loc 2 2263 3 is_stmt 1 view .LVU471 1479 .LVL156: 1480 .LBB326: 1481 .LBI326: 358:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 1482 .loc 4 358 22 view .LVU472 1483 .LBB327: 360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1484 .loc 4 360 3 view .LVU473 1485 01cc 144A ldr r2, .L88+12 ARM GAS /tmp/ccqopZd5.s page 139 1486 01ce 1368 ldr r3, [r2] 1487 .LVL157: 360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1488 .loc 4 360 3 is_stmt 0 view .LVU474 1489 01d0 43F04003 orr r3, r3, #64 1490 01d4 1360 str r3, [r2] 1491 .LVL158: 360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1492 .loc 4 360 3 view .LVU475 1493 .LBE327: 1494 .LBE326: 2264:Src/main.c **** while(((!LL_SPI_IsActiveFlag_RXNE(SPI5))&&(tmp32<=1000))) {tmp32++;}//When rec. last data cycle w 1495 .loc 2 2264 3 is_stmt 1 view .LVU476 2265:Src/main.c **** LL_SPI_Disable(SPI5);//Enable SPI for ThrLD2 ADC 1496 .loc 2 2265 3 view .LVU477 2264:Src/main.c **** while(((!LL_SPI_IsActiveFlag_RXNE(SPI5))&&(tmp32<=1000))) {tmp32++;}//When rec. last data cycle w 1497 .loc 2 2264 9 is_stmt 0 view .LVU478 1498 01d6 0023 movs r3, #0 1499 .LVL159: 1500 .L76: 2265:Src/main.c **** LL_SPI_Disable(SPI5);//Enable SPI for ThrLD2 ADC 1501 .loc 2 2265 8 is_stmt 1 discriminator 1 view .LVU479 1502 .LBB328: 1503 .LBI328: 905:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 1504 .loc 4 905 26 discriminator 1 view .LVU480 1505 .LBB329: 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1506 .loc 4 907 3 discriminator 1 view .LVU481 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1507 .loc 4 907 12 is_stmt 0 discriminator 1 view .LVU482 1508 01d8 114A ldr r2, .L88+12 1509 01da 9268 ldr r2, [r2, #8] 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1510 .loc 4 907 68 discriminator 1 view .LVU483 1511 01dc 12F0010F tst r2, #1 1512 01e0 04D1 bne .L77 1513 .LVL160: 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1514 .loc 4 907 68 discriminator 1 view .LVU484 1515 .LBE329: 1516 .LBE328: 2265:Src/main.c **** LL_SPI_Disable(SPI5);//Enable SPI for ThrLD2 ADC 1517 .loc 2 2265 43 view .LVU485 1518 01e2 B3F57A7F cmp r3, #1000 1519 01e6 01D8 bhi .L77 2265:Src/main.c **** LL_SPI_Disable(SPI5);//Enable SPI for ThrLD2 ADC 1520 .loc 2 2265 62 is_stmt 1 discriminator 3 view .LVU486 2265:Src/main.c **** LL_SPI_Disable(SPI5);//Enable SPI for ThrLD2 ADC 1521 .loc 2 2265 67 is_stmt 0 discriminator 3 view .LVU487 1522 01e8 0133 adds r3, r3, #1 1523 .LVL161: 2265:Src/main.c **** LL_SPI_Disable(SPI5);//Enable SPI for ThrLD2 ADC 1524 .loc 2 2265 67 discriminator 3 view .LVU488 1525 01ea F5E7 b .L76 1526 .L77: 2266:Src/main.c **** while(tmp32<500){tmp32++;} ARM GAS /tmp/ccqopZd5.s page 140 1527 .loc 2 2266 3 is_stmt 1 view .LVU489 1528 .LVL162: 1529 .LBB330: 1530 .LBI330: 370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 1531 .loc 4 370 22 view .LVU490 1532 .LBB331: 372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1533 .loc 4 372 3 view .LVU491 1534 01ec 0C49 ldr r1, .L88+12 1535 01ee 0A68 ldr r2, [r1] 1536 01f0 22F04002 bic r2, r2, #64 1537 01f4 0A60 str r2, [r1] 373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 1538 .loc 4 373 1 is_stmt 0 view .LVU492 1539 01f6 00E0 b .L79 1540 .LVL163: 1541 .L80: 373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 1542 .loc 4 373 1 view .LVU493 1543 .LBE331: 1544 .LBE330: 2267:Src/main.c **** //HAL_SPI_Receive(&hspi4, &P[0], 1, 100); 1545 .loc 2 2267 20 is_stmt 1 discriminator 2 view .LVU494 2267:Src/main.c **** //HAL_SPI_Receive(&hspi4, &P[0], 1, 100); 1546 .loc 2 2267 25 is_stmt 0 discriminator 2 view .LVU495 1547 01f8 0133 adds r3, r3, #1 1548 .LVL164: 1549 .L79: 2267:Src/main.c **** //HAL_SPI_Receive(&hspi4, &P[0], 1, 100); 1550 .loc 2 2267 8 is_stmt 1 discriminator 1 view .LVU496 1551 01fa B3F5FA7F cmp r3, #500 1552 01fe FBD3 bcc .L80 2269:Src/main.c **** P = LL_SPI_ReceiveData16(SPI5); 1553 .loc 2 2269 3 view .LVU497 1554 0200 0122 movs r2, #1 1555 0202 4FF48061 mov r1, #1024 1556 0206 0448 ldr r0, .L88+4 1557 0208 FFF7FEFF bl HAL_GPIO_WritePin 1558 .LVL165: 2270:Src/main.c **** } 1559 .loc 2 2270 3 view .LVU498 1560 .LBB332: 1561 .LBI332: 1344:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 1562 .loc 4 1344 26 view .LVU499 1563 .LBB333: 1564 .loc 4 1346 3 view .LVU500 1565 .loc 4 1346 21 is_stmt 0 view .LVU501 1566 020c 044B ldr r3, .L88+12 1567 020e DD68 ldr r5, [r3, #12] 1568 .loc 4 1346 10 view .LVU502 1569 0210 ADB2 uxth r5, r5 1570 .LVL166: 1571 .loc 4 1346 10 view .LVU503 1572 0212 24E7 b .L57 1573 .L89: ARM GAS /tmp/ccqopZd5.s page 141 1574 .align 2 1575 .L88: 1576 0214 00100240 .word 1073876992 1577 0218 00140240 .word 1073878016 1578 021c 00340140 .word 1073820672 1579 0220 00500140 .word 1073827840 1580 .LBE333: 1581 .LBE332: 1582 .cfi_endproc 1583 .LFE1211: 1585 .section .text.Stop_TIM10,"ax",%progbits 1586 .align 1 1587 .syntax unified 1588 .thumb 1589 .thumb_func 1590 .fpu fpv5-d16 1592 Stop_TIM10: 1593 .LFB1222: 2435:Src/main.c **** uint8_t CheckChecksum(uint16_t *pbuff) 2436:Src/main.c **** { 2437:Src/main.c **** uint16_t cl_ind; 2438:Src/main.c **** 2439:Src/main.c **** switch (UART_header) 2440:Src/main.c **** { 2441:Src/main.c **** case 0x7777: 2442:Src/main.c **** cl_ind = TSK_16 - 2; 2443:Src/main.c **** break; 2444:Src/main.c **** case 0x1111: 2445:Src/main.c **** cl_ind = CL_16 - 2; 2446:Src/main.c **** break; 2447:Src/main.c **** default: 2448:Src/main.c **** return 0; 2449:Src/main.c **** break; 2450:Src/main.c **** } 2451:Src/main.c **** 2452:Src/main.c **** CS_result = CalculateChecksum(pbuff, cl_ind); 2453:Src/main.c **** 2454:Src/main.c **** return ((CS_result == COMMAND[cl_ind]) ? 1 : 0); 2455:Src/main.c **** } 2456:Src/main.c **** uint16_t CalculateChecksum(uint16_t *pbuff, uint16_t len) 2457:Src/main.c **** { 2458:Src/main.c **** short i; 2459:Src/main.c **** uint16_t cs = *pbuff; 2460:Src/main.c **** 2461:Src/main.c **** for(i = 1; i < len; i++) 2462:Src/main.c **** { 2463:Src/main.c **** cs ^= *(pbuff+i); 2464:Src/main.c **** } 2465:Src/main.c **** return cs; 2466:Src/main.c **** } 2467:Src/main.c **** 2468:Src/main.c **** /*int SD_Init(void) 2469:Src/main.c **** { 2470:Src/main.c **** int test=0; 2471:Src/main.c **** if (HAL_GPIO_ReadPin(SDMMC1_EN_GPIO_Port, SDMMC1_EN_Pin)==GPIO_PIN_RESET) 2472:Src/main.c **** { 2473:Src/main.c **** test = Mount_SD("/"); ARM GAS /tmp/ccqopZd5.s page 142 2474:Src/main.c **** if (test == 0) //0 - suc 2475:Src/main.c **** { 2476:Src/main.c **** //Format_SD(); 2477:Src/main.c **** test = Create_File("FILE1.TXT"); // 0 -suc 2478:Src/main.c **** //Create_File("FILE2.TXT"); 2479:Src/main.c **** Write_File ("FILE1.TXT", "____OSGG main borad information. Program made by Kazakov Viktor. Part 2480:Src/main.c **** test = Unmount_SD("/"); // 0 - succ 2481:Src/main.c **** return test; 2482:Src/main.c **** } 2483:Src/main.c **** else 2484:Src/main.c **** { 2485:Src/main.c **** return 1; 2486:Src/main.c **** } 2487:Src/main.c **** } 2488:Src/main.c **** else 2489:Src/main.c **** { 2490:Src/main.c **** return 1; 2491:Src/main.c **** } 2492:Src/main.c **** }*/ 2493:Src/main.c **** 2494:Src/main.c **** int SD_SAVE(uint16_t *pbuff) 2495:Src/main.c **** { 2496:Src/main.c **** int test=0; 2497:Src/main.c **** if (HAL_GPIO_ReadPin(SDMMC1_EN_GPIO_Port, SDMMC1_EN_Pin)==GPIO_PIN_RESET) 2498:Src/main.c **** { 2499:Src/main.c **** test = Mount_SD("/"); 2500:Src/main.c **** if (test == 0) //0 - suc 2501:Src/main.c **** { 2502:Src/main.c **** //Format_SD(); 2503:Src/main.c **** test = Update_File_byte("FILE1.TXT", (uint8_t *)pbuff, DL_8); 2504:Src/main.c **** test = Unmount_SD("/"); // 0 - succ 2505:Src/main.c **** return test; 2506:Src/main.c **** } 2507:Src/main.c **** else 2508:Src/main.c **** { 2509:Src/main.c **** return 1; 2510:Src/main.c **** } 2511:Src/main.c **** } 2512:Src/main.c **** else 2513:Src/main.c **** { 2514:Src/main.c **** return 1; 2515:Src/main.c **** } 2516:Src/main.c **** } 2517:Src/main.c **** 2518:Src/main.c **** 2519:Src/main.c **** 2520:Src/main.c **** //uint32_t Get_Length(void) 2521:Src/main.c **** //{ 2522:Src/main.c **** // return SD_matr[0][0] + ((uint32_t) (SD_matr[0][1])<<16); 2523:Src/main.c **** //} 2524:Src/main.c **** 2525:Src/main.c **** int SD_READ(uint16_t *pbuff) 2526:Src/main.c **** { 2527:Src/main.c **** int test=0; 2528:Src/main.c **** if (HAL_GPIO_ReadPin(SDMMC1_EN_GPIO_Port, SDMMC1_EN_Pin)==GPIO_PIN_RESET) 2529:Src/main.c **** { 2530:Src/main.c **** test = Mount_SD("/"); ARM GAS /tmp/ccqopZd5.s page 143 2531:Src/main.c **** if (test == 0) //0 - suc 2532:Src/main.c **** { 2533:Src/main.c **** //Format_SD(); 2534:Src/main.c **** test = Seek_Read_File ("FILE1.TXT", (uint8_t *)pbuff, DL_8, fgoto);//Read next 246 bytes 2535:Src/main.c **** fgoto+=DL_8; 2536:Src/main.c **** test = Unmount_SD("/"); // 0 - succ 2537:Src/main.c **** return test; 2538:Src/main.c **** } 2539:Src/main.c **** else 2540:Src/main.c **** { 2541:Src/main.c **** return 1; 2542:Src/main.c **** } 2543:Src/main.c **** } 2544:Src/main.c **** else 2545:Src/main.c **** { 2546:Src/main.c **** return 1; 2547:Src/main.c **** } 2548:Src/main.c **** 2549:Src/main.c **** /* for (uint16_t j = 0; j < DL_16; j++) 2550:Src/main.c **** { 2551:Src/main.c **** *(pbuff+j) = SD_matr[SD_SLIDE][j]; 2552:Src/main.c **** } 2553:Src/main.c **** if (SD_SLIDEAHB1ENR, Periphs) == Periphs); 374:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } 375:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 376:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** 377:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Disable AHB1 peripherals clock. 378:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll AHB1ENR GPIOAEN LL_AHB1_GRP1_DisableClock\n 379:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOBEN LL_AHB1_GRP1_DisableClock\n 380:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOCEN LL_AHB1_GRP1_DisableClock\n 381:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIODEN LL_AHB1_GRP1_DisableClock\n 382:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOEEN LL_AHB1_GRP1_DisableClock\n 383:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOFEN LL_AHB1_GRP1_DisableClock\n 384:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOGEN LL_AHB1_GRP1_DisableClock\n 385:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOHEN LL_AHB1_GRP1_DisableClock\n 386:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOIEN LL_AHB1_GRP1_DisableClock\n 387:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOJEN LL_AHB1_GRP1_DisableClock\n 388:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOKEN LL_AHB1_GRP1_DisableClock\n 389:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR CRCEN LL_AHB1_GRP1_DisableClock\n 390:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR BKPSRAMEN LL_AHB1_GRP1_DisableClock\n 391:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR DTCMRAMEN LL_AHB1_GRP1_DisableClock\n 392:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR DMA1EN LL_AHB1_GRP1_DisableClock\n 393:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR DMA2EN LL_AHB1_GRP1_DisableClock\n 394:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR DMA2DEN LL_AHB1_GRP1_DisableClock\n 395:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR ETHMACEN LL_AHB1_GRP1_DisableClock\n 396:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR ETHMACTXEN LL_AHB1_GRP1_DisableClock\n 397:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR ETHMACRXEN LL_AHB1_GRP1_DisableClock\n 398:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR ETHMACPTPEN LL_AHB1_GRP1_DisableClock\n 399:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR OTGHSEN LL_AHB1_GRP1_DisableClock\n 400:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR OTGHSULPIENDEN LL_AHB1_GRP1_DisableClock 401:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: 402:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA 403:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB 404:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC 405:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD 406:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE 407:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF 408:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG 409:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH 410:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI 411:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*) 412:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*) 413:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRC 414:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM 415:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DTCMRAM 416:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 417:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 418:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*) 419:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*) 420:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*) 421:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*) 422:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACPTP (*) 423:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS 424:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHSULPI ARM GAS /tmp/ccqopZd5.s page 159 425:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * 426:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. 427:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval None 428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ 429:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs) 430:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { 431:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** CLEAR_BIT(RCC->AHB1ENR, Periphs); 432:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } 433:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 434:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** 435:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Force AHB1 peripherals reset. 436:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll AHB1RSTR GPIOARST LL_AHB1_GRP1_ForceReset\n 437:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR GPIOBRST LL_AHB1_GRP1_ForceReset\n 438:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR GPIOCRST LL_AHB1_GRP1_ForceReset\n 439:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR GPIODRST LL_AHB1_GRP1_ForceReset\n 440:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR GPIOERST LL_AHB1_GRP1_ForceReset\n 441:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR GPIOFRST LL_AHB1_GRP1_ForceReset\n 442:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR GPIOGRST LL_AHB1_GRP1_ForceReset\n 443:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR GPIOHRST LL_AHB1_GRP1_ForceReset\n 444:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR GPIOIRST LL_AHB1_GRP1_ForceReset\n 445:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR GPIOJRST LL_AHB1_GRP1_ForceReset\n 446:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR GPIOKRST LL_AHB1_GRP1_ForceReset\n 447:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR CRCRST LL_AHB1_GRP1_ForceReset\n 448:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR DMA1RST LL_AHB1_GRP1_ForceReset\n 449:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR DMA2RST LL_AHB1_GRP1_ForceReset\n 450:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR DMA2DRST LL_AHB1_GRP1_ForceReset\n 451:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR ETHMACRST LL_AHB1_GRP1_ForceReset\n 452:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR OTGHSRST LL_AHB1_GRP1_ForceReset 453:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: 454:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ALL 455:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA 456:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB 457:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC 458:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD 459:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE 460:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF 461:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG 462:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH 463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI 464:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*) 465:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*) 466:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRC 467:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 468:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 469:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*) 470:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*) 471:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS 472:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * 473:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. 474:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval None 475:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ 476:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs) 477:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { 478:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** SET_BIT(RCC->AHB1RSTR, Periphs); 479:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } 480:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 481:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** ARM GAS /tmp/ccqopZd5.s page 160 482:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Release AHB1 peripherals reset. 483:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll AHB1RSTR GPIOARST LL_AHB1_GRP1_ReleaseReset\n 484:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR GPIOBRST LL_AHB1_GRP1_ReleaseReset\n 485:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR GPIOCRST LL_AHB1_GRP1_ReleaseReset\n 486:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR GPIODRST LL_AHB1_GRP1_ReleaseReset\n 487:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR GPIOERST LL_AHB1_GRP1_ReleaseReset\n 488:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR GPIOFRST LL_AHB1_GRP1_ReleaseReset\n 489:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR GPIOGRST LL_AHB1_GRP1_ReleaseReset\n 490:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR GPIOHRST LL_AHB1_GRP1_ReleaseReset\n 491:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR GPIOIRST LL_AHB1_GRP1_ReleaseReset\n 492:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR GPIOJRST LL_AHB1_GRP1_ReleaseReset\n 493:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR GPIOKRST LL_AHB1_GRP1_ReleaseReset\n 494:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR CRCRST LL_AHB1_GRP1_ReleaseReset\n 495:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR DMA1RST LL_AHB1_GRP1_ReleaseReset\n 496:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR DMA2RST LL_AHB1_GRP1_ReleaseReset\n 497:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR DMA2DRST LL_AHB1_GRP1_ReleaseReset\n 498:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR ETHMACRST LL_AHB1_GRP1_ReleaseReset\n 499:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR OTGHSRST LL_AHB1_GRP1_ReleaseReset 500:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: 501:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ALL 502:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA 503:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB 504:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC 505:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD 506:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE 507:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF 508:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG 509:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH 510:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI 511:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*) 512:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*) 513:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRC 514:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 515:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 516:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*) 517:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*) 518:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS 519:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * 520:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. 521:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval None 522:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ 523:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs) 524:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { 525:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** CLEAR_BIT(RCC->AHB1RSTR, Periphs); 526:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } 527:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 528:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** 529:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Enable AHB1 peripheral clocks in low-power mode 530:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll AHB1LPENR GPIOALPEN LL_AHB1_GRP1_EnableClockLowPower\n 531:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR GPIOBLPEN LL_AHB1_GRP1_EnableClockLowPower\n 532:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR GPIOCLPEN LL_AHB1_GRP1_EnableClockLowPower\n 533:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR GPIODLPEN LL_AHB1_GRP1_EnableClockLowPower\n 534:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR GPIOELPEN LL_AHB1_GRP1_EnableClockLowPower\n 535:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR GPIOFLPEN LL_AHB1_GRP1_EnableClockLowPower\n 536:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR GPIOGLPEN LL_AHB1_GRP1_EnableClockLowPower\n 537:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR GPIOHLPEN LL_AHB1_GRP1_EnableClockLowPower\n 538:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR GPIOILPEN LL_AHB1_GRP1_EnableClockLowPower\n ARM GAS /tmp/ccqopZd5.s page 161 539:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR GPIOJLPEN LL_AHB1_GRP1_EnableClockLowPower\n 540:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR GPIOKLPEN LL_AHB1_GRP1_EnableClockLowPower\n 541:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR CRCLPEN LL_AHB1_GRP1_EnableClockLowPower\n 542:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR AXILPEN LL_AHB1_GRP1_EnableClockLowPower\n 543:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR FLITFLPEN LL_AHB1_GRP1_EnableClockLowPower\n 544:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR SRAM1LPEN LL_AHB1_GRP1_EnableClockLowPower\n 545:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR SRAM2LPEN LL_AHB1_GRP1_EnableClockLowPower\n 546:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR BKPSRAMLPEN LL_AHB1_GRP1_EnableClockLowPower\n 547:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR DTCMRAMLPEN LL_AHB1_GRP1_EnableClockLowPower\n 548:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR DMA1LPEN LL_AHB1_GRP1_EnableClockLowPower\n 549:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR DMA2LPEN LL_AHB1_GRP1_EnableClockLowPower\n 550:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR DMA2DLPEN LL_AHB1_GRP1_EnableClockLowPower\n 551:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR ETHMACLPEN LL_AHB1_GRP1_EnableClockLowPower\n 552:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR ETHMACTXLPEN LL_AHB1_GRP1_EnableClockLowPower\n 553:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR ETHMACRXLPEN LL_AHB1_GRP1_EnableClockLowPower\n 554:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR ETHMACPTPLPEN LL_AHB1_GRP1_EnableClockLowPower\n 555:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR OTGHSLPEN LL_AHB1_GRP1_EnableClockLowPower\n 556:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR OTGHSULPILPEN LL_AHB1_GRP1_EnableClockLowPower 557:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: 558:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA 559:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB 560:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC 561:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD 562:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE 563:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF 564:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG 565:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH 566:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI 567:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*) 568:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*) 569:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRC 570:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_AXI 571:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_FLITF 572:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1 573:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM2 574:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM 575:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DTCMRAM 576:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 577:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 578:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*) 579:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*) 580:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*) 581:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*) 582:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACPTP (*) 583:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS 584:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHSULPI 585:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * 586:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. 587:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval None 588:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ 589:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB1_GRP1_EnableClockLowPower(uint32_t Periphs) 590:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { 591:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __IO uint32_t tmpreg; 592:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** SET_BIT(RCC->AHB1LPENR, Periphs); 593:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Delay after an RCC peripheral clock enabling */ 594:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** tmpreg = READ_BIT(RCC->AHB1LPENR, Periphs); 595:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; ARM GAS /tmp/ccqopZd5.s page 162 596:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } 597:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 598:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** 599:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Disable AHB1 peripheral clocks in low-power mode 600:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll AHB1LPENR GPIOALPEN LL_AHB1_GRP1_DisableClockLowPower\n 601:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR GPIOBLPEN LL_AHB1_GRP1_DisableClockLowPower\n 602:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR GPIOCLPEN LL_AHB1_GRP1_DisableClockLowPower\n 603:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR GPIODLPEN LL_AHB1_GRP1_DisableClockLowPower\n 604:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR GPIOELPEN LL_AHB1_GRP1_DisableClockLowPower\n 605:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR GPIOFLPEN LL_AHB1_GRP1_DisableClockLowPower\n 606:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR GPIOGLPEN LL_AHB1_GRP1_DisableClockLowPower\n 607:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR GPIOHLPEN LL_AHB1_GRP1_DisableClockLowPower\n 608:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR GPIOILPEN LL_AHB1_GRP1_DisableClockLowPower\n 609:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR GPIOJLPEN LL_AHB1_GRP1_DisableClockLowPower\n 610:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR GPIOKLPEN LL_AHB1_GRP1_DisableClockLowPower\n 611:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR CRCLPEN LL_AHB1_GRP1_DisableClockLowPower\n 612:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR AXILPEN LL_AHB1_GRP1_DisableClockLowPower\n 613:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR FLITFLPEN LL_AHB1_GRP1_DisableClockLowPower\n 614:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR SRAM1LPEN LL_AHB1_GRP1_DisableClockLowPower\n 615:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR SRAM2LPEN LL_AHB1_GRP1_DisableClockLowPower\n 616:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR BKPSRAMLPEN LL_AHB1_GRP1_DisableClockLowPower\n 617:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR DTCMRAMLPEN LL_AHB1_GRP1_DisableClockLowPower\n 618:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR DMA1LPEN LL_AHB1_GRP1_DisableClockLowPower\n 619:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR DMA2LPEN LL_AHB1_GRP1_DisableClockLowPower\n 620:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR DMA2DLPEN LL_AHB1_GRP1_DisableClockLowPower\n 621:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR ETHMACLPEN LL_AHB1_GRP1_DisableClockLowPower\n 622:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR ETHMACTXLPEN LL_AHB1_GRP1_DisableClockLowPower\n 623:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR ETHMACRXLPEN LL_AHB1_GRP1_DisableClockLowPower\n 624:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR ETHMACPTPLPEN LL_AHB1_GRP1_DisableClockLowPower\n 625:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR OTGHSLPEN LL_AHB1_GRP1_DisableClockLowPower\n 626:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR OTGHSULPILPEN LL_AHB1_GRP1_DisableClockLowPower 627:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: 628:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA 629:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB 630:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC 631:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD 632:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE 633:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF 634:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG 635:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH 636:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI 637:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*) 638:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*) 639:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRC 640:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_AXI 641:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_FLITF 642:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1 643:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM2 644:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM 645:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DTCMRAM 646:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 647:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 648:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*) 649:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*) 650:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*) 651:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*) 652:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACPTP (*) ARM GAS /tmp/ccqopZd5.s page 163 653:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS 654:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHSULPI 655:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * 656:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. 657:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval None 658:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ 659:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB1_GRP1_DisableClockLowPower(uint32_t Periphs) 660:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { 661:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** CLEAR_BIT(RCC->AHB1LPENR, Periphs); 662:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } 663:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 664:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** 665:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @} 666:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ 667:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 668:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** @defgroup BUS_LL_EF_AHB2 AHB2 669:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @{ 670:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ 671:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 672:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** 673:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Enable AHB2 peripherals clock. 674:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll AHB2ENR DCMIEN LL_AHB2_GRP1_EnableClock\n 675:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2ENR JPEGEN LL_AHB2_GRP1_EnableClock\n 676:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2ENR CRYPEN LL_AHB2_GRP1_EnableClock\n 677:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2ENR AESEN LL_AHB2_GRP1_EnableClock\n 678:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2ENR HASHEN LL_AHB2_GRP1_EnableClock\n 679:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2ENR RNGEN LL_AHB2_GRP1_EnableClock\n 680:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2ENR OTGFSEN LL_AHB2_GRP1_EnableClock 681:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: 682:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*) 683:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_JPEG (*) 684:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) 685:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*) 686:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) 687:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_RNG 688:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS 689:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * 690:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. 691:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval None 692:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ 693:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB2_GRP1_EnableClock(uint32_t Periphs) 694:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { 695:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __IO uint32_t tmpreg; 696:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** SET_BIT(RCC->AHB2ENR, Periphs); 697:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Delay after an RCC peripheral clock enabling */ 698:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** tmpreg = READ_BIT(RCC->AHB2ENR, Periphs); 699:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; 700:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } 701:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 702:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** 703:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Check if AHB2 peripheral clock is enabled or not 704:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll AHB2ENR DCMIEN LL_AHB2_GRP1_IsEnabledClock\n 705:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2ENR JPEGEN LL_AHB2_GRP1_IsEnabledClock\n 706:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2ENR CRYPEN LL_AHB2_GRP1_IsEnabledClock\n 707:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2ENR AESEN LL_AHB2_GRP1_IsEnabledClock\n 708:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2ENR HASHEN LL_AHB2_GRP1_IsEnabledClock\n 709:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2ENR RNGEN LL_AHB2_GRP1_IsEnabledClock\n ARM GAS /tmp/ccqopZd5.s page 164 710:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2ENR OTGFSEN LL_AHB2_GRP1_IsEnabledClock 711:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: 712:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*) 713:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_JPEG (*) 714:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) 715:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*) 716:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) 717:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_RNG 718:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS 719:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * 720:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. 721:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval State of Periphs (1 or 0). 722:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ 723:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE uint32_t LL_AHB2_GRP1_IsEnabledClock(uint32_t Periphs) 724:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { 725:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** return (READ_BIT(RCC->AHB2ENR, Periphs) == Periphs); 726:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } 727:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 728:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** 729:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Disable AHB2 peripherals clock. 730:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll AHB2ENR DCMIEN LL_AHB2_GRP1_DisableClock\n 731:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2ENR JPEGEN LL_AHB2_GRP1_DisableClock\n 732:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2ENR CRYPEN LL_AHB2_GRP1_DisableClock\n 733:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2ENR AESEN LL_AHB2_GRP1_DisableClock\n 734:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2ENR HASHEN LL_AHB2_GRP1_DisableClock\n 735:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2ENR RNGEN LL_AHB2_GRP1_DisableClock\n 736:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2ENR OTGFSEN LL_AHB2_GRP1_DisableClock 737:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: 738:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*) 739:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_JPEG (*) 740:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) 741:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*) 742:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) 743:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_RNG 744:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS 745:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * 746:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. 747:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval None 748:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ 749:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB2_GRP1_DisableClock(uint32_t Periphs) 750:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { 751:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** CLEAR_BIT(RCC->AHB2ENR, Periphs); 752:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } 753:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 754:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** 755:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Force AHB2 peripherals reset. 756:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll AHB2RSTR DCMIRST LL_AHB2_GRP1_ForceReset\n 757:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2RSTR JPEGRST LL_AHB2_GRP1_ForceReset\n 758:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2RSTR CRYPRST LL_AHB2_GRP1_ForceReset\n 759:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2RSTR AESRST LL_AHB2_GRP1_ForceReset\n 760:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2RSTR HASHRST LL_AHB2_GRP1_ForceReset\n 761:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2RSTR RNGRST LL_AHB2_GRP1_ForceReset\n 762:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2RSTR OTGFSRST LL_AHB2_GRP1_ForceReset 763:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: 764:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_ALL 765:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*) 766:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_JPEG (*) ARM GAS /tmp/ccqopZd5.s page 165 767:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) 768:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*) 769:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) 770:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_RNG 771:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS 772:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * 773:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. 774:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval None 775:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ 776:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB2_GRP1_ForceReset(uint32_t Periphs) 777:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { 778:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** SET_BIT(RCC->AHB2RSTR, Periphs); 779:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } 780:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 781:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** 782:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Release AHB2 peripherals reset. 783:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll AHB2RSTR DCMIRST LL_AHB2_GRP1_ReleaseReset\n 784:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2RSTR JPEGRST LL_AHB2_GRP1_ReleaseReset\n 785:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2RSTR CRYPRST LL_AHB2_GRP1_ReleaseReset\n 786:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2RSTR AESRST LL_AHB2_GRP1_ReleaseReset\n 787:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2RSTR HASHRST LL_AHB2_GRP1_ReleaseReset\n 788:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2RSTR RNGRST LL_AHB2_GRP1_ReleaseReset\n 789:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2RSTR OTGFSRST LL_AHB2_GRP1_ReleaseReset 790:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: 791:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_ALL 792:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*) 793:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_JPEG (*) 794:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) 795:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*) 796:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) 797:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_RNG 798:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS 799:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * 800:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. 801:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval None 802:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ 803:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB2_GRP1_ReleaseReset(uint32_t Periphs) 804:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { 805:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** CLEAR_BIT(RCC->AHB2RSTR, Periphs); 806:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } 807:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 808:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** 809:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Enable AHB2 peripheral clocks in low-power mode 810:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll AHB2LPENR DCMILPEN LL_AHB2_GRP1_EnableClockLowPower\n 811:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2LPENR JPEGLPEN LL_AHB2_GRP1_EnableClockLowPower\n 812:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2LPENR CRYPLPEN LL_AHB2_GRP1_EnableClockLowPower\n 813:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2LPENR AESLPEN LL_AHB2_GRP1_EnableClockLowPower\n 814:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2LPENR HASHLPEN LL_AHB2_GRP1_EnableClockLowPower\n 815:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2LPENR RNGLPEN LL_AHB2_GRP1_EnableClockLowPower\n 816:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2LPENR OTGFSLPEN LL_AHB2_GRP1_EnableClockLowPower 817:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: 818:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*) 819:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_JPEG (*) 820:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) 821:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*) 822:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) 823:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_RNG ARM GAS /tmp/ccqopZd5.s page 166 824:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS 825:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * 826:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. 827:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval None 828:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ 829:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB2_GRP1_EnableClockLowPower(uint32_t Periphs) 830:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { 831:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __IO uint32_t tmpreg; 832:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** SET_BIT(RCC->AHB2LPENR, Periphs); 833:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Delay after an RCC peripheral clock enabling */ 834:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** tmpreg = READ_BIT(RCC->AHB2LPENR, Periphs); 835:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; 836:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } 837:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 838:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** 839:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Disable AHB2 peripheral clocks in low-power mode 840:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll AHB2LPENR DCMILPEN LL_AHB2_GRP1_DisableClockLowPower\n 841:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2LPENR JPEGLPEN LL_AHB2_GRP1_DisableClockLowPower\n 842:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2LPENR CRYPLPEN LL_AHB2_GRP1_DisableClockLowPower\n 843:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2LPENR AESLPEN LL_AHB2_GRP1_DisableClockLowPower\n 844:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2LPENR HASHLPEN LL_AHB2_GRP1_DisableClockLowPower\n 845:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2LPENR RNGLPEN LL_AHB2_GRP1_DisableClockLowPower\n 846:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2LPENR OTGFSLPEN LL_AHB2_GRP1_DisableClockLowPower 847:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: 848:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*) 849:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_JPEG (*) 850:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) 851:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*) 852:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) 853:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_RNG 854:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS 855:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * 856:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. 857:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval None 858:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ 859:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB2_GRP1_DisableClockLowPower(uint32_t Periphs) 860:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { 861:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** CLEAR_BIT(RCC->AHB2LPENR, Periphs); 862:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } 863:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 864:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** 865:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @} 866:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ 867:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 868:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** @defgroup BUS_LL_EF_AHB3 AHB3 869:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @{ 870:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ 871:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 872:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** 873:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Enable AHB3 peripherals clock. 874:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll AHB3ENR FMCEN LL_AHB3_GRP1_EnableClock\n 875:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB3ENR QSPIEN LL_AHB3_GRP1_EnableClock 876:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: 877:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*) 878:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI 879:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * 880:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. ARM GAS /tmp/ccqopZd5.s page 167 881:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval None 882:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ 883:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB3_GRP1_EnableClock(uint32_t Periphs) 884:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { 885:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __IO uint32_t tmpreg; 886:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** SET_BIT(RCC->AHB3ENR, Periphs); 887:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Delay after an RCC peripheral clock enabling */ 888:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** tmpreg = READ_BIT(RCC->AHB3ENR, Periphs); 889:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; 890:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } 891:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 892:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** 893:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Check if AHB3 peripheral clock is enabled or not 894:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll AHB3ENR FMCEN LL_AHB3_GRP1_IsEnabledClock\n 895:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB3ENR QSPIEN LL_AHB3_GRP1_IsEnabledClock 896:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: 897:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*) 898:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI 899:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * 900:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. 901:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval State of Periphs (1 or 0). 902:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ 903:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE uint32_t LL_AHB3_GRP1_IsEnabledClock(uint32_t Periphs) 904:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { 905:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** return (READ_BIT(RCC->AHB3ENR, Periphs) == Periphs); 906:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 908:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** 909:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Disable AHB3 peripherals clock. 910:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll AHB3ENR FMCEN LL_AHB3_GRP1_DisableClock\n 911:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB3ENR QSPIEN LL_AHB3_GRP1_DisableClock 912:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: 913:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*) 914:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI 915:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * 916:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. 917:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval None 918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ 919:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB3_GRP1_DisableClock(uint32_t Periphs) 920:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { 921:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** CLEAR_BIT(RCC->AHB3ENR, Periphs); 922:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } 923:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 924:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** 925:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Force AHB3 peripherals reset. 926:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll AHB3RSTR FMCRST LL_AHB3_GRP1_ForceReset\n 927:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB3RSTR QSPIRST LL_AHB3_GRP1_ForceReset 928:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: 929:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB3_GRP1_PERIPH_ALL 930:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*) 931:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI 932:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * 933:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. 934:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval None 935:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ 936:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB3_GRP1_ForceReset(uint32_t Periphs) 937:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { ARM GAS /tmp/ccqopZd5.s page 168 938:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** SET_BIT(RCC->AHB3RSTR, Periphs); 939:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } 940:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 941:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** 942:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Release AHB3 peripherals reset. 943:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll AHB3RSTR FMCRST LL_AHB3_GRP1_ReleaseReset\n 944:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB3RSTR QSPIRST LL_AHB3_GRP1_ReleaseReset 945:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: 946:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_ALL 947:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*) 948:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI 949:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * 950:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. 951:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval None 952:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ 953:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB3_GRP1_ReleaseReset(uint32_t Periphs) 954:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { 955:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** CLEAR_BIT(RCC->AHB3RSTR, Periphs); 956:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } 957:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 958:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** 959:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Enable AHB3 peripheral clocks in low-power mode 960:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll AHB3LPENR FMCLPEN LL_AHB3_GRP1_EnableClockLowPower\n 961:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB3LPENR QSPILPEN LL_AHB3_GRP1_EnableClockLowPower 962:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: 963:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*) 964:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI 965:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * 966:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. 967:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval None 968:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ 969:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB3_GRP1_EnableClockLowPower(uint32_t Periphs) 970:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { 971:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __IO uint32_t tmpreg; 972:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** SET_BIT(RCC->AHB3LPENR, Periphs); 973:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Delay after an RCC peripheral clock enabling */ 974:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** tmpreg = READ_BIT(RCC->AHB3LPENR, Periphs); 975:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; 976:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } 977:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 978:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** 979:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Disable AHB3 peripheral clocks in low-power mode 980:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll AHB3LPENR FMCLPEN LL_AHB3_GRP1_DisableClockLowPower\n 981:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB3LPENR QSPILPEN LL_AHB3_GRP1_DisableClockLowPower 982:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: 983:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*) 984:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI 985:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * 986:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. 987:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval None 988:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ 989:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB3_GRP1_DisableClockLowPower(uint32_t Periphs) 990:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { 991:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** CLEAR_BIT(RCC->AHB3LPENR, Periphs); 992:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } 993:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 994:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** ARM GAS /tmp/ccqopZd5.s page 169 995:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @} 996:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ 997:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 998:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** @defgroup BUS_LL_EF_APB1 APB1 999:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @{ 1000:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ 1001:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 1002:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** 1003:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Enable APB1 peripherals clock. 1004:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_EnableClock\n 1005:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR TIM3EN LL_APB1_GRP1_EnableClock\n 1006:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR TIM4EN LL_APB1_GRP1_EnableClock\n 1007:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR TIM5EN LL_APB1_GRP1_EnableClock\n 1008:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR TIM6EN LL_APB1_GRP1_EnableClock\n 1009:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR TIM7EN LL_APB1_GRP1_EnableClock\n 1010:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR TIM12EN LL_APB1_GRP1_EnableClock\n 1011:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR TIM13EN LL_APB1_GRP1_EnableClock\n 1012:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR TIM14EN LL_APB1_GRP1_EnableClock\n 1013:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR LPTIM1EN LL_APB1_GRP1_EnableClock\n 1014:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR WWDGEN LL_APB1_GRP1_EnableClock\n 1015:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR SPI2EN LL_APB1_GRP1_EnableClock\n 1016:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR SPI3EN LL_APB1_GRP1_EnableClock\n 1017:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR SPDIFRXEN LL_APB1_GRP1_EnableClock\n 1018:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR USART2EN LL_APB1_GRP1_EnableClock\n 1019:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR USART3EN LL_APB1_GRP1_EnableClock\n 1020:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR UART4EN LL_APB1_GRP1_EnableClock\n 1021:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR UART5EN LL_APB1_GRP1_EnableClock\n 1022:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR I2C1EN LL_APB1_GRP1_EnableClock\n 1023:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR I2C2EN LL_APB1_GRP1_EnableClock\n 1024:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR I2C3EN LL_APB1_GRP1_EnableClock\n 1025:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR I2C4EN LL_APB1_GRP1_EnableClock\n 1026:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR CAN1EN LL_APB1_GRP1_EnableClock\n 1027:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR CAN2EN LL_APB1_GRP1_EnableClock\n 1028:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR CAN3EN LL_APB1_GRP1_EnableClock\n 1029:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR CECEN LL_APB1_GRP1_EnableClock\n 1030:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR PWREN LL_APB1_GRP1_EnableClock\n 1031:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR DACEN LL_APB1_GRP1_EnableClock\n 1032:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR UART7EN LL_APB1_GRP1_EnableClock\n 1033:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR UART8EN LL_APB1_GRP1_EnableClock\n 1034:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR RTCEN LL_APB1_GRP1_EnableClock 1035:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: 1036:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 1037:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 1038:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 1039:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 1040:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 1041:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 1042:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 1043:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 1044:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 1045:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 1046:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_WWDG 1047:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 1048:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 1049:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*) 1050:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART2 1051:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART3 ARM GAS /tmp/ccqopZd5.s page 170 1052:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART4 1053:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART5 1054:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 1055:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 1056:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 1057:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C4 (*) 1058:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 1059:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*) 1060:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*) 1061:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) 1062:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_PWR 1063:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 1064:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART7 1065:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART8 1066:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*) 1067:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * 1068:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. 1069:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval None 1070:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ 1071:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs) 1072:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { 1073:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __IO uint32_t tmpreg; 1074:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** SET_BIT(RCC->APB1ENR, Periphs); 1075:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Delay after an RCC peripheral clock enabling */ 1076:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** tmpreg = READ_BIT(RCC->APB1ENR, Periphs); 1077:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; 1078:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } 1079:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 1080:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** 1081:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Check if APB1 peripheral clock is enabled or not 1082:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_IsEnabledClock\n 1083:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR TIM3EN LL_APB1_GRP1_IsEnabledClock\n 1084:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR TIM4EN LL_APB1_GRP1_IsEnabledClock\n 1085:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR TIM5EN LL_APB1_GRP1_IsEnabledClock\n 1086:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR TIM6EN LL_APB1_GRP1_IsEnabledClock\n 1087:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR TIM7EN LL_APB1_GRP1_IsEnabledClock\n 1088:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR TIM12EN LL_APB1_GRP1_IsEnabledClock\n 1089:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR TIM13EN LL_APB1_GRP1_IsEnabledClock\n 1090:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR TIM14EN LL_APB1_GRP1_IsEnabledClock\n 1091:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR LPTIM1EN LL_APB1_GRP1_IsEnabledClock\n 1092:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR WWDGEN LL_APB1_GRP1_IsEnabledClock\n 1093:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR SPI2EN LL_APB1_GRP1_IsEnabledClock\n 1094:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR SPI3EN LL_APB1_GRP1_IsEnabledClock\n 1095:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR SPDIFRXEN LL_APB1_GRP1_IsEnabledClock\n 1096:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR USART2EN LL_APB1_GRP1_IsEnabledClock\n 1097:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR USART3EN LL_APB1_GRP1_IsEnabledClock\n 1098:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR UART4EN LL_APB1_GRP1_IsEnabledClock\n 1099:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR UART5EN LL_APB1_GRP1_IsEnabledClock\n 1100:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR I2C1EN LL_APB1_GRP1_IsEnabledClock\n 1101:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR I2C2EN LL_APB1_GRP1_IsEnabledClock\n 1102:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR I2C3EN LL_APB1_GRP1_IsEnabledClock\n 1103:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR I2C4EN LL_APB1_GRP1_IsEnabledClock\n 1104:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR CAN1EN LL_APB1_GRP1_IsEnabledClock\n 1105:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR CAN2EN LL_APB1_GRP1_IsEnabledClock\n 1106:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR CAN3EN LL_APB1_GRP1_IsEnabledClock\n 1107:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR CECEN LL_APB1_GRP1_IsEnabledClock\n 1108:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR PWREN LL_APB1_GRP1_IsEnabledClock\n ARM GAS /tmp/ccqopZd5.s page 171 1109:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR DACEN LL_APB1_GRP1_IsEnabledClock\n 1110:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR UART7EN LL_APB1_GRP1_IsEnabledClock\n 1111:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR UART8EN LL_APB1_GRP1_IsEnabledClock\n 1112:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR RTCEN LL_APB1_GRP1_IsEnabledClock 1113:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: 1114:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 1115:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 1116:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 1117:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 1118:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 1119:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 1120:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 1121:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 1122:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 1123:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 1124:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_WWDG 1125:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 1126:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 1127:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*) 1128:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART2 1129:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART3 1130:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART4 1131:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART5 1132:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 1133:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 1134:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 1135:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C4 (*) 1136:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 1137:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*) 1138:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*) 1139:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) 1140:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_PWR 1141:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 1142:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART7 1143:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART8 1144:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*) 1145:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * 1146:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. 1147:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval State of Periphs (1 or 0). 1148:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ 1149:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs) 1150:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { 1151:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** return (READ_BIT(RCC->APB1ENR, Periphs) == Periphs); 1152:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } 1153:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 1154:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** 1155:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Disable APB1 peripherals clock. 1156:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_DisableClock\n 1157:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR TIM3EN LL_APB1_GRP1_DisableClock\n 1158:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR TIM4EN LL_APB1_GRP1_DisableClock\n 1159:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR TIM5EN LL_APB1_GRP1_DisableClock\n 1160:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR TIM6EN LL_APB1_GRP1_DisableClock\n 1161:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR TIM7EN LL_APB1_GRP1_DisableClock\n 1162:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR TIM12EN LL_APB1_GRP1_DisableClock\n 1163:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR TIM13EN LL_APB1_GRP1_DisableClock\n 1164:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR TIM14EN LL_APB1_GRP1_DisableClock\n 1165:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR LPTIM1EN LL_APB1_GRP1_DisableClock\n ARM GAS /tmp/ccqopZd5.s page 172 1166:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR WWDGEN LL_APB1_GRP1_DisableClock\n 1167:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR SPI2EN LL_APB1_GRP1_DisableClock\n 1168:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR SPI3EN LL_APB1_GRP1_DisableClock\n 1169:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR SPDIFRXEN LL_APB1_GRP1_DisableClock\n 1170:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR USART2EN LL_APB1_GRP1_DisableClock\n 1171:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR USART3EN LL_APB1_GRP1_DisableClock\n 1172:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR UART4EN LL_APB1_GRP1_DisableClock\n 1173:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR UART5EN LL_APB1_GRP1_DisableClock\n 1174:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR I2C1EN LL_APB1_GRP1_DisableClock\n 1175:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR I2C2EN LL_APB1_GRP1_DisableClock\n 1176:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR I2C3EN LL_APB1_GRP1_DisableClock\n 1177:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR I2C4EN LL_APB1_GRP1_DisableClock\n 1178:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR CAN1EN LL_APB1_GRP1_DisableClock\n 1179:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR CAN2EN LL_APB1_GRP1_DisableClock\n 1180:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR CAN3EN LL_APB1_GRP1_DisableClock\n 1181:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR CECEN LL_APB1_GRP1_DisableClock\n 1182:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR PWREN LL_APB1_GRP1_DisableClock\n 1183:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR DACEN LL_APB1_GRP1_DisableClock\n 1184:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR UART7EN LL_APB1_GRP1_DisableClock\n 1185:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR UART8EN LL_APB1_GRP1_DisableClock\n 1186:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR RTCEN LL_APB1_GRP1_DisableClock 1187:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: 1188:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 1189:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 1190:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 1191:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 1192:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 1193:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 1194:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 1195:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 1196:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 1197:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 1198:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_WWDG 1199:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 1200:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 1201:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*) 1202:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART2 1203:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART3 1204:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART4 1205:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART5 1206:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 1207:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 1208:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 1209:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C4 (*) 1210:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 1211:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*) 1212:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*) 1213:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) 1214:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_PWR 1215:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 1216:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART7 1217:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART8 1218:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*) 1219:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * 1220:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. 1221:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval None 1222:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ ARM GAS /tmp/ccqopZd5.s page 173 1223:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_APB1_GRP1_DisableClock(uint32_t Periphs) 1224:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { 1225:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** CLEAR_BIT(RCC->APB1ENR, Periphs); 1226:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } 1227:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 1228:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** 1229:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Force APB1 peripherals reset. 1230:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll APB1RSTR TIM2RST LL_APB1_GRP1_ForceReset\n 1231:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR TIM3RST LL_APB1_GRP1_ForceReset\n 1232:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR TIM4RST LL_APB1_GRP1_ForceReset\n 1233:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR TIM5RST LL_APB1_GRP1_ForceReset\n 1234:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR TIM6RST LL_APB1_GRP1_ForceReset\n 1235:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR TIM7RST LL_APB1_GRP1_ForceReset\n 1236:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR TIM12RST LL_APB1_GRP1_ForceReset\n 1237:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR TIM13RST LL_APB1_GRP1_ForceReset\n 1238:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR TIM14RST LL_APB1_GRP1_ForceReset\n 1239:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR LPTIM1RST LL_APB1_GRP1_ForceReset\n 1240:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR WWDGRST LL_APB1_GRP1_ForceReset\n 1241:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR SPI2RST LL_APB1_GRP1_ForceReset\n 1242:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR SPI3RST LL_APB1_GRP1_ForceReset\n 1243:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR SPDIFRXRST LL_APB1_GRP1_ForceReset\n 1244:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR USART2RST LL_APB1_GRP1_ForceReset\n 1245:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR USART3RST LL_APB1_GRP1_ForceReset\n 1246:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR UART4RST LL_APB1_GRP1_ForceReset\n 1247:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR UART5RST LL_APB1_GRP1_ForceReset\n 1248:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR I2C1RST LL_APB1_GRP1_ForceReset\n 1249:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR I2C2RST LL_APB1_GRP1_ForceReset\n 1250:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR I2C3RST LL_APB1_GRP1_ForceReset\n 1251:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR I2C4RST LL_APB1_GRP1_ForceReset\n 1252:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR CAN1RST LL_APB1_GRP1_ForceReset\n 1253:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR CAN2RST LL_APB1_GRP1_ForceReset\n 1254:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR CAN3RST LL_APB1_GRP1_ForceReset\n 1255:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR CECRST LL_APB1_GRP1_ForceReset\n 1256:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR PWRRST LL_APB1_GRP1_ForceReset\n 1257:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR DACRST LL_APB1_GRP1_ForceReset\n 1258:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR UART7RST LL_APB1_GRP1_ForceReset\n 1259:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR UART8RST LL_APB1_GRP1_ForceReset 1260:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: 1261:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 1262:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 1263:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 1264:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 1265:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 1266:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 1267:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 1268:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 1269:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 1270:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 1271:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_WWDG 1272:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 1273:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 1274:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*) 1275:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART2 1276:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART3 1277:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART4 1278:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART5 1279:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 ARM GAS /tmp/ccqopZd5.s page 174 1280:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 1281:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 1282:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C4 (*) 1283:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 1284:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*) 1285:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*) 1286:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) 1287:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_PWR 1288:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 1289:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART7 1290:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART8 1291:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * 1292:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. 1293:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval None 1294:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ 1295:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_APB1_GRP1_ForceReset(uint32_t Periphs) 1296:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { 1297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** SET_BIT(RCC->APB1RSTR, Periphs); 1298:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } 1299:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 1300:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** 1301:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Release APB1 peripherals reset. 1302:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll APB1RSTR TIM2RST LL_APB1_GRP1_ReleaseReset\n 1303:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR TIM3RST LL_APB1_GRP1_ReleaseReset\n 1304:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR TIM4RST LL_APB1_GRP1_ReleaseReset\n 1305:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR TIM5RST LL_APB1_GRP1_ReleaseReset\n 1306:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR TIM6RST LL_APB1_GRP1_ReleaseReset\n 1307:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR TIM7RST LL_APB1_GRP1_ReleaseReset\n 1308:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR TIM12RST LL_APB1_GRP1_ReleaseReset\n 1309:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR TIM13RST LL_APB1_GRP1_ReleaseReset\n 1310:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR TIM14RST LL_APB1_GRP1_ReleaseReset\n 1311:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR LPTIM1RST LL_APB1_GRP1_ReleaseReset\n 1312:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR WWDGRST LL_APB1_GRP1_ReleaseReset\n 1313:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR SPI2RST LL_APB1_GRP1_ReleaseReset\n 1314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR SPI3RST LL_APB1_GRP1_ReleaseReset\n 1315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR SPDIFRXRST LL_APB1_GRP1_ReleaseReset\n 1316:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR USART2RST LL_APB1_GRP1_ReleaseReset\n 1317:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR USART3RST LL_APB1_GRP1_ReleaseReset\n 1318:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR UART4RST LL_APB1_GRP1_ReleaseReset\n 1319:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR UART5RST LL_APB1_GRP1_ReleaseReset\n 1320:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR I2C1RST LL_APB1_GRP1_ReleaseReset\n 1321:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR I2C2RST LL_APB1_GRP1_ReleaseReset\n 1322:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR I2C3RST LL_APB1_GRP1_ReleaseReset\n 1323:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR I2C4RST LL_APB1_GRP1_ReleaseReset\n 1324:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR CAN1RST LL_APB1_GRP1_ReleaseReset\n 1325:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR CAN2RST LL_APB1_GRP1_ReleaseReset\n 1326:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR CAN3RST LL_APB1_GRP1_ReleaseReset\n 1327:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR CECRST LL_APB1_GRP1_ReleaseReset\n 1328:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR PWRRST LL_APB1_GRP1_ReleaseReset\n 1329:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR DACRST LL_APB1_GRP1_ReleaseReset\n 1330:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR UART7RST LL_APB1_GRP1_ReleaseReset\n 1331:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR UART8RST LL_APB1_GRP1_ReleaseReset 1332:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: 1333:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 1334:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 1335:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 1336:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 ARM GAS /tmp/ccqopZd5.s page 175 1337:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 1338:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 1339:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 1340:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 1341:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 1342:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 1343:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_WWDG 1344:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 1345:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 1346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*) 1347:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART2 1348:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART3 1349:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART4 1350:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART5 1351:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 1352:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 1353:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 1354:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C4 (*) 1355:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 1356:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*) 1357:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*) 1358:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) 1359:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_PWR 1360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 1361:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART7 1362:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART8 1363:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * 1364:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. 1365:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval None 1366:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ 1367:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_APB1_GRP1_ReleaseReset(uint32_t Periphs) 1368:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { 1369:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** CLEAR_BIT(RCC->APB1RSTR, Periphs); 1370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } 1371:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 1372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** 1373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Enable APB1 peripheral clocks in low-power mode 1374:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll APB1LPENR TIM2LPEN LL_APB1_GRP1_EnableClockLowPower\n 1375:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR TIM3LPEN LL_APB1_GRP1_EnableClockLowPower\n 1376:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR TIM4LPEN LL_APB1_GRP1_EnableClockLowPower\n 1377:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR TIM5LPEN LL_APB1_GRP1_EnableClockLowPower\n 1378:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR TIM6LPEN LL_APB1_GRP1_EnableClockLowPower\n 1379:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR TIM7LPEN LL_APB1_GRP1_EnableClockLowPower\n 1380:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR TIM12LPEN LL_APB1_GRP1_EnableClockLowPower\n 1381:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR TIM13LPEN LL_APB1_GRP1_EnableClockLowPower\n 1382:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR TIM14LPEN LL_APB1_GRP1_EnableClockLowPower\n 1383:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR LPTIM1LPEN LL_APB1_GRP1_EnableClockLowPower\n 1384:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR WWDGLPEN LL_APB1_GRP1_EnableClockLowPower\n 1385:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR SPI2LPEN LL_APB1_GRP1_EnableClockLowPower\n 1386:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR SPI3LPEN LL_APB1_GRP1_EnableClockLowPower\n 1387:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR SPDIFRXLPEN LL_APB1_GRP1_EnableClockLowPower\n 1388:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR USART2LPEN LL_APB1_GRP1_EnableClockLowPower\n 1389:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR USART3LPEN LL_APB1_GRP1_EnableClockLowPower\n 1390:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR UART4LPEN LL_APB1_GRP1_EnableClockLowPower\n 1391:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR UART5LPEN LL_APB1_GRP1_EnableClockLowPower\n 1392:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR I2C1LPEN LL_APB1_GRP1_EnableClockLowPower\n 1393:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR I2C2LPEN LL_APB1_GRP1_EnableClockLowPower\n ARM GAS /tmp/ccqopZd5.s page 176 1394:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR I2C3LPEN LL_APB1_GRP1_EnableClockLowPower\n 1395:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR I2C4LPEN LL_APB1_GRP1_EnableClockLowPower\n 1396:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR CAN1LPEN LL_APB1_GRP1_EnableClockLowPower\n 1397:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR CAN2LPEN LL_APB1_GRP1_EnableClockLowPower\n 1398:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR CAN3LPEN LL_APB1_GRP1_EnableClockLowPower\n 1399:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR CECLPEN LL_APB1_GRP1_EnableClockLowPower\n 1400:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR PWRLPEN LL_APB1_GRP1_EnableClockLowPower\n 1401:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR DACLPEN LL_APB1_GRP1_EnableClockLowPower\n 1402:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR UART7LPEN LL_APB1_GRP1_EnableClockLowPower\n 1403:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR UART8LPEN LL_APB1_GRP1_EnableClockLowPower\n 1404:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR RTCLPEN LL_APB1_GRP1_EnableClockLowPower 1405:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: 1406:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 1407:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 1408:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 1409:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 1410:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 1411:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 1412:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 1413:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 1414:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 1415:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 1416:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_WWDG 1417:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 1418:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 1419:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*) 1420:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART2 1421:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART3 1422:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART4 1423:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART5 1424:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 1425:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 1426:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 1427:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C4 (*) 1428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 1429:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*) 1430:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*) 1431:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) 1432:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_PWR 1433:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 1434:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART7 1435:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART8 1436:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*) 1437:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * 1438:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. 1439:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval None 1440:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ 1441:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_APB1_GRP1_EnableClockLowPower(uint32_t Periphs) 1442:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { 1443:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __IO uint32_t tmpreg; 1444:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** SET_BIT(RCC->APB1LPENR, Periphs); 1445:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Delay after an RCC peripheral clock enabling */ 1446:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** tmpreg = READ_BIT(RCC->APB1LPENR, Periphs); 1447:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; 1448:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } 1449:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 1450:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** ARM GAS /tmp/ccqopZd5.s page 177 1451:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Disable APB1 peripheral clocks in low-power mode 1452:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll APB1LPENR TIM2LPEN LL_APB1_GRP1_DisableClockLowPower\n 1453:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR TIM3LPEN LL_APB1_GRP1_DisableClockLowPower\n 1454:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR TIM4LPEN LL_APB1_GRP1_DisableClockLowPower\n 1455:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR TIM5LPEN LL_APB1_GRP1_DisableClockLowPower\n 1456:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR TIM6LPEN LL_APB1_GRP1_DisableClockLowPower\n 1457:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR TIM7LPEN LL_APB1_GRP1_DisableClockLowPower\n 1458:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR TIM12LPEN LL_APB1_GRP1_DisableClockLowPower\n 1459:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR TIM13LPEN LL_APB1_GRP1_DisableClockLowPower\n 1460:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR TIM14LPEN LL_APB1_GRP1_DisableClockLowPower\n 1461:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR LPTIM1LPEN LL_APB1_GRP1_DisableClockLowPower\n 1462:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR WWDGLPEN LL_APB1_GRP1_DisableClockLowPower\n 1463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR SPI2LPEN LL_APB1_GRP1_DisableClockLowPower\n 1464:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR SPI3LPEN LL_APB1_GRP1_DisableClockLowPower\n 1465:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR SPDIFRXLPEN LL_APB1_GRP1_DisableClockLowPower\n 1466:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR USART2LPEN LL_APB1_GRP1_DisableClockLowPower\n 1467:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR USART3LPEN LL_APB1_GRP1_DisableClockLowPower\n 1468:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR UART4LPEN LL_APB1_GRP1_DisableClockLowPower\n 1469:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR UART5LPEN LL_APB1_GRP1_DisableClockLowPower\n 1470:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR I2C1LPEN LL_APB1_GRP1_DisableClockLowPower\n 1471:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR I2C2LPEN LL_APB1_GRP1_DisableClockLowPower\n 1472:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR I2C3LPEN LL_APB1_GRP1_DisableClockLowPower\n 1473:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR I2C4LPEN LL_APB1_GRP1_DisableClockLowPower\n 1474:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR CAN1LPEN LL_APB1_GRP1_DisableClockLowPower\n 1475:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR CAN2LPEN LL_APB1_GRP1_DisableClockLowPower\n 1476:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR CAN3LPEN LL_APB1_GRP1_DisableClockLowPower\n 1477:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR CECLPEN LL_APB1_GRP1_DisableClockLowPower\n 1478:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR PWRLPEN LL_APB1_GRP1_DisableClockLowPower\n 1479:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR DACLPEN LL_APB1_GRP1_DisableClockLowPower\n 1480:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR UART7LPEN LL_APB1_GRP1_DisableClockLowPower\n 1481:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR UART8LPEN LL_APB1_GRP1_DisableClockLowPower\n 1482:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR RTCLPEN LL_APB1_GRP1_DisableClockLowPower 1483:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: 1484:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 1485:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 1486:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 1487:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 1488:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 1489:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 1490:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 1491:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 1492:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 1493:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 1494:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_WWDG 1495:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 1496:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 1497:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*) 1498:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART2 1499:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART3 1500:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART4 1501:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART5 1502:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 1503:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 1504:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 1505:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C4 (*) 1506:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 1507:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*) ARM GAS /tmp/ccqopZd5.s page 178 1508:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*) 1509:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) 1510:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_PWR 1511:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 1512:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART7 1513:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART8 1514:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*) 1515:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * 1516:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. 1517:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval None 1518:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ 1519:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_APB1_GRP1_DisableClockLowPower(uint32_t Periphs) 1520:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { 1521:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** CLEAR_BIT(RCC->APB1LPENR, Periphs); 1522:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } 1523:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 1524:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** 1525:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @} 1526:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ 1527:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 1528:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** @defgroup BUS_LL_EF_APB2 APB2 1529:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @{ 1530:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ 1531:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 1532:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** 1533:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Enable APB2 peripherals clock. 1534:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll APB2ENR TIM1EN LL_APB2_GRP1_EnableClock\n 1535:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR TIM8EN LL_APB2_GRP1_EnableClock\n 1536:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR USART1EN LL_APB2_GRP1_EnableClock\n 1537:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR USART6EN LL_APB2_GRP1_EnableClock\n 1538:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR ADC1EN LL_APB2_GRP1_EnableClock\n 1539:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR ADC2EN LL_APB2_GRP1_EnableClock\n 1540:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR ADC3EN LL_APB2_GRP1_EnableClock\n 1541:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR SDMMC1EN LL_APB2_GRP1_EnableClock\n 1542:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR SDMMC2EN LL_APB2_GRP1_EnableClock\n 1543:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR SPI1EN LL_APB2_GRP1_EnableClock\n 1544:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR SPI4EN LL_APB2_GRP1_EnableClock\n 1545:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR SYSCFGEN LL_APB2_GRP1_EnableClock\n 1546:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR TIM9EN LL_APB2_GRP1_EnableClock\n 1547:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR TIM10EN LL_APB2_GRP1_EnableClock\n 1548:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR TIM11EN LL_APB2_GRP1_EnableClock\n 1549:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR SPI5EN LL_APB2_GRP1_EnableClock\n 1550:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR SPI6EN LL_APB2_GRP1_EnableClock\n 1551:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR SAI1EN LL_APB2_GRP1_EnableClock\n 1552:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR SAI2EN LL_APB2_GRP1_EnableClock\n 1553:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR LTDCEN LL_APB2_GRP1_EnableClock\n 1554:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR DSIEN LL_APB2_GRP1_EnableClock\n 1555:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR DFSDM1EN LL_APB2_GRP1_EnableClock\n 1556:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR MDIOEN LL_APB2_GRP1_EnableClock\n 1557:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR OTGPHYCEN LL_APB2_GRP1_EnableClock 1558:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: 1559:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 1560:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 1561:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_USART1 1562:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_USART6 1563:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_ADC1 1564:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_ADC2 ARM GAS /tmp/ccqopZd5.s page 179 1565:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_ADC3 1566:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1 1567:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC2 (*) 1568:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 1569:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 1570:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG 1571:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_TIM9 1572:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_TIM10 1573:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_TIM11 1574:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 1575:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*) 1576:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 1577:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 1578:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*) 1579:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*) 1580:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*) 1581:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_MDIO (*) 1582:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_OTGPHYC (*) 1583:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * 1584:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. 1585:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval None 1586:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ 1587:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_APB2_GRP1_EnableClock(uint32_t Periphs) 2139 .loc 3 1587 22 view .LVU688 2140 .LBB343: 1588:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { 1589:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __IO uint32_t tmpreg; 2141 .loc 3 1589 3 view .LVU689 1590:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** SET_BIT(RCC->APB2ENR, Periphs); 2142 .loc 3 1590 3 view .LVU690 2143 001e 2A4B ldr r3, .L100 2144 0020 5A6C ldr r2, [r3, #68] 2145 0022 42F40052 orr r2, r2, #8192 2146 0026 5A64 str r2, [r3, #68] 1591:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Delay after an RCC peripheral clock enabling */ 1592:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** tmpreg = READ_BIT(RCC->APB2ENR, Periphs); 2147 .loc 3 1592 3 view .LVU691 2148 .loc 3 1592 12 is_stmt 0 view .LVU692 2149 0028 5A6C ldr r2, [r3, #68] 2150 002a 02F40052 and r2, r2, #8192 2151 .loc 3 1592 10 view .LVU693 2152 002e 0192 str r2, [sp, #4] 1593:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; 2153 .loc 3 1593 3 is_stmt 1 view .LVU694 2154 0030 019A ldr r2, [sp, #4] 2155 .LVL193: 2156 .loc 3 1593 3 is_stmt 0 view .LVU695 2157 .LBE343: 2158 .LBE342: 991:Src/main.c **** /**SPI4 GPIO Configuration 2159 .loc 2 991 3 is_stmt 1 view .LVU696 2160 .LBB344: 2161 .LBI344: 309:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { 2162 .loc 3 309 22 view .LVU697 2163 .LBB345: 311:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** SET_BIT(RCC->AHB1ENR, Periphs); ARM GAS /tmp/ccqopZd5.s page 180 2164 .loc 3 311 3 view .LVU698 312:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Delay after an RCC peripheral clock enabling */ 2165 .loc 3 312 3 view .LVU699 2166 0032 1A6B ldr r2, [r3, #48] 2167 0034 42F01002 orr r2, r2, #16 2168 0038 1A63 str r2, [r3, #48] 314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; 2169 .loc 3 314 3 view .LVU700 314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; 2170 .loc 3 314 12 is_stmt 0 view .LVU701 2171 003a 1B6B ldr r3, [r3, #48] 2172 003c 03F01003 and r3, r3, #16 314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; 2173 .loc 3 314 10 view .LVU702 2174 0040 0093 str r3, [sp] 315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } 2175 .loc 3 315 3 is_stmt 1 view .LVU703 2176 0042 009B ldr r3, [sp] 2177 .LVL194: 315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } 2178 .loc 3 315 3 is_stmt 0 view .LVU704 2179 .LBE345: 2180 .LBE344: 996:Src/main.c **** GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE; 2181 .loc 2 996 3 is_stmt 1 view .LVU705 996:Src/main.c **** GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE; 2182 .loc 2 996 23 is_stmt 0 view .LVU706 2183 0044 4FF48053 mov r3, #4096 2184 0048 0293 str r3, [sp, #8] 997:Src/main.c **** GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH; 2185 .loc 2 997 3 is_stmt 1 view .LVU707 997:Src/main.c **** GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH; 2186 .loc 2 997 24 is_stmt 0 view .LVU708 2187 004a 0225 movs r5, #2 2188 004c 0395 str r5, [sp, #12] 998:Src/main.c **** GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; 2189 .loc 2 998 3 is_stmt 1 view .LVU709 998:Src/main.c **** GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; 2190 .loc 2 998 25 is_stmt 0 view .LVU710 2191 004e 4FF00308 mov r8, #3 2192 0052 CDF81080 str r8, [sp, #16] 999:Src/main.c **** GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; 2193 .loc 2 999 3 is_stmt 1 view .LVU711 1000:Src/main.c **** GPIO_InitStruct.Alternate = LL_GPIO_AF_5; 2194 .loc 2 1000 3 view .LVU712 1001:Src/main.c **** LL_GPIO_Init(GPIOE, &GPIO_InitStruct); 2195 .loc 2 1001 3 view .LVU713 1001:Src/main.c **** LL_GPIO_Init(GPIOE, &GPIO_InitStruct); 2196 .loc 2 1001 29 is_stmt 0 view .LVU714 2197 0056 0527 movs r7, #5 2198 0058 0797 str r7, [sp, #28] 1002:Src/main.c **** 2199 .loc 2 1002 3 is_stmt 1 view .LVU715 2200 005a 1C4E ldr r6, .L100+4 2201 005c 02A9 add r1, sp, #8 2202 005e 3046 mov r0, r6 2203 0060 FFF7FEFF bl LL_GPIO_Init ARM GAS /tmp/ccqopZd5.s page 181 2204 .LVL195: 1004:Src/main.c **** GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE; 2205 .loc 2 1004 3 view .LVU716 1004:Src/main.c **** GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE; 2206 .loc 2 1004 23 is_stmt 0 view .LVU717 2207 0064 4FF40053 mov r3, #8192 2208 0068 0293 str r3, [sp, #8] 1005:Src/main.c **** GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH; 2209 .loc 2 1005 3 is_stmt 1 view .LVU718 1005:Src/main.c **** GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH; 2210 .loc 2 1005 24 is_stmt 0 view .LVU719 2211 006a 0395 str r5, [sp, #12] 1006:Src/main.c **** GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; 2212 .loc 2 1006 3 is_stmt 1 view .LVU720 1006:Src/main.c **** GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; 2213 .loc 2 1006 25 is_stmt 0 view .LVU721 2214 006c CDF81080 str r8, [sp, #16] 1007:Src/main.c **** GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; 2215 .loc 2 1007 3 is_stmt 1 view .LVU722 1007:Src/main.c **** GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; 2216 .loc 2 1007 30 is_stmt 0 view .LVU723 2217 0070 0594 str r4, [sp, #20] 1008:Src/main.c **** GPIO_InitStruct.Alternate = LL_GPIO_AF_5; 2218 .loc 2 1008 3 is_stmt 1 view .LVU724 1008:Src/main.c **** GPIO_InitStruct.Alternate = LL_GPIO_AF_5; 2219 .loc 2 1008 24 is_stmt 0 view .LVU725 2220 0072 0694 str r4, [sp, #24] 1009:Src/main.c **** LL_GPIO_Init(GPIOE, &GPIO_InitStruct); 2221 .loc 2 1009 3 is_stmt 1 view .LVU726 1009:Src/main.c **** LL_GPIO_Init(GPIOE, &GPIO_InitStruct); 2222 .loc 2 1009 29 is_stmt 0 view .LVU727 2223 0074 0797 str r7, [sp, #28] 1010:Src/main.c **** 2224 .loc 2 1010 3 is_stmt 1 view .LVU728 2225 0076 02A9 add r1, sp, #8 2226 0078 3046 mov r0, r6 2227 007a FFF7FEFF bl LL_GPIO_Init 2228 .LVL196: 1016:Src/main.c **** SPI_InitStruct.Mode = LL_SPI_MODE_MASTER; 2229 .loc 2 1016 3 view .LVU729 1016:Src/main.c **** SPI_InitStruct.Mode = LL_SPI_MODE_MASTER; 2230 .loc 2 1016 36 is_stmt 0 view .LVU730 2231 007e 4FF48063 mov r3, #1024 2232 0082 0893 str r3, [sp, #32] 1017:Src/main.c **** SPI_InitStruct.DataWidth = LL_SPI_DATAWIDTH_16BIT; 2233 .loc 2 1017 3 is_stmt 1 view .LVU731 1017:Src/main.c **** SPI_InitStruct.DataWidth = LL_SPI_DATAWIDTH_16BIT; 2234 .loc 2 1017 23 is_stmt 0 view .LVU732 2235 0084 4FF48273 mov r3, #260 2236 0088 0993 str r3, [sp, #36] 1018:Src/main.c **** SPI_InitStruct.ClockPolarity = LL_SPI_POLARITY_HIGH; 2237 .loc 2 1018 3 is_stmt 1 view .LVU733 1018:Src/main.c **** SPI_InitStruct.ClockPolarity = LL_SPI_POLARITY_HIGH; 2238 .loc 2 1018 28 is_stmt 0 view .LVU734 2239 008a 4FF47063 mov r3, #3840 2240 008e 0A93 str r3, [sp, #40] 1019:Src/main.c **** SPI_InitStruct.ClockPhase = LL_SPI_PHASE_1EDGE; ARM GAS /tmp/ccqopZd5.s page 182 2241 .loc 2 1019 3 is_stmt 1 view .LVU735 1019:Src/main.c **** SPI_InitStruct.ClockPhase = LL_SPI_PHASE_1EDGE; 2242 .loc 2 1019 32 is_stmt 0 view .LVU736 2243 0090 0B95 str r5, [sp, #44] 1020:Src/main.c **** SPI_InitStruct.NSS = LL_SPI_NSS_SOFT; 2244 .loc 2 1020 3 is_stmt 1 view .LVU737 1020:Src/main.c **** SPI_InitStruct.NSS = LL_SPI_NSS_SOFT; 2245 .loc 2 1020 29 is_stmt 0 view .LVU738 2246 0092 0C94 str r4, [sp, #48] 1021:Src/main.c **** SPI_InitStruct.BaudRate = LL_SPI_BAUDRATEPRESCALER_DIV16; 2247 .loc 2 1021 3 is_stmt 1 view .LVU739 1021:Src/main.c **** SPI_InitStruct.BaudRate = LL_SPI_BAUDRATEPRESCALER_DIV16; 2248 .loc 2 1021 22 is_stmt 0 view .LVU740 2249 0094 4FF40073 mov r3, #512 2250 0098 0D93 str r3, [sp, #52] 1022:Src/main.c **** SPI_InitStruct.BitOrder = LL_SPI_MSB_FIRST; 2251 .loc 2 1022 3 is_stmt 1 view .LVU741 1022:Src/main.c **** SPI_InitStruct.BitOrder = LL_SPI_MSB_FIRST; 2252 .loc 2 1022 27 is_stmt 0 view .LVU742 2253 009a 1823 movs r3, #24 2254 009c 0E93 str r3, [sp, #56] 1023:Src/main.c **** SPI_InitStruct.CRCCalculation = LL_SPI_CRCCALCULATION_DISABLE; 2255 .loc 2 1023 3 is_stmt 1 view .LVU743 1023:Src/main.c **** SPI_InitStruct.CRCCalculation = LL_SPI_CRCCALCULATION_DISABLE; 2256 .loc 2 1023 27 is_stmt 0 view .LVU744 2257 009e 0F94 str r4, [sp, #60] 1024:Src/main.c **** SPI_InitStruct.CRCPoly = 7; 2258 .loc 2 1024 3 is_stmt 1 view .LVU745 1024:Src/main.c **** SPI_InitStruct.CRCPoly = 7; 2259 .loc 2 1024 33 is_stmt 0 view .LVU746 2260 00a0 1094 str r4, [sp, #64] 1025:Src/main.c **** LL_SPI_Init(SPI4, &SPI_InitStruct); 2261 .loc 2 1025 3 is_stmt 1 view .LVU747 1025:Src/main.c **** LL_SPI_Init(SPI4, &SPI_InitStruct); 2262 .loc 2 1025 26 is_stmt 0 view .LVU748 2263 00a2 0723 movs r3, #7 2264 00a4 1193 str r3, [sp, #68] 1026:Src/main.c **** LL_SPI_SetStandard(SPI4, LL_SPI_PROTOCOL_MOTOROLA); 2265 .loc 2 1026 3 is_stmt 1 view .LVU749 2266 00a6 0A4C ldr r4, .L100+8 2267 00a8 08A9 add r1, sp, #32 2268 00aa 2046 mov r0, r4 2269 00ac FFF7FEFF bl LL_SPI_Init 2270 .LVL197: 1027:Src/main.c **** LL_SPI_DisableNSSPulseMgt(SPI4); 2271 .loc 2 1027 3 view .LVU750 2272 .LBB346: 2273 .LBI346: 426:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 2274 .loc 4 426 22 view .LVU751 2275 .LBB347: 428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 2276 .loc 4 428 3 view .LVU752 2277 00b0 6368 ldr r3, [r4, #4] 2278 00b2 23F01003 bic r3, r3, #16 2279 00b6 6360 str r3, [r4, #4] 2280 .LVL198: ARM GAS /tmp/ccqopZd5.s page 183 428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 2281 .loc 4 428 3 is_stmt 0 view .LVU753 2282 .LBE347: 2283 .LBE346: 1028:Src/main.c **** /* USER CODE BEGIN SPI4_Init 2 */ 2284 .loc 2 1028 3 is_stmt 1 view .LVU754 2285 .LBB348: 2286 .LBI348: 874:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 2287 .loc 4 874 22 view .LVU755 2288 .LBB349: 876:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 2289 .loc 4 876 3 view .LVU756 2290 00b8 6368 ldr r3, [r4, #4] 2291 00ba 23F00803 bic r3, r3, #8 2292 00be 6360 str r3, [r4, #4] 2293 .LVL199: 876:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 2294 .loc 4 876 3 is_stmt 0 view .LVU757 2295 .LBE349: 2296 .LBE348: 1033:Src/main.c **** 2297 .loc 2 1033 1 view .LVU758 2298 00c0 12B0 add sp, sp, #72 2299 .LCFI16: 2300 .cfi_def_cfa_offset 24 2301 @ sp needed 2302 00c2 BDE8F081 pop {r4, r5, r6, r7, r8, pc} 2303 .L101: 2304 00c6 00BF .align 2 2305 .L100: 2306 00c8 00380240 .word 1073887232 2307 00cc 00100240 .word 1073876992 2308 00d0 00340140 .word 1073820672 2309 .cfi_endproc 2310 .LFE1192: 2312 .section .text.MX_SPI2_Init,"ax",%progbits 2313 .align 1 2314 .syntax unified 2315 .thumb 2316 .thumb_func 2317 .fpu fpv5-d16 2319 MX_SPI2_Init: 2320 .LFB1191: 915:Src/main.c **** 2321 .loc 2 915 1 is_stmt 1 view -0 2322 .cfi_startproc 2323 @ args = 0, pretend = 0, frame = 72 2324 @ frame_needed = 0, uses_anonymous_args = 0 2325 0000 2DE9F041 push {r4, r5, r6, r7, r8, lr} 2326 .LCFI17: 2327 .cfi_def_cfa_offset 24 2328 .cfi_offset 4, -24 2329 .cfi_offset 5, -20 2330 .cfi_offset 6, -16 2331 .cfi_offset 7, -12 2332 .cfi_offset 8, -8 ARM GAS /tmp/ccqopZd5.s page 184 2333 .cfi_offset 14, -4 2334 0004 92B0 sub sp, sp, #72 2335 .LCFI18: 2336 .cfi_def_cfa_offset 96 921:Src/main.c **** 2337 .loc 2 921 3 view .LVU760 921:Src/main.c **** 2338 .loc 2 921 22 is_stmt 0 view .LVU761 2339 0006 2822 movs r2, #40 2340 0008 0021 movs r1, #0 2341 000a 08A8 add r0, sp, #32 2342 000c FFF7FEFF bl memset 2343 .LVL200: 923:Src/main.c **** 2344 .loc 2 923 3 is_stmt 1 view .LVU762 923:Src/main.c **** 2345 .loc 2 923 23 is_stmt 0 view .LVU763 2346 0010 0024 movs r4, #0 2347 0012 0294 str r4, [sp, #8] 2348 0014 0394 str r4, [sp, #12] 2349 0016 0494 str r4, [sp, #16] 2350 0018 0594 str r4, [sp, #20] 2351 001a 0694 str r4, [sp, #24] 2352 001c 0794 str r4, [sp, #28] 926:Src/main.c **** 2353 .loc 2 926 3 is_stmt 1 view .LVU764 2354 .LVL201: 2355 .LBB350: 2356 .LBI350: 1071:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { 2357 .loc 3 1071 22 view .LVU765 2358 .LBB351: 1073:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** SET_BIT(RCC->APB1ENR, Periphs); 2359 .loc 3 1073 3 view .LVU766 1074:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Delay after an RCC peripheral clock enabling */ 2360 .loc 3 1074 3 view .LVU767 2361 001e 294B ldr r3, .L104 2362 0020 1A6C ldr r2, [r3, #64] 2363 0022 42F48042 orr r2, r2, #16384 2364 0026 1A64 str r2, [r3, #64] 1076:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; 2365 .loc 3 1076 3 view .LVU768 1076:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; 2366 .loc 3 1076 12 is_stmt 0 view .LVU769 2367 0028 1A6C ldr r2, [r3, #64] 2368 002a 02F48042 and r2, r2, #16384 1076:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; 2369 .loc 3 1076 10 view .LVU770 2370 002e 0192 str r2, [sp, #4] 1077:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } 2371 .loc 3 1077 3 is_stmt 1 view .LVU771 2372 0030 019A ldr r2, [sp, #4] 2373 .LVL202: 1077:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } 2374 .loc 3 1077 3 is_stmt 0 view .LVU772 2375 .LBE351: 2376 .LBE350: ARM GAS /tmp/ccqopZd5.s page 185 928:Src/main.c **** /**SPI2 GPIO Configuration 2377 .loc 2 928 3 is_stmt 1 view .LVU773 2378 .LBB352: 2379 .LBI352: 309:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { 2380 .loc 3 309 22 view .LVU774 2381 .LBB353: 311:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** SET_BIT(RCC->AHB1ENR, Periphs); 2382 .loc 3 311 3 view .LVU775 312:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Delay after an RCC peripheral clock enabling */ 2383 .loc 3 312 3 view .LVU776 2384 0032 1A6B ldr r2, [r3, #48] 2385 0034 42F00202 orr r2, r2, #2 2386 0038 1A63 str r2, [r3, #48] 314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; 2387 .loc 3 314 3 view .LVU777 314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; 2388 .loc 3 314 12 is_stmt 0 view .LVU778 2389 003a 1B6B ldr r3, [r3, #48] 2390 003c 03F00203 and r3, r3, #2 314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; 2391 .loc 3 314 10 view .LVU779 2392 0040 0093 str r3, [sp] 315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } 2393 .loc 3 315 3 is_stmt 1 view .LVU780 2394 0042 009B ldr r3, [sp] 2395 .LVL203: 315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } 2396 .loc 3 315 3 is_stmt 0 view .LVU781 2397 .LBE353: 2398 .LBE352: 933:Src/main.c **** GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE; 2399 .loc 2 933 3 is_stmt 1 view .LVU782 933:Src/main.c **** GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE; 2400 .loc 2 933 23 is_stmt 0 view .LVU783 2401 0044 4FF40053 mov r3, #8192 2402 0048 0293 str r3, [sp, #8] 934:Src/main.c **** GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH; 2403 .loc 2 934 3 is_stmt 1 view .LVU784 934:Src/main.c **** GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH; 2404 .loc 2 934 24 is_stmt 0 view .LVU785 2405 004a 0225 movs r5, #2 2406 004c 0395 str r5, [sp, #12] 935:Src/main.c **** GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; 2407 .loc 2 935 3 is_stmt 1 view .LVU786 935:Src/main.c **** GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; 2408 .loc 2 935 25 is_stmt 0 view .LVU787 2409 004e 4FF00308 mov r8, #3 2410 0052 CDF81080 str r8, [sp, #16] 936:Src/main.c **** GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; 2411 .loc 2 936 3 is_stmt 1 view .LVU788 937:Src/main.c **** GPIO_InitStruct.Alternate = LL_GPIO_AF_5; 2412 .loc 2 937 3 view .LVU789 938:Src/main.c **** LL_GPIO_Init(GPIOB, &GPIO_InitStruct); 2413 .loc 2 938 3 view .LVU790 938:Src/main.c **** LL_GPIO_Init(GPIOB, &GPIO_InitStruct); 2414 .loc 2 938 29 is_stmt 0 view .LVU791 ARM GAS /tmp/ccqopZd5.s page 186 2415 0056 0527 movs r7, #5 2416 0058 0797 str r7, [sp, #28] 939:Src/main.c **** 2417 .loc 2 939 3 is_stmt 1 view .LVU792 2418 005a 1B4E ldr r6, .L104+4 2419 005c 02A9 add r1, sp, #8 2420 005e 3046 mov r0, r6 2421 0060 FFF7FEFF bl LL_GPIO_Init 2422 .LVL204: 941:Src/main.c **** GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE; 2423 .loc 2 941 3 view .LVU793 941:Src/main.c **** GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE; 2424 .loc 2 941 23 is_stmt 0 view .LVU794 2425 0064 4FF40043 mov r3, #32768 2426 0068 0293 str r3, [sp, #8] 942:Src/main.c **** GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH; 2427 .loc 2 942 3 is_stmt 1 view .LVU795 942:Src/main.c **** GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH; 2428 .loc 2 942 24 is_stmt 0 view .LVU796 2429 006a 0395 str r5, [sp, #12] 943:Src/main.c **** GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; 2430 .loc 2 943 3 is_stmt 1 view .LVU797 943:Src/main.c **** GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; 2431 .loc 2 943 25 is_stmt 0 view .LVU798 2432 006c CDF81080 str r8, [sp, #16] 944:Src/main.c **** GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; 2433 .loc 2 944 3 is_stmt 1 view .LVU799 944:Src/main.c **** GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; 2434 .loc 2 944 30 is_stmt 0 view .LVU800 2435 0070 0594 str r4, [sp, #20] 945:Src/main.c **** GPIO_InitStruct.Alternate = LL_GPIO_AF_5; 2436 .loc 2 945 3 is_stmt 1 view .LVU801 945:Src/main.c **** GPIO_InitStruct.Alternate = LL_GPIO_AF_5; 2437 .loc 2 945 24 is_stmt 0 view .LVU802 2438 0072 0694 str r4, [sp, #24] 946:Src/main.c **** LL_GPIO_Init(GPIOB, &GPIO_InitStruct); 2439 .loc 2 946 3 is_stmt 1 view .LVU803 946:Src/main.c **** LL_GPIO_Init(GPIOB, &GPIO_InitStruct); 2440 .loc 2 946 29 is_stmt 0 view .LVU804 2441 0074 0797 str r7, [sp, #28] 947:Src/main.c **** 2442 .loc 2 947 3 is_stmt 1 view .LVU805 2443 0076 02A9 add r1, sp, #8 2444 0078 3046 mov r0, r6 2445 007a FFF7FEFF bl LL_GPIO_Init 2446 .LVL205: 953:Src/main.c **** SPI_InitStruct.Mode = LL_SPI_MODE_MASTER; 2447 .loc 2 953 3 view .LVU806 953:Src/main.c **** SPI_InitStruct.Mode = LL_SPI_MODE_MASTER; 2448 .loc 2 953 36 is_stmt 0 view .LVU807 2449 007e 0894 str r4, [sp, #32] 954:Src/main.c **** SPI_InitStruct.DataWidth = LL_SPI_DATAWIDTH_16BIT; 2450 .loc 2 954 3 is_stmt 1 view .LVU808 954:Src/main.c **** SPI_InitStruct.DataWidth = LL_SPI_DATAWIDTH_16BIT; 2451 .loc 2 954 23 is_stmt 0 view .LVU809 2452 0080 4FF48273 mov r3, #260 2453 0084 0993 str r3, [sp, #36] ARM GAS /tmp/ccqopZd5.s page 187 955:Src/main.c **** SPI_InitStruct.ClockPolarity = LL_SPI_POLARITY_HIGH; 2454 .loc 2 955 3 is_stmt 1 view .LVU810 955:Src/main.c **** SPI_InitStruct.ClockPolarity = LL_SPI_POLARITY_HIGH; 2455 .loc 2 955 28 is_stmt 0 view .LVU811 2456 0086 4FF47063 mov r3, #3840 2457 008a 0A93 str r3, [sp, #40] 956:Src/main.c **** SPI_InitStruct.ClockPhase = LL_SPI_PHASE_2EDGE; 2458 .loc 2 956 3 is_stmt 1 view .LVU812 956:Src/main.c **** SPI_InitStruct.ClockPhase = LL_SPI_PHASE_2EDGE; 2459 .loc 2 956 32 is_stmt 0 view .LVU813 2460 008c 0B95 str r5, [sp, #44] 957:Src/main.c **** SPI_InitStruct.NSS = LL_SPI_NSS_SOFT; 2461 .loc 2 957 3 is_stmt 1 view .LVU814 957:Src/main.c **** SPI_InitStruct.NSS = LL_SPI_NSS_SOFT; 2462 .loc 2 957 29 is_stmt 0 view .LVU815 2463 008e 0123 movs r3, #1 2464 0090 0C93 str r3, [sp, #48] 958:Src/main.c **** SPI_InitStruct.BaudRate = LL_SPI_BAUDRATEPRESCALER_DIV8; 2465 .loc 2 958 3 is_stmt 1 view .LVU816 958:Src/main.c **** SPI_InitStruct.BaudRate = LL_SPI_BAUDRATEPRESCALER_DIV8; 2466 .loc 2 958 22 is_stmt 0 view .LVU817 2467 0092 4FF40073 mov r3, #512 2468 0096 0D93 str r3, [sp, #52] 959:Src/main.c **** SPI_InitStruct.BitOrder = LL_SPI_MSB_FIRST; 2469 .loc 2 959 3 is_stmt 1 view .LVU818 959:Src/main.c **** SPI_InitStruct.BitOrder = LL_SPI_MSB_FIRST; 2470 .loc 2 959 27 is_stmt 0 view .LVU819 2471 0098 1023 movs r3, #16 2472 009a 0E93 str r3, [sp, #56] 960:Src/main.c **** SPI_InitStruct.CRCCalculation = LL_SPI_CRCCALCULATION_DISABLE; 2473 .loc 2 960 3 is_stmt 1 view .LVU820 960:Src/main.c **** SPI_InitStruct.CRCCalculation = LL_SPI_CRCCALCULATION_DISABLE; 2474 .loc 2 960 27 is_stmt 0 view .LVU821 2475 009c 0F94 str r4, [sp, #60] 961:Src/main.c **** SPI_InitStruct.CRCPoly = 7; 2476 .loc 2 961 3 is_stmt 1 view .LVU822 961:Src/main.c **** SPI_InitStruct.CRCPoly = 7; 2477 .loc 2 961 33 is_stmt 0 view .LVU823 2478 009e 1094 str r4, [sp, #64] 962:Src/main.c **** LL_SPI_Init(SPI2, &SPI_InitStruct); 2479 .loc 2 962 3 is_stmt 1 view .LVU824 962:Src/main.c **** LL_SPI_Init(SPI2, &SPI_InitStruct); 2480 .loc 2 962 26 is_stmt 0 view .LVU825 2481 00a0 0723 movs r3, #7 2482 00a2 1193 str r3, [sp, #68] 963:Src/main.c **** LL_SPI_SetStandard(SPI2, LL_SPI_PROTOCOL_MOTOROLA); 2483 .loc 2 963 3 is_stmt 1 view .LVU826 2484 00a4 094C ldr r4, .L104+8 2485 00a6 08A9 add r1, sp, #32 2486 00a8 2046 mov r0, r4 2487 00aa FFF7FEFF bl LL_SPI_Init 2488 .LVL206: 964:Src/main.c **** LL_SPI_DisableNSSPulseMgt(SPI2); 2489 .loc 2 964 3 view .LVU827 2490 .LBB354: 2491 .LBI354: 426:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { ARM GAS /tmp/ccqopZd5.s page 188 2492 .loc 4 426 22 view .LVU828 2493 .LBB355: 428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 2494 .loc 4 428 3 view .LVU829 2495 00ae 6368 ldr r3, [r4, #4] 2496 00b0 23F01003 bic r3, r3, #16 2497 00b4 6360 str r3, [r4, #4] 2498 .LVL207: 428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 2499 .loc 4 428 3 is_stmt 0 view .LVU830 2500 .LBE355: 2501 .LBE354: 965:Src/main.c **** /* USER CODE BEGIN SPI2_Init 2 */ 2502 .loc 2 965 3 is_stmt 1 view .LVU831 2503 .LBB356: 2504 .LBI356: 874:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 2505 .loc 4 874 22 view .LVU832 2506 .LBB357: 876:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 2507 .loc 4 876 3 view .LVU833 2508 00b6 6368 ldr r3, [r4, #4] 2509 00b8 23F00803 bic r3, r3, #8 2510 00bc 6360 str r3, [r4, #4] 2511 .LVL208: 876:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 2512 .loc 4 876 3 is_stmt 0 view .LVU834 2513 .LBE357: 2514 .LBE356: 970:Src/main.c **** 2515 .loc 2 970 1 view .LVU835 2516 00be 12B0 add sp, sp, #72 2517 .LCFI19: 2518 .cfi_def_cfa_offset 24 2519 @ sp needed 2520 00c0 BDE8F081 pop {r4, r5, r6, r7, r8, pc} 2521 .L105: 2522 .align 2 2523 .L104: 2524 00c4 00380240 .word 1073887232 2525 00c8 00040240 .word 1073873920 2526 00cc 00380040 .word 1073756160 2527 .cfi_endproc 2528 .LFE1191: 2530 .section .text.MX_SPI5_Init,"ax",%progbits 2531 .align 1 2532 .syntax unified 2533 .thumb 2534 .thumb_func 2535 .fpu fpv5-d16 2537 MX_SPI5_Init: 2538 .LFB1193: 1041:Src/main.c **** 2539 .loc 2 1041 1 is_stmt 1 view -0 2540 .cfi_startproc 2541 @ args = 0, pretend = 0, frame = 72 2542 @ frame_needed = 0, uses_anonymous_args = 0 ARM GAS /tmp/ccqopZd5.s page 189 2543 0000 2DE9F041 push {r4, r5, r6, r7, r8, lr} 2544 .LCFI20: 2545 .cfi_def_cfa_offset 24 2546 .cfi_offset 4, -24 2547 .cfi_offset 5, -20 2548 .cfi_offset 6, -16 2549 .cfi_offset 7, -12 2550 .cfi_offset 8, -8 2551 .cfi_offset 14, -4 2552 0004 92B0 sub sp, sp, #72 2553 .LCFI21: 2554 .cfi_def_cfa_offset 96 1047:Src/main.c **** 2555 .loc 2 1047 3 view .LVU837 1047:Src/main.c **** 2556 .loc 2 1047 22 is_stmt 0 view .LVU838 2557 0006 2822 movs r2, #40 2558 0008 0021 movs r1, #0 2559 000a 08A8 add r0, sp, #32 2560 000c FFF7FEFF bl memset 2561 .LVL209: 1049:Src/main.c **** 2562 .loc 2 1049 3 is_stmt 1 view .LVU839 1049:Src/main.c **** 2563 .loc 2 1049 23 is_stmt 0 view .LVU840 2564 0010 0024 movs r4, #0 2565 0012 0294 str r4, [sp, #8] 2566 0014 0394 str r4, [sp, #12] 2567 0016 0494 str r4, [sp, #16] 2568 0018 0594 str r4, [sp, #20] 2569 001a 0694 str r4, [sp, #24] 2570 001c 0794 str r4, [sp, #28] 1052:Src/main.c **** 2571 .loc 2 1052 3 is_stmt 1 view .LVU841 2572 .LVL210: 2573 .LBB358: 2574 .LBI358: 1587:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { 2575 .loc 3 1587 22 view .LVU842 2576 .LBB359: 1589:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** SET_BIT(RCC->APB2ENR, Periphs); 2577 .loc 3 1589 3 view .LVU843 1590:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Delay after an RCC peripheral clock enabling */ 2578 .loc 3 1590 3 view .LVU844 2579 001e 294B ldr r3, .L108 2580 0020 5A6C ldr r2, [r3, #68] 2581 0022 42F48012 orr r2, r2, #1048576 2582 0026 5A64 str r2, [r3, #68] 1592:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; 2583 .loc 3 1592 3 view .LVU845 1592:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; 2584 .loc 3 1592 12 is_stmt 0 view .LVU846 2585 0028 5A6C ldr r2, [r3, #68] 2586 002a 02F48012 and r2, r2, #1048576 1592:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; 2587 .loc 3 1592 10 view .LVU847 2588 002e 0192 str r2, [sp, #4] ARM GAS /tmp/ccqopZd5.s page 190 2589 .loc 3 1593 3 is_stmt 1 view .LVU848 2590 0030 019A ldr r2, [sp, #4] 2591 .LVL211: 2592 .loc 3 1593 3 is_stmt 0 view .LVU849 2593 .LBE359: 2594 .LBE358: 1054:Src/main.c **** /**SPI5 GPIO Configuration 2595 .loc 2 1054 3 is_stmt 1 view .LVU850 2596 .LBB360: 2597 .LBI360: 309:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { 2598 .loc 3 309 22 view .LVU851 2599 .LBB361: 311:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** SET_BIT(RCC->AHB1ENR, Periphs); 2600 .loc 3 311 3 view .LVU852 312:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Delay after an RCC peripheral clock enabling */ 2601 .loc 3 312 3 view .LVU853 2602 0032 1A6B ldr r2, [r3, #48] 2603 0034 42F02002 orr r2, r2, #32 2604 0038 1A63 str r2, [r3, #48] 314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; 2605 .loc 3 314 3 view .LVU854 314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; 2606 .loc 3 314 12 is_stmt 0 view .LVU855 2607 003a 1B6B ldr r3, [r3, #48] 2608 003c 03F02003 and r3, r3, #32 314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; 2609 .loc 3 314 10 view .LVU856 2610 0040 0093 str r3, [sp] 315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } 2611 .loc 3 315 3 is_stmt 1 view .LVU857 2612 0042 009B ldr r3, [sp] 2613 .LVL212: 315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } 2614 .loc 3 315 3 is_stmt 0 view .LVU858 2615 .LBE361: 2616 .LBE360: 1059:Src/main.c **** GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE; 2617 .loc 2 1059 3 is_stmt 1 view .LVU859 1059:Src/main.c **** GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE; 2618 .loc 2 1059 23 is_stmt 0 view .LVU860 2619 0044 8023 movs r3, #128 2620 0046 0293 str r3, [sp, #8] 1060:Src/main.c **** GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH; 2621 .loc 2 1060 3 is_stmt 1 view .LVU861 1060:Src/main.c **** GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH; 2622 .loc 2 1060 24 is_stmt 0 view .LVU862 2623 0048 0225 movs r5, #2 2624 004a 0395 str r5, [sp, #12] 1061:Src/main.c **** GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; 2625 .loc 2 1061 3 is_stmt 1 view .LVU863 1061:Src/main.c **** GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; 2626 .loc 2 1061 25 is_stmt 0 view .LVU864 2627 004c 4FF00308 mov r8, #3 2628 0050 CDF81080 str r8, [sp, #16] 1062:Src/main.c **** GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; 2629 .loc 2 1062 3 is_stmt 1 view .LVU865 ARM GAS /tmp/ccqopZd5.s page 191 1063:Src/main.c **** GPIO_InitStruct.Alternate = LL_GPIO_AF_5; 2630 .loc 2 1063 3 view .LVU866 1064:Src/main.c **** LL_GPIO_Init(GPIOF, &GPIO_InitStruct); 2631 .loc 2 1064 3 view .LVU867 1064:Src/main.c **** LL_GPIO_Init(GPIOF, &GPIO_InitStruct); 2632 .loc 2 1064 29 is_stmt 0 view .LVU868 2633 0054 0527 movs r7, #5 2634 0056 0797 str r7, [sp, #28] 1065:Src/main.c **** 2635 .loc 2 1065 3 is_stmt 1 view .LVU869 2636 0058 1B4E ldr r6, .L108+4 2637 005a 02A9 add r1, sp, #8 2638 005c 3046 mov r0, r6 2639 005e FFF7FEFF bl LL_GPIO_Init 2640 .LVL213: 1067:Src/main.c **** GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE; 2641 .loc 2 1067 3 view .LVU870 1067:Src/main.c **** GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE; 2642 .loc 2 1067 23 is_stmt 0 view .LVU871 2643 0062 4FF48073 mov r3, #256 2644 0066 0293 str r3, [sp, #8] 1068:Src/main.c **** GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH; 2645 .loc 2 1068 3 is_stmt 1 view .LVU872 1068:Src/main.c **** GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH; 2646 .loc 2 1068 24 is_stmt 0 view .LVU873 2647 0068 0395 str r5, [sp, #12] 1069:Src/main.c **** GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; 2648 .loc 2 1069 3 is_stmt 1 view .LVU874 1069:Src/main.c **** GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; 2649 .loc 2 1069 25 is_stmt 0 view .LVU875 2650 006a CDF81080 str r8, [sp, #16] 1070:Src/main.c **** GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; 2651 .loc 2 1070 3 is_stmt 1 view .LVU876 1070:Src/main.c **** GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; 2652 .loc 2 1070 30 is_stmt 0 view .LVU877 2653 006e 0594 str r4, [sp, #20] 1071:Src/main.c **** GPIO_InitStruct.Alternate = LL_GPIO_AF_5; 2654 .loc 2 1071 3 is_stmt 1 view .LVU878 1071:Src/main.c **** GPIO_InitStruct.Alternate = LL_GPIO_AF_5; 2655 .loc 2 1071 24 is_stmt 0 view .LVU879 2656 0070 0694 str r4, [sp, #24] 1072:Src/main.c **** LL_GPIO_Init(GPIOF, &GPIO_InitStruct); 2657 .loc 2 1072 3 is_stmt 1 view .LVU880 1072:Src/main.c **** LL_GPIO_Init(GPIOF, &GPIO_InitStruct); 2658 .loc 2 1072 29 is_stmt 0 view .LVU881 2659 0072 0797 str r7, [sp, #28] 1073:Src/main.c **** 2660 .loc 2 1073 3 is_stmt 1 view .LVU882 2661 0074 02A9 add r1, sp, #8 2662 0076 3046 mov r0, r6 2663 0078 FFF7FEFF bl LL_GPIO_Init 2664 .LVL214: 1079:Src/main.c **** SPI_InitStruct.Mode = LL_SPI_MODE_MASTER; 2665 .loc 2 1079 3 view .LVU883 1079:Src/main.c **** SPI_InitStruct.Mode = LL_SPI_MODE_MASTER; 2666 .loc 2 1079 36 is_stmt 0 view .LVU884 2667 007c 4FF48063 mov r3, #1024 ARM GAS /tmp/ccqopZd5.s page 192 2668 0080 0893 str r3, [sp, #32] 1080:Src/main.c **** SPI_InitStruct.DataWidth = LL_SPI_DATAWIDTH_16BIT; 2669 .loc 2 1080 3 is_stmt 1 view .LVU885 1080:Src/main.c **** SPI_InitStruct.DataWidth = LL_SPI_DATAWIDTH_16BIT; 2670 .loc 2 1080 23 is_stmt 0 view .LVU886 2671 0082 4FF48273 mov r3, #260 2672 0086 0993 str r3, [sp, #36] 1081:Src/main.c **** SPI_InitStruct.ClockPolarity = LL_SPI_POLARITY_HIGH; 2673 .loc 2 1081 3 is_stmt 1 view .LVU887 1081:Src/main.c **** SPI_InitStruct.ClockPolarity = LL_SPI_POLARITY_HIGH; 2674 .loc 2 1081 28 is_stmt 0 view .LVU888 2675 0088 4FF47063 mov r3, #3840 2676 008c 0A93 str r3, [sp, #40] 1082:Src/main.c **** SPI_InitStruct.ClockPhase = LL_SPI_PHASE_1EDGE; 2677 .loc 2 1082 3 is_stmt 1 view .LVU889 1082:Src/main.c **** SPI_InitStruct.ClockPhase = LL_SPI_PHASE_1EDGE; 2678 .loc 2 1082 32 is_stmt 0 view .LVU890 2679 008e 0B95 str r5, [sp, #44] 1083:Src/main.c **** SPI_InitStruct.NSS = LL_SPI_NSS_SOFT; 2680 .loc 2 1083 3 is_stmt 1 view .LVU891 1083:Src/main.c **** SPI_InitStruct.NSS = LL_SPI_NSS_SOFT; 2681 .loc 2 1083 29 is_stmt 0 view .LVU892 2682 0090 0C94 str r4, [sp, #48] 1084:Src/main.c **** SPI_InitStruct.BaudRate = LL_SPI_BAUDRATEPRESCALER_DIV16; 2683 .loc 2 1084 3 is_stmt 1 view .LVU893 1084:Src/main.c **** SPI_InitStruct.BaudRate = LL_SPI_BAUDRATEPRESCALER_DIV16; 2684 .loc 2 1084 22 is_stmt 0 view .LVU894 2685 0092 4FF40073 mov r3, #512 2686 0096 0D93 str r3, [sp, #52] 1085:Src/main.c **** SPI_InitStruct.BitOrder = LL_SPI_MSB_FIRST; 2687 .loc 2 1085 3 is_stmt 1 view .LVU895 1085:Src/main.c **** SPI_InitStruct.BitOrder = LL_SPI_MSB_FIRST; 2688 .loc 2 1085 27 is_stmt 0 view .LVU896 2689 0098 1823 movs r3, #24 2690 009a 0E93 str r3, [sp, #56] 1086:Src/main.c **** SPI_InitStruct.CRCCalculation = LL_SPI_CRCCALCULATION_DISABLE; 2691 .loc 2 1086 3 is_stmt 1 view .LVU897 1086:Src/main.c **** SPI_InitStruct.CRCCalculation = LL_SPI_CRCCALCULATION_DISABLE; 2692 .loc 2 1086 27 is_stmt 0 view .LVU898 2693 009c 0F94 str r4, [sp, #60] 1087:Src/main.c **** SPI_InitStruct.CRCPoly = 7; 2694 .loc 2 1087 3 is_stmt 1 view .LVU899 1087:Src/main.c **** SPI_InitStruct.CRCPoly = 7; 2695 .loc 2 1087 33 is_stmt 0 view .LVU900 2696 009e 1094 str r4, [sp, #64] 1088:Src/main.c **** LL_SPI_Init(SPI5, &SPI_InitStruct); 2697 .loc 2 1088 3 is_stmt 1 view .LVU901 1088:Src/main.c **** LL_SPI_Init(SPI5, &SPI_InitStruct); 2698 .loc 2 1088 26 is_stmt 0 view .LVU902 2699 00a0 0723 movs r3, #7 2700 00a2 1193 str r3, [sp, #68] 1089:Src/main.c **** LL_SPI_SetStandard(SPI5, LL_SPI_PROTOCOL_MOTOROLA); 2701 .loc 2 1089 3 is_stmt 1 view .LVU903 2702 00a4 094C ldr r4, .L108+8 2703 00a6 08A9 add r1, sp, #32 2704 00a8 2046 mov r0, r4 2705 00aa FFF7FEFF bl LL_SPI_Init ARM GAS /tmp/ccqopZd5.s page 193 2706 .LVL215: 1090:Src/main.c **** LL_SPI_DisableNSSPulseMgt(SPI5); 2707 .loc 2 1090 3 view .LVU904 2708 .LBB362: 2709 .LBI362: 426:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 2710 .loc 4 426 22 view .LVU905 2711 .LBB363: 428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 2712 .loc 4 428 3 view .LVU906 2713 00ae 6368 ldr r3, [r4, #4] 2714 00b0 23F01003 bic r3, r3, #16 2715 00b4 6360 str r3, [r4, #4] 2716 .LVL216: 428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 2717 .loc 4 428 3 is_stmt 0 view .LVU907 2718 .LBE363: 2719 .LBE362: 1091:Src/main.c **** /* USER CODE BEGIN SPI5_Init 2 */ 2720 .loc 2 1091 3 is_stmt 1 view .LVU908 2721 .LBB364: 2722 .LBI364: 874:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 2723 .loc 4 874 22 view .LVU909 2724 .LBB365: 876:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 2725 .loc 4 876 3 view .LVU910 2726 00b6 6368 ldr r3, [r4, #4] 2727 00b8 23F00803 bic r3, r3, #8 2728 00bc 6360 str r3, [r4, #4] 2729 .LVL217: 876:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 2730 .loc 4 876 3 is_stmt 0 view .LVU911 2731 .LBE365: 2732 .LBE364: 1096:Src/main.c **** 2733 .loc 2 1096 1 view .LVU912 2734 00be 12B0 add sp, sp, #72 2735 .LCFI22: 2736 .cfi_def_cfa_offset 24 2737 @ sp needed 2738 00c0 BDE8F081 pop {r4, r5, r6, r7, r8, pc} 2739 .L109: 2740 .align 2 2741 .L108: 2742 00c4 00380240 .word 1073887232 2743 00c8 00140240 .word 1073878016 2744 00cc 00500140 .word 1073827840 2745 .cfi_endproc 2746 .LFE1193: 2748 .section .text.MX_SPI6_Init,"ax",%progbits 2749 .align 1 2750 .syntax unified 2751 .thumb 2752 .thumb_func 2753 .fpu fpv5-d16 2755 MX_SPI6_Init: ARM GAS /tmp/ccqopZd5.s page 194 2756 .LFB1194: 1104:Src/main.c **** 2757 .loc 2 1104 1 is_stmt 1 view -0 2758 .cfi_startproc 2759 @ args = 0, pretend = 0, frame = 72 2760 @ frame_needed = 0, uses_anonymous_args = 0 2761 0000 2DE9F041 push {r4, r5, r6, r7, r8, lr} 2762 .LCFI23: 2763 .cfi_def_cfa_offset 24 2764 .cfi_offset 4, -24 2765 .cfi_offset 5, -20 2766 .cfi_offset 6, -16 2767 .cfi_offset 7, -12 2768 .cfi_offset 8, -8 2769 .cfi_offset 14, -4 2770 0004 92B0 sub sp, sp, #72 2771 .LCFI24: 2772 .cfi_def_cfa_offset 96 1110:Src/main.c **** 2773 .loc 2 1110 3 view .LVU914 1110:Src/main.c **** 2774 .loc 2 1110 22 is_stmt 0 view .LVU915 2775 0006 2822 movs r2, #40 2776 0008 0021 movs r1, #0 2777 000a 08A8 add r0, sp, #32 2778 000c FFF7FEFF bl memset 2779 .LVL218: 1112:Src/main.c **** 2780 .loc 2 1112 3 is_stmt 1 view .LVU916 1112:Src/main.c **** 2781 .loc 2 1112 23 is_stmt 0 view .LVU917 2782 0010 0024 movs r4, #0 2783 0012 0294 str r4, [sp, #8] 2784 0014 0394 str r4, [sp, #12] 2785 0016 0494 str r4, [sp, #16] 2786 0018 0594 str r4, [sp, #20] 2787 001a 0694 str r4, [sp, #24] 2788 001c 0794 str r4, [sp, #28] 1115:Src/main.c **** 2789 .loc 2 1115 3 is_stmt 1 view .LVU918 2790 .LVL219: 2791 .LBB366: 2792 .LBI366: 1587:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { 2793 .loc 3 1587 22 view .LVU919 2794 .LBB367: 1589:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** SET_BIT(RCC->APB2ENR, Periphs); 2795 .loc 3 1589 3 view .LVU920 1590:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Delay after an RCC peripheral clock enabling */ 2796 .loc 3 1590 3 view .LVU921 2797 001e 294B ldr r3, .L112 2798 0020 5A6C ldr r2, [r3, #68] 2799 0022 42F40012 orr r2, r2, #2097152 2800 0026 5A64 str r2, [r3, #68] 1592:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; 2801 .loc 3 1592 3 view .LVU922 1592:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; ARM GAS /tmp/ccqopZd5.s page 195 2802 .loc 3 1592 12 is_stmt 0 view .LVU923 2803 0028 5A6C ldr r2, [r3, #68] 2804 002a 02F40012 and r2, r2, #2097152 1592:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; 2805 .loc 3 1592 10 view .LVU924 2806 002e 0192 str r2, [sp, #4] 2807 .loc 3 1593 3 is_stmt 1 view .LVU925 2808 0030 019A ldr r2, [sp, #4] 2809 .LVL220: 2810 .loc 3 1593 3 is_stmt 0 view .LVU926 2811 .LBE367: 2812 .LBE366: 1117:Src/main.c **** /**SPI6 GPIO Configuration 2813 .loc 2 1117 3 is_stmt 1 view .LVU927 2814 .LBB368: 2815 .LBI368: 309:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { 2816 .loc 3 309 22 view .LVU928 2817 .LBB369: 311:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** SET_BIT(RCC->AHB1ENR, Periphs); 2818 .loc 3 311 3 view .LVU929 312:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Delay after an RCC peripheral clock enabling */ 2819 .loc 3 312 3 view .LVU930 2820 0032 1A6B ldr r2, [r3, #48] 2821 0034 42F00102 orr r2, r2, #1 2822 0038 1A63 str r2, [r3, #48] 314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; 2823 .loc 3 314 3 view .LVU931 314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; 2824 .loc 3 314 12 is_stmt 0 view .LVU932 2825 003a 1B6B ldr r3, [r3, #48] 2826 003c 03F00103 and r3, r3, #1 314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; 2827 .loc 3 314 10 view .LVU933 2828 0040 0093 str r3, [sp] 315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } 2829 .loc 3 315 3 is_stmt 1 view .LVU934 2830 0042 009B ldr r3, [sp] 2831 .LVL221: 315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } 2832 .loc 3 315 3 is_stmt 0 view .LVU935 2833 .LBE369: 2834 .LBE368: 1122:Src/main.c **** GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE; 2835 .loc 2 1122 3 is_stmt 1 view .LVU936 1122:Src/main.c **** GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE; 2836 .loc 2 1122 23 is_stmt 0 view .LVU937 2837 0044 2023 movs r3, #32 2838 0046 0293 str r3, [sp, #8] 1123:Src/main.c **** GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH; 2839 .loc 2 1123 3 is_stmt 1 view .LVU938 1123:Src/main.c **** GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH; 2840 .loc 2 1123 24 is_stmt 0 view .LVU939 2841 0048 0225 movs r5, #2 2842 004a 0395 str r5, [sp, #12] 1124:Src/main.c **** GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; 2843 .loc 2 1124 3 is_stmt 1 view .LVU940 ARM GAS /tmp/ccqopZd5.s page 196 1124:Src/main.c **** GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; 2844 .loc 2 1124 25 is_stmt 0 view .LVU941 2845 004c 4FF00308 mov r8, #3 2846 0050 CDF81080 str r8, [sp, #16] 1125:Src/main.c **** GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; 2847 .loc 2 1125 3 is_stmt 1 view .LVU942 1126:Src/main.c **** GPIO_InitStruct.Alternate = LL_GPIO_AF_8; 2848 .loc 2 1126 3 view .LVU943 1127:Src/main.c **** LL_GPIO_Init(GPIOA, &GPIO_InitStruct); 2849 .loc 2 1127 3 view .LVU944 1127:Src/main.c **** LL_GPIO_Init(GPIOA, &GPIO_InitStruct); 2850 .loc 2 1127 29 is_stmt 0 view .LVU945 2851 0054 0827 movs r7, #8 2852 0056 0797 str r7, [sp, #28] 1128:Src/main.c **** 2853 .loc 2 1128 3 is_stmt 1 view .LVU946 2854 0058 1B4E ldr r6, .L112+4 2855 005a 0DEB0701 add r1, sp, r7 2856 005e 3046 mov r0, r6 2857 0060 FFF7FEFF bl LL_GPIO_Init 2858 .LVL222: 1130:Src/main.c **** GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE; 2859 .loc 2 1130 3 view .LVU947 1130:Src/main.c **** GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE; 2860 .loc 2 1130 23 is_stmt 0 view .LVU948 2861 0064 8023 movs r3, #128 2862 0066 0293 str r3, [sp, #8] 1131:Src/main.c **** GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH; 2863 .loc 2 1131 3 is_stmt 1 view .LVU949 1131:Src/main.c **** GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH; 2864 .loc 2 1131 24 is_stmt 0 view .LVU950 2865 0068 0395 str r5, [sp, #12] 1132:Src/main.c **** GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; 2866 .loc 2 1132 3 is_stmt 1 view .LVU951 1132:Src/main.c **** GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; 2867 .loc 2 1132 25 is_stmt 0 view .LVU952 2868 006a CDF81080 str r8, [sp, #16] 1133:Src/main.c **** GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; 2869 .loc 2 1133 3 is_stmt 1 view .LVU953 1133:Src/main.c **** GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; 2870 .loc 2 1133 30 is_stmt 0 view .LVU954 2871 006e 0594 str r4, [sp, #20] 1134:Src/main.c **** GPIO_InitStruct.Alternate = LL_GPIO_AF_8; 2872 .loc 2 1134 3 is_stmt 1 view .LVU955 1134:Src/main.c **** GPIO_InitStruct.Alternate = LL_GPIO_AF_8; 2873 .loc 2 1134 24 is_stmt 0 view .LVU956 2874 0070 0694 str r4, [sp, #24] 1135:Src/main.c **** LL_GPIO_Init(GPIOA, &GPIO_InitStruct); 2875 .loc 2 1135 3 is_stmt 1 view .LVU957 1135:Src/main.c **** LL_GPIO_Init(GPIOA, &GPIO_InitStruct); 2876 .loc 2 1135 29 is_stmt 0 view .LVU958 2877 0072 0797 str r7, [sp, #28] 1136:Src/main.c **** 2878 .loc 2 1136 3 is_stmt 1 view .LVU959 2879 0074 0DEB0701 add r1, sp, r7 2880 0078 3046 mov r0, r6 2881 007a FFF7FEFF bl LL_GPIO_Init ARM GAS /tmp/ccqopZd5.s page 197 2882 .LVL223: 1142:Src/main.c **** SPI_InitStruct.Mode = LL_SPI_MODE_MASTER; 2883 .loc 2 1142 3 view .LVU960 1142:Src/main.c **** SPI_InitStruct.Mode = LL_SPI_MODE_MASTER; 2884 .loc 2 1142 36 is_stmt 0 view .LVU961 2885 007e 0894 str r4, [sp, #32] 1143:Src/main.c **** SPI_InitStruct.DataWidth = LL_SPI_DATAWIDTH_16BIT; 2886 .loc 2 1143 3 is_stmt 1 view .LVU962 1143:Src/main.c **** SPI_InitStruct.DataWidth = LL_SPI_DATAWIDTH_16BIT; 2887 .loc 2 1143 23 is_stmt 0 view .LVU963 2888 0080 4FF48273 mov r3, #260 2889 0084 0993 str r3, [sp, #36] 1144:Src/main.c **** SPI_InitStruct.ClockPolarity = LL_SPI_POLARITY_HIGH; 2890 .loc 2 1144 3 is_stmt 1 view .LVU964 1144:Src/main.c **** SPI_InitStruct.ClockPolarity = LL_SPI_POLARITY_HIGH; 2891 .loc 2 1144 28 is_stmt 0 view .LVU965 2892 0086 4FF47063 mov r3, #3840 2893 008a 0A93 str r3, [sp, #40] 1145:Src/main.c **** SPI_InitStruct.ClockPhase = LL_SPI_PHASE_2EDGE; 2894 .loc 2 1145 3 is_stmt 1 view .LVU966 1145:Src/main.c **** SPI_InitStruct.ClockPhase = LL_SPI_PHASE_2EDGE; 2895 .loc 2 1145 32 is_stmt 0 view .LVU967 2896 008c 0B95 str r5, [sp, #44] 1146:Src/main.c **** SPI_InitStruct.NSS = LL_SPI_NSS_SOFT; 2897 .loc 2 1146 3 is_stmt 1 view .LVU968 1146:Src/main.c **** SPI_InitStruct.NSS = LL_SPI_NSS_SOFT; 2898 .loc 2 1146 29 is_stmt 0 view .LVU969 2899 008e 0123 movs r3, #1 2900 0090 0C93 str r3, [sp, #48] 1147:Src/main.c **** SPI_InitStruct.BaudRate = LL_SPI_BAUDRATEPRESCALER_DIV16; 2901 .loc 2 1147 3 is_stmt 1 view .LVU970 1147:Src/main.c **** SPI_InitStruct.BaudRate = LL_SPI_BAUDRATEPRESCALER_DIV16; 2902 .loc 2 1147 22 is_stmt 0 view .LVU971 2903 0092 4FF40073 mov r3, #512 2904 0096 0D93 str r3, [sp, #52] 1148:Src/main.c **** SPI_InitStruct.BitOrder = LL_SPI_MSB_FIRST; 2905 .loc 2 1148 3 is_stmt 1 view .LVU972 1148:Src/main.c **** SPI_InitStruct.BitOrder = LL_SPI_MSB_FIRST; 2906 .loc 2 1148 27 is_stmt 0 view .LVU973 2907 0098 1823 movs r3, #24 2908 009a 0E93 str r3, [sp, #56] 1149:Src/main.c **** SPI_InitStruct.CRCCalculation = LL_SPI_CRCCALCULATION_DISABLE; 2909 .loc 2 1149 3 is_stmt 1 view .LVU974 1149:Src/main.c **** SPI_InitStruct.CRCCalculation = LL_SPI_CRCCALCULATION_DISABLE; 2910 .loc 2 1149 27 is_stmt 0 view .LVU975 2911 009c 0F94 str r4, [sp, #60] 1150:Src/main.c **** SPI_InitStruct.CRCPoly = 7; 2912 .loc 2 1150 3 is_stmt 1 view .LVU976 1150:Src/main.c **** SPI_InitStruct.CRCPoly = 7; 2913 .loc 2 1150 33 is_stmt 0 view .LVU977 2914 009e 1094 str r4, [sp, #64] 1151:Src/main.c **** LL_SPI_Init(SPI6, &SPI_InitStruct); 2915 .loc 2 1151 3 is_stmt 1 view .LVU978 1151:Src/main.c **** LL_SPI_Init(SPI6, &SPI_InitStruct); 2916 .loc 2 1151 26 is_stmt 0 view .LVU979 2917 00a0 0723 movs r3, #7 2918 00a2 1193 str r3, [sp, #68] ARM GAS /tmp/ccqopZd5.s page 198 1152:Src/main.c **** LL_SPI_SetStandard(SPI6, LL_SPI_PROTOCOL_MOTOROLA); 2919 .loc 2 1152 3 is_stmt 1 view .LVU980 2920 00a4 094C ldr r4, .L112+8 2921 00a6 08A9 add r1, sp, #32 2922 00a8 2046 mov r0, r4 2923 00aa FFF7FEFF bl LL_SPI_Init 2924 .LVL224: 1153:Src/main.c **** LL_SPI_DisableNSSPulseMgt(SPI6); 2925 .loc 2 1153 3 view .LVU981 2926 .LBB370: 2927 .LBI370: 426:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 2928 .loc 4 426 22 view .LVU982 2929 .LBB371: 428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 2930 .loc 4 428 3 view .LVU983 2931 00ae 6368 ldr r3, [r4, #4] 2932 00b0 23F01003 bic r3, r3, #16 2933 00b4 6360 str r3, [r4, #4] 2934 .LVL225: 428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 2935 .loc 4 428 3 is_stmt 0 view .LVU984 2936 .LBE371: 2937 .LBE370: 1154:Src/main.c **** /* USER CODE BEGIN SPI6_Init 2 */ 2938 .loc 2 1154 3 is_stmt 1 view .LVU985 2939 .LBB372: 2940 .LBI372: 874:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 2941 .loc 4 874 22 view .LVU986 2942 .LBB373: 876:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 2943 .loc 4 876 3 view .LVU987 2944 00b6 6368 ldr r3, [r4, #4] 2945 00b8 23F00803 bic r3, r3, #8 2946 00bc 6360 str r3, [r4, #4] 2947 .LVL226: 876:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 2948 .loc 4 876 3 is_stmt 0 view .LVU988 2949 .LBE373: 2950 .LBE372: 1159:Src/main.c **** 2951 .loc 2 1159 1 view .LVU989 2952 00be 12B0 add sp, sp, #72 2953 .LCFI25: 2954 .cfi_def_cfa_offset 24 2955 @ sp needed 2956 00c0 BDE8F081 pop {r4, r5, r6, r7, r8, pc} 2957 .L113: 2958 .align 2 2959 .L112: 2960 00c4 00380240 .word 1073887232 2961 00c8 00000240 .word 1073872896 2962 00cc 00540140 .word 1073828864 2963 .cfi_endproc 2964 .LFE1194: 2966 .section .text.MX_TIM2_Init,"ax",%progbits ARM GAS /tmp/ccqopZd5.s page 199 2967 .align 1 2968 .syntax unified 2969 .thumb 2970 .thumb_func 2971 .fpu fpv5-d16 2973 MX_TIM2_Init: 2974 .LFB1195: 1167:Src/main.c **** 2975 .loc 2 1167 1 is_stmt 1 view -0 2976 .cfi_startproc 2977 @ args = 0, pretend = 0, frame = 24 2978 @ frame_needed = 0, uses_anonymous_args = 0 2979 0000 10B5 push {r4, lr} 2980 .LCFI26: 2981 .cfi_def_cfa_offset 8 2982 .cfi_offset 4, -8 2983 .cfi_offset 14, -4 2984 0002 86B0 sub sp, sp, #24 2985 .LCFI27: 2986 .cfi_def_cfa_offset 32 1173:Src/main.c **** 2987 .loc 2 1173 3 view .LVU991 1173:Src/main.c **** 2988 .loc 2 1173 22 is_stmt 0 view .LVU992 2989 0004 0024 movs r4, #0 2990 0006 0194 str r4, [sp, #4] 2991 0008 0294 str r4, [sp, #8] 2992 000a 0394 str r4, [sp, #12] 2993 000c 0494 str r4, [sp, #16] 2994 000e 0594 str r4, [sp, #20] 1176:Src/main.c **** 2995 .loc 2 1176 3 is_stmt 1 view .LVU993 2996 .LVL227: 2997 .LBB374: 2998 .LBI374: 1071:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { 2999 .loc 3 1071 22 view .LVU994 3000 .LBB375: 1073:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** SET_BIT(RCC->APB1ENR, Periphs); 3001 .loc 3 1073 3 view .LVU995 1074:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Delay after an RCC peripheral clock enabling */ 3002 .loc 3 1074 3 view .LVU996 3003 0010 1D4B ldr r3, .L116 3004 0012 1A6C ldr r2, [r3, #64] 3005 0014 42F00102 orr r2, r2, #1 3006 0018 1A64 str r2, [r3, #64] 1076:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; 3007 .loc 3 1076 3 view .LVU997 1076:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; 3008 .loc 3 1076 12 is_stmt 0 view .LVU998 3009 001a 1B6C ldr r3, [r3, #64] 3010 001c 03F00103 and r3, r3, #1 1076:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; 3011 .loc 3 1076 10 view .LVU999 3012 0020 0093 str r3, [sp] 1077:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } 3013 .loc 3 1077 3 is_stmt 1 view .LVU1000 ARM GAS /tmp/ccqopZd5.s page 200 3014 0022 009B ldr r3, [sp] 3015 .LVL228: 1077:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } 3016 .loc 3 1077 3 is_stmt 0 view .LVU1001 3017 .LBE375: 3018 .LBE374: 1179:Src/main.c **** NVIC_EnableIRQ(TIM2_IRQn); 3019 .loc 2 1179 3 is_stmt 1 view .LVU1002 3020 .LBB376: 3021 .LBI376: 1884:Drivers/CMSIS/Include/core_cm7.h **** { 3022 .loc 1 1884 26 view .LVU1003 3023 .LBB377: 1886:Drivers/CMSIS/Include/core_cm7.h **** } 3024 .loc 1 1886 3 view .LVU1004 1886:Drivers/CMSIS/Include/core_cm7.h **** } 3025 .loc 1 1886 26 is_stmt 0 view .LVU1005 3026 0024 194B ldr r3, .L116+4 3027 0026 D868 ldr r0, [r3, #12] 3028 .LBE377: 3029 .LBE376: 1179:Src/main.c **** NVIC_EnableIRQ(TIM2_IRQn); 3030 .loc 2 1179 3 view .LVU1006 3031 0028 2246 mov r2, r4 3032 002a 2146 mov r1, r4 3033 002c C0F30220 ubfx r0, r0, #8, #3 3034 0030 FFF7FEFF bl NVIC_EncodePriority 3035 .LVL229: 3036 .LBB378: 3037 .LBI378: 2024:Drivers/CMSIS/Include/core_cm7.h **** { 3038 .loc 1 2024 22 is_stmt 1 view .LVU1007 3039 .LBB379: 2026:Drivers/CMSIS/Include/core_cm7.h **** { 3040 .loc 1 2026 3 view .LVU1008 2028:Drivers/CMSIS/Include/core_cm7.h **** } 3041 .loc 1 2028 5 view .LVU1009 2028:Drivers/CMSIS/Include/core_cm7.h **** } 3042 .loc 1 2028 49 is_stmt 0 view .LVU1010 3043 0034 0001 lsls r0, r0, #4 3044 .LVL230: 2028:Drivers/CMSIS/Include/core_cm7.h **** } 3045 .loc 1 2028 49 view .LVU1011 3046 0036 C0B2 uxtb r0, r0 2028:Drivers/CMSIS/Include/core_cm7.h **** } 3047 .loc 1 2028 47 view .LVU1012 3048 0038 154B ldr r3, .L116+8 3049 003a 83F81C03 strb r0, [r3, #796] 3050 .LVL231: 2028:Drivers/CMSIS/Include/core_cm7.h **** } 3051 .loc 1 2028 47 view .LVU1013 3052 .LBE379: 3053 .LBE378: 1180:Src/main.c **** 3054 .loc 2 1180 3 is_stmt 1 view .LVU1014 3055 .LBB380: 3056 .LBI380: ARM GAS /tmp/ccqopZd5.s page 201 1896:Drivers/CMSIS/Include/core_cm7.h **** { 3057 .loc 1 1896 22 view .LVU1015 3058 .LBB381: 1898:Drivers/CMSIS/Include/core_cm7.h **** { 3059 .loc 1 1898 3 view .LVU1016 1900:Drivers/CMSIS/Include/core_cm7.h **** } 3060 .loc 1 1900 5 view .LVU1017 1900:Drivers/CMSIS/Include/core_cm7.h **** } 3061 .loc 1 1900 43 is_stmt 0 view .LVU1018 3062 003e 4FF08052 mov r2, #268435456 3063 0042 1A60 str r2, [r3] 3064 .LVL232: 1900:Drivers/CMSIS/Include/core_cm7.h **** } 3065 .loc 1 1900 43 view .LVU1019 3066 .LBE381: 3067 .LBE380: 1185:Src/main.c **** TIM_InitStruct.CounterMode = LL_TIM_COUNTERMODE_UP; 3068 .loc 2 1185 3 is_stmt 1 view .LVU1020 1185:Src/main.c **** TIM_InitStruct.CounterMode = LL_TIM_COUNTERMODE_UP; 3069 .loc 2 1185 28 is_stmt 0 view .LVU1021 3070 0044 4FF47A73 mov r3, #1000 3071 0048 ADF80430 strh r3, [sp, #4] @ movhi 1186:Src/main.c **** TIM_InitStruct.Autoreload = 840000; 3072 .loc 2 1186 3 is_stmt 1 view .LVU1022 1186:Src/main.c **** TIM_InitStruct.Autoreload = 840000; 3073 .loc 2 1186 30 is_stmt 0 view .LVU1023 3074 004c 0294 str r4, [sp, #8] 1187:Src/main.c **** TIM_InitStruct.ClockDivision = LL_TIM_CLOCKDIVISION_DIV1; 3075 .loc 2 1187 3 is_stmt 1 view .LVU1024 1187:Src/main.c **** TIM_InitStruct.ClockDivision = LL_TIM_CLOCKDIVISION_DIV1; 3076 .loc 2 1187 29 is_stmt 0 view .LVU1025 3077 004e 114B ldr r3, .L116+12 3078 0050 0393 str r3, [sp, #12] 1188:Src/main.c **** LL_TIM_Init(TIM2, &TIM_InitStruct); 3079 .loc 2 1188 3 is_stmt 1 view .LVU1026 1188:Src/main.c **** LL_TIM_Init(TIM2, &TIM_InitStruct); 3080 .loc 2 1188 32 is_stmt 0 view .LVU1027 3081 0052 0494 str r4, [sp, #16] 1189:Src/main.c **** LL_TIM_DisableARRPreload(TIM2); 3082 .loc 2 1189 3 is_stmt 1 view .LVU1028 3083 0054 01A9 add r1, sp, #4 3084 0056 4FF08040 mov r0, #1073741824 3085 005a FFF7FEFF bl LL_TIM_Init 3086 .LVL233: 1190:Src/main.c **** LL_TIM_SetClockSource(TIM2, LL_TIM_CLOCKSOURCE_INTERNAL); 3087 .loc 2 1190 3 view .LVU1029 3088 .LBB382: 3089 .LBI382: 3090 .file 5 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h" 1:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 2:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** ****************************************************************************** 3:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @file stm32f7xx_ll_tim.h 4:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @author MCD Application Team 5:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Header file of TIM LL module. 6:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** ****************************************************************************** 7:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @attention 8:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * ARM GAS /tmp/ccqopZd5.s page 202 9:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * Copyright (c) 2017 STMicroelectronics. 10:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * All rights reserved. 11:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * 12:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * This software is licensed under terms that can be found in the LICENSE file 13:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * in the root directory of this software component. 14:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * If no LICENSE file comes with this software, it is provided AS-IS. 15:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * 16:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** ****************************************************************************** 17:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 18:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 19:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /* Define to prevent recursive inclusion -------------------------------------*/ 20:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #ifndef __STM32F7xx_LL_TIM_H 21:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define __STM32F7xx_LL_TIM_H 22:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 23:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #ifdef __cplusplus 24:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** extern "C" { 25:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #endif 26:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 27:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /* Includes ------------------------------------------------------------------*/ 28:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #include "stm32f7xx.h" 29:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 30:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @addtogroup STM32F7xx_LL_Driver 31:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ 32:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 33:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 34:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #if defined (TIM1) || defined (TIM8) || defined (TIM2) || defined (TIM3) || defined (TIM4) || defi 35:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 36:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL TIM 37:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ 38:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 39:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 40:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /* Private types -------------------------------------------------------------*/ 41:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /* Private variables ---------------------------------------------------------*/ 42:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_Private_Variables TIM Private Variables 43:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ 44:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 45:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** static const uint8_t OFFSET_TAB_CCMRx[] = 46:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 47:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 0x00U, /* 0: TIMx_CH1 */ 48:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 0x00U, /* 1: TIMx_CH1N */ 49:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 0x00U, /* 2: TIMx_CH2 */ 50:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 0x00U, /* 3: TIMx_CH2N */ 51:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 0x04U, /* 4: TIMx_CH3 */ 52:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 0x04U, /* 5: TIMx_CH3N */ 53:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 0x04U, /* 6: TIMx_CH4 */ 54:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 0x3CU, /* 7: TIMx_CH5 */ 55:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 0x3CU /* 8: TIMx_CH6 */ 56:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }; 57:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 58:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** static const uint8_t SHIFT_TAB_OCxx[] = 59:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 60:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 0U, /* 0: OC1M, OC1FE, OC1PE */ 61:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 0U, /* 1: - NA */ 62:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 8U, /* 2: OC2M, OC2FE, OC2PE */ 63:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 0U, /* 3: - NA */ 64:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 0U, /* 4: OC3M, OC3FE, OC3PE */ 65:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 0U, /* 5: - NA */ ARM GAS /tmp/ccqopZd5.s page 203 66:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 8U, /* 6: OC4M, OC4FE, OC4PE */ 67:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 0U, /* 7: OC5M, OC5FE, OC5PE */ 68:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 8U /* 8: OC6M, OC6FE, OC6PE */ 69:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }; 70:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 71:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** static const uint8_t SHIFT_TAB_ICxx[] = 72:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 73:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 0U, /* 0: CC1S, IC1PSC, IC1F */ 74:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 0U, /* 1: - NA */ 75:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 8U, /* 2: CC2S, IC2PSC, IC2F */ 76:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 0U, /* 3: - NA */ 77:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 0U, /* 4: CC3S, IC3PSC, IC3F */ 78:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 0U, /* 5: - NA */ 79:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 8U, /* 6: CC4S, IC4PSC, IC4F */ 80:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 0U, /* 7: - NA */ 81:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 0U /* 8: - NA */ 82:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }; 83:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 84:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** static const uint8_t SHIFT_TAB_CCxP[] = 85:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 86:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 0U, /* 0: CC1P */ 87:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 2U, /* 1: CC1NP */ 88:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 4U, /* 2: CC2P */ 89:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 6U, /* 3: CC2NP */ 90:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 8U, /* 4: CC3P */ 91:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 10U, /* 5: CC3NP */ 92:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 12U, /* 6: CC4P */ 93:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 16U, /* 7: CC5P */ 94:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 20U /* 8: CC6P */ 95:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }; 96:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 97:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** static const uint8_t SHIFT_TAB_OISx[] = 98:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 99:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 0U, /* 0: OIS1 */ 100:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1U, /* 1: OIS1N */ 101:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 2U, /* 2: OIS2 */ 102:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3U, /* 3: OIS2N */ 103:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 4U, /* 4: OIS3 */ 104:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 5U, /* 5: OIS3N */ 105:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 6U, /* 6: OIS4 */ 106:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 8U, /* 7: OIS5 */ 107:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 10U /* 8: OIS6 */ 108:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }; 109:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 110:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} 111:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 112:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 113:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /* Private constants ---------------------------------------------------------*/ 114:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_Private_Constants TIM Private Constants 115:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ 116:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 117:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 118:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #if defined(TIM_BREAK_INPUT_SUPPORT) 119:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /* Defines used for the bit position in the register and perform offsets */ 120:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define TIM_POSITION_BRK_SOURCE (POSITION_VAL(Source) & 0x1FUL) 121:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 122:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /* Generic bit definitions for TIMx_AF1 register */ ARM GAS /tmp/ccqopZd5.s page 204 123:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define TIMx_AF1_BKINP TIM1_AF1_BKINP /*!< BRK BKIN input polarity */ 124:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #endif /* TIM_BREAK_INPUT_SUPPORT */ 125:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 126:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /* Remap mask definitions */ 127:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define TIMx_OR_RMP_SHIFT 16U 128:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define TIMx_OR_RMP_MASK 0x0000FFFFU 129:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define TIM2_OR_RMP_MASK (TIM2_OR_ITR1_RMP << TIMx_OR_RMP_SHIFT) 130:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define TIM5_OR_RMP_MASK (TIM5_OR_TI4_RMP << TIMx_OR_RMP_SHIFT) 131:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define TIM11_OR_RMP_MASK (TIM11_OR_TI1_RMP << TIMx_OR_RMP_SHIFT) 132:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 133:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /* Mask used to set the TDG[x:0] of the DTG bits of the TIMx_BDTR register */ 134:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define DT_DELAY_1 ((uint8_t)0x7F) 135:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define DT_DELAY_2 ((uint8_t)0x3F) 136:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define DT_DELAY_3 ((uint8_t)0x1F) 137:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define DT_DELAY_4 ((uint8_t)0x1F) 138:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 139:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /* Mask used to set the DTG[7:5] bits of the DTG bits of the TIMx_BDTR register */ 140:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define DT_RANGE_1 ((uint8_t)0x00) 141:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define DT_RANGE_2 ((uint8_t)0x80) 142:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define DT_RANGE_3 ((uint8_t)0xC0) 143:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define DT_RANGE_4 ((uint8_t)0xE0) 144:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 145:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 146:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 147:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} 148:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 149:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 150:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /* Private macros ------------------------------------------------------------*/ 151:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_Private_Macros TIM Private Macros 152:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ 153:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 154:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @brief Convert channel id into channel index. 155:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param __CHANNEL__ This parameter can be one of the following values: 156:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 157:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1N 158:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 159:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2N 160:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 161:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3N 162:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 163:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH5 164:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH6 165:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval none 166:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 167:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define TIM_GET_CHANNEL_INDEX( __CHANNEL__) \ 168:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** (((__CHANNEL__) == LL_TIM_CHANNEL_CH1) ? 0U :\ 169:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** ((__CHANNEL__) == LL_TIM_CHANNEL_CH1N) ? 1U :\ 170:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** ((__CHANNEL__) == LL_TIM_CHANNEL_CH2) ? 2U :\ 171:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** ((__CHANNEL__) == LL_TIM_CHANNEL_CH2N) ? 3U :\ 172:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** ((__CHANNEL__) == LL_TIM_CHANNEL_CH3) ? 4U :\ 173:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** ((__CHANNEL__) == LL_TIM_CHANNEL_CH3N) ? 5U :\ 174:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** ((__CHANNEL__) == LL_TIM_CHANNEL_CH4) ? 6U :\ 175:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** ((__CHANNEL__) == LL_TIM_CHANNEL_CH5) ? 7U : 8U) 176:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 177:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @brief Calculate the deadtime sampling period(in ps). 178:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param __TIMCLK__ timer input clock frequency (in Hz). 179:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param __CKD__ This parameter can be one of the following values: ARM GAS /tmp/ccqopZd5.s page 205 180:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CLOCKDIVISION_DIV1 181:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CLOCKDIVISION_DIV2 182:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CLOCKDIVISION_DIV4 183:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval none 184:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 185:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define TIM_CALC_DTS(__TIMCLK__, __CKD__) \ 186:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** (((__CKD__) == LL_TIM_CLOCKDIVISION_DIV1) ? ((uint64_t)1000000000000U/(__TIMCLK__)) : \ 187:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** ((__CKD__) == LL_TIM_CLOCKDIVISION_DIV2) ? ((uint64_t)1000000000000U/((__TIMCLK__) >> 1U)) : \ 188:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** ((uint64_t)1000000000000U/((__TIMCLK__) >> 2U))) 189:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 190:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} 191:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 192:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 193:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 194:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /* Exported types ------------------------------------------------------------*/ 195:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #if defined(USE_FULL_LL_DRIVER) 196:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_ES_INIT TIM Exported Init structure 197:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ 198:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 199:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 200:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 201:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief TIM Time Base configuration structure definition. 202:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 203:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** typedef struct 204:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 205:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint16_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock. 206:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a number between Min_Data=0x0000 and Max_D 207:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 208:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary function 209:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_SetPrescaler().*/ 210:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 211:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t CounterMode; /*!< Specifies the counter mode. 212:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_COUNTERMODE. 213:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 214:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary function 215:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_SetCounterMode().*/ 216:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 217:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t Autoreload; /*!< Specifies the auto reload value to be loaded into the active 218:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** Auto-Reload Register at the next update event. 219:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter must be a number between Min_Data=0x0000 and Max_ 220:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** Some timer instances may support 32 bits counters. In that case 221:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** be a number between 0x0000 and 0xFFFFFFFF. 222:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 223:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary function 224:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_SetAutoReload().*/ 225:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 226:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t ClockDivision; /*!< Specifies the clock division. 227:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_CLOCKDIVISION. 228:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 229:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary function 230:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_SetClockDivision().*/ 231:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 232:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downc 233:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** reaches zero, an update event is generated and counting restarts 234:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** from the RCR value (N). 235:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This means in PWM mode that (N+1) corresponds to: 236:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** - the number of PWM periods in edge-aligned mode ARM GAS /tmp/ccqopZd5.s page 206 237:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** - the number of half PWM period in center-aligned mode 238:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** GP timers: this parameter must be a number between Min_Data = 0x 239:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** Max_Data = 0xFF. 240:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** Advanced timers: this parameter must be a number between Min_Dat 241:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** Max_Data = 0xFFFF. 242:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 243:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary function 244:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_SetRepetitionCounter().*/ 245:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } LL_TIM_InitTypeDef; 246:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 247:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 248:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief TIM Output Compare configuration structure definition. 249:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 250:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** typedef struct 251:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 252:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t OCMode; /*!< Specifies the output mode. 253:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_OCMODE. 254:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 255:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary function 256:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_OC_SetMode().*/ 257:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 258:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t OCState; /*!< Specifies the TIM Output Compare state. 259:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_OCSTATE. 260:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 261:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary functions 262:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/ 263:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 264:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t OCNState; /*!< Specifies the TIM complementary Output Compare state. 265:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_OCSTATE. 266:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 267:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary functions 268:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/ 269:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 270:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t CompareValue; /*!< Specifies the Compare value to be loaded into the Capture Compare Re 271:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a number between Min_Data=0x0000 and Max_Data= 272:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 273:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary function 274:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** LL_TIM_OC_SetCompareCHx (x=1..6).*/ 275:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 276:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t OCPolarity; /*!< Specifies the output polarity. 277:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY. 278:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 279:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary function 280:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_OC_SetPolarity().*/ 281:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 282:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t OCNPolarity; /*!< Specifies the complementary output polarity. 283:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY. 284:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 285:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary function 286:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_OC_SetPolarity().*/ 287:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 288:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 289:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. 290:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE. 291:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 292:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary function 293:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_OC_SetIdleState().*/ ARM GAS /tmp/ccqopZd5.s page 207 294:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 295:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. 296:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE. 297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 298:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary function 299:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_OC_SetIdleState().*/ 300:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } LL_TIM_OC_InitTypeDef; 301:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 302:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 303:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief TIM Input Capture configuration structure definition. 304:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 305:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 306:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** typedef struct 307:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 308:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 309:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t ICPolarity; /*!< Specifies the active edge of the input signal. 310:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY. 311:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 312:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary function 313:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_IC_SetPolarity().*/ 314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t ICActiveInput; /*!< Specifies the input. 316:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT. 317:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 318:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary function 319:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_IC_SetActiveInput().*/ 320:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 321:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler. 322:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_ICPSC. 323:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 324:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary function 325:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_IC_SetPrescaler().*/ 326:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 327:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t ICFilter; /*!< Specifies the input capture filter. 328:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_IC_FILTER. 329:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 330:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary function 331:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_IC_SetFilter().*/ 332:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } LL_TIM_IC_InitTypeDef; 333:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 334:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 335:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 336:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief TIM Encoder interface configuration structure definition. 337:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 338:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** typedef struct 339:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 340:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t EncoderMode; /*!< Specifies the encoder resolution (x2 or x4). 341:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_ENCODERMODE. 342:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 343:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary function 344:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_SetEncoderMode().*/ 345:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input. 347:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY. 348:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 349:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary function 350:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_IC_SetPolarity().*/ ARM GAS /tmp/ccqopZd5.s page 208 351:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 352:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t IC1ActiveInput; /*!< Specifies the TI1 input source 353:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT. 354:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 355:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary function 356:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_IC_SetActiveInput().*/ 357:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 358:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value. 359:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_ICPSC. 360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 361:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary function 362:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_IC_SetPrescaler().*/ 363:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 364:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t IC1Filter; /*!< Specifies the TI1 input filter. 365:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_IC_FILTER. 366:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 367:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary function 368:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_IC_SetFilter().*/ 369:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t IC2Polarity; /*!< Specifies the active edge of TI2 input. 371:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY. 372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary function 374:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_IC_SetPolarity().*/ 375:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 376:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t IC2ActiveInput; /*!< Specifies the TI2 input source 377:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT. 378:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 379:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary function 380:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_IC_SetActiveInput().*/ 381:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 382:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t IC2Prescaler; /*!< Specifies the TI2 input prescaler value. 383:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_ICPSC. 384:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 385:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary function 386:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_IC_SetPrescaler().*/ 387:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 388:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t IC2Filter; /*!< Specifies the TI2 input filter. 389:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_IC_FILTER. 390:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 391:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary function 392:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_IC_SetFilter().*/ 393:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 394:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } LL_TIM_ENCODER_InitTypeDef; 395:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 396:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 397:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief TIM Hall sensor interface configuration structure definition. 398:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 399:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** typedef struct 400:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 401:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 402:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input. 403:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY. 404:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 405:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary function 406:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_IC_SetPolarity().*/ 407:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** ARM GAS /tmp/ccqopZd5.s page 209 408:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value. 409:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** Prescaler must be set to get a maximum counter period longer th 410:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** time interval between 2 consecutive changes on the Hall inputs. 411:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_ICPSC. 412:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 413:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary function 414:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_IC_SetPrescaler().*/ 415:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 416:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t IC1Filter; /*!< Specifies the TI1 input filter. 417:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of 418:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref TIM_LL_EC_IC_FILTER. 419:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 420:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary function 421:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_IC_SetFilter().*/ 422:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 423:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t CommutationDelay; /*!< Specifies the compare value to be loaded into the Capture Compa 424:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** A positive pulse (TRGO event) is generated with a programmable 425:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** a change occurs on the Hall inputs. 426:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a number between Min_Data = 0x0000 and Ma 427:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary function 429:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_OC_SetCompareCH2().*/ 430:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } LL_TIM_HALLSENSOR_InitTypeDef; 431:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 432:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 433:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief BDTR (Break and Dead Time) structure definition 434:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 435:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** typedef struct 436:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 437:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t OSSRState; /*!< Specifies the Off-State selection used in Run mode. 438:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_OSSR 439:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 440:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary functio 441:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_SetOffStates() 442:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 443:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @note This bit-field cannot be modified as long as LOCK level 444:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** programmed. */ 445:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 446:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t OSSIState; /*!< Specifies the Off-State used in Idle state. 447:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_OSSI 448:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 449:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary functio 450:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_SetOffStates() 451:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 452:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @note This bit-field cannot be modified as long as LOCK level 453:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** programmed. */ 454:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 455:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t LockLevel; /*!< Specifies the LOCK level parameters. 456:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_LOCKLEVEL 457:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 458:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @note The LOCK bits can be written only once after the reset. 459:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** register has been written, their content is frozen until the 460:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 461:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint8_t DeadTime; /*!< Specifies the delay time between the switching-off and the 462:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** switching-on of the outputs. 463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a number between Min_Data = 0x00 and Ma 464:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** ARM GAS /tmp/ccqopZd5.s page 210 465:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary functio 466:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_OC_SetDeadTime() 467:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 468:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @note This bit-field can not be modified as long as LOCK leve 469:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** programmed. */ 470:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 471:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint16_t BreakState; /*!< Specifies whether the TIM Break input is enabled or not. 472:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_BREAK_ENABLE 473:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 474:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary functio 475:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_EnableBRK() or @ref LL_TIM_DisableBRK() 476:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 477:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @note This bit-field can not be modified as long as LOCK leve 478:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** programmed. */ 479:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 480:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t BreakPolarity; /*!< Specifies the TIM Break Input pin polarity. 481:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_BREAK_POLARIT 482:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 483:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary functio 484:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_ConfigBRK() 485:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 486:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @note This bit-field can not be modified as long as LOCK leve 487:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** programmed. */ 488:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 489:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t BreakFilter; /*!< Specifies the TIM Break Filter. 490:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_BREAK_FILTER 491:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 492:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary functio 493:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_ConfigBRK() 494:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 495:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @note This bit-field can not be modified as long as LOCK leve 496:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** programmed. */ 497:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 498:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t Break2State; /*!< Specifies whether the TIM Break2 input is enabled or not. 499:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_BREAK2_ENABLE 500:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 501:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary functio 502:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_EnableBRK2() or @ref LL_TIM_DisableBRK2() 503:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 504:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @note This bit-field can not be modified as long as LOCK leve 505:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** programmed. */ 506:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 507:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t Break2Polarity; /*!< Specifies the TIM Break2 Input pin polarity. 508:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_BREAK2_POLARI 509:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 510:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary functio 511:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_ConfigBRK2() 512:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 513:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @note This bit-field can not be modified as long as LOCK leve 514:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** programmed. */ 515:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 516:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t Break2Filter; /*!< Specifies the TIM Break2 Filter. 517:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_BREAK2_FILTER 518:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 519:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary functio 520:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_ConfigBRK2() 521:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** ARM GAS /tmp/ccqopZd5.s page 211 522:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @note This bit-field can not be modified as long as LOCK leve 523:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** programmed. */ 524:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 525:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t AutomaticOutput; /*!< Specifies whether the TIM Automatic Output feature is enabled 526:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_AUTOMATICOUTP 527:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 528:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary functio 529:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_EnableAutomaticOutput() or @ref LL_TIM_DisableAut 530:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 531:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @note This bit-field can not be modified as long as LOCK leve 532:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** programmed. */ 533:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } LL_TIM_BDTR_InitTypeDef; 534:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 535:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 536:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} 537:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 538:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #endif /* USE_FULL_LL_DRIVER */ 539:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 540:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /* Exported constants --------------------------------------------------------*/ 541:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_Exported_Constants TIM Exported Constants 542:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ 543:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 544:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 545:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EC_GET_FLAG Get Flags Defines 546:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Flags defines which can be used with LL_TIM_ReadReg function. 547:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ 548:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 549:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_SR_UIF TIM_SR_UIF /*!< Update interrupt flag */ 550:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_SR_CC1IF TIM_SR_CC1IF /*!< Capture/compare 1 interrup 551:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_SR_CC2IF TIM_SR_CC2IF /*!< Capture/compare 2 interrup 552:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_SR_CC3IF TIM_SR_CC3IF /*!< Capture/compare 3 interrup 553:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_SR_CC4IF TIM_SR_CC4IF /*!< Capture/compare 4 interrup 554:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_SR_CC5IF TIM_SR_CC5IF /*!< Capture/compare 5 interrup 555:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_SR_CC6IF TIM_SR_CC6IF /*!< Capture/compare 6 interrup 556:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_SR_COMIF TIM_SR_COMIF /*!< COM interrupt flag */ 557:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_SR_TIF TIM_SR_TIF /*!< Trigger interrupt flag */ 558:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_SR_BIF TIM_SR_BIF /*!< Break interrupt flag */ 559:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_SR_B2IF TIM_SR_B2IF /*!< Second break interrupt fla 560:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_SR_CC1OF TIM_SR_CC1OF /*!< Capture/Compare 1 overcapt 561:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_SR_CC2OF TIM_SR_CC2OF /*!< Capture/Compare 2 overcapt 562:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_SR_CC3OF TIM_SR_CC3OF /*!< Capture/Compare 3 overcapt 563:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_SR_CC4OF TIM_SR_CC4OF /*!< Capture/Compare 4 overcapt 564:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_SR_SBIF TIM_SR_SBIF /*!< System Break interrupt fla 565:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 566:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} 567:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 568:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 569:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #if defined(USE_FULL_LL_DRIVER) 570:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EC_BREAK_ENABLE Break Enable 571:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ 572:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 573:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_BREAK_DISABLE 0x00000000U /*!< Break function disabled */ 574:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_BREAK_ENABLE TIM_BDTR_BKE /*!< Break function enabled */ 575:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 576:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} 577:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 578:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** ARM GAS /tmp/ccqopZd5.s page 212 579:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EC_BREAK2_ENABLE Break2 Enable 580:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ 581:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 582:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_BREAK2_DISABLE 0x00000000U /*!< Break2 function disabled */ 583:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_BREAK2_ENABLE TIM_BDTR_BK2E /*!< Break2 function enabled */ 584:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 585:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} 586:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 587:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 588:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EC_AUTOMATICOUTPUT_ENABLE Automatic output enable 589:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ 590:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 591:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U /*!< MOE can be set only by 592:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /*!< MOE can be set by softw 593:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 594:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} 595:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 596:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #endif /* USE_FULL_LL_DRIVER */ 597:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 598:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EC_IT IT Defines 599:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief IT defines which can be used with LL_TIM_ReadReg and LL_TIM_WriteReg functions. 600:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ 601:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 602:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_DIER_UIE TIM_DIER_UIE /*!< Update interrupt enable */ 603:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_DIER_CC1IE TIM_DIER_CC1IE /*!< Capture/compare 1 interrup 604:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_DIER_CC2IE TIM_DIER_CC2IE /*!< Capture/compare 2 interrup 605:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_DIER_CC3IE TIM_DIER_CC3IE /*!< Capture/compare 3 interrup 606:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_DIER_CC4IE TIM_DIER_CC4IE /*!< Capture/compare 4 interrup 607:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_DIER_COMIE TIM_DIER_COMIE /*!< COM interrupt enable */ 608:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_DIER_TIE TIM_DIER_TIE /*!< Trigger interrupt enable * 609:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_DIER_BIE TIM_DIER_BIE /*!< Break interrupt enable */ 610:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 611:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} 612:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 613:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 614:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EC_UPDATESOURCE Update Source 615:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ 616:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 617:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_UPDATESOURCE_REGULAR 0x00000000U /*!< Counter overflow/underflow 618:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_UPDATESOURCE_COUNTER TIM_CR1_URS /*!< Only counter overflow/unde 619:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 620:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} 621:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 622:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 623:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EC_ONEPULSEMODE One Pulse Mode 624:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ 625:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 626:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_ONEPULSEMODE_SINGLE TIM_CR1_OPM /*!< Counter stops counting at 627:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_ONEPULSEMODE_REPETITIVE 0x00000000U /*!< Counter is not stopped at 628:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 629:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} 630:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 631:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 632:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EC_COUNTERMODE Counter Mode 633:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ 634:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 635:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_COUNTERMODE_UP 0x00000000U /*!< Counter used as upcounter ARM GAS /tmp/ccqopZd5.s page 213 636:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_COUNTERMODE_DOWN TIM_CR1_DIR /*!< Counter used as downcounte 637:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_COUNTERMODE_CENTER_DOWN TIM_CR1_CMS_0 /*!< The counter counts up and 638:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_COUNTERMODE_CENTER_UP TIM_CR1_CMS_1 /*!< The counter counts up and 639:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_COUNTERMODE_CENTER_UP_DOWN TIM_CR1_CMS /*!< The counter counts up and 640:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 641:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} 642:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 643:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 644:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EC_CLOCKDIVISION Clock Division 645:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ 646:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 647:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_CLOCKDIVISION_DIV1 0x00000000U /*!< tDTS=tCK_INT */ 648:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0 /*!< tDTS=2*tCK_INT */ 649:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1 /*!< tDTS=4*tCK_INT */ 650:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 651:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} 652:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 653:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 654:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EC_COUNTERDIRECTION Counter Direction 655:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ 656:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 657:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_COUNTERDIRECTION_UP 0x00000000U /*!< Timer counter counts up */ 658:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_COUNTERDIRECTION_DOWN TIM_CR1_DIR /*!< Timer counter counts down 659:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 660:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} 661:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 662:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 663:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EC_CCUPDATESOURCE Capture Compare Update Source 664:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ 665:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 666:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_CCUPDATESOURCE_COMG_ONLY 0x00000000U /*!< Capture/compare control bi 667:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI TIM_CR2_CCUS /*!< Capture/compare control bi 668:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 669:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} 670:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 671:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 672:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EC_CCDMAREQUEST Capture Compare DMA Request 673:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ 674:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 675:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_CCDMAREQUEST_CC 0x00000000U /*!< CCx DMA request sent when 676:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_CCDMAREQUEST_UPDATE TIM_CR2_CCDS /*!< CCx DMA requests sent when 677:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 678:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} 679:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 680:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 681:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EC_LOCKLEVEL Lock Level 682:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ 683:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 684:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_LOCKLEVEL_OFF 0x00000000U /*!< LOCK OFF - No bit is write 685:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0 /*!< LOCK Level 1 */ 686:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1 /*!< LOCK Level 2 */ 687:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_LOCKLEVEL_3 TIM_BDTR_LOCK /*!< LOCK Level 3 */ 688:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 689:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} 690:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 691:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 692:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EC_CHANNEL Channel ARM GAS /tmp/ccqopZd5.s page 214 693:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ 694:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 695:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_CHANNEL_CH1 TIM_CCER_CC1E /*!< Timer input/output channel 1 696:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_CHANNEL_CH1N TIM_CCER_CC1NE /*!< Timer complementary output ch 697:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_CHANNEL_CH2 TIM_CCER_CC2E /*!< Timer input/output channel 2 698:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_CHANNEL_CH2N TIM_CCER_CC2NE /*!< Timer complementary output ch 699:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_CHANNEL_CH3 TIM_CCER_CC3E /*!< Timer input/output channel 3 700:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_CHANNEL_CH3N TIM_CCER_CC3NE /*!< Timer complementary output ch 701:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_CHANNEL_CH4 TIM_CCER_CC4E /*!< Timer input/output channel 4 702:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_CHANNEL_CH5 TIM_CCER_CC5E /*!< Timer output channel 5 */ 703:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_CHANNEL_CH6 TIM_CCER_CC6E /*!< Timer output channel 6 */ 704:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 705:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} 706:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 707:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 708:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #if defined(USE_FULL_LL_DRIVER) 709:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EC_OCSTATE Output Configuration State 710:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ 711:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 712:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_OCSTATE_DISABLE 0x00000000U /*!< OCx is not active */ 713:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_OCSTATE_ENABLE TIM_CCER_CC1E /*!< OCx signal is output on 714:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 715:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} 716:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 717:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #endif /* USE_FULL_LL_DRIVER */ 718:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 719:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** Legacy definitions for compatibility purpose 720:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @cond 0 721:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 722:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_OCMODE_ASSYMETRIC_PWM1 LL_TIM_OCMODE_ASYMMETRIC_PWM1 723:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_OCMODE_ASSYMETRIC_PWM2 LL_TIM_OCMODE_ASYMMETRIC_PWM2 724:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 725:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @endcond 726:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 727:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 728:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EC_OCMODE Output Configuration Mode 729:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ 730:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 731:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_OCMODE_FROZEN 0x00000000U 732:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0 733:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1 734:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) 735:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_OCMODE_FORCED_INACTIVE TIM_CCMR1_OC1M_2 736:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0) 737:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1) 738:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1 739:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_OCMODE_RETRIG_OPM1 TIM_CCMR1_OC1M_3 740:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_OCMODE_RETRIG_OPM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0) 741:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_OCMODE_COMBINED_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2) 742:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_OCMODE_COMBINED_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1 743:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_OCMODE_ASYMMETRIC_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1 744:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_OCMODE_ASYMMETRIC_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M) 745:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 746:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} 747:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 748:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 749:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EC_OCPOLARITY Output Configuration Polarity ARM GAS /tmp/ccqopZd5.s page 215 750:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ 751:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 752:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_OCPOLARITY_HIGH 0x00000000U /*!< OCxactive high*/ 753:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_OCPOLARITY_LOW TIM_CCER_CC1P /*!< OCxactive low*/ 754:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 755:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} 756:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 757:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 758:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EC_OCIDLESTATE Output Configuration Idle State 759:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ 760:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 761:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_OCIDLESTATE_LOW 0x00000000U /*!__REG__, (__VAL 1185:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1186:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 1187:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Read a value in TIM register. 1188:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param __INSTANCE__ TIM Instance 1189:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param __REG__ Register to be read 1190:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval Register value 1191:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1192:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__) 1193:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 1194:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} 1195:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1196:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1197:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 1198:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief HELPER macro retrieving the UIFCPY flag from the counter value. 1199:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note ex: @ref __LL_TIM_GETFLAG_UIFCPY (@ref LL_TIM_GetCounter ()); 1200:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Relevant only if UIF flag remapping has been enabled (UIF status bit is copied 1201:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * to TIMx_CNT register bit 31) 1202:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param __CNT__ Counter value 1203:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval UIF status bit 1204:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1205:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define __LL_TIM_GETFLAG_UIFCPY(__CNT__) \ ARM GAS /tmp/ccqopZd5.s page 223 1206:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** (READ_BIT((__CNT__), TIM_CNT_UIFCPY) >> TIM_CNT_UIFCPY_Pos) 1207:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1208:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 1209:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief HELPER macro calculating DTG[0:7] in the TIMx_BDTR register to achieve the requested de 1210:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note ex: @ref __LL_TIM_CALC_DEADTIME (80000000, @ref LL_TIM_GetClockDivision (), 120); 1211:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param __TIMCLK__ timer input clock frequency (in Hz) 1212:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param __CKD__ This parameter can be one of the following values: 1213:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CLOCKDIVISION_DIV1 1214:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CLOCKDIVISION_DIV2 1215:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CLOCKDIVISION_DIV4 1216:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param __DT__ deadtime duration (in ns) 1217:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval DTG[0:7] 1218:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1219:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define __LL_TIM_CALC_DEADTIME(__TIMCLK__, __CKD__, __DT__) \ 1220:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** ( (((uint64_t)((__DT__)*1000U)) < ((DT_DELAY_1+1U) * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? 1221:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** (uint8_t)(((uint64_t)((__DT__)*1000U) / TIM_CALC_DTS((__TIMCLK__), (__CKD__))) & DT_DELAY_1) : 1222:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** (((uint64_t)((__DT__)*1000U)) < ((64U + (DT_DELAY_2+1U)) * 2U * TIM_CALC_DTS((__TIMCLK__), (__C 1223:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** (uint8_t)(DT_RANGE_2 | ((uint8_t)((uint8_t)((((uint64_t)((__DT__)*1000U))/ TIM_CALC_DTS((__TIMC 1224:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** (__CKD__))) >> 1U) - (uint8_t) 64) & DT_DELAY_2)) 1225:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_3+1U)) * 8U * TIM_CALC_DTS((__TIMCLK__), (__C 1226:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** (uint8_t)(DT_RANGE_3 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMC 1227:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** (__CKD__))) >> 3U) - (uint8_t) 32) & DT_DELAY_3)) 1228:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_4+1U)) * 16U * TIM_CALC_DTS((__TIMCLK__), (__ 1229:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** (uint8_t)(DT_RANGE_4 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMC 1230:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** (__CKD__))) >> 4U) - (uint8_t) 32) & DT_DELAY_4)) 1231:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 0U) 1232:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1233:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 1234:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief HELPER macro calculating the prescaler value to achieve the required counter clock freq 1235:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note ex: @ref __LL_TIM_CALC_PSC (80000000, 1000000); 1236:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param __TIMCLK__ timer input clock frequency (in Hz) 1237:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param __CNTCLK__ counter clock frequency (in Hz) 1238:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval Prescaler value (between Min_Data=0 and Max_Data=65535) 1239:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1240:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define __LL_TIM_CALC_PSC(__TIMCLK__, __CNTCLK__) \ 1241:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** (((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)((((__TIMCLK__) + (__CNTCLK__)/2U)/(__CNTCLK__)) - 1U 1242:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1243:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 1244:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief HELPER macro calculating the auto-reload value to achieve the required output signal fr 1245:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note ex: @ref __LL_TIM_CALC_ARR (1000000, @ref LL_TIM_GetPrescaler (), 10000); 1246:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param __TIMCLK__ timer input clock frequency (in Hz) 1247:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param __PSC__ prescaler 1248:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param __FREQ__ output signal frequency (in Hz) 1249:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535) 1250:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1251:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define __LL_TIM_CALC_ARR(__TIMCLK__, __PSC__, __FREQ__) \ 1252:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** ((((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? (((__TIMCLK__)/((__FREQ__) * ((__PSC__) + 1U)) 1253:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1254:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 1255:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief HELPER macro calculating the compare value required to achieve the required timer outpu 1256:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * active/inactive delay. 1257:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note ex: @ref __LL_TIM_CALC_DELAY (1000000, @ref LL_TIM_GetPrescaler (), 10); 1258:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param __TIMCLK__ timer input clock frequency (in Hz) 1259:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param __PSC__ prescaler 1260:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param __DELAY__ timer output compare active/inactive delay (in us) 1261:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval Compare value (between Min_Data=0 and Max_Data=65535) 1262:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ ARM GAS /tmp/ccqopZd5.s page 224 1263:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define __LL_TIM_CALC_DELAY(__TIMCLK__, __PSC__, __DELAY__) \ 1264:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** ((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__)) \ 1265:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** / ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U)))) 1266:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1267:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 1268:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief HELPER macro calculating the auto-reload value to achieve the required pulse duration 1269:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * (when the timer operates in one pulse mode). 1270:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note ex: @ref __LL_TIM_CALC_PULSE (1000000, @ref LL_TIM_GetPrescaler (), 10, 20); 1271:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param __TIMCLK__ timer input clock frequency (in Hz) 1272:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param __PSC__ prescaler 1273:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param __DELAY__ timer output compare active/inactive delay (in us) 1274:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param __PULSE__ pulse duration (in us) 1275:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535) 1276:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1277:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define __LL_TIM_CALC_PULSE(__TIMCLK__, __PSC__, __DELAY__, __PULSE__) \ 1278:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** ((uint32_t)(__LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__PULSE__)) \ 1279:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + __LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__DELAY__)))) 1280:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1281:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 1282:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief HELPER macro retrieving the ratio of the input capture prescaler 1283:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note ex: @ref __LL_TIM_GET_ICPSC_RATIO (@ref LL_TIM_IC_GetPrescaler ()); 1284:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param __ICPSC__ This parameter can be one of the following values: 1285:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ICPSC_DIV1 1286:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ICPSC_DIV2 1287:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ICPSC_DIV4 1288:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ICPSC_DIV8 1289:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval Input capture prescaler ratio (1, 2, 4 or 8) 1290:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1291:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define __LL_TIM_GET_ICPSC_RATIO(__ICPSC__) \ 1292:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** ((uint32_t)(0x01U << (((__ICPSC__) >> 16U) >> TIM_CCMR1_IC1PSC_Pos))) 1293:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1294:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1295:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 1296:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} 1297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1298:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1299:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /* Exported functions --------------------------------------------------------*/ 1300:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_Exported_Functions TIM Exported Functions 1301:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ 1302:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1303:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1304:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EF_Time_Base Time Base configuration 1305:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ 1306:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1307:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 1308:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Enable timer counter. 1309:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR1 CEN LL_TIM_EnableCounter 1310:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 1311:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 1312:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1313:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_EnableCounter(TIM_TypeDef *TIMx) 1314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 1315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** SET_BIT(TIMx->CR1, TIM_CR1_CEN); 1316:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 1317:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1318:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 1319:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Disable timer counter. ARM GAS /tmp/ccqopZd5.s page 225 1320:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR1 CEN LL_TIM_DisableCounter 1321:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 1322:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 1323:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1324:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_DisableCounter(TIM_TypeDef *TIMx) 1325:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 1326:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** CLEAR_BIT(TIMx->CR1, TIM_CR1_CEN); 1327:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 1328:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1329:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 1330:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Indicates whether the timer counter is enabled. 1331:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR1 CEN LL_TIM_IsEnabledCounter 1332:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 1333:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval State of bit (1 or 0). 1334:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1335:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsEnabledCounter(const TIM_TypeDef *TIMx) 1336:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 1337:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return ((READ_BIT(TIMx->CR1, TIM_CR1_CEN) == (TIM_CR1_CEN)) ? 1UL : 0UL); 1338:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 1339:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1340:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 1341:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Enable update event generation. 1342:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR1 UDIS LL_TIM_EnableUpdateEvent 1343:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 1344:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 1345:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_EnableUpdateEvent(TIM_TypeDef *TIMx) 1347:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 1348:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** CLEAR_BIT(TIMx->CR1, TIM_CR1_UDIS); 1349:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 1350:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1351:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 1352:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Disable update event generation. 1353:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR1 UDIS LL_TIM_DisableUpdateEvent 1354:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 1355:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 1356:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1357:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_DisableUpdateEvent(TIM_TypeDef *TIMx) 1358:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 1359:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** SET_BIT(TIMx->CR1, TIM_CR1_UDIS); 1360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 1361:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1362:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 1363:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Indicates whether update event generation is enabled. 1364:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR1 UDIS LL_TIM_IsEnabledUpdateEvent 1365:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 1366:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval Inverted state of bit (0 or 1). 1367:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1368:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsEnabledUpdateEvent(const TIM_TypeDef *TIMx) 1369:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 1370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return ((READ_BIT(TIMx->CR1, TIM_CR1_UDIS) == (uint32_t)RESET) ? 1UL : 0UL); 1371:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 1372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 1374:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Set update event source 1375:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Update event source set to LL_TIM_UPDATESOURCE_REGULAR: any of the following events 1376:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * generate an update interrupt or DMA request if enabled: ARM GAS /tmp/ccqopZd5.s page 226 1377:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * - Counter overflow/underflow 1378:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * - Setting the UG bit 1379:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * - Update generation through the slave mode controller 1380:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Update event source set to LL_TIM_UPDATESOURCE_COUNTER: only counter 1381:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * overflow/underflow generates an update interrupt or DMA request if enabled. 1382:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR1 URS LL_TIM_SetUpdateSource 1383:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 1384:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param UpdateSource This parameter can be one of the following values: 1385:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_UPDATESOURCE_REGULAR 1386:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_UPDATESOURCE_COUNTER 1387:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 1388:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1389:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_SetUpdateSource(TIM_TypeDef *TIMx, uint32_t UpdateSource) 1390:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 1391:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(TIMx->CR1, TIM_CR1_URS, UpdateSource); 1392:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 1393:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1394:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 1395:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Get actual event update source 1396:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR1 URS LL_TIM_GetUpdateSource 1397:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 1398:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval Returned value can be one of the following values: 1399:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_UPDATESOURCE_REGULAR 1400:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_UPDATESOURCE_COUNTER 1401:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1402:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_GetUpdateSource(const TIM_TypeDef *TIMx) 1403:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 1404:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_URS)); 1405:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 1406:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1407:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 1408:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Set one pulse mode (one shot v.s. repetitive). 1409:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR1 OPM LL_TIM_SetOnePulseMode 1410:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 1411:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param OnePulseMode This parameter can be one of the following values: 1412:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ONEPULSEMODE_SINGLE 1413:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE 1414:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 1415:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1416:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_SetOnePulseMode(TIM_TypeDef *TIMx, uint32_t OnePulseMode) 1417:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 1418:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(TIMx->CR1, TIM_CR1_OPM, OnePulseMode); 1419:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 1420:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1421:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 1422:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Get actual one pulse mode. 1423:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR1 OPM LL_TIM_GetOnePulseMode 1424:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 1425:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval Returned value can be one of the following values: 1426:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ONEPULSEMODE_SINGLE 1427:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE 1428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1429:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_GetOnePulseMode(const TIM_TypeDef *TIMx) 1430:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 1431:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_OPM)); 1432:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 1433:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** ARM GAS /tmp/ccqopZd5.s page 227 1434:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 1435:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Set the timer counter counting mode. 1436:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to 1437:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * check whether or not the counter mode selection feature is supported 1438:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * by a timer instance. 1439:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) 1440:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * requires a timer reset to avoid unexpected direction 1441:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * due to DIR bit readonly in center aligned mode. 1442:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR1 DIR LL_TIM_SetCounterMode\n 1443:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CR1 CMS LL_TIM_SetCounterMode 1444:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 1445:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param CounterMode This parameter can be one of the following values: 1446:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_COUNTERMODE_UP 1447:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_COUNTERMODE_DOWN 1448:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP 1449:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN 1450:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN 1451:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 1452:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1453:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_SetCounterMode(TIM_TypeDef *TIMx, uint32_t CounterMode) 1454:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 1455:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(TIMx->CR1, (TIM_CR1_DIR | TIM_CR1_CMS), CounterMode); 1456:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 1457:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1458:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 1459:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Get actual counter mode. 1460:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to 1461:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * check whether or not the counter mode selection feature is supported 1462:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * by a timer instance. 1463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR1 DIR LL_TIM_GetCounterMode\n 1464:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CR1 CMS LL_TIM_GetCounterMode 1465:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 1466:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval Returned value can be one of the following values: 1467:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_COUNTERMODE_UP 1468:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_COUNTERMODE_DOWN 1469:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP 1470:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN 1471:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN 1472:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1473:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_GetCounterMode(const TIM_TypeDef *TIMx) 1474:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 1475:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t counter_mode; 1476:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1477:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** counter_mode = (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CMS)); 1478:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1479:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** if (counter_mode == 0U) 1480:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 1481:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** counter_mode = (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR)); 1482:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 1483:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1484:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return counter_mode; 1485:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 1486:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1487:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 1488:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Enable auto-reload (ARR) preload. 1489:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR1 ARPE LL_TIM_EnableARRPreload 1490:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance ARM GAS /tmp/ccqopZd5.s page 228 1491:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 1492:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1493:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_EnableARRPreload(TIM_TypeDef *TIMx) 1494:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 1495:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** SET_BIT(TIMx->CR1, TIM_CR1_ARPE); 1496:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 1497:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1498:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 1499:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Disable auto-reload (ARR) preload. 1500:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR1 ARPE LL_TIM_DisableARRPreload 1501:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 1502:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 1503:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1504:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_DisableARRPreload(TIM_TypeDef *TIMx) 3091 .loc 5 1504 22 view .LVU1030 3092 .LBB383: 1505:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 1506:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** CLEAR_BIT(TIMx->CR1, TIM_CR1_ARPE); 3093 .loc 5 1506 3 view .LVU1031 3094 005e 4FF08043 mov r3, #1073741824 3095 0062 1A68 ldr r2, [r3] 3096 0064 22F08002 bic r2, r2, #128 3097 0068 1A60 str r2, [r3] 3098 .LVL234: 3099 .loc 5 1506 3 is_stmt 0 view .LVU1032 3100 .LBE383: 3101 .LBE382: 1191:Src/main.c **** LL_TIM_SetTriggerOutput(TIM2, LL_TIM_TRGO_RESET); 3102 .loc 2 1191 3 is_stmt 1 view .LVU1033 3103 .LBB384: 3104 .LBI384: 1507:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 1508:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1509:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 1510:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Indicates whether auto-reload (ARR) preload is enabled. 1511:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR1 ARPE LL_TIM_IsEnabledARRPreload 1512:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 1513:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval State of bit (1 or 0). 1514:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1515:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsEnabledARRPreload(const TIM_TypeDef *TIMx) 1516:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 1517:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return ((READ_BIT(TIMx->CR1, TIM_CR1_ARPE) == (TIM_CR1_ARPE)) ? 1UL : 0UL); 1518:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 1519:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1520:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 1521:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Set the division ratio between the timer clock and the sampling clock used by the dead 1522:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * (when supported) and the digital filters. 1523:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check 1524:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * whether or not the clock division feature is supported by the timer 1525:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * instance. 1526:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR1 CKD LL_TIM_SetClockDivision 1527:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 1528:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param ClockDivision This parameter can be one of the following values: 1529:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CLOCKDIVISION_DIV1 1530:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CLOCKDIVISION_DIV2 1531:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CLOCKDIVISION_DIV4 1532:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None ARM GAS /tmp/ccqopZd5.s page 229 1533:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1534:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_SetClockDivision(TIM_TypeDef *TIMx, uint32_t ClockDivision) 1535:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 1536:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(TIMx->CR1, TIM_CR1_CKD, ClockDivision); 1537:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 1538:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1539:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 1540:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Get the actual division ratio between the timer clock and the sampling clock used by t 1541:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * generators (when supported) and the digital filters. 1542:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check 1543:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * whether or not the clock division feature is supported by the timer 1544:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * instance. 1545:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR1 CKD LL_TIM_GetClockDivision 1546:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 1547:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval Returned value can be one of the following values: 1548:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CLOCKDIVISION_DIV1 1549:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CLOCKDIVISION_DIV2 1550:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CLOCKDIVISION_DIV4 1551:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1552:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_GetClockDivision(const TIM_TypeDef *TIMx) 1553:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 1554:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CKD)); 1555:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 1556:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1557:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 1558:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Set the counter value. 1559:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check 1560:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * whether or not a timer instance supports a 32 bits counter. 1561:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CNT CNT LL_TIM_SetCounter 1562:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 1563:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Counter Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF) 1564:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 1565:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1566:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_SetCounter(TIM_TypeDef *TIMx, uint32_t Counter) 1567:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 1568:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** WRITE_REG(TIMx->CNT, Counter); 1569:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 1570:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1571:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 1572:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Get the counter value. 1573:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check 1574:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * whether or not a timer instance supports a 32 bits counter. 1575:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CNT CNT LL_TIM_GetCounter 1576:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 1577:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF) 1578:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1579:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_GetCounter(const TIM_TypeDef *TIMx) 1580:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 1581:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return (uint32_t)(READ_REG(TIMx->CNT)); 1582:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 1583:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1584:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 1585:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Get the current direction of the counter 1586:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR1 DIR LL_TIM_GetDirection 1587:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 1588:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval Returned value can be one of the following values: 1589:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_COUNTERDIRECTION_UP ARM GAS /tmp/ccqopZd5.s page 230 1590:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_COUNTERDIRECTION_DOWN 1591:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1592:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_GetDirection(const TIM_TypeDef *TIMx) 1593:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 1594:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR)); 1595:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 1596:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1597:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 1598:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Set the prescaler value. 1599:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note The counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1). 1600:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note The prescaler can be changed on the fly as this control register is buffered. The new 1601:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * prescaler ratio is taken into account at the next update event. 1602:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Helper macro @ref __LL_TIM_CALC_PSC can be used to calculate the Prescaler parameter 1603:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll PSC PSC LL_TIM_SetPrescaler 1604:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 1605:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Prescaler between Min_Data=0 and Max_Data=65535 1606:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 1607:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1608:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Prescaler) 1609:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 1610:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** WRITE_REG(TIMx->PSC, Prescaler); 1611:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 1612:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1613:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 1614:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Get the prescaler value. 1615:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll PSC PSC LL_TIM_GetPrescaler 1616:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 1617:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval Prescaler value between Min_Data=0 and Max_Data=65535 1618:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1619:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_GetPrescaler(const TIM_TypeDef *TIMx) 1620:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 1621:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return (uint32_t)(READ_REG(TIMx->PSC)); 1622:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 1623:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1624:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 1625:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Set the auto-reload value. 1626:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note The counter is blocked while the auto-reload value is null. 1627:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check 1628:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * whether or not a timer instance supports a 32 bits counter. 1629:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Helper macro @ref __LL_TIM_CALC_ARR can be used to calculate the AutoReload parameter 1630:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll ARR ARR LL_TIM_SetAutoReload 1631:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 1632:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param AutoReload between Min_Data=0 and Max_Data=65535 1633:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 1634:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1635:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_SetAutoReload(TIM_TypeDef *TIMx, uint32_t AutoReload) 1636:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 1637:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** WRITE_REG(TIMx->ARR, AutoReload); 1638:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 1639:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1640:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 1641:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Get the auto-reload value. 1642:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll ARR ARR LL_TIM_GetAutoReload 1643:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check 1644:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * whether or not a timer instance supports a 32 bits counter. 1645:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 1646:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval Auto-reload value ARM GAS /tmp/ccqopZd5.s page 231 1647:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1648:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_GetAutoReload(const TIM_TypeDef *TIMx) 1649:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 1650:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return (uint32_t)(READ_REG(TIMx->ARR)); 1651:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 1652:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1653:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 1654:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Set the repetition counter value. 1655:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note For advanced timer instances RepetitionCounter can be up to 65535. 1656:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check 1657:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * whether or not a timer instance supports a repetition counter. 1658:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll RCR REP LL_TIM_SetRepetitionCounter 1659:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 1660:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param RepetitionCounter between Min_Data=0 and Max_Data=255 or 65535 for advanced timer. 1661:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 1662:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1663:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_SetRepetitionCounter(TIM_TypeDef *TIMx, uint32_t RepetitionCounter) 1664:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 1665:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** WRITE_REG(TIMx->RCR, RepetitionCounter); 1666:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 1667:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1668:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 1669:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Get the repetition counter value. 1670:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check 1671:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * whether or not a timer instance supports a repetition counter. 1672:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll RCR REP LL_TIM_GetRepetitionCounter 1673:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 1674:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval Repetition counter value 1675:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1676:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_GetRepetitionCounter(const TIM_TypeDef *TIMx) 1677:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 1678:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return (uint32_t)(READ_REG(TIMx->RCR)); 1679:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 1680:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1681:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 1682:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Force a continuous copy of the update interrupt flag (UIF) into the timer counter regis 1683:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note This allows both the counter value and a potential roll-over condition signalled by the U 1684:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * in an atomic way. 1685:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR1 UIFREMAP LL_TIM_EnableUIFRemap 1686:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 1687:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 1688:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1689:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_EnableUIFRemap(TIM_TypeDef *TIMx) 1690:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 1691:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** SET_BIT(TIMx->CR1, TIM_CR1_UIFREMAP); 1692:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 1693:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1694:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 1695:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Disable update interrupt flag (UIF) remapping. 1696:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR1 UIFREMAP LL_TIM_DisableUIFRemap 1697:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 1698:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 1699:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1700:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_DisableUIFRemap(TIM_TypeDef *TIMx) 1701:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 1702:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** CLEAR_BIT(TIMx->CR1, TIM_CR1_UIFREMAP); 1703:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } ARM GAS /tmp/ccqopZd5.s page 232 1704:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1705:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 1706:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Indicate whether update interrupt flag (UIF) copy is set. 1707:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Counter Counter value 1708:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval State of bit (1 or 0). 1709:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1710:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsActiveUIFCPY(const uint32_t Counter) 1711:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 1712:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return (((Counter & TIM_CNT_UIFCPY) == (TIM_CNT_UIFCPY)) ? 1UL : 0UL); 1713:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 1714:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1715:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 1716:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} 1717:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1718:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1719:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EF_Capture_Compare Capture Compare configuration 1720:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ 1721:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1722:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 1723:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Enable the capture/compare control bits (CCxE, CCxNE and OCxM) preload. 1724:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note CCxE, CCxNE and OCxM bits are preloaded, after having been written, 1725:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * they are updated only when a commutation event (COM) occurs. 1726:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Only on channels that have a complementary output. 1727:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check 1728:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * whether or not a timer instance is able to generate a commutation event. 1729:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR2 CCPC LL_TIM_CC_EnablePreload 1730:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 1731:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 1732:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1733:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_CC_EnablePreload(TIM_TypeDef *TIMx) 1734:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 1735:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** SET_BIT(TIMx->CR2, TIM_CR2_CCPC); 1736:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 1737:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1738:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 1739:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Disable the capture/compare control bits (CCxE, CCxNE and OCxM) preload. 1740:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check 1741:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * whether or not a timer instance is able to generate a commutation event. 1742:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR2 CCPC LL_TIM_CC_DisablePreload 1743:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 1744:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 1745:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1746:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_CC_DisablePreload(TIM_TypeDef *TIMx) 1747:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 1748:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** CLEAR_BIT(TIMx->CR2, TIM_CR2_CCPC); 1749:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 1750:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1751:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 1752:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Indicates whether the capture/compare control bits (CCxE, CCxNE and OCxM) preload is en 1753:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR2 CCPC LL_TIM_CC_IsEnabledPreload 1754:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 1755:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval State of bit (1 or 0). 1756:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1757:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledPreload(const TIM_TypeDef *TIMx) 1758:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 1759:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return ((READ_BIT(TIMx->CR2, TIM_CR2_CCPC) == (TIM_CR2_CCPC)) ? 1UL : 0UL); 1760:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } ARM GAS /tmp/ccqopZd5.s page 233 1761:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1762:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 1763:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Set the updated source of the capture/compare control bits (CCxE, CCxNE and OCxM). 1764:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check 1765:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * whether or not a timer instance is able to generate a commutation event. 1766:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR2 CCUS LL_TIM_CC_SetUpdate 1767:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 1768:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param CCUpdateSource This parameter can be one of the following values: 1769:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CCUPDATESOURCE_COMG_ONLY 1770:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI 1771:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 1772:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1773:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_CC_SetUpdate(TIM_TypeDef *TIMx, uint32_t CCUpdateSource) 1774:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 1775:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(TIMx->CR2, TIM_CR2_CCUS, CCUpdateSource); 1776:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 1777:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1778:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 1779:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Set the trigger of the capture/compare DMA request. 1780:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR2 CCDS LL_TIM_CC_SetDMAReqTrigger 1781:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 1782:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param DMAReqTrigger This parameter can be one of the following values: 1783:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CCDMAREQUEST_CC 1784:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CCDMAREQUEST_UPDATE 1785:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 1786:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1787:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_CC_SetDMAReqTrigger(TIM_TypeDef *TIMx, uint32_t DMAReqTrigger) 1788:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 1789:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(TIMx->CR2, TIM_CR2_CCDS, DMAReqTrigger); 1790:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 1791:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1792:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 1793:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Get actual trigger of the capture/compare DMA request. 1794:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR2 CCDS LL_TIM_CC_GetDMAReqTrigger 1795:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 1796:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval Returned value can be one of the following values: 1797:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CCDMAREQUEST_CC 1798:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CCDMAREQUEST_UPDATE 1799:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1800:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_CC_GetDMAReqTrigger(const TIM_TypeDef *TIMx) 1801:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 1802:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return (uint32_t)(READ_BIT(TIMx->CR2, TIM_CR2_CCDS)); 1803:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 1804:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1805:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 1806:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Set the lock level to freeze the 1807:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * configuration of several capture/compare parameters. 1808:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not 1809:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * the lock mechanism is supported by a timer instance. 1810:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll BDTR LOCK LL_TIM_CC_SetLockLevel 1811:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 1812:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param LockLevel This parameter can be one of the following values: 1813:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_LOCKLEVEL_OFF 1814:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_LOCKLEVEL_1 1815:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_LOCKLEVEL_2 1816:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_LOCKLEVEL_3 1817:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None ARM GAS /tmp/ccqopZd5.s page 234 1818:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1819:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_CC_SetLockLevel(TIM_TypeDef *TIMx, uint32_t LockLevel) 1820:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 1821:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(TIMx->BDTR, TIM_BDTR_LOCK, LockLevel); 1822:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 1823:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1824:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 1825:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Enable capture/compare channels. 1826:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCER CC1E LL_TIM_CC_EnableChannel\n 1827:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC1NE LL_TIM_CC_EnableChannel\n 1828:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC2E LL_TIM_CC_EnableChannel\n 1829:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC2NE LL_TIM_CC_EnableChannel\n 1830:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC3E LL_TIM_CC_EnableChannel\n 1831:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC3NE LL_TIM_CC_EnableChannel\n 1832:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC4E LL_TIM_CC_EnableChannel\n 1833:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC5E LL_TIM_CC_EnableChannel\n 1834:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC6E LL_TIM_CC_EnableChannel 1835:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 1836:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Channels This parameter can be a combination of the following values: 1837:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 1838:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1N 1839:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 1840:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2N 1841:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 1842:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3N 1843:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 1844:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH5 1845:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH6 1846:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 1847:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1848:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_CC_EnableChannel(TIM_TypeDef *TIMx, uint32_t Channels) 1849:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 1850:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** SET_BIT(TIMx->CCER, Channels); 1851:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 1852:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1853:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 1854:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Disable capture/compare channels. 1855:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCER CC1E LL_TIM_CC_DisableChannel\n 1856:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC1NE LL_TIM_CC_DisableChannel\n 1857:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC2E LL_TIM_CC_DisableChannel\n 1858:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC2NE LL_TIM_CC_DisableChannel\n 1859:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC3E LL_TIM_CC_DisableChannel\n 1860:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC3NE LL_TIM_CC_DisableChannel\n 1861:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC4E LL_TIM_CC_DisableChannel\n 1862:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC5E LL_TIM_CC_DisableChannel\n 1863:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC6E LL_TIM_CC_DisableChannel 1864:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 1865:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Channels This parameter can be a combination of the following values: 1866:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 1867:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1N 1868:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 1869:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2N 1870:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 1871:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3N 1872:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 1873:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH5 1874:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH6 ARM GAS /tmp/ccqopZd5.s page 235 1875:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 1876:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1877:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_CC_DisableChannel(TIM_TypeDef *TIMx, uint32_t Channels) 1878:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 1879:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** CLEAR_BIT(TIMx->CCER, Channels); 1880:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 1881:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1882:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 1883:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Indicate whether channel(s) is(are) enabled. 1884:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCER CC1E LL_TIM_CC_IsEnabledChannel\n 1885:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC1NE LL_TIM_CC_IsEnabledChannel\n 1886:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC2E LL_TIM_CC_IsEnabledChannel\n 1887:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC2NE LL_TIM_CC_IsEnabledChannel\n 1888:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC3E LL_TIM_CC_IsEnabledChannel\n 1889:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC3NE LL_TIM_CC_IsEnabledChannel\n 1890:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC4E LL_TIM_CC_IsEnabledChannel\n 1891:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC5E LL_TIM_CC_IsEnabledChannel\n 1892:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC6E LL_TIM_CC_IsEnabledChannel 1893:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 1894:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Channels This parameter can be a combination of the following values: 1895:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 1896:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1N 1897:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 1898:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2N 1899:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 1900:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3N 1901:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 1902:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH5 1903:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH6 1904:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval State of bit (1 or 0). 1905:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1906:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledChannel(const TIM_TypeDef *TIMx, uint32_t Channels) 1907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 1908:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return ((READ_BIT(TIMx->CCER, Channels) == (Channels)) ? 1UL : 0UL); 1909:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 1910:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1911:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 1912:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} 1913:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1914:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1915:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EF_Output_Channel Output channel configuration 1916:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ 1917:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 1919:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Configure an output channel. 1920:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCMR1 CC1S LL_TIM_OC_ConfigOutput\n 1921:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR1 CC2S LL_TIM_OC_ConfigOutput\n 1922:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 CC3S LL_TIM_OC_ConfigOutput\n 1923:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 CC4S LL_TIM_OC_ConfigOutput\n 1924:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR3 CC5S LL_TIM_OC_ConfigOutput\n 1925:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR3 CC6S LL_TIM_OC_ConfigOutput\n 1926:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC1P LL_TIM_OC_ConfigOutput\n 1927:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC2P LL_TIM_OC_ConfigOutput\n 1928:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC3P LL_TIM_OC_ConfigOutput\n 1929:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC4P LL_TIM_OC_ConfigOutput\n 1930:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC5P LL_TIM_OC_ConfigOutput\n 1931:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC6P LL_TIM_OC_ConfigOutput\n ARM GAS /tmp/ccqopZd5.s page 236 1932:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CR2 OIS1 LL_TIM_OC_ConfigOutput\n 1933:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CR2 OIS2 LL_TIM_OC_ConfigOutput\n 1934:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CR2 OIS3 LL_TIM_OC_ConfigOutput\n 1935:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CR2 OIS4 LL_TIM_OC_ConfigOutput\n 1936:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CR2 OIS5 LL_TIM_OC_ConfigOutput\n 1937:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CR2 OIS6 LL_TIM_OC_ConfigOutput 1938:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 1939:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Channel This parameter can be one of the following values: 1940:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 1941:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 1942:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 1943:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 1944:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH5 1945:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH6 1946:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Configuration This parameter must be a combination of all the following values: 1947:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCPOLARITY_HIGH or @ref LL_TIM_OCPOLARITY_LOW 1948:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCIDLESTATE_LOW or @ref LL_TIM_OCIDLESTATE_HIGH 1949:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 1950:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1951:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configura 1952:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 1953:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 1954:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iC 1955:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** CLEAR_BIT(*pReg, (TIM_CCMR1_CC1S << SHIFT_TAB_OCxx[iChannel])); 1956:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]), 1957:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** (Configuration & TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]); 1958:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]), 1959:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** (Configuration & TIM_CR2_OIS1) << SHIFT_TAB_OISx[iChannel]); 1960:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 1961:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1962:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 1963:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Define the behavior of the output reference signal OCxREF from which 1964:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * OCx and OCxN (when relevant) are derived. 1965:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCMR1 OC1M LL_TIM_OC_SetMode\n 1966:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR1 OC2M LL_TIM_OC_SetMode\n 1967:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 OC3M LL_TIM_OC_SetMode\n 1968:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 OC4M LL_TIM_OC_SetMode\n 1969:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR3 OC5M LL_TIM_OC_SetMode\n 1970:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR3 OC6M LL_TIM_OC_SetMode 1971:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 1972:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Channel This parameter can be one of the following values: 1973:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 1974:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 1975:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 1976:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 1977:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH5 1978:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH6 1979:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Mode This parameter can be one of the following values: 1980:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_FROZEN 1981:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_ACTIVE 1982:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_INACTIVE 1983:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_TOGGLE 1984:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE 1985:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE 1986:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_PWM1 1987:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_PWM2 1988:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_RETRIG_OPM1 ARM GAS /tmp/ccqopZd5.s page 237 1989:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_RETRIG_OPM2 1990:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_COMBINED_PWM1 1991:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_COMBINED_PWM2 1992:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_ASYMMETRIC_PWM1 1993:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_ASYMMETRIC_PWM2 1994:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 1995:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1996:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Mode) 1997:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 1998:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 1999:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iC 2000:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel]), Mode << SHIFT 2001:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 2002:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 2003:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 2004:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Get the output compare mode of an output channel. 2005:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCMR1 OC1M LL_TIM_OC_GetMode\n 2006:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR1 OC2M LL_TIM_OC_GetMode\n 2007:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 OC3M LL_TIM_OC_GetMode\n 2008:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 OC4M LL_TIM_OC_GetMode\n 2009:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR3 OC5M LL_TIM_OC_GetMode\n 2010:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR3 OC6M LL_TIM_OC_GetMode 2011:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 2012:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Channel This parameter can be one of the following values: 2013:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 2014:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 2015:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 2016:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 2017:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH5 2018:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH6 2019:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval Returned value can be one of the following values: 2020:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_FROZEN 2021:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_ACTIVE 2022:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_INACTIVE 2023:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_TOGGLE 2024:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE 2025:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE 2026:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_PWM1 2027:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_PWM2 2028:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_RETRIG_OPM1 2029:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_RETRIG_OPM2 2030:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_COMBINED_PWM1 2031:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_COMBINED_PWM2 2032:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_ASYMMETRIC_PWM1 2033:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_ASYMMETRIC_PWM2 2034:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 2035:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_OC_GetMode(const TIM_TypeDef *TIMx, uint32_t Channel) 2036:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 2037:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 2038:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CC 2039:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return (READ_BIT(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel])) >> SHIFT 2040:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 2041:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 2042:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 2043:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Set the polarity of an output channel. 2044:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCER CC1P LL_TIM_OC_SetPolarity\n 2045:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC1NP LL_TIM_OC_SetPolarity\n ARM GAS /tmp/ccqopZd5.s page 238 2046:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC2P LL_TIM_OC_SetPolarity\n 2047:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC2NP LL_TIM_OC_SetPolarity\n 2048:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC3P LL_TIM_OC_SetPolarity\n 2049:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC3NP LL_TIM_OC_SetPolarity\n 2050:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC4P LL_TIM_OC_SetPolarity\n 2051:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC5P LL_TIM_OC_SetPolarity\n 2052:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC6P LL_TIM_OC_SetPolarity 2053:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 2054:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Channel This parameter can be one of the following values: 2055:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 2056:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1N 2057:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 2058:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2N 2059:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 2060:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3N 2061:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 2062:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH5 2063:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH6 2064:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Polarity This parameter can be one of the following values: 2065:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCPOLARITY_HIGH 2066:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCPOLARITY_LOW 2067:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 2068:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 2069:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_OC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Polarity) 2070:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 2071:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 2072:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]), Polarity << SHIFT_TAB_CCxP[i 2073:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 2074:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 2075:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 2076:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Get the polarity of an output channel. 2077:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCER CC1P LL_TIM_OC_GetPolarity\n 2078:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC1NP LL_TIM_OC_GetPolarity\n 2079:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC2P LL_TIM_OC_GetPolarity\n 2080:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC2NP LL_TIM_OC_GetPolarity\n 2081:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC3P LL_TIM_OC_GetPolarity\n 2082:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC3NP LL_TIM_OC_GetPolarity\n 2083:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC4P LL_TIM_OC_GetPolarity\n 2084:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC5P LL_TIM_OC_GetPolarity\n 2085:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC6P LL_TIM_OC_GetPolarity 2086:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 2087:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Channel This parameter can be one of the following values: 2088:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 2089:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1N 2090:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 2091:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2N 2092:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 2093:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3N 2094:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 2095:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH5 2096:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH6 2097:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval Returned value can be one of the following values: 2098:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCPOLARITY_HIGH 2099:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCPOLARITY_LOW 2100:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 2101:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity(const TIM_TypeDef *TIMx, uint32_t Channel) 2102:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { ARM GAS /tmp/ccqopZd5.s page 239 2103:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 2104:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return (READ_BIT(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel])) >> SHIFT_TAB_CCxP[iChan 2105:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 2106:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 2107:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 2108:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Set the IDLE state of an output channel 2109:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note This function is significant only for the timer instances 2110:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * supporting the break feature. Macro IS_TIM_BREAK_INSTANCE(TIMx) 2111:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * can be used to check whether or not a timer instance provides 2112:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * a break input. 2113:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR2 OIS1 LL_TIM_OC_SetIdleState\n 2114:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CR2 OIS2N LL_TIM_OC_SetIdleState\n 2115:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CR2 OIS2 LL_TIM_OC_SetIdleState\n 2116:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CR2 OIS2N LL_TIM_OC_SetIdleState\n 2117:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CR2 OIS3 LL_TIM_OC_SetIdleState\n 2118:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CR2 OIS3N LL_TIM_OC_SetIdleState\n 2119:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CR2 OIS4 LL_TIM_OC_SetIdleState\n 2120:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CR2 OIS5 LL_TIM_OC_SetIdleState\n 2121:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CR2 OIS6 LL_TIM_OC_SetIdleState 2122:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 2123:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Channel This parameter can be one of the following values: 2124:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 2125:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1N 2126:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 2127:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2N 2128:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 2129:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3N 2130:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 2131:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH5 2132:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH6 2133:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param IdleState This parameter can be one of the following values: 2134:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCIDLESTATE_LOW 2135:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCIDLESTATE_HIGH 2136:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 2137:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 2138:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_OC_SetIdleState(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t IdleState 2139:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 2140:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 2141:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]), IdleState << SHIFT_TAB_OISx[iC 2142:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 2143:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 2144:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 2145:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Get the IDLE state of an output channel 2146:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR2 OIS1 LL_TIM_OC_GetIdleState\n 2147:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CR2 OIS2N LL_TIM_OC_GetIdleState\n 2148:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CR2 OIS2 LL_TIM_OC_GetIdleState\n 2149:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CR2 OIS2N LL_TIM_OC_GetIdleState\n 2150:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CR2 OIS3 LL_TIM_OC_GetIdleState\n 2151:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CR2 OIS3N LL_TIM_OC_GetIdleState\n 2152:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CR2 OIS4 LL_TIM_OC_GetIdleState\n 2153:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CR2 OIS5 LL_TIM_OC_GetIdleState\n 2154:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CR2 OIS6 LL_TIM_OC_GetIdleState 2155:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 2156:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Channel This parameter can be one of the following values: 2157:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 2158:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1N 2159:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 ARM GAS /tmp/ccqopZd5.s page 240 2160:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2N 2161:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 2162:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3N 2163:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 2164:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH5 2165:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH6 2166:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval Returned value can be one of the following values: 2167:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCIDLESTATE_LOW 2168:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCIDLESTATE_HIGH 2169:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 2170:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_OC_GetIdleState(const TIM_TypeDef *TIMx, uint32_t Channel) 2171:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 2172:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 2173:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return (READ_BIT(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel])) >> SHIFT_TAB_OISx[iChanne 2174:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 2175:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 2176:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 2177:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Enable fast mode for the output channel. 2178:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Acts only if the channel is configured in PWM1 or PWM2 mode. 2179:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCMR1 OC1FE LL_TIM_OC_EnableFast\n 2180:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR1 OC2FE LL_TIM_OC_EnableFast\n 2181:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 OC3FE LL_TIM_OC_EnableFast\n 2182:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 OC4FE LL_TIM_OC_EnableFast\n 2183:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR3 OC5FE LL_TIM_OC_EnableFast\n 2184:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR3 OC6FE LL_TIM_OC_EnableFast 2185:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 2186:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Channel This parameter can be one of the following values: 2187:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 2188:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 2189:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 2190:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 2191:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH5 2192:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH6 2193:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 2194:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 2195:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_OC_EnableFast(TIM_TypeDef *TIMx, uint32_t Channel) 2196:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 2197:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 2198:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iC 2199:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** SET_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel])); 2200:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 2201:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 2202:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 2203:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 2204:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Disable fast mode for the output channel. 2205:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCMR1 OC1FE LL_TIM_OC_DisableFast\n 2206:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR1 OC2FE LL_TIM_OC_DisableFast\n 2207:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 OC3FE LL_TIM_OC_DisableFast\n 2208:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 OC4FE LL_TIM_OC_DisableFast\n 2209:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR3 OC5FE LL_TIM_OC_DisableFast\n 2210:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR3 OC6FE LL_TIM_OC_DisableFast 2211:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 2212:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Channel This parameter can be one of the following values: 2213:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 2214:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 2215:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 2216:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 ARM GAS /tmp/ccqopZd5.s page 241 2217:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH5 2218:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH6 2219:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 2220:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 2221:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_OC_DisableFast(TIM_TypeDef *TIMx, uint32_t Channel) 2222:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 2223:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 2224:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iC 2225:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** CLEAR_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel])); 2226:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 2227:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 2228:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 2229:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 2230:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Indicates whether fast mode is enabled for the output channel. 2231:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCMR1 OC1FE LL_TIM_OC_IsEnabledFast\n 2232:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR1 OC2FE LL_TIM_OC_IsEnabledFast\n 2233:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 OC3FE LL_TIM_OC_IsEnabledFast\n 2234:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 OC4FE LL_TIM_OC_IsEnabledFast\n 2235:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR3 OC5FE LL_TIM_OC_IsEnabledFast\n 2236:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR3 OC6FE LL_TIM_OC_IsEnabledFast 2237:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 2238:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Channel This parameter can be one of the following values: 2239:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 2240:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 2241:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 2242:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 2243:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH5 2244:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH6 2245:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval State of bit (1 or 0). 2246:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 2247:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(const TIM_TypeDef *TIMx, uint32_t Channel) 2248:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 2249:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 2250:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CC 2251:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t bitfield = TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]; 2252:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL); 2253:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 2254:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 2255:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 2256:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Enable compare register (TIMx_CCRx) preload for the output channel. 2257:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCMR1 OC1PE LL_TIM_OC_EnablePreload\n 2258:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR1 OC2PE LL_TIM_OC_EnablePreload\n 2259:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 OC3PE LL_TIM_OC_EnablePreload\n 2260:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 OC4PE LL_TIM_OC_EnablePreload\n 2261:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR3 OC5PE LL_TIM_OC_EnablePreload\n 2262:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR3 OC6PE LL_TIM_OC_EnablePreload 2263:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 2264:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Channel This parameter can be one of the following values: 2265:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 2266:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 2267:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 2268:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 2269:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH5 2270:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH6 2271:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 2272:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 2273:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_OC_EnablePreload(TIM_TypeDef *TIMx, uint32_t Channel) ARM GAS /tmp/ccqopZd5.s page 242 2274:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 2275:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 2276:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iC 2277:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** SET_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel])); 2278:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 2279:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 2280:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 2281:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Disable compare register (TIMx_CCRx) preload for the output channel. 2282:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCMR1 OC1PE LL_TIM_OC_DisablePreload\n 2283:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR1 OC2PE LL_TIM_OC_DisablePreload\n 2284:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 OC3PE LL_TIM_OC_DisablePreload\n 2285:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 OC4PE LL_TIM_OC_DisablePreload\n 2286:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR3 OC5PE LL_TIM_OC_DisablePreload\n 2287:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR3 OC6PE LL_TIM_OC_DisablePreload 2288:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 2289:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Channel This parameter can be one of the following values: 2290:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 2291:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 2292:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 2293:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 2294:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH5 2295:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH6 2296:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 2297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 2298:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_OC_DisablePreload(TIM_TypeDef *TIMx, uint32_t Channel) 2299:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 2300:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 2301:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iC 2302:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** CLEAR_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel])); 2303:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 2304:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 2305:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 2306:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Indicates whether compare register (TIMx_CCRx) preload is enabled for the output channe 2307:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCMR1 OC1PE LL_TIM_OC_IsEnabledPreload\n 2308:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR1 OC2PE LL_TIM_OC_IsEnabledPreload\n 2309:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 OC3PE LL_TIM_OC_IsEnabledPreload\n 2310:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 OC4PE LL_TIM_OC_IsEnabledPreload\n 2311:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR3 OC5PE LL_TIM_OC_IsEnabledPreload\n 2312:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR3 OC6PE LL_TIM_OC_IsEnabledPreload 2313:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 2314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Channel This parameter can be one of the following values: 2315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 2316:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 2317:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 2318:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 2319:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH5 2320:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH6 2321:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval State of bit (1 or 0). 2322:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 2323:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(const TIM_TypeDef *TIMx, uint32_t Channel) 2324:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 2325:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 2326:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CC 2327:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t bitfield = TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]; 2328:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL); 2329:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 2330:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** ARM GAS /tmp/ccqopZd5.s page 243 2331:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 2332:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Enable clearing the output channel on an external event. 2333:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note This function can only be used in Output compare and PWM modes. It does not work in Force 2334:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether 2335:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * or not a timer instance can clear the OCxREF signal on an external event. 2336:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCMR1 OC1CE LL_TIM_OC_EnableClear\n 2337:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR1 OC2CE LL_TIM_OC_EnableClear\n 2338:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 OC3CE LL_TIM_OC_EnableClear\n 2339:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 OC4CE LL_TIM_OC_EnableClear\n 2340:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR3 OC5CE LL_TIM_OC_EnableClear\n 2341:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR3 OC6CE LL_TIM_OC_EnableClear 2342:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 2343:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Channel This parameter can be one of the following values: 2344:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 2345:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 2346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 2347:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 2348:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH5 2349:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH6 2350:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 2351:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 2352:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_OC_EnableClear(TIM_TypeDef *TIMx, uint32_t Channel) 2353:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 2354:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 2355:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iC 2356:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** SET_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel])); 2357:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 2358:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 2359:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 2360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Disable clearing the output channel on an external event. 2361:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether 2362:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * or not a timer instance can clear the OCxREF signal on an external event. 2363:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCMR1 OC1CE LL_TIM_OC_DisableClear\n 2364:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR1 OC2CE LL_TIM_OC_DisableClear\n 2365:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 OC3CE LL_TIM_OC_DisableClear\n 2366:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 OC4CE LL_TIM_OC_DisableClear\n 2367:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR3 OC5CE LL_TIM_OC_DisableClear\n 2368:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR3 OC6CE LL_TIM_OC_DisableClear 2369:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 2370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Channel This parameter can be one of the following values: 2371:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 2372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 2373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 2374:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 2375:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH5 2376:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH6 2377:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 2378:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 2379:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_OC_DisableClear(TIM_TypeDef *TIMx, uint32_t Channel) 2380:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 2381:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 2382:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iC 2383:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** CLEAR_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel])); 2384:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 2385:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 2386:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 2387:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Indicates clearing the output channel on an external event is enabled for the output ch ARM GAS /tmp/ccqopZd5.s page 244 2388:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note This function enables clearing the output channel on an external event. 2389:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note This function can only be used in Output compare and PWM modes. It does not work in Force 2390:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether 2391:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * or not a timer instance can clear the OCxREF signal on an external event. 2392:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCMR1 OC1CE LL_TIM_OC_IsEnabledClear\n 2393:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR1 OC2CE LL_TIM_OC_IsEnabledClear\n 2394:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 OC3CE LL_TIM_OC_IsEnabledClear\n 2395:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 OC4CE LL_TIM_OC_IsEnabledClear\n 2396:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR3 OC5CE LL_TIM_OC_IsEnabledClear\n 2397:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR3 OC6CE LL_TIM_OC_IsEnabledClear 2398:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 2399:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Channel This parameter can be one of the following values: 2400:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 2401:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 2402:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 2403:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 2404:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH5 2405:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH6 2406:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval State of bit (1 or 0). 2407:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 2408:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(const TIM_TypeDef *TIMx, uint32_t Channel) 2409:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 2410:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 2411:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CC 2412:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t bitfield = TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]; 2413:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL); 2414:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 2415:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 2416:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 2417:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Set the dead-time delay (delay inserted between the rising edge of the OCxREF signal an 2418:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * the Ocx and OCxN signals). 2419:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not 2420:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * dead-time insertion feature is supported by a timer instance. 2421:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Helper macro @ref __LL_TIM_CALC_DEADTIME can be used to calculate the DeadTime parameter 2422:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll BDTR DTG LL_TIM_OC_SetDeadTime 2423:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 2424:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param DeadTime between Min_Data=0 and Max_Data=255 2425:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 2426:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 2427:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_OC_SetDeadTime(TIM_TypeDef *TIMx, uint32_t DeadTime) 2428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 2429:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(TIMx->BDTR, TIM_BDTR_DTG, DeadTime); 2430:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 2431:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 2432:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 2433:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Set compare value for output channel 1 (TIMx_CCR1). 2434:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF. 2435:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check 2436:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * whether or not a timer instance supports a 32 bits counter. 2437:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not 2438:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * output channel 1 is supported by a timer instance. 2439:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCR1 CCR1 LL_TIM_OC_SetCompareCH1 2440:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 2441:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param CompareValue between Min_Data=0 and Max_Data=65535 2442:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 2443:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 2444:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_OC_SetCompareCH1(TIM_TypeDef *TIMx, uint32_t CompareValue) ARM GAS /tmp/ccqopZd5.s page 245 2445:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 2446:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** WRITE_REG(TIMx->CCR1, CompareValue); 2447:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 2448:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 2449:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 2450:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Set compare value for output channel 2 (TIMx_CCR2). 2451:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF. 2452:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check 2453:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * whether or not a timer instance supports a 32 bits counter. 2454:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not 2455:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * output channel 2 is supported by a timer instance. 2456:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCR2 CCR2 LL_TIM_OC_SetCompareCH2 2457:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 2458:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param CompareValue between Min_Data=0 and Max_Data=65535 2459:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 2460:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 2461:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_OC_SetCompareCH2(TIM_TypeDef *TIMx, uint32_t CompareValue) 2462:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 2463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** WRITE_REG(TIMx->CCR2, CompareValue); 2464:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 2465:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 2466:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 2467:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Set compare value for output channel 3 (TIMx_CCR3). 2468:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF. 2469:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check 2470:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * whether or not a timer instance supports a 32 bits counter. 2471:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not 2472:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * output channel is supported by a timer instance. 2473:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCR3 CCR3 LL_TIM_OC_SetCompareCH3 2474:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 2475:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param CompareValue between Min_Data=0 and Max_Data=65535 2476:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 2477:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 2478:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_OC_SetCompareCH3(TIM_TypeDef *TIMx, uint32_t CompareValue) 2479:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 2480:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** WRITE_REG(TIMx->CCR3, CompareValue); 2481:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 2482:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 2483:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 2484:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Set compare value for output channel 4 (TIMx_CCR4). 2485:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF. 2486:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check 2487:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * whether or not a timer instance supports a 32 bits counter. 2488:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not 2489:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * output channel 4 is supported by a timer instance. 2490:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCR4 CCR4 LL_TIM_OC_SetCompareCH4 2491:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 2492:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param CompareValue between Min_Data=0 and Max_Data=65535 2493:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 2494:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 2495:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_OC_SetCompareCH4(TIM_TypeDef *TIMx, uint32_t CompareValue) 2496:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 2497:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** WRITE_REG(TIMx->CCR4, CompareValue); 2498:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 2499:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 2500:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 2501:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Set compare value for output channel 5 (TIMx_CCR5). ARM GAS /tmp/ccqopZd5.s page 246 2502:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not 2503:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * output channel 5 is supported by a timer instance. 2504:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCR5 CCR5 LL_TIM_OC_SetCompareCH5 2505:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 2506:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param CompareValue between Min_Data=0 and Max_Data=65535 2507:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 2508:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 2509:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_OC_SetCompareCH5(TIM_TypeDef *TIMx, uint32_t CompareValue) 2510:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 2511:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(TIMx->CCR5, TIM_CCR5_CCR5, CompareValue); 2512:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 2513:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 2514:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 2515:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Set compare value for output channel 6 (TIMx_CCR6). 2516:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not 2517:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * output channel 6 is supported by a timer instance. 2518:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCR6 CCR6 LL_TIM_OC_SetCompareCH6 2519:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 2520:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param CompareValue between Min_Data=0 and Max_Data=65535 2521:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 2522:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 2523:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_OC_SetCompareCH6(TIM_TypeDef *TIMx, uint32_t CompareValue) 2524:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 2525:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** WRITE_REG(TIMx->CCR6, CompareValue); 2526:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 2527:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 2528:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 2529:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Get compare value (TIMx_CCR1) set for output channel 1. 2530:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFF 2531:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check 2532:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * whether or not a timer instance supports a 32 bits counter. 2533:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not 2534:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * output channel 1 is supported by a timer instance. 2535:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCR1 CCR1 LL_TIM_OC_GetCompareCH1 2536:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 2537:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval CompareValue (between Min_Data=0 and Max_Data=65535) 2538:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 2539:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH1(const TIM_TypeDef *TIMx) 2540:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 2541:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return (uint32_t)(READ_REG(TIMx->CCR1)); 2542:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 2543:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 2544:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 2545:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Get compare value (TIMx_CCR2) set for output channel 2. 2546:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFF 2547:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check 2548:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * whether or not a timer instance supports a 32 bits counter. 2549:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not 2550:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * output channel 2 is supported by a timer instance. 2551:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCR2 CCR2 LL_TIM_OC_GetCompareCH2 2552:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 2553:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval CompareValue (between Min_Data=0 and Max_Data=65535) 2554:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 2555:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH2(const TIM_TypeDef *TIMx) 2556:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 2557:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return (uint32_t)(READ_REG(TIMx->CCR2)); 2558:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } ARM GAS /tmp/ccqopZd5.s page 247 2559:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 2560:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 2561:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Get compare value (TIMx_CCR3) set for output channel 3. 2562:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFF 2563:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check 2564:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * whether or not a timer instance supports a 32 bits counter. 2565:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not 2566:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * output channel 3 is supported by a timer instance. 2567:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCR3 CCR3 LL_TIM_OC_GetCompareCH3 2568:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 2569:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval CompareValue (between Min_Data=0 and Max_Data=65535) 2570:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 2571:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH3(const TIM_TypeDef *TIMx) 2572:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 2573:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return (uint32_t)(READ_REG(TIMx->CCR3)); 2574:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 2575:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 2576:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 2577:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Get compare value (TIMx_CCR4) set for output channel 4. 2578:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFF 2579:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check 2580:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * whether or not a timer instance supports a 32 bits counter. 2581:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not 2582:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * output channel 4 is supported by a timer instance. 2583:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCR4 CCR4 LL_TIM_OC_GetCompareCH4 2584:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 2585:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval CompareValue (between Min_Data=0 and Max_Data=65535) 2586:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 2587:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH4(const TIM_TypeDef *TIMx) 2588:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 2589:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return (uint32_t)(READ_REG(TIMx->CCR4)); 2590:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 2591:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 2592:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 2593:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Get compare value (TIMx_CCR5) set for output channel 5. 2594:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not 2595:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * output channel 5 is supported by a timer instance. 2596:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCR5 CCR5 LL_TIM_OC_GetCompareCH5 2597:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 2598:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval CompareValue (between Min_Data=0 and Max_Data=65535) 2599:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 2600:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH5(const TIM_TypeDef *TIMx) 2601:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 2602:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return (uint32_t)(READ_BIT(TIMx->CCR5, TIM_CCR5_CCR5)); 2603:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 2604:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 2605:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 2606:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Get compare value (TIMx_CCR6) set for output channel 6. 2607:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not 2608:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * output channel 6 is supported by a timer instance. 2609:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCR6 CCR6 LL_TIM_OC_GetCompareCH6 2610:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 2611:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval CompareValue (between Min_Data=0 and Max_Data=65535) 2612:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 2613:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH6(const TIM_TypeDef *TIMx) 2614:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 2615:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return (uint32_t)(READ_REG(TIMx->CCR6)); ARM GAS /tmp/ccqopZd5.s page 248 2616:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 2617:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 2618:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 2619:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Select on which reference signal the OC5REF is combined to. 2620:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_COMBINED3PHASEPWM_INSTANCE(TIMx) can be used to check 2621:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * whether or not a timer instance supports the combined 3-phase PWM mode. 2622:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCR5 GC5C3 LL_TIM_SetCH5CombinedChannels\n 2623:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCR5 GC5C2 LL_TIM_SetCH5CombinedChannels\n 2624:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCR5 GC5C1 LL_TIM_SetCH5CombinedChannels 2625:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 2626:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param GroupCH5 This parameter can be a combination of the following values: 2627:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_GROUPCH5_NONE 2628:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_GROUPCH5_OC1REFC 2629:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_GROUPCH5_OC2REFC 2630:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_GROUPCH5_OC3REFC 2631:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 2632:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 2633:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_SetCH5CombinedChannels(TIM_TypeDef *TIMx, uint32_t GroupCH5) 2634:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 2635:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(TIMx->CCR5, (TIM_CCR5_GC5C3 | TIM_CCR5_GC5C2 | TIM_CCR5_GC5C1), GroupCH5); 2636:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 2637:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 2638:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 2639:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} 2640:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 2641:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 2642:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EF_Input_Channel Input channel configuration 2643:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ 2644:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 2645:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 2646:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Configure input channel. 2647:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCMR1 CC1S LL_TIM_IC_Config\n 2648:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR1 IC1PSC LL_TIM_IC_Config\n 2649:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR1 IC1F LL_TIM_IC_Config\n 2650:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR1 CC2S LL_TIM_IC_Config\n 2651:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR1 IC2PSC LL_TIM_IC_Config\n 2652:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR1 IC2F LL_TIM_IC_Config\n 2653:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 CC3S LL_TIM_IC_Config\n 2654:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 IC3PSC LL_TIM_IC_Config\n 2655:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 IC3F LL_TIM_IC_Config\n 2656:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 CC4S LL_TIM_IC_Config\n 2657:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 IC4PSC LL_TIM_IC_Config\n 2658:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 IC4F LL_TIM_IC_Config\n 2659:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC1P LL_TIM_IC_Config\n 2660:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC1NP LL_TIM_IC_Config\n 2661:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC2P LL_TIM_IC_Config\n 2662:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC2NP LL_TIM_IC_Config\n 2663:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC3P LL_TIM_IC_Config\n 2664:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC3NP LL_TIM_IC_Config\n 2665:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC4P LL_TIM_IC_Config\n 2666:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC4NP LL_TIM_IC_Config 2667:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 2668:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Channel This parameter can be one of the following values: 2669:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 2670:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 2671:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 2672:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 ARM GAS /tmp/ccqopZd5.s page 249 2673:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Configuration This parameter must be a combination of all the following values: 2674:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI or @ref LL_TIM_ACTIVEINPUT_INDIRECTTI or @ref LL_ 2675:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ICPSC_DIV1 or ... or @ref LL_TIM_ICPSC_DIV8 2676:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV1 or ... or @ref LL_TIM_IC_FILTER_FDIV32_N8 2677:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_POLARITY_RISING or @ref LL_TIM_IC_POLARITY_FALLING or @ref LL_TIM_I 2678:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 2679:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 2680:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration) 2681:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 2682:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 2683:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iC 2684:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChanne 2685:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** ((Configuration >> 16U) & (TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S)) 2686:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** << SHIFT_TAB_ICxx[iChannel]); 2687:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]), 2688:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** (Configuration & (TIM_CCER_CC1NP | TIM_CCER_CC1P)) << SHIFT_TAB_CCxP[iChannel]); 2689:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 2690:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 2691:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 2692:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Set the active input. 2693:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCMR1 CC1S LL_TIM_IC_SetActiveInput\n 2694:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR1 CC2S LL_TIM_IC_SetActiveInput\n 2695:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 CC3S LL_TIM_IC_SetActiveInput\n 2696:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 CC4S LL_TIM_IC_SetActiveInput 2697:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 2698:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Channel This parameter can be one of the following values: 2699:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 2700:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 2701:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 2702:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 2703:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param ICActiveInput This parameter can be one of the following values: 2704:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI 2705:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI 2706:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ACTIVEINPUT_TRC 2707:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 2708:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 2709:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_IC_SetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICActiv 2710:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 2711:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 2712:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iC 2713:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), (ICActiveInput >> 16U) << SHIFT 2714:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 2715:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 2716:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 2717:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Get the current active input. 2718:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCMR1 CC1S LL_TIM_IC_GetActiveInput\n 2719:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR1 CC2S LL_TIM_IC_GetActiveInput\n 2720:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 CC3S LL_TIM_IC_GetActiveInput\n 2721:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 CC4S LL_TIM_IC_GetActiveInput 2722:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 2723:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Channel This parameter can be one of the following values: 2724:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 2725:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 2726:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 2727:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 2728:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval Returned value can be one of the following values: 2729:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI ARM GAS /tmp/ccqopZd5.s page 250 2730:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI 2731:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ACTIVEINPUT_TRC 2732:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 2733:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(const TIM_TypeDef *TIMx, uint32_t Channel) 2734:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 2735:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 2736:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CC 2737:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return ((READ_BIT(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChann 2738:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 2739:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 2740:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 2741:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Set the prescaler of input channel. 2742:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCMR1 IC1PSC LL_TIM_IC_SetPrescaler\n 2743:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR1 IC2PSC LL_TIM_IC_SetPrescaler\n 2744:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 IC3PSC LL_TIM_IC_SetPrescaler\n 2745:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 IC4PSC LL_TIM_IC_SetPrescaler 2746:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 2747:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Channel This parameter can be one of the following values: 2748:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 2749:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 2750:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 2751:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 2752:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param ICPrescaler This parameter can be one of the following values: 2753:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ICPSC_DIV1 2754:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ICPSC_DIV2 2755:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ICPSC_DIV4 2756:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ICPSC_DIV8 2757:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 2758:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 2759:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_IC_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPrescal 2760:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 2761:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 2762:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iC 2763:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel]), (ICPrescaler >> 16U) << SHIFT 2764:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 2765:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 2766:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 2767:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Get the current prescaler value acting on an input channel. 2768:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCMR1 IC1PSC LL_TIM_IC_GetPrescaler\n 2769:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR1 IC2PSC LL_TIM_IC_GetPrescaler\n 2770:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 IC3PSC LL_TIM_IC_GetPrescaler\n 2771:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 IC4PSC LL_TIM_IC_GetPrescaler 2772:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 2773:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Channel This parameter can be one of the following values: 2774:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 2775:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 2776:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 2777:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 2778:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval Returned value can be one of the following values: 2779:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ICPSC_DIV1 2780:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ICPSC_DIV2 2781:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ICPSC_DIV4 2782:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ICPSC_DIV8 2783:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 2784:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(const TIM_TypeDef *TIMx, uint32_t Channel) 2785:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 2786:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); ARM GAS /tmp/ccqopZd5.s page 251 2787:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CC 2788:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iCha 2789:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 2790:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 2791:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 2792:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Set the input filter duration. 2793:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCMR1 IC1F LL_TIM_IC_SetFilter\n 2794:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR1 IC2F LL_TIM_IC_SetFilter\n 2795:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 IC3F LL_TIM_IC_SetFilter\n 2796:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 IC4F LL_TIM_IC_SetFilter 2797:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 2798:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Channel This parameter can be one of the following values: 2799:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 2800:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 2801:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 2802:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 2803:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param ICFilter This parameter can be one of the following values: 2804:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV1 2805:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV1_N2 2806:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV1_N4 2807:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV1_N8 2808:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV2_N6 2809:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV2_N8 2810:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV4_N6 2811:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV4_N8 2812:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV8_N6 2813:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV8_N8 2814:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV16_N5 2815:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV16_N6 2816:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV16_N8 2817:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV32_N5 2818:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV32_N6 2819:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV32_N8 2820:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 2821:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 2822:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_IC_SetFilter(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICFilter) 2823:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 2824:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 2825:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iC 2826:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel]), (ICFilter >> 16U) << SHIFT_TAB_ 2827:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 2828:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 2829:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 2830:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Get the input filter duration. 2831:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCMR1 IC1F LL_TIM_IC_GetFilter\n 2832:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR1 IC2F LL_TIM_IC_GetFilter\n 2833:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 IC3F LL_TIM_IC_GetFilter\n 2834:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 IC4F LL_TIM_IC_GetFilter 2835:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 2836:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Channel This parameter can be one of the following values: 2837:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 2838:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 2839:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 2840:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 2841:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval Returned value can be one of the following values: 2842:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV1 2843:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV1_N2 ARM GAS /tmp/ccqopZd5.s page 252 2844:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV1_N4 2845:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV1_N8 2846:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV2_N6 2847:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV2_N8 2848:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV4_N6 2849:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV4_N8 2850:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV8_N6 2851:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV8_N8 2852:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV16_N5 2853:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV16_N6 2854:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV16_N8 2855:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV32_N5 2856:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV32_N6 2857:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV32_N8 2858:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 2859:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IC_GetFilter(const TIM_TypeDef *TIMx, uint32_t Channel) 2860:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 2861:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 2862:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CC 2863:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChann 2864:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 2865:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 2866:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 2867:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Set the input channel polarity. 2868:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCER CC1P LL_TIM_IC_SetPolarity\n 2869:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC1NP LL_TIM_IC_SetPolarity\n 2870:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC2P LL_TIM_IC_SetPolarity\n 2871:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC2NP LL_TIM_IC_SetPolarity\n 2872:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC3P LL_TIM_IC_SetPolarity\n 2873:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC3NP LL_TIM_IC_SetPolarity\n 2874:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC4P LL_TIM_IC_SetPolarity\n 2875:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC4NP LL_TIM_IC_SetPolarity 2876:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 2877:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Channel This parameter can be one of the following values: 2878:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 2879:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 2880:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 2881:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 2882:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param ICPolarity This parameter can be one of the following values: 2883:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_POLARITY_RISING 2884:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_POLARITY_FALLING 2885:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE 2886:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 2887:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 2888:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_IC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPolarity 2889:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 2890:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 2891:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]), 2892:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** ICPolarity << SHIFT_TAB_CCxP[iChannel]); 2893:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 2894:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 2895:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 2896:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Get the current input channel polarity. 2897:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCER CC1P LL_TIM_IC_GetPolarity\n 2898:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC1NP LL_TIM_IC_GetPolarity\n 2899:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC2P LL_TIM_IC_GetPolarity\n 2900:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC2NP LL_TIM_IC_GetPolarity\n ARM GAS /tmp/ccqopZd5.s page 253 2901:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC3P LL_TIM_IC_GetPolarity\n 2902:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC3NP LL_TIM_IC_GetPolarity\n 2903:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC4P LL_TIM_IC_GetPolarity\n 2904:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC4NP LL_TIM_IC_GetPolarity 2905:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 2906:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Channel This parameter can be one of the following values: 2907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 2908:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 2909:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 2910:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 2911:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval Returned value can be one of the following values: 2912:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_POLARITY_RISING 2913:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_POLARITY_FALLING 2914:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE 2915:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 2916:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IC_GetPolarity(const TIM_TypeDef *TIMx, uint32_t Channel) 2917:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 2918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 2919:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return (READ_BIT(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel])) >> 2920:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** SHIFT_TAB_CCxP[iChannel]); 2921:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 2922:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 2923:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 2924:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Connect the TIMx_CH1, CH2 and CH3 pins to the TI1 input (XOR combination). 2925:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not 2926:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * a timer instance provides an XOR input. 2927:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR2 TI1S LL_TIM_IC_EnableXORCombination 2928:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 2929:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 2930:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 2931:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_IC_EnableXORCombination(TIM_TypeDef *TIMx) 2932:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 2933:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** SET_BIT(TIMx->CR2, TIM_CR2_TI1S); 2934:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 2935:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 2936:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 2937:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Disconnect the TIMx_CH1, CH2 and CH3 pins from the TI1 input. 2938:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not 2939:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * a timer instance provides an XOR input. 2940:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR2 TI1S LL_TIM_IC_DisableXORCombination 2941:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 2942:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 2943:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 2944:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_IC_DisableXORCombination(TIM_TypeDef *TIMx) 2945:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 2946:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** CLEAR_BIT(TIMx->CR2, TIM_CR2_TI1S); 2947:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 2948:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 2949:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 2950:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Indicates whether the TIMx_CH1, CH2 and CH3 pins are connectected to the TI1 input. 2951:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not 2952:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * a timer instance provides an XOR input. 2953:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR2 TI1S LL_TIM_IC_IsEnabledXORCombination 2954:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 2955:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval State of bit (1 or 0). 2956:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 2957:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IC_IsEnabledXORCombination(const TIM_TypeDef *TIMx) ARM GAS /tmp/ccqopZd5.s page 254 2958:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 2959:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return ((READ_BIT(TIMx->CR2, TIM_CR2_TI1S) == (TIM_CR2_TI1S)) ? 1UL : 0UL); 2960:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 2961:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 2962:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 2963:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Get captured value for input channel 1. 2964:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xF 2965:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check 2966:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * whether or not a timer instance supports a 32 bits counter. 2967:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not 2968:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * input channel 1 is supported by a timer instance. 2969:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCR1 CCR1 LL_TIM_IC_GetCaptureCH1 2970:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 2971:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval CapturedValue (between Min_Data=0 and Max_Data=65535) 2972:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 2973:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH1(const TIM_TypeDef *TIMx) 2974:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 2975:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return (uint32_t)(READ_REG(TIMx->CCR1)); 2976:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 2977:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 2978:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 2979:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Get captured value for input channel 2. 2980:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xF 2981:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check 2982:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * whether or not a timer instance supports a 32 bits counter. 2983:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not 2984:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * input channel 2 is supported by a timer instance. 2985:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCR2 CCR2 LL_TIM_IC_GetCaptureCH2 2986:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 2987:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval CapturedValue (between Min_Data=0 and Max_Data=65535) 2988:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 2989:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH2(const TIM_TypeDef *TIMx) 2990:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 2991:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return (uint32_t)(READ_REG(TIMx->CCR2)); 2992:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 2993:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 2994:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 2995:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Get captured value for input channel 3. 2996:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xF 2997:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check 2998:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * whether or not a timer instance supports a 32 bits counter. 2999:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not 3000:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * input channel 3 is supported by a timer instance. 3001:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCR3 CCR3 LL_TIM_IC_GetCaptureCH3 3002:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3003:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval CapturedValue (between Min_Data=0 and Max_Data=65535) 3004:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3005:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH3(const TIM_TypeDef *TIMx) 3006:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3007:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return (uint32_t)(READ_REG(TIMx->CCR3)); 3008:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3009:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3010:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3011:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Get captured value for input channel 4. 3012:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xF 3013:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check 3014:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * whether or not a timer instance supports a 32 bits counter. ARM GAS /tmp/ccqopZd5.s page 255 3015:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not 3016:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * input channel 4 is supported by a timer instance. 3017:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCR4 CCR4 LL_TIM_IC_GetCaptureCH4 3018:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3019:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval CapturedValue (between Min_Data=0 and Max_Data=65535) 3020:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3021:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH4(const TIM_TypeDef *TIMx) 3022:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3023:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return (uint32_t)(READ_REG(TIMx->CCR4)); 3024:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3025:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3026:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3027:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} 3028:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3029:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3030:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EF_Clock_Selection Counter clock selection 3031:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ 3032:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3033:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3034:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Enable external clock mode 2. 3035:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note When external clock mode 2 is enabled the counter is clocked by any active edge on the ET 3036:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check 3037:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * whether or not a timer instance supports external clock mode2. 3038:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SMCR ECE LL_TIM_EnableExternalClock 3039:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3040:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 3041:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3042:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_EnableExternalClock(TIM_TypeDef *TIMx) 3043:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3044:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** SET_BIT(TIMx->SMCR, TIM_SMCR_ECE); 3045:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3046:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3047:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3048:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Disable external clock mode 2. 3049:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check 3050:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * whether or not a timer instance supports external clock mode2. 3051:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SMCR ECE LL_TIM_DisableExternalClock 3052:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3053:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 3054:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3055:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_DisableExternalClock(TIM_TypeDef *TIMx) 3056:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3057:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** CLEAR_BIT(TIMx->SMCR, TIM_SMCR_ECE); 3058:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3059:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3060:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3061:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Indicate whether external clock mode 2 is enabled. 3062:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check 3063:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * whether or not a timer instance supports external clock mode2. 3064:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SMCR ECE LL_TIM_IsEnabledExternalClock 3065:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3066:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval State of bit (1 or 0). 3067:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3068:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsEnabledExternalClock(const TIM_TypeDef *TIMx) 3069:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3070:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return ((READ_BIT(TIMx->SMCR, TIM_SMCR_ECE) == (TIM_SMCR_ECE)) ? 1UL : 0UL); 3071:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } ARM GAS /tmp/ccqopZd5.s page 256 3072:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3073:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3074:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Set the clock source of the counter clock. 3075:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note when selected clock source is external clock mode 1, the timer input 3076:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * the external clock is applied is selected by calling the @ref LL_TIM_SetTriggerInput() 3077:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * function. This timer input must be configured by calling 3078:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * the @ref LL_TIM_IC_Config() function. 3079:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(TIMx) can be used to check 3080:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * whether or not a timer instance supports external clock mode1. 3081:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check 3082:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * whether or not a timer instance supports external clock mode2. 3083:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SMCR SMS LL_TIM_SetClockSource\n 3084:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * SMCR ECE LL_TIM_SetClockSource 3085:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3086:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param ClockSource This parameter can be one of the following values: 3087:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CLOCKSOURCE_INTERNAL 3088:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE1 3089:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE2 3090:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 3091:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3092:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_SetClockSource(TIM_TypeDef *TIMx, uint32_t ClockSource) 3105 .loc 5 3092 22 view .LVU1034 3106 .LBB385: 3093:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3094:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS | TIM_SMCR_ECE, ClockSource); 3107 .loc 5 3094 3 view .LVU1035 3108 006a 9968 ldr r1, [r3, #8] 3109 006c 0A4A ldr r2, .L116+16 3110 006e 0A40 ands r2, r2, r1 3111 0070 9A60 str r2, [r3, #8] 3112 .LVL235: 3113 .loc 5 3094 3 is_stmt 0 view .LVU1036 3114 .LBE385: 3115 .LBE384: 1192:Src/main.c **** LL_TIM_DisableMasterSlaveMode(TIM2); 3116 .loc 2 1192 3 is_stmt 1 view .LVU1037 3117 .LBB386: 3118 .LBI386: 3095:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3096:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3097:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3098:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Set the encoder interface mode. 3099:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx) can be used to check 3100:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * whether or not a timer instance supports the encoder mode. 3101:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SMCR SMS LL_TIM_SetEncoderMode 3102:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3103:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param EncoderMode This parameter can be one of the following values: 3104:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ENCODERMODE_X2_TI1 3105:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ENCODERMODE_X2_TI2 3106:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ENCODERMODE_X4_TI12 3107:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 3108:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3109:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_SetEncoderMode(TIM_TypeDef *TIMx, uint32_t EncoderMode) 3110:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3111:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, EncoderMode); 3112:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3113:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** ARM GAS /tmp/ccqopZd5.s page 257 3114:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3115:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} 3116:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3117:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3118:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EF_Timer_Synchronization Timer synchronisation configuration 3119:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ 3120:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3121:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3122:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Set the trigger output (TRGO) used for timer synchronization . 3123:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_MASTER_INSTANCE(TIMx) can be used to check 3124:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * whether or not a timer instance can operate as a master timer. 3125:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR2 MMS LL_TIM_SetTriggerOutput 3126:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3127:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TimerSynchronization This parameter can be one of the following values: 3128:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TRGO_RESET 3129:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TRGO_ENABLE 3130:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TRGO_UPDATE 3131:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TRGO_CC1IF 3132:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TRGO_OC1REF 3133:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TRGO_OC2REF 3134:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TRGO_OC3REF 3135:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TRGO_OC4REF 3136:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 3137:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3138:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_SetTriggerOutput(TIM_TypeDef *TIMx, uint32_t TimerSynchronization) 3119 .loc 5 3138 22 view .LVU1038 3120 .LBB387: 3139:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3140:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(TIMx->CR2, TIM_CR2_MMS, TimerSynchronization); 3121 .loc 5 3140 3 view .LVU1039 3122 0072 5A68 ldr r2, [r3, #4] 3123 0074 22F07002 bic r2, r2, #112 3124 0078 5A60 str r2, [r3, #4] 3125 .LVL236: 3126 .loc 5 3140 3 is_stmt 0 view .LVU1040 3127 .LBE387: 3128 .LBE386: 1193:Src/main.c **** /* USER CODE BEGIN TIM2_Init 2 */ 3129 .loc 2 1193 3 is_stmt 1 view .LVU1041 3130 .LBB388: 3131 .LBI388: 3141:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3142:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3143:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3144:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Set the trigger output 2 (TRGO2) used for ADC synchronization . 3145:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_TRGO2_INSTANCE(TIMx) can be used to check 3146:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * whether or not a timer instance can be used for ADC synchronization. 3147:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR2 MMS2 LL_TIM_SetTriggerOutput2 3148:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer Instance 3149:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param ADCSynchronization This parameter can be one of the following values: 3150:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TRGO2_RESET 3151:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TRGO2_ENABLE 3152:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TRGO2_UPDATE 3153:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TRGO2_CC1F 3154:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TRGO2_OC1 3155:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TRGO2_OC2 3156:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TRGO2_OC3 ARM GAS /tmp/ccqopZd5.s page 258 3157:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TRGO2_OC4 3158:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TRGO2_OC5 3159:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TRGO2_OC6 3160:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TRGO2_OC4_RISINGFALLING 3161:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TRGO2_OC6_RISINGFALLING 3162:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TRGO2_OC4_RISING_OC6_RISING 3163:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TRGO2_OC4_RISING_OC6_FALLING 3164:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TRGO2_OC5_RISING_OC6_RISING 3165:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TRGO2_OC5_RISING_OC6_FALLING 3166:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 3167:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3168:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_SetTriggerOutput2(TIM_TypeDef *TIMx, uint32_t ADCSynchronization) 3169:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3170:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(TIMx->CR2, TIM_CR2_MMS2, ADCSynchronization); 3171:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3172:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3173:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3174:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Set the synchronization mode of a slave timer. 3175:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not 3176:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * a timer instance can operate as a slave timer. 3177:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SMCR SMS LL_TIM_SetSlaveMode 3178:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3179:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param SlaveMode This parameter can be one of the following values: 3180:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_SLAVEMODE_DISABLED 3181:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_SLAVEMODE_RESET 3182:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_SLAVEMODE_GATED 3183:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_SLAVEMODE_TRIGGER 3184:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_SLAVEMODE_COMBINED_RESETTRIGGER 3185:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 3186:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3187:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_SetSlaveMode(TIM_TypeDef *TIMx, uint32_t SlaveMode) 3188:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3189:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, SlaveMode); 3190:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3191:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3192:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3193:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Set the selects the trigger input to be used to synchronize the counter. 3194:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not 3195:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * a timer instance can operate as a slave timer. 3196:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SMCR TS LL_TIM_SetTriggerInput 3197:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3198:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TriggerInput This parameter can be one of the following values: 3199:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TS_ITR0 3200:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TS_ITR1 3201:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TS_ITR2 3202:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TS_ITR3 3203:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TS_TI1F_ED 3204:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TS_TI1FP1 3205:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TS_TI2FP2 3206:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TS_ETRF 3207:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 3208:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3209:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_SetTriggerInput(TIM_TypeDef *TIMx, uint32_t TriggerInput) 3210:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3211:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(TIMx->SMCR, TIM_SMCR_TS, TriggerInput); 3212:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3213:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** ARM GAS /tmp/ccqopZd5.s page 259 3214:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3215:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Enable the Master/Slave mode. 3216:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not 3217:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * a timer instance can operate as a slave timer. 3218:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SMCR MSM LL_TIM_EnableMasterSlaveMode 3219:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3220:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 3221:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3222:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_EnableMasterSlaveMode(TIM_TypeDef *TIMx) 3223:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3224:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** SET_BIT(TIMx->SMCR, TIM_SMCR_MSM); 3225:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3226:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3227:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3228:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Disable the Master/Slave mode. 3229:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not 3230:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * a timer instance can operate as a slave timer. 3231:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SMCR MSM LL_TIM_DisableMasterSlaveMode 3232:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3233:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 3234:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3235:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_DisableMasterSlaveMode(TIM_TypeDef *TIMx) 3132 .loc 5 3235 22 view .LVU1042 3133 .LBB389: 3236:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3237:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** CLEAR_BIT(TIMx->SMCR, TIM_SMCR_MSM); 3134 .loc 5 3237 3 view .LVU1043 3135 007a 9A68 ldr r2, [r3, #8] 3136 007c 22F08002 bic r2, r2, #128 3137 0080 9A60 str r2, [r3, #8] 3138 .LVL237: 3139 .loc 5 3237 3 is_stmt 0 view .LVU1044 3140 .LBE389: 3141 .LBE388: 1198:Src/main.c **** 3142 .loc 2 1198 1 view .LVU1045 3143 0082 06B0 add sp, sp, #24 3144 .LCFI28: 3145 .cfi_def_cfa_offset 8 3146 @ sp needed 3147 0084 10BD pop {r4, pc} 3148 .L117: 3149 0086 00BF .align 2 3150 .L116: 3151 0088 00380240 .word 1073887232 3152 008c 00ED00E0 .word -536810240 3153 0090 00E100E0 .word -536813312 3154 0094 40D10C00 .word 840000 3155 0098 F8BFFEFF .word -81928 3156 .cfi_endproc 3157 .LFE1195: 3159 .section .text.MX_TIM5_Init,"ax",%progbits 3160 .align 1 3161 .syntax unified 3162 .thumb 3163 .thumb_func 3164 .fpu fpv5-d16 ARM GAS /tmp/ccqopZd5.s page 260 3166 MX_TIM5_Init: 3167 .LFB1196: 1206:Src/main.c **** 3168 .loc 2 1206 1 is_stmt 1 view -0 3169 .cfi_startproc 3170 @ args = 0, pretend = 0, frame = 24 3171 @ frame_needed = 0, uses_anonymous_args = 0 3172 0000 10B5 push {r4, lr} 3173 .LCFI29: 3174 .cfi_def_cfa_offset 8 3175 .cfi_offset 4, -8 3176 .cfi_offset 14, -4 3177 0002 86B0 sub sp, sp, #24 3178 .LCFI30: 3179 .cfi_def_cfa_offset 32 1212:Src/main.c **** 3180 .loc 2 1212 3 view .LVU1047 1212:Src/main.c **** 3181 .loc 2 1212 22 is_stmt 0 view .LVU1048 3182 0004 0024 movs r4, #0 3183 0006 0194 str r4, [sp, #4] 3184 0008 0294 str r4, [sp, #8] 3185 000a 0394 str r4, [sp, #12] 3186 000c 0494 str r4, [sp, #16] 3187 000e 0594 str r4, [sp, #20] 1215:Src/main.c **** 3188 .loc 2 1215 3 is_stmt 1 view .LVU1049 3189 .LVL238: 3190 .LBB390: 3191 .LBI390: 1071:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { 3192 .loc 3 1071 22 view .LVU1050 3193 .LBB391: 1073:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** SET_BIT(RCC->APB1ENR, Periphs); 3194 .loc 3 1073 3 view .LVU1051 1074:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Delay after an RCC peripheral clock enabling */ 3195 .loc 3 1074 3 view .LVU1052 3196 0010 1C4B ldr r3, .L120 3197 0012 1A6C ldr r2, [r3, #64] 3198 0014 42F00802 orr r2, r2, #8 3199 0018 1A64 str r2, [r3, #64] 1076:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; 3200 .loc 3 1076 3 view .LVU1053 1076:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; 3201 .loc 3 1076 12 is_stmt 0 view .LVU1054 3202 001a 1B6C ldr r3, [r3, #64] 3203 001c 03F00803 and r3, r3, #8 1076:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; 3204 .loc 3 1076 10 view .LVU1055 3205 0020 0093 str r3, [sp] 1077:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } 3206 .loc 3 1077 3 is_stmt 1 view .LVU1056 3207 0022 009B ldr r3, [sp] 3208 .LVL239: 1077:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } 3209 .loc 3 1077 3 is_stmt 0 view .LVU1057 3210 .LBE391: ARM GAS /tmp/ccqopZd5.s page 261 3211 .LBE390: 1218:Src/main.c **** NVIC_EnableIRQ(TIM5_IRQn); 3212 .loc 2 1218 3 is_stmt 1 view .LVU1058 3213 .LBB392: 3214 .LBI392: 1884:Drivers/CMSIS/Include/core_cm7.h **** { 3215 .loc 1 1884 26 view .LVU1059 3216 .LBB393: 1886:Drivers/CMSIS/Include/core_cm7.h **** } 3217 .loc 1 1886 3 view .LVU1060 1886:Drivers/CMSIS/Include/core_cm7.h **** } 3218 .loc 1 1886 26 is_stmt 0 view .LVU1061 3219 0024 184B ldr r3, .L120+4 3220 0026 D868 ldr r0, [r3, #12] 3221 .LBE393: 3222 .LBE392: 1218:Src/main.c **** NVIC_EnableIRQ(TIM5_IRQn); 3223 .loc 2 1218 3 view .LVU1062 3224 0028 2246 mov r2, r4 3225 002a 2146 mov r1, r4 3226 002c C0F30220 ubfx r0, r0, #8, #3 3227 0030 FFF7FEFF bl NVIC_EncodePriority 3228 .LVL240: 3229 .LBB394: 3230 .LBI394: 2024:Drivers/CMSIS/Include/core_cm7.h **** { 3231 .loc 1 2024 22 is_stmt 1 view .LVU1063 3232 .LBB395: 2026:Drivers/CMSIS/Include/core_cm7.h **** { 3233 .loc 1 2026 3 view .LVU1064 2028:Drivers/CMSIS/Include/core_cm7.h **** } 3234 .loc 1 2028 5 view .LVU1065 2028:Drivers/CMSIS/Include/core_cm7.h **** } 3235 .loc 1 2028 49 is_stmt 0 view .LVU1066 3236 0034 0001 lsls r0, r0, #4 3237 .LVL241: 2028:Drivers/CMSIS/Include/core_cm7.h **** } 3238 .loc 1 2028 49 view .LVU1067 3239 0036 C0B2 uxtb r0, r0 2028:Drivers/CMSIS/Include/core_cm7.h **** } 3240 .loc 1 2028 47 view .LVU1068 3241 0038 144B ldr r3, .L120+8 3242 003a 83F83203 strb r0, [r3, #818] 3243 .LVL242: 2028:Drivers/CMSIS/Include/core_cm7.h **** } 3244 .loc 1 2028 47 view .LVU1069 3245 .LBE395: 3246 .LBE394: 1219:Src/main.c **** 3247 .loc 2 1219 3 is_stmt 1 view .LVU1070 3248 .LBB396: 3249 .LBI396: 1896:Drivers/CMSIS/Include/core_cm7.h **** { 3250 .loc 1 1896 22 view .LVU1071 3251 .LBB397: 1898:Drivers/CMSIS/Include/core_cm7.h **** { 3252 .loc 1 1898 3 view .LVU1072 ARM GAS /tmp/ccqopZd5.s page 262 1900:Drivers/CMSIS/Include/core_cm7.h **** } 3253 .loc 1 1900 5 view .LVU1073 1900:Drivers/CMSIS/Include/core_cm7.h **** } 3254 .loc 1 1900 43 is_stmt 0 view .LVU1074 3255 003e 4FF48022 mov r2, #262144 3256 0042 5A60 str r2, [r3, #4] 3257 .LVL243: 1900:Drivers/CMSIS/Include/core_cm7.h **** } 3258 .loc 1 1900 43 view .LVU1075 3259 .LBE397: 3260 .LBE396: 1224:Src/main.c **** TIM_InitStruct.CounterMode = LL_TIM_COUNTERMODE_UP; 3261 .loc 2 1224 3 is_stmt 1 view .LVU1076 1224:Src/main.c **** TIM_InitStruct.CounterMode = LL_TIM_COUNTERMODE_UP; 3262 .loc 2 1224 28 is_stmt 0 view .LVU1077 3263 0044 42F21073 movw r3, #10000 3264 0048 ADF80430 strh r3, [sp, #4] @ movhi 1225:Src/main.c **** TIM_InitStruct.Autoreload = 560; 3265 .loc 2 1225 3 is_stmt 1 view .LVU1078 1225:Src/main.c **** TIM_InitStruct.Autoreload = 560; 3266 .loc 2 1225 30 is_stmt 0 view .LVU1079 3267 004c 0294 str r4, [sp, #8] 1226:Src/main.c **** TIM_InitStruct.ClockDivision = LL_TIM_CLOCKDIVISION_DIV1; 3268 .loc 2 1226 3 is_stmt 1 view .LVU1080 1226:Src/main.c **** TIM_InitStruct.ClockDivision = LL_TIM_CLOCKDIVISION_DIV1; 3269 .loc 2 1226 29 is_stmt 0 view .LVU1081 3270 004e 4FF40C73 mov r3, #560 3271 0052 0393 str r3, [sp, #12] 1227:Src/main.c **** LL_TIM_Init(TIM5, &TIM_InitStruct); 3272 .loc 2 1227 3 is_stmt 1 view .LVU1082 1227:Src/main.c **** LL_TIM_Init(TIM5, &TIM_InitStruct); 3273 .loc 2 1227 32 is_stmt 0 view .LVU1083 3274 0054 0494 str r4, [sp, #16] 1228:Src/main.c **** LL_TIM_DisableARRPreload(TIM5); 3275 .loc 2 1228 3 is_stmt 1 view .LVU1084 3276 0056 0E4C ldr r4, .L120+12 3277 0058 01A9 add r1, sp, #4 3278 005a 2046 mov r0, r4 3279 005c FFF7FEFF bl LL_TIM_Init 3280 .LVL244: 1229:Src/main.c **** LL_TIM_SetClockSource(TIM5, LL_TIM_CLOCKSOURCE_INTERNAL); 3281 .loc 2 1229 3 view .LVU1085 3282 .LBB398: 3283 .LBI398: 1504:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3284 .loc 5 1504 22 view .LVU1086 3285 .LBB399: 1506:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3286 .loc 5 1506 3 view .LVU1087 3287 0060 2368 ldr r3, [r4] 3288 0062 23F08003 bic r3, r3, #128 3289 0066 2360 str r3, [r4] 3290 .LVL245: 1506:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3291 .loc 5 1506 3 is_stmt 0 view .LVU1088 3292 .LBE399: 3293 .LBE398: ARM GAS /tmp/ccqopZd5.s page 263 1230:Src/main.c **** LL_TIM_SetTriggerOutput(TIM5, LL_TIM_TRGO_RESET); 3294 .loc 2 1230 3 is_stmt 1 view .LVU1089 3295 .LBB400: 3296 .LBI400: 3092:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3297 .loc 5 3092 22 view .LVU1090 3298 .LBB401: 3094:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3299 .loc 5 3094 3 view .LVU1091 3300 0068 A268 ldr r2, [r4, #8] 3301 006a 0A4B ldr r3, .L120+16 3302 006c 1340 ands r3, r3, r2 3303 006e A360 str r3, [r4, #8] 3304 .LVL246: 3094:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3305 .loc 5 3094 3 is_stmt 0 view .LVU1092 3306 .LBE401: 3307 .LBE400: 1231:Src/main.c **** LL_TIM_DisableMasterSlaveMode(TIM5); 3308 .loc 2 1231 3 is_stmt 1 view .LVU1093 3309 .LBB402: 3310 .LBI402: 3138:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3311 .loc 5 3138 22 view .LVU1094 3312 .LBB403: 3140:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3313 .loc 5 3140 3 view .LVU1095 3314 0070 6368 ldr r3, [r4, #4] 3315 0072 23F07003 bic r3, r3, #112 3316 0076 6360 str r3, [r4, #4] 3317 .LVL247: 3140:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3318 .loc 5 3140 3 is_stmt 0 view .LVU1096 3319 .LBE403: 3320 .LBE402: 1232:Src/main.c **** /* USER CODE BEGIN TIM5_Init 2 */ 3321 .loc 2 1232 3 is_stmt 1 view .LVU1097 3322 .LBB404: 3323 .LBI404: 3235:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3324 .loc 5 3235 22 view .LVU1098 3325 .LBB405: 3326 .loc 5 3237 3 view .LVU1099 3327 0078 A368 ldr r3, [r4, #8] 3328 007a 23F08003 bic r3, r3, #128 3329 007e A360 str r3, [r4, #8] 3330 .LVL248: 3331 .loc 5 3237 3 is_stmt 0 view .LVU1100 3332 .LBE405: 3333 .LBE404: 1237:Src/main.c **** 3334 .loc 2 1237 1 view .LVU1101 3335 0080 06B0 add sp, sp, #24 3336 .LCFI31: 3337 .cfi_def_cfa_offset 8 3338 @ sp needed 3339 0082 10BD pop {r4, pc} ARM GAS /tmp/ccqopZd5.s page 264 3340 .L121: 3341 .align 2 3342 .L120: 3343 0084 00380240 .word 1073887232 3344 0088 00ED00E0 .word -536810240 3345 008c 00E100E0 .word -536813312 3346 0090 000C0040 .word 1073744896 3347 0094 F8BFFEFF .word -81928 3348 .cfi_endproc 3349 .LFE1196: 3351 .section .text.MX_TIM7_Init,"ax",%progbits 3352 .align 1 3353 .syntax unified 3354 .thumb 3355 .thumb_func 3356 .fpu fpv5-d16 3358 MX_TIM7_Init: 3359 .LFB1198: 1282:Src/main.c **** 3360 .loc 2 1282 1 is_stmt 1 view -0 3361 .cfi_startproc 3362 @ args = 0, pretend = 0, frame = 24 3363 @ frame_needed = 0, uses_anonymous_args = 0 3364 0000 10B5 push {r4, lr} 3365 .LCFI32: 3366 .cfi_def_cfa_offset 8 3367 .cfi_offset 4, -8 3368 .cfi_offset 14, -4 3369 0002 86B0 sub sp, sp, #24 3370 .LCFI33: 3371 .cfi_def_cfa_offset 32 1288:Src/main.c **** 3372 .loc 2 1288 3 view .LVU1103 1288:Src/main.c **** 3373 .loc 2 1288 22 is_stmt 0 view .LVU1104 3374 0004 0024 movs r4, #0 3375 0006 0194 str r4, [sp, #4] 3376 0008 0294 str r4, [sp, #8] 3377 000a 0394 str r4, [sp, #12] 3378 000c 0494 str r4, [sp, #16] 3379 000e 0594 str r4, [sp, #20] 1291:Src/main.c **** 3380 .loc 2 1291 3 is_stmt 1 view .LVU1105 3381 .LVL249: 3382 .LBB406: 3383 .LBI406: 1071:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { 3384 .loc 3 1071 22 view .LVU1106 3385 .LBB407: 1073:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** SET_BIT(RCC->APB1ENR, Periphs); 3386 .loc 3 1073 3 view .LVU1107 1074:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Delay after an RCC peripheral clock enabling */ 3387 .loc 3 1074 3 view .LVU1108 3388 0010 1A4B ldr r3, .L124 3389 0012 1A6C ldr r2, [r3, #64] 3390 0014 42F02002 orr r2, r2, #32 3391 0018 1A64 str r2, [r3, #64] ARM GAS /tmp/ccqopZd5.s page 265 1076:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; 3392 .loc 3 1076 3 view .LVU1109 1076:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; 3393 .loc 3 1076 12 is_stmt 0 view .LVU1110 3394 001a 1B6C ldr r3, [r3, #64] 3395 001c 03F02003 and r3, r3, #32 1076:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; 3396 .loc 3 1076 10 view .LVU1111 3397 0020 0093 str r3, [sp] 1077:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } 3398 .loc 3 1077 3 is_stmt 1 view .LVU1112 3399 0022 009B ldr r3, [sp] 3400 .LVL250: 1077:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } 3401 .loc 3 1077 3 is_stmt 0 view .LVU1113 3402 .LBE407: 3403 .LBE406: 1294:Src/main.c **** NVIC_EnableIRQ(TIM7_IRQn); 3404 .loc 2 1294 3 is_stmt 1 view .LVU1114 3405 .LBB408: 3406 .LBI408: 1884:Drivers/CMSIS/Include/core_cm7.h **** { 3407 .loc 1 1884 26 view .LVU1115 3408 .LBB409: 1886:Drivers/CMSIS/Include/core_cm7.h **** } 3409 .loc 1 1886 3 view .LVU1116 1886:Drivers/CMSIS/Include/core_cm7.h **** } 3410 .loc 1 1886 26 is_stmt 0 view .LVU1117 3411 0024 164B ldr r3, .L124+4 3412 0026 D868 ldr r0, [r3, #12] 3413 .LBE409: 3414 .LBE408: 1294:Src/main.c **** NVIC_EnableIRQ(TIM7_IRQn); 3415 .loc 2 1294 3 view .LVU1118 3416 0028 2246 mov r2, r4 3417 002a 2146 mov r1, r4 3418 002c C0F30220 ubfx r0, r0, #8, #3 3419 0030 FFF7FEFF bl NVIC_EncodePriority 3420 .LVL251: 3421 .LBB410: 3422 .LBI410: 2024:Drivers/CMSIS/Include/core_cm7.h **** { 3423 .loc 1 2024 22 is_stmt 1 view .LVU1119 3424 .LBB411: 2026:Drivers/CMSIS/Include/core_cm7.h **** { 3425 .loc 1 2026 3 view .LVU1120 2028:Drivers/CMSIS/Include/core_cm7.h **** } 3426 .loc 1 2028 5 view .LVU1121 2028:Drivers/CMSIS/Include/core_cm7.h **** } 3427 .loc 1 2028 49 is_stmt 0 view .LVU1122 3428 0034 0001 lsls r0, r0, #4 3429 .LVL252: 2028:Drivers/CMSIS/Include/core_cm7.h **** } 3430 .loc 1 2028 49 view .LVU1123 3431 0036 C0B2 uxtb r0, r0 2028:Drivers/CMSIS/Include/core_cm7.h **** } 3432 .loc 1 2028 47 view .LVU1124 ARM GAS /tmp/ccqopZd5.s page 266 3433 0038 124B ldr r3, .L124+8 3434 003a 83F83703 strb r0, [r3, #823] 3435 .LVL253: 2028:Drivers/CMSIS/Include/core_cm7.h **** } 3436 .loc 1 2028 47 view .LVU1125 3437 .LBE411: 3438 .LBE410: 1295:Src/main.c **** 3439 .loc 2 1295 3 is_stmt 1 view .LVU1126 3440 .LBB412: 3441 .LBI412: 1896:Drivers/CMSIS/Include/core_cm7.h **** { 3442 .loc 1 1896 22 view .LVU1127 3443 .LBB413: 1898:Drivers/CMSIS/Include/core_cm7.h **** { 3444 .loc 1 1898 3 view .LVU1128 1900:Drivers/CMSIS/Include/core_cm7.h **** } 3445 .loc 1 1900 5 view .LVU1129 1900:Drivers/CMSIS/Include/core_cm7.h **** } 3446 .loc 1 1900 43 is_stmt 0 view .LVU1130 3447 003e 4FF40002 mov r2, #8388608 3448 0042 5A60 str r2, [r3, #4] 3449 .LVL254: 1900:Drivers/CMSIS/Include/core_cm7.h **** } 3450 .loc 1 1900 43 view .LVU1131 3451 .LBE413: 3452 .LBE412: 1300:Src/main.c **** TIM_InitStruct.CounterMode = LL_TIM_COUNTERMODE_UP; 3453 .loc 2 1300 3 is_stmt 1 view .LVU1132 1300:Src/main.c **** TIM_InitStruct.CounterMode = LL_TIM_COUNTERMODE_UP; 3454 .loc 2 1300 28 is_stmt 0 view .LVU1133 3455 0044 40F29733 movw r3, #919 3456 0048 ADF80430 strh r3, [sp, #4] @ movhi 1301:Src/main.c **** TIM_InitStruct.Autoreload = 99; 3457 .loc 2 1301 3 is_stmt 1 view .LVU1134 1301:Src/main.c **** TIM_InitStruct.Autoreload = 99; 3458 .loc 2 1301 30 is_stmt 0 view .LVU1135 3459 004c 0294 str r4, [sp, #8] 1302:Src/main.c **** LL_TIM_Init(TIM7, &TIM_InitStruct); 3460 .loc 2 1302 3 is_stmt 1 view .LVU1136 1302:Src/main.c **** LL_TIM_Init(TIM7, &TIM_InitStruct); 3461 .loc 2 1302 29 is_stmt 0 view .LVU1137 3462 004e 6323 movs r3, #99 3463 0050 0393 str r3, [sp, #12] 1303:Src/main.c **** LL_TIM_DisableARRPreload(TIM7); 3464 .loc 2 1303 3 is_stmt 1 view .LVU1138 3465 0052 0D4C ldr r4, .L124+12 3466 0054 01A9 add r1, sp, #4 3467 0056 2046 mov r0, r4 3468 0058 FFF7FEFF bl LL_TIM_Init 3469 .LVL255: 1304:Src/main.c **** LL_TIM_SetTriggerOutput(TIM7, LL_TIM_TRGO_ENABLE); 3470 .loc 2 1304 3 view .LVU1139 3471 .LBB414: 3472 .LBI414: 1504:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3473 .loc 5 1504 22 view .LVU1140 ARM GAS /tmp/ccqopZd5.s page 267 3474 .LBB415: 1506:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3475 .loc 5 1506 3 view .LVU1141 3476 005c 2368 ldr r3, [r4] 3477 005e 23F08003 bic r3, r3, #128 3478 0062 2360 str r3, [r4] 3479 .LVL256: 1506:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3480 .loc 5 1506 3 is_stmt 0 view .LVU1142 3481 .LBE415: 3482 .LBE414: 1305:Src/main.c **** LL_TIM_DisableMasterSlaveMode(TIM7); 3483 .loc 2 1305 3 is_stmt 1 view .LVU1143 3484 .LBB416: 3485 .LBI416: 3138:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3486 .loc 5 3138 22 view .LVU1144 3487 .LBB417: 3140:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3488 .loc 5 3140 3 view .LVU1145 3489 0064 6368 ldr r3, [r4, #4] 3490 0066 23F07003 bic r3, r3, #112 3491 006a 43F01003 orr r3, r3, #16 3492 006e 6360 str r3, [r4, #4] 3493 .LVL257: 3140:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3494 .loc 5 3140 3 is_stmt 0 view .LVU1146 3495 .LBE417: 3496 .LBE416: 1306:Src/main.c **** /* USER CODE BEGIN TIM7_Init 2 */ 3497 .loc 2 1306 3 is_stmt 1 view .LVU1147 3498 .LBB418: 3499 .LBI418: 3235:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3500 .loc 5 3235 22 view .LVU1148 3501 .LBB419: 3502 .loc 5 3237 3 view .LVU1149 3503 0070 A368 ldr r3, [r4, #8] 3504 0072 23F08003 bic r3, r3, #128 3505 0076 A360 str r3, [r4, #8] 3506 .LVL258: 3507 .loc 5 3237 3 is_stmt 0 view .LVU1150 3508 .LBE419: 3509 .LBE418: 1311:Src/main.c **** 3510 .loc 2 1311 1 view .LVU1151 3511 0078 06B0 add sp, sp, #24 3512 .LCFI34: 3513 .cfi_def_cfa_offset 8 3514 @ sp needed 3515 007a 10BD pop {r4, pc} 3516 .L125: 3517 .align 2 3518 .L124: 3519 007c 00380240 .word 1073887232 3520 0080 00ED00E0 .word -536810240 3521 0084 00E100E0 .word -536813312 ARM GAS /tmp/ccqopZd5.s page 268 3522 0088 00140040 .word 1073746944 3523 .cfi_endproc 3524 .LFE1198: 3526 .section .text.MX_TIM6_Init,"ax",%progbits 3527 .align 1 3528 .syntax unified 3529 .thumb 3530 .thumb_func 3531 .fpu fpv5-d16 3533 MX_TIM6_Init: 3534 .LFB1197: 1245:Src/main.c **** 3535 .loc 2 1245 1 is_stmt 1 view -0 3536 .cfi_startproc 3537 @ args = 0, pretend = 0, frame = 24 3538 @ frame_needed = 0, uses_anonymous_args = 0 3539 0000 10B5 push {r4, lr} 3540 .LCFI35: 3541 .cfi_def_cfa_offset 8 3542 .cfi_offset 4, -8 3543 .cfi_offset 14, -4 3544 0002 86B0 sub sp, sp, #24 3545 .LCFI36: 3546 .cfi_def_cfa_offset 32 1251:Src/main.c **** 3547 .loc 2 1251 3 view .LVU1153 1251:Src/main.c **** 3548 .loc 2 1251 22 is_stmt 0 view .LVU1154 3549 0004 0024 movs r4, #0 3550 0006 0194 str r4, [sp, #4] 3551 0008 0294 str r4, [sp, #8] 3552 000a 0394 str r4, [sp, #12] 3553 000c 0494 str r4, [sp, #16] 3554 000e 0594 str r4, [sp, #20] 1254:Src/main.c **** 3555 .loc 2 1254 3 is_stmt 1 view .LVU1155 3556 .LVL259: 3557 .LBB420: 3558 .LBI420: 1071:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { 3559 .loc 3 1071 22 view .LVU1156 3560 .LBB421: 1073:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** SET_BIT(RCC->APB1ENR, Periphs); 3561 .loc 3 1073 3 view .LVU1157 1074:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Delay after an RCC peripheral clock enabling */ 3562 .loc 3 1074 3 view .LVU1158 3563 0010 1A4B ldr r3, .L128 3564 0012 1A6C ldr r2, [r3, #64] 3565 0014 42F01002 orr r2, r2, #16 3566 0018 1A64 str r2, [r3, #64] 1076:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; 3567 .loc 3 1076 3 view .LVU1159 1076:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; 3568 .loc 3 1076 12 is_stmt 0 view .LVU1160 3569 001a 1B6C ldr r3, [r3, #64] 3570 001c 03F01003 and r3, r3, #16 1076:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; ARM GAS /tmp/ccqopZd5.s page 269 3571 .loc 3 1076 10 view .LVU1161 3572 0020 0093 str r3, [sp] 1077:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } 3573 .loc 3 1077 3 is_stmt 1 view .LVU1162 3574 0022 009B ldr r3, [sp] 3575 .LVL260: 1077:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } 3576 .loc 3 1077 3 is_stmt 0 view .LVU1163 3577 .LBE421: 3578 .LBE420: 1257:Src/main.c **** NVIC_EnableIRQ(TIM6_DAC_IRQn); 3579 .loc 2 1257 3 is_stmt 1 view .LVU1164 3580 .LBB422: 3581 .LBI422: 1884:Drivers/CMSIS/Include/core_cm7.h **** { 3582 .loc 1 1884 26 view .LVU1165 3583 .LBB423: 1886:Drivers/CMSIS/Include/core_cm7.h **** } 3584 .loc 1 1886 3 view .LVU1166 1886:Drivers/CMSIS/Include/core_cm7.h **** } 3585 .loc 1 1886 26 is_stmt 0 view .LVU1167 3586 0024 164B ldr r3, .L128+4 3587 0026 D868 ldr r0, [r3, #12] 3588 .LBE423: 3589 .LBE422: 1257:Src/main.c **** NVIC_EnableIRQ(TIM6_DAC_IRQn); 3590 .loc 2 1257 3 view .LVU1168 3591 0028 2246 mov r2, r4 3592 002a 2146 mov r1, r4 3593 002c C0F30220 ubfx r0, r0, #8, #3 3594 0030 FFF7FEFF bl NVIC_EncodePriority 3595 .LVL261: 3596 .LBB424: 3597 .LBI424: 2024:Drivers/CMSIS/Include/core_cm7.h **** { 3598 .loc 1 2024 22 is_stmt 1 view .LVU1169 3599 .LBB425: 2026:Drivers/CMSIS/Include/core_cm7.h **** { 3600 .loc 1 2026 3 view .LVU1170 2028:Drivers/CMSIS/Include/core_cm7.h **** } 3601 .loc 1 2028 5 view .LVU1171 2028:Drivers/CMSIS/Include/core_cm7.h **** } 3602 .loc 1 2028 49 is_stmt 0 view .LVU1172 3603 0034 0001 lsls r0, r0, #4 3604 .LVL262: 2028:Drivers/CMSIS/Include/core_cm7.h **** } 3605 .loc 1 2028 49 view .LVU1173 3606 0036 C0B2 uxtb r0, r0 2028:Drivers/CMSIS/Include/core_cm7.h **** } 3607 .loc 1 2028 47 view .LVU1174 3608 0038 124B ldr r3, .L128+8 3609 003a 83F83603 strb r0, [r3, #822] 3610 .LVL263: 2028:Drivers/CMSIS/Include/core_cm7.h **** } 3611 .loc 1 2028 47 view .LVU1175 3612 .LBE425: 3613 .LBE424: ARM GAS /tmp/ccqopZd5.s page 270 1258:Src/main.c **** 3614 .loc 2 1258 3 is_stmt 1 view .LVU1176 3615 .LBB426: 3616 .LBI426: 1896:Drivers/CMSIS/Include/core_cm7.h **** { 3617 .loc 1 1896 22 view .LVU1177 3618 .LBB427: 1898:Drivers/CMSIS/Include/core_cm7.h **** { 3619 .loc 1 1898 3 view .LVU1178 1900:Drivers/CMSIS/Include/core_cm7.h **** } 3620 .loc 1 1900 5 view .LVU1179 1900:Drivers/CMSIS/Include/core_cm7.h **** } 3621 .loc 1 1900 43 is_stmt 0 view .LVU1180 3622 003e 4FF48002 mov r2, #4194304 3623 0042 5A60 str r2, [r3, #4] 3624 .LVL264: 1900:Drivers/CMSIS/Include/core_cm7.h **** } 3625 .loc 1 1900 43 view .LVU1181 3626 .LBE427: 3627 .LBE426: 1263:Src/main.c **** TIM_InitStruct.CounterMode = LL_TIM_COUNTERMODE_UP; 3628 .loc 2 1263 3 is_stmt 1 view .LVU1182 1263:Src/main.c **** TIM_InitStruct.CounterMode = LL_TIM_COUNTERMODE_UP; 3629 .loc 2 1263 28 is_stmt 0 view .LVU1183 3630 0044 4BF2AF33 movw r3, #45999 3631 0048 ADF80430 strh r3, [sp, #4] @ movhi 1264:Src/main.c **** TIM_InitStruct.Autoreload = 19; 3632 .loc 2 1264 3 is_stmt 1 view .LVU1184 1264:Src/main.c **** TIM_InitStruct.Autoreload = 19; 3633 .loc 2 1264 30 is_stmt 0 view .LVU1185 3634 004c 0294 str r4, [sp, #8] 1265:Src/main.c **** LL_TIM_Init(TIM6, &TIM_InitStruct); 3635 .loc 2 1265 3 is_stmt 1 view .LVU1186 1265:Src/main.c **** LL_TIM_Init(TIM6, &TIM_InitStruct); 3636 .loc 2 1265 29 is_stmt 0 view .LVU1187 3637 004e 1323 movs r3, #19 3638 0050 0393 str r3, [sp, #12] 1266:Src/main.c **** LL_TIM_DisableARRPreload(TIM6); 3639 .loc 2 1266 3 is_stmt 1 view .LVU1188 3640 0052 0D4C ldr r4, .L128+12 3641 0054 01A9 add r1, sp, #4 3642 0056 2046 mov r0, r4 3643 0058 FFF7FEFF bl LL_TIM_Init 3644 .LVL265: 1267:Src/main.c **** LL_TIM_SetTriggerOutput(TIM6, LL_TIM_TRGO_ENABLE); 3645 .loc 2 1267 3 view .LVU1189 3646 .LBB428: 3647 .LBI428: 1504:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3648 .loc 5 1504 22 view .LVU1190 3649 .LBB429: 1506:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3650 .loc 5 1506 3 view .LVU1191 3651 005c 2368 ldr r3, [r4] 3652 005e 23F08003 bic r3, r3, #128 3653 0062 2360 str r3, [r4] 3654 .LVL266: ARM GAS /tmp/ccqopZd5.s page 271 1506:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3655 .loc 5 1506 3 is_stmt 0 view .LVU1192 3656 .LBE429: 3657 .LBE428: 1268:Src/main.c **** LL_TIM_DisableMasterSlaveMode(TIM6); 3658 .loc 2 1268 3 is_stmt 1 view .LVU1193 3659 .LBB430: 3660 .LBI430: 3138:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3661 .loc 5 3138 22 view .LVU1194 3662 .LBB431: 3140:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3663 .loc 5 3140 3 view .LVU1195 3664 0064 6368 ldr r3, [r4, #4] 3665 0066 23F07003 bic r3, r3, #112 3666 006a 43F01003 orr r3, r3, #16 3667 006e 6360 str r3, [r4, #4] 3668 .LVL267: 3140:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3669 .loc 5 3140 3 is_stmt 0 view .LVU1196 3670 .LBE431: 3671 .LBE430: 1269:Src/main.c **** /* USER CODE BEGIN TIM6_Init 2 */ 3672 .loc 2 1269 3 is_stmt 1 view .LVU1197 3673 .LBB432: 3674 .LBI432: 3235:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3675 .loc 5 3235 22 view .LVU1198 3676 .LBB433: 3677 .loc 5 3237 3 view .LVU1199 3678 0070 A368 ldr r3, [r4, #8] 3679 0072 23F08003 bic r3, r3, #128 3680 0076 A360 str r3, [r4, #8] 3681 .LVL268: 3682 .loc 5 3237 3 is_stmt 0 view .LVU1200 3683 .LBE433: 3684 .LBE432: 1274:Src/main.c **** 3685 .loc 2 1274 1 view .LVU1201 3686 0078 06B0 add sp, sp, #24 3687 .LCFI37: 3688 .cfi_def_cfa_offset 8 3689 @ sp needed 3690 007a 10BD pop {r4, pc} 3691 .L129: 3692 .align 2 3693 .L128: 3694 007c 00380240 .word 1073887232 3695 0080 00ED00E0 .word -536810240 3696 0084 00E100E0 .word -536813312 3697 0088 00100040 .word 1073745920 3698 .cfi_endproc 3699 .LFE1197: 3701 .section .rodata.Init_params.str1.4,"aMS",%progbits,1 3702 .align 2 3703 .LC0: 3704 0000 2F00 .ascii "/\000" ARM GAS /tmp/ccqopZd5.s page 272 3705 0002 0000 .align 2 3706 .LC1: 3707 0004 434F4D4D .ascii "COMMAND.TXT\000" 3707 414E442E 3707 54585400 3708 .section .text.Init_params,"ax",%progbits 3709 .align 1 3710 .syntax unified 3711 .thumb 3712 .thumb_func 3713 .fpu fpv5-d16 3715 Init_params: 3716 .LFB1206: 1744:Src/main.c **** TO6 = 0; 3717 .loc 2 1744 1 is_stmt 1 view -0 3718 .cfi_startproc 3719 @ args = 0, pretend = 0, frame = 0 3720 @ frame_needed = 0, uses_anonymous_args = 0 3721 0000 2DE9F041 push {r4, r5, r6, r7, r8, lr} 3722 .LCFI38: 3723 .cfi_def_cfa_offset 24 3724 .cfi_offset 4, -24 3725 .cfi_offset 5, -20 3726 .cfi_offset 6, -16 3727 .cfi_offset 7, -12 3728 .cfi_offset 8, -8 3729 .cfi_offset 14, -4 1745:Src/main.c **** TO7 = 0; 3730 .loc 2 1745 2 view .LVU1203 1745:Src/main.c **** TO7 = 0; 3731 .loc 2 1745 6 is_stmt 0 view .LVU1204 3732 0004 0023 movs r3, #0 3733 0006 9C4A ldr r2, .L142 3734 0008 1360 str r3, [r2] 1746:Src/main.c **** TO7_before = 0; 3735 .loc 2 1746 2 is_stmt 1 view .LVU1205 1746:Src/main.c **** TO7_before = 0; 3736 .loc 2 1746 6 is_stmt 0 view .LVU1206 3737 000a 9C4A ldr r2, .L142+4 3738 000c 1360 str r3, [r2] 1747:Src/main.c **** TO6_before = 0; 3739 .loc 2 1747 2 is_stmt 1 view .LVU1207 1747:Src/main.c **** TO6_before = 0; 3740 .loc 2 1747 13 is_stmt 0 view .LVU1208 3741 000e 9C4A ldr r2, .L142+8 3742 0010 1360 str r3, [r2] 1748:Src/main.c **** TO6_uart = 0; 3743 .loc 2 1748 2 is_stmt 1 view .LVU1209 1748:Src/main.c **** TO6_uart = 0; 3744 .loc 2 1748 13 is_stmt 0 view .LVU1210 3745 0012 9C4A ldr r2, .L142+12 3746 0014 1360 str r3, [r2] 1749:Src/main.c **** flg_tmt = 0; 3747 .loc 2 1749 2 is_stmt 1 view .LVU1211 1749:Src/main.c **** flg_tmt = 0; 3748 .loc 2 1749 11 is_stmt 0 view .LVU1212 3749 0016 9C4A ldr r2, .L142+16 ARM GAS /tmp/ccqopZd5.s page 273 3750 0018 1360 str r3, [r2] 1750:Src/main.c **** UART_rec_incr = 0; 3751 .loc 2 1750 2 is_stmt 1 view .LVU1213 1750:Src/main.c **** UART_rec_incr = 0; 3752 .loc 2 1750 10 is_stmt 0 view .LVU1214 3753 001a 9C4A ldr r2, .L142+20 3754 001c 1370 strb r3, [r2] 1751:Src/main.c **** fgoto = 0; 3755 .loc 2 1751 2 is_stmt 1 view .LVU1215 1751:Src/main.c **** fgoto = 0; 3756 .loc 2 1751 16 is_stmt 0 view .LVU1216 3757 001e 9C4A ldr r2, .L142+24 3758 0020 1380 strh r3, [r2] @ movhi 1752:Src/main.c **** sizeoffile = 0; 3759 .loc 2 1752 2 is_stmt 1 view .LVU1217 1752:Src/main.c **** sizeoffile = 0; 3760 .loc 2 1752 8 is_stmt 0 view .LVU1218 3761 0022 9C4A ldr r2, .L142+28 3762 0024 1360 str r3, [r2] 1753:Src/main.c **** u_tx_flg = 0; 3763 .loc 2 1753 2 is_stmt 1 view .LVU1219 1753:Src/main.c **** u_tx_flg = 0; 3764 .loc 2 1753 13 is_stmt 0 view .LVU1220 3765 0026 9C4A ldr r2, .L142+32 3766 0028 1360 str r3, [r2] 1754:Src/main.c **** u_rx_flg = 0; 3767 .loc 2 1754 2 is_stmt 1 view .LVU1221 1754:Src/main.c **** u_rx_flg = 0; 3768 .loc 2 1754 11 is_stmt 0 view .LVU1222 3769 002a 9C4A ldr r2, .L142+36 3770 002c 1370 strb r3, [r2] 1755:Src/main.c **** //State_Data[0]=0; 3771 .loc 2 1755 2 is_stmt 1 view .LVU1223 1755:Src/main.c **** //State_Data[0]=0; 3772 .loc 2 1755 11 is_stmt 0 view .LVU1224 3773 002e 9C4A ldr r2, .L142+40 3774 0030 1370 strb r3, [r2] 1758:Src/main.c **** { 3775 .loc 2 1758 2 is_stmt 1 view .LVU1225 3776 .LBB434: 1758:Src/main.c **** { 3777 .loc 2 1758 7 view .LVU1226 3778 .LVL269: 1758:Src/main.c **** { 3779 .loc 2 1758 2 is_stmt 0 view .LVU1227 3780 0032 05E0 b .L131 3781 .LVL270: 3782 .L132: 1760:Src/main.c **** } 3783 .loc 2 1760 3 is_stmt 1 discriminator 3 view .LVU1228 1760:Src/main.c **** } 3784 .loc 2 1760 16 is_stmt 0 discriminator 3 view .LVU1229 3785 0034 9B4A ldr r2, .L142+44 3786 0036 0021 movs r1, #0 3787 0038 22F81310 strh r1, [r2, r3, lsl #1] @ movhi 1758:Src/main.c **** { 3788 .loc 2 1758 30 is_stmt 1 discriminator 3 view .LVU1230 ARM GAS /tmp/ccqopZd5.s page 274 1758:Src/main.c **** { 3789 .loc 2 1758 31 is_stmt 0 discriminator 3 view .LVU1231 3790 003c 0133 adds r3, r3, #1 3791 .LVL271: 1758:Src/main.c **** { 3792 .loc 2 1758 31 discriminator 3 view .LVU1232 3793 003e 9BB2 uxth r3, r3 3794 .LVL272: 3795 .L131: 1758:Src/main.c **** { 3796 .loc 2 1758 21 is_stmt 1 discriminator 1 view .LVU1233 1758:Src/main.c **** { 3797 .loc 2 1758 2 is_stmt 0 discriminator 1 view .LVU1234 3798 0040 0E2B cmp r3, #14 3799 0042 F7D9 bls .L132 3800 .LBE434: 1762:Src/main.c **** 3801 .loc 2 1762 2 is_stmt 1 view .LVU1235 1762:Src/main.c **** 3802 .loc 2 1762 14 is_stmt 0 view .LVU1236 3803 0044 974B ldr r3, .L142+44 3804 .LVL273: 1762:Src/main.c **** 3805 .loc 2 1762 14 view .LVU1237 3806 0046 41F21112 movw r2, #4369 3807 004a 1A80 strh r2, [r3] @ movhi 1765:Src/main.c **** Def_setup.LD1_EN = 0; 3808 .loc 2 1765 2 is_stmt 1 view .LVU1238 1765:Src/main.c **** Def_setup.LD1_EN = 0; 3809 .loc 2 1765 21 is_stmt 0 view .LVU1239 3810 004c 964B ldr r3, .L142+48 3811 004e 0022 movs r2, #0 3812 0050 DA81 strh r2, [r3, #14] @ movhi 1766:Src/main.c **** Def_setup.LD2_EN = 0; 3813 .loc 2 1766 2 is_stmt 1 view .LVU1240 1766:Src/main.c **** Def_setup.LD2_EN = 0; 3814 .loc 2 1766 19 is_stmt 0 view .LVU1241 3815 0052 DA70 strb r2, [r3, #3] 1767:Src/main.c **** Def_setup.MES_ID = 0; 3816 .loc 2 1767 2 is_stmt 1 view .LVU1242 1767:Src/main.c **** Def_setup.MES_ID = 0; 3817 .loc 2 1767 19 is_stmt 0 view .LVU1243 3818 0054 1A71 strb r2, [r3, #4] 1768:Src/main.c **** Def_setup.PI1_RD = 0; 3819 .loc 2 1768 2 is_stmt 1 view .LVU1244 1768:Src/main.c **** Def_setup.PI1_RD = 0; 3820 .loc 2 1768 19 is_stmt 0 view .LVU1245 3821 0056 1A82 strh r2, [r3, #16] @ movhi 1769:Src/main.c **** Def_setup.PI2_RD = 0; 3822 .loc 2 1769 2 is_stmt 1 view .LVU1246 1769:Src/main.c **** Def_setup.PI2_RD = 0; 3823 .loc 2 1769 19 is_stmt 0 view .LVU1247 3824 0058 1A73 strb r2, [r3, #12] 1770:Src/main.c **** Def_setup.REF1_EN = 0; 3825 .loc 2 1770 2 is_stmt 1 view .LVU1248 1770:Src/main.c **** Def_setup.REF1_EN = 0; 3826 .loc 2 1770 19 is_stmt 0 view .LVU1249 ARM GAS /tmp/ccqopZd5.s page 275 3827 005a 5A73 strb r2, [r3, #13] 1771:Src/main.c **** Def_setup.REF2_EN = 0; 3828 .loc 2 1771 2 is_stmt 1 view .LVU1250 1771:Src/main.c **** Def_setup.REF2_EN = 0; 3829 .loc 2 1771 20 is_stmt 0 view .LVU1251 3830 005c 5A71 strb r2, [r3, #5] 1772:Src/main.c **** Def_setup.SD_EN = 0; 3831 .loc 2 1772 2 is_stmt 1 view .LVU1252 1772:Src/main.c **** Def_setup.SD_EN = 0; 3832 .loc 2 1772 20 is_stmt 0 view .LVU1253 3833 005e 9A71 strb r2, [r3, #6] 1773:Src/main.c **** Def_setup.TEC1_EN = 0; 3834 .loc 2 1773 2 is_stmt 1 view .LVU1254 1773:Src/main.c **** Def_setup.TEC1_EN = 0; 3835 .loc 2 1773 18 is_stmt 0 view .LVU1255 3836 0060 DA72 strb r2, [r3, #11] 1774:Src/main.c **** Def_setup.TEC2_EN = 0; 3837 .loc 2 1774 2 is_stmt 1 view .LVU1256 1774:Src/main.c **** Def_setup.TEC2_EN = 0; 3838 .loc 2 1774 20 is_stmt 0 view .LVU1257 3839 0062 DA71 strb r2, [r3, #7] 1775:Src/main.c **** Def_setup.TS1_EN = 0; 3840 .loc 2 1775 2 is_stmt 1 view .LVU1258 1775:Src/main.c **** Def_setup.TS1_EN = 0; 3841 .loc 2 1775 20 is_stmt 0 view .LVU1259 3842 0064 1A72 strb r2, [r3, #8] 1776:Src/main.c **** Def_setup.TS2_EN = 0; 3843 .loc 2 1776 2 is_stmt 1 view .LVU1260 1776:Src/main.c **** Def_setup.TS2_EN = 0; 3844 .loc 2 1776 19 is_stmt 0 view .LVU1261 3845 0066 5A72 strb r2, [r3, #9] 1777:Src/main.c **** Def_setup.U5V1_EN = 0; 3846 .loc 2 1777 2 is_stmt 1 view .LVU1262 1777:Src/main.c **** Def_setup.U5V1_EN = 0; 3847 .loc 2 1777 19 is_stmt 0 view .LVU1263 3848 0068 9A72 strb r2, [r3, #10] 1778:Src/main.c **** Def_setup.U5V2_EN = 0; 3849 .loc 2 1778 2 is_stmt 1 view .LVU1264 1778:Src/main.c **** Def_setup.U5V2_EN = 0; 3850 .loc 2 1778 20 is_stmt 0 view .LVU1265 3851 006a 5A70 strb r2, [r3, #1] 1779:Src/main.c **** Def_setup.WORK_EN = 0; 3852 .loc 2 1779 2 is_stmt 1 view .LVU1266 1779:Src/main.c **** Def_setup.WORK_EN = 0; 3853 .loc 2 1779 20 is_stmt 0 view .LVU1267 3854 006c 9A70 strb r2, [r3, #2] 1780:Src/main.c **** 3855 .loc 2 1780 2 is_stmt 1 view .LVU1268 1780:Src/main.c **** 3856 .loc 2 1780 20 is_stmt 0 view .LVU1269 3857 006e 1A70 strb r2, [r3] 1782:Src/main.c **** LD2_def_setup.LD_TEMP = 0; 3858 .loc 2 1782 2 is_stmt 1 view .LVU1270 1782:Src/main.c **** LD2_def_setup.LD_TEMP = 0; 3859 .loc 2 1782 24 is_stmt 0 view .LVU1271 3860 0070 8E4D ldr r5, .L142+52 3861 0072 2A80 strh r2, [r5] @ movhi ARM GAS /tmp/ccqopZd5.s page 276 1783:Src/main.c **** LD1_def_setup.P_coef_temp = 0; 3862 .loc 2 1783 2 is_stmt 1 view .LVU1272 1783:Src/main.c **** LD1_def_setup.P_coef_temp = 0; 3863 .loc 2 1783 24 is_stmt 0 view .LVU1273 3864 0074 8E4C ldr r4, .L142+56 3865 0076 2280 strh r2, [r4] @ movhi 1784:Src/main.c **** LD2_def_setup.P_coef_temp = 0; 3866 .loc 2 1784 2 is_stmt 1 view .LVU1274 1784:Src/main.c **** LD2_def_setup.P_coef_temp = 0; 3867 .loc 2 1784 28 is_stmt 0 view .LVU1275 3868 0078 0022 movs r2, #0 3869 007a 6A60 str r2, [r5, #4] @ float 1785:Src/main.c **** LD1_def_setup.I_coef_temp = 0; 3870 .loc 2 1785 2 is_stmt 1 view .LVU1276 1785:Src/main.c **** LD1_def_setup.I_coef_temp = 0; 3871 .loc 2 1785 28 is_stmt 0 view .LVU1277 3872 007c 6260 str r2, [r4, #4] @ float 1786:Src/main.c **** LD2_def_setup.I_coef_temp = 0; 3873 .loc 2 1786 2 is_stmt 1 view .LVU1278 1786:Src/main.c **** LD2_def_setup.I_coef_temp = 0; 3874 .loc 2 1786 28 is_stmt 0 view .LVU1279 3875 007e AA60 str r2, [r5, #8] @ float 1787:Src/main.c **** 3876 .loc 2 1787 2 is_stmt 1 view .LVU1280 1787:Src/main.c **** 3877 .loc 2 1787 28 is_stmt 0 view .LVU1281 3878 0080 A260 str r2, [r4, #8] @ float 1790:Src/main.c **** LD1_curr_setup = LD1_def_setup; 3879 .loc 2 1790 2 is_stmt 1 view .LVU1282 1790:Src/main.c **** LD1_curr_setup = LD1_def_setup; 3880 .loc 2 1790 13 is_stmt 0 view .LVU1283 3881 0082 8C4E ldr r6, .L142+60 3882 0084 9C46 mov ip, r3 3883 0086 BCE80F00 ldmia ip!, {r0, r1, r2, r3} 3884 008a 0FC6 stmia r6!, {r0, r1, r2, r3} 3885 008c DCF80030 ldr r3, [ip] 3886 0090 3380 strh r3, [r6] @ movhi 1791:Src/main.c **** LD2_curr_setup = LD2_def_setup; 3887 .loc 2 1791 2 is_stmt 1 view .LVU1284 1791:Src/main.c **** LD2_curr_setup = LD2_def_setup; 3888 .loc 2 1791 17 is_stmt 0 view .LVU1285 3889 0092 894E ldr r6, .L142+64 3890 0094 95E80F00 ldm r5, {r0, r1, r2, r3} 3891 0098 86E80F00 stm r6, {r0, r1, r2, r3} 1792:Src/main.c **** 3892 .loc 2 1792 2 is_stmt 1 view .LVU1286 1792:Src/main.c **** 3893 .loc 2 1792 17 is_stmt 0 view .LVU1287 3894 009c 874D ldr r5, .L142+68 3895 009e 94E80F00 ldm r4, {r0, r1, r2, r3} 3896 00a2 85E80F00 stm r5, {r0, r1, r2, r3} 1797:Src/main.c **** LL_TIM_EnableCounter(TIM6); 3897 .loc 2 1797 2 is_stmt 1 view .LVU1288 3898 .LVL274: 3899 .LBB435: 3900 .LBI435: 3238:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } ARM GAS /tmp/ccqopZd5.s page 277 3239:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3240:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3241:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Indicates whether the Master/Slave mode is enabled. 3242:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not 3243:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * a timer instance can operate as a slave timer. 3244:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SMCR MSM LL_TIM_IsEnabledMasterSlaveMode 3245:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3246:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval State of bit (1 or 0). 3247:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3248:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsEnabledMasterSlaveMode(const TIM_TypeDef *TIMx) 3249:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3250:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return ((READ_BIT(TIMx->SMCR, TIM_SMCR_MSM) == (TIM_SMCR_MSM)) ? 1UL : 0UL); 3251:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3252:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3253:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3254:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Configure the external trigger (ETR) input. 3255:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_ETR_INSTANCE(TIMx) can be used to check whether or not 3256:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * a timer instance provides an external trigger input. 3257:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SMCR ETP LL_TIM_ConfigETR\n 3258:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * SMCR ETPS LL_TIM_ConfigETR\n 3259:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * SMCR ETF LL_TIM_ConfigETR 3260:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3261:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param ETRPolarity This parameter can be one of the following values: 3262:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ETR_POLARITY_NONINVERTED 3263:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ETR_POLARITY_INVERTED 3264:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param ETRPrescaler This parameter can be one of the following values: 3265:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ETR_PRESCALER_DIV1 3266:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ETR_PRESCALER_DIV2 3267:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ETR_PRESCALER_DIV4 3268:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ETR_PRESCALER_DIV8 3269:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param ETRFilter This parameter can be one of the following values: 3270:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ETR_FILTER_FDIV1 3271:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N2 3272:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N4 3273:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N8 3274:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ETR_FILTER_FDIV2_N6 3275:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ETR_FILTER_FDIV2_N8 3276:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ETR_FILTER_FDIV4_N6 3277:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ETR_FILTER_FDIV4_N8 3278:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ETR_FILTER_FDIV8_N6 3279:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ETR_FILTER_FDIV8_N8 3280:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N5 3281:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N6 3282:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N8 3283:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N5 3284:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N6 3285:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N8 3286:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 3287:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3288:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_ConfigETR(TIM_TypeDef *TIMx, uint32_t ETRPolarity, uint32_t ETRPrescale 3289:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t ETRFilter) 3290:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3291:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(TIMx->SMCR, TIM_SMCR_ETP | TIM_SMCR_ETPS | TIM_SMCR_ETF, ETRPolarity | ETRPrescaler | 3292:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3293:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3294:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3295:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} ARM GAS /tmp/ccqopZd5.s page 278 3296:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3298:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EF_Break_Function Break function configuration 3299:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ 3300:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3301:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3302:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Enable the break function. 3303:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not 3304:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * a timer instance provides a break input. 3305:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll BDTR BKE LL_TIM_EnableBRK 3306:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3307:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 3308:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3309:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_EnableBRK(TIM_TypeDef *TIMx) 3310:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3311:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** SET_BIT(TIMx->BDTR, TIM_BDTR_BKE); 3312:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3313:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Disable the break function. 3316:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll BDTR BKE LL_TIM_DisableBRK 3317:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3318:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not 3319:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * a timer instance provides a break input. 3320:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 3321:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3322:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_DisableBRK(TIM_TypeDef *TIMx) 3323:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3324:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BKE); 3325:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3326:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3327:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3328:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Configure the break input. 3329:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not 3330:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * a timer instance provides a break input. 3331:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll BDTR BKP LL_TIM_ConfigBRK\n 3332:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * BDTR BKF LL_TIM_ConfigBRK 3333:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3334:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param BreakPolarity This parameter can be one of the following values: 3335:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK_POLARITY_LOW 3336:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK_POLARITY_HIGH 3337:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param BreakFilter This parameter can be one of the following values: 3338:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK_FILTER_FDIV1 3339:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N2 3340:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N4 3341:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N8 3342:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N6 3343:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N8 3344:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N6 3345:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N8 3346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N6 3347:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N8 3348:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N5 3349:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N6 3350:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N8 3351:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N5 3352:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N6 ARM GAS /tmp/ccqopZd5.s page 279 3353:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N8 3354:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 3355:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3356:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_ConfigBRK(TIM_TypeDef *TIMx, uint32_t BreakPolarity, 3357:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t BreakFilter) 3358:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3359:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(TIMx->BDTR, TIM_BDTR_BKP | TIM_BDTR_BKF, BreakPolarity | BreakFilter); 3360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3361:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3362:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3363:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Enable the break 2 function. 3364:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not 3365:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * a timer instance provides a second break input. 3366:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll BDTR BK2E LL_TIM_EnableBRK2 3367:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3368:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 3369:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_EnableBRK2(TIM_TypeDef *TIMx) 3371:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** SET_BIT(TIMx->BDTR, TIM_BDTR_BK2E); 3373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3374:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3375:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3376:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Disable the break 2 function. 3377:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not 3378:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * a timer instance provides a second break input. 3379:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll BDTR BK2E LL_TIM_DisableBRK2 3380:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3381:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 3382:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3383:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_DisableBRK2(TIM_TypeDef *TIMx) 3384:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3385:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BK2E); 3386:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3387:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3388:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3389:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Configure the break 2 input. 3390:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not 3391:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * a timer instance provides a second break input. 3392:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll BDTR BK2P LL_TIM_ConfigBRK2\n 3393:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * BDTR BK2F LL_TIM_ConfigBRK2 3394:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3395:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Break2Polarity This parameter can be one of the following values: 3396:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK2_POLARITY_LOW 3397:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK2_POLARITY_HIGH 3398:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Break2Filter This parameter can be one of the following values: 3399:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1 3400:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N2 3401:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N4 3402:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N8 3403:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N6 3404:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N8 3405:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N6 3406:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N8 3407:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N6 3408:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N8 3409:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N5 ARM GAS /tmp/ccqopZd5.s page 280 3410:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N6 3411:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N8 3412:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N5 3413:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N6 3414:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N8 3415:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 3416:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3417:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_ConfigBRK2(TIM_TypeDef *TIMx, uint32_t Break2Polarity, uint32_t Break2F 3418:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3419:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(TIMx->BDTR, TIM_BDTR_BK2P | TIM_BDTR_BK2F, Break2Polarity | Break2Filter); 3420:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3421:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3422:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3423:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Select the outputs off state (enabled v.s. disabled) in Idle and Run modes. 3424:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not 3425:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * a timer instance provides a break input. 3426:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll BDTR OSSI LL_TIM_SetOffStates\n 3427:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * BDTR OSSR LL_TIM_SetOffStates 3428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3429:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param OffStateIdle This parameter can be one of the following values: 3430:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OSSI_DISABLE 3431:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OSSI_ENABLE 3432:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param OffStateRun This parameter can be one of the following values: 3433:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OSSR_DISABLE 3434:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OSSR_ENABLE 3435:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 3436:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3437:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_SetOffStates(TIM_TypeDef *TIMx, uint32_t OffStateIdle, uint32_t OffStat 3438:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3439:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(TIMx->BDTR, TIM_BDTR_OSSI | TIM_BDTR_OSSR, OffStateIdle | OffStateRun); 3440:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3441:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3442:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3443:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Enable automatic output (MOE can be set by software or automatically when a break input 3444:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not 3445:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * a timer instance provides a break input. 3446:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll BDTR AOE LL_TIM_EnableAutomaticOutput 3447:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3448:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 3449:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3450:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_EnableAutomaticOutput(TIM_TypeDef *TIMx) 3451:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3452:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** SET_BIT(TIMx->BDTR, TIM_BDTR_AOE); 3453:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3454:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3455:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3456:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Disable automatic output (MOE can be set only by software). 3457:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not 3458:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * a timer instance provides a break input. 3459:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll BDTR AOE LL_TIM_DisableAutomaticOutput 3460:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3461:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 3462:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_DisableAutomaticOutput(TIM_TypeDef *TIMx) 3464:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3465:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** CLEAR_BIT(TIMx->BDTR, TIM_BDTR_AOE); 3466:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } ARM GAS /tmp/ccqopZd5.s page 281 3467:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3468:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3469:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Indicate whether automatic output is enabled. 3470:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not 3471:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * a timer instance provides a break input. 3472:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll BDTR AOE LL_TIM_IsEnabledAutomaticOutput 3473:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3474:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval State of bit (1 or 0). 3475:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3476:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsEnabledAutomaticOutput(const TIM_TypeDef *TIMx) 3477:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3478:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return ((READ_BIT(TIMx->BDTR, TIM_BDTR_AOE) == (TIM_BDTR_AOE)) ? 1UL : 0UL); 3479:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3480:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3481:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3482:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Enable the outputs (set the MOE bit in TIMx_BDTR register). 3483:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by 3484:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * software and is reset in case of break or break2 event 3485:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not 3486:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * a timer instance provides a break input. 3487:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll BDTR MOE LL_TIM_EnableAllOutputs 3488:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3489:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 3490:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3491:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_EnableAllOutputs(TIM_TypeDef *TIMx) 3492:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3493:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** SET_BIT(TIMx->BDTR, TIM_BDTR_MOE); 3494:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3495:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3496:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3497:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Disable the outputs (reset the MOE bit in TIMx_BDTR register). 3498:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by 3499:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * software and is reset in case of break or break2 event. 3500:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not 3501:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * a timer instance provides a break input. 3502:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll BDTR MOE LL_TIM_DisableAllOutputs 3503:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3504:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 3505:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3506:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_DisableAllOutputs(TIM_TypeDef *TIMx) 3507:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3508:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** CLEAR_BIT(TIMx->BDTR, TIM_BDTR_MOE); 3509:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3510:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3511:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3512:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Indicates whether outputs are enabled. 3513:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not 3514:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * a timer instance provides a break input. 3515:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll BDTR MOE LL_TIM_IsEnabledAllOutputs 3516:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3517:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval State of bit (1 or 0). 3518:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3519:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsEnabledAllOutputs(const TIM_TypeDef *TIMx) 3520:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3521:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return ((READ_BIT(TIMx->BDTR, TIM_BDTR_MOE) == (TIM_BDTR_MOE)) ? 1UL : 0UL); 3522:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3523:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** ARM GAS /tmp/ccqopZd5.s page 282 3524:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #if defined(TIM_BREAK_INPUT_SUPPORT) 3525:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3526:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Enable the signals connected to the designated timer break input. 3527:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether 3528:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * or not a timer instance allows for break input selection. 3529:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll AF1 BKINE LL_TIM_EnableBreakInputSource\n 3530:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * AF1 BKDFBKE LL_TIM_EnableBreakInputSource\n 3531:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * AF2 BK2INE LL_TIM_EnableBreakInputSource\n 3532:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * AF2 BK2DFBKE LL_TIM_EnableBreakInputSource 3533:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3534:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param BreakInput This parameter can be one of the following values: 3535:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK_INPUT_BKIN 3536:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK_INPUT_BKIN2 3537:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Source This parameter can be one of the following values: 3538:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BKIN_SOURCE_BKIN 3539:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BKIN_SOURCE_DF1BK 3540:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 3541:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3542:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_EnableBreakInputSource(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t 3543:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3544:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput)); 3545:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** SET_BIT(*pReg, Source); 3546:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3547:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3548:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3549:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Disable the signals connected to the designated timer break input. 3550:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether 3551:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * or not a timer instance allows for break input selection. 3552:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll AF1 BKINE LL_TIM_DisableBreakInputSource\n 3553:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * AF1 BKDFBKE LL_TIM_DisableBreakInputSource\n 3554:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * AF2 BK2INE LL_TIM_DisableBreakInputSource\n 3555:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * AF2 BK2DFBKE LL_TIM_DisableBreakInputSource 3556:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3557:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param BreakInput This parameter can be one of the following values: 3558:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK_INPUT_BKIN 3559:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK_INPUT_BKIN2 3560:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Source This parameter can be one of the following values: 3561:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BKIN_SOURCE_BKIN 3562:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BKIN_SOURCE_DF1BK 3563:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 3564:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3565:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_DisableBreakInputSource(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_ 3566:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3567:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput)); 3568:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** CLEAR_BIT(*pReg, Source); 3569:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3570:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3571:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3572:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Set the polarity of the break signal for the timer break input. 3573:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether 3574:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * or not a timer instance allows for break input selection. 3575:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll AF1 BKINP LL_TIM_SetBreakInputSourcePolarity\n 3576:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * AF1 BKDFBKP LL_TIM_SetBreakInputSourcePolarity\n 3577:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * AF2 BK2INP LL_TIM_SetBreakInputSourcePolarity\n 3578:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * AF2 BK2DFBKP LL_TIM_SetBreakInputSourcePolarity 3579:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3580:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param BreakInput This parameter can be one of the following values: ARM GAS /tmp/ccqopZd5.s page 283 3581:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK_INPUT_BKIN 3582:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK_INPUT_BKIN2 3583:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Source This parameter can be one of the following values: 3584:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BKIN_SOURCE_BKIN 3585:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BKIN_SOURCE_DF1BK 3586:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Polarity This parameter can be one of the following values: 3587:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BKIN_POLARITY_LOW 3588:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BKIN_POLARITY_HIGH 3589:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 3590:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3591:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_SetBreakInputSourcePolarity(TIM_TypeDef *TIMx, uint32_t BreakInput, uin 3592:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t Polarity) 3593:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3594:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput)); 3595:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(*pReg, (TIMx_AF1_BKINP << TIM_POSITION_BRK_SOURCE), (Polarity << TIM_POSITION_BRK_SOUR 3596:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3597:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #endif /* TIM_BREAK_INPUT_SUPPORT */ 3598:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3599:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} 3600:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3601:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3602:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EF_DMA_Burst_Mode DMA burst mode configuration 3603:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ 3604:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3605:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3606:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Configures the timer DMA burst feature. 3607:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_DMABURST_INSTANCE(TIMx) can be used to check whether or 3608:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * not a timer instance supports the DMA burst mode. 3609:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll DCR DBL LL_TIM_ConfigDMABurst\n 3610:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * DCR DBA LL_TIM_ConfigDMABurst 3611:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3612:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param DMABurstBaseAddress This parameter can be one of the following values: 3613:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_BASEADDR_CR1 3614:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_BASEADDR_CR2 3615:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_BASEADDR_SMCR 3616:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_BASEADDR_DIER 3617:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_BASEADDR_SR 3618:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_BASEADDR_EGR 3619:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR1 3620:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR2 3621:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_BASEADDR_CCER 3622:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_BASEADDR_CNT 3623:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_BASEADDR_PSC 3624:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_BASEADDR_ARR 3625:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_BASEADDR_RCR 3626:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR1 3627:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR2 3628:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR3 3629:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR4 3630:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_BASEADDR_BDTR 3631:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_BASEADDR_OR 3632:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR3 3633:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR5 3634:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR6 3635:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_BASEADDR_AF1 (*) 3636:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_BASEADDR_AF2 (*) 3637:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * (*) value not defined in all devices ARM GAS /tmp/ccqopZd5.s page 284 3638:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param DMABurstLength This parameter can be one of the following values: 3639:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_LENGTH_1TRANSFER 3640:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_LENGTH_2TRANSFERS 3641:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_LENGTH_3TRANSFERS 3642:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_LENGTH_4TRANSFERS 3643:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_LENGTH_5TRANSFERS 3644:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_LENGTH_6TRANSFERS 3645:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_LENGTH_7TRANSFERS 3646:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_LENGTH_8TRANSFERS 3647:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_LENGTH_9TRANSFERS 3648:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_LENGTH_10TRANSFERS 3649:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_LENGTH_11TRANSFERS 3650:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_LENGTH_12TRANSFERS 3651:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_LENGTH_13TRANSFERS 3652:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_LENGTH_14TRANSFERS 3653:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_LENGTH_15TRANSFERS 3654:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_LENGTH_16TRANSFERS 3655:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_LENGTH_17TRANSFERS 3656:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_LENGTH_18TRANSFERS 3657:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 3658:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3659:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_ConfigDMABurst(TIM_TypeDef *TIMx, uint32_t DMABurstBaseAddress, uint32_ 3660:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3661:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(TIMx->DCR, (TIM_DCR_DBL | TIM_DCR_DBA), (DMABurstBaseAddress | DMABurstLength)); 3662:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3663:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3664:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3665:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} 3666:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3667:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3668:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EF_Timer_Inputs_Remapping Timer input remapping 3669:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ 3670:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3671:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3672:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Remap TIM inputs (input channel, internal/external triggers). 3673:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_REMAP_INSTANCE(TIMx) can be used to check whether or not 3674:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * a some timer inputs can be remapped. 3675:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll TIM2_OR ITR1_RMP LL_TIM_SetRemap\n 3676:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * TIM5_OR TI4_RMP LL_TIM_SetRemap\n 3677:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * TIM11_OR TI1_RMP LL_TIM_SetRemap 3678:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3679:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Remap Remap param depends on the TIMx. Description available only 3680:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * in CHM version of the User Manual (not in .pdf). 3681:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * Otherwise see Reference Manual description of OR registers. 3682:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * 3683:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * Below description summarizes "Timer Instance" and "Remap" param combinations: 3684:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * 3685:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * TIM2: one of the following values 3686:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * 3687:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * ITR1_RMP can be one of the following values 3688:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TIM2_ITR1_RMP_TIM8_TRGO 3689:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TIM2_ITR1_RMP_ETH_PTP 3690:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TIM2_ITR1_RMP_OTG_FS_SOF 3691:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TIM2_ITR1_RMP_OTG_HS_SOF 3692:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * 3693:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * TIM5: one of the following values 3694:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * ARM GAS /tmp/ccqopZd5.s page 285 3695:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TIM5_TI4_RMP_GPIO 3696:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TIM5_TI4_RMP_LSI 3697:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TIM5_TI4_RMP_LSE 3698:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TIM5_TI4_RMP_RTC 3699:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * 3700:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * TIM11: one of the following values 3701:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * 3702:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TIM11_TI1_RMP_GPIO 3703:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TIM11_TI1_RMP_SPDIFRX 3704:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TIM11_TI1_RMP_HSE 3705:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TIM11_TI1_RMP_MCO1 3706:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * 3707:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 3708:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3709:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_SetRemap(TIM_TypeDef *TIMx, uint32_t Remap) 3710:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3711:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(TIMx->OR, (Remap >> TIMx_OR_RMP_SHIFT), (Remap & TIMx_OR_RMP_MASK)); 3712:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3713:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3714:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3715:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} 3716:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3717:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3718:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EF_FLAG_Management FLAG-Management 3719:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ 3720:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3721:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3722:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Clear the update interrupt flag (UIF). 3723:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SR UIF LL_TIM_ClearFlag_UPDATE 3724:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3725:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 3726:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3727:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_ClearFlag_UPDATE(TIM_TypeDef *TIMx) 3728:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3729:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** WRITE_REG(TIMx->SR, ~(TIM_SR_UIF)); 3730:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3731:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3732:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3733:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Indicate whether update interrupt flag (UIF) is set (update interrupt is pending). 3734:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SR UIF LL_TIM_IsActiveFlag_UPDATE 3735:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3736:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval State of bit (1 or 0). 3737:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3738:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_UPDATE(const TIM_TypeDef *TIMx) 3739:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3740:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return ((READ_BIT(TIMx->SR, TIM_SR_UIF) == (TIM_SR_UIF)) ? 1UL : 0UL); 3741:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3742:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3743:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3744:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Clear the Capture/Compare 1 interrupt flag (CC1F). 3745:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SR CC1IF LL_TIM_ClearFlag_CC1 3746:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3747:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 3748:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3749:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_ClearFlag_CC1(TIM_TypeDef *TIMx) 3750:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3751:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** WRITE_REG(TIMx->SR, ~(TIM_SR_CC1IF)); ARM GAS /tmp/ccqopZd5.s page 286 3752:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3753:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3754:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3755:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Indicate whether Capture/Compare 1 interrupt flag (CC1F) is set (Capture/Compare 1 inte 3756:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SR CC1IF LL_TIM_IsActiveFlag_CC1 3757:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3758:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval State of bit (1 or 0). 3759:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3760:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1(const TIM_TypeDef *TIMx) 3761:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3762:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return ((READ_BIT(TIMx->SR, TIM_SR_CC1IF) == (TIM_SR_CC1IF)) ? 1UL : 0UL); 3763:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3764:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3765:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3766:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Clear the Capture/Compare 2 interrupt flag (CC2F). 3767:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SR CC2IF LL_TIM_ClearFlag_CC2 3768:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3769:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 3770:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3771:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_ClearFlag_CC2(TIM_TypeDef *TIMx) 3772:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3773:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** WRITE_REG(TIMx->SR, ~(TIM_SR_CC2IF)); 3774:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3775:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3776:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3777:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Indicate whether Capture/Compare 2 interrupt flag (CC2F) is set (Capture/Compare 2 inte 3778:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SR CC2IF LL_TIM_IsActiveFlag_CC2 3779:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3780:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval State of bit (1 or 0). 3781:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3782:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2(const TIM_TypeDef *TIMx) 3783:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3784:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return ((READ_BIT(TIMx->SR, TIM_SR_CC2IF) == (TIM_SR_CC2IF)) ? 1UL : 0UL); 3785:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3786:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3787:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3788:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Clear the Capture/Compare 3 interrupt flag (CC3F). 3789:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SR CC3IF LL_TIM_ClearFlag_CC3 3790:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3791:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 3792:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3793:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_ClearFlag_CC3(TIM_TypeDef *TIMx) 3794:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3795:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** WRITE_REG(TIMx->SR, ~(TIM_SR_CC3IF)); 3796:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3797:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3798:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3799:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Indicate whether Capture/Compare 3 interrupt flag (CC3F) is set (Capture/Compare 3 inte 3800:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SR CC3IF LL_TIM_IsActiveFlag_CC3 3801:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3802:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval State of bit (1 or 0). 3803:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3804:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3(const TIM_TypeDef *TIMx) 3805:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3806:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return ((READ_BIT(TIMx->SR, TIM_SR_CC3IF) == (TIM_SR_CC3IF)) ? 1UL : 0UL); 3807:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3808:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** ARM GAS /tmp/ccqopZd5.s page 287 3809:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3810:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Clear the Capture/Compare 4 interrupt flag (CC4F). 3811:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SR CC4IF LL_TIM_ClearFlag_CC4 3812:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3813:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 3814:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3815:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_ClearFlag_CC4(TIM_TypeDef *TIMx) 3816:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3817:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** WRITE_REG(TIMx->SR, ~(TIM_SR_CC4IF)); 3818:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3819:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3820:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3821:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Indicate whether Capture/Compare 4 interrupt flag (CC4F) is set (Capture/Compare 4 inte 3822:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SR CC4IF LL_TIM_IsActiveFlag_CC4 3823:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3824:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval State of bit (1 or 0). 3825:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3826:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4(const TIM_TypeDef *TIMx) 3827:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3828:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return ((READ_BIT(TIMx->SR, TIM_SR_CC4IF) == (TIM_SR_CC4IF)) ? 1UL : 0UL); 3829:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3830:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3831:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3832:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Clear the Capture/Compare 5 interrupt flag (CC5F). 3833:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SR CC5IF LL_TIM_ClearFlag_CC5 3834:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3835:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 3836:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3837:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_ClearFlag_CC5(TIM_TypeDef *TIMx) 3838:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3839:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** WRITE_REG(TIMx->SR, ~(TIM_SR_CC5IF)); 3840:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3841:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3842:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3843:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Indicate whether Capture/Compare 5 interrupt flag (CC5F) is set (Capture/Compare 5 inte 3844:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SR CC5IF LL_TIM_IsActiveFlag_CC5 3845:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3846:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval State of bit (1 or 0). 3847:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3848:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC5(const TIM_TypeDef *TIMx) 3849:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3850:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return ((READ_BIT(TIMx->SR, TIM_SR_CC5IF) == (TIM_SR_CC5IF)) ? 1UL : 0UL); 3851:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3852:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3853:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3854:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Clear the Capture/Compare 6 interrupt flag (CC6F). 3855:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SR CC6IF LL_TIM_ClearFlag_CC6 3856:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3857:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 3858:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3859:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_ClearFlag_CC6(TIM_TypeDef *TIMx) 3860:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3861:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** WRITE_REG(TIMx->SR, ~(TIM_SR_CC6IF)); 3862:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3863:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3864:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3865:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Indicate whether Capture/Compare 6 interrupt flag (CC6F) is set (Capture/Compare 6 inte ARM GAS /tmp/ccqopZd5.s page 288 3866:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SR CC6IF LL_TIM_IsActiveFlag_CC6 3867:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3868:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval State of bit (1 or 0). 3869:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3870:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC6(const TIM_TypeDef *TIMx) 3871:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3872:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return ((READ_BIT(TIMx->SR, TIM_SR_CC6IF) == (TIM_SR_CC6IF)) ? 1UL : 0UL); 3873:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3874:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3875:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3876:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Clear the commutation interrupt flag (COMIF). 3877:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SR COMIF LL_TIM_ClearFlag_COM 3878:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3879:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 3880:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3881:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_ClearFlag_COM(TIM_TypeDef *TIMx) 3882:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3883:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** WRITE_REG(TIMx->SR, ~(TIM_SR_COMIF)); 3884:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3885:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3886:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3887:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Indicate whether commutation interrupt flag (COMIF) is set (commutation interrupt is pe 3888:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SR COMIF LL_TIM_IsActiveFlag_COM 3889:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3890:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval State of bit (1 or 0). 3891:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3892:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_COM(const TIM_TypeDef *TIMx) 3893:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3894:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return ((READ_BIT(TIMx->SR, TIM_SR_COMIF) == (TIM_SR_COMIF)) ? 1UL : 0UL); 3895:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3896:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3897:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3898:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Clear the trigger interrupt flag (TIF). 3899:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SR TIF LL_TIM_ClearFlag_TRIG 3900:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3901:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 3902:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3903:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_ClearFlag_TRIG(TIM_TypeDef *TIMx) 3904:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3905:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** WRITE_REG(TIMx->SR, ~(TIM_SR_TIF)); 3906:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3908:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3909:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Indicate whether trigger interrupt flag (TIF) is set (trigger interrupt is pending). 3910:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SR TIF LL_TIM_IsActiveFlag_TRIG 3911:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3912:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval State of bit (1 or 0). 3913:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3914:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_TRIG(const TIM_TypeDef *TIMx) 3915:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3916:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return ((READ_BIT(TIMx->SR, TIM_SR_TIF) == (TIM_SR_TIF)) ? 1UL : 0UL); 3917:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3919:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3920:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Clear the break interrupt flag (BIF). 3921:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SR BIF LL_TIM_ClearFlag_BRK 3922:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance ARM GAS /tmp/ccqopZd5.s page 289 3923:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 3924:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3925:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_ClearFlag_BRK(TIM_TypeDef *TIMx) 3926:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3927:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** WRITE_REG(TIMx->SR, ~(TIM_SR_BIF)); 3928:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3929:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3930:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3931:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Indicate whether break interrupt flag (BIF) is set (break interrupt is pending). 3932:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SR BIF LL_TIM_IsActiveFlag_BRK 3933:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3934:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval State of bit (1 or 0). 3935:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3936:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK(const TIM_TypeDef *TIMx) 3937:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3938:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return ((READ_BIT(TIMx->SR, TIM_SR_BIF) == (TIM_SR_BIF)) ? 1UL : 0UL); 3939:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3940:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3941:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3942:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Clear the break 2 interrupt flag (B2IF). 3943:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SR B2IF LL_TIM_ClearFlag_BRK2 3944:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3945:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 3946:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3947:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_ClearFlag_BRK2(TIM_TypeDef *TIMx) 3948:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3949:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** WRITE_REG(TIMx->SR, ~(TIM_SR_B2IF)); 3950:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3951:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3952:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3953:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Indicate whether break 2 interrupt flag (B2IF) is set (break 2 interrupt is pending). 3954:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SR B2IF LL_TIM_IsActiveFlag_BRK2 3955:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3956:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval State of bit (1 or 0). 3957:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3958:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK2(const TIM_TypeDef *TIMx) 3959:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3960:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return ((READ_BIT(TIMx->SR, TIM_SR_B2IF) == (TIM_SR_B2IF)) ? 1UL : 0UL); 3961:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3962:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3963:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3964:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Clear the Capture/Compare 1 over-capture interrupt flag (CC1OF). 3965:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SR CC1OF LL_TIM_ClearFlag_CC1OVR 3966:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3967:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 3968:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3969:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_ClearFlag_CC1OVR(TIM_TypeDef *TIMx) 3970:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3971:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** WRITE_REG(TIMx->SR, ~(TIM_SR_CC1OF)); 3972:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3973:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3974:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3975:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Indicate whether Capture/Compare 1 over-capture interrupt flag (CC1OF) is set 3976:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * (Capture/Compare 1 interrupt is pending). 3977:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SR CC1OF LL_TIM_IsActiveFlag_CC1OVR 3978:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3979:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval State of bit (1 or 0). ARM GAS /tmp/ccqopZd5.s page 290 3980:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3981:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1OVR(const TIM_TypeDef *TIMx) 3982:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3983:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return ((READ_BIT(TIMx->SR, TIM_SR_CC1OF) == (TIM_SR_CC1OF)) ? 1UL : 0UL); 3984:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3985:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3986:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3987:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Clear the Capture/Compare 2 over-capture interrupt flag (CC2OF). 3988:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SR CC2OF LL_TIM_ClearFlag_CC2OVR 3989:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3990:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 3991:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3992:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_ClearFlag_CC2OVR(TIM_TypeDef *TIMx) 3993:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3994:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** WRITE_REG(TIMx->SR, ~(TIM_SR_CC2OF)); 3995:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3996:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3997:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3998:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Indicate whether Capture/Compare 2 over-capture interrupt flag (CC2OF) is set 3999:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * (Capture/Compare 2 over-capture interrupt is pending). 4000:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SR CC2OF LL_TIM_IsActiveFlag_CC2OVR 4001:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 4002:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval State of bit (1 or 0). 4003:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 4004:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2OVR(const TIM_TypeDef *TIMx) 4005:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 4006:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return ((READ_BIT(TIMx->SR, TIM_SR_CC2OF) == (TIM_SR_CC2OF)) ? 1UL : 0UL); 4007:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 4008:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 4009:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 4010:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Clear the Capture/Compare 3 over-capture interrupt flag (CC3OF). 4011:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SR CC3OF LL_TIM_ClearFlag_CC3OVR 4012:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 4013:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 4014:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 4015:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_ClearFlag_CC3OVR(TIM_TypeDef *TIMx) 4016:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 4017:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** WRITE_REG(TIMx->SR, ~(TIM_SR_CC3OF)); 4018:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 4019:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 4020:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 4021:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Indicate whether Capture/Compare 3 over-capture interrupt flag (CC3OF) is set 4022:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * (Capture/Compare 3 over-capture interrupt is pending). 4023:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SR CC3OF LL_TIM_IsActiveFlag_CC3OVR 4024:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 4025:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval State of bit (1 or 0). 4026:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 4027:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3OVR(const TIM_TypeDef *TIMx) 4028:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 4029:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return ((READ_BIT(TIMx->SR, TIM_SR_CC3OF) == (TIM_SR_CC3OF)) ? 1UL : 0UL); 4030:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 4031:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 4032:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 4033:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Clear the Capture/Compare 4 over-capture interrupt flag (CC4OF). 4034:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SR CC4OF LL_TIM_ClearFlag_CC4OVR 4035:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 4036:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None ARM GAS /tmp/ccqopZd5.s page 291 4037:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 4038:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_ClearFlag_CC4OVR(TIM_TypeDef *TIMx) 4039:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 4040:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** WRITE_REG(TIMx->SR, ~(TIM_SR_CC4OF)); 4041:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 4042:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 4043:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 4044:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Indicate whether Capture/Compare 4 over-capture interrupt flag (CC4OF) is set 4045:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * (Capture/Compare 4 over-capture interrupt is pending). 4046:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SR CC4OF LL_TIM_IsActiveFlag_CC4OVR 4047:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 4048:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval State of bit (1 or 0). 4049:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 4050:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4OVR(const TIM_TypeDef *TIMx) 4051:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 4052:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return ((READ_BIT(TIMx->SR, TIM_SR_CC4OF) == (TIM_SR_CC4OF)) ? 1UL : 0UL); 4053:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 4054:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 4055:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 4056:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Clear the system break interrupt flag (SBIF). 4057:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SR SBIF LL_TIM_ClearFlag_SYSBRK 4058:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 4059:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 4060:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 4061:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_ClearFlag_SYSBRK(TIM_TypeDef *TIMx) 4062:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 4063:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** WRITE_REG(TIMx->SR, ~(TIM_SR_SBIF)); 4064:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 4065:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 4066:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 4067:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Indicate whether system break interrupt flag (SBIF) is set (system break interrupt is p 4068:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SR SBIF LL_TIM_IsActiveFlag_SYSBRK 4069:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 4070:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval State of bit (1 or 0). 4071:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 4072:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_SYSBRK(const TIM_TypeDef *TIMx) 4073:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 4074:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return ((READ_BIT(TIMx->SR, TIM_SR_SBIF) == (TIM_SR_SBIF)) ? 1UL : 0UL); 4075:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 4076:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 4077:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 4078:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} 4079:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 4080:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 4081:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EF_IT_Management IT-Management 4082:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ 4083:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 4084:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 4085:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Enable update interrupt (UIE). 4086:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll DIER UIE LL_TIM_EnableIT_UPDATE 4087:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 4088:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 4089:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 4090:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_EnableIT_UPDATE(TIM_TypeDef *TIMx) 3901 .loc 5 4090 22 view .LVU1289 3902 .LBB436: 4091:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { ARM GAS /tmp/ccqopZd5.s page 292 4092:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** SET_BIT(TIMx->DIER, TIM_DIER_UIE); 3903 .loc 5 4092 3 view .LVU1290 3904 00a6 864B ldr r3, .L142+72 3905 00a8 DA68 ldr r2, [r3, #12] 3906 00aa 42F00102 orr r2, r2, #1 3907 00ae DA60 str r2, [r3, #12] 3908 .LVL275: 3909 .loc 5 4092 3 is_stmt 0 view .LVU1291 3910 .LBE436: 3911 .LBE435: 1798:Src/main.c **** LL_TIM_EnableIT_UPDATE(TIM7); 3912 .loc 2 1798 2 is_stmt 1 view .LVU1292 3913 .LBB437: 3914 .LBI437: 1313:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3915 .loc 5 1313 22 view .LVU1293 3916 .LBB438: 1315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3917 .loc 5 1315 3 view .LVU1294 3918 00b0 1A68 ldr r2, [r3] 3919 00b2 42F00102 orr r2, r2, #1 3920 00b6 1A60 str r2, [r3] 3921 .LVL276: 1315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3922 .loc 5 1315 3 is_stmt 0 view .LVU1295 3923 .LBE438: 3924 .LBE437: 1799:Src/main.c **** LL_TIM_EnableCounter(TIM7); 3925 .loc 2 1799 2 is_stmt 1 view .LVU1296 3926 .LBB439: 3927 .LBI439: 4090:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3928 .loc 5 4090 22 view .LVU1297 3929 .LBB440: 3930 .loc 5 4092 3 view .LVU1298 3931 00b8 03F58063 add r3, r3, #1024 3932 00bc DA68 ldr r2, [r3, #12] 3933 00be 42F00102 orr r2, r2, #1 3934 00c2 DA60 str r2, [r3, #12] 3935 .LVL277: 3936 .loc 5 4092 3 is_stmt 0 view .LVU1299 3937 .LBE440: 3938 .LBE439: 1800:Src/main.c **** //HAL_TIM_Base_Start_IT(&htim6); 3939 .loc 2 1800 2 is_stmt 1 view .LVU1300 3940 .LBB441: 3941 .LBI441: 1313:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3942 .loc 5 1313 22 view .LVU1301 3943 .LBB442: 1315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3944 .loc 5 1315 3 view .LVU1302 3945 00c4 1A68 ldr r2, [r3] 3946 00c6 42F00102 orr r2, r2, #1 3947 00ca 1A60 str r2, [r3] 3948 .LVL278: 1315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } ARM GAS /tmp/ccqopZd5.s page 293 3949 .loc 5 1315 3 is_stmt 0 view .LVU1303 3950 .LBE442: 3951 .LBE441: 1807:Src/main.c **** LL_DMA_ClearFlag_TC7(DMA2); 3952 .loc 2 1807 3 is_stmt 1 view .LVU1304 3953 .LBB443: 3954 .LBI443: 3955 .file 6 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h" 1:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 2:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** ****************************************************************************** 3:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @file stm32f7xx_ll_dma.h 4:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @author MCD Application Team 5:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Header file of DMA LL module. 6:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** ****************************************************************************** 7:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @attention 8:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * 9:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * Copyright (c) 2017 STMicroelectronics. 10:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * All rights reserved. 11:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * 12:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * This software is licensed under terms that can be found in the LICENSE file in 13:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * the root directory of this software component. 14:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * If no LICENSE file comes with this software, it is provided AS-IS. 15:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * 16:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** ****************************************************************************** 17:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 18:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 19:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /* Define to prevent recursive inclusion -------------------------------------*/ 20:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #ifndef __STM32F7xx_LL_DMA_H 21:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define __STM32F7xx_LL_DMA_H 22:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 23:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #ifdef __cplusplus 24:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** extern "C" { 25:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #endif 26:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 27:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /* Includes ------------------------------------------------------------------*/ 28:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #include "stm32f7xx.h" 29:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 30:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @addtogroup STM32F7xx_LL_Driver 31:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @{ 32:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 33:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 34:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #if defined (DMA1) || defined (DMA2) 35:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 36:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL DMA 37:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @{ 38:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 39:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 40:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /* Private types -------------------------------------------------------------*/ 41:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /* Private variables ---------------------------------------------------------*/ 42:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_Private_Variables DMA Private Variables 43:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @{ 44:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 45:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /* Array used to get the DMA stream register offset versus stream index LL_DMA_STREAM_x */ 46:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** static const uint8_t STREAM_OFFSET_TAB[] = 47:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 48:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** (uint8_t)(DMA1_Stream0_BASE - DMA1_BASE), 49:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** (uint8_t)(DMA1_Stream1_BASE - DMA1_BASE), ARM GAS /tmp/ccqopZd5.s page 294 50:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** (uint8_t)(DMA1_Stream2_BASE - DMA1_BASE), 51:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** (uint8_t)(DMA1_Stream3_BASE - DMA1_BASE), 52:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** (uint8_t)(DMA1_Stream4_BASE - DMA1_BASE), 53:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** (uint8_t)(DMA1_Stream5_BASE - DMA1_BASE), 54:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** (uint8_t)(DMA1_Stream6_BASE - DMA1_BASE), 55:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** (uint8_t)(DMA1_Stream7_BASE - DMA1_BASE) 56:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }; 57:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 58:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 59:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @} 60:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 61:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 62:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /* Private constants ---------------------------------------------------------*/ 63:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_Private_Constants DMA Private Constants 64:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @{ 65:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 66:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #if defined(DMA_SxCR_CHSEL_3) 67:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define DMA_CHANNEL_SELECTION_8_15 68:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #endif /* DMA_SxCR_CHSEL_3 */ 69:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 70:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @} 71:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 72:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 73:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 74:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /* Private macros ------------------------------------------------------------*/ 75:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /* Exported types ------------------------------------------------------------*/ 76:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #if defined(USE_FULL_LL_DRIVER) 77:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_ES_INIT DMA Exported Init structure 78:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @{ 79:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 80:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** typedef struct 81:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 82:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** uint32_t PeriphOrM2MSrcAddress; /*!< Specifies the peripheral base address for DMA transfer 83:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** or as Source base address in case of memory to memory trans 84:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 85:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** This parameter must be a value between Min_Data = 0 and Max 86:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 87:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** uint32_t MemoryOrM2MDstAddress; /*!< Specifies the memory base address for DMA transfer 88:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** or as Destination base address in case of memory to memory 89:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 90:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** This parameter must be a value between Min_Data = 0 and Max 91:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 92:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** uint32_t Direction; /*!< Specifies if the data will be transferred from memory to pe 93:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** from memory to memory or from peripheral to memory. 94:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** This parameter can be a value of @ref DMA_LL_EC_DIRECTION 95:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 96:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** This feature can be modified afterwards using unitary funct 97:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 98:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** uint32_t Mode; /*!< Specifies the normal or circular operation mode. 99:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** This parameter can be a value of @ref DMA_LL_EC_MODE 100:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** @note The circular buffer mode cannot be used if the memory 101:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** data transfer direction is configured on the selected 102:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 103:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** This feature can be modified afterwards using unitary funct 104:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 105:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** uint32_t PeriphOrM2MSrcIncMode; /*!< Specifies whether the Peripheral address or Source address 106:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** is incremented or not. ARM GAS /tmp/ccqopZd5.s page 295 107:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** This parameter can be a value of @ref DMA_LL_EC_PERIPH 108:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 109:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** This feature can be modified afterwards using unitary funct 110:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 111:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** uint32_t MemoryOrM2MDstIncMode; /*!< Specifies whether the Memory address or Destination address 112:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** is incremented or not. 113:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** This parameter can be a value of @ref DMA_LL_EC_MEMORY 114:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 115:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** This feature can be modified afterwards using unitary funct 116:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 117:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** uint32_t PeriphOrM2MSrcDataSize; /*!< Specifies the Peripheral data size alignment or Source data 118:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** in case of memory to memory transfer direction. 119:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** This parameter can be a value of @ref DMA_LL_EC_PDATAALIGN 120:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 121:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** This feature can be modified afterwards using unitary funct 122:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 123:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** uint32_t MemoryOrM2MDstDataSize; /*!< Specifies the Memory data size alignment or Destination dat 124:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** in case of memory to memory transfer direction. 125:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** This parameter can be a value of @ref DMA_LL_EC_MDATAALIGN 126:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 127:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** This feature can be modified afterwards using unitary funct 128:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 129:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** uint32_t NbData; /*!< Specifies the number of data to transfer, in data unit. 130:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** The data unit is equal to the source buffer configuration s 131:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** or MemorySize parameters depending in the transfer directio 132:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** This parameter must be a value between Min_Data = 0 and Max 133:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 134:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** This feature can be modified afterwards using unitary funct 135:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 136:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** uint32_t Channel; /*!< Specifies the peripheral channel. 137:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** This parameter can be a value of @ref DMA_LL_EC_CHANNEL 138:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 139:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** This feature can be modified afterwards using unitary funct 140:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 141:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** uint32_t Priority; /*!< Specifies the channel priority level. 142:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** This parameter can be a value of @ref DMA_LL_EC_PRIORITY 143:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 144:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** This feature can be modified afterwards using unitary funct 145:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 146:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** uint32_t FIFOMode; /*!< Specifies if the FIFO mode or Direct mode will be used for 147:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** This parameter can be a value of @ref DMA_LL_FIFOMODE 148:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** @note The Direct mode (FIFO mode disabled) cannot be used i 149:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** memory-to-memory data transfer is configured on the selecte 150:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 151:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** This feature can be modified afterwards using unitary funct 152:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 153:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** uint32_t FIFOThreshold; /*!< Specifies the FIFO threshold level. 154:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** This parameter can be a value of @ref DMA_LL_EC_FIFOTHRESHO 155:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 156:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** This feature can be modified afterwards using unitary funct 157:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 158:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** uint32_t MemBurst; /*!< Specifies the Burst transfer configuration for the memory t 159:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** It specifies the amount of data to be transferred in a sing 160:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** transaction. 161:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** This parameter can be a value of @ref DMA_LL_EC_MBURST 162:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** @note The burst mode is possible only if the address Increm 163:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** ARM GAS /tmp/ccqopZd5.s page 296 164:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** This feature can be modified afterwards using unitary funct 165:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 166:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** uint32_t PeriphBurst; /*!< Specifies the Burst transfer configuration for the peripher 167:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** It specifies the amount of data to be transferred in a sing 168:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** transaction. 169:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** This parameter can be a value of @ref DMA_LL_EC_PBURST 170:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** @note The burst mode is possible only if the address Increm 171:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 172:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** This feature can be modified afterwards using unitary funct 173:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 174:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } LL_DMA_InitTypeDef; 175:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 176:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @} 177:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 178:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #endif /*USE_FULL_LL_DRIVER*/ 179:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /* Exported constants --------------------------------------------------------*/ 180:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_Exported_Constants DMA Exported Constants 181:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @{ 182:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 183:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 184:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_EC_STREAM STREAM 185:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @{ 186:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 187:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_STREAM_0 0x00000000U 188:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_STREAM_1 0x00000001U 189:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_STREAM_2 0x00000002U 190:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_STREAM_3 0x00000003U 191:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_STREAM_4 0x00000004U 192:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_STREAM_5 0x00000005U 193:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_STREAM_6 0x00000006U 194:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_STREAM_7 0x00000007U 195:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_STREAM_ALL 0xFFFF0000U 196:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 197:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @} 198:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 199:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 200:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_EC_DIRECTION DIRECTION 201:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @{ 202:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 203:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_DIRECTION_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direc 204:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_DIRECTION_MEMORY_TO_PERIPH DMA_SxCR_DIR_0 /*!< Memory to peripheral direc 205:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_DIRECTION_MEMORY_TO_MEMORY DMA_SxCR_DIR_1 /*!< Memory to memory direction 206:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 207:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @} 208:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 209:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 210:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_EC_MODE MODE 211:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @{ 212:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 213:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_MODE_NORMAL 0x00000000U /*!< Normal Mode 214:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_MODE_CIRCULAR DMA_SxCR_CIRC /*!< Circular Mode 215:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_MODE_PFCTRL DMA_SxCR_PFCTRL /*!< Peripheral flow control mo 216:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 217:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @} 218:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 219:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 220:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_EC_DOUBLEBUFFER_MODE DOUBLE BUFFER MODE ARM GAS /tmp/ccqopZd5.s page 297 221:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @{ 222:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 223:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_DOUBLEBUFFER_MODE_DISABLE 0x00000000U /*!< Disable double buffering m 224:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_DOUBLEBUFFER_MODE_ENABLE DMA_SxCR_DBM /*!< Enable double buffering mo 225:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 226:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @} 227:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 228:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 229:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_EC_PERIPH PERIPH 230:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @{ 231:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 232:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_PERIPH_NOINCREMENT 0x00000000U /*!< Peripheral increment mode 233:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_PERIPH_INCREMENT DMA_SxCR_PINC /*!< Peripheral increment mode 234:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 235:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @} 236:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 237:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 238:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_EC_MEMORY MEMORY 239:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @{ 240:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 241:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_MEMORY_NOINCREMENT 0x00000000U /*!< Memory increment mode Disa 242:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_MEMORY_INCREMENT DMA_SxCR_MINC /*!< Memory increment mode Enab 243:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 244:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @} 245:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 246:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 247:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_EC_PDATAALIGN PDATAALIGN 248:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @{ 249:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 250:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_PDATAALIGN_BYTE 0x00000000U /*!< Peripheral data alignment 251:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_PDATAALIGN_HALFWORD DMA_SxCR_PSIZE_0 /*!< Peripheral data alignment 252:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_PDATAALIGN_WORD DMA_SxCR_PSIZE_1 /*!< Peripheral data alignment 253:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 254:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @} 255:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 256:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 257:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_EC_MDATAALIGN MDATAALIGN 258:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @{ 259:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 260:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_MDATAALIGN_BYTE 0x00000000U /*!< Memory data alignment : By 261:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_MDATAALIGN_HALFWORD DMA_SxCR_MSIZE_0 /*!< Memory data alignment : Ha 262:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_MDATAALIGN_WORD DMA_SxCR_MSIZE_1 /*!< Memory data alignment : Wo 263:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 264:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @} 265:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 266:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 267:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_EC_OFFSETSIZE OFFSETSIZE 268:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @{ 269:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 270:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_OFFSETSIZE_PSIZE 0x00000000U /*!< Peripheral increment offse 271:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_OFFSETSIZE_FIXEDTO4 DMA_SxCR_PINCOS /*!< Peripheral increment offse 272:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 273:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @} 274:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 275:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 276:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_EC_PRIORITY PRIORITY 277:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @{ ARM GAS /tmp/ccqopZd5.s page 298 278:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 279:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_PRIORITY_LOW 0x00000000U /*!< Priority level : Low 280:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_PRIORITY_MEDIUM DMA_SxCR_PL_0 /*!< Priority level : Medium 281:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_PRIORITY_HIGH DMA_SxCR_PL_1 /*!< Priority level : High 282:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_PRIORITY_VERYHIGH DMA_SxCR_PL /*!< Priority level : Very_High 283:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 284:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @} 285:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 286:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 287:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_EC_CHANNEL CHANNEL 288:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @{ 289:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 290:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_CHANNEL_0 0x00000000U 291:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_CHANNEL_1 DMA_SxCR_CHSEL_0 292:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_CHANNEL_2 DMA_SxCR_CHSEL_1 293:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_CHANNEL_3 (DMA_SxCR_CHSEL_0 | DMA_SxCR_CHSEL_1) 294:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_CHANNEL_4 DMA_SxCR_CHSEL_2 295:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_CHANNEL_5 (DMA_SxCR_CHSEL_2 | DMA_SxCR_CHSEL_0) 296:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_CHANNEL_6 (DMA_SxCR_CHSEL_2 | DMA_SxCR_CHSEL_1) 297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_CHANNEL_7 (DMA_SxCR_CHSEL_2 | DMA_SxCR_CHSEL_1 | DMA_SxCR_CHSEL_0) 298:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #if defined(DMA_CHANNEL_SELECTION_8_15) 299:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_CHANNEL_8 DMA_SxCR_CHSEL_3 300:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_CHANNEL_9 (DMA_SxCR_CHSEL_3 | DMA_SxCR_CHSEL_0) 301:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_CHANNEL_10 (DMA_SxCR_CHSEL_3 | DMA_SxCR_CHSEL_1) 302:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_CHANNEL_11 (DMA_SxCR_CHSEL_3 | DMA_SxCR_CHSEL_1 | DMA_SxCR_CHSEL_0) 303:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_CHANNEL_12 (DMA_SxCR_CHSEL_3 | DMA_SxCR_CHSEL_2) 304:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_CHANNEL_13 (DMA_SxCR_CHSEL_3 | DMA_SxCR_CHSEL_2 | DMA_SxCR_CHSEL_0) 305:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_CHANNEL_14 (DMA_SxCR_CHSEL_3 | DMA_SxCR_CHSEL_2 | DMA_SxCR_CHSEL_1) 306:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_CHANNEL_15 DMA_SxCR_CHSEL 307:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #endif /* DMA_CHANNEL_SELECTION_8_15 */ 308:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 309:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @} 310:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 311:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 312:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_EC_MBURST MBURST 313:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @{ 314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_MBURST_SINGLE 0x00000000U /*!< Memory burst 316:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_MBURST_INC4 DMA_SxCR_MBURST_0 /*!< Memory burst 317:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_MBURST_INC8 DMA_SxCR_MBURST_1 /*!< Memory burst 318:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_MBURST_INC16 (DMA_SxCR_MBURST_0 | DMA_SxCR_MBURST_1) /*!< Memory burst 319:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 320:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @} 321:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 322:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 323:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_EC_PBURST PBURST 324:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @{ 325:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 326:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_PBURST_SINGLE 0x00000000U /*!< Peripheral b 327:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_PBURST_INC4 DMA_SxCR_PBURST_0 /*!< Peripheral b 328:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_PBURST_INC8 DMA_SxCR_PBURST_1 /*!< Peripheral b 329:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_PBURST_INC16 (DMA_SxCR_PBURST_0 | DMA_SxCR_PBURST_1) /*!< Peripheral b 330:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 331:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @} 332:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 333:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 334:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_FIFOMODE DMA_LL_FIFOMODE ARM GAS /tmp/ccqopZd5.s page 299 335:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @{ 336:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 337:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_FIFOMODE_DISABLE 0x00000000U /*!< FIFO mode di 338:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_FIFOMODE_ENABLE DMA_SxFCR_DMDIS /*!< FIFO mode en 339:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 340:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @} 341:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 342:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 343:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_EC_FIFOSTATUS_0 FIFOSTATUS 0 344:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @{ 345:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_FIFOSTATUS_0_25 0x00000000U /*!< 0 < fifo_lev 347:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_FIFOSTATUS_25_50 DMA_SxFCR_FS_0 /*!< 1/4 < fifo_l 348:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_FIFOSTATUS_50_75 DMA_SxFCR_FS_1 /*!< 1/2 < fifo_l 349:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_FIFOSTATUS_75_100 (DMA_SxFCR_FS_1 | DMA_SxFCR_FS_0) /*!< 3/4 < fifo_l 350:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_FIFOSTATUS_EMPTY DMA_SxFCR_FS_2 /*!< FIFO is empt 351:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_FIFOSTATUS_FULL (DMA_SxFCR_FS_2 | DMA_SxFCR_FS_0) /*!< FIFO is full 352:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 353:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @} 354:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 355:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 356:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_EC_FIFOTHRESHOLD FIFOTHRESHOLD 357:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @{ 358:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 359:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_FIFOTHRESHOLD_1_4 0x00000000U /*!< FIFO thresho 360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_FIFOTHRESHOLD_1_2 DMA_SxFCR_FTH_0 /*!< FIFO thresho 361:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_FIFOTHRESHOLD_3_4 DMA_SxFCR_FTH_1 /*!< FIFO thresho 362:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_FIFOTHRESHOLD_FULL DMA_SxFCR_FTH /*!< FIFO thresho 363:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 364:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @} 365:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 366:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 367:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_EC_CURRENTTARGETMEM CURRENTTARGETMEM 368:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @{ 369:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_CURRENTTARGETMEM0 0x00000000U /*!< Set CurrentT 371:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_CURRENTTARGETMEM1 DMA_SxCR_CT /*!< Set CurrentT 372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @} 374:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 375:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 376:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 377:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @} 378:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 379:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 380:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /* Exported macro ------------------------------------------------------------*/ 381:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_Exported_Macros DMA Exported Macros 382:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @{ 383:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 384:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 385:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_EM_WRITE_READ Common Write and read registers macros 386:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @{ 387:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 388:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 389:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Write a value in DMA register 390:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param __INSTANCE__ DMA Instance 391:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param __REG__ Register to be written ARM GAS /tmp/ccqopZd5.s page 300 392:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param __VALUE__ Value to be written in the register 393:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 394:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 395:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE 396:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 397:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 398:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Read a value in DMA register 399:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param __INSTANCE__ DMA Instance 400:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param __REG__ Register to be read 401:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval Register value 402:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 403:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) 404:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 405:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @} 406:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 407:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 408:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_EM_CONVERT_DMAxCHANNELy Convert DMAxStreamy 409:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @{ 410:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 411:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 412:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Convert DMAx_Streamy into DMAx 413:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param __STREAM_INSTANCE__ DMAx_Streamy 414:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval DMAx 415:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 416:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define __LL_DMA_GET_INSTANCE(__STREAM_INSTANCE__) \ 417:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** (((uint32_t)(__STREAM_INSTANCE__) > ((uint32_t)DMA1_Stream7)) ? DMA2 : DMA1) 418:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 419:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 420:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Convert DMAx_Streamy into LL_DMA_STREAM_y 421:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param __STREAM_INSTANCE__ DMAx_Streamy 422:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval LL_DMA_CHANNEL_y 423:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 424:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define __LL_DMA_GET_STREAM(__STREAM_INSTANCE__) \ 425:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** (((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream0)) ? LL_DMA_STREAM_0 : \ 426:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream0)) ? LL_DMA_STREAM_0 : \ 427:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream1)) ? LL_DMA_STREAM_1 : \ 428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream1)) ? LL_DMA_STREAM_1 : \ 429:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream2)) ? LL_DMA_STREAM_2 : \ 430:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream2)) ? LL_DMA_STREAM_2 : \ 431:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream3)) ? LL_DMA_STREAM_3 : \ 432:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream3)) ? LL_DMA_STREAM_3 : \ 433:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream4)) ? LL_DMA_STREAM_4 : \ 434:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream4)) ? LL_DMA_STREAM_4 : \ 435:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream5)) ? LL_DMA_STREAM_5 : \ 436:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream5)) ? LL_DMA_STREAM_5 : \ 437:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream6)) ? LL_DMA_STREAM_6 : \ 438:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream6)) ? LL_DMA_STREAM_6 : \ 439:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** LL_DMA_STREAM_7) 440:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 441:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 442:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Convert DMA Instance DMAx and LL_DMA_STREAM_y into DMAx_Streamy 443:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param __DMA_INSTANCE__ DMAx 444:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param __STREAM__ LL_DMA_STREAM_y 445:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval DMAx_Streamy 446:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 447:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define __LL_DMA_GET_STREAM_INSTANCE(__DMA_INSTANCE__, __STREAM__) \ 448:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** ((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DM ARM GAS /tmp/ccqopZd5.s page 301 449:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DM 450:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DM 451:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DM 452:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DM 453:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DM 454:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DM 455:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DM 456:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DM 457:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DM 458:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DM 459:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DM 460:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DM 461:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DM 462:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DM 463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** DMA2_Stream7) 464:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 465:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 466:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @} 467:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 468:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 469:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 470:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @} 471:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 472:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 473:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 474:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /* Exported functions --------------------------------------------------------*/ 475:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_Exported_Functions DMA Exported Functions 476:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @{ 477:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 478:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 479:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_EF_Configuration Configuration 480:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @{ 481:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 482:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 483:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Enable DMA stream. 484:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR EN LL_DMA_EnableStream 485:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 486:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: 487:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 488:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 489:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 490:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 491:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 492:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 493:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 494:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 495:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 496:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 497:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_EnableStream(DMA_TypeDef *DMAx, uint32_t Stream) 498:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 499:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA 500:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 501:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 502:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 503:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Disable DMA stream. 504:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR EN LL_DMA_DisableStream 505:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance ARM GAS /tmp/ccqopZd5.s page 302 506:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: 507:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 508:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 509:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 510:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 511:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 512:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 513:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 514:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 515:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 516:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 517:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_DisableStream(DMA_TypeDef *DMAx, uint32_t Stream) 3956 .loc 6 517 22 view .LVU1305 3957 .LBB444: 518:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 519:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, D 3958 .loc 6 519 3 view .LVU1306 3959 00cc 03F51433 add r3, r3, #151552 3960 00d0 D3F8B820 ldr r2, [r3, #184] 3961 00d4 22F00102 bic r2, r2, #1 3962 00d8 C3F8B820 str r2, [r3, #184] 3963 .LVL279: 3964 .loc 6 519 3 is_stmt 0 view .LVU1307 3965 .LBE444: 3966 .LBE443: 1808:Src/main.c **** LL_DMA_ClearFlag_TE7(DMA2); 3967 .loc 2 1808 3 is_stmt 1 view .LVU1308 3968 .LBB445: 3969 .LBI445: 520:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 521:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 522:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 523:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Check if DMA stream is enabled or disabled. 524:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR EN LL_DMA_IsEnabledStream 525:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 526:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: 527:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 528:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 529:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 530:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 531:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 532:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 533:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 534:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 535:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). 536:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 537:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsEnabledStream(DMA_TypeDef *DMAx, uint32_t Stream) 538:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 539:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))- 540:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 541:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 542:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 543:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Configure all parameters linked to DMA transfer. 544:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR DIR LL_DMA_ConfigTransfer\n 545:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * CR CIRC LL_DMA_ConfigTransfer\n 546:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * CR PINC LL_DMA_ConfigTransfer\n 547:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * CR MINC LL_DMA_ConfigTransfer\n ARM GAS /tmp/ccqopZd5.s page 303 548:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * CR PSIZE LL_DMA_ConfigTransfer\n 549:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * CR MSIZE LL_DMA_ConfigTransfer\n 550:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * CR PL LL_DMA_ConfigTransfer\n 551:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * CR PFCTRL LL_DMA_ConfigTransfer 552:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 553:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: 554:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 555:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 556:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 557:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 558:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 559:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 560:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 561:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 562:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Configuration This parameter must be a combination of all the following values: 563:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY or @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH o 564:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_MODE_NORMAL or @ref LL_DMA_MODE_CIRCULAR or @ref LL_DMA_MODE_PFCTRL 565:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_PERIPH_INCREMENT or @ref LL_DMA_PERIPH_NOINCREMENT 566:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_MEMORY_INCREMENT or @ref LL_DMA_MEMORY_NOINCREMENT 567:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_PDATAALIGN_BYTE or @ref LL_DMA_PDATAALIGN_HALFWORD or @ref LL_DMA_PDAT 568:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_MDATAALIGN_BYTE or @ref LL_DMA_MDATAALIGN_HALFWORD or @ref LL_DMA_MDAT 569:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_PRIORITY_LOW or @ref LL_DMA_PRIORITY_MEDIUM or @ref LL_DMA_PRIORITY_HI 570:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** *@retval None 571:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 572:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ConfigTransfer(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Configurati 573:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 574:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** MODIFY_REG(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, 575:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** DMA_SxCR_DIR | DMA_SxCR_CIRC | DMA_SxCR_PINC | DMA_SxCR_MINC | DMA_SxCR_PSIZE | DMA_Sx 576:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** Configuration); 577:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 578:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 579:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 580:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Set Data transfer direction (read from peripheral or from memory). 581:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR DIR LL_DMA_SetDataTransferDirection 582:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 583:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: 584:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 585:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 586:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 587:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 588:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 589:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 590:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 591:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 592:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Direction This parameter can be one of the following values: 593:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY 594:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH 595:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY 596:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 597:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 598:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_SetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t 599:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 600:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, D 601:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 602:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 603:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 604:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Data transfer direction (read from peripheral or from memory). ARM GAS /tmp/ccqopZd5.s page 304 605:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR DIR LL_DMA_GetDataTransferDirection 606:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 607:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: 608:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 609:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 610:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 611:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 612:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 613:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 614:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 615:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 616:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval Returned value can be one of the following values: 617:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY 618:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH 619:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY 620:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 621:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Stream) 622:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 623:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))- 624:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 625:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 626:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 627:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Set DMA mode normal, circular or peripheral flow control. 628:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR CIRC LL_DMA_SetMode\n 629:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * CR PFCTRL LL_DMA_SetMode 630:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 631:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: 632:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 633:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 634:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 635:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 636:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 637:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 638:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 639:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 640:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Mode This parameter can be one of the following values: 641:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_MODE_NORMAL 642:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_MODE_CIRCULAR 643:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_MODE_PFCTRL 644:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 645:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 646:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_SetMode(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Mode) 647:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 648:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, D 649:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 650:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 651:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 652:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get DMA mode normal, circular or peripheral flow control. 653:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR CIRC LL_DMA_GetMode\n 654:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * CR PFCTRL LL_DMA_GetMode 655:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 656:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: 657:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 658:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 659:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 660:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 661:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 ARM GAS /tmp/ccqopZd5.s page 305 662:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 663:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 664:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 665:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval Returned value can be one of the following values: 666:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_MODE_NORMAL 667:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_MODE_CIRCULAR 668:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_MODE_PFCTRL 669:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 670:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_GetMode(DMA_TypeDef *DMAx, uint32_t Stream) 671:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 672:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))- 673:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 674:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 675:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 676:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Set Peripheral increment mode. 677:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR PINC LL_DMA_SetPeriphIncMode 678:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 679:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: 680:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 681:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 682:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 683:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 684:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 685:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 686:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 687:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 688:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param IncrementMode This parameter can be one of the following values: 689:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_PERIPH_NOINCREMENT 690:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_PERIPH_INCREMENT 691:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 692:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 693:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_SetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Increment 694:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 695:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, D 696:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 697:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 698:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 699:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Peripheral increment mode. 700:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR PINC LL_DMA_GetPeriphIncMode 701:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 702:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: 703:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 704:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 705:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 706:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 707:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 708:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 709:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 710:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 711:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval Returned value can be one of the following values: 712:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_PERIPH_NOINCREMENT 713:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_PERIPH_INCREMENT 714:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 715:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_GetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Stream) 716:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 717:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))- 718:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } ARM GAS /tmp/ccqopZd5.s page 306 719:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 720:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 721:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Set Memory increment mode. 722:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR MINC LL_DMA_SetMemoryIncMode 723:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 724:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: 725:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 726:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 727:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 728:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 729:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 730:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 731:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 732:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 733:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param IncrementMode This parameter can be one of the following values: 734:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_MEMORY_NOINCREMENT 735:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_MEMORY_INCREMENT 736:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 737:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 738:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_SetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Increment 739:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 740:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, D 741:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 742:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 743:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 744:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Memory increment mode. 745:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR MINC LL_DMA_GetMemoryIncMode 746:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 747:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: 748:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 749:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 750:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 751:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 752:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 753:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 754:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 755:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 756:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval Returned value can be one of the following values: 757:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_MEMORY_NOINCREMENT 758:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_MEMORY_INCREMENT 759:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 760:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Stream) 761:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 762:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))- 763:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 764:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 765:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 766:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Set Peripheral size. 767:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR PSIZE LL_DMA_SetPeriphSize 768:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 769:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: 770:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 771:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 772:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 773:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 774:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 775:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 ARM GAS /tmp/ccqopZd5.s page 307 776:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 777:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 778:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Size This parameter can be one of the following values: 779:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_PDATAALIGN_BYTE 780:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_PDATAALIGN_HALFWORD 781:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_PDATAALIGN_WORD 782:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 783:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 784:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_SetPeriphSize(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Size) 785:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 786:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, D 787:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 788:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 789:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 790:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Peripheral size. 791:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR PSIZE LL_DMA_GetPeriphSize 792:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 793:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: 794:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 795:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 796:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 797:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 798:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 799:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 800:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 801:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 802:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval Returned value can be one of the following values: 803:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_PDATAALIGN_BYTE 804:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_PDATAALIGN_HALFWORD 805:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_PDATAALIGN_WORD 806:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 807:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_GetPeriphSize(DMA_TypeDef *DMAx, uint32_t Stream) 808:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 809:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))- 810:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 811:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 812:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 813:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Set Memory size. 814:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR MSIZE LL_DMA_SetMemorySize 815:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 816:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: 817:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 818:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 819:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 820:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 821:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 822:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 823:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 824:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 825:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Size This parameter can be one of the following values: 826:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_MDATAALIGN_BYTE 827:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_MDATAALIGN_HALFWORD 828:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_MDATAALIGN_WORD 829:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 830:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 831:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_SetMemorySize(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Size) 832:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { ARM GAS /tmp/ccqopZd5.s page 308 833:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, D 834:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 835:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 836:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 837:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Memory size. 838:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR MSIZE LL_DMA_GetMemorySize 839:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 840:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: 841:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 842:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 843:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 844:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 845:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 846:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 847:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 848:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 849:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval Returned value can be one of the following values: 850:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_MDATAALIGN_BYTE 851:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_MDATAALIGN_HALFWORD 852:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_MDATAALIGN_WORD 853:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 854:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_GetMemorySize(DMA_TypeDef *DMAx, uint32_t Stream) 855:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 856:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))- 857:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 858:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 859:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 860:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Set Peripheral increment offset size. 861:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR PINCOS LL_DMA_SetIncOffsetSize 862:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 863:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: 864:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 865:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 866:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 867:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 868:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 869:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 870:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 871:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 872:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param OffsetSize This parameter can be one of the following values: 873:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_OFFSETSIZE_PSIZE 874:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_OFFSETSIZE_FIXEDTO4 875:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 876:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 877:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_SetIncOffsetSize(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t OffsetSiz 878:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 879:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, D 880:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 881:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 882:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 883:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Peripheral increment offset size. 884:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR PINCOS LL_DMA_GetIncOffsetSize 885:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 886:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: 887:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 888:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 889:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 ARM GAS /tmp/ccqopZd5.s page 309 890:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 891:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 892:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 893:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 894:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 895:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval Returned value can be one of the following values: 896:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_OFFSETSIZE_PSIZE 897:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_OFFSETSIZE_FIXEDTO4 898:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 899:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_GetIncOffsetSize(DMA_TypeDef *DMAx, uint32_t Stream) 900:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 901:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))- 902:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 903:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 904:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 905:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Set Stream priority level. 906:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR PL LL_DMA_SetStreamPriorityLevel 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 908:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: 909:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 910:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 911:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 912:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 913:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 914:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 915:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 916:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 917:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Priority This parameter can be one of the following values: 918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_PRIORITY_LOW 919:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_PRIORITY_MEDIUM 920:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_PRIORITY_HIGH 921:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_PRIORITY_VERYHIGH 922:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 923:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 924:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_SetStreamPriorityLevel(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Pr 925:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 926:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, D 927:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 928:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 929:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 930:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream priority level. 931:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR PL LL_DMA_GetStreamPriorityLevel 932:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 933:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: 934:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 935:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 936:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 937:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 938:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 939:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 940:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 941:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 942:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval Returned value can be one of the following values: 943:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_PRIORITY_LOW 944:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_PRIORITY_MEDIUM 945:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_PRIORITY_HIGH 946:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_PRIORITY_VERYHIGH ARM GAS /tmp/ccqopZd5.s page 310 947:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 948:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_GetStreamPriorityLevel(DMA_TypeDef *DMAx, uint32_t Stream) 949:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 950:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))- 951:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 952:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 953:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 954:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Set Number of data to transfer. 955:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll NDTR NDT LL_DMA_SetDataLength 956:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @note This action has no effect if 957:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * stream is enabled. 958:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 959:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: 960:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 961:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 962:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 963:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 964:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 965:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 966:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 967:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 968:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param NbData Between 0 to 0xFFFFFFFF 969:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 970:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 971:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_SetDataLength(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t NbData) 972:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 973:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->NDTR, 974:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 975:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 976:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 977:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Number of data to transfer. 978:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll NDTR NDT LL_DMA_GetDataLength 979:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @note Once the stream is enabled, the return value indicate the 980:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * remaining bytes to be transmitted. 981:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 982:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: 983:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 984:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 985:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 986:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 987:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 988:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 989:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 990:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 991:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval Between 0 to 0xFFFFFFFF 992:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 993:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_GetDataLength(DMA_TypeDef* DMAx, uint32_t Stream) 994:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 995:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))- 996:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 997:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 998:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 999:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Select Channel number associated to the Stream. 1000:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR CHSEL LL_DMA_SetChannelSelection 1001:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 1002:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: 1003:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 ARM GAS /tmp/ccqopZd5.s page 311 1004:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 1005:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 1006:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 1007:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 1008:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 1009:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 1010:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 1011:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Channel This parameter can be one of the following values: 1012:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_0 1013:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_1 1014:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_2 1015:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_3 1016:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_4 1017:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_5 1018:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_6 1019:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_7 1020:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_8 (*) 1021:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_9 (*) 1022:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_10 (*) 1023:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_11 (*) 1024:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_12 (*) 1025:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_13 (*) 1026:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_14 (*) 1027:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_15 (*) 1028:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * 1029:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * (*) value not defined in all devices. 1030:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 1031:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1032:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_SetChannelSelection(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Channe 1033:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1034:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, D 1035:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1036:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1037:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1038:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get the Channel number associated to the Stream. 1039:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR CHSEL LL_DMA_GetChannelSelection 1040:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 1041:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: 1042:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 1043:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 1044:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 1045:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 1046:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 1047:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 1048:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 1049:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 1050:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval Returned value can be one of the following values: 1051:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_0 1052:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_1 1053:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_2 1054:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_3 1055:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_4 1056:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_5 1057:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_6 1058:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_7 1059:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_8 (*) 1060:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_9 (*) ARM GAS /tmp/ccqopZd5.s page 312 1061:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_10 (*) 1062:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_11 (*) 1063:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_12 (*) 1064:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_13 (*) 1065:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_14 (*) 1066:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_15 (*) 1067:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * 1068:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * (*) value not defined in all devices. 1069:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1070:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_GetChannelSelection(DMA_TypeDef *DMAx, uint32_t Stream) 1071:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1072:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))- 1073:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1074:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1075:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1076:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Set Memory burst transfer configuration. 1077:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR MBURST LL_DMA_SetMemoryBurstxfer 1078:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 1079:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: 1080:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 1081:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 1082:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 1083:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 1084:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 1085:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 1086:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 1087:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 1088:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Mburst This parameter can be one of the following values: 1089:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_MBURST_SINGLE 1090:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_MBURST_INC4 1091:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_MBURST_INC8 1092:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_MBURST_INC16 1093:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 1094:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1095:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_SetMemoryBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Mburst) 1096:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1097:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, D 1098:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1099:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1100:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1101:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Memory burst transfer configuration. 1102:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR MBURST LL_DMA_GetMemoryBurstxfer 1103:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 1104:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: 1105:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 1106:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 1107:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 1108:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 1109:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 1110:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 1111:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 1112:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 1113:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval Returned value can be one of the following values: 1114:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_MBURST_SINGLE 1115:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_MBURST_INC4 1116:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_MBURST_INC8 1117:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_MBURST_INC16 ARM GAS /tmp/ccqopZd5.s page 313 1118:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1119:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_GetMemoryBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream) 1120:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1121:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))- 1122:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1123:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1124:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1125:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Set Peripheral burst transfer configuration. 1126:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR PBURST LL_DMA_SetPeriphBurstxfer 1127:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 1128:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: 1129:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 1130:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 1131:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 1132:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 1133:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 1134:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 1135:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 1136:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 1137:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Pburst This parameter can be one of the following values: 1138:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_PBURST_SINGLE 1139:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_PBURST_INC4 1140:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_PBURST_INC8 1141:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_PBURST_INC16 1142:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 1143:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1144:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_SetPeriphBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Pburst) 1145:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1146:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, D 1147:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1148:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1149:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1150:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Peripheral burst transfer configuration. 1151:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR PBURST LL_DMA_GetPeriphBurstxfer 1152:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 1153:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: 1154:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 1155:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 1156:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 1157:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 1158:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 1159:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 1160:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 1161:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 1162:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval Returned value can be one of the following values: 1163:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_PBURST_SINGLE 1164:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_PBURST_INC4 1165:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_PBURST_INC8 1166:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_PBURST_INC16 1167:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1168:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_GetPeriphBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream) 1169:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1170:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))- 1171:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1172:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1173:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1174:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Set Current target (only in double buffer mode) to Memory 1 or Memory 0. ARM GAS /tmp/ccqopZd5.s page 314 1175:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR CT LL_DMA_SetCurrentTargetMem 1176:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 1177:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: 1178:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 1179:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 1180:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 1181:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 1182:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 1183:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 1184:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 1185:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 1186:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param CurrentMemory This parameter can be one of the following values: 1187:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CURRENTTARGETMEM0 1188:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CURRENTTARGETMEM1 1189:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 1190:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1191:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_SetCurrentTargetMem(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Curren 1192:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1193:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, 1194:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1195:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1196:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1197:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Set Current target (only in double buffer mode) to Memory 1 or Memory 0. 1198:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR CT LL_DMA_GetCurrentTargetMem 1199:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 1200:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: 1201:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 1202:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 1203:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 1204:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 1205:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 1206:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 1207:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 1208:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 1209:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval Returned value can be one of the following values: 1210:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CURRENTTARGETMEM0 1211:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CURRENTTARGETMEM1 1212:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1213:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_GetCurrentTargetMem(DMA_TypeDef *DMAx, uint32_t Stream) 1214:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1215:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))- 1216:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1217:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1218:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1219:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Enable the double buffer mode. 1220:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR DBM LL_DMA_EnableDoubleBufferMode 1221:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 1222:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: 1223:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 1224:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 1225:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 1226:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 1227:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 1228:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 1229:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 1230:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 1231:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None ARM GAS /tmp/ccqopZd5.s page 315 1232:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1233:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_EnableDoubleBufferMode(DMA_TypeDef *DMAx, uint32_t Stream) 1234:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1235:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA 1236:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1237:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1238:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1239:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Disable the double buffer mode. 1240:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR DBM LL_DMA_DisableDoubleBufferMode 1241:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 1242:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: 1243:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 1244:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 1245:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 1246:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 1247:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 1248:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 1249:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 1250:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 1251:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 1252:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1253:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_DisableDoubleBufferMode(DMA_TypeDef *DMAx, uint32_t Stream) 1254:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1255:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, D 1256:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1257:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1258:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1259:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get FIFO status. 1260:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll FCR FS LL_DMA_GetFIFOStatus 1261:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 1262:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: 1263:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 1264:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 1265:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 1266:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 1267:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 1268:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 1269:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 1270:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 1271:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval Returned value can be one of the following values: 1272:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_FIFOSTATUS_0_25 1273:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_FIFOSTATUS_25_50 1274:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_FIFOSTATUS_50_75 1275:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_FIFOSTATUS_75_100 1276:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_FIFOSTATUS_EMPTY 1277:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_FIFOSTATUS_FULL 1278:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1279:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_GetFIFOStatus(DMA_TypeDef *DMAx, uint32_t Stream) 1280:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1281:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))- 1282:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1283:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1284:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1285:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Disable Fifo mode. 1286:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll FCR DMDIS LL_DMA_DisableFifoMode 1287:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 1288:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: ARM GAS /tmp/ccqopZd5.s page 316 1289:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 1290:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 1291:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 1292:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 1293:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 1294:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 1295:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 1296:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 1297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 1298:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1299:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_DisableFifoMode(DMA_TypeDef *DMAx, uint32_t Stream) 1300:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1301:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, 1302:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1303:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1304:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1305:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Enable Fifo mode. 1306:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll FCR DMDIS LL_DMA_EnableFifoMode 1307:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 1308:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: 1309:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 1310:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 1311:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 1312:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 1313:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 1314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 1315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 1316:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 1317:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 1318:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1319:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_EnableFifoMode(DMA_TypeDef *DMAx, uint32_t Stream) 1320:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1321:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DM 1322:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1323:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1324:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1325:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Select FIFO threshold. 1326:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll FCR FTH LL_DMA_SetFIFOThreshold 1327:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 1328:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: 1329:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 1330:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 1331:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 1332:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 1333:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 1334:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 1335:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 1336:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 1337:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Threshold This parameter can be one of the following values: 1338:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_FIFOTHRESHOLD_1_4 1339:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_FIFOTHRESHOLD_1_2 1340:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_FIFOTHRESHOLD_3_4 1341:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_FIFOTHRESHOLD_FULL 1342:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 1343:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1344:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_SetFIFOThreshold(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Threshold 1345:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { ARM GAS /tmp/ccqopZd5.s page 317 1346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, 1347:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1348:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1349:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1350:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get FIFO threshold. 1351:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll FCR FTH LL_DMA_GetFIFOThreshold 1352:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 1353:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: 1354:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 1355:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 1356:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 1357:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 1358:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 1359:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 1360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 1361:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 1362:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval Returned value can be one of the following values: 1363:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_FIFOTHRESHOLD_1_4 1364:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_FIFOTHRESHOLD_1_2 1365:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_FIFOTHRESHOLD_3_4 1366:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_FIFOTHRESHOLD_FULL 1367:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1368:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_GetFIFOThreshold(DMA_TypeDef *DMAx, uint32_t Stream) 1369:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))- 1371:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1374:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Configure the FIFO . 1375:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll FCR FTH LL_DMA_ConfigFifo\n 1376:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * FCR DMDIS LL_DMA_ConfigFifo 1377:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 1378:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: 1379:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 1380:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 1381:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 1382:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 1383:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 1384:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 1385:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 1386:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 1387:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param FifoMode This parameter can be one of the following values: 1388:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_FIFOMODE_ENABLE 1389:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_FIFOMODE_DISABLE 1390:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param FifoThreshold This parameter can be one of the following values: 1391:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_FIFOTHRESHOLD_1_4 1392:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_FIFOTHRESHOLD_1_2 1393:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_FIFOTHRESHOLD_3_4 1394:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_FIFOTHRESHOLD_FULL 1395:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 1396:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1397:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ConfigFifo(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t FifoMode, uint3 1398:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1399:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, 1400:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1401:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1402:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** ARM GAS /tmp/ccqopZd5.s page 318 1403:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Configure the Source and Destination addresses. 1404:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @note This API must not be called when the DMA stream is enabled. 1405:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll M0AR M0A LL_DMA_ConfigAddresses\n 1406:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * PAR PA LL_DMA_ConfigAddresses 1407:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 1408:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: 1409:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 1410:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 1411:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 1412:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 1413:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 1414:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 1415:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 1416:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 1417:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param SrcAddress Between 0 to 0xFFFFFFFF 1418:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DstAddress Between 0 to 0xFFFFFFFF 1419:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Direction This parameter can be one of the following values: 1420:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY 1421:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH 1422:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY 1423:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 1424:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1425:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ConfigAddresses(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t SrcAddress 1426:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1427:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /* Direction Memory to Periph */ 1428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** if (Direction == LL_DMA_DIRECTION_MEMORY_TO_PERIPH) 1429:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1430:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR 1431:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR, 1432:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1433:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /* Direction Periph to Memory and Memory to Memory */ 1434:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** else 1435:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1436:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR, 1437:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR 1438:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1439:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1440:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1441:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1442:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Set the Memory address. 1443:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll M0AR M0A LL_DMA_SetMemoryAddress 1444:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMO 1445:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @note This API must not be called when the DMA channel is enabled. 1446:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 1447:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: 1448:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 1449:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 1450:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 1451:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 1452:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 1453:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 1454:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 1455:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 1456:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param MemoryAddress Between 0 to 0xFFFFFFFF 1457:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 1458:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1459:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_SetMemoryAddress(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t MemoryAdd ARM GAS /tmp/ccqopZd5.s page 319 1460:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1461:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR, 1462:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1464:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1465:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Set the Peripheral address. 1466:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll PAR PA LL_DMA_SetPeriphAddress 1467:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMO 1468:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @note This API must not be called when the DMA channel is enabled. 1469:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 1470:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: 1471:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 1472:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 1473:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 1474:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 1475:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 1476:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 1477:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 1478:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 1479:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param PeriphAddress Between 0 to 0xFFFFFFFF 1480:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 1481:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1482:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_SetPeriphAddress(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t PeriphAdd 1483:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1484:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR, P 1485:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1486:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1487:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1488:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get the Memory address. 1489:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll M0AR M0A LL_DMA_GetMemoryAddress 1490:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMO 1491:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 1492:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: 1493:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 1494:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 1495:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 1496:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 1497:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 1498:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 1499:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 1500:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 1501:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval Between 0 to 0xFFFFFFFF 1502:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1503:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress(DMA_TypeDef* DMAx, uint32_t Stream) 1504:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1505:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))- 1506:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1507:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1508:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1509:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get the Peripheral address. 1510:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll PAR PA LL_DMA_GetPeriphAddress 1511:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMO 1512:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 1513:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: 1514:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 1515:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 1516:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 ARM GAS /tmp/ccqopZd5.s page 320 1517:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 1518:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 1519:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 1520:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 1521:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 1522:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval Between 0 to 0xFFFFFFFF 1523:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1524:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress(DMA_TypeDef* DMAx, uint32_t Stream) 1525:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1526:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_REG(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream]))) 1527:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1528:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1529:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1530:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Set the Memory to Memory Source address. 1531:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll PAR PA LL_DMA_SetM2MSrcAddress 1532:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only. 1533:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @note This API must not be called when the DMA channel is enabled. 1534:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 1535:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: 1536:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 1537:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 1538:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 1539:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 1540:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 1541:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 1542:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 1543:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 1544:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param MemoryAddress Between 0 to 0xFFFFFFFF 1545:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 1546:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1547:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_SetM2MSrcAddress(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t MemoryAdd 1548:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1549:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR, M 1550:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1551:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1552:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1553:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Set the Memory to Memory Destination address. 1554:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll M0AR M0A LL_DMA_SetM2MDstAddress 1555:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only. 1556:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @note This API must not be called when the DMA channel is enabled. 1557:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 1558:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: 1559:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 1560:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 1561:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 1562:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 1563:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 1564:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 1565:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 1566:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 1567:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param MemoryAddress Between 0 to 0xFFFFFFFF 1568:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 1569:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1570:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_SetM2MDstAddress(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t MemoryAdd 1571:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1572:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR 1573:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } ARM GAS /tmp/ccqopZd5.s page 321 1574:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1575:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1576:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get the Memory to Memory Source address. 1577:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll PAR PA LL_DMA_GetM2MSrcAddress 1578:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only. 1579:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 1580:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: 1581:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 1582:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 1583:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 1584:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 1585:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 1586:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 1587:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 1588:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 1589:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval Between 0 to 0xFFFFFFFF 1590:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1591:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress(DMA_TypeDef* DMAx, uint32_t Stream) 1592:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1593:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_REG(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])) 1594:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1595:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1596:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1597:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get the Memory to Memory Destination address. 1598:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll M0AR M0A LL_DMA_GetM2MDstAddress 1599:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only. 1600:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 1601:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: 1602:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 1603:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 1604:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 1605:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 1606:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 1607:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 1608:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 1609:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 1610:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval Between 0 to 0xFFFFFFFF 1611:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1612:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(DMA_TypeDef* DMAx, uint32_t Stream) 1613:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1614:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))-> 1615:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1616:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1617:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1618:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Set Memory 1 address (used in case of Double buffer mode). 1619:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll M1AR M1A LL_DMA_SetMemory1Address 1620:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 1621:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: 1622:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 1623:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 1624:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 1625:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 1626:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 1627:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 1628:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 1629:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 1630:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Address Between 0 to 0xFFFFFFFF ARM GAS /tmp/ccqopZd5.s page 322 1631:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 1632:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1633:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_SetMemory1Address(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Address) 1634:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1635:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M1AR, 1636:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1637:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1638:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1639:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Memory 1 address (used in case of Double buffer mode). 1640:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll M1AR M1A LL_DMA_GetMemory1Address 1641:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 1642:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: 1643:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 1644:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 1645:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 1646:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 1647:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 1648:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 1649:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 1650:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 1651:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval Between 0 to 0xFFFFFFFF 1652:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1653:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_GetMemory1Address(DMA_TypeDef *DMAx, uint32_t Stream) 1654:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1655:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M1AR); 1656:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1657:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1658:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1659:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @} 1660:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1661:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1662:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_EF_FLAG_Management FLAG_Management 1663:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @{ 1664:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1665:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1666:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1667:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 0 half transfer flag. 1668:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LISR HTIF0 LL_DMA_IsActiveFlag_HT0 1669:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 1670:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). 1671:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1672:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT0(DMA_TypeDef *DMAx) 1673:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1674:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->LISR ,DMA_LISR_HTIF0)==(DMA_LISR_HTIF0)); 1675:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1676:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1677:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1678:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 1 half transfer flag. 1679:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LISR HTIF1 LL_DMA_IsActiveFlag_HT1 1680:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 1681:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). 1682:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1683:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT1(DMA_TypeDef *DMAx) 1684:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1685:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->LISR ,DMA_LISR_HTIF1)==(DMA_LISR_HTIF1)); 1686:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1687:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** ARM GAS /tmp/ccqopZd5.s page 323 1688:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1689:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 2 half transfer flag. 1690:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LISR HTIF2 LL_DMA_IsActiveFlag_HT2 1691:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 1692:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). 1693:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1694:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT2(DMA_TypeDef *DMAx) 1695:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1696:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->LISR ,DMA_LISR_HTIF2)==(DMA_LISR_HTIF2)); 1697:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1698:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1699:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1700:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 3 half transfer flag. 1701:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LISR HTIF3 LL_DMA_IsActiveFlag_HT3 1702:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 1703:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). 1704:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1705:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT3(DMA_TypeDef *DMAx) 1706:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1707:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->LISR ,DMA_LISR_HTIF3)==(DMA_LISR_HTIF3)); 1708:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1709:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1710:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1711:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 4 half transfer flag. 1712:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HISR HTIF4 LL_DMA_IsActiveFlag_HT4 1713:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 1714:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). 1715:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1716:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT4(DMA_TypeDef *DMAx) 1717:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1718:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->HISR ,DMA_HISR_HTIF4)==(DMA_HISR_HTIF4)); 1719:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1720:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1721:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1722:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 5 half transfer flag. 1723:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HISR HTIF0 LL_DMA_IsActiveFlag_HT5 1724:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 1725:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). 1726:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1727:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT5(DMA_TypeDef *DMAx) 1728:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1729:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->HISR ,DMA_HISR_HTIF5)==(DMA_HISR_HTIF5)); 1730:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1731:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1732:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1733:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 6 half transfer flag. 1734:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HISR HTIF6 LL_DMA_IsActiveFlag_HT6 1735:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 1736:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). 1737:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1738:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT6(DMA_TypeDef *DMAx) 1739:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1740:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->HISR ,DMA_HISR_HTIF6)==(DMA_HISR_HTIF6)); 1741:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1742:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1743:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1744:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 7 half transfer flag. ARM GAS /tmp/ccqopZd5.s page 324 1745:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HISR HTIF7 LL_DMA_IsActiveFlag_HT7 1746:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 1747:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). 1748:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1749:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT7(DMA_TypeDef *DMAx) 1750:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1751:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->HISR ,DMA_HISR_HTIF7)==(DMA_HISR_HTIF7)); 1752:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1753:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1754:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1755:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 0 transfer complete flag. 1756:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LISR TCIF0 LL_DMA_IsActiveFlag_TC0 1757:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 1758:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). 1759:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1760:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC0(DMA_TypeDef *DMAx) 1761:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1762:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->LISR ,DMA_LISR_TCIF0)==(DMA_LISR_TCIF0)); 1763:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1764:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1765:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1766:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 1 transfer complete flag. 1767:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LISR TCIF1 LL_DMA_IsActiveFlag_TC1 1768:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 1769:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). 1770:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1771:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC1(DMA_TypeDef *DMAx) 1772:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1773:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->LISR ,DMA_LISR_TCIF1)==(DMA_LISR_TCIF1)); 1774:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1775:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1776:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1777:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 2 transfer complete flag. 1778:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LISR TCIF2 LL_DMA_IsActiveFlag_TC2 1779:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 1780:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). 1781:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1782:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC2(DMA_TypeDef *DMAx) 1783:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1784:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->LISR ,DMA_LISR_TCIF2)==(DMA_LISR_TCIF2)); 1785:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1786:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1787:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1788:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 3 transfer complete flag. 1789:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LISR TCIF3 LL_DMA_IsActiveFlag_TC3 1790:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 1791:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). 1792:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1793:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC3(DMA_TypeDef *DMAx) 1794:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1795:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->LISR ,DMA_LISR_TCIF3)==(DMA_LISR_TCIF3)); 1796:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1797:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1798:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1799:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 4 transfer complete flag. 1800:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HISR TCIF4 LL_DMA_IsActiveFlag_TC4 1801:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance ARM GAS /tmp/ccqopZd5.s page 325 1802:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). 1803:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1804:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC4(DMA_TypeDef *DMAx) 1805:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1806:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->HISR ,DMA_HISR_TCIF4)==(DMA_HISR_TCIF4)); 1807:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1808:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1809:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1810:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 5 transfer complete flag. 1811:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HISR TCIF0 LL_DMA_IsActiveFlag_TC5 1812:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 1813:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). 1814:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1815:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC5(DMA_TypeDef *DMAx) 1816:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1817:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->HISR ,DMA_HISR_TCIF5)==(DMA_HISR_TCIF5)); 1818:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1819:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1820:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1821:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 6 transfer complete flag. 1822:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HISR TCIF6 LL_DMA_IsActiveFlag_TC6 1823:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 1824:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). 1825:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1826:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC6(DMA_TypeDef *DMAx) 1827:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1828:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->HISR ,DMA_HISR_TCIF6)==(DMA_HISR_TCIF6)); 1829:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1830:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1831:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1832:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 7 transfer complete flag. 1833:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HISR TCIF7 LL_DMA_IsActiveFlag_TC7 1834:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 1835:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). 1836:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1837:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC7(DMA_TypeDef *DMAx) 1838:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1839:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->HISR ,DMA_HISR_TCIF7)==(DMA_HISR_TCIF7)); 1840:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1841:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1842:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1843:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 0 transfer error flag. 1844:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LISR TEIF0 LL_DMA_IsActiveFlag_TE0 1845:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 1846:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). 1847:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1848:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE0(DMA_TypeDef *DMAx) 1849:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1850:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->LISR ,DMA_LISR_TEIF0)==(DMA_LISR_TEIF0)); 1851:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1852:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1853:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1854:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 1 transfer error flag. 1855:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LISR TEIF1 LL_DMA_IsActiveFlag_TE1 1856:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 1857:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). 1858:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ ARM GAS /tmp/ccqopZd5.s page 326 1859:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE1(DMA_TypeDef *DMAx) 1860:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1861:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->LISR ,DMA_LISR_TEIF1)==(DMA_LISR_TEIF1)); 1862:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1863:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1864:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1865:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 2 transfer error flag. 1866:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LISR TEIF2 LL_DMA_IsActiveFlag_TE2 1867:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 1868:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). 1869:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1870:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE2(DMA_TypeDef *DMAx) 1871:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1872:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->LISR ,DMA_LISR_TEIF2)==(DMA_LISR_TEIF2)); 1873:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1874:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1875:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1876:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 3 transfer error flag. 1877:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LISR TEIF3 LL_DMA_IsActiveFlag_TE3 1878:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 1879:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). 1880:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1881:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE3(DMA_TypeDef *DMAx) 1882:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1883:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->LISR ,DMA_LISR_TEIF3)==(DMA_LISR_TEIF3)); 1884:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1885:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1886:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1887:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 4 transfer error flag. 1888:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HISR TEIF4 LL_DMA_IsActiveFlag_TE4 1889:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 1890:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). 1891:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1892:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE4(DMA_TypeDef *DMAx) 1893:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1894:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->HISR ,DMA_HISR_TEIF4)==(DMA_HISR_TEIF4)); 1895:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1896:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1897:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1898:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 5 transfer error flag. 1899:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HISR TEIF0 LL_DMA_IsActiveFlag_TE5 1900:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 1901:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). 1902:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1903:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE5(DMA_TypeDef *DMAx) 1904:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1905:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->HISR ,DMA_HISR_TEIF5)==(DMA_HISR_TEIF5)); 1906:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1908:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1909:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 6 transfer error flag. 1910:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HISR TEIF6 LL_DMA_IsActiveFlag_TE6 1911:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 1912:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). 1913:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1914:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE6(DMA_TypeDef *DMAx) 1915:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { ARM GAS /tmp/ccqopZd5.s page 327 1916:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->HISR ,DMA_HISR_TEIF6)==(DMA_HISR_TEIF6)); 1917:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1919:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1920:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 7 transfer error flag. 1921:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HISR TEIF7 LL_DMA_IsActiveFlag_TE7 1922:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 1923:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). 1924:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1925:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE7(DMA_TypeDef *DMAx) 1926:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1927:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->HISR ,DMA_HISR_TEIF7)==(DMA_HISR_TEIF7)); 1928:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1929:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1930:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1931:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 0 direct mode error flag. 1932:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LISR DMEIF0 LL_DMA_IsActiveFlag_DME0 1933:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 1934:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). 1935:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1936:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME0(DMA_TypeDef *DMAx) 1937:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1938:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->LISR ,DMA_LISR_DMEIF0)==(DMA_LISR_DMEIF0)); 1939:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1940:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1941:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1942:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 1 direct mode error flag. 1943:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LISR DMEIF1 LL_DMA_IsActiveFlag_DME1 1944:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 1945:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). 1946:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1947:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME1(DMA_TypeDef *DMAx) 1948:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1949:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->LISR ,DMA_LISR_DMEIF1)==(DMA_LISR_DMEIF1)); 1950:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1951:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1952:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1953:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 2 direct mode error flag. 1954:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LISR DMEIF2 LL_DMA_IsActiveFlag_DME2 1955:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 1956:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). 1957:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1958:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME2(DMA_TypeDef *DMAx) 1959:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1960:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->LISR ,DMA_LISR_DMEIF2)==(DMA_LISR_DMEIF2)); 1961:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1962:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1963:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1964:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 3 direct mode error flag. 1965:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LISR DMEIF3 LL_DMA_IsActiveFlag_DME3 1966:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 1967:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). 1968:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1969:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME3(DMA_TypeDef *DMAx) 1970:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1971:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->LISR ,DMA_LISR_DMEIF3)==(DMA_LISR_DMEIF3)); 1972:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } ARM GAS /tmp/ccqopZd5.s page 328 1973:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1974:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1975:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 4 direct mode error flag. 1976:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HISR DMEIF4 LL_DMA_IsActiveFlag_DME4 1977:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 1978:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). 1979:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1980:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME4(DMA_TypeDef *DMAx) 1981:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1982:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->HISR ,DMA_HISR_DMEIF4)==(DMA_HISR_DMEIF4)); 1983:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1984:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1985:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1986:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 5 direct mode error flag. 1987:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HISR DMEIF0 LL_DMA_IsActiveFlag_DME5 1988:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 1989:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). 1990:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1991:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME5(DMA_TypeDef *DMAx) 1992:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1993:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->HISR ,DMA_HISR_DMEIF5)==(DMA_HISR_DMEIF5)); 1994:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1995:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1996:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1997:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 6 direct mode error flag. 1998:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HISR DMEIF6 LL_DMA_IsActiveFlag_DME6 1999:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 2000:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). 2001:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 2002:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME6(DMA_TypeDef *DMAx) 2003:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 2004:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->HISR ,DMA_HISR_DMEIF6)==(DMA_HISR_DMEIF6)); 2005:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 2006:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 2007:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 2008:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 7 direct mode error flag. 2009:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HISR DMEIF7 LL_DMA_IsActiveFlag_DME7 2010:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 2011:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). 2012:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 2013:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME7(DMA_TypeDef *DMAx) 2014:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 2015:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->HISR ,DMA_HISR_DMEIF7)==(DMA_HISR_DMEIF7)); 2016:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 2017:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 2018:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 2019:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 0 FIFO error flag. 2020:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LISR FEIF0 LL_DMA_IsActiveFlag_FE0 2021:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 2022:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). 2023:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 2024:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE0(DMA_TypeDef *DMAx) 2025:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 2026:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->LISR ,DMA_LISR_FEIF0)==(DMA_LISR_FEIF0)); 2027:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 2028:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 2029:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** ARM GAS /tmp/ccqopZd5.s page 329 2030:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 1 FIFO error flag. 2031:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LISR FEIF1 LL_DMA_IsActiveFlag_FE1 2032:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 2033:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). 2034:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 2035:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE1(DMA_TypeDef *DMAx) 2036:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 2037:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->LISR ,DMA_LISR_FEIF1)==(DMA_LISR_FEIF1)); 2038:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 2039:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 2040:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 2041:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 2 FIFO error flag. 2042:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LISR FEIF2 LL_DMA_IsActiveFlag_FE2 2043:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 2044:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). 2045:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 2046:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE2(DMA_TypeDef *DMAx) 2047:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 2048:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->LISR ,DMA_LISR_FEIF2)==(DMA_LISR_FEIF2)); 2049:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 2050:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 2051:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 2052:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 3 FIFO error flag. 2053:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LISR FEIF3 LL_DMA_IsActiveFlag_FE3 2054:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 2055:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). 2056:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 2057:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE3(DMA_TypeDef *DMAx) 2058:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 2059:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->LISR ,DMA_LISR_FEIF3)==(DMA_LISR_FEIF3)); 2060:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 2061:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 2062:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 2063:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 4 FIFO error flag. 2064:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HISR FEIF4 LL_DMA_IsActiveFlag_FE4 2065:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 2066:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). 2067:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 2068:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE4(DMA_TypeDef *DMAx) 2069:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 2070:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->HISR ,DMA_HISR_FEIF4)==(DMA_HISR_FEIF4)); 2071:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 2072:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 2073:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 2074:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 5 FIFO error flag. 2075:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HISR FEIF0 LL_DMA_IsActiveFlag_FE5 2076:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 2077:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). 2078:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 2079:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE5(DMA_TypeDef *DMAx) 2080:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 2081:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->HISR ,DMA_HISR_FEIF5)==(DMA_HISR_FEIF5)); 2082:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 2083:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 2084:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 2085:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 6 FIFO error flag. 2086:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HISR FEIF6 LL_DMA_IsActiveFlag_FE6 ARM GAS /tmp/ccqopZd5.s page 330 2087:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 2088:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). 2089:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 2090:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE6(DMA_TypeDef *DMAx) 2091:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 2092:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->HISR ,DMA_HISR_FEIF6)==(DMA_HISR_FEIF6)); 2093:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 2094:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 2095:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 2096:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 7 FIFO error flag. 2097:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HISR FEIF7 LL_DMA_IsActiveFlag_FE7 2098:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 2099:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). 2100:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 2101:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE7(DMA_TypeDef *DMAx) 2102:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 2103:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->HISR ,DMA_HISR_FEIF7)==(DMA_HISR_FEIF7)); 2104:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 2105:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 2106:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 2107:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Clear Stream 0 half transfer flag. 2108:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LIFCR CHTIF0 LL_DMA_ClearFlag_HT0 2109:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 2110:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 2111:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 2112:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_HT0(DMA_TypeDef *DMAx) 2113:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 2114:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CHTIF0); 2115:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 2116:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 2117:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 2118:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Clear Stream 1 half transfer flag. 2119:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LIFCR CHTIF1 LL_DMA_ClearFlag_HT1 2120:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 2121:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 2122:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 2123:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_HT1(DMA_TypeDef *DMAx) 2124:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 2125:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CHTIF1); 2126:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 2127:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 2128:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 2129:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Clear Stream 2 half transfer flag. 2130:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LIFCR CHTIF2 LL_DMA_ClearFlag_HT2 2131:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 2132:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 2133:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 2134:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_HT2(DMA_TypeDef *DMAx) 2135:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 2136:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CHTIF2); 2137:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 2138:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 2139:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 2140:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Clear Stream 3 half transfer flag. 2141:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LIFCR CHTIF3 LL_DMA_ClearFlag_HT3 2142:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 2143:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None ARM GAS /tmp/ccqopZd5.s page 331 2144:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 2145:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_HT3(DMA_TypeDef *DMAx) 2146:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 2147:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CHTIF3); 2148:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 2149:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 2150:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 2151:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Clear Stream 4 half transfer flag. 2152:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HIFCR CHTIF4 LL_DMA_ClearFlag_HT4 2153:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 2154:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 2155:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 2156:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_HT4(DMA_TypeDef *DMAx) 2157:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 2158:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CHTIF4); 2159:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 2160:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 2161:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 2162:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Clear Stream 5 half transfer flag. 2163:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HIFCR CHTIF5 LL_DMA_ClearFlag_HT5 2164:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 2165:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 2166:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 2167:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_HT5(DMA_TypeDef *DMAx) 2168:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 2169:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CHTIF5); 2170:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 2171:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 2172:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 2173:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Clear Stream 6 half transfer flag. 2174:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HIFCR CHTIF6 LL_DMA_ClearFlag_HT6 2175:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 2176:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 2177:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 2178:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_HT6(DMA_TypeDef *DMAx) 2179:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 2180:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CHTIF6); 2181:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 2182:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 2183:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 2184:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Clear Stream 7 half transfer flag. 2185:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HIFCR CHTIF7 LL_DMA_ClearFlag_HT7 2186:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 2187:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 2188:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 2189:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_HT7(DMA_TypeDef *DMAx) 2190:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 2191:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CHTIF7); 2192:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 2193:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 2194:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 2195:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Clear Stream 0 transfer complete flag. 2196:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LIFCR CTCIF0 LL_DMA_ClearFlag_TC0 2197:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 2198:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 2199:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 2200:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_TC0(DMA_TypeDef *DMAx) ARM GAS /tmp/ccqopZd5.s page 332 2201:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 2202:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTCIF0); 2203:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 2204:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 2205:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 2206:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Clear Stream 1 transfer complete flag. 2207:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LIFCR CTCIF1 LL_DMA_ClearFlag_TC1 2208:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 2209:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 2210:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 2211:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_TC1(DMA_TypeDef *DMAx) 2212:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 2213:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTCIF1); 2214:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 2215:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 2216:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 2217:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Clear Stream 2 transfer complete flag. 2218:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LIFCR CTCIF2 LL_DMA_ClearFlag_TC2 2219:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 2220:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 2221:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 2222:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_TC2(DMA_TypeDef *DMAx) 2223:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 2224:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTCIF2); 2225:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 2226:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 2227:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 2228:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Clear Stream 3 transfer complete flag. 2229:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LIFCR CTCIF3 LL_DMA_ClearFlag_TC3 2230:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 2231:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 2232:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 2233:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_TC3(DMA_TypeDef *DMAx) 2234:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 2235:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTCIF3); 2236:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 2237:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 2238:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 2239:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Clear Stream 4 transfer complete flag. 2240:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HIFCR CTCIF4 LL_DMA_ClearFlag_TC4 2241:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 2242:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 2243:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 2244:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_TC4(DMA_TypeDef *DMAx) 2245:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 2246:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTCIF4); 2247:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 2248:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 2249:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 2250:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Clear Stream 5 transfer complete flag. 2251:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HIFCR CTCIF5 LL_DMA_ClearFlag_TC5 2252:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 2253:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 2254:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 2255:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_TC5(DMA_TypeDef *DMAx) 2256:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 2257:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTCIF5); ARM GAS /tmp/ccqopZd5.s page 333 2258:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 2259:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 2260:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 2261:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Clear Stream 6 transfer complete flag. 2262:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HIFCR CTCIF6 LL_DMA_ClearFlag_TC6 2263:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 2264:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 2265:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 2266:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_TC6(DMA_TypeDef *DMAx) 2267:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 2268:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTCIF6); 2269:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 2270:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 2271:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 2272:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Clear Stream 7 transfer complete flag. 2273:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HIFCR CTCIF7 LL_DMA_ClearFlag_TC7 2274:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 2275:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 2276:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 2277:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_TC7(DMA_TypeDef *DMAx) 3970 .loc 6 2277 22 view .LVU1309 3971 .LBB446: 2278:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 2279:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTCIF7); 3972 .loc 6 2279 3 view .LVU1310 3973 00dc 4FF00062 mov r2, #134217728 3974 00e0 DA60 str r2, [r3, #12] 3975 .LVL280: 3976 .loc 6 2279 3 is_stmt 0 view .LVU1311 3977 .LBE446: 3978 .LBE445: 1809:Src/main.c **** LL_USART_EnableDMAReq_TX(USART1); 3979 .loc 2 1809 3 is_stmt 1 view .LVU1312 3980 .LBB447: 3981 .LBI447: 2280:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 2281:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 2282:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 2283:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Clear Stream 0 transfer error flag. 2284:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LIFCR CTEIF0 LL_DMA_ClearFlag_TE0 2285:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 2286:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 2287:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 2288:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_TE0(DMA_TypeDef *DMAx) 2289:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 2290:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTEIF0); 2291:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 2292:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 2293:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 2294:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Clear Stream 1 transfer error flag. 2295:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LIFCR CTEIF1 LL_DMA_ClearFlag_TE1 2296:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 2297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 2298:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 2299:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_TE1(DMA_TypeDef *DMAx) 2300:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 2301:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTEIF1); ARM GAS /tmp/ccqopZd5.s page 334 2302:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 2303:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 2304:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 2305:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Clear Stream 2 transfer error flag. 2306:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LIFCR CTEIF2 LL_DMA_ClearFlag_TE2 2307:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 2308:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 2309:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 2310:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_TE2(DMA_TypeDef *DMAx) 2311:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 2312:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTEIF2); 2313:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 2314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 2315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 2316:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Clear Stream 3 transfer error flag. 2317:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LIFCR CTEIF3 LL_DMA_ClearFlag_TE3 2318:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 2319:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 2320:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 2321:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_TE3(DMA_TypeDef *DMAx) 2322:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 2323:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTEIF3); 2324:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 2325:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 2326:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 2327:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Clear Stream 4 transfer error flag. 2328:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HIFCR CTEIF4 LL_DMA_ClearFlag_TE4 2329:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 2330:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 2331:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 2332:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_TE4(DMA_TypeDef *DMAx) 2333:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 2334:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTEIF4); 2335:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 2336:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 2337:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 2338:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Clear Stream 5 transfer error flag. 2339:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HIFCR CTEIF5 LL_DMA_ClearFlag_TE5 2340:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 2341:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 2342:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 2343:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_TE5(DMA_TypeDef *DMAx) 2344:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 2345:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTEIF5); 2346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 2347:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 2348:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 2349:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Clear Stream 6 transfer error flag. 2350:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HIFCR CTEIF6 LL_DMA_ClearFlag_TE6 2351:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 2352:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 2353:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 2354:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_TE6(DMA_TypeDef *DMAx) 2355:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 2356:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTEIF6); 2357:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 2358:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** ARM GAS /tmp/ccqopZd5.s page 335 2359:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 2360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Clear Stream 7 transfer error flag. 2361:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HIFCR CTEIF7 LL_DMA_ClearFlag_TE7 2362:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 2363:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 2364:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 2365:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_TE7(DMA_TypeDef *DMAx) 3982 .loc 6 2365 22 view .LVU1313 3983 .LBB448: 2366:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 2367:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTEIF7); 3984 .loc 6 2367 3 view .LVU1314 3985 00e2 4FF00072 mov r2, #33554432 3986 00e6 DA60 str r2, [r3, #12] 3987 .LVL281: 3988 .L133: 3989 .loc 6 2367 3 is_stmt 0 view .LVU1315 3990 .LBE448: 3991 .LBE447: 3992 .file 7 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h" 1:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ****************************************************************************** 3:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @file stm32f7xx_ll_usart.h 4:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @author MCD Application Team 5:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Header file of USART LL module. 6:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ****************************************************************************** 7:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @attention 8:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * 9:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Copyright (c) 2017 STMicroelectronics. 10:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * All rights reserved. 11:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * 12:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * This software is licensed under terms that can be found in the LICENSE file 13:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * in the root directory of this software component. 14:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * If no LICENSE file comes with this software, it is provided AS-IS. 15:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * 16:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ****************************************************************************** 17:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 18:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 19:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* Define to prevent recursive inclusion -------------------------------------*/ 20:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #ifndef STM32F7xx_LL_USART_H 21:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define STM32F7xx_LL_USART_H 22:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 23:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #ifdef __cplusplus 24:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** extern "C" { 25:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif 26:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 27:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* Includes ------------------------------------------------------------------*/ 28:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #include "stm32f7xx.h" 29:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 30:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @addtogroup STM32F7xx_LL_Driver 31:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ 32:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 33:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 34:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART1) || defined(USART2) || defined(USART3) || defined(USART6) \ 35:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** || defined(UART4) || defined(UART5) || defined(UART7) || defined(UART8) 36:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 37:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL USART ARM GAS /tmp/ccqopZd5.s page 336 38:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ 39:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 40:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 41:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* Private types -------------------------------------------------------------*/ 42:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* Private variables ---------------------------------------------------------*/ 43:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 44:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* Private constants ---------------------------------------------------------*/ 45:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_Private_Constants USART Private Constants 46:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ 47:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 48:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 49:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} 50:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 51:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* Private macros ------------------------------------------------------------*/ 52:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USE_FULL_LL_DRIVER) 53:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_Private_Macros USART Private Macros 54:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ 55:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 56:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 57:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} 58:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 59:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /*USE_FULL_LL_DRIVER*/ 60:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 61:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* Exported types ------------------------------------------------------------*/ 62:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USE_FULL_LL_DRIVER) 63:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_ES_INIT USART Exported Init structures 64:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ 65:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 66:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 67:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 68:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief LL USART Init Structure definition 69:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 70:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** typedef struct 71:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 72:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 73:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** uint32_t BaudRate; /*!< This field defines expected Usart communication baud rat 74:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 75:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** This feature can be modified afterwards using unitary 76:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** function @ref LL_USART_SetBaudRate().*/ 77:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 78:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** uint32_t DataWidth; /*!< Specifies the number of data bits transmitted or receive 79:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** This parameter can be a value of @ref USART_LL_EC_DATAWI 80:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 81:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** This feature can be modified afterwards using unitary 82:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** function @ref LL_USART_SetDataWidth().*/ 83:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 84:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** uint32_t StopBits; /*!< Specifies the number of stop bits transmitted. 85:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** This parameter can be a value of @ref USART_LL_EC_STOPBI 86:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 87:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** This feature can be modified afterwards using unitary 88:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** function @ref LL_USART_SetStopBitsLength().*/ 89:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 90:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** uint32_t Parity; /*!< Specifies the parity mode. 91:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** This parameter can be a value of @ref USART_LL_EC_PARITY 92:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 93:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** This feature can be modified afterwards using unitary 94:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** function @ref LL_USART_SetParity().*/ ARM GAS /tmp/ccqopZd5.s page 337 95:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 96:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** uint32_t TransferDirection; /*!< Specifies whether the Receive and/or Transmit mode is en 97:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** This parameter can be a value of @ref USART_LL_EC_DIRECT 98:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 99:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** This feature can be modified afterwards using unitary 100:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** function @ref LL_USART_SetTransferDirection().*/ 101:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 102:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** uint32_t HardwareFlowControl; /*!< Specifies whether the hardware flow control mode is enab 103:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** This parameter can be a value of @ref USART_LL_EC_HWCONT 104:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 105:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** This feature can be modified afterwards using unitary 106:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** function @ref LL_USART_SetHWFlowCtrl().*/ 107:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 108:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** uint32_t OverSampling; /*!< Specifies whether USART oversampling mode is 16 or 8. 109:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** This parameter can be a value of @ref USART_LL_EC_OVERSA 110:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 111:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** This feature can be modified afterwards using unitary 112:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** function @ref LL_USART_SetOverSampling().*/ 113:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 114:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } LL_USART_InitTypeDef; 115:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 116:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 117:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief LL USART Clock Init Structure definition 118:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 119:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** typedef struct 120:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 121:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** uint32_t ClockOutput; /*!< Specifies whether the USART clock is enabled or disabled 122:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** This parameter can be a value of @ref USART_LL_EC_CLOCK. 123:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 124:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** USART HW configuration can be modified afterwards using 125:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** @ref LL_USART_EnableSCLKOutput() or @ref LL_USART_Disabl 126:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** For more details, refer to description of this function. 127:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 128:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** uint32_t ClockPolarity; /*!< Specifies the steady state of the serial clock. 129:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** This parameter can be a value of @ref USART_LL_EC_POLARI 130:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 131:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** USART HW configuration can be modified afterwards using 132:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** functions @ref LL_USART_SetClockPolarity(). 133:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** For more details, refer to description of this function. 134:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 135:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** uint32_t ClockPhase; /*!< Specifies the clock transition on which the bit capture 136:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** This parameter can be a value of @ref USART_LL_EC_PHASE. 137:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 138:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** USART HW configuration can be modified afterwards using 139:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** functions @ref LL_USART_SetClockPhase(). 140:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** For more details, refer to description of this function. 141:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 142:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** uint32_t LastBitClockPulse; /*!< Specifies whether the clock pulse corresponding to the l 143:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** data bit (MSB) has to be output on the SCLK pin in synch 144:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** This parameter can be a value of @ref USART_LL_EC_LASTCL 145:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 146:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** USART HW configuration can be modified afterwards using 147:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** functions @ref LL_USART_SetLastClkPulseOutput(). 148:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** For more details, refer to description of this function. 149:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 150:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } LL_USART_ClockInitTypeDef; 151:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ARM GAS /tmp/ccqopZd5.s page 338 152:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 153:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} 154:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 155:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USE_FULL_LL_DRIVER */ 156:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 157:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* Exported constants --------------------------------------------------------*/ 158:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_Exported_Constants USART Exported Constants 159:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ 160:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 161:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 162:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_CLEAR_FLAG Clear Flags Defines 163:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Flags defines which can be used with LL_USART_WriteReg function 164:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ 165:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 166:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ICR_PECF USART_ICR_PECF /*!< Parity error cle 167:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ICR_FECF USART_ICR_FECF /*!< Framing error cl 168:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ICR_NCF USART_ICR_NCF /*!< Noise error dete 169:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ICR_ORECF USART_ICR_ORECF /*!< Overrun error cl 170:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ICR_IDLECF USART_ICR_IDLECF /*!< Idle line detect 171:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ICR_TCCF USART_ICR_TCCF /*!< Transmission com 172:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_TCBGT_SUPPORT) 173:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ICR_TCBGTCF USART_ICR_TCBGTCF /*!< Transmission com 174:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_TCBGT_SUPPORT */ 175:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ICR_LBDCF USART_ICR_LBDCF /*!< LIN break detect 176:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ICR_CTSCF USART_ICR_CTSCF /*!< CTS clear flag * 177:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ICR_RTOCF USART_ICR_RTOCF /*!< Receiver timeout 178:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ICR_EOBCF USART_ICR_EOBCF /*!< End of block cle 179:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ICR_CMCF USART_ICR_CMCF /*!< Character match 180:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_CR1_UESM) 181:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_CR3_WUFIE) 182:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ICR_WUCF USART_ICR_WUCF /*!< Wakeup from Stop 183:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_CR3_WUFIE */ 184:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_CR1_UESM */ 185:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 186:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} 187:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 188:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 189:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_GET_FLAG Get Flags Defines 190:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Flags defines which can be used with LL_USART_ReadReg function 191:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ 192:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 193:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_PE USART_ISR_PE /*!< Parity error fla 194:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_FE USART_ISR_FE /*!< Framing error fl 195:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_NE USART_ISR_NE /*!< Noise detected f 196:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_ORE USART_ISR_ORE /*!< Overrun error fl 197:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_IDLE USART_ISR_IDLE /*!< Idle line detect 198:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_RXNE USART_ISR_RXNE /*!< Read data regist 199:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_TC USART_ISR_TC /*!< Transmission com 200:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_TXE USART_ISR_TXE /*!< Transmit data re 201:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_LBDF USART_ISR_LBDF /*!< LIN break detect 202:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_CTSIF USART_ISR_CTSIF /*!< CTS interrupt fl 203:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_CTS USART_ISR_CTS /*!< CTS flag */ 204:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_RTOF USART_ISR_RTOF /*!< Receiver timeout 205:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_EOBF USART_ISR_EOBF /*!< End of block fla 206:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_ABRE USART_ISR_ABRE /*!< Auto baud rate e 207:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_ABRF USART_ISR_ABRF /*!< Auto baud rate f 208:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_BUSY USART_ISR_BUSY /*!< Busy flag */ ARM GAS /tmp/ccqopZd5.s page 339 209:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_CMF USART_ISR_CMF /*!< Character match 210:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_SBKF USART_ISR_SBKF /*!< Send break flag 211:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_RWU USART_ISR_RWU /*!< Receiver wakeup 212:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_CR1_UESM) 213:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_CR3_WUFIE) 214:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_WUF USART_ISR_WUF /*!< Wakeup from Stop 215:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_CR3_WUFIE */ 216:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_CR1_UESM */ 217:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_TEACK USART_ISR_TEACK /*!< Transmit enable 218:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_ISR_REACK) 219:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_REACK USART_ISR_REACK /*!< Receive enable a 220:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_ISR_REACK */ 221:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_TCBGT_SUPPORT) 222:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_TCBGT USART_ISR_TCBGT /*!< Transmission com 223:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_TCBGT_SUPPORT */ 224:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 225:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} 226:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 227:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 228:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_IT IT Defines 229:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief IT defines which can be used with LL_USART_ReadReg and LL_USART_WriteReg functions 230:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ 231:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 232:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_CR1_IDLEIE USART_CR1_IDLEIE /*!< IDLE interrupt e 233:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_CR1_RXNEIE USART_CR1_RXNEIE /*!< Read data regist 234:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_CR1_TCIE USART_CR1_TCIE /*!< Transmission com 235:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_CR1_TXEIE USART_CR1_TXEIE /*!< Transmit data re 236:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_CR1_PEIE USART_CR1_PEIE /*!< Parity error */ 237:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_CR1_CMIE USART_CR1_CMIE /*!< Character match 238:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_CR1_RTOIE USART_CR1_RTOIE /*!< Receiver timeout 239:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_CR1_EOBIE USART_CR1_EOBIE /*!< End of Block int 240:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_CR2_LBDIE USART_CR2_LBDIE /*!< LIN break detect 241:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_CR3_EIE USART_CR3_EIE /*!< Error interrupt 242:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_CR3_CTSIE USART_CR3_CTSIE /*!< CTS interrupt en 243:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_CR1_UESM) 244:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_CR3_WUFIE) 245:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_CR3_WUFIE USART_CR3_WUFIE /*!< Wakeup from Stop 246:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_CR3_WUFIE */ 247:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_CR1_UESM */ 248:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_TCBGT_SUPPORT) 249:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_CR3_TCBGTIE USART_CR3_TCBGTIE /*!< Transmission com 250:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_TCBGT_SUPPORT */ 251:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 252:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} 253:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 254:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 255:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_DIRECTION Communication Direction 256:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ 257:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 258:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_DIRECTION_NONE 0x00000000U /*!< Transmitter 259:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_DIRECTION_RX USART_CR1_RE /*!< Transmitter 260:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_DIRECTION_TX USART_CR1_TE /*!< Transmitter 261:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_DIRECTION_TX_RX (USART_CR1_TE |USART_CR1_RE) /*!< Transmitter 262:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 263:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} 264:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 265:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ARM GAS /tmp/ccqopZd5.s page 340 266:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_PARITY Parity Control 267:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ 268:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 269:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_PARITY_NONE 0x00000000U /*!< Parity co 270:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_PARITY_EVEN USART_CR1_PCE /*!< Parity co 271:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS) /*!< Parity co 272:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 273:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} 274:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 275:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 276:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_WAKEUP Wakeup 277:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ 278:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 279:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_WAKEUP_IDLELINE 0x00000000U /*!< USART wake up from Mute 280:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_WAKEUP_ADDRESSMARK USART_CR1_WAKE /*!< USART wake up from Mute 281:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 282:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} 283:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 284:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 285:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_DATAWIDTH Datawidth 286:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ 287:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 288:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_DATAWIDTH_7B USART_CR1_M1 /*!< 7 bits word length : S 289:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_DATAWIDTH_8B 0x00000000U /*!< 8 bits word length : S 290:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_DATAWIDTH_9B USART_CR1_M0 /*!< 9 bits word length : S 291:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 292:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} 293:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 294:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 295:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_OVERSAMPLING Oversampling 296:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ 297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 298:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_OVERSAMPLING_16 0x00000000U /*!< Oversampling by 16 */ 299:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_OVERSAMPLING_8 USART_CR1_OVER8 /*!< Oversampling by 8 */ 300:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 301:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} 302:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 303:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 304:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USE_FULL_LL_DRIVER) 305:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_CLOCK Clock Signal 306:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ 307:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 308:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 309:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_CLOCK_DISABLE 0x00000000U /*!< Clock signal not provid 310:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_CLOCK_ENABLE USART_CR2_CLKEN /*!< Clock signal provided * 311:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 312:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} 313:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /*USE_FULL_LL_DRIVER*/ 315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 316:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_LASTCLKPULSE Last Clock Pulse 317:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ 318:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 319:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_LASTCLKPULSE_NO_OUTPUT 0x00000000U /*!< The clock pulse of the l 320:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_LASTCLKPULSE_OUTPUT USART_CR2_LBCL /*!< The clock pulse of the l 321:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 322:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} ARM GAS /tmp/ccqopZd5.s page 341 323:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 324:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 325:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_PHASE Clock Phase 326:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ 327:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 328:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_PHASE_1EDGE 0x00000000U /*!< The first clock transiti 329:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_PHASE_2EDGE USART_CR2_CPHA /*!< The second clock transit 330:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 331:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} 332:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 333:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 334:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_POLARITY Clock Polarity 335:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ 336:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 337:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_POLARITY_LOW 0x00000000U /*!< Steady low value on SCLK 338:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_POLARITY_HIGH USART_CR2_CPOL /*!< Steady high value on SCL 339:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 340:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} 341:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 342:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 343:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_STOPBITS Stop Bits 344:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ 345:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_STOPBITS_0_5 USART_CR2_STOP_0 /*!< 0.5 347:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_STOPBITS_1 0x00000000U /*!< 1 s 348:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_STOPBITS_1_5 (USART_CR2_STOP_0 | USART_CR2_STOP_1) /*!< 1.5 349:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_STOPBITS_2 USART_CR2_STOP_1 /*!< 2 s 350:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 351:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} 352:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 353:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 354:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_TXRX TX RX Pins Swap 355:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ 356:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 357:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_TXRX_STANDARD 0x00000000U /*!< TX/RX pins are used as d 358:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_TXRX_SWAPPED (USART_CR2_SWAP) /*!< TX and RX pins functions 359:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} 361:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 362:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 363:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_RXPIN_LEVEL RX Pin Active Level Inversion 364:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ 365:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 366:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_RXPIN_LEVEL_STANDARD 0x00000000U /*!< RX pin signal works usin 367:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_RXPIN_LEVEL_INVERTED (USART_CR2_RXINV) /*!< RX pin signal values are 368:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 369:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} 370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 371:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_TXPIN_LEVEL TX Pin Active Level Inversion 373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ 374:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 375:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_TXPIN_LEVEL_STANDARD 0x00000000U /*!< TX pin signal works usin 376:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_TXPIN_LEVEL_INVERTED (USART_CR2_TXINV) /*!< TX pin signal values are 377:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 378:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} 379:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ ARM GAS /tmp/ccqopZd5.s page 342 380:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 381:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_BINARY_LOGIC Binary Data Inversion 382:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ 383:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 384:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_BINARY_LOGIC_POSITIVE 0x00000000U /*!< Logical data from the da 385:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_BINARY_LOGIC_NEGATIVE USART_CR2_DATAINV /*!< Logical data from the da 386:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 387:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} 388:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 389:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 390:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_BITORDER Bit Order 391:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ 392:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 393:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_BITORDER_LSBFIRST 0x00000000U /*!< data is transmitted/rece 394:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_BITORDER_MSBFIRST USART_CR2_MSBFIRST /*!< data is transmitted/rece 395:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 396:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} 397:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 398:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 399:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_AUTOBAUD_DETECT_ON Autobaud Detection 400:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ 401:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 402:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_AUTOBAUD_DETECT_ON_STARTBIT 0x00000000U /*!< Me 403:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_AUTOBAUD_DETECT_ON_FALLINGEDGE USART_CR2_ABRMODE_0 /*!< Fa 404:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME USART_CR2_ABRMODE_1 /*!< 0x 405:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_AUTOBAUD_DETECT_ON_55_FRAME (USART_CR2_ABRMODE_1 | USART_CR2_ABRMODE_0) /*!< 0x 406:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 407:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} 408:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 409:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 410:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_ADDRESS_DETECT Address Length Detection 411:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ 412:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 413:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ADDRESS_DETECT_4B 0x00000000U /*!< 4-bit address detection 414:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ADDRESS_DETECT_7B USART_CR2_ADDM7 /*!< 7-bit address detection 415:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 416:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} 417:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 418:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 419:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_HWCONTROL Hardware Control 420:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ 421:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 422:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_HWCONTROL_NONE 0x00000000U /*!< CTS and R 423:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_HWCONTROL_RTS USART_CR3_RTSE /*!< RTS outpu 424:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_HWCONTROL_CTS USART_CR3_CTSE /*!< CTS mode 425:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_HWCONTROL_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE) /*!< CTS and R 426:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 427:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} 428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 429:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 430:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_CR1_UESM) 431:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_CR3_WUS) 432:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_WAKEUP_ON Wakeup Activation 433:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ 434:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 435:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_WAKEUP_ON_ADDRESS 0x00000000U /*!< Wake u 436:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_WAKEUP_ON_STARTBIT USART_CR3_WUS_1 /*!< Wake u ARM GAS /tmp/ccqopZd5.s page 343 437:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_WAKEUP_ON_RXNE (USART_CR3_WUS_0 | USART_CR3_WUS_1) /*!< Wake u 438:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 439:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} 440:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 441:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 442:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_CR3_WUS */ 443:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_CR1_UESM */ 444:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_IRDA_POWER IrDA Power 445:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ 446:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 447:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_IRDA_POWER_NORMAL 0x00000000U /*!< IrDA normal power mode * 448:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_IRDA_POWER_LOW USART_CR3_IRLP /*!< IrDA low power mode */ 449:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 450:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} 451:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 452:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 453:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_LINBREAK_DETECT LIN Break Detection Length 454:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ 455:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 456:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_LINBREAK_DETECT_10B 0x00000000U /*!< 10-bit break detection m 457:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_LINBREAK_DETECT_11B USART_CR2_LBDL /*!< 11-bit break detection m 458:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 459:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} 460:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 461:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 462:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_DE_POLARITY Driver Enable Polarity 463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ 464:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 465:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_DE_POLARITY_HIGH 0x00000000U /*!< DE signal is active high 466:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_DE_POLARITY_LOW USART_CR3_DEP /*!< DE signal is active low 467:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 468:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} 469:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 470:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 471:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_DMA_REG_DATA DMA Register Data 472:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ 473:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 474:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_DMA_REG_DATA_TRANSMIT 0x00000000U /*!< Get address of data regis 475:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_DMA_REG_DATA_RECEIVE 0x00000001U /*!< Get address of data regis 476:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 477:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} 478:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 479:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 480:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 481:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} 482:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 483:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 484:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* Exported macro ------------------------------------------------------------*/ 485:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_Exported_Macros USART Exported Macros 486:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ 487:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 488:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 489:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EM_WRITE_READ Common Write and read registers Macros 490:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ 491:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 492:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 493:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** ARM GAS /tmp/ccqopZd5.s page 344 494:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Write a value in USART register 495:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param __INSTANCE__ USART Instance 496:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param __REG__ Register to be written 497:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param __VALUE__ Value to be written in the register 498:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 499:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 500:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VAL 501:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 502:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 503:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Read a value in USART register 504:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param __INSTANCE__ USART Instance 505:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param __REG__ Register to be read 506:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Register value 507:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 508:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) 509:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 510:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} 511:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 512:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 513:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EM_Exported_Macros_Helper Exported_Macros_Helper 514:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ 515:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 516:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 517:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 518:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Compute USARTDIV value according to Peripheral Clock and 519:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * expected Baud Rate in 8 bits sampling mode (32 bits value of USARTDIV is returned) 520:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param __PERIPHCLK__ Peripheral Clock frequency used for USART instance 521:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param __BAUDRATE__ Baud rate value to achieve 522:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval USARTDIV value to be used for BRR register filling in OverSampling_8 case 523:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 524:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define __LL_USART_DIV_SAMPLING8(__PERIPHCLK__, __BAUDRATE__) ((((__PERIPHCLK__)*2U)\ 525:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + ((__BAUDRATE__)/2U))/(__BAUDRATE_ 526:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 527:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 528:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Compute USARTDIV value according to Peripheral Clock and 529:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * expected Baud Rate in 16 bits sampling mode (32 bits value of USARTDIV is returned) 530:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param __PERIPHCLK__ Peripheral Clock frequency used for USART instance 531:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param __BAUDRATE__ Baud rate value to achieve 532:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval USARTDIV value to be used for BRR register filling in OverSampling_16 case 533:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 534:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define __LL_USART_DIV_SAMPLING16(__PERIPHCLK__, __BAUDRATE__) (((__PERIPHCLK__) + ((__BAUDRATE__)/ 535:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 536:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 537:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} 538:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 539:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 540:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 541:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} 542:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 543:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 544:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* Exported functions --------------------------------------------------------*/ 545:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 546:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_Exported_Functions USART Exported Functions 547:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ 548:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 549:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 550:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EF_Configuration Configuration functions ARM GAS /tmp/ccqopZd5.s page 345 551:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ 552:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 553:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 554:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 555:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief USART Enable 556:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 UE LL_USART_Enable 557:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 558:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 559:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 560:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_Enable(USART_TypeDef *USARTx) 561:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 562:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** SET_BIT(USARTx->CR1, USART_CR1_UE); 563:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 564:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 565:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 566:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief USART Disable (all USART prescalers and outputs are disabled) 567:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note When USART is disabled, USART prescalers and outputs are stopped immediately, 568:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * and current operations are discarded. The configuration of the USART is kept, but all t 569:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * flags, in the USARTx_ISR are set to their default values. 570:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 UE LL_USART_Disable 571:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 572:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 573:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 574:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_Disable(USART_TypeDef *USARTx) 575:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 576:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** CLEAR_BIT(USARTx->CR1, USART_CR1_UE); 577:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 578:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 579:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 580:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Indicate if USART is enabled 581:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 UE LL_USART_IsEnabled 582:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 583:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). 584:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 585:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabled(const USART_TypeDef *USARTx) 586:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 587:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->CR1, USART_CR1_UE) == (USART_CR1_UE)) ? 1UL : 0UL); 588:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 589:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 590:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_CR1_UESM) 591:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 592:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief USART enabled in STOP Mode. 593:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note When this function is enabled, USART is able to wake up the MCU from Stop mode, provide 594:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * USART clock selection is HSI or LSE in RCC. 595:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not 596:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Wake-up from Stop mode feature is supported by the USARTx instance. 597:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 UESM LL_USART_EnableInStopMode 598:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 599:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 600:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 601:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableInStopMode(USART_TypeDef *USARTx) 602:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 603:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_UESM); 604:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 605:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 606:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 607:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief USART disabled in STOP Mode. ARM GAS /tmp/ccqopZd5.s page 346 608:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note When this function is disabled, USART is not able to wake up the MCU from Stop mode 609:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not 610:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Wake-up from Stop mode feature is supported by the USARTx instance. 611:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 UESM LL_USART_DisableInStopMode 612:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 613:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 614:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 615:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableInStopMode(USART_TypeDef *USARTx) 616:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 617:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_UESM); 618:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 619:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 620:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 621:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Indicate if USART is enabled in STOP Mode (able to wake up MCU from Stop mode or not) 622:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not 623:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Wake-up from Stop mode feature is supported by the USARTx instance. 624:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 UESM LL_USART_IsEnabledInStopMode 625:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 626:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). 627:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 628:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledInStopMode(const USART_TypeDef *USARTx) 629:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 630:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->CR1, USART_CR1_UESM) == (USART_CR1_UESM)) ? 1UL : 0UL); 631:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 632:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 633:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_CR3_UCESM) 634:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 635:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief USART Clock enabled in STOP Mode 636:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note When this function is called, USART Clock is enabled while in STOP mode 637:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 UCESM LL_USART_EnableClockInStopMode 638:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 639:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 640:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 641:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableClockInStopMode(USART_TypeDef *USARTx) 642:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 643:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_UCESM); 644:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 645:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 646:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 647:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief USART clock disabled in STOP Mode 648:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note When this function is called, USART Clock is disabled while in STOP mode 649:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 UCESM LL_USART_DisableClockInStopMode 650:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 651:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 652:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 653:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableClockInStopMode(USART_TypeDef *USARTx) 654:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 655:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_UCESM); 656:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 657:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 658:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 659:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Indicate if USART clock is enabled in STOP Mode 660:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 UCESM LL_USART_IsClockEnabledInStopMode 661:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 662:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). 663:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 664:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsClockEnabledInStopMode(const USART_TypeDef *USARTx) ARM GAS /tmp/ccqopZd5.s page 347 665:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 666:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return (READ_BIT(USARTx->CR3, USART_CR3_UCESM) == (USART_CR3_UCESM)); 667:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 668:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 669:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_CR3_UCESM */ 670:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_CR1_UESM*/ 671:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 672:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Receiver Enable (Receiver is enabled and begins searching for a start bit) 673:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 RE LL_USART_EnableDirectionRx 674:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 675:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 676:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 677:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableDirectionRx(USART_TypeDef *USARTx) 678:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 679:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_RE); 680:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 681:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 682:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 683:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Receiver Disable 684:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 RE LL_USART_DisableDirectionRx 685:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 686:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 687:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 688:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableDirectionRx(USART_TypeDef *USARTx) 689:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 690:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_RE); 691:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 692:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 693:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 694:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Transmitter Enable 695:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 TE LL_USART_EnableDirectionTx 696:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 697:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 698:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 699:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableDirectionTx(USART_TypeDef *USARTx) 700:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 701:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_TE); 702:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 703:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 704:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 705:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Transmitter Disable 706:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 TE LL_USART_DisableDirectionTx 707:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 708:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 709:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 710:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableDirectionTx(USART_TypeDef *USARTx) 711:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 712:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_TE); 713:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 714:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 715:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 716:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Configure simultaneously enabled/disabled states 717:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * of Transmitter and Receiver 718:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 RE LL_USART_SetTransferDirection\n 719:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR1 TE LL_USART_SetTransferDirection 720:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 721:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param TransferDirection This parameter can be one of the following values: ARM GAS /tmp/ccqopZd5.s page 348 722:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_DIRECTION_NONE 723:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_DIRECTION_RX 724:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_DIRECTION_TX 725:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_DIRECTION_TX_RX 726:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 727:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 728:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetTransferDirection(USART_TypeDef *USARTx, uint32_t TransferDirectio 729:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 730:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_MODIFY_REG(USARTx->CR1, USART_CR1_RE | USART_CR1_TE, TransferDirection); 731:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 732:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 733:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 734:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Return enabled/disabled states of Transmitter and Receiver 735:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 RE LL_USART_GetTransferDirection\n 736:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR1 TE LL_USART_GetTransferDirection 737:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 738:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Returned value can be one of the following values: 739:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_DIRECTION_NONE 740:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_DIRECTION_RX 741:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_DIRECTION_TX 742:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_DIRECTION_TX_RX 743:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 744:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetTransferDirection(const USART_TypeDef *USARTx) 745:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 746:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_RE | USART_CR1_TE)); 747:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 748:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 749:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 750:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Configure Parity (enabled/disabled and parity mode if enabled). 751:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note This function selects if hardware parity control (generation and detection) is enabled 752:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * When the parity control is enabled (Odd or Even), computed parity bit is inserted at th 753:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * (9th or 8th bit depending on data width) and parity is checked on the received data. 754:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 PS LL_USART_SetParity\n 755:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR1 PCE LL_USART_SetParity 756:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 757:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param Parity This parameter can be one of the following values: 758:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_PARITY_NONE 759:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_PARITY_EVEN 760:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_PARITY_ODD 761:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 762:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 763:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetParity(USART_TypeDef *USARTx, uint32_t Parity) 764:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 765:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** MODIFY_REG(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE, Parity); 766:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 767:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 768:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 769:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Return Parity configuration (enabled/disabled and parity mode if enabled) 770:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 PS LL_USART_GetParity\n 771:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR1 PCE LL_USART_GetParity 772:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 773:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Returned value can be one of the following values: 774:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_PARITY_NONE 775:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_PARITY_EVEN 776:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_PARITY_ODD 777:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 778:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetParity(const USART_TypeDef *USARTx) ARM GAS /tmp/ccqopZd5.s page 349 779:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 780:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE)); 781:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 782:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 783:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 784:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Set Receiver Wake Up method from Mute mode. 785:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 WAKE LL_USART_SetWakeUpMethod 786:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 787:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param Method This parameter can be one of the following values: 788:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_WAKEUP_IDLELINE 789:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_WAKEUP_ADDRESSMARK 790:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 791:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 792:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetWakeUpMethod(USART_TypeDef *USARTx, uint32_t Method) 793:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 794:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** MODIFY_REG(USARTx->CR1, USART_CR1_WAKE, Method); 795:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 796:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 797:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 798:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Return Receiver Wake Up method from Mute mode 799:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 WAKE LL_USART_GetWakeUpMethod 800:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 801:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Returned value can be one of the following values: 802:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_WAKEUP_IDLELINE 803:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_WAKEUP_ADDRESSMARK 804:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 805:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetWakeUpMethod(const USART_TypeDef *USARTx) 806:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 807:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_WAKE)); 808:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 809:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 810:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 811:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Set Word length (i.e. nb of data bits, excluding start and stop bits) 812:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 M0 LL_USART_SetDataWidth\n 813:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR1 M1 LL_USART_SetDataWidth 814:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 815:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param DataWidth This parameter can be one of the following values: 816:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_DATAWIDTH_7B 817:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_DATAWIDTH_8B 818:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_DATAWIDTH_9B 819:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 820:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 821:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetDataWidth(USART_TypeDef *USARTx, uint32_t DataWidth) 822:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 823:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** MODIFY_REG(USARTx->CR1, USART_CR1_M, DataWidth); 824:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 825:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 826:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 827:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Return Word length (i.e. nb of data bits, excluding start and stop bits) 828:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 M0 LL_USART_GetDataWidth\n 829:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR1 M1 LL_USART_GetDataWidth 830:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 831:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Returned value can be one of the following values: 832:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_DATAWIDTH_7B 833:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_DATAWIDTH_8B 834:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_DATAWIDTH_9B 835:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ ARM GAS /tmp/ccqopZd5.s page 350 836:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetDataWidth(const USART_TypeDef *USARTx) 837:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 838:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_M)); 839:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 840:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 841:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 842:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Allow switch between Mute Mode and Active mode 843:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 MME LL_USART_EnableMuteMode 844:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 845:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 846:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 847:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableMuteMode(USART_TypeDef *USARTx) 848:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 849:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_MME); 850:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 851:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 852:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 853:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Prevent Mute Mode use. Set Receiver in active mode permanently. 854:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 MME LL_USART_DisableMuteMode 855:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 856:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 857:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 858:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableMuteMode(USART_TypeDef *USARTx) 859:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 860:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_MME); 861:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 862:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 863:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 864:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Indicate if switch between Mute Mode and Active mode is allowed 865:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 MME LL_USART_IsEnabledMuteMode 866:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 867:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). 868:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 869:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledMuteMode(const USART_TypeDef *USARTx) 870:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 871:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->CR1, USART_CR1_MME) == (USART_CR1_MME)) ? 1UL : 0UL); 872:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 873:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 874:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 875:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Set Oversampling to 8-bit or 16-bit mode 876:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 OVER8 LL_USART_SetOverSampling 877:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 878:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param OverSampling This parameter can be one of the following values: 879:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_OVERSAMPLING_16 880:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_OVERSAMPLING_8 881:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 882:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 883:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetOverSampling(USART_TypeDef *USARTx, uint32_t OverSampling) 884:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 885:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** MODIFY_REG(USARTx->CR1, USART_CR1_OVER8, OverSampling); 886:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 887:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 888:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 889:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Return Oversampling mode 890:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 OVER8 LL_USART_GetOverSampling 891:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 892:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Returned value can be one of the following values: ARM GAS /tmp/ccqopZd5.s page 351 893:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_OVERSAMPLING_16 894:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_OVERSAMPLING_8 895:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 896:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetOverSampling(const USART_TypeDef *USARTx) 897:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 898:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_OVER8)); 899:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 900:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 901:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 902:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Configure if Clock pulse of the last data bit is output to the SCLK pin or not 903:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not 904:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Synchronous mode is supported by the USARTx instance. 905:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 LBCL LL_USART_SetLastClkPulseOutput 906:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param LastBitClockPulse This parameter can be one of the following values: 908:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT 909:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_LASTCLKPULSE_OUTPUT 910:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 911:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 912:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetLastClkPulseOutput(USART_TypeDef *USARTx, uint32_t LastBitClockPul 913:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 914:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** MODIFY_REG(USARTx->CR2, USART_CR2_LBCL, LastBitClockPulse); 915:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 916:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 917:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Retrieve Clock pulse of the last data bit output configuration 919:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * (Last bit Clock pulse output to the SCLK pin or not) 920:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not 921:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Synchronous mode is supported by the USARTx instance. 922:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 LBCL LL_USART_GetLastClkPulseOutput 923:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 924:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Returned value can be one of the following values: 925:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT 926:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_LASTCLKPULSE_OUTPUT 927:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 928:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetLastClkPulseOutput(const USART_TypeDef *USARTx) 929:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 930:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_LBCL)); 931:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 932:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 933:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 934:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Select the phase of the clock output on the SCLK pin in synchronous mode 935:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not 936:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Synchronous mode is supported by the USARTx instance. 937:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 CPHA LL_USART_SetClockPhase 938:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 939:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param ClockPhase This parameter can be one of the following values: 940:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_PHASE_1EDGE 941:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_PHASE_2EDGE 942:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 943:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 944:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetClockPhase(USART_TypeDef *USARTx, uint32_t ClockPhase) 945:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 946:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** MODIFY_REG(USARTx->CR2, USART_CR2_CPHA, ClockPhase); 947:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 948:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 949:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** ARM GAS /tmp/ccqopZd5.s page 352 950:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Return phase of the clock output on the SCLK pin in synchronous mode 951:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not 952:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Synchronous mode is supported by the USARTx instance. 953:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 CPHA LL_USART_GetClockPhase 954:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 955:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Returned value can be one of the following values: 956:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_PHASE_1EDGE 957:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_PHASE_2EDGE 958:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 959:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetClockPhase(const USART_TypeDef *USARTx) 960:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 961:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_CPHA)); 962:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 963:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 964:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 965:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Select the polarity of the clock output on the SCLK pin in synchronous mode 966:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not 967:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Synchronous mode is supported by the USARTx instance. 968:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 CPOL LL_USART_SetClockPolarity 969:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 970:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param ClockPolarity This parameter can be one of the following values: 971:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_POLARITY_LOW 972:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_POLARITY_HIGH 973:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 974:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 975:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetClockPolarity(USART_TypeDef *USARTx, uint32_t ClockPolarity) 976:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 977:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** MODIFY_REG(USARTx->CR2, USART_CR2_CPOL, ClockPolarity); 978:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 979:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 980:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 981:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Return polarity of the clock output on the SCLK pin in synchronous mode 982:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not 983:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Synchronous mode is supported by the USARTx instance. 984:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 CPOL LL_USART_GetClockPolarity 985:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 986:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Returned value can be one of the following values: 987:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_POLARITY_LOW 988:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_POLARITY_HIGH 989:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 990:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetClockPolarity(const USART_TypeDef *USARTx) 991:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 992:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_CPOL)); 993:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 994:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 995:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 996:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Configure Clock signal format (Phase Polarity and choice about output of last bit clock 997:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not 998:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Synchronous mode is supported by the USARTx instance. 999:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Call of this function is equivalent to following function call sequence : 1000:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Clock Phase configuration using @ref LL_USART_SetClockPhase() function 1001:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Clock Polarity configuration using @ref LL_USART_SetClockPolarity() function 1002:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Output of Last bit Clock pulse configuration using @ref LL_USART_SetLastClkPulseOutpu 1003:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 CPHA LL_USART_ConfigClock\n 1004:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR2 CPOL LL_USART_ConfigClock\n 1005:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR2 LBCL LL_USART_ConfigClock 1006:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance ARM GAS /tmp/ccqopZd5.s page 353 1007:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param Phase This parameter can be one of the following values: 1008:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_PHASE_1EDGE 1009:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_PHASE_2EDGE 1010:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param Polarity This parameter can be one of the following values: 1011:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_POLARITY_LOW 1012:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_POLARITY_HIGH 1013:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param LBCPOutput This parameter can be one of the following values: 1014:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT 1015:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_LASTCLKPULSE_OUTPUT 1016:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 1017:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1018:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_ConfigClock(USART_TypeDef *USARTx, uint32_t Phase, uint32_t Polarity, 1019:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1020:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** MODIFY_REG(USARTx->CR2, USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_LBCL, Phase | Polarity | LBCP 1021:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1022:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1023:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1024:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Enable Clock output on SCLK pin 1025:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not 1026:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Synchronous mode is supported by the USARTx instance. 1027:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 CLKEN LL_USART_EnableSCLKOutput 1028:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1029:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 1030:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1031:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableSCLKOutput(USART_TypeDef *USARTx) 1032:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1033:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** SET_BIT(USARTx->CR2, USART_CR2_CLKEN); 1034:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1035:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1036:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1037:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Disable Clock output on SCLK pin 1038:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not 1039:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Synchronous mode is supported by the USARTx instance. 1040:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 CLKEN LL_USART_DisableSCLKOutput 1041:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1042:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 1043:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1044:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableSCLKOutput(USART_TypeDef *USARTx) 1045:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1046:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** CLEAR_BIT(USARTx->CR2, USART_CR2_CLKEN); 1047:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1048:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1049:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1050:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Indicate if Clock output on SCLK pin is enabled 1051:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not 1052:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Synchronous mode is supported by the USARTx instance. 1053:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 CLKEN LL_USART_IsEnabledSCLKOutput 1054:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1055:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). 1056:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1057:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledSCLKOutput(const USART_TypeDef *USARTx) 1058:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1059:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->CR2, USART_CR2_CLKEN) == (USART_CR2_CLKEN)) ? 1UL : 0UL); 1060:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1061:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1062:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1063:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Set the length of the stop bits ARM GAS /tmp/ccqopZd5.s page 354 1064:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 STOP LL_USART_SetStopBitsLength 1065:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1066:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param StopBits This parameter can be one of the following values: 1067:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_STOPBITS_0_5 1068:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_STOPBITS_1 1069:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_STOPBITS_1_5 1070:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_STOPBITS_2 1071:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 1072:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1073:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetStopBitsLength(USART_TypeDef *USARTx, uint32_t StopBits) 1074:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1075:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** MODIFY_REG(USARTx->CR2, USART_CR2_STOP, StopBits); 1076:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1077:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1078:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1079:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Retrieve the length of the stop bits 1080:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 STOP LL_USART_GetStopBitsLength 1081:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1082:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Returned value can be one of the following values: 1083:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_STOPBITS_0_5 1084:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_STOPBITS_1 1085:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_STOPBITS_1_5 1086:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_STOPBITS_2 1087:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1088:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetStopBitsLength(const USART_TypeDef *USARTx) 1089:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1090:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_STOP)); 1091:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1092:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1093:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1094:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Configure Character frame format (Datawidth, Parity control, Stop Bits) 1095:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Call of this function is equivalent to following function call sequence : 1096:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Data Width configuration using @ref LL_USART_SetDataWidth() function 1097:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Parity Control and mode configuration using @ref LL_USART_SetParity() function 1098:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Stop bits configuration using @ref LL_USART_SetStopBitsLength() function 1099:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 PS LL_USART_ConfigCharacter\n 1100:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR1 PCE LL_USART_ConfigCharacter\n 1101:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR1 M0 LL_USART_ConfigCharacter\n 1102:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR1 M1 LL_USART_ConfigCharacter\n 1103:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR2 STOP LL_USART_ConfigCharacter 1104:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1105:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param DataWidth This parameter can be one of the following values: 1106:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_DATAWIDTH_7B 1107:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_DATAWIDTH_8B 1108:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_DATAWIDTH_9B 1109:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param Parity This parameter can be one of the following values: 1110:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_PARITY_NONE 1111:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_PARITY_EVEN 1112:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_PARITY_ODD 1113:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param StopBits This parameter can be one of the following values: 1114:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_STOPBITS_0_5 1115:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_STOPBITS_1 1116:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_STOPBITS_1_5 1117:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_STOPBITS_2 1118:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 1119:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1120:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_ConfigCharacter(USART_TypeDef *USARTx, uint32_t DataWidth, uint32_t P ARM GAS /tmp/ccqopZd5.s page 355 1121:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** uint32_t StopBits) 1122:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1123:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** MODIFY_REG(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE | USART_CR1_M, Parity | DataWidth); 1124:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** MODIFY_REG(USARTx->CR2, USART_CR2_STOP, StopBits); 1125:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1126:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1127:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1128:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Configure TX/RX pins swapping setting. 1129:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 SWAP LL_USART_SetTXRXSwap 1130:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1131:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param SwapConfig This parameter can be one of the following values: 1132:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_TXRX_STANDARD 1133:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_TXRX_SWAPPED 1134:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 1135:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1136:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetTXRXSwap(USART_TypeDef *USARTx, uint32_t SwapConfig) 1137:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1138:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** MODIFY_REG(USARTx->CR2, USART_CR2_SWAP, SwapConfig); 1139:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1140:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1141:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1142:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Retrieve TX/RX pins swapping configuration. 1143:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 SWAP LL_USART_GetTXRXSwap 1144:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1145:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Returned value can be one of the following values: 1146:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_TXRX_STANDARD 1147:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_TXRX_SWAPPED 1148:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1149:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetTXRXSwap(const USART_TypeDef *USARTx) 1150:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1151:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_SWAP)); 1152:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1153:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1154:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1155:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Configure RX pin active level logic 1156:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 RXINV LL_USART_SetRXPinLevel 1157:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1158:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param PinInvMethod This parameter can be one of the following values: 1159:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_RXPIN_LEVEL_STANDARD 1160:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_RXPIN_LEVEL_INVERTED 1161:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 1162:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1163:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetRXPinLevel(USART_TypeDef *USARTx, uint32_t PinInvMethod) 1164:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1165:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** MODIFY_REG(USARTx->CR2, USART_CR2_RXINV, PinInvMethod); 1166:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1167:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1168:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1169:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Retrieve RX pin active level logic configuration 1170:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 RXINV LL_USART_GetRXPinLevel 1171:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1172:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Returned value can be one of the following values: 1173:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_RXPIN_LEVEL_STANDARD 1174:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_RXPIN_LEVEL_INVERTED 1175:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1176:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetRXPinLevel(const USART_TypeDef *USARTx) 1177:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { ARM GAS /tmp/ccqopZd5.s page 356 1178:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_RXINV)); 1179:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1180:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1181:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1182:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Configure TX pin active level logic 1183:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 TXINV LL_USART_SetTXPinLevel 1184:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1185:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param PinInvMethod This parameter can be one of the following values: 1186:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_TXPIN_LEVEL_STANDARD 1187:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_TXPIN_LEVEL_INVERTED 1188:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 1189:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1190:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetTXPinLevel(USART_TypeDef *USARTx, uint32_t PinInvMethod) 1191:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1192:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** MODIFY_REG(USARTx->CR2, USART_CR2_TXINV, PinInvMethod); 1193:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1194:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1195:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1196:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Retrieve TX pin active level logic configuration 1197:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 TXINV LL_USART_GetTXPinLevel 1198:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1199:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Returned value can be one of the following values: 1200:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_TXPIN_LEVEL_STANDARD 1201:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_TXPIN_LEVEL_INVERTED 1202:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1203:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetTXPinLevel(const USART_TypeDef *USARTx) 1204:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1205:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_TXINV)); 1206:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1207:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1208:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1209:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Configure Binary data logic. 1210:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Allow to define how Logical data from the data register are send/received : 1211:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * either in positive/direct logic (1=H, 0=L) or in negative/inverse logic (1=L, 0=H) 1212:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 DATAINV LL_USART_SetBinaryDataLogic 1213:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1214:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param DataLogic This parameter can be one of the following values: 1215:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_BINARY_LOGIC_POSITIVE 1216:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_BINARY_LOGIC_NEGATIVE 1217:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 1218:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1219:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetBinaryDataLogic(USART_TypeDef *USARTx, uint32_t DataLogic) 1220:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1221:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** MODIFY_REG(USARTx->CR2, USART_CR2_DATAINV, DataLogic); 1222:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1223:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1224:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1225:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Retrieve Binary data configuration 1226:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 DATAINV LL_USART_GetBinaryDataLogic 1227:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1228:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Returned value can be one of the following values: 1229:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_BINARY_LOGIC_POSITIVE 1230:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_BINARY_LOGIC_NEGATIVE 1231:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1232:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetBinaryDataLogic(const USART_TypeDef *USARTx) 1233:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1234:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_DATAINV)); ARM GAS /tmp/ccqopZd5.s page 357 1235:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1236:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1237:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1238:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Configure transfer bit order (either Less or Most Significant Bit First) 1239:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note MSB First means data is transmitted/received with the MSB first, following the start bi 1240:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * LSB First means data is transmitted/received with data bit 0 first, following the start 1241:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 MSBFIRST LL_USART_SetTransferBitOrder 1242:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1243:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param BitOrder This parameter can be one of the following values: 1244:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_BITORDER_LSBFIRST 1245:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_BITORDER_MSBFIRST 1246:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 1247:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1248:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetTransferBitOrder(USART_TypeDef *USARTx, uint32_t BitOrder) 1249:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1250:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** MODIFY_REG(USARTx->CR2, USART_CR2_MSBFIRST, BitOrder); 1251:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1252:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1253:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1254:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Return transfer bit order (either Less or Most Significant Bit First) 1255:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note MSB First means data is transmitted/received with the MSB first, following the start bi 1256:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * LSB First means data is transmitted/received with data bit 0 first, following the start 1257:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 MSBFIRST LL_USART_GetTransferBitOrder 1258:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1259:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Returned value can be one of the following values: 1260:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_BITORDER_LSBFIRST 1261:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_BITORDER_MSBFIRST 1262:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1263:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetTransferBitOrder(const USART_TypeDef *USARTx) 1264:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1265:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_MSBFIRST)); 1266:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1267:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1268:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1269:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Enable Auto Baud-Rate Detection 1270:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or 1271:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Auto Baud Rate detection feature is supported by the USARTx instance. 1272:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 ABREN LL_USART_EnableAutoBaudRate 1273:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1274:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 1275:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1276:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableAutoBaudRate(USART_TypeDef *USARTx) 1277:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1278:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** SET_BIT(USARTx->CR2, USART_CR2_ABREN); 1279:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1280:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1281:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1282:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Disable Auto Baud-Rate Detection 1283:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or 1284:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Auto Baud Rate detection feature is supported by the USARTx instance. 1285:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 ABREN LL_USART_DisableAutoBaudRate 1286:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1287:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 1288:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1289:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableAutoBaudRate(USART_TypeDef *USARTx) 1290:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1291:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** CLEAR_BIT(USARTx->CR2, USART_CR2_ABREN); ARM GAS /tmp/ccqopZd5.s page 358 1292:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1293:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1294:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1295:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Indicate if Auto Baud-Rate Detection mechanism is enabled 1296:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or 1297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Auto Baud Rate detection feature is supported by the USARTx instance. 1298:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 ABREN LL_USART_IsEnabledAutoBaud 1299:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1300:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). 1301:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1302:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledAutoBaud(const USART_TypeDef *USARTx) 1303:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1304:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->CR2, USART_CR2_ABREN) == (USART_CR2_ABREN)) ? 1UL : 0UL); 1305:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1306:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1307:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1308:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Set Auto Baud-Rate mode bits 1309:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or 1310:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Auto Baud Rate detection feature is supported by the USARTx instance. 1311:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 ABRMODE LL_USART_SetAutoBaudRateMode 1312:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1313:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param AutoBaudRateMode This parameter can be one of the following values: 1314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_STARTBIT 1315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_FALLINGEDGE 1316:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME 1317:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_55_FRAME 1318:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 1319:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1320:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetAutoBaudRateMode(USART_TypeDef *USARTx, uint32_t AutoBaudRateMode) 1321:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1322:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** MODIFY_REG(USARTx->CR2, USART_CR2_ABRMODE, AutoBaudRateMode); 1323:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1324:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1325:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1326:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Return Auto Baud-Rate mode 1327:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or 1328:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Auto Baud Rate detection feature is supported by the USARTx instance. 1329:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 ABRMODE LL_USART_GetAutoBaudRateMode 1330:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1331:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Returned value can be one of the following values: 1332:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_STARTBIT 1333:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_FALLINGEDGE 1334:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME 1335:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_55_FRAME 1336:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1337:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetAutoBaudRateMode(const USART_TypeDef *USARTx) 1338:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1339:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_ABRMODE)); 1340:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1341:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1342:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1343:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Enable Receiver Timeout 1344:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 RTOEN LL_USART_EnableRxTimeout 1345:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 1347:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1348:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableRxTimeout(USART_TypeDef *USARTx) ARM GAS /tmp/ccqopZd5.s page 359 1349:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1350:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** SET_BIT(USARTx->CR2, USART_CR2_RTOEN); 1351:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1352:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1353:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1354:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Disable Receiver Timeout 1355:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 RTOEN LL_USART_DisableRxTimeout 1356:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1357:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 1358:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1359:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableRxTimeout(USART_TypeDef *USARTx) 1360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1361:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** CLEAR_BIT(USARTx->CR2, USART_CR2_RTOEN); 1362:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1363:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1364:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1365:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Indicate if Receiver Timeout feature is enabled 1366:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 RTOEN LL_USART_IsEnabledRxTimeout 1367:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1368:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). 1369:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledRxTimeout(const USART_TypeDef *USARTx) 1371:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->CR2, USART_CR2_RTOEN) == (USART_CR2_RTOEN)) ? 1UL : 0UL); 1373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1374:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1375:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1376:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Set Address of the USART node. 1377:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note This is used in multiprocessor communication during Mute mode or Stop mode, 1378:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * for wake up with address mark detection. 1379:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note 4bits address node is used when 4-bit Address Detection is selected in ADDM7. 1380:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * (b7-b4 should be set to 0) 1381:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * 8bits address node is used when 7-bit Address Detection is selected in ADDM7. 1382:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * (This is used in multiprocessor communication during Mute mode or Stop mode, 1383:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * for wake up with 7-bit address mark detection. 1384:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * The MSB of the character sent by the transmitter should be equal to 1. 1385:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * It may also be used for character detection during normal reception, 1386:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Mute mode inactive (for example, end of block detection in ModBus protocol). 1387:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * In this case, the whole received character (8-bit) is compared to the ADD[7:0] 1388:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * value and CMF flag is set on match) 1389:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 ADD LL_USART_ConfigNodeAddress\n 1390:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR2 ADDM7 LL_USART_ConfigNodeAddress 1391:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1392:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param AddressLen This parameter can be one of the following values: 1393:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_ADDRESS_DETECT_4B 1394:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_ADDRESS_DETECT_7B 1395:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param NodeAddress 4 or 7 bit Address of the USART node. 1396:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 1397:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1398:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_ConfigNodeAddress(USART_TypeDef *USARTx, uint32_t AddressLen, uint32_ 1399:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1400:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** MODIFY_REG(USARTx->CR2, USART_CR2_ADD | USART_CR2_ADDM7, 1401:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** (uint32_t)(AddressLen | (NodeAddress << USART_CR2_ADD_Pos))); 1402:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1403:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1404:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1405:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Return 8 bit Address of the USART node as set in ADD field of CR2. ARM GAS /tmp/ccqopZd5.s page 360 1406:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note If 4-bit Address Detection is selected in ADDM7, 1407:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * only 4bits (b3-b0) of returned value are relevant (b31-b4 are not relevant) 1408:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * If 7-bit Address Detection is selected in ADDM7, 1409:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * only 8bits (b7-b0) of returned value are relevant (b31-b8 are not relevant) 1410:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 ADD LL_USART_GetNodeAddress 1411:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1412:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Address of the USART node (Value between Min_Data=0 and Max_Data=255) 1413:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1414:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetNodeAddress(const USART_TypeDef *USARTx) 1415:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1416:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_ADD) >> USART_CR2_ADD_Pos); 1417:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1418:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1419:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1420:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Return Length of Node Address used in Address Detection mode (7-bit or 4-bit) 1421:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 ADDM7 LL_USART_GetNodeAddressLen 1422:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1423:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Returned value can be one of the following values: 1424:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_ADDRESS_DETECT_4B 1425:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_ADDRESS_DETECT_7B 1426:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1427:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetNodeAddressLen(const USART_TypeDef *USARTx) 1428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1429:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_ADDM7)); 1430:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1431:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1432:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1433:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Enable RTS HW Flow Control 1434:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not 1435:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Hardware Flow control feature is supported by the USARTx instance. 1436:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 RTSE LL_USART_EnableRTSHWFlowCtrl 1437:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1438:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 1439:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1440:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableRTSHWFlowCtrl(USART_TypeDef *USARTx) 1441:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1442:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** SET_BIT(USARTx->CR3, USART_CR3_RTSE); 1443:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1444:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1445:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1446:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Disable RTS HW Flow Control 1447:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not 1448:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Hardware Flow control feature is supported by the USARTx instance. 1449:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 RTSE LL_USART_DisableRTSHWFlowCtrl 1450:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1451:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 1452:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1453:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableRTSHWFlowCtrl(USART_TypeDef *USARTx) 1454:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1455:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** CLEAR_BIT(USARTx->CR3, USART_CR3_RTSE); 1456:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1457:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1458:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1459:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Enable CTS HW Flow Control 1460:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not 1461:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Hardware Flow control feature is supported by the USARTx instance. 1462:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 CTSE LL_USART_EnableCTSHWFlowCtrl ARM GAS /tmp/ccqopZd5.s page 361 1463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1464:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 1465:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1466:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableCTSHWFlowCtrl(USART_TypeDef *USARTx) 1467:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1468:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** SET_BIT(USARTx->CR3, USART_CR3_CTSE); 1469:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1470:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1471:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1472:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Disable CTS HW Flow Control 1473:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not 1474:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Hardware Flow control feature is supported by the USARTx instance. 1475:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 CTSE LL_USART_DisableCTSHWFlowCtrl 1476:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1477:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 1478:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1479:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableCTSHWFlowCtrl(USART_TypeDef *USARTx) 1480:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1481:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** CLEAR_BIT(USARTx->CR3, USART_CR3_CTSE); 1482:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1483:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1484:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1485:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Configure HW Flow Control mode (both CTS and RTS) 1486:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not 1487:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Hardware Flow control feature is supported by the USARTx instance. 1488:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 RTSE LL_USART_SetHWFlowCtrl\n 1489:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR3 CTSE LL_USART_SetHWFlowCtrl 1490:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1491:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param HardwareFlowControl This parameter can be one of the following values: 1492:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_HWCONTROL_NONE 1493:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_HWCONTROL_RTS 1494:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_HWCONTROL_CTS 1495:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_HWCONTROL_RTS_CTS 1496:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 1497:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1498:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetHWFlowCtrl(USART_TypeDef *USARTx, uint32_t HardwareFlowControl) 1499:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1500:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** MODIFY_REG(USARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE, HardwareFlowControl); 1501:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1502:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1503:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1504:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Return HW Flow Control configuration (both CTS and RTS) 1505:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not 1506:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Hardware Flow control feature is supported by the USARTx instance. 1507:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 RTSE LL_USART_GetHWFlowCtrl\n 1508:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR3 CTSE LL_USART_GetHWFlowCtrl 1509:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1510:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Returned value can be one of the following values: 1511:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_HWCONTROL_NONE 1512:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_HWCONTROL_RTS 1513:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_HWCONTROL_CTS 1514:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_HWCONTROL_RTS_CTS 1515:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1516:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetHWFlowCtrl(const USART_TypeDef *USARTx) 1517:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1518:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE)); 1519:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } ARM GAS /tmp/ccqopZd5.s page 362 1520:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1521:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1522:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Enable One bit sampling method 1523:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 ONEBIT LL_USART_EnableOneBitSamp 1524:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1525:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 1526:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1527:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableOneBitSamp(USART_TypeDef *USARTx) 1528:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1529:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** SET_BIT(USARTx->CR3, USART_CR3_ONEBIT); 1530:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1531:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1532:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1533:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Disable One bit sampling method 1534:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 ONEBIT LL_USART_DisableOneBitSamp 1535:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1536:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 1537:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1538:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableOneBitSamp(USART_TypeDef *USARTx) 1539:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1540:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** CLEAR_BIT(USARTx->CR3, USART_CR3_ONEBIT); 1541:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1542:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1543:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1544:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Indicate if One bit sampling method is enabled 1545:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 ONEBIT LL_USART_IsEnabledOneBitSamp 1546:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1547:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). 1548:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1549:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledOneBitSamp(const USART_TypeDef *USARTx) 1550:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1551:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->CR3, USART_CR3_ONEBIT) == (USART_CR3_ONEBIT)) ? 1UL : 0UL); 1552:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1553:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1554:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1555:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Enable Overrun detection 1556:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 OVRDIS LL_USART_EnableOverrunDetect 1557:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1558:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 1559:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1560:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableOverrunDetect(USART_TypeDef *USARTx) 1561:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1562:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** CLEAR_BIT(USARTx->CR3, USART_CR3_OVRDIS); 1563:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1564:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1565:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1566:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Disable Overrun detection 1567:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 OVRDIS LL_USART_DisableOverrunDetect 1568:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1569:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 1570:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1571:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableOverrunDetect(USART_TypeDef *USARTx) 1572:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1573:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** SET_BIT(USARTx->CR3, USART_CR3_OVRDIS); 1574:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1575:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1576:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** ARM GAS /tmp/ccqopZd5.s page 363 1577:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Indicate if Overrun detection is enabled 1578:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 OVRDIS LL_USART_IsEnabledOverrunDetect 1579:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1580:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). 1581:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1582:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledOverrunDetect(const USART_TypeDef *USARTx) 1583:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1584:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->CR3, USART_CR3_OVRDIS) != USART_CR3_OVRDIS) ? 1UL : 0UL); 1585:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1586:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1587:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_CR1_UESM) 1588:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_CR3_WUS) 1589:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1590:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Select event type for Wake UP Interrupt Flag (WUS[1:0] bits) 1591:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not 1592:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Wake-up from Stop mode feature is supported by the USARTx instance. 1593:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 WUS LL_USART_SetWKUPType 1594:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1595:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param Type This parameter can be one of the following values: 1596:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_WAKEUP_ON_ADDRESS 1597:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_WAKEUP_ON_STARTBIT 1598:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_WAKEUP_ON_RXNE 1599:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 1600:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1601:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetWKUPType(USART_TypeDef *USARTx, uint32_t Type) 1602:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1603:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** MODIFY_REG(USARTx->CR3, USART_CR3_WUS, Type); 1604:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1605:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1606:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1607:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Return event type for Wake UP Interrupt Flag (WUS[1:0] bits) 1608:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not 1609:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Wake-up from Stop mode feature is supported by the USARTx instance. 1610:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 WUS LL_USART_GetWKUPType 1611:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1612:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Returned value can be one of the following values: 1613:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_WAKEUP_ON_ADDRESS 1614:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_WAKEUP_ON_STARTBIT 1615:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_WAKEUP_ON_RXNE 1616:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1617:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetWKUPType(const USART_TypeDef *USARTx) 1618:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1619:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_WUS)); 1620:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1621:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1622:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_CR3_WUS */ 1623:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_CR1_UESM */ 1624:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1625:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Configure USART BRR register for achieving expected Baud Rate value. 1626:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Compute and set USARTDIV value in BRR Register (full BRR content) 1627:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * according to used Peripheral Clock, Oversampling mode, and expected Baud Rate values 1628:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Peripheral clock and Baud rate values provided as function parameters should be valid 1629:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * (Baud rate value != 0) 1630:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note In case of oversampling by 16 and 8, BRR content must be greater than or equal to 16d. 1631:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll BRR BRR LL_USART_SetBaudRate 1632:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1633:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param PeriphClk Peripheral Clock ARM GAS /tmp/ccqopZd5.s page 364 1634:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param OverSampling This parameter can be one of the following values: 1635:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_OVERSAMPLING_16 1636:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_OVERSAMPLING_8 1637:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param BaudRate Baud Rate 1638:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 1639:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1640:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetBaudRate(USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t OverS 1641:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** uint32_t BaudRate) 1642:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1643:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** uint32_t usartdiv; 1644:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** uint32_t brrtemp; 1645:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1646:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** if (OverSampling == LL_USART_OVERSAMPLING_8) 1647:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1648:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** usartdiv = (uint16_t)(__LL_USART_DIV_SAMPLING8(PeriphClk, BaudRate)); 1649:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** brrtemp = usartdiv & 0xFFF0U; 1650:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U); 1651:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** USARTx->BRR = brrtemp; 1652:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1653:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** else 1654:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1655:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** USARTx->BRR = (uint16_t)(__LL_USART_DIV_SAMPLING16(PeriphClk, BaudRate)); 1656:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1657:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1658:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1659:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1660:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Return current Baud Rate value, according to USARTDIV present in BRR register 1661:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * (full BRR content), and to used Peripheral Clock and Oversampling mode values 1662:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note In case of non-initialized or invalid value stored in BRR register, value 0 will be ret 1663:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note In case of oversampling by 16 and 8, BRR content must be greater than or equal to 16d. 1664:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll BRR BRR LL_USART_GetBaudRate 1665:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1666:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param PeriphClk Peripheral Clock 1667:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param OverSampling This parameter can be one of the following values: 1668:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_OVERSAMPLING_16 1669:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_OVERSAMPLING_8 1670:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Baud Rate 1671:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1672:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetBaudRate(const USART_TypeDef *USARTx, uint32_t PeriphClk, uint 1673:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1674:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** uint32_t usartdiv; 1675:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** uint32_t brrresult = 0x0U; 1676:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1677:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** usartdiv = USARTx->BRR; 1678:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1679:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** if (usartdiv == 0U) 1680:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1681:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* Do not perform a division by 0 */ 1682:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1683:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** else if (OverSampling == LL_USART_OVERSAMPLING_8) 1684:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1685:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** usartdiv = (uint16_t)((usartdiv & 0xFFF0U) | ((usartdiv & 0x0007U) << 1U)) ; 1686:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** if (usartdiv != 0U) 1687:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1688:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** brrresult = (PeriphClk * 2U) / usartdiv; 1689:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1690:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } ARM GAS /tmp/ccqopZd5.s page 365 1691:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** else 1692:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1693:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** if ((usartdiv & 0xFFFFU) != 0U) 1694:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1695:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** brrresult = PeriphClk / usartdiv; 1696:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1697:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1698:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return (brrresult); 1699:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1700:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1701:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1702:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Set Receiver Time Out Value (expressed in nb of bits duration) 1703:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll RTOR RTO LL_USART_SetRxTimeout 1704:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1705:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param Timeout Value between Min_Data=0x00 and Max_Data=0x00FFFFFF 1706:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 1707:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1708:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetRxTimeout(USART_TypeDef *USARTx, uint32_t Timeout) 1709:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1710:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** MODIFY_REG(USARTx->RTOR, USART_RTOR_RTO, Timeout); 1711:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1712:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1713:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1714:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Get Receiver Time Out Value (expressed in nb of bits duration) 1715:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll RTOR RTO LL_USART_GetRxTimeout 1716:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1717:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Value between Min_Data=0x00 and Max_Data=0x00FFFFFF 1718:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1719:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetRxTimeout(const USART_TypeDef *USARTx) 1720:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1721:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return (uint32_t)(READ_BIT(USARTx->RTOR, USART_RTOR_RTO)); 1722:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1723:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1724:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1725:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Set Block Length value in reception 1726:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll RTOR BLEN LL_USART_SetBlockLength 1727:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1728:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param BlockLength Value between Min_Data=0x00 and Max_Data=0xFF 1729:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 1730:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1731:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetBlockLength(USART_TypeDef *USARTx, uint32_t BlockLength) 1732:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1733:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** MODIFY_REG(USARTx->RTOR, USART_RTOR_BLEN, BlockLength << USART_RTOR_BLEN_Pos); 1734:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1735:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1736:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1737:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Get Block Length value in reception 1738:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll RTOR BLEN LL_USART_GetBlockLength 1739:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1740:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Value between Min_Data=0x00 and Max_Data=0xFF 1741:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1742:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetBlockLength(const USART_TypeDef *USARTx) 1743:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1744:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return (uint32_t)(READ_BIT(USARTx->RTOR, USART_RTOR_BLEN) >> USART_RTOR_BLEN_Pos); 1745:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1746:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1747:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** ARM GAS /tmp/ccqopZd5.s page 366 1748:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} 1749:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1750:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1751:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EF_Configuration_IRDA Configuration functions related to Irda feature 1752:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ 1753:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1754:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1755:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1756:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Enable IrDA mode 1757:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not 1758:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * IrDA feature is supported by the USARTx instance. 1759:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 IREN LL_USART_EnableIrda 1760:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1761:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 1762:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1763:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableIrda(USART_TypeDef *USARTx) 1764:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1765:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** SET_BIT(USARTx->CR3, USART_CR3_IREN); 1766:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1767:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1768:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1769:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Disable IrDA mode 1770:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not 1771:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * IrDA feature is supported by the USARTx instance. 1772:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 IREN LL_USART_DisableIrda 1773:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1774:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 1775:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1776:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableIrda(USART_TypeDef *USARTx) 1777:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1778:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** CLEAR_BIT(USARTx->CR3, USART_CR3_IREN); 1779:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1780:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1781:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1782:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Indicate if IrDA mode is enabled 1783:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not 1784:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * IrDA feature is supported by the USARTx instance. 1785:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 IREN LL_USART_IsEnabledIrda 1786:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1787:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). 1788:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1789:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledIrda(const USART_TypeDef *USARTx) 1790:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1791:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->CR3, USART_CR3_IREN) == (USART_CR3_IREN)) ? 1UL : 0UL); 1792:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1793:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1794:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1795:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Configure IrDA Power Mode (Normal or Low Power) 1796:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not 1797:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * IrDA feature is supported by the USARTx instance. 1798:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 IRLP LL_USART_SetIrdaPowerMode 1799:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1800:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param PowerMode This parameter can be one of the following values: 1801:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_IRDA_POWER_NORMAL 1802:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_IRDA_POWER_LOW 1803:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 1804:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ ARM GAS /tmp/ccqopZd5.s page 367 1805:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetIrdaPowerMode(USART_TypeDef *USARTx, uint32_t PowerMode) 1806:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1807:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** MODIFY_REG(USARTx->CR3, USART_CR3_IRLP, PowerMode); 1808:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1809:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1810:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1811:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Retrieve IrDA Power Mode configuration (Normal or Low Power) 1812:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not 1813:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * IrDA feature is supported by the USARTx instance. 1814:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 IRLP LL_USART_GetIrdaPowerMode 1815:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1816:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Returned value can be one of the following values: 1817:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_IRDA_POWER_NORMAL 1818:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_PHASE_2EDGE 1819:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1820:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetIrdaPowerMode(const USART_TypeDef *USARTx) 1821:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1822:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_IRLP)); 1823:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1824:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1825:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1826:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Set Irda prescaler value, used for dividing the USART clock source 1827:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * to achieve the Irda Low Power frequency (8 bits value) 1828:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not 1829:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * IrDA feature is supported by the USARTx instance. 1830:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll GTPR PSC LL_USART_SetIrdaPrescaler 1831:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1832:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param PrescalerValue Value between Min_Data=0x00 and Max_Data=0xFF 1833:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 1834:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1835:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetIrdaPrescaler(USART_TypeDef *USARTx, uint32_t PrescalerValue) 1836:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1837:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** MODIFY_REG(USARTx->GTPR, USART_GTPR_PSC, (uint16_t)PrescalerValue); 1838:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1839:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1840:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1841:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Return Irda prescaler value, used for dividing the USART clock source 1842:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * to achieve the Irda Low Power frequency (8 bits value) 1843:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not 1844:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * IrDA feature is supported by the USARTx instance. 1845:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll GTPR PSC LL_USART_GetIrdaPrescaler 1846:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1847:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Irda prescaler value (Value between Min_Data=0x00 and Max_Data=0xFF) 1848:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1849:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetIrdaPrescaler(const USART_TypeDef *USARTx) 1850:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1851:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_PSC)); 1852:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1853:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1854:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1855:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} 1856:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1857:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1858:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EF_Configuration_Smartcard Configuration functions related to Smartcard feat 1859:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ 1860:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1861:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ARM GAS /tmp/ccqopZd5.s page 368 1862:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1863:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Enable Smartcard NACK transmission 1864:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not 1865:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Smartcard feature is supported by the USARTx instance. 1866:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 NACK LL_USART_EnableSmartcardNACK 1867:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1868:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 1869:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1870:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableSmartcardNACK(USART_TypeDef *USARTx) 1871:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1872:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** SET_BIT(USARTx->CR3, USART_CR3_NACK); 1873:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1874:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1875:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1876:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Disable Smartcard NACK transmission 1877:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not 1878:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Smartcard feature is supported by the USARTx instance. 1879:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 NACK LL_USART_DisableSmartcardNACK 1880:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1881:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 1882:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1883:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableSmartcardNACK(USART_TypeDef *USARTx) 1884:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1885:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** CLEAR_BIT(USARTx->CR3, USART_CR3_NACK); 1886:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1887:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1888:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1889:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Indicate if Smartcard NACK transmission is enabled 1890:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not 1891:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Smartcard feature is supported by the USARTx instance. 1892:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 NACK LL_USART_IsEnabledSmartcardNACK 1893:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1894:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). 1895:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1896:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcardNACK(const USART_TypeDef *USARTx) 1897:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1898:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->CR3, USART_CR3_NACK) == (USART_CR3_NACK)) ? 1UL : 0UL); 1899:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1900:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1901:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1902:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Enable Smartcard mode 1903:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not 1904:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Smartcard feature is supported by the USARTx instance. 1905:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 SCEN LL_USART_EnableSmartcard 1906:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 1908:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1909:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableSmartcard(USART_TypeDef *USARTx) 1910:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1911:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** SET_BIT(USARTx->CR3, USART_CR3_SCEN); 1912:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1913:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1914:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1915:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Disable Smartcard mode 1916:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not 1917:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Smartcard feature is supported by the USARTx instance. 1918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 SCEN LL_USART_DisableSmartcard ARM GAS /tmp/ccqopZd5.s page 369 1919:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1920:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 1921:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1922:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableSmartcard(USART_TypeDef *USARTx) 1923:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1924:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** CLEAR_BIT(USARTx->CR3, USART_CR3_SCEN); 1925:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1926:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1927:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1928:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Indicate if Smartcard mode is enabled 1929:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not 1930:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Smartcard feature is supported by the USARTx instance. 1931:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 SCEN LL_USART_IsEnabledSmartcard 1932:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1933:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). 1934:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1935:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcard(const USART_TypeDef *USARTx) 1936:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1937:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->CR3, USART_CR3_SCEN) == (USART_CR3_SCEN)) ? 1UL : 0UL); 1938:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1939:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1940:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1941:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Set Smartcard Auto-Retry Count value (SCARCNT[2:0] bits) 1942:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not 1943:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Smartcard feature is supported by the USARTx instance. 1944:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note This bit-field specifies the number of retries in transmit and receive, in Smartcard mo 1945:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * In transmission mode, it specifies the number of automatic retransmission retries, befo 1946:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * generating a transmission error (FE bit set). 1947:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * In reception mode, it specifies the number or erroneous reception trials, before genera 1948:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * reception error (RXNE and PE bits set) 1949:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 SCARCNT LL_USART_SetSmartcardAutoRetryCount 1950:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1951:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param AutoRetryCount Value between Min_Data=0 and Max_Data=7 1952:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 1953:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1954:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetSmartcardAutoRetryCount(USART_TypeDef *USARTx, uint32_t AutoRetryC 1955:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1956:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** MODIFY_REG(USARTx->CR3, USART_CR3_SCARCNT, AutoRetryCount << USART_CR3_SCARCNT_Pos); 1957:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1958:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1959:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1960:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Return Smartcard Auto-Retry Count value (SCARCNT[2:0] bits) 1961:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not 1962:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Smartcard feature is supported by the USARTx instance. 1963:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 SCARCNT LL_USART_GetSmartcardAutoRetryCount 1964:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1965:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Smartcard Auto-Retry Count value (Value between Min_Data=0 and Max_Data=7) 1966:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1967:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetSmartcardAutoRetryCount(const USART_TypeDef *USARTx) 1968:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1969:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_SCARCNT) >> USART_CR3_SCARCNT_Pos); 1970:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1971:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1972:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1973:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Set Smartcard prescaler value, used for dividing the USART clock 1974:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * source to provide the SMARTCARD Clock (5 bits value) 1975:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not ARM GAS /tmp/ccqopZd5.s page 370 1976:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Smartcard feature is supported by the USARTx instance. 1977:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll GTPR PSC LL_USART_SetSmartcardPrescaler 1978:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1979:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param PrescalerValue Value between Min_Data=0 and Max_Data=31 1980:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 1981:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1982:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetSmartcardPrescaler(USART_TypeDef *USARTx, uint32_t PrescalerValue) 1983:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1984:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** MODIFY_REG(USARTx->GTPR, USART_GTPR_PSC, (uint16_t)PrescalerValue); 1985:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1986:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1987:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1988:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Return Smartcard prescaler value, used for dividing the USART clock 1989:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * source to provide the SMARTCARD Clock (5 bits value) 1990:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not 1991:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Smartcard feature is supported by the USARTx instance. 1992:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll GTPR PSC LL_USART_GetSmartcardPrescaler 1993:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1994:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Smartcard prescaler value (Value between Min_Data=0 and Max_Data=31) 1995:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1996:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetSmartcardPrescaler(const USART_TypeDef *USARTx) 1997:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1998:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_PSC)); 1999:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2000:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2001:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2002:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Set Smartcard Guard time value, expressed in nb of baud clocks periods 2003:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * (GT[7:0] bits : Guard time value) 2004:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not 2005:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Smartcard feature is supported by the USARTx instance. 2006:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll GTPR GT LL_USART_SetSmartcardGuardTime 2007:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2008:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param GuardTime Value between Min_Data=0x00 and Max_Data=0xFF 2009:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 2010:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2011:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetSmartcardGuardTime(USART_TypeDef *USARTx, uint32_t GuardTime) 2012:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2013:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** MODIFY_REG(USARTx->GTPR, USART_GTPR_GT, (uint16_t)(GuardTime << USART_GTPR_GT_Pos)); 2014:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2015:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2016:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2017:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Return Smartcard Guard time value, expressed in nb of baud clocks periods 2018:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * (GT[7:0] bits : Guard time value) 2019:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not 2020:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Smartcard feature is supported by the USARTx instance. 2021:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll GTPR GT LL_USART_GetSmartcardGuardTime 2022:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2023:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Smartcard Guard time value (Value between Min_Data=0x00 and Max_Data=0xFF) 2024:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2025:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetSmartcardGuardTime(const USART_TypeDef *USARTx) 2026:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2027:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_GT) >> USART_GTPR_GT_Pos); 2028:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2029:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2030:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2031:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} 2032:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ ARM GAS /tmp/ccqopZd5.s page 371 2033:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2034:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EF_Configuration_HalfDuplex Configuration functions related to Half Duplex f 2035:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ 2036:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2037:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2038:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2039:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Enable Single Wire Half-Duplex mode 2040:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not 2041:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Half-Duplex mode is supported by the USARTx instance. 2042:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 HDSEL LL_USART_EnableHalfDuplex 2043:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2044:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 2045:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2046:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableHalfDuplex(USART_TypeDef *USARTx) 2047:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2048:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** SET_BIT(USARTx->CR3, USART_CR3_HDSEL); 2049:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2050:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2051:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2052:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Disable Single Wire Half-Duplex mode 2053:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not 2054:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Half-Duplex mode is supported by the USARTx instance. 2055:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 HDSEL LL_USART_DisableHalfDuplex 2056:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2057:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 2058:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2059:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableHalfDuplex(USART_TypeDef *USARTx) 2060:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2061:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** CLEAR_BIT(USARTx->CR3, USART_CR3_HDSEL); 2062:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2063:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2064:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2065:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Indicate if Single Wire Half-Duplex mode is enabled 2066:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not 2067:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Half-Duplex mode is supported by the USARTx instance. 2068:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 HDSEL LL_USART_IsEnabledHalfDuplex 2069:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2070:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). 2071:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2072:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledHalfDuplex(const USART_TypeDef *USARTx) 2073:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2074:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->CR3, USART_CR3_HDSEL) == (USART_CR3_HDSEL)) ? 1UL : 0UL); 2075:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2076:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2077:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2078:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} 2079:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2080:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2081:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EF_Configuration_LIN Configuration functions related to LIN feature 2082:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ 2083:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2084:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2085:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2086:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Set LIN Break Detection Length 2087:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not 2088:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * LIN feature is supported by the USARTx instance. 2089:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 LBDL LL_USART_SetLINBrkDetectionLen ARM GAS /tmp/ccqopZd5.s page 372 2090:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2091:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param LINBDLength This parameter can be one of the following values: 2092:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_LINBREAK_DETECT_10B 2093:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_LINBREAK_DETECT_11B 2094:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 2095:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2096:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetLINBrkDetectionLen(USART_TypeDef *USARTx, uint32_t LINBDLength) 2097:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2098:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** MODIFY_REG(USARTx->CR2, USART_CR2_LBDL, LINBDLength); 2099:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2100:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2101:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2102:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Return LIN Break Detection Length 2103:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not 2104:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * LIN feature is supported by the USARTx instance. 2105:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 LBDL LL_USART_GetLINBrkDetectionLen 2106:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2107:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Returned value can be one of the following values: 2108:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_LINBREAK_DETECT_10B 2109:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_LINBREAK_DETECT_11B 2110:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2111:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetLINBrkDetectionLen(const USART_TypeDef *USARTx) 2112:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2113:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_LBDL)); 2114:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2115:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2116:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2117:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Enable LIN mode 2118:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not 2119:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * LIN feature is supported by the USARTx instance. 2120:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 LINEN LL_USART_EnableLIN 2121:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2122:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 2123:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2124:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableLIN(USART_TypeDef *USARTx) 2125:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2126:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** SET_BIT(USARTx->CR2, USART_CR2_LINEN); 2127:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2128:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2129:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2130:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Disable LIN mode 2131:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not 2132:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * LIN feature is supported by the USARTx instance. 2133:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 LINEN LL_USART_DisableLIN 2134:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2135:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 2136:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2137:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableLIN(USART_TypeDef *USARTx) 2138:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2139:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** CLEAR_BIT(USARTx->CR2, USART_CR2_LINEN); 2140:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2141:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2142:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2143:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Indicate if LIN mode is enabled 2144:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not 2145:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * LIN feature is supported by the USARTx instance. 2146:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 LINEN LL_USART_IsEnabledLIN ARM GAS /tmp/ccqopZd5.s page 373 2147:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2148:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). 2149:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2150:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledLIN(const USART_TypeDef *USARTx) 2151:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2152:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->CR2, USART_CR2_LINEN) == (USART_CR2_LINEN)) ? 1UL : 0UL); 2153:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2154:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2155:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2156:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} 2157:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2158:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2159:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EF_Configuration_DE Configuration functions related to Driver Enable feature 2160:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ 2161:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2162:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2163:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2164:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Set DEDT (Driver Enable De-Assertion Time), Time value expressed on 5 bits ([4:0] bits) 2165:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not 2166:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Driver Enable feature is supported by the USARTx instance. 2167:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 DEDT LL_USART_SetDEDeassertionTime 2168:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2169:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param Time Value between Min_Data=0 and Max_Data=31 2170:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 2171:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2172:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetDEDeassertionTime(USART_TypeDef *USARTx, uint32_t Time) 2173:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2174:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** MODIFY_REG(USARTx->CR1, USART_CR1_DEDT, Time << USART_CR1_DEDT_Pos); 2175:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2176:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2177:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2178:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Return DEDT (Driver Enable De-Assertion Time) 2179:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not 2180:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Driver Enable feature is supported by the USARTx instance. 2181:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 DEDT LL_USART_GetDEDeassertionTime 2182:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2183:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Time value expressed on 5 bits ([4:0] bits) : Value between Min_Data=0 and Max_Data=31 2184:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2185:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetDEDeassertionTime(const USART_TypeDef *USARTx) 2186:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2187:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_DEDT) >> USART_CR1_DEDT_Pos); 2188:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2189:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2190:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2191:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Set DEAT (Driver Enable Assertion Time), Time value expressed on 5 bits ([4:0] bits). 2192:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not 2193:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Driver Enable feature is supported by the USARTx instance. 2194:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 DEAT LL_USART_SetDEAssertionTime 2195:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2196:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param Time Value between Min_Data=0 and Max_Data=31 2197:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 2198:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2199:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetDEAssertionTime(USART_TypeDef *USARTx, uint32_t Time) 2200:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2201:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** MODIFY_REG(USARTx->CR1, USART_CR1_DEAT, Time << USART_CR1_DEAT_Pos); 2202:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2203:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ARM GAS /tmp/ccqopZd5.s page 374 2204:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2205:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Return DEAT (Driver Enable Assertion Time) 2206:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not 2207:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Driver Enable feature is supported by the USARTx instance. 2208:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 DEAT LL_USART_GetDEAssertionTime 2209:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2210:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Time value expressed on 5 bits ([4:0] bits) : Value between Min_Data=0 and Max_Data=31 2211:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2212:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetDEAssertionTime(const USART_TypeDef *USARTx) 2213:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2214:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_DEAT) >> USART_CR1_DEAT_Pos); 2215:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2216:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2217:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2218:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Enable Driver Enable (DE) Mode 2219:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not 2220:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Driver Enable feature is supported by the USARTx instance. 2221:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 DEM LL_USART_EnableDEMode 2222:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2223:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 2224:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2225:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableDEMode(USART_TypeDef *USARTx) 2226:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2227:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** SET_BIT(USARTx->CR3, USART_CR3_DEM); 2228:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2229:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2230:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2231:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Disable Driver Enable (DE) Mode 2232:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not 2233:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Driver Enable feature is supported by the USARTx instance. 2234:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 DEM LL_USART_DisableDEMode 2235:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2236:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 2237:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2238:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableDEMode(USART_TypeDef *USARTx) 2239:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2240:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** CLEAR_BIT(USARTx->CR3, USART_CR3_DEM); 2241:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2242:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2243:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2244:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Indicate if Driver Enable (DE) Mode is enabled 2245:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not 2246:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Driver Enable feature is supported by the USARTx instance. 2247:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 DEM LL_USART_IsEnabledDEMode 2248:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2249:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). 2250:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2251:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledDEMode(const USART_TypeDef *USARTx) 2252:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2253:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->CR3, USART_CR3_DEM) == (USART_CR3_DEM)) ? 1UL : 0UL); 2254:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2255:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2256:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2257:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Select Driver Enable Polarity 2258:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not 2259:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Driver Enable feature is supported by the USARTx instance. 2260:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 DEP LL_USART_SetDESignalPolarity ARM GAS /tmp/ccqopZd5.s page 375 2261:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2262:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param Polarity This parameter can be one of the following values: 2263:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_DE_POLARITY_HIGH 2264:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_DE_POLARITY_LOW 2265:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 2266:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2267:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetDESignalPolarity(USART_TypeDef *USARTx, uint32_t Polarity) 2268:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2269:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** MODIFY_REG(USARTx->CR3, USART_CR3_DEP, Polarity); 2270:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2271:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2272:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2273:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Return Driver Enable Polarity 2274:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not 2275:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Driver Enable feature is supported by the USARTx instance. 2276:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 DEP LL_USART_GetDESignalPolarity 2277:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2278:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Returned value can be one of the following values: 2279:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_DE_POLARITY_HIGH 2280:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_DE_POLARITY_LOW 2281:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2282:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetDESignalPolarity(const USART_TypeDef *USARTx) 2283:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2284:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_DEP)); 2285:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2286:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2287:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2288:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} 2289:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2290:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2291:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EF_AdvancedConfiguration Advanced Configurations services 2292:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ 2293:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2294:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2295:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2296:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Perform basic configuration of USART for enabling use in Asynchronous Mode (UART) 2297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note In UART mode, the following bits must be kept cleared: 2298:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - LINEN bit in the USART_CR2 register, 2299:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - CLKEN bit in the USART_CR2 register, 2300:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - SCEN bit in the USART_CR3 register, 2301:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - IREN bit in the USART_CR3 register, 2302:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - HDSEL bit in the USART_CR3 register. 2303:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Call of this function is equivalent to following function call sequence : 2304:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function 2305:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function 2306:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function 2307:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function 2308:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function 2309:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Other remaining configurations items related to Asynchronous Mode 2310:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * (as Baud Rate, Word length, Parity, ...) should be set using 2311:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * dedicated functions 2312:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 LINEN LL_USART_ConfigAsyncMode\n 2313:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR2 CLKEN LL_USART_ConfigAsyncMode\n 2314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR3 SCEN LL_USART_ConfigAsyncMode\n 2315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR3 IREN LL_USART_ConfigAsyncMode\n 2316:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR3 HDSEL LL_USART_ConfigAsyncMode 2317:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance ARM GAS /tmp/ccqopZd5.s page 376 2318:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 2319:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2320:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_ConfigAsyncMode(USART_TypeDef *USARTx) 2321:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2322:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* In Asynchronous mode, the following bits must be kept cleared: 2323:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** - LINEN, CLKEN bits in the USART_CR2 register, 2324:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** - SCEN, IREN and HDSEL bits in the USART_CR3 register. 2325:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2326:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); 2327:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN | USART_CR3_HDSEL)); 2328:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2329:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2330:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2331:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Perform basic configuration of USART for enabling use in Synchronous Mode 2332:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note In Synchronous mode, the following bits must be kept cleared: 2333:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - LINEN bit in the USART_CR2 register, 2334:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - SCEN bit in the USART_CR3 register, 2335:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - IREN bit in the USART_CR3 register, 2336:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - HDSEL bit in the USART_CR3 register. 2337:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * This function also sets the USART in Synchronous mode. 2338:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not 2339:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Synchronous mode is supported by the USARTx instance. 2340:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Call of this function is equivalent to following function call sequence : 2341:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function 2342:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function 2343:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function 2344:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function 2345:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Set CLKEN in CR2 using @ref LL_USART_EnableSCLKOutput() function 2346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Other remaining configurations items related to Synchronous Mode 2347:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * (as Baud Rate, Word length, Parity, Clock Polarity, ...) should be set using 2348:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * dedicated functions 2349:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 LINEN LL_USART_ConfigSyncMode\n 2350:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR2 CLKEN LL_USART_ConfigSyncMode\n 2351:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR3 SCEN LL_USART_ConfigSyncMode\n 2352:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR3 IREN LL_USART_ConfigSyncMode\n 2353:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR3 HDSEL LL_USART_ConfigSyncMode 2354:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2355:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 2356:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2357:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_ConfigSyncMode(USART_TypeDef *USARTx) 2358:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2359:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* In Synchronous mode, the following bits must be kept cleared: 2360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** - LINEN bit in the USART_CR2 register, 2361:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** - SCEN, IREN and HDSEL bits in the USART_CR3 register. 2362:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2363:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN)); 2364:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN | USART_CR3_HDSEL)); 2365:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* set the UART/USART in Synchronous mode */ 2366:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** SET_BIT(USARTx->CR2, USART_CR2_CLKEN); 2367:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2368:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2369:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Perform basic configuration of USART for enabling use in LIN Mode 2371:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note In LIN mode, the following bits must be kept cleared: 2372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - STOP and CLKEN bits in the USART_CR2 register, 2373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - SCEN bit in the USART_CR3 register, 2374:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - IREN bit in the USART_CR3 register, ARM GAS /tmp/ccqopZd5.s page 377 2375:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - HDSEL bit in the USART_CR3 register. 2376:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * This function also set the UART/USART in LIN mode. 2377:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not 2378:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * LIN feature is supported by the USARTx instance. 2379:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Call of this function is equivalent to following function call sequence : 2380:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function 2381:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Clear STOP in CR2 using @ref LL_USART_SetStopBitsLength() function 2382:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function 2383:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function 2384:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function 2385:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Set LINEN in CR2 using @ref LL_USART_EnableLIN() function 2386:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Other remaining configurations items related to LIN Mode 2387:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * (as Baud Rate, Word length, LIN Break Detection Length, ...) should be set using 2388:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * dedicated functions 2389:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 CLKEN LL_USART_ConfigLINMode\n 2390:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR2 STOP LL_USART_ConfigLINMode\n 2391:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR2 LINEN LL_USART_ConfigLINMode\n 2392:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR3 IREN LL_USART_ConfigLINMode\n 2393:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR3 SCEN LL_USART_ConfigLINMode\n 2394:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR3 HDSEL LL_USART_ConfigLINMode 2395:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2396:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 2397:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2398:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_ConfigLINMode(USART_TypeDef *USARTx) 2399:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2400:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* In LIN mode, the following bits must be kept cleared: 2401:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** - STOP and CLKEN bits in the USART_CR2 register, 2402:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** - IREN, SCEN and HDSEL bits in the USART_CR3 register. 2403:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2404:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** CLEAR_BIT(USARTx->CR2, (USART_CR2_CLKEN | USART_CR2_STOP)); 2405:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** CLEAR_BIT(USARTx->CR3, (USART_CR3_IREN | USART_CR3_SCEN | USART_CR3_HDSEL)); 2406:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* Set the UART/USART in LIN mode */ 2407:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** SET_BIT(USARTx->CR2, USART_CR2_LINEN); 2408:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2409:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2410:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2411:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Perform basic configuration of USART for enabling use in Half Duplex Mode 2412:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note In Half Duplex mode, the following bits must be kept cleared: 2413:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - LINEN bit in the USART_CR2 register, 2414:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - CLKEN bit in the USART_CR2 register, 2415:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - SCEN bit in the USART_CR3 register, 2416:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - IREN bit in the USART_CR3 register, 2417:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * This function also sets the UART/USART in Half Duplex mode. 2418:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not 2419:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Half-Duplex mode is supported by the USARTx instance. 2420:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Call of this function is equivalent to following function call sequence : 2421:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function 2422:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function 2423:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function 2424:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function 2425:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Set HDSEL in CR3 using @ref LL_USART_EnableHalfDuplex() function 2426:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Other remaining configurations items related to Half Duplex Mode 2427:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * (as Baud Rate, Word length, Parity, ...) should be set using 2428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * dedicated functions 2429:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 LINEN LL_USART_ConfigHalfDuplexMode\n 2430:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR2 CLKEN LL_USART_ConfigHalfDuplexMode\n 2431:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR3 HDSEL LL_USART_ConfigHalfDuplexMode\n ARM GAS /tmp/ccqopZd5.s page 378 2432:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR3 SCEN LL_USART_ConfigHalfDuplexMode\n 2433:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR3 IREN LL_USART_ConfigHalfDuplexMode 2434:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2435:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 2436:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2437:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_ConfigHalfDuplexMode(USART_TypeDef *USARTx) 2438:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2439:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* In Half Duplex mode, the following bits must be kept cleared: 2440:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** - LINEN and CLKEN bits in the USART_CR2 register, 2441:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** - SCEN and IREN bits in the USART_CR3 register. 2442:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2443:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); 2444:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN)); 2445:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* set the UART/USART in Half Duplex mode */ 2446:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** SET_BIT(USARTx->CR3, USART_CR3_HDSEL); 2447:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2448:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2449:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2450:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Perform basic configuration of USART for enabling use in Smartcard Mode 2451:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note In Smartcard mode, the following bits must be kept cleared: 2452:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - LINEN bit in the USART_CR2 register, 2453:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - IREN bit in the USART_CR3 register, 2454:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - HDSEL bit in the USART_CR3 register. 2455:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * This function also configures Stop bits to 1.5 bits and 2456:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * sets the USART in Smartcard mode (SCEN bit). 2457:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Clock Output is also enabled (CLKEN). 2458:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not 2459:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Smartcard feature is supported by the USARTx instance. 2460:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Call of this function is equivalent to following function call sequence : 2461:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function 2462:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function 2463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function 2464:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Configure STOP in CR2 using @ref LL_USART_SetStopBitsLength() function 2465:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Set CLKEN in CR2 using @ref LL_USART_EnableSCLKOutput() function 2466:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Set SCEN in CR3 using @ref LL_USART_EnableSmartcard() function 2467:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Other remaining configurations items related to Smartcard Mode 2468:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * (as Baud Rate, Word length, Parity, ...) should be set using 2469:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * dedicated functions 2470:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 LINEN LL_USART_ConfigSmartcardMode\n 2471:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR2 STOP LL_USART_ConfigSmartcardMode\n 2472:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR2 CLKEN LL_USART_ConfigSmartcardMode\n 2473:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR3 HDSEL LL_USART_ConfigSmartcardMode\n 2474:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR3 SCEN LL_USART_ConfigSmartcardMode 2475:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2476:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 2477:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2478:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_ConfigSmartcardMode(USART_TypeDef *USARTx) 2479:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2480:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* In Smartcard mode, the following bits must be kept cleared: 2481:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** - LINEN bit in the USART_CR2 register, 2482:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** - IREN and HDSEL bits in the USART_CR3 register. 2483:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2484:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN)); 2485:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** CLEAR_BIT(USARTx->CR3, (USART_CR3_IREN | USART_CR3_HDSEL)); 2486:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* Configure Stop bits to 1.5 bits */ 2487:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* Synchronous mode is activated by default */ 2488:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** SET_BIT(USARTx->CR2, (USART_CR2_STOP_0 | USART_CR2_STOP_1 | USART_CR2_CLKEN)); ARM GAS /tmp/ccqopZd5.s page 379 2489:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* set the UART/USART in Smartcard mode */ 2490:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** SET_BIT(USARTx->CR3, USART_CR3_SCEN); 2491:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2492:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2493:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2494:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Perform basic configuration of USART for enabling use in Irda Mode 2495:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note In IRDA mode, the following bits must be kept cleared: 2496:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - LINEN bit in the USART_CR2 register, 2497:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - STOP and CLKEN bits in the USART_CR2 register, 2498:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - SCEN bit in the USART_CR3 register, 2499:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - HDSEL bit in the USART_CR3 register. 2500:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * This function also sets the UART/USART in IRDA mode (IREN bit). 2501:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not 2502:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * IrDA feature is supported by the USARTx instance. 2503:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Call of this function is equivalent to following function call sequence : 2504:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function 2505:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function 2506:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function 2507:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function 2508:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Configure STOP in CR2 using @ref LL_USART_SetStopBitsLength() function 2509:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Set IREN in CR3 using @ref LL_USART_EnableIrda() function 2510:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Other remaining configurations items related to Irda Mode 2511:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * (as Baud Rate, Word length, Power mode, ...) should be set using 2512:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * dedicated functions 2513:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 LINEN LL_USART_ConfigIrdaMode\n 2514:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR2 CLKEN LL_USART_ConfigIrdaMode\n 2515:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR2 STOP LL_USART_ConfigIrdaMode\n 2516:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR3 SCEN LL_USART_ConfigIrdaMode\n 2517:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR3 HDSEL LL_USART_ConfigIrdaMode\n 2518:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR3 IREN LL_USART_ConfigIrdaMode 2519:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2520:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 2521:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2522:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_ConfigIrdaMode(USART_TypeDef *USARTx) 2523:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2524:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* In IRDA mode, the following bits must be kept cleared: 2525:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** - LINEN, STOP and CLKEN bits in the USART_CR2 register, 2526:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** - SCEN and HDSEL bits in the USART_CR3 register. 2527:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2528:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN | USART_CR2_STOP)); 2529:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL)); 2530:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* set the UART/USART in IRDA mode */ 2531:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** SET_BIT(USARTx->CR3, USART_CR3_IREN); 2532:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2533:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2534:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2535:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Perform basic configuration of USART for enabling use in Multi processor Mode 2536:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * (several USARTs connected in a network, one of the USARTs can be the master, 2537:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * its TX output connected to the RX inputs of the other slaves USARTs). 2538:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note In MultiProcessor mode, the following bits must be kept cleared: 2539:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - LINEN bit in the USART_CR2 register, 2540:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - CLKEN bit in the USART_CR2 register, 2541:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - SCEN bit in the USART_CR3 register, 2542:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - IREN bit in the USART_CR3 register, 2543:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - HDSEL bit in the USART_CR3 register. 2544:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Call of this function is equivalent to following function call sequence : 2545:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function ARM GAS /tmp/ccqopZd5.s page 380 2546:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function 2547:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function 2548:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function 2549:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function 2550:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Other remaining configurations items related to Multi processor Mode 2551:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * (as Baud Rate, Wake Up Method, Node address, ...) should be set using 2552:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * dedicated functions 2553:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 LINEN LL_USART_ConfigMultiProcessMode\n 2554:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR2 CLKEN LL_USART_ConfigMultiProcessMode\n 2555:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR3 SCEN LL_USART_ConfigMultiProcessMode\n 2556:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR3 HDSEL LL_USART_ConfigMultiProcessMode\n 2557:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR3 IREN LL_USART_ConfigMultiProcessMode 2558:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2559:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 2560:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2561:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_ConfigMultiProcessMode(USART_TypeDef *USARTx) 2562:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2563:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* In Multi Processor mode, the following bits must be kept cleared: 2564:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** - LINEN and CLKEN bits in the USART_CR2 register, 2565:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** - IREN, SCEN and HDSEL bits in the USART_CR3 register. 2566:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2567:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); 2568:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN)); 2569:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2570:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2571:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2572:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} 2573:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2574:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2575:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EF_FLAG_Management FLAG_Management 2576:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ 2577:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2578:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2579:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2580:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if the USART Parity Error Flag is set or not 2581:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll ISR PE LL_USART_IsActiveFlag_PE 2582:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2583:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). 2584:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2585:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_PE(const USART_TypeDef *USARTx) 2586:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2587:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->ISR, USART_ISR_PE) == (USART_ISR_PE)) ? 1UL : 0UL); 2588:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2589:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2590:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2591:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if the USART Framing Error Flag is set or not 2592:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll ISR FE LL_USART_IsActiveFlag_FE 2593:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2594:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). 2595:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2596:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_FE(const USART_TypeDef *USARTx) 2597:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2598:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->ISR, USART_ISR_FE) == (USART_ISR_FE)) ? 1UL : 0UL); 2599:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2600:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2601:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2602:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if the USART Noise error detected Flag is set or not ARM GAS /tmp/ccqopZd5.s page 381 2603:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll ISR NE LL_USART_IsActiveFlag_NE 2604:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2605:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). 2606:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2607:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_NE(const USART_TypeDef *USARTx) 2608:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2609:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->ISR, USART_ISR_NE) == (USART_ISR_NE)) ? 1UL : 0UL); 2610:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2611:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2612:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2613:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if the USART OverRun Error Flag is set or not 2614:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll ISR ORE LL_USART_IsActiveFlag_ORE 2615:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2616:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). 2617:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2618:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ORE(const USART_TypeDef *USARTx) 2619:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2620:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->ISR, USART_ISR_ORE) == (USART_ISR_ORE)) ? 1UL : 0UL); 2621:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2622:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2623:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2624:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if the USART IDLE line detected Flag is set or not 2625:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll ISR IDLE LL_USART_IsActiveFlag_IDLE 2626:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2627:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). 2628:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2629:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_IDLE(const USART_TypeDef *USARTx) 2630:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2631:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->ISR, USART_ISR_IDLE) == (USART_ISR_IDLE)) ? 1UL : 0UL); 2632:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2633:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2634:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2635:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if the USART Read Data Register Not Empty Flag is set or not 2636:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll ISR RXNE LL_USART_IsActiveFlag_RXNE 2637:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2638:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). 2639:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2640:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXNE(const USART_TypeDef *USARTx) 2641:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2642:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->ISR, USART_ISR_RXNE) == (USART_ISR_RXNE)) ? 1UL : 0UL); 2643:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2644:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2645:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2646:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if the USART Transmission Complete Flag is set or not 2647:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll ISR TC LL_USART_IsActiveFlag_TC 2648:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2649:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). 2650:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2651:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TC(const USART_TypeDef *USARTx) 2652:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2653:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->ISR, USART_ISR_TC) == (USART_ISR_TC)) ? 1UL : 0UL); 2654:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2655:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2656:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2657:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if the USART Transmit Data Register Empty Flag is set or not 2658:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll ISR TXE LL_USART_IsActiveFlag_TXE 2659:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance ARM GAS /tmp/ccqopZd5.s page 382 2660:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). 2661:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2662:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXE(const USART_TypeDef *USARTx) 2663:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2664:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->ISR, USART_ISR_TXE) == (USART_ISR_TXE)) ? 1UL : 0UL); 2665:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2666:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2667:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2668:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if the USART LIN Break Detection Flag is set or not 2669:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not 2670:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * LIN feature is supported by the USARTx instance. 2671:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll ISR LBDF LL_USART_IsActiveFlag_LBD 2672:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2673:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). 2674:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2675:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_LBD(const USART_TypeDef *USARTx) 2676:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2677:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->ISR, USART_ISR_LBDF) == (USART_ISR_LBDF)) ? 1UL : 0UL); 2678:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2679:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2680:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2681:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if the USART CTS interrupt Flag is set or not 2682:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not 2683:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Hardware Flow control feature is supported by the USARTx instance. 2684:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll ISR CTSIF LL_USART_IsActiveFlag_nCTS 2685:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2686:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). 2687:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2688:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_nCTS(const USART_TypeDef *USARTx) 2689:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2690:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->ISR, USART_ISR_CTSIF) == (USART_ISR_CTSIF)) ? 1UL : 0UL); 2691:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2692:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2693:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2694:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if the USART CTS Flag is set or not 2695:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not 2696:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Hardware Flow control feature is supported by the USARTx instance. 2697:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll ISR CTS LL_USART_IsActiveFlag_CTS 2698:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2699:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). 2700:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2701:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_CTS(const USART_TypeDef *USARTx) 2702:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2703:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->ISR, USART_ISR_CTS) == (USART_ISR_CTS)) ? 1UL : 0UL); 2704:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2705:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2706:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2707:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if the USART Receiver Time Out Flag is set or not 2708:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll ISR RTOF LL_USART_IsActiveFlag_RTO 2709:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2710:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). 2711:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2712:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RTO(const USART_TypeDef *USARTx) 2713:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2714:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->ISR, USART_ISR_RTOF) == (USART_ISR_RTOF)) ? 1UL : 0UL); 2715:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2716:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ARM GAS /tmp/ccqopZd5.s page 383 2717:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2718:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if the USART End Of Block Flag is set or not 2719:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not 2720:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Smartcard feature is supported by the USARTx instance. 2721:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll ISR EOBF LL_USART_IsActiveFlag_EOB 2722:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2723:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). 2724:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2725:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_EOB(const USART_TypeDef *USARTx) 2726:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2727:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->ISR, USART_ISR_EOBF) == (USART_ISR_EOBF)) ? 1UL : 0UL); 2728:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2729:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2730:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2731:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if the USART Auto-Baud Rate Error Flag is set or not 2732:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or 2733:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Auto Baud Rate detection feature is supported by the USARTx instance. 2734:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll ISR ABRE LL_USART_IsActiveFlag_ABRE 2735:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2736:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). 2737:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2738:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ABRE(const USART_TypeDef *USARTx) 2739:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2740:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->ISR, USART_ISR_ABRE) == (USART_ISR_ABRE)) ? 1UL : 0UL); 2741:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2742:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2743:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2744:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if the USART Auto-Baud Rate Flag is set or not 2745:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or 2746:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Auto Baud Rate detection feature is supported by the USARTx instance. 2747:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll ISR ABRF LL_USART_IsActiveFlag_ABR 2748:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2749:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). 2750:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2751:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ABR(const USART_TypeDef *USARTx) 2752:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2753:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->ISR, USART_ISR_ABRF) == (USART_ISR_ABRF)) ? 1UL : 0UL); 2754:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2755:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2756:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2757:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if the USART Busy Flag is set or not 2758:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll ISR BUSY LL_USART_IsActiveFlag_BUSY 2759:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2760:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). 2761:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2762:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_BUSY(const USART_TypeDef *USARTx) 2763:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2764:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->ISR, USART_ISR_BUSY) == (USART_ISR_BUSY)) ? 1UL : 0UL); 2765:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2766:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2767:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2768:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if the USART Character Match Flag is set or not 2769:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll ISR CMF LL_USART_IsActiveFlag_CM 2770:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2771:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). 2772:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2773:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_CM(const USART_TypeDef *USARTx) ARM GAS /tmp/ccqopZd5.s page 384 2774:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2775:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->ISR, USART_ISR_CMF) == (USART_ISR_CMF)) ? 1UL : 0UL); 2776:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2777:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2778:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2779:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if the USART Send Break Flag is set or not 2780:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll ISR SBKF LL_USART_IsActiveFlag_SBK 2781:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2782:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). 2783:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2784:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_SBK(const USART_TypeDef *USARTx) 2785:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2786:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->ISR, USART_ISR_SBKF) == (USART_ISR_SBKF)) ? 1UL : 0UL); 2787:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2788:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2789:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2790:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if the USART Receive Wake Up from mute mode Flag is set or not 2791:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll ISR RWU LL_USART_IsActiveFlag_RWU 2792:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2793:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). 2794:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2795:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RWU(const USART_TypeDef *USARTx) 2796:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2797:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->ISR, USART_ISR_RWU) == (USART_ISR_RWU)) ? 1UL : 0UL); 2798:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2799:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2800:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_CR1_UESM) 2801:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_CR3_WUFIE) 2802:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2803:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if the USART Wake Up from stop mode Flag is set or not 2804:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not 2805:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Wake-up from Stop mode feature is supported by the USARTx instance. 2806:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll ISR WUF LL_USART_IsActiveFlag_WKUP 2807:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2808:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). 2809:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2810:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_WKUP(const USART_TypeDef *USARTx) 2811:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2812:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->ISR, USART_ISR_WUF) == (USART_ISR_WUF)) ? 1UL : 0UL); 2813:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2814:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2815:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_CR3_WUFIE */ 2816:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_CR1_UESM */ 2817:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2818:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if the USART Transmit Enable Acknowledge Flag is set or not 2819:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll ISR TEACK LL_USART_IsActiveFlag_TEACK 2820:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2821:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). 2822:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2823:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TEACK(const USART_TypeDef *USARTx) 2824:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2825:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->ISR, USART_ISR_TEACK) == (USART_ISR_TEACK)) ? 1UL : 0UL); 2826:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2827:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2828:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_ISR_REACK) 2829:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2830:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if the USART Receive Enable Acknowledge Flag is set or not ARM GAS /tmp/ccqopZd5.s page 385 2831:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll ISR REACK LL_USART_IsActiveFlag_REACK 2832:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2833:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). 2834:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2835:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_REACK(const USART_TypeDef *USARTx) 2836:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2837:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->ISR, USART_ISR_REACK) == (USART_ISR_REACK)) ? 1UL : 0UL); 2838:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2839:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2840:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_ISR_REACK */ 2841:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_TCBGT_SUPPORT) 2842:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* Function available only on devices supporting Transmit Complete before Guard Time feature */ 2843:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2844:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if the Smartcard Transmission Complete Before Guard Time Flag is set or not 2845:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll ISR TCBGT LL_USART_IsActiveFlag_TCBGT 2846:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2847:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). 2848:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2849:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TCBGT(const USART_TypeDef *USARTx) 2850:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2851:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->ISR, USART_ISR_TCBGT) == (USART_ISR_TCBGT)) ? 1UL : 0UL); 2852:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2853:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2854:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_TCBGT_SUPPORT */ 2855:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2856:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Clear Parity Error Flag 2857:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll ICR PECF LL_USART_ClearFlag_PE 2858:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2859:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 2860:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2861:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_ClearFlag_PE(USART_TypeDef *USARTx) 2862:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2863:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** WRITE_REG(USARTx->ICR, USART_ICR_PECF); 2864:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2865:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2866:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2867:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Clear Framing Error Flag 2868:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll ICR FECF LL_USART_ClearFlag_FE 2869:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2870:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 2871:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2872:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_ClearFlag_FE(USART_TypeDef *USARTx) 2873:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2874:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** WRITE_REG(USARTx->ICR, USART_ICR_FECF); 2875:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2876:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2877:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2878:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Clear Noise Error detected Flag 2879:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll ICR NCF LL_USART_ClearFlag_NE 2880:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2881:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 2882:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2883:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_ClearFlag_NE(USART_TypeDef *USARTx) 2884:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2885:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** WRITE_REG(USARTx->ICR, USART_ICR_NCF); 2886:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2887:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ARM GAS /tmp/ccqopZd5.s page 386 2888:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2889:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Clear OverRun Error Flag 2890:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll ICR ORECF LL_USART_ClearFlag_ORE 2891:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2892:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 2893:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2894:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_ClearFlag_ORE(USART_TypeDef *USARTx) 2895:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2896:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** WRITE_REG(USARTx->ICR, USART_ICR_ORECF); 2897:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2898:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2899:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2900:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Clear IDLE line detected Flag 2901:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll ICR IDLECF LL_USART_ClearFlag_IDLE 2902:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2903:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 2904:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2905:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_ClearFlag_IDLE(USART_TypeDef *USARTx) 2906:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** WRITE_REG(USARTx->ICR, USART_ICR_IDLECF); 2908:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2909:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2910:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2911:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Clear Transmission Complete Flag 2912:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll ICR TCCF LL_USART_ClearFlag_TC 2913:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2914:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 2915:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2916:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_ClearFlag_TC(USART_TypeDef *USARTx) 2917:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** WRITE_REG(USARTx->ICR, USART_ICR_TCCF); 2919:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2920:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2921:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_TCBGT_SUPPORT) 2922:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* Function available only on devices supporting Transmit Complete before Guard Time feature */ 2923:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2924:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Clear Smartcard Transmission Complete Before Guard Time Flag 2925:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll ICR TCBGTCF LL_USART_ClearFlag_TCBGT 2926:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2927:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 2928:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2929:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_ClearFlag_TCBGT(USART_TypeDef *USARTx) 2930:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2931:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** WRITE_REG(USARTx->ICR, USART_ICR_TCBGTCF); 2932:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2933:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_TCBGT_SUPPORT */ 2934:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2935:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2936:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Clear LIN Break Detection Flag 2937:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not 2938:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * LIN feature is supported by the USARTx instance. 2939:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll ICR LBDCF LL_USART_ClearFlag_LBD 2940:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2941:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 2942:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2943:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_ClearFlag_LBD(USART_TypeDef *USARTx) 2944:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { ARM GAS /tmp/ccqopZd5.s page 387 2945:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** WRITE_REG(USARTx->ICR, USART_ICR_LBDCF); 2946:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2947:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2948:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2949:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Clear CTS Interrupt Flag 2950:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not 2951:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Hardware Flow control feature is supported by the USARTx instance. 2952:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll ICR CTSCF LL_USART_ClearFlag_nCTS 2953:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2954:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 2955:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2956:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_ClearFlag_nCTS(USART_TypeDef *USARTx) 2957:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2958:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** WRITE_REG(USARTx->ICR, USART_ICR_CTSCF); 2959:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2960:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2961:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2962:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Clear Receiver Time Out Flag 2963:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll ICR RTOCF LL_USART_ClearFlag_RTO 2964:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2965:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 2966:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2967:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_ClearFlag_RTO(USART_TypeDef *USARTx) 2968:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2969:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** WRITE_REG(USARTx->ICR, USART_ICR_RTOCF); 2970:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2971:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2972:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2973:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Clear End Of Block Flag 2974:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not 2975:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Smartcard feature is supported by the USARTx instance. 2976:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll ICR EOBCF LL_USART_ClearFlag_EOB 2977:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2978:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 2979:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2980:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_ClearFlag_EOB(USART_TypeDef *USARTx) 2981:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2982:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** WRITE_REG(USARTx->ICR, USART_ICR_EOBCF); 2983:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2984:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2985:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2986:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Clear Character Match Flag 2987:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll ICR CMCF LL_USART_ClearFlag_CM 2988:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2989:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 2990:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2991:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_ClearFlag_CM(USART_TypeDef *USARTx) 2992:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2993:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** WRITE_REG(USARTx->ICR, USART_ICR_CMCF); 2994:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2995:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2996:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_CR1_UESM) 2997:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_CR3_WUFIE) 2998:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2999:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Clear Wake Up from stop mode Flag 3000:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not 3001:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Wake-up from Stop mode feature is supported by the USARTx instance. ARM GAS /tmp/ccqopZd5.s page 388 3002:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll ICR WUCF LL_USART_ClearFlag_WKUP 3003:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 3004:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 3005:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3006:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_ClearFlag_WKUP(USART_TypeDef *USARTx) 3007:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 3008:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** WRITE_REG(USARTx->ICR, USART_ICR_WUCF); 3009:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 3010:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3011:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_CR3_WUFIE */ 3012:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_CR1_UESM */ 3013:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 3014:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} 3015:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3016:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3017:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EF_IT_Management IT_Management 3018:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ 3019:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3020:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3021:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 3022:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Enable IDLE Interrupt 3023:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 IDLEIE LL_USART_EnableIT_IDLE 3024:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 3025:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 3026:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3027:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableIT_IDLE(USART_TypeDef *USARTx) 3028:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 3029:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_IDLEIE); 3030:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 3031:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3032:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 3033:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Enable RX Not Empty Interrupt 3034:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 RXNEIE LL_USART_EnableIT_RXNE 3035:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 3036:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 3037:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3038:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableIT_RXNE(USART_TypeDef *USARTx) 3039:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 3040:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_RXNEIE); 3041:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 3042:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3043:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 3044:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Enable Transmission Complete Interrupt 3045:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 TCIE LL_USART_EnableIT_TC 3046:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 3047:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 3048:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3049:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableIT_TC(USART_TypeDef *USARTx) 3050:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 3051:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_TCIE); 3052:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 3053:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3054:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 3055:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Enable TX Empty Interrupt 3056:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 TXEIE LL_USART_EnableIT_TXE 3057:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 3058:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None ARM GAS /tmp/ccqopZd5.s page 389 3059:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3060:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableIT_TXE(USART_TypeDef *USARTx) 3061:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 3062:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_TXEIE); 3063:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 3064:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3065:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 3066:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Enable Parity Error Interrupt 3067:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 PEIE LL_USART_EnableIT_PE 3068:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 3069:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 3070:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3071:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableIT_PE(USART_TypeDef *USARTx) 3072:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 3073:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_PEIE); 3074:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 3075:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3076:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 3077:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Enable Character Match Interrupt 3078:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 CMIE LL_USART_EnableIT_CM 3079:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 3080:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 3081:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3082:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableIT_CM(USART_TypeDef *USARTx) 3083:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 3084:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_CMIE); 3085:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 3086:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3087:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 3088:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Enable Receiver Timeout Interrupt 3089:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 RTOIE LL_USART_EnableIT_RTO 3090:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 3091:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 3092:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3093:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableIT_RTO(USART_TypeDef *USARTx) 3094:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 3095:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_RTOIE); 3096:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 3097:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3098:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 3099:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Enable End Of Block Interrupt 3100:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not 3101:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Smartcard feature is supported by the USARTx instance. 3102:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 EOBIE LL_USART_EnableIT_EOB 3103:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 3104:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 3105:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3106:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableIT_EOB(USART_TypeDef *USARTx) 3107:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 3108:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_EOBIE); 3109:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 3110:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3111:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 3112:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Enable LIN Break Detection Interrupt 3113:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not 3114:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * LIN feature is supported by the USARTx instance. 3115:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 LBDIE LL_USART_EnableIT_LBD ARM GAS /tmp/ccqopZd5.s page 390 3116:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 3117:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 3118:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3119:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableIT_LBD(USART_TypeDef *USARTx) 3120:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 3121:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** SET_BIT(USARTx->CR2, USART_CR2_LBDIE); 3122:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 3123:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3124:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 3125:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Enable Error Interrupt 3126:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a fram 3127:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the USARTx_ISR register). 3128:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * 0: Interrupt is inhibited 3129:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * 1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the USARTx_ISR register. 3130:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 EIE LL_USART_EnableIT_ERROR 3131:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 3132:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 3133:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3134:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableIT_ERROR(USART_TypeDef *USARTx) 3135:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 3136:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_EIE); 3137:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 3138:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3139:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 3140:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Enable CTS Interrupt 3141:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not 3142:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Hardware Flow control feature is supported by the USARTx instance. 3143:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 CTSIE LL_USART_EnableIT_CTS 3144:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 3145:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 3146:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3147:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableIT_CTS(USART_TypeDef *USARTx) 3148:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 3149:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_CTSIE); 3150:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 3151:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3152:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_CR1_UESM) 3153:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_CR3_WUFIE) 3154:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 3155:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Enable Wake Up from Stop Mode Interrupt 3156:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not 3157:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Wake-up from Stop mode feature is supported by the USARTx instance. 3158:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 WUFIE LL_USART_EnableIT_WKUP 3159:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 3160:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 3161:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3162:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableIT_WKUP(USART_TypeDef *USARTx) 3163:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 3164:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_WUFIE); 3165:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 3166:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3167:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_CR3_WUFIE */ 3168:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_CR1_UESM */ 3169:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_TCBGT_SUPPORT) 3170:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* Function available only on devices supporting Transmit Complete before Guard Time feature */ 3171:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 3172:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Enable Smartcard Transmission Complete Before Guard Time Interrupt ARM GAS /tmp/ccqopZd5.s page 391 3173:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not 3174:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Smartcard feature is supported by the USARTx instance. 3175:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 TCBGTIE LL_USART_EnableIT_TCBGT 3176:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 3177:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 3178:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3179:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableIT_TCBGT(USART_TypeDef *USARTx) 3180:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 3181:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_TCBGTIE); 3182:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 3183:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_TCBGT_SUPPORT */ 3184:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3185:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 3186:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Disable IDLE Interrupt 3187:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 IDLEIE LL_USART_DisableIT_IDLE 3188:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 3189:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 3190:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3191:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableIT_IDLE(USART_TypeDef *USARTx) 3192:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 3193:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_IDLEIE); 3194:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 3195:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3196:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 3197:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Disable RX Not Empty Interrupt 3198:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 RXNEIE LL_USART_DisableIT_RXNE 3199:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 3200:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 3201:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3202:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableIT_RXNE(USART_TypeDef *USARTx) 3203:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 3204:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_RXNEIE); 3205:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 3206:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3207:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 3208:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Disable Transmission Complete Interrupt 3209:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 TCIE LL_USART_DisableIT_TC 3210:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 3211:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 3212:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3213:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableIT_TC(USART_TypeDef *USARTx) 3214:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 3215:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_TCIE); 3216:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 3217:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3218:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 3219:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Disable TX Empty Interrupt 3220:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 TXEIE LL_USART_DisableIT_TXE 3221:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 3222:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 3223:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3224:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableIT_TXE(USART_TypeDef *USARTx) 3225:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 3226:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_TXEIE); 3227:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 3228:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3229:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** ARM GAS /tmp/ccqopZd5.s page 392 3230:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Disable Parity Error Interrupt 3231:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 PEIE LL_USART_DisableIT_PE 3232:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 3233:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 3234:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3235:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableIT_PE(USART_TypeDef *USARTx) 3236:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 3237:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_PEIE); 3238:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 3239:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3240:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 3241:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Disable Character Match Interrupt 3242:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 CMIE LL_USART_DisableIT_CM 3243:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 3244:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 3245:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3246:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableIT_CM(USART_TypeDef *USARTx) 3247:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 3248:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_CMIE); 3249:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 3250:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3251:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 3252:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Disable Receiver Timeout Interrupt 3253:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 RTOIE LL_USART_DisableIT_RTO 3254:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 3255:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 3256:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3257:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableIT_RTO(USART_TypeDef *USARTx) 3258:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 3259:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_RTOIE); 3260:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 3261:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3262:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 3263:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Disable End Of Block Interrupt 3264:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not 3265:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Smartcard feature is supported by the USARTx instance. 3266:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 EOBIE LL_USART_DisableIT_EOB 3267:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 3268:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 3269:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3270:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableIT_EOB(USART_TypeDef *USARTx) 3271:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 3272:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_EOBIE); 3273:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 3274:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3275:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 3276:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Disable LIN Break Detection Interrupt 3277:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not 3278:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * LIN feature is supported by the USARTx instance. 3279:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 LBDIE LL_USART_DisableIT_LBD 3280:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 3281:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 3282:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3283:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableIT_LBD(USART_TypeDef *USARTx) 3284:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 3285:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** CLEAR_BIT(USARTx->CR2, USART_CR2_LBDIE); 3286:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } ARM GAS /tmp/ccqopZd5.s page 393 3287:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3288:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 3289:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Disable Error Interrupt 3290:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a fram 3291:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the USARTx_ISR register). 3292:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * 0: Interrupt is inhibited 3293:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * 1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the USARTx_ISR register. 3294:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 EIE LL_USART_DisableIT_ERROR 3295:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 3296:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 3297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3298:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableIT_ERROR(USART_TypeDef *USARTx) 3299:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 3300:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_EIE); 3301:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 3302:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3303:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 3304:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Disable CTS Interrupt 3305:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not 3306:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Hardware Flow control feature is supported by the USARTx instance. 3307:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 CTSIE LL_USART_DisableIT_CTS 3308:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 3309:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 3310:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3311:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableIT_CTS(USART_TypeDef *USARTx) 3312:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 3313:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_CTSIE); 3314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 3315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3316:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_CR1_UESM) 3317:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_CR3_WUFIE) 3318:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 3319:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Disable Wake Up from Stop Mode Interrupt 3320:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not 3321:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Wake-up from Stop mode feature is supported by the USARTx instance. 3322:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 WUFIE LL_USART_DisableIT_WKUP 3323:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 3324:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 3325:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3326:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableIT_WKUP(USART_TypeDef *USARTx) 3327:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 3328:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_WUFIE); 3329:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 3330:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3331:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_CR3_WUFIE */ 3332:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_CR1_UESM */ 3333:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_TCBGT_SUPPORT) 3334:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* Function available only on devices supporting Transmit Complete before Guard Time feature */ 3335:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 3336:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Disable Smartcard Transmission Complete Before Guard Time Interrupt 3337:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not 3338:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Smartcard feature is supported by the USARTx instance. 3339:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 TCBGTIE LL_USART_DisableIT_TCBGT 3340:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 3341:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 3342:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3343:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableIT_TCBGT(USART_TypeDef *USARTx) ARM GAS /tmp/ccqopZd5.s page 394 3344:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 3345:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_TCBGTIE); 3346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 3347:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_TCBGT_SUPPORT */ 3348:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3349:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 3350:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if the USART IDLE Interrupt source is enabled or disabled. 3351:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 IDLEIE LL_USART_IsEnabledIT_IDLE 3352:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 3353:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). 3354:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3355:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_IDLE(const USART_TypeDef *USARTx) 3356:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 3357:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->CR1, USART_CR1_IDLEIE) == (USART_CR1_IDLEIE)) ? 1UL : 0UL); 3358:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 3359:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 3361:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if the USART RX Not Empty Interrupt is enabled or disabled. 3362:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 RXNEIE LL_USART_IsEnabledIT_RXNE 3363:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 3364:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). 3365:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3366:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXNE(const USART_TypeDef *USARTx) 3367:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 3368:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->CR1, USART_CR1_RXNEIE) == (USART_CR1_RXNEIE)) ? 1U : 0U); 3369:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 3370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3371:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 3372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if the USART Transmission Complete Interrupt is enabled or disabled. 3373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 TCIE LL_USART_IsEnabledIT_TC 3374:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 3375:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). 3376:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3377:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TC(const USART_TypeDef *USARTx) 3378:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 3379:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->CR1, USART_CR1_TCIE) == (USART_CR1_TCIE)) ? 1UL : 0UL); 3380:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 3381:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3382:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 3383:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if the USART TX Empty Interrupt is enabled or disabled. 3384:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 TXEIE LL_USART_IsEnabledIT_TXE 3385:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 3386:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). 3387:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3388:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXE(const USART_TypeDef *USARTx) 3389:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 3390:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->CR1, USART_CR1_TXEIE) == (USART_CR1_TXEIE)) ? 1U : 0U); 3391:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 3392:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3393:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 3394:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if the USART Parity Error Interrupt is enabled or disabled. 3395:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 PEIE LL_USART_IsEnabledIT_PE 3396:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 3397:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). 3398:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3399:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_PE(const USART_TypeDef *USARTx) 3400:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { ARM GAS /tmp/ccqopZd5.s page 395 3401:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->CR1, USART_CR1_PEIE) == (USART_CR1_PEIE)) ? 1UL : 0UL); 3402:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 3403:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3404:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 3405:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if the USART Character Match Interrupt is enabled or disabled. 3406:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 CMIE LL_USART_IsEnabledIT_CM 3407:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 3408:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). 3409:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3410:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_CM(const USART_TypeDef *USARTx) 3411:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 3412:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->CR1, USART_CR1_CMIE) == (USART_CR1_CMIE)) ? 1UL : 0UL); 3413:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 3414:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3415:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 3416:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if the USART Receiver Timeout Interrupt is enabled or disabled. 3417:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 RTOIE LL_USART_IsEnabledIT_RTO 3418:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 3419:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). 3420:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3421:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RTO(const USART_TypeDef *USARTx) 3422:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 3423:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->CR1, USART_CR1_RTOIE) == (USART_CR1_RTOIE)) ? 1UL : 0UL); 3424:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 3425:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3426:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 3427:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if the USART End Of Block Interrupt is enabled or disabled. 3428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not 3429:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Smartcard feature is supported by the USARTx instance. 3430:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 EOBIE LL_USART_IsEnabledIT_EOB 3431:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 3432:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). 3433:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3434:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_EOB(const USART_TypeDef *USARTx) 3435:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 3436:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->CR1, USART_CR1_EOBIE) == (USART_CR1_EOBIE)) ? 1UL : 0UL); 3437:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 3438:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3439:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 3440:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if the USART LIN Break Detection Interrupt is enabled or disabled. 3441:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not 3442:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * LIN feature is supported by the USARTx instance. 3443:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 LBDIE LL_USART_IsEnabledIT_LBD 3444:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 3445:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). 3446:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3447:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_LBD(const USART_TypeDef *USARTx) 3448:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 3449:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->CR2, USART_CR2_LBDIE) == (USART_CR2_LBDIE)) ? 1UL : 0UL); 3450:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 3451:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3452:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 3453:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if the USART Error Interrupt is enabled or disabled. 3454:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 EIE LL_USART_IsEnabledIT_ERROR 3455:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 3456:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). 3457:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ ARM GAS /tmp/ccqopZd5.s page 396 3458:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_ERROR(const USART_TypeDef *USARTx) 3459:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 3460:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->CR3, USART_CR3_EIE) == (USART_CR3_EIE)) ? 1UL : 0UL); 3461:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 3462:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 3464:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if the USART CTS Interrupt is enabled or disabled. 3465:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not 3466:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Hardware Flow control feature is supported by the USARTx instance. 3467:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 CTSIE LL_USART_IsEnabledIT_CTS 3468:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 3469:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). 3470:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3471:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_CTS(const USART_TypeDef *USARTx) 3472:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 3473:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->CR3, USART_CR3_CTSIE) == (USART_CR3_CTSIE)) ? 1UL : 0UL); 3474:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 3475:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3476:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_CR1_UESM) 3477:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_CR3_WUFIE) 3478:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 3479:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if the USART Wake Up from Stop Mode Interrupt is enabled or disabled. 3480:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not 3481:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Wake-up from Stop mode feature is supported by the USARTx instance. 3482:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 WUFIE LL_USART_IsEnabledIT_WKUP 3483:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 3484:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). 3485:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3486:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_WKUP(const USART_TypeDef *USARTx) 3487:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 3488:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->CR3, USART_CR3_WUFIE) == (USART_CR3_WUFIE)) ? 1UL : 0UL); 3489:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 3490:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3491:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_CR3_WUFIE */ 3492:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_CR1_UESM */ 3493:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_TCBGT_SUPPORT) 3494:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* Function available only on devices supporting Transmit Complete before Guard Time feature */ 3495:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 3496:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if the Smartcard Transmission Complete Before Guard Time Interrupt is enabled or 3497:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not 3498:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Smartcard feature is supported by the USARTx instance. 3499:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 TCBGTIE LL_USART_IsEnabledIT_TCBGT 3500:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 3501:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). 3502:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3503:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TCBGT(const USART_TypeDef *USARTx) 3504:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 3505:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->CR3, USART_CR3_TCBGTIE) == (USART_CR3_TCBGTIE)) ? 1UL : 0UL); 3506:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 3507:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_TCBGT_SUPPORT */ 3508:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3509:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 3510:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} 3511:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3512:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3513:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EF_DMA_Management DMA_Management 3514:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ ARM GAS /tmp/ccqopZd5.s page 397 3515:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3516:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3517:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 3518:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Enable DMA Mode for reception 3519:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 DMAR LL_USART_EnableDMAReq_RX 3520:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 3521:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 3522:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3523:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableDMAReq_RX(USART_TypeDef *USARTx) 3524:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 3525:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_DMAR); 3526:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 3527:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3528:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 3529:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Disable DMA Mode for reception 3530:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 DMAR LL_USART_DisableDMAReq_RX 3531:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 3532:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 3533:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3534:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableDMAReq_RX(USART_TypeDef *USARTx) 3535:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 3536:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_DMAR); 3537:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 3538:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3539:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 3540:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if DMA Mode is enabled for reception 3541:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 DMAR LL_USART_IsEnabledDMAReq_RX 3542:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 3543:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). 3544:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3545:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_RX(const USART_TypeDef *USARTx) 3546:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 3547:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->CR3, USART_CR3_DMAR) == (USART_CR3_DMAR)) ? 1UL : 0UL); 3548:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 3549:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3550:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 3551:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Enable DMA Mode for transmission 3552:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 DMAT LL_USART_EnableDMAReq_TX 3553:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 3554:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 3555:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3556:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableDMAReq_TX(USART_TypeDef *USARTx) 3557:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 3558:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_DMAT); 3993 .loc 7 3558 3 is_stmt 1 view .LVU1316 3994 .LBB449: 3995 .LBB450: 3996 .loc 7 3558 3 view .LVU1317 3997 .loc 7 3558 3 view .LVU1318 3998 .loc 7 3558 3 view .LVU1319 3999 00e8 764A ldr r2, .L142+76 4000 .LVL282: 4001 .LBB451: 4002 .LBI451: 4003 .file 8 "Drivers/CMSIS/Include/cmsis_gcc.h" 1:Drivers/CMSIS/Include/cmsis_gcc.h **** /**************************************************************************//** 2:Drivers/CMSIS/Include/cmsis_gcc.h **** * @file cmsis_gcc.h ARM GAS /tmp/ccqopZd5.s page 398 3:Drivers/CMSIS/Include/cmsis_gcc.h **** * @brief CMSIS compiler GCC header file 4:Drivers/CMSIS/Include/cmsis_gcc.h **** * @version V5.0.4 5:Drivers/CMSIS/Include/cmsis_gcc.h **** * @date 09. April 2018 6:Drivers/CMSIS/Include/cmsis_gcc.h **** ******************************************************************************/ 7:Drivers/CMSIS/Include/cmsis_gcc.h **** /* 8:Drivers/CMSIS/Include/cmsis_gcc.h **** * Copyright (c) 2009-2018 Arm Limited. All rights reserved. 9:Drivers/CMSIS/Include/cmsis_gcc.h **** * 10:Drivers/CMSIS/Include/cmsis_gcc.h **** * SPDX-License-Identifier: Apache-2.0 11:Drivers/CMSIS/Include/cmsis_gcc.h **** * 12:Drivers/CMSIS/Include/cmsis_gcc.h **** * Licensed under the Apache License, Version 2.0 (the License); you may 13:Drivers/CMSIS/Include/cmsis_gcc.h **** * not use this file except in compliance with the License. 14:Drivers/CMSIS/Include/cmsis_gcc.h **** * You may obtain a copy of the License at 15:Drivers/CMSIS/Include/cmsis_gcc.h **** * 16:Drivers/CMSIS/Include/cmsis_gcc.h **** * www.apache.org/licenses/LICENSE-2.0 17:Drivers/CMSIS/Include/cmsis_gcc.h **** * 18:Drivers/CMSIS/Include/cmsis_gcc.h **** * Unless required by applicable law or agreed to in writing, software 19:Drivers/CMSIS/Include/cmsis_gcc.h **** * distributed under the License is distributed on an AS IS BASIS, WITHOUT 20:Drivers/CMSIS/Include/cmsis_gcc.h **** * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 21:Drivers/CMSIS/Include/cmsis_gcc.h **** * See the License for the specific language governing permissions and 22:Drivers/CMSIS/Include/cmsis_gcc.h **** * limitations under the License. 23:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 24:Drivers/CMSIS/Include/cmsis_gcc.h **** 25:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __CMSIS_GCC_H 26:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_H 27:Drivers/CMSIS/Include/cmsis_gcc.h **** 28:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ignore some GCC warnings */ 29:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push 30:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wsign-conversion" 31:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wconversion" 32:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wunused-parameter" 33:Drivers/CMSIS/Include/cmsis_gcc.h **** 34:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Fallback for __has_builtin */ 35:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __has_builtin 36:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __has_builtin(x) (0) 37:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 38:Drivers/CMSIS/Include/cmsis_gcc.h **** 39:Drivers/CMSIS/Include/cmsis_gcc.h **** /* CMSIS compiler specific defines */ 40:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __ASM 41:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __ASM __asm 42:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 43:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __INLINE 44:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __INLINE inline 45:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 46:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __STATIC_INLINE 47:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __STATIC_INLINE static inline 48:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 49:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __STATIC_FORCEINLINE 50:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline 51:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 52:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __NO_RETURN 53:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __NO_RETURN __attribute__((__noreturn__)) 54:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 55:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __USED 56:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __USED __attribute__((used)) 57:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 58:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __WEAK 59:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __WEAK __attribute__((weak)) ARM GAS /tmp/ccqopZd5.s page 399 60:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 61:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PACKED 62:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PACKED __attribute__((packed, aligned(1))) 63:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 64:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PACKED_STRUCT 65:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) 66:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 67:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PACKED_UNION 68:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PACKED_UNION union __attribute__((packed, aligned(1))) 69:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 70:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT32 /* deprecated */ 71:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push 72:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" 73:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" 74:Drivers/CMSIS/Include/cmsis_gcc.h **** struct __attribute__((packed)) T_UINT32 { uint32_t v; }; 75:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop 76:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) 77:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 78:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT16_WRITE 79:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push 80:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" 81:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" 82:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; 83:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop 84:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))- 85:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 86:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT16_READ 87:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push 88:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" 89:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" 90:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; 91:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop 92:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(add 93:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 94:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT32_WRITE 95:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push 96:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" 97:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" 98:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; 99:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop 100:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))- 101:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 102:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT32_READ 103:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push 104:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" 105:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" 106:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; 107:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop 108:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(add 109:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 110:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __ALIGNED 111:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __ALIGNED(x) __attribute__((aligned(x))) 112:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 113:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __RESTRICT 114:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __RESTRICT __restrict 115:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 116:Drivers/CMSIS/Include/cmsis_gcc.h **** ARM GAS /tmp/ccqopZd5.s page 400 117:Drivers/CMSIS/Include/cmsis_gcc.h **** 118:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ########################### Core Function Access ########################### */ 119:Drivers/CMSIS/Include/cmsis_gcc.h **** /** \ingroup CMSIS_Core_FunctionInterface 120:Drivers/CMSIS/Include/cmsis_gcc.h **** \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions 121:Drivers/CMSIS/Include/cmsis_gcc.h **** @{ 122:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 123:Drivers/CMSIS/Include/cmsis_gcc.h **** 124:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 125:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Enable IRQ Interrupts 126:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Enables IRQ interrupts by clearing the I-bit in the CPSR. 127:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes. 128:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 129:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __enable_irq(void) 130:Drivers/CMSIS/Include/cmsis_gcc.h **** { 131:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsie i" : : : "memory"); 132:Drivers/CMSIS/Include/cmsis_gcc.h **** } 133:Drivers/CMSIS/Include/cmsis_gcc.h **** 134:Drivers/CMSIS/Include/cmsis_gcc.h **** 135:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 136:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Disable IRQ Interrupts 137:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Disables IRQ interrupts by setting the I-bit in the CPSR. 138:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes. 139:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 140:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __disable_irq(void) 141:Drivers/CMSIS/Include/cmsis_gcc.h **** { 142:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsid i" : : : "memory"); 143:Drivers/CMSIS/Include/cmsis_gcc.h **** } 144:Drivers/CMSIS/Include/cmsis_gcc.h **** 145:Drivers/CMSIS/Include/cmsis_gcc.h **** 146:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 147:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Control Register 148:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the Control Register. 149:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Control Register value 150:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 151:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_CONTROL(void) 152:Drivers/CMSIS/Include/cmsis_gcc.h **** { 153:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 154:Drivers/CMSIS/Include/cmsis_gcc.h **** 155:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, control" : "=r" (result) ); 156:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 157:Drivers/CMSIS/Include/cmsis_gcc.h **** } 158:Drivers/CMSIS/Include/cmsis_gcc.h **** 159:Drivers/CMSIS/Include/cmsis_gcc.h **** 160:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) 161:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 162:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Control Register (non-secure) 163:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the non-secure Control Register when in secure mode. 164:Drivers/CMSIS/Include/cmsis_gcc.h **** \return non-secure Control Register value 165:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 166:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) 167:Drivers/CMSIS/Include/cmsis_gcc.h **** { 168:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 169:Drivers/CMSIS/Include/cmsis_gcc.h **** 170:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); 171:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 172:Drivers/CMSIS/Include/cmsis_gcc.h **** } 173:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif ARM GAS /tmp/ccqopZd5.s page 401 174:Drivers/CMSIS/Include/cmsis_gcc.h **** 175:Drivers/CMSIS/Include/cmsis_gcc.h **** 176:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 177:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Control Register 178:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Writes the given value to the Control Register. 179:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] control Control Register value to set 180:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 181:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) 182:Drivers/CMSIS/Include/cmsis_gcc.h **** { 183:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); 184:Drivers/CMSIS/Include/cmsis_gcc.h **** } 185:Drivers/CMSIS/Include/cmsis_gcc.h **** 186:Drivers/CMSIS/Include/cmsis_gcc.h **** 187:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) 188:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 189:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Control Register (non-secure) 190:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Writes the given value to the non-secure Control Register when in secure state. 191:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] control Control Register value to set 192:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 193:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) 194:Drivers/CMSIS/Include/cmsis_gcc.h **** { 195:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); 196:Drivers/CMSIS/Include/cmsis_gcc.h **** } 197:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 198:Drivers/CMSIS/Include/cmsis_gcc.h **** 199:Drivers/CMSIS/Include/cmsis_gcc.h **** 200:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 201:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get IPSR Register 202:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the IPSR Register. 203:Drivers/CMSIS/Include/cmsis_gcc.h **** \return IPSR Register value 204:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 205:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_IPSR(void) 206:Drivers/CMSIS/Include/cmsis_gcc.h **** { 207:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 208:Drivers/CMSIS/Include/cmsis_gcc.h **** 209:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); 210:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 211:Drivers/CMSIS/Include/cmsis_gcc.h **** } 212:Drivers/CMSIS/Include/cmsis_gcc.h **** 213:Drivers/CMSIS/Include/cmsis_gcc.h **** 214:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 215:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get APSR Register 216:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the APSR Register. 217:Drivers/CMSIS/Include/cmsis_gcc.h **** \return APSR Register value 218:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 219:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_APSR(void) 220:Drivers/CMSIS/Include/cmsis_gcc.h **** { 221:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 222:Drivers/CMSIS/Include/cmsis_gcc.h **** 223:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, apsr" : "=r" (result) ); 224:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 225:Drivers/CMSIS/Include/cmsis_gcc.h **** } 226:Drivers/CMSIS/Include/cmsis_gcc.h **** 227:Drivers/CMSIS/Include/cmsis_gcc.h **** 228:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 229:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get xPSR Register 230:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the xPSR Register. ARM GAS /tmp/ccqopZd5.s page 402 231:Drivers/CMSIS/Include/cmsis_gcc.h **** \return xPSR Register value 232:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 233:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_xPSR(void) 234:Drivers/CMSIS/Include/cmsis_gcc.h **** { 235:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 236:Drivers/CMSIS/Include/cmsis_gcc.h **** 237:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); 238:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 239:Drivers/CMSIS/Include/cmsis_gcc.h **** } 240:Drivers/CMSIS/Include/cmsis_gcc.h **** 241:Drivers/CMSIS/Include/cmsis_gcc.h **** 242:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 243:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Process Stack Pointer 244:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Process Stack Pointer (PSP). 245:Drivers/CMSIS/Include/cmsis_gcc.h **** \return PSP Register value 246:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 247:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_PSP(void) 248:Drivers/CMSIS/Include/cmsis_gcc.h **** { 249:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 250:Drivers/CMSIS/Include/cmsis_gcc.h **** 251:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, psp" : "=r" (result) ); 252:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 253:Drivers/CMSIS/Include/cmsis_gcc.h **** } 254:Drivers/CMSIS/Include/cmsis_gcc.h **** 255:Drivers/CMSIS/Include/cmsis_gcc.h **** 256:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) 257:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 258:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Process Stack Pointer (non-secure) 259:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure s 260:Drivers/CMSIS/Include/cmsis_gcc.h **** \return PSP Register value 261:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 262:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) 263:Drivers/CMSIS/Include/cmsis_gcc.h **** { 264:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 265:Drivers/CMSIS/Include/cmsis_gcc.h **** 266:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); 267:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 268:Drivers/CMSIS/Include/cmsis_gcc.h **** } 269:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 270:Drivers/CMSIS/Include/cmsis_gcc.h **** 271:Drivers/CMSIS/Include/cmsis_gcc.h **** 272:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 273:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Process Stack Pointer 274:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Process Stack Pointer (PSP). 275:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfProcStack Process Stack Pointer value to set 276:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 277:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) 278:Drivers/CMSIS/Include/cmsis_gcc.h **** { 279:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); 280:Drivers/CMSIS/Include/cmsis_gcc.h **** } 281:Drivers/CMSIS/Include/cmsis_gcc.h **** 282:Drivers/CMSIS/Include/cmsis_gcc.h **** 283:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) 284:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 285:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Process Stack Pointer (non-secure) 286:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure sta 287:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfProcStack Process Stack Pointer value to set ARM GAS /tmp/ccqopZd5.s page 403 288:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 289:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) 290:Drivers/CMSIS/Include/cmsis_gcc.h **** { 291:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); 292:Drivers/CMSIS/Include/cmsis_gcc.h **** } 293:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 294:Drivers/CMSIS/Include/cmsis_gcc.h **** 295:Drivers/CMSIS/Include/cmsis_gcc.h **** 296:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 297:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Main Stack Pointer 298:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Main Stack Pointer (MSP). 299:Drivers/CMSIS/Include/cmsis_gcc.h **** \return MSP Register value 300:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 301:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_MSP(void) 302:Drivers/CMSIS/Include/cmsis_gcc.h **** { 303:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 304:Drivers/CMSIS/Include/cmsis_gcc.h **** 305:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, msp" : "=r" (result) ); 306:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 307:Drivers/CMSIS/Include/cmsis_gcc.h **** } 308:Drivers/CMSIS/Include/cmsis_gcc.h **** 309:Drivers/CMSIS/Include/cmsis_gcc.h **** 310:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) 311:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 312:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Main Stack Pointer (non-secure) 313:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure stat 314:Drivers/CMSIS/Include/cmsis_gcc.h **** \return MSP Register value 315:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 316:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) 317:Drivers/CMSIS/Include/cmsis_gcc.h **** { 318:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 319:Drivers/CMSIS/Include/cmsis_gcc.h **** 320:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); 321:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 322:Drivers/CMSIS/Include/cmsis_gcc.h **** } 323:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 324:Drivers/CMSIS/Include/cmsis_gcc.h **** 325:Drivers/CMSIS/Include/cmsis_gcc.h **** 326:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 327:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Main Stack Pointer 328:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Main Stack Pointer (MSP). 329:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfMainStack Main Stack Pointer value to set 330:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 331:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) 332:Drivers/CMSIS/Include/cmsis_gcc.h **** { 333:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); 334:Drivers/CMSIS/Include/cmsis_gcc.h **** } 335:Drivers/CMSIS/Include/cmsis_gcc.h **** 336:Drivers/CMSIS/Include/cmsis_gcc.h **** 337:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) 338:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 339:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Main Stack Pointer (non-secure) 340:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. 341:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfMainStack Main Stack Pointer value to set 342:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 343:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) 344:Drivers/CMSIS/Include/cmsis_gcc.h **** { ARM GAS /tmp/ccqopZd5.s page 404 345:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); 346:Drivers/CMSIS/Include/cmsis_gcc.h **** } 347:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 348:Drivers/CMSIS/Include/cmsis_gcc.h **** 349:Drivers/CMSIS/Include/cmsis_gcc.h **** 350:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) 351:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 352:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Stack Pointer (non-secure) 353:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. 354:Drivers/CMSIS/Include/cmsis_gcc.h **** \return SP Register value 355:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 356:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) 357:Drivers/CMSIS/Include/cmsis_gcc.h **** { 358:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 359:Drivers/CMSIS/Include/cmsis_gcc.h **** 360:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); 361:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 362:Drivers/CMSIS/Include/cmsis_gcc.h **** } 363:Drivers/CMSIS/Include/cmsis_gcc.h **** 364:Drivers/CMSIS/Include/cmsis_gcc.h **** 365:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 366:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Stack Pointer (non-secure) 367:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. 368:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfStack Stack Pointer value to set 369:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 370:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) 371:Drivers/CMSIS/Include/cmsis_gcc.h **** { 372:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); 373:Drivers/CMSIS/Include/cmsis_gcc.h **** } 374:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 375:Drivers/CMSIS/Include/cmsis_gcc.h **** 376:Drivers/CMSIS/Include/cmsis_gcc.h **** 377:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 378:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Priority Mask 379:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current state of the priority mask bit from the Priority Mask Register. 380:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Priority Mask value 381:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 382:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) 383:Drivers/CMSIS/Include/cmsis_gcc.h **** { 384:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 385:Drivers/CMSIS/Include/cmsis_gcc.h **** 386:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); 387:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 388:Drivers/CMSIS/Include/cmsis_gcc.h **** } 389:Drivers/CMSIS/Include/cmsis_gcc.h **** 390:Drivers/CMSIS/Include/cmsis_gcc.h **** 391:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) 392:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 393:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Priority Mask (non-secure) 394:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current state of the non-secure priority mask bit from the Priority Mask Reg 395:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Priority Mask value 396:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 397:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) 398:Drivers/CMSIS/Include/cmsis_gcc.h **** { 399:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 400:Drivers/CMSIS/Include/cmsis_gcc.h **** 401:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, primask_ns" : "=r" (result) :: "memory"); ARM GAS /tmp/ccqopZd5.s page 405 402:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 403:Drivers/CMSIS/Include/cmsis_gcc.h **** } 404:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 405:Drivers/CMSIS/Include/cmsis_gcc.h **** 406:Drivers/CMSIS/Include/cmsis_gcc.h **** 407:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 408:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Priority Mask 409:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Priority Mask Register. 410:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] priMask Priority Mask 411:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 412:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) 413:Drivers/CMSIS/Include/cmsis_gcc.h **** { 414:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); 415:Drivers/CMSIS/Include/cmsis_gcc.h **** } 416:Drivers/CMSIS/Include/cmsis_gcc.h **** 417:Drivers/CMSIS/Include/cmsis_gcc.h **** 418:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) 419:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 420:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Priority Mask (non-secure) 421:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Priority Mask Register when in secure state. 422:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] priMask Priority Mask 423:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 424:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) 425:Drivers/CMSIS/Include/cmsis_gcc.h **** { 426:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); 427:Drivers/CMSIS/Include/cmsis_gcc.h **** } 428:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 429:Drivers/CMSIS/Include/cmsis_gcc.h **** 430:Drivers/CMSIS/Include/cmsis_gcc.h **** 431:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ 432:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ 433:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) 434:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 435:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Enable FIQ 436:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Enables FIQ interrupts by clearing the F-bit in the CPSR. 437:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes. 438:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 439:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __enable_fault_irq(void) 440:Drivers/CMSIS/Include/cmsis_gcc.h **** { 441:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsie f" : : : "memory"); 442:Drivers/CMSIS/Include/cmsis_gcc.h **** } 443:Drivers/CMSIS/Include/cmsis_gcc.h **** 444:Drivers/CMSIS/Include/cmsis_gcc.h **** 445:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 446:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Disable FIQ 447:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Disables FIQ interrupts by setting the F-bit in the CPSR. 448:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes. 449:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 450:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __disable_fault_irq(void) 451:Drivers/CMSIS/Include/cmsis_gcc.h **** { 452:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsid f" : : : "memory"); 453:Drivers/CMSIS/Include/cmsis_gcc.h **** } 454:Drivers/CMSIS/Include/cmsis_gcc.h **** 455:Drivers/CMSIS/Include/cmsis_gcc.h **** 456:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 457:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Base Priority 458:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Base Priority register. ARM GAS /tmp/ccqopZd5.s page 406 459:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Base Priority register value 460:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 461:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) 462:Drivers/CMSIS/Include/cmsis_gcc.h **** { 463:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 464:Drivers/CMSIS/Include/cmsis_gcc.h **** 465:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, basepri" : "=r" (result) ); 466:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 467:Drivers/CMSIS/Include/cmsis_gcc.h **** } 468:Drivers/CMSIS/Include/cmsis_gcc.h **** 469:Drivers/CMSIS/Include/cmsis_gcc.h **** 470:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) 471:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 472:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Base Priority (non-secure) 473:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Base Priority register when in secure state. 474:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Base Priority register value 475:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 476:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) 477:Drivers/CMSIS/Include/cmsis_gcc.h **** { 478:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 479:Drivers/CMSIS/Include/cmsis_gcc.h **** 480:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); 481:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 482:Drivers/CMSIS/Include/cmsis_gcc.h **** } 483:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 484:Drivers/CMSIS/Include/cmsis_gcc.h **** 485:Drivers/CMSIS/Include/cmsis_gcc.h **** 486:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 487:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Base Priority 488:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Base Priority register. 489:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] basePri Base Priority value to set 490:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 491:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) 492:Drivers/CMSIS/Include/cmsis_gcc.h **** { 493:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); 494:Drivers/CMSIS/Include/cmsis_gcc.h **** } 495:Drivers/CMSIS/Include/cmsis_gcc.h **** 496:Drivers/CMSIS/Include/cmsis_gcc.h **** 497:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) 498:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 499:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Base Priority (non-secure) 500:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Base Priority register when in secure state. 501:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] basePri Base Priority value to set 502:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 503:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) 504:Drivers/CMSIS/Include/cmsis_gcc.h **** { 505:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); 506:Drivers/CMSIS/Include/cmsis_gcc.h **** } 507:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 508:Drivers/CMSIS/Include/cmsis_gcc.h **** 509:Drivers/CMSIS/Include/cmsis_gcc.h **** 510:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 511:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Base Priority with condition 512:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Base Priority register only if BASEPRI masking is disable 513:Drivers/CMSIS/Include/cmsis_gcc.h **** or the new value increases the BASEPRI priority level. 514:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] basePri Base Priority value to set 515:Drivers/CMSIS/Include/cmsis_gcc.h **** */ ARM GAS /tmp/ccqopZd5.s page 407 516:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) 517:Drivers/CMSIS/Include/cmsis_gcc.h **** { 518:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); 519:Drivers/CMSIS/Include/cmsis_gcc.h **** } 520:Drivers/CMSIS/Include/cmsis_gcc.h **** 521:Drivers/CMSIS/Include/cmsis_gcc.h **** 522:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 523:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Fault Mask 524:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Fault Mask register. 525:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Fault Mask register value 526:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 527:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) 528:Drivers/CMSIS/Include/cmsis_gcc.h **** { 529:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 530:Drivers/CMSIS/Include/cmsis_gcc.h **** 531:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); 532:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 533:Drivers/CMSIS/Include/cmsis_gcc.h **** } 534:Drivers/CMSIS/Include/cmsis_gcc.h **** 535:Drivers/CMSIS/Include/cmsis_gcc.h **** 536:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) 537:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 538:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Fault Mask (non-secure) 539:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Fault Mask register when in secure state. 540:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Fault Mask register value 541:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 542:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) 543:Drivers/CMSIS/Include/cmsis_gcc.h **** { 544:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 545:Drivers/CMSIS/Include/cmsis_gcc.h **** 546:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); 547:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 548:Drivers/CMSIS/Include/cmsis_gcc.h **** } 549:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 550:Drivers/CMSIS/Include/cmsis_gcc.h **** 551:Drivers/CMSIS/Include/cmsis_gcc.h **** 552:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 553:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Fault Mask 554:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Fault Mask register. 555:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] faultMask Fault Mask value to set 556:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 557:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) 558:Drivers/CMSIS/Include/cmsis_gcc.h **** { 559:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); 560:Drivers/CMSIS/Include/cmsis_gcc.h **** } 561:Drivers/CMSIS/Include/cmsis_gcc.h **** 562:Drivers/CMSIS/Include/cmsis_gcc.h **** 563:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) 564:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 565:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Fault Mask (non-secure) 566:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Fault Mask register when in secure state. 567:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] faultMask Fault Mask value to set 568:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 569:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) 570:Drivers/CMSIS/Include/cmsis_gcc.h **** { 571:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); 572:Drivers/CMSIS/Include/cmsis_gcc.h **** } ARM GAS /tmp/ccqopZd5.s page 408 573:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 574:Drivers/CMSIS/Include/cmsis_gcc.h **** 575:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ 576:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ 577:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ 578:Drivers/CMSIS/Include/cmsis_gcc.h **** 579:Drivers/CMSIS/Include/cmsis_gcc.h **** 580:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ 581:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) 582:Drivers/CMSIS/Include/cmsis_gcc.h **** 583:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 584:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Process Stack Pointer Limit 585:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure 586:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence zero is returned always in non-secure 587:Drivers/CMSIS/Include/cmsis_gcc.h **** mode. 588:Drivers/CMSIS/Include/cmsis_gcc.h **** 589:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). 590:Drivers/CMSIS/Include/cmsis_gcc.h **** \return PSPLIM Register value 591:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 592:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) 593:Drivers/CMSIS/Include/cmsis_gcc.h **** { 594:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ 595:Drivers/CMSIS/Include/cmsis_gcc.h **** (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) 596:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure PSPLIM is RAZ/WI 597:Drivers/CMSIS/Include/cmsis_gcc.h **** return 0U; 598:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 599:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 600:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, psplim" : "=r" (result) ); 601:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; 602:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 603:Drivers/CMSIS/Include/cmsis_gcc.h **** } 604:Drivers/CMSIS/Include/cmsis_gcc.h **** 605:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) 606:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 607:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Process Stack Pointer Limit (non-secure) 608:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure 609:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence zero is returned always. 610:Drivers/CMSIS/Include/cmsis_gcc.h **** 611:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in 612:Drivers/CMSIS/Include/cmsis_gcc.h **** \return PSPLIM Register value 613:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 614:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) 615:Drivers/CMSIS/Include/cmsis_gcc.h **** { 616:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) 617:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure PSPLIM is RAZ/WI 618:Drivers/CMSIS/Include/cmsis_gcc.h **** return 0U; 619:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 620:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 621:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); 622:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; 623:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 624:Drivers/CMSIS/Include/cmsis_gcc.h **** } 625:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 626:Drivers/CMSIS/Include/cmsis_gcc.h **** 627:Drivers/CMSIS/Include/cmsis_gcc.h **** 628:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 629:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Process Stack Pointer Limit ARM GAS /tmp/ccqopZd5.s page 409 630:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure 631:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence the write is silently ignored in non-secure 632:Drivers/CMSIS/Include/cmsis_gcc.h **** mode. 633:Drivers/CMSIS/Include/cmsis_gcc.h **** 634:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). 635:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set 636:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 637:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) 638:Drivers/CMSIS/Include/cmsis_gcc.h **** { 639:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ 640:Drivers/CMSIS/Include/cmsis_gcc.h **** (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) 641:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure PSPLIM is RAZ/WI 642:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)ProcStackPtrLimit; 643:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 644:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); 645:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 646:Drivers/CMSIS/Include/cmsis_gcc.h **** } 647:Drivers/CMSIS/Include/cmsis_gcc.h **** 648:Drivers/CMSIS/Include/cmsis_gcc.h **** 649:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) 650:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 651:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Process Stack Pointer (non-secure) 652:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure 653:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence the write is silently ignored. 654:Drivers/CMSIS/Include/cmsis_gcc.h **** 655:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in s 656:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set 657:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 658:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) 659:Drivers/CMSIS/Include/cmsis_gcc.h **** { 660:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) 661:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure PSPLIM is RAZ/WI 662:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)ProcStackPtrLimit; 663:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 664:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); 665:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 666:Drivers/CMSIS/Include/cmsis_gcc.h **** } 667:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 668:Drivers/CMSIS/Include/cmsis_gcc.h **** 669:Drivers/CMSIS/Include/cmsis_gcc.h **** 670:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 671:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Main Stack Pointer Limit 672:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure 673:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence zero is returned always in non-secure 674:Drivers/CMSIS/Include/cmsis_gcc.h **** mode. 675:Drivers/CMSIS/Include/cmsis_gcc.h **** 676:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). 677:Drivers/CMSIS/Include/cmsis_gcc.h **** \return MSPLIM Register value 678:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 679:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) 680:Drivers/CMSIS/Include/cmsis_gcc.h **** { 681:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ 682:Drivers/CMSIS/Include/cmsis_gcc.h **** (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) 683:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure MSPLIM is RAZ/WI 684:Drivers/CMSIS/Include/cmsis_gcc.h **** return 0U; 685:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 686:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; ARM GAS /tmp/ccqopZd5.s page 410 687:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, msplim" : "=r" (result) ); 688:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; 689:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 690:Drivers/CMSIS/Include/cmsis_gcc.h **** } 691:Drivers/CMSIS/Include/cmsis_gcc.h **** 692:Drivers/CMSIS/Include/cmsis_gcc.h **** 693:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) 694:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 695:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Main Stack Pointer Limit (non-secure) 696:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure 697:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence zero is returned always. 698:Drivers/CMSIS/Include/cmsis_gcc.h **** 699:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in sec 700:Drivers/CMSIS/Include/cmsis_gcc.h **** \return MSPLIM Register value 701:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 702:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) 703:Drivers/CMSIS/Include/cmsis_gcc.h **** { 704:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) 705:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure MSPLIM is RAZ/WI 706:Drivers/CMSIS/Include/cmsis_gcc.h **** return 0U; 707:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 708:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 709:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); 710:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; 711:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 712:Drivers/CMSIS/Include/cmsis_gcc.h **** } 713:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 714:Drivers/CMSIS/Include/cmsis_gcc.h **** 715:Drivers/CMSIS/Include/cmsis_gcc.h **** 716:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 717:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Main Stack Pointer Limit 718:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure 719:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence the write is silently ignored in non-secure 720:Drivers/CMSIS/Include/cmsis_gcc.h **** mode. 721:Drivers/CMSIS/Include/cmsis_gcc.h **** 722:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). 723:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set 724:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 725:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) 726:Drivers/CMSIS/Include/cmsis_gcc.h **** { 727:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ 728:Drivers/CMSIS/Include/cmsis_gcc.h **** (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) 729:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure MSPLIM is RAZ/WI 730:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)MainStackPtrLimit; 731:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 732:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); 733:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 734:Drivers/CMSIS/Include/cmsis_gcc.h **** } 735:Drivers/CMSIS/Include/cmsis_gcc.h **** 736:Drivers/CMSIS/Include/cmsis_gcc.h **** 737:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) 738:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 739:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Main Stack Pointer Limit (non-secure) 740:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure 741:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence the write is silently ignored. 742:Drivers/CMSIS/Include/cmsis_gcc.h **** 743:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secu ARM GAS /tmp/ccqopZd5.s page 411 744:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] MainStackPtrLimit Main Stack Pointer value to set 745:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 746:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) 747:Drivers/CMSIS/Include/cmsis_gcc.h **** { 748:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) 749:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure MSPLIM is RAZ/WI 750:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)MainStackPtrLimit; 751:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 752:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); 753:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 754:Drivers/CMSIS/Include/cmsis_gcc.h **** } 755:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 756:Drivers/CMSIS/Include/cmsis_gcc.h **** 757:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ 758:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ 759:Drivers/CMSIS/Include/cmsis_gcc.h **** 760:Drivers/CMSIS/Include/cmsis_gcc.h **** 761:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 762:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get FPSCR 763:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Floating Point Status/Control register. 764:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Floating Point Status/Control register value 765:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 766:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_FPSCR(void) 767:Drivers/CMSIS/Include/cmsis_gcc.h **** { 768:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ 769:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) 770:Drivers/CMSIS/Include/cmsis_gcc.h **** #if __has_builtin(__builtin_arm_get_fpscr) 771:Drivers/CMSIS/Include/cmsis_gcc.h **** // Re-enable using built-in when GCC has been fixed 772:Drivers/CMSIS/Include/cmsis_gcc.h **** // || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) 773:Drivers/CMSIS/Include/cmsis_gcc.h **** /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ 774:Drivers/CMSIS/Include/cmsis_gcc.h **** return __builtin_arm_get_fpscr(); 775:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 776:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 777:Drivers/CMSIS/Include/cmsis_gcc.h **** 778:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); 779:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 780:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 781:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 782:Drivers/CMSIS/Include/cmsis_gcc.h **** return(0U); 783:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 784:Drivers/CMSIS/Include/cmsis_gcc.h **** } 785:Drivers/CMSIS/Include/cmsis_gcc.h **** 786:Drivers/CMSIS/Include/cmsis_gcc.h **** 787:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 788:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set FPSCR 789:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Floating Point Status/Control register. 790:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] fpscr Floating Point Status/Control value to set 791:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 792:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) 793:Drivers/CMSIS/Include/cmsis_gcc.h **** { 794:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ 795:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) 796:Drivers/CMSIS/Include/cmsis_gcc.h **** #if __has_builtin(__builtin_arm_set_fpscr) 797:Drivers/CMSIS/Include/cmsis_gcc.h **** // Re-enable using built-in when GCC has been fixed 798:Drivers/CMSIS/Include/cmsis_gcc.h **** // || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) 799:Drivers/CMSIS/Include/cmsis_gcc.h **** /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ 800:Drivers/CMSIS/Include/cmsis_gcc.h **** __builtin_arm_set_fpscr(fpscr); ARM GAS /tmp/ccqopZd5.s page 412 801:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 802:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory"); 803:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 804:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 805:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)fpscr; 806:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 807:Drivers/CMSIS/Include/cmsis_gcc.h **** } 808:Drivers/CMSIS/Include/cmsis_gcc.h **** 809:Drivers/CMSIS/Include/cmsis_gcc.h **** 810:Drivers/CMSIS/Include/cmsis_gcc.h **** /*@} end of CMSIS_Core_RegAccFunctions */ 811:Drivers/CMSIS/Include/cmsis_gcc.h **** 812:Drivers/CMSIS/Include/cmsis_gcc.h **** 813:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ########################## Core Instruction Access ######################### */ 814:Drivers/CMSIS/Include/cmsis_gcc.h **** /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface 815:Drivers/CMSIS/Include/cmsis_gcc.h **** Access to dedicated instructions 816:Drivers/CMSIS/Include/cmsis_gcc.h **** @{ 817:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 818:Drivers/CMSIS/Include/cmsis_gcc.h **** 819:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Define macros for porting to both thumb1 and thumb2. 820:Drivers/CMSIS/Include/cmsis_gcc.h **** * For thumb1, use low register (r0-r7), specified by constraint "l" 821:Drivers/CMSIS/Include/cmsis_gcc.h **** * Otherwise, use general registers, specified by constraint "r" */ 822:Drivers/CMSIS/Include/cmsis_gcc.h **** #if defined (__thumb__) && !defined (__thumb2__) 823:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_OUT_REG(r) "=l" (r) 824:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_RW_REG(r) "+l" (r) 825:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_USE_REG(r) "l" (r) 826:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 827:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_OUT_REG(r) "=r" (r) 828:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_RW_REG(r) "+r" (r) 829:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_USE_REG(r) "r" (r) 830:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 831:Drivers/CMSIS/Include/cmsis_gcc.h **** 832:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 833:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief No Operation 834:Drivers/CMSIS/Include/cmsis_gcc.h **** \details No Operation does nothing. This instruction can be used for code alignment purposes. 835:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 836:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __NOP() __ASM volatile ("nop") 837:Drivers/CMSIS/Include/cmsis_gcc.h **** 838:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 839:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Wait For Interrupt 840:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Wait For Interrupt is a hint instruction that suspends execution until one of a number o 841:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 842:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __WFI() __ASM volatile ("wfi") 843:Drivers/CMSIS/Include/cmsis_gcc.h **** 844:Drivers/CMSIS/Include/cmsis_gcc.h **** 845:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 846:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Wait For Event 847:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Wait For Event is a hint instruction that permits the processor to enter 848:Drivers/CMSIS/Include/cmsis_gcc.h **** a low-power state until one of a number of events occurs. 849:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 850:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __WFE() __ASM volatile ("wfe") 851:Drivers/CMSIS/Include/cmsis_gcc.h **** 852:Drivers/CMSIS/Include/cmsis_gcc.h **** 853:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 854:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Send Event 855:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. 856:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 857:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __SEV() __ASM volatile ("sev") ARM GAS /tmp/ccqopZd5.s page 413 858:Drivers/CMSIS/Include/cmsis_gcc.h **** 859:Drivers/CMSIS/Include/cmsis_gcc.h **** 860:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 861:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Instruction Synchronization Barrier 862:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Instruction Synchronization Barrier flushes the pipeline in the processor, 863:Drivers/CMSIS/Include/cmsis_gcc.h **** so that all instructions following the ISB are fetched from cache or memory, 864:Drivers/CMSIS/Include/cmsis_gcc.h **** after the instruction has been completed. 865:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 866:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __ISB(void) 867:Drivers/CMSIS/Include/cmsis_gcc.h **** { 868:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("isb 0xF":::"memory"); 869:Drivers/CMSIS/Include/cmsis_gcc.h **** } 870:Drivers/CMSIS/Include/cmsis_gcc.h **** 871:Drivers/CMSIS/Include/cmsis_gcc.h **** 872:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 873:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Data Synchronization Barrier 874:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Acts as a special kind of Data Memory Barrier. 875:Drivers/CMSIS/Include/cmsis_gcc.h **** It completes when all explicit memory accesses before this instruction complete. 876:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 877:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __DSB(void) 878:Drivers/CMSIS/Include/cmsis_gcc.h **** { 879:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("dsb 0xF":::"memory"); 880:Drivers/CMSIS/Include/cmsis_gcc.h **** } 881:Drivers/CMSIS/Include/cmsis_gcc.h **** 882:Drivers/CMSIS/Include/cmsis_gcc.h **** 883:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 884:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Data Memory Barrier 885:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Ensures the apparent order of the explicit memory operations before 886:Drivers/CMSIS/Include/cmsis_gcc.h **** and after the instruction, without ensuring their completion. 887:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 888:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __DMB(void) 889:Drivers/CMSIS/Include/cmsis_gcc.h **** { 890:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("dmb 0xF":::"memory"); 891:Drivers/CMSIS/Include/cmsis_gcc.h **** } 892:Drivers/CMSIS/Include/cmsis_gcc.h **** 893:Drivers/CMSIS/Include/cmsis_gcc.h **** 894:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 895:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Reverse byte order (32 bit) 896:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x785 897:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to reverse 898:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Reversed value 899:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 900:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __REV(uint32_t value) 901:Drivers/CMSIS/Include/cmsis_gcc.h **** { 902:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) 903:Drivers/CMSIS/Include/cmsis_gcc.h **** return __builtin_bswap32(value); 904:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 905:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 906:Drivers/CMSIS/Include/cmsis_gcc.h **** 907:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); 908:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; 909:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 910:Drivers/CMSIS/Include/cmsis_gcc.h **** } 911:Drivers/CMSIS/Include/cmsis_gcc.h **** 912:Drivers/CMSIS/Include/cmsis_gcc.h **** 913:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 914:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Reverse byte order (16 bit) ARM GAS /tmp/ccqopZd5.s page 414 915:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 916:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to reverse 917:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Reversed value 918:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 919:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __REV16(uint32_t value) 920:Drivers/CMSIS/Include/cmsis_gcc.h **** { 921:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 922:Drivers/CMSIS/Include/cmsis_gcc.h **** 923:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); 924:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; 925:Drivers/CMSIS/Include/cmsis_gcc.h **** } 926:Drivers/CMSIS/Include/cmsis_gcc.h **** 927:Drivers/CMSIS/Include/cmsis_gcc.h **** 928:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 929:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Reverse byte order (16 bit) 930:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For exam 931:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to reverse 932:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Reversed value 933:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 934:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE int16_t __REVSH(int16_t value) 935:Drivers/CMSIS/Include/cmsis_gcc.h **** { 936:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) 937:Drivers/CMSIS/Include/cmsis_gcc.h **** return (int16_t)__builtin_bswap16(value); 938:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 939:Drivers/CMSIS/Include/cmsis_gcc.h **** int16_t result; 940:Drivers/CMSIS/Include/cmsis_gcc.h **** 941:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); 942:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; 943:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 944:Drivers/CMSIS/Include/cmsis_gcc.h **** } 945:Drivers/CMSIS/Include/cmsis_gcc.h **** 946:Drivers/CMSIS/Include/cmsis_gcc.h **** 947:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 948:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Rotate Right in unsigned value (32 bit) 949:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Rotate Right (immediate) provides the value of the contents of a register rotated by a v 950:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] op1 Value to rotate 951:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] op2 Number of Bits to rotate 952:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Rotated value 953:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 954:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) 955:Drivers/CMSIS/Include/cmsis_gcc.h **** { 956:Drivers/CMSIS/Include/cmsis_gcc.h **** op2 %= 32U; 957:Drivers/CMSIS/Include/cmsis_gcc.h **** if (op2 == 0U) 958:Drivers/CMSIS/Include/cmsis_gcc.h **** { 959:Drivers/CMSIS/Include/cmsis_gcc.h **** return op1; 960:Drivers/CMSIS/Include/cmsis_gcc.h **** } 961:Drivers/CMSIS/Include/cmsis_gcc.h **** return (op1 >> op2) | (op1 << (32U - op2)); 962:Drivers/CMSIS/Include/cmsis_gcc.h **** } 963:Drivers/CMSIS/Include/cmsis_gcc.h **** 964:Drivers/CMSIS/Include/cmsis_gcc.h **** 965:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 966:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Breakpoint 967:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Causes the processor to enter Debug state. 968:Drivers/CMSIS/Include/cmsis_gcc.h **** Debug tools can use this to investigate system state when the instruction at a particula 969:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value is ignored by the processor. 970:Drivers/CMSIS/Include/cmsis_gcc.h **** If required, a debugger can use it to store additional information about the break 971:Drivers/CMSIS/Include/cmsis_gcc.h **** */ ARM GAS /tmp/ccqopZd5.s page 415 972:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __BKPT(value) __ASM volatile ("bkpt "#value) 973:Drivers/CMSIS/Include/cmsis_gcc.h **** 974:Drivers/CMSIS/Include/cmsis_gcc.h **** 975:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 976:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Reverse bit order of value 977:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Reverses the bit order of the given value. 978:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to reverse 979:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Reversed value 980:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 981:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value) 982:Drivers/CMSIS/Include/cmsis_gcc.h **** { 983:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 984:Drivers/CMSIS/Include/cmsis_gcc.h **** 985:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ 986:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ 987:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) 988:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 989:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 990:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ 991:Drivers/CMSIS/Include/cmsis_gcc.h **** 992:Drivers/CMSIS/Include/cmsis_gcc.h **** result = value; /* r will be reversed bits of v; first get LSB of v */ 993:Drivers/CMSIS/Include/cmsis_gcc.h **** for (value >>= 1U; value != 0U; value >>= 1U) 994:Drivers/CMSIS/Include/cmsis_gcc.h **** { 995:Drivers/CMSIS/Include/cmsis_gcc.h **** result <<= 1U; 996:Drivers/CMSIS/Include/cmsis_gcc.h **** result |= value & 1U; 997:Drivers/CMSIS/Include/cmsis_gcc.h **** s--; 998:Drivers/CMSIS/Include/cmsis_gcc.h **** } 999:Drivers/CMSIS/Include/cmsis_gcc.h **** result <<= s; /* shift when v's highest bits are zero */ 1000:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 1001:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; 1002:Drivers/CMSIS/Include/cmsis_gcc.h **** } 1003:Drivers/CMSIS/Include/cmsis_gcc.h **** 1004:Drivers/CMSIS/Include/cmsis_gcc.h **** 1005:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 1006:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Count leading zeros 1007:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Counts the number of leading zeros of a data value. 1008:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to count the leading zeros 1009:Drivers/CMSIS/Include/cmsis_gcc.h **** \return number of leading zeros in value 1010:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 1011:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CLZ (uint8_t)__builtin_clz 1012:Drivers/CMSIS/Include/cmsis_gcc.h **** 1013:Drivers/CMSIS/Include/cmsis_gcc.h **** 1014:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ 1015:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ 1016:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ 1017:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) 1018:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 1019:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief LDR Exclusive (8 bit) 1020:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Executes a exclusive LDR instruction for 8 bit value. 1021:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ptr Pointer to data 1022:Drivers/CMSIS/Include/cmsis_gcc.h **** \return value of type uint8_t at (*ptr) 1023:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 1024:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr) 1025:Drivers/CMSIS/Include/cmsis_gcc.h **** { 1026:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 1027:Drivers/CMSIS/Include/cmsis_gcc.h **** 1028:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) ARM GAS /tmp/ccqopZd5.s page 416 1029:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); 1030:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 1031:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not 1032:Drivers/CMSIS/Include/cmsis_gcc.h **** accepted by assembler. So has to use following less efficient pattern. 1033:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 1034:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); 1035:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 1036:Drivers/CMSIS/Include/cmsis_gcc.h **** return ((uint8_t) result); /* Add explicit type cast here */ 1037:Drivers/CMSIS/Include/cmsis_gcc.h **** } 1038:Drivers/CMSIS/Include/cmsis_gcc.h **** 1039:Drivers/CMSIS/Include/cmsis_gcc.h **** 1040:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 1041:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief LDR Exclusive (16 bit) 1042:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Executes a exclusive LDR instruction for 16 bit values. 1043:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ptr Pointer to data 1044:Drivers/CMSIS/Include/cmsis_gcc.h **** \return value of type uint16_t at (*ptr) 1045:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 1046:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr) 1047:Drivers/CMSIS/Include/cmsis_gcc.h **** { 1048:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 1049:Drivers/CMSIS/Include/cmsis_gcc.h **** 1050:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) 1051:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); 1052:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 1053:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not 1054:Drivers/CMSIS/Include/cmsis_gcc.h **** accepted by assembler. So has to use following less efficient pattern. 1055:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 1056:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); 1057:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 1058:Drivers/CMSIS/Include/cmsis_gcc.h **** return ((uint16_t) result); /* Add explicit type cast here */ 1059:Drivers/CMSIS/Include/cmsis_gcc.h **** } 1060:Drivers/CMSIS/Include/cmsis_gcc.h **** 1061:Drivers/CMSIS/Include/cmsis_gcc.h **** 1062:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 1063:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief LDR Exclusive (32 bit) 1064:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Executes a exclusive LDR instruction for 32 bit values. 1065:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ptr Pointer to data 1066:Drivers/CMSIS/Include/cmsis_gcc.h **** \return value of type uint32_t at (*ptr) 1067:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 1068:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr) 4004 .loc 8 1068 31 view .LVU1320 4005 .LBB452: 1069:Drivers/CMSIS/Include/cmsis_gcc.h **** { 1070:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 4006 .loc 8 1070 5 view .LVU1321 1071:Drivers/CMSIS/Include/cmsis_gcc.h **** 1072:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 4007 .loc 8 1072 4 view .LVU1322 4008 .syntax unified 4009 @ 1072 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 4010 00ea 52E8003F ldrex r3, [r2] 4011 @ 0 "" 2 4012 .LVL283: 1073:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 4013 .loc 8 1073 4 view .LVU1323 4014 .loc 8 1073 4 is_stmt 0 view .LVU1324 4015 .thumb ARM GAS /tmp/ccqopZd5.s page 417 4016 .syntax unified 4017 .LBE452: 4018 .LBE451: 4019 .loc 7 3558 3 view .LVU1325 4020 00ee 43F08003 orr r3, r3, #128 4021 .LVL284: 4022 .loc 7 3558 3 is_stmt 1 view .LVU1326 4023 .LBB453: 4024 .LBI453: 1074:Drivers/CMSIS/Include/cmsis_gcc.h **** } 1075:Drivers/CMSIS/Include/cmsis_gcc.h **** 1076:Drivers/CMSIS/Include/cmsis_gcc.h **** 1077:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 1078:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief STR Exclusive (8 bit) 1079:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Executes a exclusive STR instruction for 8 bit values. 1080:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to store 1081:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ptr Pointer to location 1082:Drivers/CMSIS/Include/cmsis_gcc.h **** \return 0 Function succeeded 1083:Drivers/CMSIS/Include/cmsis_gcc.h **** \return 1 Function failed 1084:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 1085:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) 1086:Drivers/CMSIS/Include/cmsis_gcc.h **** { 1087:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 1088:Drivers/CMSIS/Include/cmsis_gcc.h **** 1089:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); 1090:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 1091:Drivers/CMSIS/Include/cmsis_gcc.h **** } 1092:Drivers/CMSIS/Include/cmsis_gcc.h **** 1093:Drivers/CMSIS/Include/cmsis_gcc.h **** 1094:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 1095:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief STR Exclusive (16 bit) 1096:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Executes a exclusive STR instruction for 16 bit values. 1097:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to store 1098:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ptr Pointer to location 1099:Drivers/CMSIS/Include/cmsis_gcc.h **** \return 0 Function succeeded 1100:Drivers/CMSIS/Include/cmsis_gcc.h **** \return 1 Function failed 1101:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 1102:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) 1103:Drivers/CMSIS/Include/cmsis_gcc.h **** { 1104:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 1105:Drivers/CMSIS/Include/cmsis_gcc.h **** 1106:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); 1107:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 1108:Drivers/CMSIS/Include/cmsis_gcc.h **** } 1109:Drivers/CMSIS/Include/cmsis_gcc.h **** 1110:Drivers/CMSIS/Include/cmsis_gcc.h **** 1111:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 1112:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief STR Exclusive (32 bit) 1113:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Executes a exclusive STR instruction for 32 bit values. 1114:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to store 1115:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ptr Pointer to location 1116:Drivers/CMSIS/Include/cmsis_gcc.h **** \return 0 Function succeeded 1117:Drivers/CMSIS/Include/cmsis_gcc.h **** \return 1 Function failed 1118:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 1119:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) 4025 .loc 8 1119 31 view .LVU1327 4026 .LBB454: ARM GAS /tmp/ccqopZd5.s page 418 1120:Drivers/CMSIS/Include/cmsis_gcc.h **** { 1121:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 4027 .loc 8 1121 4 view .LVU1328 1122:Drivers/CMSIS/Include/cmsis_gcc.h **** 1123:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 4028 .loc 8 1123 4 view .LVU1329 4029 .syntax unified 4030 @ 1123 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 4031 00f2 42E80031 strex r1, r3, [r2] 4032 @ 0 "" 2 4033 .LVL285: 1124:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 4034 .loc 8 1124 4 view .LVU1330 4035 .loc 8 1124 4 is_stmt 0 view .LVU1331 4036 .thumb 4037 .syntax unified 4038 .LBE454: 4039 .LBE453: 4040 .loc 7 3558 3 view .LVU1332 4041 00f6 0029 cmp r1, #0 4042 00f8 F6D1 bne .L133 4043 .LBE450: 4044 .LBE449: 4045 .loc 7 3558 3 is_stmt 1 view .LVU1333 4046 .LVL286: 1811:Src/main.c **** LL_DMA_EnableIT_TE(DMA2, LL_DMA_STREAM_7); 4047 .loc 2 1811 3 view .LVU1334 4048 .LBB455: 4049 .LBI455: 2368:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 2369:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 2370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 2371:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Clear Stream 0 direct mode error flag. 2372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LIFCR CDMEIF0 LL_DMA_ClearFlag_DME0 2373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 2374:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 2375:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 2376:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_DME0(DMA_TypeDef *DMAx) 2377:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 2378:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CDMEIF0); 2379:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 2380:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 2381:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 2382:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Clear Stream 1 direct mode error flag. 2383:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LIFCR CDMEIF1 LL_DMA_ClearFlag_DME1 2384:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 2385:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 2386:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 2387:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_DME1(DMA_TypeDef *DMAx) 2388:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 2389:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CDMEIF1); 2390:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 2391:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 2392:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 2393:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Clear Stream 2 direct mode error flag. 2394:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LIFCR CDMEIF2 LL_DMA_ClearFlag_DME2 2395:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance ARM GAS /tmp/ccqopZd5.s page 419 2396:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 2397:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 2398:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_DME2(DMA_TypeDef *DMAx) 2399:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 2400:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CDMEIF2); 2401:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 2402:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 2403:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 2404:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Clear Stream 3 direct mode error flag. 2405:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LIFCR CDMEIF3 LL_DMA_ClearFlag_DME3 2406:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 2407:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 2408:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 2409:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_DME3(DMA_TypeDef *DMAx) 2410:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 2411:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CDMEIF3); 2412:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 2413:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 2414:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 2415:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Clear Stream 4 direct mode error flag. 2416:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HIFCR CDMEIF4 LL_DMA_ClearFlag_DME4 2417:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 2418:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 2419:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 2420:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_DME4(DMA_TypeDef *DMAx) 2421:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 2422:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CDMEIF4); 2423:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 2424:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 2425:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 2426:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Clear Stream 5 direct mode error flag. 2427:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HIFCR CDMEIF5 LL_DMA_ClearFlag_DME5 2428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 2429:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 2430:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 2431:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_DME5(DMA_TypeDef *DMAx) 2432:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 2433:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CDMEIF5); 2434:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 2435:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 2436:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 2437:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Clear Stream 6 direct mode error flag. 2438:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HIFCR CDMEIF6 LL_DMA_ClearFlag_DME6 2439:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 2440:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 2441:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 2442:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_DME6(DMA_TypeDef *DMAx) 2443:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 2444:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CDMEIF6); 2445:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 2446:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 2447:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 2448:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Clear Stream 7 direct mode error flag. 2449:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HIFCR CDMEIF7 LL_DMA_ClearFlag_DME7 2450:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 2451:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 2452:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ ARM GAS /tmp/ccqopZd5.s page 420 2453:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_DME7(DMA_TypeDef *DMAx) 2454:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 2455:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CDMEIF7); 2456:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 2457:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 2458:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 2459:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Clear Stream 0 FIFO error flag. 2460:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LIFCR CFEIF0 LL_DMA_ClearFlag_FE0 2461:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 2462:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 2463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 2464:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_FE0(DMA_TypeDef *DMAx) 2465:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 2466:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CFEIF0); 2467:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 2468:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 2469:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 2470:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Clear Stream 1 FIFO error flag. 2471:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LIFCR CFEIF1 LL_DMA_ClearFlag_FE1 2472:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 2473:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 2474:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 2475:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_FE1(DMA_TypeDef *DMAx) 2476:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 2477:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CFEIF1); 2478:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 2479:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 2480:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 2481:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Clear Stream 2 FIFO error flag. 2482:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LIFCR CFEIF2 LL_DMA_ClearFlag_FE2 2483:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 2484:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 2485:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 2486:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_FE2(DMA_TypeDef *DMAx) 2487:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 2488:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CFEIF2); 2489:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 2490:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 2491:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 2492:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Clear Stream 3 FIFO error flag. 2493:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LIFCR CFEIF3 LL_DMA_ClearFlag_FE3 2494:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 2495:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 2496:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 2497:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_FE3(DMA_TypeDef *DMAx) 2498:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 2499:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CFEIF3); 2500:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 2501:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 2502:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 2503:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Clear Stream 4 FIFO error flag. 2504:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HIFCR CFEIF4 LL_DMA_ClearFlag_FE4 2505:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 2506:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 2507:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 2508:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_FE4(DMA_TypeDef *DMAx) 2509:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { ARM GAS /tmp/ccqopZd5.s page 421 2510:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CFEIF4); 2511:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 2512:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 2513:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 2514:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Clear Stream 5 FIFO error flag. 2515:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HIFCR CFEIF5 LL_DMA_ClearFlag_FE5 2516:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 2517:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 2518:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 2519:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_FE5(DMA_TypeDef *DMAx) 2520:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 2521:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CFEIF5); 2522:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 2523:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 2524:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 2525:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Clear Stream 6 FIFO error flag. 2526:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HIFCR CFEIF6 LL_DMA_ClearFlag_FE6 2527:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 2528:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 2529:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 2530:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_FE6(DMA_TypeDef *DMAx) 2531:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 2532:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CFEIF6); 2533:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 2534:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 2535:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 2536:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Clear Stream 7 FIFO error flag. 2537:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HIFCR CFEIF7 LL_DMA_ClearFlag_FE7 2538:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 2539:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 2540:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 2541:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_FE7(DMA_TypeDef *DMAx) 2542:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 2543:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CFEIF7); 2544:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 2545:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 2546:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 2547:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @} 2548:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 2549:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 2550:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_EF_IT_Management IT_Management 2551:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @{ 2552:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 2553:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 2554:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 2555:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Enable Half transfer interrupt. 2556:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR HTIE LL_DMA_EnableIT_HT 2557:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 2558:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: 2559:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 2560:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 2561:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 2562:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 2563:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 2564:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 2565:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 2566:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 ARM GAS /tmp/ccqopZd5.s page 422 2567:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 2568:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 2569:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_EnableIT_HT(DMA_TypeDef *DMAx, uint32_t Stream) 2570:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 2571:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA 2572:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 2573:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 2574:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 2575:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Enable Transfer error interrupt. 2576:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR TEIE LL_DMA_EnableIT_TE 2577:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 2578:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: 2579:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 2580:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 2581:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 2582:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 2583:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 2584:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 2585:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 2586:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 2587:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 2588:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 2589:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_EnableIT_TE(DMA_TypeDef *DMAx, uint32_t Stream) 2590:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 2591:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA 2592:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 2593:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 2594:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 2595:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Enable Transfer complete interrupt. 2596:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR TCIE LL_DMA_EnableIT_TC 2597:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 2598:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: 2599:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 2600:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 2601:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 2602:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 2603:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 2604:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 2605:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 2606:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 2607:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 2608:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 2609:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_EnableIT_TC(DMA_TypeDef *DMAx, uint32_t Stream) 4050 .loc 6 2609 22 view .LVU1335 4051 .LBB456: 2610:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 2611:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA 4052 .loc 6 2611 3 view .LVU1336 4053 00fa 734B ldr r3, .L142+80 4054 00fc D3F8B820 ldr r2, [r3, #184] 4055 0100 42F01002 orr r2, r2, #16 4056 0104 C3F8B820 str r2, [r3, #184] 4057 .LVL287: 4058 .loc 6 2611 3 is_stmt 0 view .LVU1337 4059 .LBE456: 4060 .LBE455: 1812:Src/main.c **** LL_DMA_ClearFlag_TC7(DMA2); ARM GAS /tmp/ccqopZd5.s page 423 4061 .loc 2 1812 3 is_stmt 1 view .LVU1338 4062 .LBB457: 4063 .LBI457: 2589:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 4064 .loc 6 2589 22 view .LVU1339 4065 .LBB458: 2591:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 4066 .loc 6 2591 3 view .LVU1340 4067 0108 D3F8B820 ldr r2, [r3, #184] 4068 010c 42F00402 orr r2, r2, #4 4069 0110 C3F8B820 str r2, [r3, #184] 4070 .LVL288: 2591:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 4071 .loc 6 2591 3 is_stmt 0 view .LVU1341 4072 .LBE458: 4073 .LBE457: 1813:Src/main.c **** LL_DMA_ClearFlag_TE7(DMA2); 4074 .loc 2 1813 3 is_stmt 1 view .LVU1342 4075 .LBB459: 4076 .LBI459: 2277:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 4077 .loc 6 2277 22 view .LVU1343 4078 .LBB460: 2279:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 4079 .loc 6 2279 3 view .LVU1344 4080 0114 4FF00062 mov r2, #134217728 4081 0118 DA60 str r2, [r3, #12] 4082 .LVL289: 2279:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 4083 .loc 6 2279 3 is_stmt 0 view .LVU1345 4084 .LBE460: 4085 .LBE459: 1814:Src/main.c **** LL_DMA_ConfigAddresses(DMA2, LL_DMA_STREAM_7, (uint32_t)&UART_DATA, LL_USART_DMA_GetRegAddr(USART 4086 .loc 2 1814 3 is_stmt 1 view .LVU1346 4087 .LBB461: 4088 .LBI461: 2365:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 4089 .loc 6 2365 22 view .LVU1347 4090 .LBB462: 2367:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 4091 .loc 6 2367 3 view .LVU1348 4092 011a 4FF00072 mov r2, #33554432 4093 011e DA60 str r2, [r3, #12] 4094 .LVL290: 2367:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 4095 .loc 6 2367 3 is_stmt 0 view .LVU1349 4096 .LBE462: 4097 .LBE461: 1815:Src/main.c **** 4098 .loc 2 1815 3 is_stmt 1 view .LVU1350 4099 0120 6A49 ldr r1, .L142+84 4100 .LVL291: 4101 .LBB463: 4102 .LBI463: 3559:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 3560:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3561:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** ARM GAS /tmp/ccqopZd5.s page 424 3562:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Disable DMA Mode for transmission 3563:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 DMAT LL_USART_DisableDMAReq_TX 3564:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 3565:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 3566:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3567:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableDMAReq_TX(USART_TypeDef *USARTx) 3568:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 3569:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_DMAT); 3570:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 3571:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3572:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 3573:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if DMA Mode is enabled for transmission 3574:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 DMAT LL_USART_IsEnabledDMAReq_TX 3575:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 3576:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). 3577:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3578:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_TX(const USART_TypeDef *USARTx) 3579:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 3580:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->CR3, USART_CR3_DMAT) == (USART_CR3_DMAT)) ? 1UL : 0UL); 3581:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 3582:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3583:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 3584:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Enable DMA Disabling on Reception Error 3585:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 DDRE LL_USART_EnableDMADeactOnRxErr 3586:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 3587:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 3588:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3589:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableDMADeactOnRxErr(USART_TypeDef *USARTx) 3590:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 3591:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** SET_BIT(USARTx->CR3, USART_CR3_DDRE); 3592:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 3593:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3594:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 3595:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Disable DMA Disabling on Reception Error 3596:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 DDRE LL_USART_DisableDMADeactOnRxErr 3597:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 3598:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 3599:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3600:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableDMADeactOnRxErr(USART_TypeDef *USARTx) 3601:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 3602:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** CLEAR_BIT(USARTx->CR3, USART_CR3_DDRE); 3603:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 3604:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3605:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 3606:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Indicate if DMA Disabling on Reception Error is disabled 3607:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 DDRE LL_USART_IsEnabledDMADeactOnRxErr 3608:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 3609:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). 3610:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3611:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledDMADeactOnRxErr(const USART_TypeDef *USARTx) 3612:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 3613:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->CR3, USART_CR3_DDRE) == (USART_CR3_DDRE)) ? 1UL : 0UL); 3614:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 3615:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3616:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 3617:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Get the data register address used for DMA transfer 3618:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll RDR RDR LL_USART_DMA_GetRegAddr\n ARM GAS /tmp/ccqopZd5.s page 425 3619:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll TDR TDR LL_USART_DMA_GetRegAddr 3620:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 3621:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param Direction This parameter can be one of the following values: 3622:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_DMA_REG_DATA_TRANSMIT 3623:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_DMA_REG_DATA_RECEIVE 3624:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Address of data register 3625:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3626:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_DMA_GetRegAddr(const USART_TypeDef *USARTx, uint32_t Direction) 4103 .loc 7 3626 26 view .LVU1351 4104 .LBB464: 3627:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 3628:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** uint32_t data_reg_addr; 4105 .loc 7 3628 3 view .LVU1352 3629:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3630:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** if (Direction == LL_USART_DMA_REG_DATA_TRANSMIT) 4106 .loc 7 3630 3 view .LVU1353 3631:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 3632:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* return address of TDR register */ 3633:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** data_reg_addr = (uint32_t) &(USARTx->TDR); 4107 .loc 7 3633 5 view .LVU1354 4108 .loc 7 3633 32 is_stmt 0 view .LVU1355 4109 0122 6B4A ldr r2, .L142+88 4110 .LVL292: 3634:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 3635:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** else 3636:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 3637:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* return address of RDR register */ 3638:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** data_reg_addr = (uint32_t) &(USARTx->RDR); 3639:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 3640:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3641:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return data_reg_addr; 4111 .loc 7 3641 3 is_stmt 1 view .LVU1356 4112 .loc 7 3641 3 is_stmt 0 view .LVU1357 4113 .LBE464: 4114 .LBE463: 4115 .LBB465: 4116 .LBI465: 621:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 4117 .loc 6 621 26 is_stmt 1 view .LVU1358 4118 .LBB466: 623:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 4119 .loc 6 623 3 view .LVU1359 623:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 4120 .loc 6 623 11 is_stmt 0 view .LVU1360 4121 0124 D3F8B830 ldr r3, [r3, #184] 4122 0128 03F0C003 and r3, r3, #192 4123 .LVL293: 623:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 4124 .loc 6 623 11 view .LVU1361 4125 .LBE466: 4126 .LBE465: 4127 .LBB467: 4128 .LBI467: 1425:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 4129 .loc 6 1425 22 is_stmt 1 view .LVU1362 4130 .LBB468: 1428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { ARM GAS /tmp/ccqopZd5.s page 426 4131 .loc 6 1428 3 view .LVU1363 1428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 4132 .loc 6 1428 6 is_stmt 0 view .LVU1364 4133 012c 402B cmp r3, #64 4134 012e 7AD0 beq .L139 1436:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR 4135 .loc 6 1436 5 is_stmt 1 view .LVU1365 4136 0130 654B ldr r3, .L142+80 4137 .LVL294: 1436:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR 4138 .loc 6 1436 5 is_stmt 0 view .LVU1366 4139 0132 C3F8C010 str r1, [r3, #192] 1437:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 4140 .loc 6 1437 5 is_stmt 1 view .LVU1367 4141 0136 C3F8C420 str r2, [r3, #196] 4142 .L135: 4143 .LVL295: 1437:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 4144 .loc 6 1437 5 is_stmt 0 view .LVU1368 4145 .LBE468: 4146 .LBE467: 1820:Src/main.c **** SD_SLIDE = 0; 4147 .loc 2 1820 2 is_stmt 1 view .LVU1369 1820:Src/main.c **** SD_SLIDE = 0; 4148 .loc 2 1820 10 is_stmt 0 view .LVU1370 4149 013a 0024 movs r4, #0 4150 013c 654B ldr r3, .L142+92 4151 013e 1C60 str r4, [r3] 1821:Src/main.c **** //Reset all periphery 4152 .loc 2 1821 2 is_stmt 1 view .LVU1371 1821:Src/main.c **** //Reset all periphery 4153 .loc 2 1821 11 is_stmt 0 view .LVU1372 4154 0140 654B ldr r3, .L142+96 4155 0142 1C60 str r4, [r3] 1823:Src/main.c **** HAL_GPIO_WritePin(EN_5V2_GPIO_Port, EN_5V2_Pin, GPIO_PIN_RESET); 4156 .loc 2 1823 2 is_stmt 1 view .LVU1373 4157 0144 654F ldr r7, .L142+100 4158 0146 2246 mov r2, r4 4159 0148 0821 movs r1, #8 4160 014a 3846 mov r0, r7 4161 014c FFF7FEFF bl HAL_GPIO_WritePin 4162 .LVL296: 1824:Src/main.c **** HAL_GPIO_WritePin(LD1_EN_GPIO_Port, LD1_EN_Pin, GPIO_PIN_RESET); 4163 .loc 2 1824 2 view .LVU1374 4164 0150 2246 mov r2, r4 4165 0152 0421 movs r1, #4 4166 0154 3846 mov r0, r7 4167 0156 FFF7FEFF bl HAL_GPIO_WritePin 4168 .LVL297: 1825:Src/main.c **** HAL_GPIO_WritePin(LD2_EN_GPIO_Port, LD2_EN_Pin, GPIO_PIN_RESET); 4169 .loc 2 1825 2 view .LVU1375 4170 015a DFF8A481 ldr r8, .L142+136 4171 015e 2246 mov r2, r4 4172 0160 4FF48071 mov r1, #256 4173 0164 4046 mov r0, r8 4174 0166 FFF7FEFF bl HAL_GPIO_WritePin 4175 .LVL298: ARM GAS /tmp/ccqopZd5.s page 427 1826:Src/main.c **** HAL_GPIO_WritePin(REF0_EN_GPIO_Port, REF0_EN_Pin, GPIO_PIN_RESET); 4176 .loc 2 1826 2 view .LVU1376 4177 016a 2246 mov r2, r4 4178 016c 1021 movs r1, #16 4179 016e 3846 mov r0, r7 4180 0170 FFF7FEFF bl HAL_GPIO_WritePin 4181 .LVL299: 1827:Src/main.c **** HAL_GPIO_WritePin(REF2_ON_GPIO_Port, REF2_ON_Pin, GPIO_PIN_RESET); 4182 .loc 2 1827 2 view .LVU1377 4183 0174 5A4E ldr r6, .L142+104 4184 0176 2246 mov r2, r4 4185 0178 4FF48061 mov r1, #1024 4186 017c 3046 mov r0, r6 4187 017e FFF7FEFF bl HAL_GPIO_WritePin 4188 .LVL300: 1828:Src/main.c **** HAL_GPIO_WritePin(TECEN1_GPIO_Port, TECEN1_Pin, GPIO_PIN_RESET); 4189 .loc 2 1828 2 view .LVU1378 4190 0182 584D ldr r5, .L142+108 4191 0184 2246 mov r2, r4 4192 0186 0821 movs r1, #8 4193 0188 2846 mov r0, r5 4194 018a FFF7FEFF bl HAL_GPIO_WritePin 4195 .LVL301: 1829:Src/main.c **** HAL_GPIO_WritePin(TECEN2_GPIO_Port, TECEN2_Pin, GPIO_PIN_RESET); 4196 .loc 2 1829 2 view .LVU1379 4197 018e 2246 mov r2, r4 4198 0190 0121 movs r1, #1 4199 0192 2846 mov r0, r5 4200 0194 FFF7FEFF bl HAL_GPIO_WritePin 4201 .LVL302: 1830:Src/main.c **** HAL_GPIO_WritePin(TEC1_PD_GPIO_Port, TEC1_PD_Pin, GPIO_PIN_RESET); 4202 .loc 2 1830 2 view .LVU1380 4203 0198 2246 mov r2, r4 4204 019a 0221 movs r1, #2 4205 019c 2846 mov r0, r5 4206 019e FFF7FEFF bl HAL_GPIO_WritePin 4207 .LVL303: 1831:Src/main.c **** HAL_GPIO_WritePin(TEC2_PD_GPIO_Port, TEC2_PD_Pin, GPIO_PIN_RESET); 4208 .loc 2 1831 2 view .LVU1381 4209 01a2 2246 mov r2, r4 4210 01a4 4FF40061 mov r1, #2048 4211 01a8 3046 mov r0, r6 4212 01aa FFF7FEFF bl HAL_GPIO_WritePin 4213 .LVL304: 1832:Src/main.c **** // for (uint16_t i = 0; i < SD_Length; i++) 4214 .loc 2 1832 2 view .LVU1382 4215 01ae 2246 mov r2, r4 4216 01b0 2021 movs r1, #32 4217 01b2 3846 mov r0, r7 4218 01b4 FFF7FEFF bl HAL_GPIO_WritePin 4219 .LVL305: 1842:Src/main.c **** HAL_GPIO_WritePin(ADC_MPD2_CS_GPIO_Port, ADC_MPD2_CS_Pin, GPIO_PIN_SET);//Enable SPI for MPhD2 ADC 4220 .loc 2 1842 2 view .LVU1383 4221 01b8 07F50067 add r7, r7, #2048 4222 01bc 0122 movs r2, #1 4223 01be 4FF48061 mov r1, #1024 4224 01c2 3846 mov r0, r7 ARM GAS /tmp/ccqopZd5.s page 428 4225 01c4 FFF7FEFF bl HAL_GPIO_WritePin 4226 .LVL306: 1843:Src/main.c **** HAL_GPIO_WritePin(SPI4_CNV_GPIO_Port, SPI4_CNV_Pin, GPIO_PIN_SET); 4227 .loc 2 1843 2 view .LVU1384 4228 01c8 474C ldr r4, .L142+112 4229 01ca 0122 movs r2, #1 4230 01cc 4021 movs r1, #64 4231 01ce 2046 mov r0, r4 4232 01d0 FFF7FEFF bl HAL_GPIO_WritePin 4233 .LVL307: 1844:Src/main.c **** HAL_GPIO_WritePin(SPI5_CNV_GPIO_Port, SPI4_CNV_Pin, GPIO_PIN_SET); 4234 .loc 2 1844 2 view .LVU1385 4235 01d4 0122 movs r2, #1 4236 01d6 4FF48041 mov r1, #16384 4237 01da 3846 mov r0, r7 4238 01dc FFF7FEFF bl HAL_GPIO_WritePin 4239 .LVL308: 1845:Src/main.c **** HAL_GPIO_WritePin(DAC_LD1_CS_GPIO_Port, DAC_LD1_CS_Pin, GPIO_PIN_SET);//End operation with LDAC1 4240 .loc 2 1845 2 view .LVU1386 4241 01e0 0122 movs r2, #1 4242 01e2 4FF48041 mov r1, #16384 4243 01e6 2046 mov r0, r4 4244 01e8 FFF7FEFF bl HAL_GPIO_WritePin 4245 .LVL309: 1846:Src/main.c **** HAL_GPIO_WritePin(DAC_LD2_CS_GPIO_Port, DAC_LD2_CS_Pin, GPIO_PIN_SET);//End operation with LDAC2 4246 .loc 2 1846 2 view .LVU1387 4247 01ec 0122 movs r2, #1 4248 01ee 4FF48041 mov r1, #16384 4249 01f2 3046 mov r0, r6 4250 01f4 FFF7FEFF bl HAL_GPIO_WritePin 4251 .LVL310: 1847:Src/main.c **** HAL_GPIO_WritePin(DAC_TEC1_CS_GPIO_Port, DAC_TEC1_CS_Pin, GPIO_PIN_SET);//End operation with TEC1 4252 .loc 2 1847 2 view .LVU1388 4253 01f8 0122 movs r2, #1 4254 01fa 4021 movs r1, #64 4255 01fc 2846 mov r0, r5 4256 01fe FFF7FEFF bl HAL_GPIO_WritePin 4257 .LVL311: 1848:Src/main.c **** HAL_GPIO_WritePin(DAC_TEC2_CS_GPIO_Port, DAC_TEC2_CS_Pin, GPIO_PIN_SET);//End operation with TEC2 4258 .loc 2 1848 2 view .LVU1389 4259 0202 0122 movs r2, #1 4260 0204 4FF48051 mov r1, #4096 4261 0208 3046 mov r0, r6 4262 020a FFF7FEFF bl HAL_GPIO_WritePin 4263 .LVL312: 1849:Src/main.c **** 4264 .loc 2 1849 2 view .LVU1390 4265 020e 0122 movs r2, #1 4266 0210 1021 movs r1, #16 4267 0212 2846 mov r0, r5 4268 0214 FFF7FEFF bl HAL_GPIO_WritePin 4269 .LVL313: 1853:Src/main.c **** { 4270 .loc 2 1853 2 view .LVU1391 1853:Src/main.c **** { 4271 .loc 2 1853 6 is_stmt 0 view .LVU1392 4272 0218 0121 movs r1, #1 ARM GAS /tmp/ccqopZd5.s page 429 4273 021a 4046 mov r0, r8 4274 021c FFF7FEFF bl HAL_GPIO_ReadPin 4275 .LVL314: 1853:Src/main.c **** { 4276 .loc 2 1853 5 view .LVU1393 4277 0220 38B1 cbz r0, .L140 4278 .L130: 1883:Src/main.c **** static void Decode_uart(uint16_t *Command, LDx_SetupTypeDef *LD1_curr_setup, LDx_SetupTypeDef *LD2_ 4279 .loc 2 1883 1 view .LVU1394 4280 0222 BDE8F081 pop {r4, r5, r6, r7, r8, pc} 4281 .LVL315: 4282 .L139: 4283 .LBB470: 4284 .LBB469: 1430:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR, 4285 .loc 6 1430 5 is_stmt 1 view .LVU1395 4286 0226 284B ldr r3, .L142+80 4287 .LVL316: 1430:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR, 4288 .loc 6 1430 5 is_stmt 0 view .LVU1396 4289 0228 C3F8C410 str r1, [r3, #196] 1431:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 4290 .loc 6 1431 5 is_stmt 1 view .LVU1397 4291 022c C3F8C020 str r2, [r3, #192] 4292 0230 83E7 b .L135 4293 .LVL317: 4294 .L140: 1431:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 4295 .loc 6 1431 5 is_stmt 0 view .LVU1398 4296 .LBE469: 4297 .LBE470: 1856:Src/main.c **** { 4298 .loc 2 1856 3 is_stmt 1 view .LVU1399 1856:Src/main.c **** { 4299 .loc 2 1856 7 is_stmt 0 view .LVU1400 4300 0232 4FF48071 mov r1, #256 4301 0236 2846 mov r0, r5 4302 0238 FFF7FEFF bl HAL_GPIO_ReadPin 4303 .LVL318: 1856:Src/main.c **** { 4304 .loc 2 1856 6 view .LVU1401 4305 023c 0028 cmp r0, #0 4306 023e F0D1 bne .L130 1859:Src/main.c **** if (test == 0) //0 - suc 4307 .loc 2 1859 4 is_stmt 1 view .LVU1402 1859:Src/main.c **** if (test == 0) //0 - suc 4308 .loc 2 1859 11 is_stmt 0 view .LVU1403 4309 0240 2A48 ldr r0, .L142+116 4310 0242 FFF7FEFF bl Mount_SD 4311 .LVL319: 1859:Src/main.c **** if (test == 0) //0 - suc 4312 .loc 2 1859 9 view .LVU1404 4313 0246 2A4B ldr r3, .L142+120 4314 0248 1860 str r0, [r3] 1860:Src/main.c **** { 4315 .loc 2 1860 4 is_stmt 1 view .LVU1405 1860:Src/main.c **** { ARM GAS /tmp/ccqopZd5.s page 430 4316 .loc 2 1860 7 is_stmt 0 view .LVU1406 4317 024a 18B1 cbz r0, .L141 4318 .L137: 1872:Src/main.c **** } 4319 .loc 2 1872 4 is_stmt 1 view .LVU1407 1872:Src/main.c **** } 4320 .loc 2 1872 14 is_stmt 0 view .LVU1408 4321 024c 294B ldr r3, .L142+124 4322 024e 0122 movs r2, #1 4323 0250 1A70 strb r2, [r3] 1883:Src/main.c **** static void Decode_uart(uint16_t *Command, LDx_SetupTypeDef *LD1_curr_setup, LDx_SetupTypeDef *LD2_ 4324 .loc 2 1883 1 view .LVU1409 4325 0252 E6E7 b .L130 4326 .L141: 1863:Src/main.c **** test = Unmount_SD("/"); // 0 - succ 4327 .loc 2 1863 5 is_stmt 1 view .LVU1410 1863:Src/main.c **** test = Unmount_SD("/"); // 0 - succ 4328 .loc 2 1863 12 is_stmt 0 view .LVU1411 4329 0254 1E23 movs r3, #30 4330 0256 1A46 mov r2, r3 4331 0258 2749 ldr r1, .L142+128 4332 025a 2848 ldr r0, .L142+132 4333 025c FFF7FEFF bl Seek_Read_File 4334 .LVL320: 1863:Src/main.c **** test = Unmount_SD("/"); // 0 - succ 4335 .loc 2 1863 10 view .LVU1412 4336 0260 234C ldr r4, .L142+120 4337 0262 2060 str r0, [r4] 1864:Src/main.c **** UART_rec_incr = 0; 4338 .loc 2 1864 5 is_stmt 1 view .LVU1413 1864:Src/main.c **** UART_rec_incr = 0; 4339 .loc 2 1864 12 is_stmt 0 view .LVU1414 4340 0264 2148 ldr r0, .L142+116 4341 0266 FFF7FEFF bl Unmount_SD 4342 .LVL321: 1864:Src/main.c **** UART_rec_incr = 0; 4343 .loc 2 1864 10 view .LVU1415 4344 026a 2060 str r0, [r4] 1865:Src/main.c **** flg_tmt = 0;//Reset the timeout flag 4345 .loc 2 1865 5 is_stmt 1 view .LVU1416 1865:Src/main.c **** flg_tmt = 0;//Reset the timeout flag 4346 .loc 2 1865 19 is_stmt 0 view .LVU1417 4347 026c 0023 movs r3, #0 4348 026e 084A ldr r2, .L142+24 4349 0270 1380 strh r3, [r2] @ movhi 1866:Src/main.c **** } 4350 .loc 2 1866 5 is_stmt 1 view .LVU1418 1866:Src/main.c **** } 4351 .loc 2 1866 13 is_stmt 0 view .LVU1419 4352 0272 064A ldr r2, .L142+20 4353 0274 1370 strb r3, [r2] 4354 0276 E9E7 b .L137 4355 .L143: 4356 .align 2 4357 .L142: 4358 0278 00000000 .word .LANCHOR8 4359 027c 00000000 .word .LANCHOR3 ARM GAS /tmp/ccqopZd5.s page 431 4360 0280 00000000 .word .LANCHOR9 4361 0284 00000000 .word .LANCHOR10 4362 0288 00000000 .word .LANCHOR11 4363 028c 00000000 .word .LANCHOR12 4364 0290 00000000 .word .LANCHOR13 4365 0294 00000000 .word .LANCHOR14 4366 0298 00000000 .word .LANCHOR15 4367 029c 00000000 .word .LANCHOR16 4368 02a0 00000000 .word .LANCHOR17 4369 02a4 00000000 .word .LANCHOR18 4370 02a8 00000000 .word .LANCHOR19 4371 02ac 00000000 .word .LANCHOR20 4372 02b0 00000000 .word .LANCHOR21 4373 02b4 00000000 .word .LANCHOR22 4374 02b8 00000000 .word .LANCHOR23 4375 02bc 00000000 .word .LANCHOR24 4376 02c0 00100040 .word 1073745920 4377 02c4 08100140 .word 1073811464 4378 02c8 00640240 .word 1073898496 4379 02cc 00000000 .word .LANCHOR25 4380 02d0 28100140 .word 1073811496 4381 02d4 00000000 .word .LANCHOR26 4382 02d8 00000000 .word .LANCHOR27 4383 02dc 00080240 .word 1073874944 4384 02e0 00040240 .word 1073873920 4385 02e4 00000240 .word 1073872896 4386 02e8 00140240 .word 1073878016 4387 02ec 00000000 .word .LC0 4388 02f0 00000000 .word .LANCHOR28 4389 02f4 00000000 .word .LANCHOR30 4390 02f8 00000000 .word .LANCHOR29 4391 02fc 04000000 .word .LC1 4392 0300 000C0240 .word 1073875968 4393 .cfi_endproc 4394 .LFE1206: 4396 .section .text.Get_ADC,"ax",%progbits 4397 .align 1 4398 .syntax unified 4399 .thumb 4400 .thumb_func 4401 .fpu fpv5-d16 4403 Get_ADC: 4404 .LVL322: 4405 .LFB1212: 2312:Src/main.c **** uint16_t OUT; 4406 .loc 2 2312 1 is_stmt 1 view -0 4407 .cfi_startproc 4408 @ args = 0, pretend = 0, frame = 0 4409 @ frame_needed = 0, uses_anonymous_args = 0 2312:Src/main.c **** uint16_t OUT; 4410 .loc 2 2312 1 is_stmt 0 view .LVU1421 4411 0000 10B5 push {r4, lr} 4412 .LCFI39: 4413 .cfi_def_cfa_offset 8 4414 .cfi_offset 4, -8 4415 .cfi_offset 14, -4 4416 0002 0024 movs r4, #0 ARM GAS /tmp/ccqopZd5.s page 432 2313:Src/main.c **** switch (num) 4417 .loc 2 2313 2 is_stmt 1 view .LVU1422 2314:Src/main.c **** { 4418 .loc 2 2314 2 view .LVU1423 4419 0004 0528 cmp r0, #5 4420 0006 2CD8 bhi .L153 4421 0008 DFE800F0 tbb [pc, r0] 4422 .L147: 4423 000c 03 .byte (.L152-.L147)/2 4424 000d 08 .byte (.L151-.L147)/2 4425 000e 12 .byte (.L150-.L147)/2 4426 000f 17 .byte (.L149-.L147)/2 4427 0010 1C .byte (.L148-.L147)/2 4428 0011 26 .byte (.L146-.L147)/2 4429 .p2align 1 4430 .L152: 2317:Src/main.c **** break; 4431 .loc 2 2317 5 view .LVU1424 4432 0012 1548 ldr r0, .L155 4433 .LVL323: 2317:Src/main.c **** break; 4434 .loc 2 2317 5 is_stmt 0 view .LVU1425 4435 0014 FFF7FEFF bl HAL_ADC_Start 4436 .LVL324: 2318:Src/main.c **** case 1: 4437 .loc 2 2318 4 is_stmt 1 view .LVU1426 4438 0018 2046 mov r0, r4 4439 .L145: 4440 .LVL325: 2337:Src/main.c **** } 4441 .loc 2 2337 2 view .LVU1427 2338:Src/main.c **** 4442 .loc 2 2338 1 is_stmt 0 view .LVU1428 4443 001a 10BD pop {r4, pc} 4444 .LVL326: 4445 .L151: 2320:Src/main.c **** OUT = HAL_ADC_GetValue(&hadc1); // Get value adc 4446 .loc 2 2320 5 is_stmt 1 view .LVU1429 4447 001c 124C ldr r4, .L155 4448 001e 6421 movs r1, #100 4449 0020 2046 mov r0, r4 4450 .LVL327: 2320:Src/main.c **** OUT = HAL_ADC_GetValue(&hadc1); // Get value adc 4451 .loc 2 2320 5 is_stmt 0 view .LVU1430 4452 0022 FFF7FEFF bl HAL_ADC_PollForConversion 4453 .LVL328: 2321:Src/main.c **** break; 4454 .loc 2 2321 9 is_stmt 1 view .LVU1431 2321:Src/main.c **** break; 4455 .loc 2 2321 15 is_stmt 0 view .LVU1432 4456 0026 2046 mov r0, r4 4457 0028 FFF7FEFF bl HAL_ADC_GetValue 4458 .LVL329: 2321:Src/main.c **** break; 4459 .loc 2 2321 13 view .LVU1433 4460 002c 80B2 uxth r0, r0 4461 .LVL330: ARM GAS /tmp/ccqopZd5.s page 433 2322:Src/main.c **** case 2: 4462 .loc 2 2322 4 is_stmt 1 view .LVU1434 4463 002e F4E7 b .L145 4464 .LVL331: 4465 .L150: 2324:Src/main.c **** break; 4466 .loc 2 2324 5 view .LVU1435 4467 0030 0D48 ldr r0, .L155 4468 .LVL332: 2324:Src/main.c **** break; 4469 .loc 2 2324 5 is_stmt 0 view .LVU1436 4470 0032 FFF7FEFF bl HAL_ADC_Stop 4471 .LVL333: 2325:Src/main.c **** case 3: 4472 .loc 2 2325 4 is_stmt 1 view .LVU1437 4473 0036 2046 mov r0, r4 4474 0038 EFE7 b .L145 4475 .LVL334: 4476 .L149: 2327:Src/main.c **** break; 4477 .loc 2 2327 5 view .LVU1438 4478 003a 0C48 ldr r0, .L155+4 4479 .LVL335: 2327:Src/main.c **** break; 4480 .loc 2 2327 5 is_stmt 0 view .LVU1439 4481 003c FFF7FEFF bl HAL_ADC_Start 4482 .LVL336: 2328:Src/main.c **** case 4: 4483 .loc 2 2328 4 is_stmt 1 view .LVU1440 4484 0040 2046 mov r0, r4 4485 0042 EAE7 b .L145 4486 .LVL337: 4487 .L148: 2330:Src/main.c **** OUT = HAL_ADC_GetValue(&hadc3); // Get value adc 4488 .loc 2 2330 5 view .LVU1441 4489 0044 094C ldr r4, .L155+4 4490 0046 6421 movs r1, #100 4491 0048 2046 mov r0, r4 4492 .LVL338: 2330:Src/main.c **** OUT = HAL_ADC_GetValue(&hadc3); // Get value adc 4493 .loc 2 2330 5 is_stmt 0 view .LVU1442 4494 004a FFF7FEFF bl HAL_ADC_PollForConversion 4495 .LVL339: 2331:Src/main.c **** break; 4496 .loc 2 2331 9 is_stmt 1 view .LVU1443 2331:Src/main.c **** break; 4497 .loc 2 2331 15 is_stmt 0 view .LVU1444 4498 004e 2046 mov r0, r4 4499 0050 FFF7FEFF bl HAL_ADC_GetValue 4500 .LVL340: 2331:Src/main.c **** break; 4501 .loc 2 2331 13 view .LVU1445 4502 0054 80B2 uxth r0, r0 4503 .LVL341: 2332:Src/main.c **** case 5: 4504 .loc 2 2332 4 is_stmt 1 view .LVU1446 4505 0056 E0E7 b .L145 ARM GAS /tmp/ccqopZd5.s page 434 4506 .LVL342: 4507 .L146: 2334:Src/main.c **** break; 4508 .loc 2 2334 9 view .LVU1447 4509 0058 0448 ldr r0, .L155+4 4510 .LVL343: 2334:Src/main.c **** break; 4511 .loc 2 2334 9 is_stmt 0 view .LVU1448 4512 005a FFF7FEFF bl HAL_ADC_Stop 4513 .LVL344: 2335:Src/main.c **** } 4514 .loc 2 2335 4 is_stmt 1 view .LVU1449 4515 005e 2046 mov r0, r4 4516 0060 DBE7 b .L145 4517 .LVL345: 4518 .L153: 2314:Src/main.c **** { 4519 .loc 2 2314 2 is_stmt 0 view .LVU1450 4520 0062 2046 mov r0, r4 4521 .LVL346: 2314:Src/main.c **** { 4522 .loc 2 2314 2 view .LVU1451 4523 0064 D9E7 b .L145 4524 .L156: 4525 0066 00BF .align 2 4526 .L155: 4527 0068 00000000 .word .LANCHOR31 4528 006c 00000000 .word .LANCHOR32 4529 .cfi_endproc 4530 .LFE1212: 4532 .section .text.Set_LTEC,"ax",%progbits 4533 .align 1 4534 .global Set_LTEC 4535 .syntax unified 4536 .thumb 4537 .thumb_func 4538 .fpu fpv5-d16 4540 Set_LTEC: 4541 .LVL347: 4542 .LFB1210: 2140:Src/main.c **** uint32_t tmp32; 4543 .loc 2 2140 1 is_stmt 1 view -0 4544 .cfi_startproc 4545 @ args = 0, pretend = 0, frame = 0 4546 @ frame_needed = 0, uses_anonymous_args = 0 2140:Src/main.c **** uint32_t tmp32; 4547 .loc 2 2140 1 is_stmt 0 view .LVU1453 4548 0000 38B5 push {r3, r4, r5, lr} 4549 .LCFI40: 4550 .cfi_def_cfa_offset 16 4551 .cfi_offset 3, -16 4552 .cfi_offset 4, -12 4553 .cfi_offset 5, -8 4554 .cfi_offset 14, -4 4555 0002 0C46 mov r4, r1 2141:Src/main.c **** 4556 .loc 2 2141 2 is_stmt 1 view .LVU1454 ARM GAS /tmp/ccqopZd5.s page 435 2143:Src/main.c **** { 4557 .loc 2 2143 2 view .LVU1455 4558 0004 0138 subs r0, r0, #1 4559 .LVL348: 2143:Src/main.c **** { 4560 .loc 2 2143 2 is_stmt 0 view .LVU1456 4561 0006 0328 cmp r0, #3 4562 0008 23D8 bhi .L158 4563 000a DFE800F0 tbb [pc, r0] 4564 .L160: 4565 000e 02 .byte (.L163-.L160)/2 4566 000f 3B .byte (.L162-.L160)/2 4567 0010 5B .byte (.L161-.L160)/2 4568 0011 7C .byte (.L159-.L160)/2 4569 .p2align 1 4570 .L163: 2146:Src/main.c **** //tmp32=0; 4571 .loc 2 2146 4 is_stmt 1 view .LVU1457 4572 0012 0022 movs r2, #0 4573 0014 4FF48041 mov r1, #16384 4574 .LVL349: 2146:Src/main.c **** //tmp32=0; 4575 .loc 2 2146 4 is_stmt 0 view .LVU1458 4576 0018 4B48 ldr r0, .L189 4577 001a FFF7FEFF bl HAL_GPIO_WritePin 4578 .LVL350: 2149:Src/main.c **** while((!LL_SPI_IsActiveFlag_TXE(SPI2))&&(tmp32<=500)) {tmp32++;}//When trans. last data cycle wi 4579 .loc 2 2149 4 is_stmt 1 view .LVU1459 2150:Src/main.c **** LL_SPI_TransmitData16(SPI2, DATA);//Transmit word to Laser1 DAC 4580 .loc 2 2150 4 view .LVU1460 2149:Src/main.c **** while((!LL_SPI_IsActiveFlag_TXE(SPI2))&&(tmp32<=500)) {tmp32++;}//When trans. last data cycle wi 4581 .loc 2 2149 10 is_stmt 0 view .LVU1461 4582 001e 0022 movs r2, #0 4583 .LVL351: 4584 .L164: 2150:Src/main.c **** LL_SPI_TransmitData16(SPI2, DATA);//Transmit word to Laser1 DAC 4585 .loc 2 2150 9 is_stmt 1 discriminator 1 view .LVU1462 4586 .LBB471: 4587 .LBI471: 916:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 4588 .loc 4 916 26 discriminator 1 view .LVU1463 4589 .LBB472: 918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 4590 .loc 4 918 3 discriminator 1 view .LVU1464 918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 4591 .loc 4 918 12 is_stmt 0 discriminator 1 view .LVU1465 4592 0020 4A4B ldr r3, .L189+4 4593 0022 9B68 ldr r3, [r3, #8] 918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 4594 .loc 4 918 66 discriminator 1 view .LVU1466 4595 0024 13F0020F tst r3, #2 4596 0028 04D1 bne .L165 4597 .LVL352: 918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 4598 .loc 4 918 66 discriminator 1 view .LVU1467 4599 .LBE472: 4600 .LBE471: ARM GAS /tmp/ccqopZd5.s page 436 2150:Src/main.c **** LL_SPI_TransmitData16(SPI2, DATA);//Transmit word to Laser1 DAC 4601 .loc 2 2150 42 view .LVU1468 4602 002a B2F5FA7F cmp r2, #500 4603 002e 01D8 bhi .L165 2150:Src/main.c **** LL_SPI_TransmitData16(SPI2, DATA);//Transmit word to Laser1 DAC 4604 .loc 2 2150 59 is_stmt 1 discriminator 3 view .LVU1469 2150:Src/main.c **** LL_SPI_TransmitData16(SPI2, DATA);//Transmit word to Laser1 DAC 4605 .loc 2 2150 64 is_stmt 0 discriminator 3 view .LVU1470 4606 0030 0132 adds r2, r2, #1 4607 .LVL353: 2150:Src/main.c **** LL_SPI_TransmitData16(SPI2, DATA);//Transmit word to Laser1 DAC 4608 .loc 2 2150 64 discriminator 3 view .LVU1471 4609 0032 F5E7 b .L164 4610 .L165: 2151:Src/main.c **** tmp32 = 0; 4611 .loc 2 2151 4 is_stmt 1 view .LVU1472 4612 .LVL354: 4613 .LBB473: 4614 .LBI473: 1347:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1348:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 1349:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 1350:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Write 8-Bits in the data register 1351:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll DR DR LL_SPI_TransmitData8 1352:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 1353:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param TxData Value between Min_Data=0x00 and Max_Data=0xFF 1354:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None 1355:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 1356:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_TransmitData8(SPI_TypeDef *SPIx, uint8_t TxData) 1357:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 1358:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #if defined (__GNUC__) 1359:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __IO uint8_t *spidr = ((__IO uint8_t *)&SPIx->DR); 1360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** *spidr = TxData; 1361:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #else 1362:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** *((__IO uint8_t *)&SPIx->DR) = TxData; 1363:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #endif /* __GNUC__ */ 1364:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1365:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 1366:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 1367:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Write 16-Bits in the data register 1368:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll DR DR LL_SPI_TransmitData16 1369:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 1370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param TxData Value between Min_Data=0x00 and Max_Data=0xFFFF 1371:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None 1372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 1373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData) 4615 .loc 4 1373 22 view .LVU1473 4616 .LBB474: 1374:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 1375:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #if defined (__GNUC__) 1376:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __IO uint16_t *spidr = ((__IO uint16_t *)&SPIx->DR); 4617 .loc 4 1376 3 view .LVU1474 1377:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** *spidr = TxData; 4618 .loc 4 1377 3 view .LVU1475 4619 .loc 4 1377 10 is_stmt 0 view .LVU1476 4620 0034 454B ldr r3, .L189+4 4621 0036 9C81 strh r4, [r3, #12] @ movhi ARM GAS /tmp/ccqopZd5.s page 437 4622 .LVL355: 4623 .loc 4 1377 10 view .LVU1477 4624 .LBE474: 4625 .LBE473: 2152:Src/main.c **** while((!LL_SPI_IsActiveFlag_RXNE(SPI2))&&(tmp32<=500)) {tmp32++;}//When trans. last data cycle w 4626 .loc 2 2152 4 is_stmt 1 view .LVU1478 2153:Src/main.c **** (void) SPI2->DR; 4627 .loc 2 2153 4 view .LVU1479 2152:Src/main.c **** while((!LL_SPI_IsActiveFlag_RXNE(SPI2))&&(tmp32<=500)) {tmp32++;}//When trans. last data cycle w 4628 .loc 2 2152 10 is_stmt 0 view .LVU1480 4629 0038 0022 movs r2, #0 4630 .LVL356: 4631 .L167: 2153:Src/main.c **** (void) SPI2->DR; 4632 .loc 2 2153 9 is_stmt 1 discriminator 1 view .LVU1481 4633 .LBB475: 4634 .LBI475: 905:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 4635 .loc 4 905 26 discriminator 1 view .LVU1482 4636 .LBB476: 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 4637 .loc 4 907 3 discriminator 1 view .LVU1483 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 4638 .loc 4 907 12 is_stmt 0 discriminator 1 view .LVU1484 4639 003a 444B ldr r3, .L189+4 4640 003c 9B68 ldr r3, [r3, #8] 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 4641 .loc 4 907 68 discriminator 1 view .LVU1485 4642 003e 13F0010F tst r3, #1 4643 0042 04D1 bne .L168 4644 .LVL357: 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 4645 .loc 4 907 68 discriminator 1 view .LVU1486 4646 .LBE476: 4647 .LBE475: 2153:Src/main.c **** (void) SPI2->DR; 4648 .loc 2 2153 43 view .LVU1487 4649 0044 B2F5FA7F cmp r2, #500 4650 0048 01D8 bhi .L168 2153:Src/main.c **** (void) SPI2->DR; 4651 .loc 2 2153 60 is_stmt 1 discriminator 3 view .LVU1488 2153:Src/main.c **** (void) SPI2->DR; 4652 .loc 2 2153 65 is_stmt 0 discriminator 3 view .LVU1489 4653 004a 0132 adds r2, r2, #1 4654 .LVL358: 2153:Src/main.c **** (void) SPI2->DR; 4655 .loc 2 2153 65 discriminator 3 view .LVU1490 4656 004c F5E7 b .L167 4657 .L168: 2154:Src/main.c **** break; 4658 .loc 2 2154 4 is_stmt 1 view .LVU1491 4659 004e 3F4B ldr r3, .L189+4 4660 0050 DB68 ldr r3, [r3, #12] 2155:Src/main.c **** case 2: 4661 .loc 2 2155 3 view .LVU1492 4662 .LVL359: 4663 .L158: ARM GAS /tmp/ccqopZd5.s page 438 2191:Src/main.c **** HAL_GPIO_WritePin(DAC_LD2_CS_GPIO_Port, DAC_LD2_CS_Pin, GPIO_PIN_SET);//End operation with LDAC2 4664 .loc 2 2191 2 view .LVU1493 4665 0052 3D4D ldr r5, .L189 4666 0054 0122 movs r2, #1 4667 0056 4FF48041 mov r1, #16384 4668 005a 2846 mov r0, r5 4669 005c FFF7FEFF bl HAL_GPIO_WritePin 4670 .LVL360: 2192:Src/main.c **** HAL_GPIO_WritePin(DAC_TEC1_CS_GPIO_Port, DAC_TEC1_CS_Pin, GPIO_PIN_SET);//End operation with TEC1 4671 .loc 2 2192 2 view .LVU1494 4672 0060 3B4C ldr r4, .L189+8 4673 0062 0122 movs r2, #1 4674 0064 4021 movs r1, #64 4675 0066 2046 mov r0, r4 4676 0068 FFF7FEFF bl HAL_GPIO_WritePin 4677 .LVL361: 2193:Src/main.c **** HAL_GPIO_WritePin(DAC_TEC2_CS_GPIO_Port, DAC_TEC2_CS_Pin, GPIO_PIN_SET);//End operation with TEC2 4678 .loc 2 2193 2 view .LVU1495 4679 006c 0122 movs r2, #1 4680 006e 4FF48051 mov r1, #4096 4681 0072 2846 mov r0, r5 4682 0074 FFF7FEFF bl HAL_GPIO_WritePin 4683 .LVL362: 2194:Src/main.c **** } 4684 .loc 2 2194 2 view .LVU1496 4685 0078 0122 movs r2, #1 4686 007a 1021 movs r1, #16 4687 007c 2046 mov r0, r4 4688 007e FFF7FEFF bl HAL_GPIO_WritePin 4689 .LVL363: 2195:Src/main.c **** static uint16_t MPhD_T(uint8_t num) 4690 .loc 2 2195 1 is_stmt 0 view .LVU1497 4691 0082 38BD pop {r3, r4, r5, pc} 4692 .LVL364: 4693 .L162: 2158:Src/main.c **** //tmp32=0; 4694 .loc 2 2158 4 is_stmt 1 view .LVU1498 4695 0084 0022 movs r2, #0 4696 0086 4021 movs r1, #64 4697 .LVL365: 2158:Src/main.c **** //tmp32=0; 4698 .loc 2 2158 4 is_stmt 0 view .LVU1499 4699 0088 3148 ldr r0, .L189+8 4700 008a FFF7FEFF bl HAL_GPIO_WritePin 4701 .LVL366: 2161:Src/main.c **** while((!LL_SPI_IsActiveFlag_TXE(SPI6))&&(tmp32<=500)) {tmp32++;}//When trans. last data cycle wi 4702 .loc 2 2161 4 is_stmt 1 view .LVU1500 2162:Src/main.c **** LL_SPI_TransmitData16(SPI6, DATA);//Transmit word to Laser1 DAC 4703 .loc 2 2162 4 view .LVU1501 2161:Src/main.c **** while((!LL_SPI_IsActiveFlag_TXE(SPI6))&&(tmp32<=500)) {tmp32++;}//When trans. last data cycle wi 4704 .loc 2 2161 10 is_stmt 0 view .LVU1502 4705 008e 0022 movs r2, #0 4706 .LVL367: 4707 .L170: 2162:Src/main.c **** LL_SPI_TransmitData16(SPI6, DATA);//Transmit word to Laser1 DAC 4708 .loc 2 2162 9 is_stmt 1 discriminator 1 view .LVU1503 4709 .LBB477: ARM GAS /tmp/ccqopZd5.s page 439 4710 .LBI477: 916:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 4711 .loc 4 916 26 discriminator 1 view .LVU1504 4712 .LBB478: 918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 4713 .loc 4 918 3 discriminator 1 view .LVU1505 918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 4714 .loc 4 918 12 is_stmt 0 discriminator 1 view .LVU1506 4715 0090 304B ldr r3, .L189+12 4716 0092 9B68 ldr r3, [r3, #8] 918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 4717 .loc 4 918 66 discriminator 1 view .LVU1507 4718 0094 13F0020F tst r3, #2 4719 0098 04D1 bne .L171 4720 .LVL368: 918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 4721 .loc 4 918 66 discriminator 1 view .LVU1508 4722 .LBE478: 4723 .LBE477: 2162:Src/main.c **** LL_SPI_TransmitData16(SPI6, DATA);//Transmit word to Laser1 DAC 4724 .loc 2 2162 42 view .LVU1509 4725 009a B2F5FA7F cmp r2, #500 4726 009e 01D8 bhi .L171 2162:Src/main.c **** LL_SPI_TransmitData16(SPI6, DATA);//Transmit word to Laser1 DAC 4727 .loc 2 2162 59 is_stmt 1 discriminator 3 view .LVU1510 2162:Src/main.c **** LL_SPI_TransmitData16(SPI6, DATA);//Transmit word to Laser1 DAC 4728 .loc 2 2162 64 is_stmt 0 discriminator 3 view .LVU1511 4729 00a0 0132 adds r2, r2, #1 4730 .LVL369: 2162:Src/main.c **** LL_SPI_TransmitData16(SPI6, DATA);//Transmit word to Laser1 DAC 4731 .loc 2 2162 64 discriminator 3 view .LVU1512 4732 00a2 F5E7 b .L170 4733 .L171: 2163:Src/main.c **** tmp32 = 0; 4734 .loc 2 2163 4 is_stmt 1 view .LVU1513 4735 .LVL370: 4736 .LBB479: 4737 .LBI479: 1373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 4738 .loc 4 1373 22 view .LVU1514 4739 .LBB480: 1376:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** *spidr = TxData; 4740 .loc 4 1376 3 view .LVU1515 4741 .loc 4 1377 3 view .LVU1516 4742 .loc 4 1377 10 is_stmt 0 view .LVU1517 4743 00a4 2B4B ldr r3, .L189+12 4744 00a6 9C81 strh r4, [r3, #12] @ movhi 4745 .LVL371: 4746 .loc 4 1377 10 view .LVU1518 4747 .LBE480: 4748 .LBE479: 2164:Src/main.c **** while((!LL_SPI_IsActiveFlag_RXNE(SPI6))&&(tmp32<=500)) {tmp32++;}//When trans. last data cycle w 4749 .loc 2 2164 4 is_stmt 1 view .LVU1519 2165:Src/main.c **** (void) SPI6->DR; 4750 .loc 2 2165 4 view .LVU1520 2164:Src/main.c **** while((!LL_SPI_IsActiveFlag_RXNE(SPI6))&&(tmp32<=500)) {tmp32++;}//When trans. last data cycle w 4751 .loc 2 2164 10 is_stmt 0 view .LVU1521 ARM GAS /tmp/ccqopZd5.s page 440 4752 00a8 0022 movs r2, #0 4753 .LVL372: 4754 .L173: 2165:Src/main.c **** (void) SPI6->DR; 4755 .loc 2 2165 9 is_stmt 1 discriminator 1 view .LVU1522 4756 .LBB481: 4757 .LBI481: 905:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 4758 .loc 4 905 26 discriminator 1 view .LVU1523 4759 .LBB482: 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 4760 .loc 4 907 3 discriminator 1 view .LVU1524 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 4761 .loc 4 907 12 is_stmt 0 discriminator 1 view .LVU1525 4762 00aa 2A4B ldr r3, .L189+12 4763 00ac 9B68 ldr r3, [r3, #8] 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 4764 .loc 4 907 68 discriminator 1 view .LVU1526 4765 00ae 13F0010F tst r3, #1 4766 00b2 04D1 bne .L174 4767 .LVL373: 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 4768 .loc 4 907 68 discriminator 1 view .LVU1527 4769 .LBE482: 4770 .LBE481: 2165:Src/main.c **** (void) SPI6->DR; 4771 .loc 2 2165 43 view .LVU1528 4772 00b4 B2F5FA7F cmp r2, #500 4773 00b8 01D8 bhi .L174 2165:Src/main.c **** (void) SPI6->DR; 4774 .loc 2 2165 60 is_stmt 1 discriminator 3 view .LVU1529 2165:Src/main.c **** (void) SPI6->DR; 4775 .loc 2 2165 65 is_stmt 0 discriminator 3 view .LVU1530 4776 00ba 0132 adds r2, r2, #1 4777 .LVL374: 2165:Src/main.c **** (void) SPI6->DR; 4778 .loc 2 2165 65 discriminator 3 view .LVU1531 4779 00bc F5E7 b .L173 4780 .L174: 2166:Src/main.c **** break; 4781 .loc 2 2166 4 is_stmt 1 view .LVU1532 4782 00be 254B ldr r3, .L189+12 4783 00c0 DB68 ldr r3, [r3, #12] 2167:Src/main.c **** case 3: 4784 .loc 2 2167 3 view .LVU1533 4785 00c2 C6E7 b .L158 4786 .LVL375: 4787 .L161: 2169:Src/main.c **** //tmp32=0; 4788 .loc 2 2169 4 view .LVU1534 4789 00c4 0022 movs r2, #0 4790 00c6 4FF48051 mov r1, #4096 4791 .LVL376: 2169:Src/main.c **** //tmp32=0; 4792 .loc 2 2169 4 is_stmt 0 view .LVU1535 4793 00ca 1F48 ldr r0, .L189 4794 00cc FFF7FEFF bl HAL_GPIO_WritePin ARM GAS /tmp/ccqopZd5.s page 441 4795 .LVL377: 2172:Src/main.c **** while((!LL_SPI_IsActiveFlag_TXE(SPI2))&&(tmp32<=500)) {tmp32++;}//When trans. last data cycle wi 4796 .loc 2 2172 4 is_stmt 1 view .LVU1536 2173:Src/main.c **** LL_SPI_TransmitData16(SPI2, DATA);//Transmit word to Laser1 DAC 4797 .loc 2 2173 4 view .LVU1537 2172:Src/main.c **** while((!LL_SPI_IsActiveFlag_TXE(SPI2))&&(tmp32<=500)) {tmp32++;}//When trans. last data cycle wi 4798 .loc 2 2172 10 is_stmt 0 view .LVU1538 4799 00d0 0022 movs r2, #0 4800 .LVL378: 4801 .L176: 2173:Src/main.c **** LL_SPI_TransmitData16(SPI2, DATA);//Transmit word to Laser1 DAC 4802 .loc 2 2173 9 is_stmt 1 discriminator 1 view .LVU1539 4803 .LBB483: 4804 .LBI483: 916:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 4805 .loc 4 916 26 discriminator 1 view .LVU1540 4806 .LBB484: 918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 4807 .loc 4 918 3 discriminator 1 view .LVU1541 918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 4808 .loc 4 918 12 is_stmt 0 discriminator 1 view .LVU1542 4809 00d2 1E4B ldr r3, .L189+4 4810 00d4 9B68 ldr r3, [r3, #8] 918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 4811 .loc 4 918 66 discriminator 1 view .LVU1543 4812 00d6 13F0020F tst r3, #2 4813 00da 04D1 bne .L177 4814 .LVL379: 918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 4815 .loc 4 918 66 discriminator 1 view .LVU1544 4816 .LBE484: 4817 .LBE483: 2173:Src/main.c **** LL_SPI_TransmitData16(SPI2, DATA);//Transmit word to Laser1 DAC 4818 .loc 2 2173 42 view .LVU1545 4819 00dc B2F5FA7F cmp r2, #500 4820 00e0 01D8 bhi .L177 2173:Src/main.c **** LL_SPI_TransmitData16(SPI2, DATA);//Transmit word to Laser1 DAC 4821 .loc 2 2173 59 is_stmt 1 discriminator 3 view .LVU1546 2173:Src/main.c **** LL_SPI_TransmitData16(SPI2, DATA);//Transmit word to Laser1 DAC 4822 .loc 2 2173 64 is_stmt 0 discriminator 3 view .LVU1547 4823 00e2 0132 adds r2, r2, #1 4824 .LVL380: 2173:Src/main.c **** LL_SPI_TransmitData16(SPI2, DATA);//Transmit word to Laser1 DAC 4825 .loc 2 2173 64 discriminator 3 view .LVU1548 4826 00e4 F5E7 b .L176 4827 .L177: 2174:Src/main.c **** tmp32 = 0; 4828 .loc 2 2174 4 is_stmt 1 view .LVU1549 4829 .LVL381: 4830 .LBB485: 4831 .LBI485: 1373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 4832 .loc 4 1373 22 view .LVU1550 4833 .LBB486: 1376:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** *spidr = TxData; 4834 .loc 4 1376 3 view .LVU1551 4835 .loc 4 1377 3 view .LVU1552 ARM GAS /tmp/ccqopZd5.s page 442 4836 .loc 4 1377 10 is_stmt 0 view .LVU1553 4837 00e6 194B ldr r3, .L189+4 4838 00e8 9C81 strh r4, [r3, #12] @ movhi 4839 .LVL382: 4840 .loc 4 1377 10 view .LVU1554 4841 .LBE486: 4842 .LBE485: 2175:Src/main.c **** while((!LL_SPI_IsActiveFlag_RXNE(SPI2))&&(tmp32<=500)) {tmp32++;}//When trans. last data cycle w 4843 .loc 2 2175 4 is_stmt 1 view .LVU1555 2176:Src/main.c **** (void) SPI2->DR; 4844 .loc 2 2176 4 view .LVU1556 2175:Src/main.c **** while((!LL_SPI_IsActiveFlag_RXNE(SPI2))&&(tmp32<=500)) {tmp32++;}//When trans. last data cycle w 4845 .loc 2 2175 10 is_stmt 0 view .LVU1557 4846 00ea 0022 movs r2, #0 4847 .LVL383: 4848 .L179: 2176:Src/main.c **** (void) SPI2->DR; 4849 .loc 2 2176 9 is_stmt 1 discriminator 1 view .LVU1558 4850 .LBB487: 4851 .LBI487: 905:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 4852 .loc 4 905 26 discriminator 1 view .LVU1559 4853 .LBB488: 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 4854 .loc 4 907 3 discriminator 1 view .LVU1560 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 4855 .loc 4 907 12 is_stmt 0 discriminator 1 view .LVU1561 4856 00ec 174B ldr r3, .L189+4 4857 00ee 9B68 ldr r3, [r3, #8] 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 4858 .loc 4 907 68 discriminator 1 view .LVU1562 4859 00f0 13F0010F tst r3, #1 4860 00f4 04D1 bne .L180 4861 .LVL384: 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 4862 .loc 4 907 68 discriminator 1 view .LVU1563 4863 .LBE488: 4864 .LBE487: 2176:Src/main.c **** (void) SPI2->DR; 4865 .loc 2 2176 43 view .LVU1564 4866 00f6 B2F5FA7F cmp r2, #500 4867 00fa 01D8 bhi .L180 2176:Src/main.c **** (void) SPI2->DR; 4868 .loc 2 2176 60 is_stmt 1 discriminator 3 view .LVU1565 2176:Src/main.c **** (void) SPI2->DR; 4869 .loc 2 2176 65 is_stmt 0 discriminator 3 view .LVU1566 4870 00fc 0132 adds r2, r2, #1 4871 .LVL385: 2176:Src/main.c **** (void) SPI2->DR; 4872 .loc 2 2176 65 discriminator 3 view .LVU1567 4873 00fe F5E7 b .L179 4874 .L180: 2177:Src/main.c **** break; 4875 .loc 2 2177 4 is_stmt 1 view .LVU1568 4876 0100 124B ldr r3, .L189+4 4877 0102 DB68 ldr r3, [r3, #12] 2178:Src/main.c **** case 4: ARM GAS /tmp/ccqopZd5.s page 443 4878 .loc 2 2178 3 view .LVU1569 4879 0104 A5E7 b .L158 4880 .LVL386: 4881 .L159: 2180:Src/main.c **** //tmp32=0; 4882 .loc 2 2180 4 view .LVU1570 4883 0106 0022 movs r2, #0 4884 0108 1021 movs r1, #16 4885 .LVL387: 2180:Src/main.c **** //tmp32=0; 4886 .loc 2 2180 4 is_stmt 0 view .LVU1571 4887 010a 1148 ldr r0, .L189+8 4888 010c FFF7FEFF bl HAL_GPIO_WritePin 4889 .LVL388: 2183:Src/main.c **** while((!LL_SPI_IsActiveFlag_TXE(SPI6))&&(tmp32<=500)) {tmp32++;}//When trans. last data cycle wi 4890 .loc 2 2183 4 is_stmt 1 view .LVU1572 2184:Src/main.c **** LL_SPI_TransmitData16(SPI6, DATA);//Transmit word to Laser1 DAC 4891 .loc 2 2184 4 view .LVU1573 2183:Src/main.c **** while((!LL_SPI_IsActiveFlag_TXE(SPI6))&&(tmp32<=500)) {tmp32++;}//When trans. last data cycle wi 4892 .loc 2 2183 10 is_stmt 0 view .LVU1574 4893 0110 0022 movs r2, #0 4894 .LVL389: 4895 .L182: 2184:Src/main.c **** LL_SPI_TransmitData16(SPI6, DATA);//Transmit word to Laser1 DAC 4896 .loc 2 2184 9 is_stmt 1 discriminator 1 view .LVU1575 4897 .LBB489: 4898 .LBI489: 916:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 4899 .loc 4 916 26 discriminator 1 view .LVU1576 4900 .LBB490: 918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 4901 .loc 4 918 3 discriminator 1 view .LVU1577 918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 4902 .loc 4 918 12 is_stmt 0 discriminator 1 view .LVU1578 4903 0112 104B ldr r3, .L189+12 4904 0114 9B68 ldr r3, [r3, #8] 918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 4905 .loc 4 918 66 discriminator 1 view .LVU1579 4906 0116 13F0020F tst r3, #2 4907 011a 04D1 bne .L183 4908 .LVL390: 918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 4909 .loc 4 918 66 discriminator 1 view .LVU1580 4910 .LBE490: 4911 .LBE489: 2184:Src/main.c **** LL_SPI_TransmitData16(SPI6, DATA);//Transmit word to Laser1 DAC 4912 .loc 2 2184 42 view .LVU1581 4913 011c B2F5FA7F cmp r2, #500 4914 0120 01D8 bhi .L183 2184:Src/main.c **** LL_SPI_TransmitData16(SPI6, DATA);//Transmit word to Laser1 DAC 4915 .loc 2 2184 59 is_stmt 1 discriminator 3 view .LVU1582 2184:Src/main.c **** LL_SPI_TransmitData16(SPI6, DATA);//Transmit word to Laser1 DAC 4916 .loc 2 2184 64 is_stmt 0 discriminator 3 view .LVU1583 4917 0122 0132 adds r2, r2, #1 4918 .LVL391: 2184:Src/main.c **** LL_SPI_TransmitData16(SPI6, DATA);//Transmit word to Laser1 DAC 4919 .loc 2 2184 64 discriminator 3 view .LVU1584 ARM GAS /tmp/ccqopZd5.s page 444 4920 0124 F5E7 b .L182 4921 .L183: 2185:Src/main.c **** tmp32 = 0; 4922 .loc 2 2185 4 is_stmt 1 view .LVU1585 4923 .LVL392: 4924 .LBB491: 4925 .LBI491: 1373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 4926 .loc 4 1373 22 view .LVU1586 4927 .LBB492: 1376:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** *spidr = TxData; 4928 .loc 4 1376 3 view .LVU1587 4929 .loc 4 1377 3 view .LVU1588 4930 .loc 4 1377 10 is_stmt 0 view .LVU1589 4931 0126 0B4B ldr r3, .L189+12 4932 0128 9C81 strh r4, [r3, #12] @ movhi 4933 .LVL393: 4934 .loc 4 1377 10 view .LVU1590 4935 .LBE492: 4936 .LBE491: 2186:Src/main.c **** while((!LL_SPI_IsActiveFlag_RXNE(SPI6))&&(tmp32<=500)) {tmp32++;}//When trans. last data cycle w 4937 .loc 2 2186 4 is_stmt 1 view .LVU1591 2187:Src/main.c **** (void) SPI6->DR; 4938 .loc 2 2187 4 view .LVU1592 2186:Src/main.c **** while((!LL_SPI_IsActiveFlag_RXNE(SPI6))&&(tmp32<=500)) {tmp32++;}//When trans. last data cycle w 4939 .loc 2 2186 10 is_stmt 0 view .LVU1593 4940 012a 0022 movs r2, #0 4941 .LVL394: 4942 .L185: 2187:Src/main.c **** (void) SPI6->DR; 4943 .loc 2 2187 9 is_stmt 1 discriminator 1 view .LVU1594 4944 .LBB493: 4945 .LBI493: 905:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 4946 .loc 4 905 26 discriminator 1 view .LVU1595 4947 .LBB494: 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 4948 .loc 4 907 3 discriminator 1 view .LVU1596 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 4949 .loc 4 907 12 is_stmt 0 discriminator 1 view .LVU1597 4950 012c 094B ldr r3, .L189+12 4951 012e 9B68 ldr r3, [r3, #8] 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 4952 .loc 4 907 68 discriminator 1 view .LVU1598 4953 0130 13F0010F tst r3, #1 4954 0134 04D1 bne .L186 4955 .LVL395: 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 4956 .loc 4 907 68 discriminator 1 view .LVU1599 4957 .LBE494: 4958 .LBE493: 2187:Src/main.c **** (void) SPI6->DR; 4959 .loc 2 2187 43 view .LVU1600 4960 0136 B2F5FA7F cmp r2, #500 4961 013a 01D8 bhi .L186 2187:Src/main.c **** (void) SPI6->DR; 4962 .loc 2 2187 60 is_stmt 1 discriminator 3 view .LVU1601 ARM GAS /tmp/ccqopZd5.s page 445 2187:Src/main.c **** (void) SPI6->DR; 4963 .loc 2 2187 65 is_stmt 0 discriminator 3 view .LVU1602 4964 013c 0132 adds r2, r2, #1 4965 .LVL396: 2187:Src/main.c **** (void) SPI6->DR; 4966 .loc 2 2187 65 discriminator 3 view .LVU1603 4967 013e F5E7 b .L185 4968 .L186: 2188:Src/main.c **** break; 4969 .loc 2 2188 4 is_stmt 1 view .LVU1604 4970 0140 044B ldr r3, .L189+12 4971 0142 DB68 ldr r3, [r3, #12] 2189:Src/main.c **** } 4972 .loc 2 2189 3 view .LVU1605 4973 0144 85E7 b .L158 4974 .L190: 4975 0146 00BF .align 2 4976 .L189: 4977 0148 00040240 .word 1073873920 4978 014c 00380040 .word 1073756160 4979 0150 00000240 .word 1073872896 4980 0154 00540140 .word 1073828864 4981 .cfi_endproc 4982 .LFE1210: 4984 .section .text.Decode_uart,"ax",%progbits 4985 .align 1 4986 .syntax unified 4987 .thumb 4988 .thumb_func 4989 .fpu fpv5-d16 4991 Decode_uart: 4992 .LVL397: 4993 .LFB1207: 1885:Src/main.c **** // uint8_t *temp1; 4994 .loc 2 1885 1 view -0 4995 .cfi_startproc 4996 @ args = 0, pretend = 0, frame = 0 4997 @ frame_needed = 0, uses_anonymous_args = 0 1885:Src/main.c **** // uint8_t *temp1; 4998 .loc 2 1885 1 is_stmt 0 view .LVU1607 4999 0000 2DE9F843 push {r3, r4, r5, r6, r7, r8, r9, lr} 5000 .LCFI41: 5001 .cfi_def_cfa_offset 32 5002 .cfi_offset 3, -32 5003 .cfi_offset 4, -28 5004 .cfi_offset 5, -24 5005 .cfi_offset 6, -20 5006 .cfi_offset 7, -16 5007 .cfi_offset 8, -12 5008 .cfi_offset 9, -8 5009 .cfi_offset 14, -4 5010 0004 0546 mov r5, r0 5011 0006 0F46 mov r7, r1 5012 0008 1646 mov r6, r2 5013 000a 1C46 mov r4, r3 1887:Src/main.c **** 5014 .loc 2 1887 2 is_stmt 1 view .LVU1608 ARM GAS /tmp/ccqopZd5.s page 446 1892:Src/main.c **** if ((HAL_GPIO_ReadPin(SDMMC1_EN_GPIO_Port, SDMMC1_EN_Pin) == GPIO_PIN_RESET)&& 5015 .loc 2 1892 2 view .LVU1609 1892:Src/main.c **** if ((HAL_GPIO_ReadPin(SDMMC1_EN_GPIO_Port, SDMMC1_EN_Pin) == GPIO_PIN_RESET)&& 5016 .loc 2 1892 6 is_stmt 0 view .LVU1610 5017 000c AF4B ldr r3, .L215 5018 .LVL398: 1892:Src/main.c **** if ((HAL_GPIO_ReadPin(SDMMC1_EN_GPIO_Port, SDMMC1_EN_Pin) == GPIO_PIN_RESET)&& 5019 .loc 2 1892 6 view .LVU1611 5020 000e 0022 movs r2, #0 5021 .LVL399: 1892:Src/main.c **** if ((HAL_GPIO_ReadPin(SDMMC1_EN_GPIO_Port, SDMMC1_EN_Pin) == GPIO_PIN_RESET)&& 5022 .loc 2 1892 6 view .LVU1612 5023 0010 1A60 str r2, [r3] 1893:Src/main.c **** (HAL_GPIO_ReadPin(USB_FLAG_GPIO_Port, USB_FLAG_Pin) == GPIO_PIN_SET))//if exist sd && connect u 5024 .loc 2 1893 2 is_stmt 1 view .LVU1613 1893:Src/main.c **** (HAL_GPIO_ReadPin(USB_FLAG_GPIO_Port, USB_FLAG_Pin) == GPIO_PIN_SET))//if exist sd && connect u 5025 .loc 2 1893 7 is_stmt 0 view .LVU1614 5026 0012 0121 movs r1, #1 5027 .LVL400: 1893:Src/main.c **** (HAL_GPIO_ReadPin(USB_FLAG_GPIO_Port, USB_FLAG_Pin) == GPIO_PIN_SET))//if exist sd && connect u 5028 .loc 2 1893 7 view .LVU1615 5029 0014 AE48 ldr r0, .L215+4 5030 .LVL401: 1893:Src/main.c **** (HAL_GPIO_ReadPin(USB_FLAG_GPIO_Port, USB_FLAG_Pin) == GPIO_PIN_SET))//if exist sd && connect u 5031 .loc 2 1893 7 view .LVU1616 5032 0016 FFF7FEFF bl HAL_GPIO_ReadPin 5033 .LVL402: 1893:Src/main.c **** (HAL_GPIO_ReadPin(USB_FLAG_GPIO_Port, USB_FLAG_Pin) == GPIO_PIN_SET))//if exist sd && connect u 5034 .loc 2 1893 5 view .LVU1617 5035 001a 0028 cmp r0, #0 5036 001c 00F0D280 beq .L212 5037 .L192: 1908:Src/main.c **** Curr_setup->WORK_EN = ((uint8_t)((*temp2)>>0))&0x01; 5038 .loc 2 1908 2 is_stmt 1 view .LVU1618 5039 .LVL403: 1909:Src/main.c **** Curr_setup->U5V1_EN = ((uint8_t)((*temp2)>>1))&0x01; 5040 .loc 2 1909 2 view .LVU1619 1909:Src/main.c **** Curr_setup->U5V1_EN = ((uint8_t)((*temp2)>>1))&0x01; 5041 .loc 2 1909 36 is_stmt 0 view .LVU1620 5042 0020 2B88 ldrh r3, [r5] 1909:Src/main.c **** Curr_setup->U5V1_EN = ((uint8_t)((*temp2)>>1))&0x01; 5043 .loc 2 1909 48 view .LVU1621 5044 0022 03F00103 and r3, r3, #1 1909:Src/main.c **** Curr_setup->U5V1_EN = ((uint8_t)((*temp2)>>1))&0x01; 5045 .loc 2 1909 22 view .LVU1622 5046 0026 2370 strb r3, [r4] 1910:Src/main.c **** Curr_setup->U5V2_EN = ((uint8_t)((*temp2)>>2))&0x01; 5047 .loc 2 1910 2 is_stmt 1 view .LVU1623 1910:Src/main.c **** Curr_setup->U5V2_EN = ((uint8_t)((*temp2)>>2))&0x01; 5048 .loc 2 1910 36 is_stmt 0 view .LVU1624 5049 0028 2B88 ldrh r3, [r5] 1910:Src/main.c **** Curr_setup->U5V2_EN = ((uint8_t)((*temp2)>>2))&0x01; 5050 .loc 2 1910 48 view .LVU1625 5051 002a C3F34003 ubfx r3, r3, #1, #1 1910:Src/main.c **** Curr_setup->U5V2_EN = ((uint8_t)((*temp2)>>2))&0x01; 5052 .loc 2 1910 22 view .LVU1626 5053 002e 6370 strb r3, [r4, #1] ARM GAS /tmp/ccqopZd5.s page 447 1911:Src/main.c **** Curr_setup->LD1_EN = ((uint8_t)((*temp2)>>3))&0x01; 5054 .loc 2 1911 2 is_stmt 1 view .LVU1627 1911:Src/main.c **** Curr_setup->LD1_EN = ((uint8_t)((*temp2)>>3))&0x01; 5055 .loc 2 1911 36 is_stmt 0 view .LVU1628 5056 0030 2B88 ldrh r3, [r5] 1911:Src/main.c **** Curr_setup->LD1_EN = ((uint8_t)((*temp2)>>3))&0x01; 5057 .loc 2 1911 48 view .LVU1629 5058 0032 C3F38003 ubfx r3, r3, #2, #1 1911:Src/main.c **** Curr_setup->LD1_EN = ((uint8_t)((*temp2)>>3))&0x01; 5059 .loc 2 1911 22 view .LVU1630 5060 0036 A370 strb r3, [r4, #2] 1912:Src/main.c **** Curr_setup->LD2_EN = ((uint8_t)((*temp2)>>4))&0x01; 5061 .loc 2 1912 2 is_stmt 1 view .LVU1631 1912:Src/main.c **** Curr_setup->LD2_EN = ((uint8_t)((*temp2)>>4))&0x01; 5062 .loc 2 1912 35 is_stmt 0 view .LVU1632 5063 0038 2B88 ldrh r3, [r5] 1912:Src/main.c **** Curr_setup->LD2_EN = ((uint8_t)((*temp2)>>4))&0x01; 5064 .loc 2 1912 47 view .LVU1633 5065 003a C3F3C003 ubfx r3, r3, #3, #1 1912:Src/main.c **** Curr_setup->LD2_EN = ((uint8_t)((*temp2)>>4))&0x01; 5066 .loc 2 1912 21 view .LVU1634 5067 003e E370 strb r3, [r4, #3] 1913:Src/main.c **** Curr_setup->REF1_EN = ((uint8_t)((*temp2)>>5))&0x01; 5068 .loc 2 1913 2 is_stmt 1 view .LVU1635 1913:Src/main.c **** Curr_setup->REF1_EN = ((uint8_t)((*temp2)>>5))&0x01; 5069 .loc 2 1913 35 is_stmt 0 view .LVU1636 5070 0040 2B88 ldrh r3, [r5] 1913:Src/main.c **** Curr_setup->REF1_EN = ((uint8_t)((*temp2)>>5))&0x01; 5071 .loc 2 1913 47 view .LVU1637 5072 0042 C3F30013 ubfx r3, r3, #4, #1 1913:Src/main.c **** Curr_setup->REF1_EN = ((uint8_t)((*temp2)>>5))&0x01; 5073 .loc 2 1913 21 view .LVU1638 5074 0046 2371 strb r3, [r4, #4] 1914:Src/main.c **** Curr_setup->REF2_EN = ((uint8_t)((*temp2)>>6))&0x01; 5075 .loc 2 1914 2 is_stmt 1 view .LVU1639 1914:Src/main.c **** Curr_setup->REF2_EN = ((uint8_t)((*temp2)>>6))&0x01; 5076 .loc 2 1914 36 is_stmt 0 view .LVU1640 5077 0048 2B88 ldrh r3, [r5] 1914:Src/main.c **** Curr_setup->REF2_EN = ((uint8_t)((*temp2)>>6))&0x01; 5078 .loc 2 1914 48 view .LVU1641 5079 004a C3F34013 ubfx r3, r3, #5, #1 1914:Src/main.c **** Curr_setup->REF2_EN = ((uint8_t)((*temp2)>>6))&0x01; 5080 .loc 2 1914 22 view .LVU1642 5081 004e 6371 strb r3, [r4, #5] 1915:Src/main.c **** Curr_setup->TEC1_EN = ((uint8_t)((*temp2)>>7))&0x01; 5082 .loc 2 1915 2 is_stmt 1 view .LVU1643 1915:Src/main.c **** Curr_setup->TEC1_EN = ((uint8_t)((*temp2)>>7))&0x01; 5083 .loc 2 1915 36 is_stmt 0 view .LVU1644 5084 0050 2B88 ldrh r3, [r5] 1915:Src/main.c **** Curr_setup->TEC1_EN = ((uint8_t)((*temp2)>>7))&0x01; 5085 .loc 2 1915 48 view .LVU1645 5086 0052 C3F38013 ubfx r3, r3, #6, #1 1915:Src/main.c **** Curr_setup->TEC1_EN = ((uint8_t)((*temp2)>>7))&0x01; 5087 .loc 2 1915 22 view .LVU1646 5088 0056 A371 strb r3, [r4, #6] 1916:Src/main.c **** Curr_setup->TEC2_EN = ((uint8_t)((*temp2)>>8))&0x01; 5089 .loc 2 1916 2 is_stmt 1 view .LVU1647 ARM GAS /tmp/ccqopZd5.s page 448 1916:Src/main.c **** Curr_setup->TEC2_EN = ((uint8_t)((*temp2)>>8))&0x01; 5090 .loc 2 1916 36 is_stmt 0 view .LVU1648 5091 0058 2B88 ldrh r3, [r5] 1916:Src/main.c **** Curr_setup->TEC2_EN = ((uint8_t)((*temp2)>>8))&0x01; 5092 .loc 2 1916 48 view .LVU1649 5093 005a C3F3C013 ubfx r3, r3, #7, #1 1916:Src/main.c **** Curr_setup->TEC2_EN = ((uint8_t)((*temp2)>>8))&0x01; 5094 .loc 2 1916 22 view .LVU1650 5095 005e E371 strb r3, [r4, #7] 1917:Src/main.c **** Curr_setup->TS1_EN = ((uint8_t)((*temp2)>>9))&0x01; 5096 .loc 2 1917 2 is_stmt 1 view .LVU1651 1917:Src/main.c **** Curr_setup->TS1_EN = ((uint8_t)((*temp2)>>9))&0x01; 5097 .loc 2 1917 36 is_stmt 0 view .LVU1652 5098 0060 2B88 ldrh r3, [r5] 1917:Src/main.c **** Curr_setup->TS1_EN = ((uint8_t)((*temp2)>>9))&0x01; 5099 .loc 2 1917 48 view .LVU1653 5100 0062 C3F30023 ubfx r3, r3, #8, #1 1917:Src/main.c **** Curr_setup->TS1_EN = ((uint8_t)((*temp2)>>9))&0x01; 5101 .loc 2 1917 22 view .LVU1654 5102 0066 2372 strb r3, [r4, #8] 1918:Src/main.c **** Curr_setup->TS2_EN = ((uint8_t)((*temp2)>>10))&0x01; 5103 .loc 2 1918 2 is_stmt 1 view .LVU1655 1918:Src/main.c **** Curr_setup->TS2_EN = ((uint8_t)((*temp2)>>10))&0x01; 5104 .loc 2 1918 35 is_stmt 0 view .LVU1656 5105 0068 2B88 ldrh r3, [r5] 1918:Src/main.c **** Curr_setup->TS2_EN = ((uint8_t)((*temp2)>>10))&0x01; 5106 .loc 2 1918 47 view .LVU1657 5107 006a C3F34023 ubfx r3, r3, #9, #1 1918:Src/main.c **** Curr_setup->TS2_EN = ((uint8_t)((*temp2)>>10))&0x01; 5108 .loc 2 1918 21 view .LVU1658 5109 006e 6372 strb r3, [r4, #9] 1919:Src/main.c **** Curr_setup->SD_EN = ((uint8_t)((*temp2)>>11))&0x01; 5110 .loc 2 1919 2 is_stmt 1 view .LVU1659 1919:Src/main.c **** Curr_setup->SD_EN = ((uint8_t)((*temp2)>>11))&0x01; 5111 .loc 2 1919 35 is_stmt 0 view .LVU1660 5112 0070 2B88 ldrh r3, [r5] 1919:Src/main.c **** Curr_setup->SD_EN = ((uint8_t)((*temp2)>>11))&0x01; 5113 .loc 2 1919 48 view .LVU1661 5114 0072 C3F38023 ubfx r3, r3, #10, #1 1919:Src/main.c **** Curr_setup->SD_EN = ((uint8_t)((*temp2)>>11))&0x01; 5115 .loc 2 1919 21 view .LVU1662 5116 0076 A372 strb r3, [r4, #10] 1920:Src/main.c **** Curr_setup->PI1_RD = ((uint8_t)((*temp2)>>12))&0x01; 5117 .loc 2 1920 2 is_stmt 1 view .LVU1663 1920:Src/main.c **** Curr_setup->PI1_RD = ((uint8_t)((*temp2)>>12))&0x01; 5118 .loc 2 1920 34 is_stmt 0 view .LVU1664 5119 0078 2B88 ldrh r3, [r5] 1920:Src/main.c **** Curr_setup->PI1_RD = ((uint8_t)((*temp2)>>12))&0x01; 5120 .loc 2 1920 47 view .LVU1665 5121 007a C3F3C023 ubfx r3, r3, #11, #1 1920:Src/main.c **** Curr_setup->PI1_RD = ((uint8_t)((*temp2)>>12))&0x01; 5122 .loc 2 1920 20 view .LVU1666 5123 007e E372 strb r3, [r4, #11] 1921:Src/main.c **** Curr_setup->PI2_RD = ((uint8_t)((*temp2)>>13))&0x01; 5124 .loc 2 1921 2 is_stmt 1 view .LVU1667 1921:Src/main.c **** Curr_setup->PI2_RD = ((uint8_t)((*temp2)>>13))&0x01; 5125 .loc 2 1921 35 is_stmt 0 view .LVU1668 ARM GAS /tmp/ccqopZd5.s page 449 5126 0080 2B88 ldrh r3, [r5] 1921:Src/main.c **** Curr_setup->PI2_RD = ((uint8_t)((*temp2)>>13))&0x01; 5127 .loc 2 1921 48 view .LVU1669 5128 0082 C3F30033 ubfx r3, r3, #12, #1 1921:Src/main.c **** Curr_setup->PI2_RD = ((uint8_t)((*temp2)>>13))&0x01; 5129 .loc 2 1921 21 view .LVU1670 5130 0086 2373 strb r3, [r4, #12] 1922:Src/main.c **** 5131 .loc 2 1922 2 is_stmt 1 view .LVU1671 1922:Src/main.c **** 5132 .loc 2 1922 35 is_stmt 0 view .LVU1672 5133 0088 2B88 ldrh r3, [r5] 1922:Src/main.c **** 5134 .loc 2 1922 48 view .LVU1673 5135 008a C3F34033 ubfx r3, r3, #13, #1 1922:Src/main.c **** 5136 .loc 2 1922 21 view .LVU1674 5137 008e 6373 strb r3, [r4, #13] 1924:Src/main.c **** LD1_curr_setup->LD_TEMP = (uint16_t)(*temp2); 5138 .loc 2 1924 2 is_stmt 1 view .LVU1675 5139 .LVL404: 1925:Src/main.c **** temp2++; 5140 .loc 2 1925 2 view .LVU1676 1925:Src/main.c **** temp2++; 5141 .loc 2 1925 28 is_stmt 0 view .LVU1677 5142 0090 6B88 ldrh r3, [r5, #2] 1925:Src/main.c **** temp2++; 5143 .loc 2 1925 26 view .LVU1678 5144 0092 3B80 strh r3, [r7] @ movhi 1926:Src/main.c **** LD2_curr_setup->LD_TEMP = (uint16_t)(*temp2); 5145 .loc 2 1926 2 is_stmt 1 view .LVU1679 5146 .LVL405: 1927:Src/main.c **** temp2++; 5147 .loc 2 1927 2 view .LVU1680 1927:Src/main.c **** temp2++; 5148 .loc 2 1927 28 is_stmt 0 view .LVU1681 5149 0094 AB88 ldrh r3, [r5, #4] 1927:Src/main.c **** temp2++; 5150 .loc 2 1927 26 view .LVU1682 5151 0096 3380 strh r3, [r6] @ movhi 1928:Src/main.c **** temp2++; 5152 .loc 2 1928 2 is_stmt 1 view .LVU1683 5153 .LVL406: 1929:Src/main.c **** temp2++; 5154 .loc 2 1929 2 view .LVU1684 1930:Src/main.c **** Curr_setup->AVERAGES = (uint16_t)(*temp2); 5155 .loc 2 1930 2 view .LVU1685 1931:Src/main.c **** temp2++; 5156 .loc 2 1931 2 view .LVU1686 1931:Src/main.c **** temp2++; 5157 .loc 2 1931 25 is_stmt 0 view .LVU1687 5158 0098 6B89 ldrh r3, [r5, #10] 1931:Src/main.c **** temp2++; 5159 .loc 2 1931 23 view .LVU1688 5160 009a E381 strh r3, [r4, #14] @ movhi 1932:Src/main.c **** LD1_curr_setup->P_coef_temp = (float)((uint16_t)(*temp2))/((float)(256));//(float)(1/(float)((uint 5161 .loc 2 1932 2 is_stmt 1 view .LVU1689 ARM GAS /tmp/ccqopZd5.s page 450 5162 .LVL407: 1933:Src/main.c **** temp2++; 5163 .loc 2 1933 2 view .LVU1690 1933:Src/main.c **** temp2++; 5164 .loc 2 1933 51 is_stmt 0 view .LVU1691 5165 009c AB89 ldrh r3, [r5, #12] 5166 009e 07EE103A vmov s14, r3 @ int 1933:Src/main.c **** temp2++; 5167 .loc 2 1933 32 view .LVU1692 5168 00a2 B8EE477A vcvt.f32.u32 s14, s14 1933:Src/main.c **** temp2++; 5169 .loc 2 1933 59 view .LVU1693 5170 00a6 DFED8B6A vldr.32 s13, .L215+8 5171 00aa 27EE267A vmul.f32 s14, s14, s13 1933:Src/main.c **** temp2++; 5172 .loc 2 1933 30 view .LVU1694 5173 00ae 87ED017A vstr.32 s14, [r7, #4] 1934:Src/main.c **** LD1_curr_setup->I_coef_temp = (float)((uint16_t)(*temp2))/((float)(256));//(float)(1/(float)((uint 5174 .loc 2 1934 2 is_stmt 1 view .LVU1695 5175 .LVL408: 1935:Src/main.c **** temp2++; 5176 .loc 2 1935 2 view .LVU1696 1935:Src/main.c **** temp2++; 5177 .loc 2 1935 51 is_stmt 0 view .LVU1697 5178 00b2 EB89 ldrh r3, [r5, #14] 5179 00b4 07EE103A vmov s14, r3 @ int 1935:Src/main.c **** temp2++; 5180 .loc 2 1935 32 view .LVU1698 5181 00b8 B8EE477A vcvt.f32.u32 s14, s14 1935:Src/main.c **** temp2++; 5182 .loc 2 1935 59 view .LVU1699 5183 00bc 27EE267A vmul.f32 s14, s14, s13 1935:Src/main.c **** temp2++; 5184 .loc 2 1935 30 view .LVU1700 5185 00c0 87ED027A vstr.32 s14, [r7, #8] 1936:Src/main.c **** LD2_curr_setup->P_coef_temp = (float)((uint16_t)(*temp2))/((float)(256));//(float)(1/(float)((uint 5186 .loc 2 1936 2 is_stmt 1 view .LVU1701 5187 .LVL409: 1937:Src/main.c **** temp2++; 5188 .loc 2 1937 2 view .LVU1702 1937:Src/main.c **** temp2++; 5189 .loc 2 1937 51 is_stmt 0 view .LVU1703 5190 00c4 2B8A ldrh r3, [r5, #16] 5191 00c6 07EE103A vmov s14, r3 @ int 1937:Src/main.c **** temp2++; 5192 .loc 2 1937 32 view .LVU1704 5193 00ca B8EE477A vcvt.f32.u32 s14, s14 1937:Src/main.c **** temp2++; 5194 .loc 2 1937 59 view .LVU1705 5195 00ce 27EE267A vmul.f32 s14, s14, s13 1937:Src/main.c **** temp2++; 5196 .loc 2 1937 30 view .LVU1706 5197 00d2 86ED017A vstr.32 s14, [r6, #4] 1938:Src/main.c **** LD2_curr_setup->I_coef_temp = (float)((uint16_t)(*temp2))/((float)(256));//(float)(1/(float)((uint 5198 .loc 2 1938 2 is_stmt 1 view .LVU1707 5199 .LVL410: 1939:Src/main.c **** temp2++; ARM GAS /tmp/ccqopZd5.s page 451 5200 .loc 2 1939 2 view .LVU1708 1939:Src/main.c **** temp2++; 5201 .loc 2 1939 51 is_stmt 0 view .LVU1709 5202 00d6 6B8A ldrh r3, [r5, #18] 5203 00d8 07EE903A vmov s15, r3 @ int 1939:Src/main.c **** temp2++; 5204 .loc 2 1939 32 view .LVU1710 5205 00dc F8EE677A vcvt.f32.u32 s15, s15 1939:Src/main.c **** temp2++; 5206 .loc 2 1939 59 view .LVU1711 5207 00e0 67EEA67A vmul.f32 s15, s15, s13 1939:Src/main.c **** temp2++; 5208 .loc 2 1939 30 view .LVU1712 5209 00e4 C6ED027A vstr.32 s15, [r6, #8] 1940:Src/main.c **** Long_Data[13] = (uint16_t)(*temp2);//Message ID 5210 .loc 2 1940 2 is_stmt 1 view .LVU1713 5211 .LVL411: 1941:Src/main.c **** temp2++; 5212 .loc 2 1941 2 view .LVU1714 1941:Src/main.c **** temp2++; 5213 .loc 2 1941 18 is_stmt 0 view .LVU1715 5214 00e8 AA8A ldrh r2, [r5, #20] 1941:Src/main.c **** temp2++; 5215 .loc 2 1941 16 view .LVU1716 5216 00ea 7B4B ldr r3, .L215+12 5217 00ec 5A83 strh r2, [r3, #26] @ movhi 1942:Src/main.c **** LD1_curr_setup->CURRENT = (uint16_t)(*temp2); 5218 .loc 2 1942 2 is_stmt 1 view .LVU1717 5219 .LVL412: 1943:Src/main.c **** temp2++; 5220 .loc 2 1943 2 view .LVU1718 1943:Src/main.c **** temp2++; 5221 .loc 2 1943 28 is_stmt 0 view .LVU1719 5222 00ee EB8A ldrh r3, [r5, #22] 1943:Src/main.c **** temp2++; 5223 .loc 2 1943 26 view .LVU1720 5224 00f0 BB81 strh r3, [r7, #12] @ movhi 1944:Src/main.c **** LD2_curr_setup->CURRENT = (uint16_t)(*temp2); 5225 .loc 2 1944 2 is_stmt 1 view .LVU1721 5226 .LVL413: 1945:Src/main.c **** temp2++; 5227 .loc 2 1945 2 view .LVU1722 1945:Src/main.c **** temp2++; 5228 .loc 2 1945 28 is_stmt 0 view .LVU1723 5229 00f2 2B8B ldrh r3, [r5, #24] 1945:Src/main.c **** temp2++; 5230 .loc 2 1945 26 view .LVU1724 5231 00f4 B381 strh r3, [r6, #12] @ movhi 1946:Src/main.c **** 5232 .loc 2 1946 2 is_stmt 1 view .LVU1725 5233 .LVL414: 1948:Src/main.c **** { 5234 .loc 2 1948 2 view .LVU1726 1948:Src/main.c **** { 5235 .loc 2 1948 16 is_stmt 0 view .LVU1727 5236 00f6 6378 ldrb r3, [r4, #1] @ zero_extendqisi2 1948:Src/main.c **** { ARM GAS /tmp/ccqopZd5.s page 452 5237 .loc 2 1948 5 view .LVU1728 5238 00f8 002B cmp r3, #0 5239 00fa 00F09580 beq .L193 1950:Src/main.c **** } 5240 .loc 2 1950 3 is_stmt 1 view .LVU1729 5241 00fe 0122 movs r2, #1 5242 0100 0821 movs r1, #8 5243 0102 7648 ldr r0, .L215+16 5244 0104 FFF7FEFF bl HAL_GPIO_WritePin 5245 .LVL415: 5246 .L194: 1957:Src/main.c **** { 5247 .loc 2 1957 2 view .LVU1730 1957:Src/main.c **** { 5248 .loc 2 1957 16 is_stmt 0 view .LVU1731 5249 0108 A378 ldrb r3, [r4, #2] @ zero_extendqisi2 1957:Src/main.c **** { 5250 .loc 2 1957 5 view .LVU1732 5251 010a 002B cmp r3, #0 5252 010c 00F09280 beq .L195 1959:Src/main.c **** } 5253 .loc 2 1959 3 is_stmt 1 view .LVU1733 5254 0110 0122 movs r2, #1 5255 0112 0421 movs r1, #4 5256 0114 7148 ldr r0, .L215+16 5257 0116 FFF7FEFF bl HAL_GPIO_WritePin 5258 .LVL416: 5259 .L196: 1966:Src/main.c **** { 5260 .loc 2 1966 2 view .LVU1734 1966:Src/main.c **** { 5261 .loc 2 1966 16 is_stmt 0 view .LVU1735 5262 011a E378 ldrb r3, [r4, #3] @ zero_extendqisi2 1966:Src/main.c **** { 5263 .loc 2 1966 5 view .LVU1736 5264 011c 002B cmp r3, #0 5265 011e 00F08F80 beq .L197 1968:Src/main.c **** //LL_SPI_Enable(SPI2);//Enable SPI for Laser1 DAC 5266 .loc 2 1968 3 is_stmt 1 view .LVU1737 5267 0122 0122 movs r2, #1 5268 0124 4FF48071 mov r1, #256 5269 0128 6948 ldr r0, .L215+4 5270 012a FFF7FEFF bl HAL_GPIO_WritePin 5271 .LVL417: 5272 .L198: 1977:Src/main.c **** { 5273 .loc 2 1977 2 view .LVU1738 1977:Src/main.c **** { 5274 .loc 2 1977 16 is_stmt 0 view .LVU1739 5275 012e 2379 ldrb r3, [r4, #4] @ zero_extendqisi2 1977:Src/main.c **** { 5276 .loc 2 1977 5 view .LVU1740 5277 0130 002B cmp r3, #0 5278 0132 00F08C80 beq .L199 1979:Src/main.c **** //LL_SPI_Enable(SPI6);//Enable SPI for Laser2 DAC 5279 .loc 2 1979 3 is_stmt 1 view .LVU1741 5280 0136 0122 movs r2, #1 ARM GAS /tmp/ccqopZd5.s page 453 5281 0138 1021 movs r1, #16 5282 013a 6848 ldr r0, .L215+16 5283 013c FFF7FEFF bl HAL_GPIO_WritePin 5284 .LVL418: 5285 .L200: 1988:Src/main.c **** { 5286 .loc 2 1988 2 view .LVU1742 1988:Src/main.c **** { 5287 .loc 2 1988 16 is_stmt 0 view .LVU1743 5288 0140 6379 ldrb r3, [r4, #5] @ zero_extendqisi2 1988:Src/main.c **** { 5289 .loc 2 1988 5 view .LVU1744 5290 0142 002B cmp r3, #0 5291 0144 00F08980 beq .L201 1990:Src/main.c **** } 5292 .loc 2 1990 3 is_stmt 1 view .LVU1745 5293 0148 0122 movs r2, #1 5294 014a 4FF48061 mov r1, #1024 5295 014e 6448 ldr r0, .L215+20 5296 0150 FFF7FEFF bl HAL_GPIO_WritePin 5297 .LVL419: 5298 .L202: 1997:Src/main.c **** { 5299 .loc 2 1997 2 view .LVU1746 1997:Src/main.c **** { 5300 .loc 2 1997 16 is_stmt 0 view .LVU1747 5301 0154 A379 ldrb r3, [r4, #6] @ zero_extendqisi2 1997:Src/main.c **** { 5302 .loc 2 1997 5 view .LVU1748 5303 0156 002B cmp r3, #0 5304 0158 00F08680 beq .L203 1999:Src/main.c **** } 5305 .loc 2 1999 3 is_stmt 1 view .LVU1749 5306 015c 0122 movs r2, #1 5307 015e 0821 movs r1, #8 5308 0160 6048 ldr r0, .L215+24 5309 0162 FFF7FEFF bl HAL_GPIO_WritePin 5310 .LVL420: 5311 .L204: 2006:Src/main.c **** { 5312 .loc 2 2006 2 view .LVU1750 2006:Src/main.c **** { 5313 .loc 2 2006 17 is_stmt 0 view .LVU1751 5314 0166 637A ldrb r3, [r4, #9] @ zero_extendqisi2 2006:Src/main.c **** { 5315 .loc 2 2006 5 view .LVU1752 5316 0168 1BB1 cbz r3, .L205 2006:Src/main.c **** { 5317 .loc 2 2006 39 discriminator 1 view .LVU1753 5318 016a E379 ldrb r3, [r4, #7] @ zero_extendqisi2 2006:Src/main.c **** { 5319 .loc 2 2006 26 discriminator 1 view .LVU1754 5320 016c 002B cmp r3, #0 5321 016e 40F08180 bne .L213 5322 .L205: 2015:Src/main.c **** HAL_GPIO_WritePin(TEC1_PD_GPIO_Port, TEC1_PD_Pin, GPIO_PIN_RESET); 5323 .loc 2 2015 3 is_stmt 1 view .LVU1755 ARM GAS /tmp/ccqopZd5.s page 454 5324 0172 0022 movs r2, #0 5325 0174 0121 movs r1, #1 5326 0176 5B48 ldr r0, .L215+24 5327 0178 FFF7FEFF bl HAL_GPIO_WritePin 5328 .LVL421: 2016:Src/main.c **** } 5329 .loc 2 2016 3 view .LVU1756 5330 017c 0022 movs r2, #0 5331 017e 4FF40061 mov r1, #2048 5332 0182 5748 ldr r0, .L215+20 5333 0184 FFF7FEFF bl HAL_GPIO_WritePin 5334 .LVL422: 5335 .L206: 2019:Src/main.c **** { 5336 .loc 2 2019 2 view .LVU1757 2019:Src/main.c **** { 5337 .loc 2 2019 17 is_stmt 0 view .LVU1758 5338 0188 A37A ldrb r3, [r4, #10] @ zero_extendqisi2 2019:Src/main.c **** { 5339 .loc 2 2019 5 view .LVU1759 5340 018a 1BB1 cbz r3, .L207 2019:Src/main.c **** { 5341 .loc 2 2019 39 discriminator 1 view .LVU1760 5342 018c 237A ldrb r3, [r4, #8] @ zero_extendqisi2 2019:Src/main.c **** { 5343 .loc 2 2019 26 discriminator 1 view .LVU1761 5344 018e 002B cmp r3, #0 5345 0190 40F08680 bne .L214 5346 .L207: 2028:Src/main.c **** HAL_GPIO_WritePin(TEC2_PD_GPIO_Port, TEC2_PD_Pin, GPIO_PIN_RESET); 5347 .loc 2 2028 3 is_stmt 1 view .LVU1762 5348 0194 0022 movs r2, #0 5349 0196 0221 movs r1, #2 5350 0198 5248 ldr r0, .L215+24 5351 019a FFF7FEFF bl HAL_GPIO_WritePin 5352 .LVL423: 2029:Src/main.c **** } 5353 .loc 2 2029 3 view .LVU1763 5354 019e 0022 movs r2, #0 5355 01a0 2021 movs r1, #32 5356 01a2 4E48 ldr r0, .L215+16 5357 01a4 FFF7FEFF bl HAL_GPIO_WritePin 5358 .LVL424: 5359 .L208: 2032:Src/main.c **** { 5360 .loc 2 2032 2 view .LVU1764 2032:Src/main.c **** { 5361 .loc 2 2032 16 is_stmt 0 view .LVU1765 5362 01a8 237B ldrb r3, [r4, #12] @ zero_extendqisi2 2032:Src/main.c **** { 5363 .loc 2 2032 5 view .LVU1766 5364 01aa 1BB9 cbnz r3, .L209 2034:Src/main.c **** LD1_curr_setup->I_coef_temp = 0.01; 5365 .loc 2 2034 3 is_stmt 1 view .LVU1767 2034:Src/main.c **** LD1_curr_setup->I_coef_temp = 0.01; 5366 .loc 2 2034 31 is_stmt 0 view .LVU1768 5367 01ac 4E4B ldr r3, .L215+28 ARM GAS /tmp/ccqopZd5.s page 455 5368 01ae 7B60 str r3, [r7, #4] @ float 2035:Src/main.c **** } 5369 .loc 2 2035 3 is_stmt 1 view .LVU1769 2035:Src/main.c **** } 5370 .loc 2 2035 31 is_stmt 0 view .LVU1770 5371 01b0 4E4B ldr r3, .L215+32 5372 01b2 BB60 str r3, [r7, #8] @ float 5373 .L209: 2038:Src/main.c **** { 5374 .loc 2 2038 2 is_stmt 1 view .LVU1771 2038:Src/main.c **** { 5375 .loc 2 2038 16 is_stmt 0 view .LVU1772 5376 01b4 637B ldrb r3, [r4, #13] @ zero_extendqisi2 2038:Src/main.c **** { 5377 .loc 2 2038 5 view .LVU1773 5378 01b6 1BB9 cbnz r3, .L191 2040:Src/main.c **** LD2_curr_setup->I_coef_temp = 0.01; 5379 .loc 2 2040 3 is_stmt 1 view .LVU1774 2040:Src/main.c **** LD2_curr_setup->I_coef_temp = 0.01; 5380 .loc 2 2040 31 is_stmt 0 view .LVU1775 5381 01b8 4B4B ldr r3, .L215+28 5382 01ba 7360 str r3, [r6, #4] @ float 2041:Src/main.c **** } 5383 .loc 2 2041 3 is_stmt 1 view .LVU1776 2041:Src/main.c **** } 5384 .loc 2 2041 31 is_stmt 0 view .LVU1777 5385 01bc 4B4B ldr r3, .L215+32 5386 01be B360 str r3, [r6, #8] @ float 5387 .L191: 2043:Src/main.c **** 5388 .loc 2 2043 1 view .LVU1778 5389 01c0 BDE8F883 pop {r3, r4, r5, r6, r7, r8, r9, pc} 5390 .LVL425: 5391 .L212: 1894:Src/main.c **** { 5392 .loc 2 1894 6 discriminator 1 view .LVU1779 5393 01c4 4FF48071 mov r1, #256 5394 01c8 4648 ldr r0, .L215+24 5395 01ca FFF7FEFF bl HAL_GPIO_ReadPin 5396 .LVL426: 1893:Src/main.c **** (HAL_GPIO_ReadPin(USB_FLAG_GPIO_Port, USB_FLAG_Pin) == GPIO_PIN_SET))//if exist sd && connect u 5397 .loc 2 1893 78 discriminator 1 view .LVU1780 5398 01ce 0128 cmp r0, #1 5399 01d0 7FF426AF bne .L192 1896:Src/main.c **** if (test == 0) //0 - suc 5400 .loc 2 1896 3 is_stmt 1 view .LVU1781 1896:Src/main.c **** if (test == 0) //0 - suc 5401 .loc 2 1896 10 is_stmt 0 view .LVU1782 5402 01d4 4648 ldr r0, .L215+36 5403 01d6 FFF7FEFF bl Mount_SD 5404 .LVL427: 1896:Src/main.c **** if (test == 0) //0 - suc 5405 .loc 2 1896 8 view .LVU1783 5406 01da 3C4B ldr r3, .L215 5407 01dc 1860 str r0, [r3] 1897:Src/main.c **** { 5408 .loc 2 1897 3 is_stmt 1 view .LVU1784 ARM GAS /tmp/ccqopZd5.s page 456 1897:Src/main.c **** { 5409 .loc 2 1897 6 is_stmt 0 view .LVU1785 5410 01de 0028 cmp r0, #0 5411 01e0 7FF41EAF bne .L192 1900:Src/main.c **** test = Create_File("COMMAND.TXT"); // 0 -succ 5412 .loc 2 1900 4 is_stmt 1 view .LVU1786 1900:Src/main.c **** test = Create_File("COMMAND.TXT"); // 0 -succ 5413 .loc 2 1900 11 is_stmt 0 view .LVU1787 5414 01e4 DFF80C91 ldr r9, .L215+40 5415 01e8 4846 mov r0, r9 5416 01ea FFF7FEFF bl Remove_File 5417 .LVL428: 1900:Src/main.c **** test = Create_File("COMMAND.TXT"); // 0 -succ 5418 .loc 2 1900 9 view .LVU1788 5419 01ee DFF8DC80 ldr r8, .L215 5420 01f2 C8F80000 str r0, [r8] 1901:Src/main.c **** test = Write_File_byte("COMMAND.TXT", (uint8_t *)Command, CL_8); 5421 .loc 2 1901 4 is_stmt 1 view .LVU1789 1901:Src/main.c **** test = Write_File_byte("COMMAND.TXT", (uint8_t *)Command, CL_8); 5422 .loc 2 1901 11 is_stmt 0 view .LVU1790 5423 01f6 4846 mov r0, r9 5424 01f8 FFF7FEFF bl Create_File 5425 .LVL429: 1901:Src/main.c **** test = Write_File_byte("COMMAND.TXT", (uint8_t *)Command, CL_8); 5426 .loc 2 1901 9 view .LVU1791 5427 01fc C8F80000 str r0, [r8] 1902:Src/main.c **** test = Update_File_byte("COMMAND.TXT", (uint8_t *)Command, CL_8); 5428 .loc 2 1902 4 is_stmt 1 view .LVU1792 1902:Src/main.c **** test = Update_File_byte("COMMAND.TXT", (uint8_t *)Command, CL_8); 5429 .loc 2 1902 11 is_stmt 0 view .LVU1793 5430 0200 1E22 movs r2, #30 5431 0202 2946 mov r1, r5 5432 0204 4846 mov r0, r9 5433 0206 FFF7FEFF bl Write_File_byte 5434 .LVL430: 1902:Src/main.c **** test = Update_File_byte("COMMAND.TXT", (uint8_t *)Command, CL_8); 5435 .loc 2 1902 9 view .LVU1794 5436 020a C8F80000 str r0, [r8] 1903:Src/main.c **** test = Unmount_SD("/"); // 0 - succ 5437 .loc 2 1903 4 is_stmt 1 view .LVU1795 1903:Src/main.c **** test = Unmount_SD("/"); // 0 - succ 5438 .loc 2 1903 11 is_stmt 0 view .LVU1796 5439 020e 1E22 movs r2, #30 5440 0210 2946 mov r1, r5 5441 0212 4846 mov r0, r9 5442 0214 FFF7FEFF bl Update_File_byte 5443 .LVL431: 1903:Src/main.c **** test = Unmount_SD("/"); // 0 - succ 5444 .loc 2 1903 9 view .LVU1797 5445 0218 C8F80000 str r0, [r8] 1904:Src/main.c **** } 5446 .loc 2 1904 4 is_stmt 1 view .LVU1798 1904:Src/main.c **** } 5447 .loc 2 1904 11 is_stmt 0 view .LVU1799 5448 021c 3448 ldr r0, .L215+36 5449 021e FFF7FEFF bl Unmount_SD 5450 .LVL432: ARM GAS /tmp/ccqopZd5.s page 457 1904:Src/main.c **** } 5451 .loc 2 1904 9 view .LVU1800 5452 0222 C8F80000 str r0, [r8] 5453 0226 FBE6 b .L192 5454 .LVL433: 5455 .L193: 1954:Src/main.c **** } 5456 .loc 2 1954 3 is_stmt 1 view .LVU1801 5457 0228 0022 movs r2, #0 5458 022a 0821 movs r1, #8 5459 022c 2B48 ldr r0, .L215+16 5460 022e FFF7FEFF bl HAL_GPIO_WritePin 5461 .LVL434: 5462 0232 69E7 b .L194 5463 .L195: 1963:Src/main.c **** } 5464 .loc 2 1963 3 view .LVU1802 5465 0234 0022 movs r2, #0 5466 0236 0421 movs r1, #4 5467 0238 2848 ldr r0, .L215+16 5468 023a FFF7FEFF bl HAL_GPIO_WritePin 5469 .LVL435: 5470 023e 6CE7 b .L196 5471 .L197: 1973:Src/main.c **** //LL_SPI_Disable(SPI2);//Disable SPI for Laser1 DAC 5472 .loc 2 1973 3 view .LVU1803 5473 0240 0022 movs r2, #0 5474 0242 4FF48071 mov r1, #256 5475 0246 2248 ldr r0, .L215+4 5476 0248 FFF7FEFF bl HAL_GPIO_WritePin 5477 .LVL436: 5478 024c 6FE7 b .L198 5479 .L199: 1984:Src/main.c **** //LL_SPI_Disable(SPI6);//Disable SPI for Laser2 DAC 5480 .loc 2 1984 3 view .LVU1804 5481 024e 0022 movs r2, #0 5482 0250 1021 movs r1, #16 5483 0252 2248 ldr r0, .L215+16 5484 0254 FFF7FEFF bl HAL_GPIO_WritePin 5485 .LVL437: 5486 0258 72E7 b .L200 5487 .L201: 1994:Src/main.c **** } 5488 .loc 2 1994 3 view .LVU1805 5489 025a 0022 movs r2, #0 5490 025c 4FF48061 mov r1, #1024 5491 0260 1F48 ldr r0, .L215+20 5492 0262 FFF7FEFF bl HAL_GPIO_WritePin 5493 .LVL438: 5494 0266 75E7 b .L202 5495 .L203: 2003:Src/main.c **** } 5496 .loc 2 2003 3 view .LVU1806 5497 0268 0022 movs r2, #0 5498 026a 0821 movs r1, #8 5499 026c 1D48 ldr r0, .L215+24 5500 026e FFF7FEFF bl HAL_GPIO_WritePin ARM GAS /tmp/ccqopZd5.s page 458 5501 .LVL439: 5502 0272 78E7 b .L204 5503 .L213: 2008:Src/main.c **** Set_LTEC(3,32767); 5504 .loc 2 2008 3 view .LVU1807 5505 0274 47F6FF71 movw r1, #32767 5506 0278 0320 movs r0, #3 5507 027a FFF7FEFF bl Set_LTEC 5508 .LVL440: 2009:Src/main.c **** HAL_GPIO_WritePin(TEC1_PD_GPIO_Port, TEC1_PD_Pin, GPIO_PIN_SET); 5509 .loc 2 2009 3 view .LVU1808 5510 027e 47F6FF71 movw r1, #32767 5511 0282 0320 movs r0, #3 5512 0284 FFF7FEFF bl Set_LTEC 5513 .LVL441: 2010:Src/main.c **** HAL_GPIO_WritePin(TECEN1_GPIO_Port, TECEN1_Pin, GPIO_PIN_SET); 5514 .loc 2 2010 3 view .LVU1809 5515 0288 0122 movs r2, #1 5516 028a 4FF40061 mov r1, #2048 5517 028e 1448 ldr r0, .L215+20 5518 0290 FFF7FEFF bl HAL_GPIO_WritePin 5519 .LVL442: 2011:Src/main.c **** } 5520 .loc 2 2011 3 view .LVU1810 5521 0294 0122 movs r2, #1 5522 0296 1146 mov r1, r2 5523 0298 1248 ldr r0, .L215+24 5524 029a FFF7FEFF bl HAL_GPIO_WritePin 5525 .LVL443: 5526 029e 73E7 b .L206 5527 .L214: 2021:Src/main.c **** Set_LTEC(4,32767); 5528 .loc 2 2021 3 view .LVU1811 5529 02a0 47F6FF71 movw r1, #32767 5530 02a4 0420 movs r0, #4 5531 02a6 FFF7FEFF bl Set_LTEC 5532 .LVL444: 2022:Src/main.c **** HAL_GPIO_WritePin(TEC2_PD_GPIO_Port, TEC2_PD_Pin, GPIO_PIN_SET); 5533 .loc 2 2022 3 view .LVU1812 5534 02aa 47F6FF71 movw r1, #32767 5535 02ae 0420 movs r0, #4 5536 02b0 FFF7FEFF bl Set_LTEC 5537 .LVL445: 2023:Src/main.c **** HAL_GPIO_WritePin(TECEN2_GPIO_Port, TECEN2_Pin, GPIO_PIN_SET); 5538 .loc 2 2023 3 view .LVU1813 5539 02b4 0122 movs r2, #1 5540 02b6 2021 movs r1, #32 5541 02b8 0848 ldr r0, .L215+16 5542 02ba FFF7FEFF bl HAL_GPIO_WritePin 5543 .LVL446: 2024:Src/main.c **** } 5544 .loc 2 2024 3 view .LVU1814 5545 02be 0122 movs r2, #1 5546 02c0 0221 movs r1, #2 5547 02c2 0848 ldr r0, .L215+24 5548 02c4 FFF7FEFF bl HAL_GPIO_WritePin 5549 .LVL447: ARM GAS /tmp/ccqopZd5.s page 459 5550 02c8 6EE7 b .L208 5551 .L216: 5552 02ca 00BF .align 2 5553 .L215: 5554 02cc 00000000 .word .LANCHOR28 5555 02d0 000C0240 .word 1073875968 5556 02d4 0000803B .word 998244352 5557 02d8 00000000 .word .LANCHOR18 5558 02dc 00080240 .word 1073874944 5559 02e0 00040240 .word 1073873920 5560 02e4 00000240 .word 1073872896 5561 02e8 00002041 .word 1092616192 5562 02ec 0AD7233C .word 1008981770 5563 02f0 00000000 .word .LC0 5564 02f4 04000000 .word .LC1 5565 .cfi_endproc 5566 .LFE1207: 5568 .section .text.Advanced_Controller_Temp,"ax",%progbits 5569 .align 1 5570 .global Advanced_Controller_Temp 5571 .syntax unified 5572 .thumb 5573 .thumb_func 5574 .fpu fpv5-d16 5576 Advanced_Controller_Temp: 5577 .LVL448: 5578 .LFB1213: 2341:Src/main.c **** // Main idea: 5579 .loc 2 2341 1 view -0 5580 .cfi_startproc 5581 @ args = 0, pretend = 0, frame = 0 5582 @ frame_needed = 0, uses_anonymous_args = 0 5583 @ link register save eliminated. 2341:Src/main.c **** // Main idea: 5584 .loc 2 2341 1 is_stmt 0 view .LVU1816 5585 0000 30B4 push {r4, r5} 5586 .LCFI42: 5587 .cfi_def_cfa_offset 8 5588 .cfi_offset 4, -8 5589 .cfi_offset 5, -4 2359:Src/main.c **** float P_coef_current;//, I_coef_current; 5590 .loc 2 2359 2 is_stmt 1 view .LVU1817 2360:Src/main.c **** float e_integral; 5591 .loc 2 2360 2 view .LVU1818 2361:Src/main.c **** int x_output; 5592 .loc 2 2361 2 view .LVU1819 2362:Src/main.c **** 5593 .loc 2 2362 2 view .LVU1820 2364:Src/main.c **** 5594 .loc 2 2364 2 view .LVU1821 2364:Src/main.c **** 5595 .loc 2 2364 28 is_stmt 0 view .LVU1822 5596 0002 0B88 ldrh r3, [r1] 2364:Src/main.c **** 5597 .loc 2 2364 65 view .LVU1823 5598 0004 0488 ldrh r4, [r0] 2364:Src/main.c **** ARM GAS /tmp/ccqopZd5.s page 460 5599 .loc 2 2364 8 view .LVU1824 5600 0006 1B1B subs r3, r3, r4 5601 .LVL449: 2366:Src/main.c **** 5602 .loc 2 2366 2 is_stmt 1 view .LVU1825 2366:Src/main.c **** 5603 .loc 2 2366 13 is_stmt 0 view .LVU1826 5604 0008 D1ED017A vldr.32 s15, [r1, #4] 5605 .LVL450: 2368:Src/main.c **** e_integral += LDx_curr_setup->I_coef_temp * (float)(e_pid) * (float)(TO7 - TO7_PID) / (float) 100 5606 .loc 2 2368 2 is_stmt 1 view .LVU1827 2368:Src/main.c **** e_integral += LDx_curr_setup->I_coef_temp * (float)(e_pid) * (float)(TO7 - TO7_PID) / (float) 100 5607 .loc 2 2368 20 is_stmt 0 view .LVU1828 5608 000c 03F6B73C addw ip, r3, #2999 2368:Src/main.c **** e_integral += LDx_curr_setup->I_coef_temp * (float)(e_pid) * (float)(TO7 - TO7_PID) / (float) 100 5609 .loc 2 2368 4 view .LVU1829 5610 0010 41F26E74 movw r4, #5998 5611 0014 A445 cmp ip, r4 5612 0016 18D8 bhi .L218 2369:Src/main.c **** } 5613 .loc 2 2369 3 is_stmt 1 view .LVU1830 2369:Src/main.c **** } 5614 .loc 2 2369 31 is_stmt 0 view .LVU1831 5615 0018 90ED027A vldr.32 s14, [r0, #8] 2369:Src/main.c **** } 5616 .loc 2 2369 47 view .LVU1832 5617 001c 06EE903A vmov s13, r3 @ int 5618 0020 F8EEE66A vcvt.f32.s32 s13, s13 2369:Src/main.c **** } 5619 .loc 2 2369 45 view .LVU1833 5620 0024 67EE266A vmul.f32 s13, s14, s13 2369:Src/main.c **** } 5621 .loc 2 2369 76 view .LVU1834 5622 0028 284C ldr r4, .L228 5623 002a 2468 ldr r4, [r4] 5624 002c 284D ldr r5, .L228+4 5625 002e 2D68 ldr r5, [r5] 5626 0030 641B subs r4, r4, r5 5627 0032 07EE104A vmov s14, r4 @ int 2369:Src/main.c **** } 5628 .loc 2 2369 64 view .LVU1835 5629 0036 B8EE477A vcvt.f32.u32 s14, s14 2369:Src/main.c **** } 5630 .loc 2 2369 62 view .LVU1836 5631 003a 26EE877A vmul.f32 s14, s13, s14 2369:Src/main.c **** } 5632 .loc 2 2369 87 view .LVU1837 5633 003e 9FED256A vldr.32 s12, .L228+8 5634 0042 C7EE066A vdiv.f32 s13, s14, s12 2369:Src/main.c **** } 5635 .loc 2 2369 14 view .LVU1838 5636 0046 77EEA67A vadd.f32 s15, s15, s13 5637 .LVL451: 5638 .L218: 2371:Src/main.c **** 5639 .loc 2 2371 2 is_stmt 1 view .LVU1839 2371:Src/main.c **** ARM GAS /tmp/ccqopZd5.s page 461 5640 .loc 2 2371 17 is_stmt 0 view .LVU1840 5641 004a D0ED016A vldr.32 s13, [r0, #4] 5642 .LVL452: 2373:Src/main.c **** e_integral = 32000; 5643 .loc 2 2373 2 is_stmt 1 view .LVU1841 2373:Src/main.c **** e_integral = 32000; 5644 .loc 2 2373 5 is_stmt 0 view .LVU1842 5645 004e 9FED227A vldr.32 s14, .L228+12 5646 0052 F4EEC77A vcmpe.f32 s15, s14 5647 0056 F1EE10FA vmrs APSR_nzcv, FPSCR 5648 005a 09DC bgt .L222 2376:Src/main.c **** e_integral = -32000; 5649 .loc 2 2376 7 is_stmt 1 view .LVU1843 2376:Src/main.c **** e_integral = -32000; 5650 .loc 2 2376 10 is_stmt 0 view .LVU1844 5651 005c 9FED1F7A vldr.32 s14, .L228+16 5652 0060 F4EEC77A vcmpe.f32 s15, s14 5653 0064 F1EE10FA vmrs APSR_nzcv, FPSCR 5654 0068 04D5 bpl .L219 2377:Src/main.c **** } 5655 .loc 2 2377 15 view .LVU1845 5656 006a DFED1C7A vldr.32 s15, .L228+16 5657 .LVL453: 2377:Src/main.c **** } 5658 .loc 2 2377 15 view .LVU1846 5659 006e 01E0 b .L219 5660 .LVL454: 5661 .L222: 2374:Src/main.c **** } 5662 .loc 2 2374 15 view .LVU1847 5663 0070 DFED197A vldr.32 s15, .L228+12 5664 .LVL455: 5665 .L219: 2379:Src/main.c **** 5666 .loc 2 2379 2 is_stmt 1 view .LVU1848 2379:Src/main.c **** 5667 .loc 2 2379 26 is_stmt 0 view .LVU1849 5668 0074 C1ED017A vstr.32 s15, [r1, #4] 2381:Src/main.c **** 5669 .loc 2 2381 2 is_stmt 1 view .LVU1850 2381:Src/main.c **** 5670 .loc 2 2381 36 is_stmt 0 view .LVU1851 5671 0078 07EE103A vmov s14, r3 @ int 5672 007c B8EEC77A vcvt.f32.s32 s14, s14 5673 0080 27EE267A vmul.f32 s14, s14, s13 2381:Src/main.c **** 5674 .loc 2 2381 19 view .LVU1852 5675 0084 DFED166A vldr.32 s13, .L228+20 5676 .LVL456: 2381:Src/main.c **** 5677 .loc 2 2381 19 view .LVU1853 5678 0088 37EE267A vadd.f32 s14, s14, s13 2381:Src/main.c **** 5679 .loc 2 2381 46 view .LVU1854 5680 008c FDEEE77A vcvt.s32.f32 s15, s15 5681 .LVL457: 2381:Src/main.c **** ARM GAS /tmp/ccqopZd5.s page 462 5682 .loc 2 2381 44 view .LVU1855 5683 0090 F8EEE77A vcvt.f32.s32 s15, s15 5684 0094 77EE877A vadd.f32 s15, s15, s14 2381:Src/main.c **** 5685 .loc 2 2381 11 view .LVU1856 5686 0098 FDEEE77A vcvt.s32.f32 s15, s15 5687 009c 17EE900A vmov r0, s15 @ int 5688 .LVL458: 2383:Src/main.c **** x_output = 8800; 5689 .loc 2 2383 2 is_stmt 1 view .LVU1857 2383:Src/main.c **** x_output = 8800; 5690 .loc 2 2383 4 is_stmt 0 view .LVU1858 5691 00a0 B0F57A7F cmp r0, #1000 5692 00a4 06DB blt .L224 2386:Src/main.c **** x_output = 56800; 5693 .loc 2 2386 7 is_stmt 1 view .LVU1859 2386:Src/main.c **** x_output = 56800; 5694 .loc 2 2386 9 is_stmt 0 view .LVU1860 5695 00a6 4DF6E053 movw r3, #56800 5696 .LVL459: 2386:Src/main.c **** x_output = 56800; 5697 .loc 2 2386 9 view .LVU1861 5698 00aa 9842 cmp r0, r3 5699 00ac 04DD ble .L220 2387:Src/main.c **** } 5700 .loc 2 2387 12 view .LVU1862 5701 00ae 4DF6E050 movw r0, #56800 5702 .LVL460: 2387:Src/main.c **** } 5703 .loc 2 2387 12 view .LVU1863 5704 00b2 01E0 b .L220 5705 .LVL461: 5706 .L224: 2384:Src/main.c **** } 5707 .loc 2 2384 12 view .LVU1864 5708 00b4 42F26020 movw r0, #8800 5709 .LVL462: 5710 .L220: 2390:Src/main.c **** TO7_PID = TO7;//Save current time only on 2nd laser 5711 .loc 2 2390 2 is_stmt 1 view .LVU1865 2390:Src/main.c **** TO7_PID = TO7;//Save current time only on 2nd laser 5712 .loc 2 2390 5 is_stmt 0 view .LVU1866 5713 00b8 022A cmp r2, #2 5714 00ba 02D0 beq .L227 5715 .LVL463: 5716 .L221: 2393:Src/main.c **** } 5717 .loc 2 2393 2 is_stmt 1 view .LVU1867 2394:Src/main.c **** 5718 .loc 2 2394 1 is_stmt 0 view .LVU1868 5719 00bc 80B2 uxth r0, r0 5720 .LVL464: 2394:Src/main.c **** 5721 .loc 2 2394 1 view .LVU1869 5722 00be 30BC pop {r4, r5} 5723 .LCFI43: 5724 .cfi_remember_state ARM GAS /tmp/ccqopZd5.s page 463 5725 .cfi_restore 5 5726 .cfi_restore 4 5727 .cfi_def_cfa_offset 0 5728 00c0 7047 bx lr 5729 .LVL465: 5730 .L227: 5731 .LCFI44: 5732 .cfi_restore_state 2391:Src/main.c **** 5733 .loc 2 2391 3 is_stmt 1 view .LVU1870 2391:Src/main.c **** 5734 .loc 2 2391 11 is_stmt 0 view .LVU1871 5735 00c2 024B ldr r3, .L228 5736 00c4 1A68 ldr r2, [r3] 5737 .LVL466: 2391:Src/main.c **** 5738 .loc 2 2391 11 view .LVU1872 5739 00c6 024B ldr r3, .L228+4 5740 00c8 1A60 str r2, [r3] 5741 00ca F7E7 b .L221 5742 .L229: 5743 .align 2 5744 .L228: 5745 00cc 00000000 .word .LANCHOR3 5746 00d0 00000000 .word .LANCHOR4 5747 00d4 0000C842 .word 1120403456 5748 00d8 0000FA46 .word 1190789120 5749 00dc 0000FAC6 .word -956694528 5750 00e0 00000047 .word 1191182336 5751 .cfi_endproc 5752 .LFE1213: 5754 .section .text.CalculateChecksum,"ax",%progbits 5755 .align 1 5756 .global CalculateChecksum 5757 .syntax unified 5758 .thumb 5759 .thumb_func 5760 .fpu fpv5-d16 5762 CalculateChecksum: 5763 .LVL467: 5764 .LFB1216: 2457:Src/main.c **** short i; 5765 .loc 2 2457 1 is_stmt 1 view -0 5766 .cfi_startproc 5767 @ args = 0, pretend = 0, frame = 0 5768 @ frame_needed = 0, uses_anonymous_args = 0 5769 @ link register save eliminated. 2457:Src/main.c **** short i; 5770 .loc 2 2457 1 is_stmt 0 view .LVU1874 5771 0000 8446 mov ip, r0 2458:Src/main.c **** uint16_t cs = *pbuff; 5772 .loc 2 2458 2 is_stmt 1 view .LVU1875 2459:Src/main.c **** 5773 .loc 2 2459 2 view .LVU1876 2459:Src/main.c **** 5774 .loc 2 2459 11 is_stmt 0 view .LVU1877 5775 0002 0088 ldrh r0, [r0] ARM GAS /tmp/ccqopZd5.s page 464 5776 .LVL468: 2461:Src/main.c **** { 5777 .loc 2 2461 3 is_stmt 1 view .LVU1878 2461:Src/main.c **** { 5778 .loc 2 2461 9 is_stmt 0 view .LVU1879 5779 0004 0123 movs r3, #1 2461:Src/main.c **** { 5780 .loc 2 2461 3 view .LVU1880 5781 0006 04E0 b .L231 5782 .LVL469: 5783 .L232: 2463:Src/main.c **** } 5784 .loc 2 2463 3 is_stmt 1 discriminator 3 view .LVU1881 2463:Src/main.c **** } 5785 .loc 2 2463 9 is_stmt 0 discriminator 3 view .LVU1882 5786 0008 3CF81320 ldrh r2, [ip, r3, lsl #1] 2463:Src/main.c **** } 5787 .loc 2 2463 6 discriminator 3 view .LVU1883 5788 000c 5040 eors r0, r0, r2 5789 .LVL470: 2461:Src/main.c **** { 5790 .loc 2 2461 23 is_stmt 1 discriminator 3 view .LVU1884 2461:Src/main.c **** { 5791 .loc 2 2461 24 is_stmt 0 discriminator 3 view .LVU1885 5792 000e 0133 adds r3, r3, #1 5793 .LVL471: 2461:Src/main.c **** { 5794 .loc 2 2461 24 discriminator 3 view .LVU1886 5795 0010 1BB2 sxth r3, r3 5796 .LVL472: 5797 .L231: 2461:Src/main.c **** { 5798 .loc 2 2461 14 is_stmt 1 discriminator 1 view .LVU1887 2461:Src/main.c **** { 5799 .loc 2 2461 3 is_stmt 0 discriminator 1 view .LVU1888 5800 0012 8B42 cmp r3, r1 5801 0014 F8DB blt .L232 2465:Src/main.c **** } 5802 .loc 2 2465 2 is_stmt 1 view .LVU1889 2466:Src/main.c **** 5803 .loc 2 2466 1 is_stmt 0 view .LVU1890 5804 0016 7047 bx lr 5805 .cfi_endproc 5806 .LFE1216: 5808 .section .text.CheckChecksum,"ax",%progbits 5809 .align 1 5810 .global CheckChecksum 5811 .syntax unified 5812 .thumb 5813 .thumb_func 5814 .fpu fpv5-d16 5816 CheckChecksum: 5817 .LVL473: 5818 .LFB1215: 2436:Src/main.c **** uint16_t cl_ind; 5819 .loc 2 2436 1 is_stmt 1 view -0 5820 .cfi_startproc ARM GAS /tmp/ccqopZd5.s page 465 5821 @ args = 0, pretend = 0, frame = 0 5822 @ frame_needed = 0, uses_anonymous_args = 0 2436:Src/main.c **** uint16_t cl_ind; 5823 .loc 2 2436 1 is_stmt 0 view .LVU1892 5824 0000 10B5 push {r4, lr} 5825 .LCFI45: 5826 .cfi_def_cfa_offset 8 5827 .cfi_offset 4, -8 5828 .cfi_offset 14, -4 2437:Src/main.c **** 5829 .loc 2 2437 3 is_stmt 1 view .LVU1893 2439:Src/main.c **** { 5830 .loc 2 2439 3 view .LVU1894 5831 0002 0E4B ldr r3, .L239 5832 0004 1B88 ldrh r3, [r3] 5833 0006 41F21112 movw r2, #4369 5834 000a 9342 cmp r3, r2 5835 000c 11D0 beq .L236 5836 000e 47F27772 movw r2, #30583 5837 0012 9342 cmp r3, r2 5838 0014 0FD1 bne .L237 5839 0016 0E24 movs r4, #14 5840 .L234: 5841 .LVL474: 2449:Src/main.c **** } 5842 .loc 2 2449 5 view .LVU1895 2452:Src/main.c **** 5843 .loc 2 2452 3 view .LVU1896 2452:Src/main.c **** 5844 .loc 2 2452 15 is_stmt 0 view .LVU1897 5845 0018 2146 mov r1, r4 5846 001a FFF7FEFF bl CalculateChecksum 5847 .LVL475: 2452:Src/main.c **** 5848 .loc 2 2452 13 view .LVU1898 5849 001e 084B ldr r3, .L239+4 5850 0020 1880 strh r0, [r3] @ movhi 2454:Src/main.c **** } 5851 .loc 2 2454 3 is_stmt 1 view .LVU1899 2454:Src/main.c **** } 5852 .loc 2 2454 32 is_stmt 0 view .LVU1900 5853 0022 084B ldr r3, .L239+8 5854 0024 33F81430 ldrh r3, [r3, r4, lsl #1] 2454:Src/main.c **** } 5855 .loc 2 2454 46 view .LVU1901 5856 0028 9842 cmp r0, r3 5857 002a 14BF ite ne 5858 002c 0020 movne r0, #0 5859 002e 0120 moveq r0, #1 5860 .LVL476: 5861 .L235: 2455:Src/main.c **** uint16_t CalculateChecksum(uint16_t *pbuff, uint16_t len) 5862 .loc 2 2455 1 view .LVU1902 5863 0030 10BD pop {r4, pc} 5864 .LVL477: 5865 .L236: 2445:Src/main.c **** break; ARM GAS /tmp/ccqopZd5.s page 466 5866 .loc 2 2445 14 view .LVU1903 5867 0032 0D24 movs r4, #13 5868 0034 F0E7 b .L234 5869 .L237: 2439:Src/main.c **** { 5870 .loc 2 2439 3 view .LVU1904 5871 0036 0020 movs r0, #0 5872 .LVL478: 2439:Src/main.c **** { 5873 .loc 2 2439 3 view .LVU1905 5874 0038 FAE7 b .L235 5875 .L240: 5876 003a 00BF .align 2 5877 .L239: 5878 003c 00000000 .word .LANCHOR33 5879 0040 00000000 .word .LANCHOR34 5880 0044 00000000 .word .LANCHOR29 5881 .cfi_endproc 5882 .LFE1215: 5884 .section .rodata.SD_SAVE.str1.4,"aMS",%progbits,1 5885 .align 2 5886 .LC2: 5887 0000 46494C45 .ascii "FILE1.TXT\000" 5887 312E5458 5887 5400 5888 .section .text.SD_SAVE,"ax",%progbits 5889 .align 1 5890 .global SD_SAVE 5891 .syntax unified 5892 .thumb 5893 .thumb_func 5894 .fpu fpv5-d16 5896 SD_SAVE: 5897 .LVL479: 5898 .LFB1217: 2495:Src/main.c **** int test=0; 5899 .loc 2 2495 1 is_stmt 1 view -0 5900 .cfi_startproc 5901 @ args = 0, pretend = 0, frame = 0 5902 @ frame_needed = 0, uses_anonymous_args = 0 2495:Src/main.c **** int test=0; 5903 .loc 2 2495 1 is_stmt 0 view .LVU1907 5904 0000 10B5 push {r4, lr} 5905 .LCFI46: 5906 .cfi_def_cfa_offset 8 5907 .cfi_offset 4, -8 5908 .cfi_offset 14, -4 5909 0002 0446 mov r4, r0 2496:Src/main.c **** if (HAL_GPIO_ReadPin(SDMMC1_EN_GPIO_Port, SDMMC1_EN_Pin)==GPIO_PIN_RESET) 5910 .loc 2 2496 2 is_stmt 1 view .LVU1908 5911 .LVL480: 2497:Src/main.c **** { 5912 .loc 2 2497 2 view .LVU1909 2497:Src/main.c **** { 5913 .loc 2 2497 6 is_stmt 0 view .LVU1910 5914 0004 0121 movs r1, #1 5915 0006 0A48 ldr r0, .L248 ARM GAS /tmp/ccqopZd5.s page 467 5916 .LVL481: 2497:Src/main.c **** { 5917 .loc 2 2497 6 view .LVU1911 5918 0008 FFF7FEFF bl HAL_GPIO_ReadPin 5919 .LVL482: 2497:Src/main.c **** { 5920 .loc 2 2497 5 view .LVU1912 5921 000c 08B1 cbz r0, .L246 2514:Src/main.c **** } 5922 .loc 2 2514 10 view .LVU1913 5923 000e 0120 movs r0, #1 5924 .LVL483: 5925 .L241: 2516:Src/main.c **** 5926 .loc 2 2516 1 view .LVU1914 5927 0010 10BD pop {r4, pc} 5928 .LVL484: 5929 .L246: 2499:Src/main.c **** if (test == 0) //0 - suc 5930 .loc 2 2499 3 is_stmt 1 view .LVU1915 2499:Src/main.c **** if (test == 0) //0 - suc 5931 .loc 2 2499 10 is_stmt 0 view .LVU1916 5932 0012 0848 ldr r0, .L248+4 5933 0014 FFF7FEFF bl Mount_SD 5934 .LVL485: 2500:Src/main.c **** { 5935 .loc 2 2500 3 is_stmt 1 view .LVU1917 2500:Src/main.c **** { 5936 .loc 2 2500 6 is_stmt 0 view .LVU1918 5937 0018 08B1 cbz r0, .L247 2509:Src/main.c **** } 5938 .loc 2 2509 11 view .LVU1919 5939 001a 0120 movs r0, #1 5940 .LVL486: 2509:Src/main.c **** } 5941 .loc 2 2509 11 view .LVU1920 5942 001c F8E7 b .L241 5943 .LVL487: 5944 .L247: 2503:Src/main.c **** test = Unmount_SD("/"); // 0 - succ 5945 .loc 2 2503 4 is_stmt 1 view .LVU1921 2503:Src/main.c **** test = Unmount_SD("/"); // 0 - succ 5946 .loc 2 2503 11 is_stmt 0 view .LVU1922 5947 001e 1E22 movs r2, #30 5948 0020 2146 mov r1, r4 5949 0022 0548 ldr r0, .L248+8 5950 .LVL488: 2503:Src/main.c **** test = Unmount_SD("/"); // 0 - succ 5951 .loc 2 2503 11 view .LVU1923 5952 0024 FFF7FEFF bl Update_File_byte 5953 .LVL489: 2504:Src/main.c **** return test; 5954 .loc 2 2504 4 is_stmt 1 view .LVU1924 2504:Src/main.c **** return test; 5955 .loc 2 2504 11 is_stmt 0 view .LVU1925 5956 0028 0248 ldr r0, .L248+4 5957 002a FFF7FEFF bl Unmount_SD ARM GAS /tmp/ccqopZd5.s page 468 5958 .LVL490: 2505:Src/main.c **** } 5959 .loc 2 2505 4 is_stmt 1 view .LVU1926 2505:Src/main.c **** } 5960 .loc 2 2505 11 is_stmt 0 view .LVU1927 5961 002e EFE7 b .L241 5962 .L249: 5963 .align 2 5964 .L248: 5965 0030 000C0240 .word 1073875968 5966 0034 00000000 .word .LC0 5967 0038 00000000 .word .LC2 5968 .cfi_endproc 5969 .LFE1217: 5971 .section .text.SD_READ,"ax",%progbits 5972 .align 1 5973 .global SD_READ 5974 .syntax unified 5975 .thumb 5976 .thumb_func 5977 .fpu fpv5-d16 5979 SD_READ: 5980 .LVL491: 5981 .LFB1218: 2526:Src/main.c **** int test=0; 5982 .loc 2 2526 1 is_stmt 1 view -0 5983 .cfi_startproc 5984 @ args = 0, pretend = 0, frame = 0 5985 @ frame_needed = 0, uses_anonymous_args = 0 2526:Src/main.c **** int test=0; 5986 .loc 2 2526 1 is_stmt 0 view .LVU1929 5987 0000 38B5 push {r3, r4, r5, lr} 5988 .LCFI47: 5989 .cfi_def_cfa_offset 16 5990 .cfi_offset 3, -16 5991 .cfi_offset 4, -12 5992 .cfi_offset 5, -8 5993 .cfi_offset 14, -4 5994 0002 0446 mov r4, r0 2527:Src/main.c **** if (HAL_GPIO_ReadPin(SDMMC1_EN_GPIO_Port, SDMMC1_EN_Pin)==GPIO_PIN_RESET) 5995 .loc 2 2527 2 is_stmt 1 view .LVU1930 5996 .LVL492: 2528:Src/main.c **** { 5997 .loc 2 2528 2 view .LVU1931 2528:Src/main.c **** { 5998 .loc 2 2528 6 is_stmt 0 view .LVU1932 5999 0004 0121 movs r1, #1 6000 0006 0D48 ldr r0, .L257 6001 .LVL493: 2528:Src/main.c **** { 6002 .loc 2 2528 6 view .LVU1933 6003 0008 FFF7FEFF bl HAL_GPIO_ReadPin 6004 .LVL494: 2528:Src/main.c **** { 6005 .loc 2 2528 5 view .LVU1934 6006 000c 08B1 cbz r0, .L255 2546:Src/main.c **** } ARM GAS /tmp/ccqopZd5.s page 469 6007 .loc 2 2546 10 view .LVU1935 6008 000e 0120 movs r0, #1 6009 .LVL495: 6010 .L250: 2562:Src/main.c **** 6011 .loc 2 2562 1 view .LVU1936 6012 0010 38BD pop {r3, r4, r5, pc} 6013 .LVL496: 6014 .L255: 2530:Src/main.c **** if (test == 0) //0 - suc 6015 .loc 2 2530 3 is_stmt 1 view .LVU1937 2530:Src/main.c **** if (test == 0) //0 - suc 6016 .loc 2 2530 10 is_stmt 0 view .LVU1938 6017 0012 0B48 ldr r0, .L257+4 6018 0014 FFF7FEFF bl Mount_SD 6019 .LVL497: 2531:Src/main.c **** { 6020 .loc 2 2531 3 is_stmt 1 view .LVU1939 2531:Src/main.c **** { 6021 .loc 2 2531 6 is_stmt 0 view .LVU1940 6022 0018 08B1 cbz r0, .L256 2541:Src/main.c **** } 6023 .loc 2 2541 11 view .LVU1941 6024 001a 0120 movs r0, #1 6025 .LVL498: 2541:Src/main.c **** } 6026 .loc 2 2541 11 view .LVU1942 6027 001c F8E7 b .L250 6028 .LVL499: 6029 .L256: 2534:Src/main.c **** fgoto+=DL_8; 6030 .loc 2 2534 4 is_stmt 1 view .LVU1943 2534:Src/main.c **** fgoto+=DL_8; 6031 .loc 2 2534 11 is_stmt 0 view .LVU1944 6032 001e 094D ldr r5, .L257+8 6033 0020 2B68 ldr r3, [r5] 6034 0022 1E22 movs r2, #30 6035 0024 2146 mov r1, r4 6036 0026 0848 ldr r0, .L257+12 6037 .LVL500: 2534:Src/main.c **** fgoto+=DL_8; 6038 .loc 2 2534 11 view .LVU1945 6039 0028 FFF7FEFF bl Seek_Read_File 6040 .LVL501: 2535:Src/main.c **** test = Unmount_SD("/"); // 0 - succ 6041 .loc 2 2535 4 is_stmt 1 view .LVU1946 2535:Src/main.c **** test = Unmount_SD("/"); // 0 - succ 6042 .loc 2 2535 9 is_stmt 0 view .LVU1947 6043 002c 2B68 ldr r3, [r5] 6044 002e 1E33 adds r3, r3, #30 6045 0030 2B60 str r3, [r5] 2536:Src/main.c **** return test; 6046 .loc 2 2536 4 is_stmt 1 view .LVU1948 2536:Src/main.c **** return test; 6047 .loc 2 2536 11 is_stmt 0 view .LVU1949 6048 0032 0348 ldr r0, .L257+4 6049 0034 FFF7FEFF bl Unmount_SD ARM GAS /tmp/ccqopZd5.s page 470 6050 .LVL502: 2537:Src/main.c **** } 6051 .loc 2 2537 4 is_stmt 1 view .LVU1950 2537:Src/main.c **** } 6052 .loc 2 2537 11 is_stmt 0 view .LVU1951 6053 0038 EAE7 b .L250 6054 .L258: 6055 003a 00BF .align 2 6056 .L257: 6057 003c 000C0240 .word 1073875968 6058 0040 00000000 .word .LC0 6059 0044 00000000 .word .LANCHOR14 6060 0048 00000000 .word .LC2 6061 .cfi_endproc 6062 .LFE1218: 6064 .section .text.SD_REMOVE,"ax",%progbits 6065 .align 1 6066 .global SD_REMOVE 6067 .syntax unified 6068 .thumb 6069 .thumb_func 6070 .fpu fpv5-d16 6072 SD_REMOVE: 6073 .LFB1219: 2565:Src/main.c **** int test=0; 6074 .loc 2 2565 1 is_stmt 1 view -0 6075 .cfi_startproc 6076 @ args = 0, pretend = 0, frame = 0 6077 @ frame_needed = 0, uses_anonymous_args = 0 6078 0000 10B5 push {r4, lr} 6079 .LCFI48: 6080 .cfi_def_cfa_offset 8 6081 .cfi_offset 4, -8 6082 .cfi_offset 14, -4 2566:Src/main.c **** if (HAL_GPIO_ReadPin(SDMMC1_EN_GPIO_Port, SDMMC1_EN_Pin)==GPIO_PIN_RESET) 6083 .loc 2 2566 2 view .LVU1953 6084 .LVL503: 2567:Src/main.c **** { 6085 .loc 2 2567 2 view .LVU1954 2567:Src/main.c **** { 6086 .loc 2 2567 6 is_stmt 0 view .LVU1955 6087 0002 0121 movs r1, #1 6088 0004 0B48 ldr r0, .L266 6089 0006 FFF7FEFF bl HAL_GPIO_ReadPin 6090 .LVL504: 2567:Src/main.c **** { 6091 .loc 2 2567 5 view .LVU1956 6092 000a 08B1 cbz r0, .L264 2585:Src/main.c **** } 6093 .loc 2 2585 10 view .LVU1957 6094 000c 0120 movs r0, #1 6095 .LVL505: 6096 .L259: 2587:Src/main.c **** 6097 .loc 2 2587 1 view .LVU1958 6098 000e 10BD pop {r4, pc} 6099 .LVL506: ARM GAS /tmp/ccqopZd5.s page 471 6100 .L264: 2569:Src/main.c **** if (test==FR_OK) 6101 .loc 2 2569 3 is_stmt 1 view .LVU1959 2569:Src/main.c **** if (test==FR_OK) 6102 .loc 2 2569 10 is_stmt 0 view .LVU1960 6103 0010 0948 ldr r0, .L266+4 6104 0012 FFF7FEFF bl Mount_SD 6105 .LVL507: 2570:Src/main.c **** { 6106 .loc 2 2570 3 is_stmt 1 view .LVU1961 2570:Src/main.c **** { 6107 .loc 2 2570 6 is_stmt 0 view .LVU1962 6108 0016 08B1 cbz r0, .L265 2580:Src/main.c **** } 6109 .loc 2 2580 11 view .LVU1963 6110 0018 0120 movs r0, #1 6111 .LVL508: 2580:Src/main.c **** } 6112 .loc 2 2580 11 view .LVU1964 6113 001a F8E7 b .L259 6114 .LVL509: 6115 .L265: 2572:Src/main.c **** test = Create_File("FILE1.TXT"); // 0 -suc 6116 .loc 2 2572 4 is_stmt 1 view .LVU1965 2572:Src/main.c **** test = Create_File("FILE1.TXT"); // 0 -suc 6117 .loc 2 2572 11 is_stmt 0 view .LVU1966 6118 001c 074C ldr r4, .L266+8 6119 001e 2046 mov r0, r4 6120 .LVL510: 2572:Src/main.c **** test = Create_File("FILE1.TXT"); // 0 -suc 6121 .loc 2 2572 11 view .LVU1967 6122 0020 FFF7FEFF bl Remove_File 6123 .LVL511: 2573:Src/main.c **** //test = Write_File ("FILE1.TXT", "____OSGG main borad information. Program made by Kazakov Vikt 6124 .loc 2 2573 4 is_stmt 1 view .LVU1968 2573:Src/main.c **** //test = Write_File ("FILE1.TXT", "____OSGG main borad information. Program made by Kazakov Vikt 6125 .loc 2 2573 11 is_stmt 0 view .LVU1969 6126 0024 2046 mov r0, r4 6127 0026 FFF7FEFF bl Create_File 6128 .LVL512: 2575:Src/main.c **** return test; 6129 .loc 2 2575 4 is_stmt 1 view .LVU1970 2575:Src/main.c **** return test; 6130 .loc 2 2575 11 is_stmt 0 view .LVU1971 6131 002a 0348 ldr r0, .L266+4 6132 002c FFF7FEFF bl Unmount_SD 6133 .LVL513: 2576:Src/main.c **** } 6134 .loc 2 2576 4 is_stmt 1 view .LVU1972 2576:Src/main.c **** } 6135 .loc 2 2576 11 is_stmt 0 view .LVU1973 6136 0030 EDE7 b .L259 6137 .L267: 6138 0032 00BF .align 2 6139 .L266: 6140 0034 000C0240 .word 1073875968 6141 0038 00000000 .word .LC0 ARM GAS /tmp/ccqopZd5.s page 472 6142 003c 00000000 .word .LC2 6143 .cfi_endproc 6144 .LFE1219: 6146 .section .text.USART_TX,"ax",%progbits 6147 .align 1 6148 .global USART_TX 6149 .syntax unified 6150 .thumb 6151 .thumb_func 6152 .fpu fpv5-d16 6154 USART_TX: 6155 .LVL514: 6156 .LFB1220: 2591:Src/main.c **** uint16_t ind = 0; 6157 .loc 2 2591 1 is_stmt 1 view -0 6158 .cfi_startproc 6159 @ args = 0, pretend = 0, frame = 0 6160 @ frame_needed = 0, uses_anonymous_args = 0 6161 @ link register save eliminated. 2592:Src/main.c **** while (indRDR, USART_RDR_RDR) & 0xFFU); 3661:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 3662:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3663:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 3664:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Read Receiver Data register (Receive Data value, 9 bits) 3665:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll RDR RDR LL_USART_ReceiveData9 3666:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 3667:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Value between Min_Data=0x00 and Max_Data=0x1FF 3668:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3669:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint16_t LL_USART_ReceiveData9(const USART_TypeDef *USARTx) 3670:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 3671:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return (uint16_t)(READ_BIT(USARTx->RDR, USART_RDR_RDR)); 3672:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 3673:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3674:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 3675:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Write in Transmitter Data Register (Transmit Data value, 8 bits) 3676:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll TDR TDR LL_USART_TransmitData8 3677:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 3678:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param Value between Min_Data=0x00 and Max_Data=0xFF 3679:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 3680:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3681:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_TransmitData8(USART_TypeDef *USARTx, uint8_t Value) 6199 .loc 7 3681 22 view .LVU1988 6200 .LBB498: 3682:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 3683:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** USARTx->TDR = Value; 6201 .loc 7 3683 3 view .LVU1989 ARM GAS /tmp/ccqopZd5.s page 474 6202 .loc 7 3683 15 is_stmt 0 view .LVU1990 6203 0014 044A ldr r2, .L275 6204 0016 9462 str r4, [r2, #40] 6205 .LVL519: 6206 .loc 7 3683 15 view .LVU1991 6207 .LBE498: 6208 .LBE497: 2597:Src/main.c **** } 6209 .loc 2 2597 5 is_stmt 1 view .LVU1992 2597:Src/main.c **** } 6210 .loc 2 2597 8 is_stmt 0 view .LVU1993 6211 0018 0133 adds r3, r3, #1 6212 .LVL520: 2597:Src/main.c **** } 6213 .loc 2 2597 8 view .LVU1994 6214 001a 9BB2 uxth r3, r3 6215 .LVL521: 2593:Src/main.c **** { 6216 .loc 2 2593 9 is_stmt 1 view .LVU1995 6217 001c 8B42 cmp r3, r1 6218 001e F3D3 bcc .L270 2599:Src/main.c **** 6219 .loc 2 2599 1 is_stmt 0 view .LVU1996 6220 0020 5DF8044B ldr r4, [sp], #4 6221 .LCFI50: 6222 .cfi_restore 4 6223 .cfi_def_cfa_offset 0 6224 0024 7047 bx lr 6225 .L274: 2599:Src/main.c **** 6226 .loc 2 2599 1 view .LVU1997 6227 0026 7047 bx lr 6228 .L276: 6229 .align 2 6230 .L275: 6231 0028 00100140 .word 1073811456 6232 .cfi_endproc 6233 .LFE1220: 6235 .section .text.USART_TX_DMA,"ax",%progbits 6236 .align 1 6237 .global USART_TX_DMA 6238 .syntax unified 6239 .thumb 6240 .thumb_func 6241 .fpu fpv5-d16 6243 USART_TX_DMA: 6244 .LFB1221: 2602:Src/main.c **** while (u_tx_flg) {}//Wait until previous transfer not complete. u_tx_flg is resetting in DMA inter 6245 .loc 2 2602 1 is_stmt 1 view -0 6246 .cfi_startproc 6247 @ args = 0, pretend = 0, frame = 0 6248 @ frame_needed = 0, uses_anonymous_args = 0 6249 @ link register save eliminated. 6250 .LVL522: 6251 .L278: 2603:Src/main.c **** LL_DMA_DisableStream(DMA2, LL_DMA_STREAM_7); 6252 .loc 2 2603 20 discriminator 1 view .LVU1999 ARM GAS /tmp/ccqopZd5.s page 475 2603:Src/main.c **** LL_DMA_DisableStream(DMA2, LL_DMA_STREAM_7); 6253 .loc 2 2603 8 discriminator 1 view .LVU2000 2603:Src/main.c **** LL_DMA_DisableStream(DMA2, LL_DMA_STREAM_7); 6254 .loc 2 2603 9 is_stmt 0 discriminator 1 view .LVU2001 6255 0000 0D4B ldr r3, .L279 6256 0002 1B78 ldrb r3, [r3] @ zero_extendqisi2 2603:Src/main.c **** LL_DMA_DisableStream(DMA2, LL_DMA_STREAM_7); 6257 .loc 2 2603 8 discriminator 1 view .LVU2002 6258 0004 002B cmp r3, #0 6259 0006 FBD1 bne .L278 2604:Src/main.c **** LL_DMA_SetDataLength(DMA2, LL_DMA_STREAM_7, sz); 6260 .loc 2 2604 2 is_stmt 1 view .LVU2003 6261 .LVL523: 6262 .LBB499: 6263 .LBI499: 517:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 6264 .loc 6 517 22 view .LVU2004 6265 .LBB500: 519:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 6266 .loc 6 519 3 view .LVU2005 6267 0008 0C4B ldr r3, .L279+4 6268 000a D3F8B820 ldr r2, [r3, #184] 6269 000e 22F00102 bic r2, r2, #1 6270 0012 C3F8B820 str r2, [r3, #184] 6271 .LVL524: 519:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 6272 .loc 6 519 3 is_stmt 0 view .LVU2006 6273 .LBE500: 6274 .LBE499: 2605:Src/main.c **** LL_DMA_EnableStream(DMA2, LL_DMA_STREAM_7); 6275 .loc 2 2605 3 is_stmt 1 view .LVU2007 6276 .LBB501: 6277 .LBI501: 971:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 6278 .loc 6 971 22 view .LVU2008 6279 .LBB502: 973:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 6280 .loc 6 973 3 view .LVU2009 6281 0016 D3F8BC10 ldr r1, [r3, #188] 6282 001a 094A ldr r2, .L279+8 6283 001c 0A40 ands r2, r2, r1 6284 001e 1043 orrs r0, r0, r2 6285 .LVL525: 973:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 6286 .loc 6 973 3 is_stmt 0 view .LVU2010 6287 0020 C3F8BC00 str r0, [r3, #188] 6288 .LVL526: 973:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 6289 .loc 6 973 3 view .LVU2011 6290 .LBE502: 6291 .LBE501: 2606:Src/main.c **** u_tx_flg = 1;//indicate that transfer begin 6292 .loc 2 2606 3 is_stmt 1 view .LVU2012 6293 .LBB503: 6294 .LBI503: 497:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 6295 .loc 6 497 22 view .LVU2013 ARM GAS /tmp/ccqopZd5.s page 476 6296 .LBB504: 499:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 6297 .loc 6 499 3 view .LVU2014 6298 0024 D3F8B820 ldr r2, [r3, #184] 6299 0028 42F00102 orr r2, r2, #1 6300 002c C3F8B820 str r2, [r3, #184] 6301 .LVL527: 499:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 6302 .loc 6 499 3 is_stmt 0 view .LVU2015 6303 .LBE504: 6304 .LBE503: 2607:Src/main.c **** } 6305 .loc 2 2607 2 is_stmt 1 view .LVU2016 2607:Src/main.c **** } 6306 .loc 2 2607 11 is_stmt 0 view .LVU2017 6307 0030 014B ldr r3, .L279 6308 0032 0122 movs r2, #1 6309 0034 1A70 strb r2, [r3] 2608:Src/main.c **** 6310 .loc 2 2608 1 view .LVU2018 6311 0036 7047 bx lr 6312 .L280: 6313 .align 2 6314 .L279: 6315 0038 00000000 .word .LANCHOR16 6316 003c 00640240 .word 1073898496 6317 0040 0000FFFF .word -65536 6318 .cfi_endproc 6319 .LFE1221: 6321 .section .text.Error_Handler,"ax",%progbits 6322 .align 1 6323 .global Error_Handler 6324 .syntax unified 6325 .thumb 6326 .thumb_func 6327 .fpu fpv5-d16 6329 Error_Handler: 6330 .LFB1223: 2616:Src/main.c **** //------------------------------------------------------- 2617:Src/main.c **** /* USER CODE END 4 */ 2618:Src/main.c **** 2619:Src/main.c **** /** 2620:Src/main.c **** * @brief This function is executed in case of error occurrence. 2621:Src/main.c **** * @retval None 2622:Src/main.c **** */ 2623:Src/main.c **** void Error_Handler(void) 2624:Src/main.c **** { 6331 .loc 2 2624 1 is_stmt 1 view -0 6332 .cfi_startproc 6333 @ Volatile: function does not return. 6334 @ args = 0, pretend = 0, frame = 0 6335 @ frame_needed = 0, uses_anonymous_args = 0 6336 @ link register save eliminated. 2625:Src/main.c **** /* USER CODE BEGIN Error_Handler_Debug */ 2626:Src/main.c **** /* User can add his own implementation to report the HAL error return state */ 2627:Src/main.c **** __disable_irq(); 6337 .loc 2 2627 3 view .LVU2020 ARM GAS /tmp/ccqopZd5.s page 477 6338 .LBB505: 6339 .LBI505: 140:Drivers/CMSIS/Include/cmsis_gcc.h **** { 6340 .loc 8 140 27 view .LVU2021 6341 .LBB506: 142:Drivers/CMSIS/Include/cmsis_gcc.h **** } 6342 .loc 8 142 3 view .LVU2022 6343 .syntax unified 6344 @ 142 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 6345 0000 72B6 cpsid i 6346 @ 0 "" 2 6347 .thumb 6348 .syntax unified 6349 .L282: 6350 .LBE506: 6351 .LBE505: 2628:Src/main.c **** while (1) 6352 .loc 2 2628 3 discriminator 1 view .LVU2023 2629:Src/main.c **** { 2630:Src/main.c **** } 6353 .loc 2 2630 3 discriminator 1 view .LVU2024 2628:Src/main.c **** while (1) 6354 .loc 2 2628 9 discriminator 1 view .LVU2025 6355 0002 FEE7 b .L282 6356 .cfi_endproc 6357 .LFE1223: 6359 .section .text.MX_ADC1_Init,"ax",%progbits 6360 .align 1 6361 .syntax unified 6362 .thumb 6363 .thumb_func 6364 .fpu fpv5-d16 6366 MX_ADC1_Init: 6367 .LFB1188: 747:Src/main.c **** 6368 .loc 2 747 1 view -0 6369 .cfi_startproc 6370 @ args = 0, pretend = 0, frame = 16 6371 @ frame_needed = 0, uses_anonymous_args = 0 6372 0000 00B5 push {lr} 6373 .LCFI51: 6374 .cfi_def_cfa_offset 4 6375 .cfi_offset 14, -4 6376 0002 85B0 sub sp, sp, #20 6377 .LCFI52: 6378 .cfi_def_cfa_offset 24 753:Src/main.c **** 6379 .loc 2 753 3 view .LVU2027 753:Src/main.c **** 6380 .loc 2 753 26 is_stmt 0 view .LVU2028 6381 0004 0023 movs r3, #0 6382 0006 0093 str r3, [sp] 6383 0008 0193 str r3, [sp, #4] 6384 000a 0293 str r3, [sp, #8] 6385 000c 0393 str r3, [sp, #12] 761:Src/main.c **** hadc1.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV8; 6386 .loc 2 761 3 is_stmt 1 view .LVU2029 ARM GAS /tmp/ccqopZd5.s page 478 761:Src/main.c **** hadc1.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV8; 6387 .loc 2 761 18 is_stmt 0 view .LVU2030 6388 000e 2B48 ldr r0, .L297 6389 0010 2B4A ldr r2, .L297+4 6390 0012 0260 str r2, [r0] 762:Src/main.c **** hadc1.Init.Resolution = ADC_RESOLUTION_12B; 6391 .loc 2 762 3 is_stmt 1 view .LVU2031 762:Src/main.c **** hadc1.Init.Resolution = ADC_RESOLUTION_12B; 6392 .loc 2 762 29 is_stmt 0 view .LVU2032 6393 0014 4FF44032 mov r2, #196608 6394 0018 4260 str r2, [r0, #4] 763:Src/main.c **** hadc1.Init.ScanConvMode = ADC_SCAN_ENABLE; 6395 .loc 2 763 3 is_stmt 1 view .LVU2033 763:Src/main.c **** hadc1.Init.ScanConvMode = ADC_SCAN_ENABLE; 6396 .loc 2 763 25 is_stmt 0 view .LVU2034 6397 001a 8360 str r3, [r0, #8] 764:Src/main.c **** hadc1.Init.ContinuousConvMode = DISABLE; 6398 .loc 2 764 3 is_stmt 1 view .LVU2035 764:Src/main.c **** hadc1.Init.ContinuousConvMode = DISABLE; 6399 .loc 2 764 27 is_stmt 0 view .LVU2036 6400 001c 0122 movs r2, #1 6401 001e 0261 str r2, [r0, #16] 765:Src/main.c **** hadc1.Init.DiscontinuousConvMode = DISABLE; 6402 .loc 2 765 3 is_stmt 1 view .LVU2037 765:Src/main.c **** hadc1.Init.DiscontinuousConvMode = DISABLE; 6403 .loc 2 765 33 is_stmt 0 view .LVU2038 6404 0020 8361 str r3, [r0, #24] 766:Src/main.c **** hadc1.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE; 6405 .loc 2 766 3 is_stmt 1 view .LVU2039 766:Src/main.c **** hadc1.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE; 6406 .loc 2 766 36 is_stmt 0 view .LVU2040 6407 0022 80F82030 strb r3, [r0, #32] 767:Src/main.c **** hadc1.Init.ExternalTrigConv = ADC_SOFTWARE_START; 6408 .loc 2 767 3 is_stmt 1 view .LVU2041 767:Src/main.c **** hadc1.Init.ExternalTrigConv = ADC_SOFTWARE_START; 6409 .loc 2 767 35 is_stmt 0 view .LVU2042 6410 0026 C362 str r3, [r0, #44] 768:Src/main.c **** hadc1.Init.DataAlign = ADC_DATAALIGN_RIGHT; 6411 .loc 2 768 3 is_stmt 1 view .LVU2043 768:Src/main.c **** hadc1.Init.DataAlign = ADC_DATAALIGN_RIGHT; 6412 .loc 2 768 31 is_stmt 0 view .LVU2044 6413 0028 2649 ldr r1, .L297+8 6414 002a 8162 str r1, [r0, #40] 769:Src/main.c **** hadc1.Init.NbrOfConversion = 5; 6415 .loc 2 769 3 is_stmt 1 view .LVU2045 769:Src/main.c **** hadc1.Init.NbrOfConversion = 5; 6416 .loc 2 769 24 is_stmt 0 view .LVU2046 6417 002c C360 str r3, [r0, #12] 770:Src/main.c **** hadc1.Init.DMAContinuousRequests = DISABLE; 6418 .loc 2 770 3 is_stmt 1 view .LVU2047 770:Src/main.c **** hadc1.Init.DMAContinuousRequests = DISABLE; 6419 .loc 2 770 30 is_stmt 0 view .LVU2048 6420 002e 0521 movs r1, #5 6421 0030 C161 str r1, [r0, #28] 771:Src/main.c **** hadc1.Init.EOCSelection = ADC_EOC_SINGLE_CONV; 6422 .loc 2 771 3 is_stmt 1 view .LVU2049 771:Src/main.c **** hadc1.Init.EOCSelection = ADC_EOC_SINGLE_CONV; ARM GAS /tmp/ccqopZd5.s page 479 6423 .loc 2 771 36 is_stmt 0 view .LVU2050 6424 0032 80F83030 strb r3, [r0, #48] 772:Src/main.c **** if (HAL_ADC_Init(&hadc1) != HAL_OK) 6425 .loc 2 772 3 is_stmt 1 view .LVU2051 772:Src/main.c **** if (HAL_ADC_Init(&hadc1) != HAL_OK) 6426 .loc 2 772 27 is_stmt 0 view .LVU2052 6427 0036 4261 str r2, [r0, #20] 773:Src/main.c **** { 6428 .loc 2 773 3 is_stmt 1 view .LVU2053 773:Src/main.c **** { 6429 .loc 2 773 7 is_stmt 0 view .LVU2054 6430 0038 FFF7FEFF bl HAL_ADC_Init 6431 .LVL528: 773:Src/main.c **** { 6432 .loc 2 773 6 view .LVU2055 6433 003c 0028 cmp r0, #0 6434 003e 31D1 bne .L291 780:Src/main.c **** sConfig.Rank = ADC_REGULAR_RANK_1; 6435 .loc 2 780 3 is_stmt 1 view .LVU2056 780:Src/main.c **** sConfig.Rank = ADC_REGULAR_RANK_1; 6436 .loc 2 780 19 is_stmt 0 view .LVU2057 6437 0040 0923 movs r3, #9 6438 0042 0093 str r3, [sp] 781:Src/main.c **** sConfig.SamplingTime = ADC_SAMPLETIME_480CYCLES; 6439 .loc 2 781 3 is_stmt 1 view .LVU2058 781:Src/main.c **** sConfig.SamplingTime = ADC_SAMPLETIME_480CYCLES; 6440 .loc 2 781 16 is_stmt 0 view .LVU2059 6441 0044 0123 movs r3, #1 6442 0046 0193 str r3, [sp, #4] 782:Src/main.c **** if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 6443 .loc 2 782 3 is_stmt 1 view .LVU2060 782:Src/main.c **** if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 6444 .loc 2 782 24 is_stmt 0 view .LVU2061 6445 0048 0723 movs r3, #7 6446 004a 0293 str r3, [sp, #8] 783:Src/main.c **** { 6447 .loc 2 783 3 is_stmt 1 view .LVU2062 783:Src/main.c **** { 6448 .loc 2 783 7 is_stmt 0 view .LVU2063 6449 004c 6946 mov r1, sp 6450 004e 1B48 ldr r0, .L297 6451 0050 FFF7FEFF bl HAL_ADC_ConfigChannel 6452 .LVL529: 783:Src/main.c **** { 6453 .loc 2 783 6 view .LVU2064 6454 0054 40BB cbnz r0, .L292 790:Src/main.c **** sConfig.Rank = ADC_REGULAR_RANK_2; 6455 .loc 2 790 3 is_stmt 1 view .LVU2065 790:Src/main.c **** sConfig.Rank = ADC_REGULAR_RANK_2; 6456 .loc 2 790 19 is_stmt 0 view .LVU2066 6457 0056 0823 movs r3, #8 6458 0058 0093 str r3, [sp] 791:Src/main.c **** if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 6459 .loc 2 791 3 is_stmt 1 view .LVU2067 791:Src/main.c **** if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 6460 .loc 2 791 16 is_stmt 0 view .LVU2068 6461 005a 0223 movs r3, #2 ARM GAS /tmp/ccqopZd5.s page 480 6462 005c 0193 str r3, [sp, #4] 792:Src/main.c **** { 6463 .loc 2 792 3 is_stmt 1 view .LVU2069 792:Src/main.c **** { 6464 .loc 2 792 7 is_stmt 0 view .LVU2070 6465 005e 6946 mov r1, sp 6466 0060 1648 ldr r0, .L297 6467 0062 FFF7FEFF bl HAL_ADC_ConfigChannel 6468 .LVL530: 792:Src/main.c **** { 6469 .loc 2 792 6 view .LVU2071 6470 0066 08BB cbnz r0, .L293 799:Src/main.c **** sConfig.Rank = ADC_REGULAR_RANK_3; 6471 .loc 2 799 3 is_stmt 1 view .LVU2072 799:Src/main.c **** sConfig.Rank = ADC_REGULAR_RANK_3; 6472 .loc 2 799 19 is_stmt 0 view .LVU2073 6473 0068 0223 movs r3, #2 6474 006a 0093 str r3, [sp] 800:Src/main.c **** if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 6475 .loc 2 800 3 is_stmt 1 view .LVU2074 800:Src/main.c **** if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 6476 .loc 2 800 16 is_stmt 0 view .LVU2075 6477 006c 0323 movs r3, #3 6478 006e 0193 str r3, [sp, #4] 801:Src/main.c **** { 6479 .loc 2 801 3 is_stmt 1 view .LVU2076 801:Src/main.c **** { 6480 .loc 2 801 7 is_stmt 0 view .LVU2077 6481 0070 6946 mov r1, sp 6482 0072 1248 ldr r0, .L297 6483 0074 FFF7FEFF bl HAL_ADC_ConfigChannel 6484 .LVL531: 801:Src/main.c **** { 6485 .loc 2 801 6 view .LVU2078 6486 0078 D0B9 cbnz r0, .L294 808:Src/main.c **** sConfig.Rank = ADC_REGULAR_RANK_4; 6487 .loc 2 808 3 is_stmt 1 view .LVU2079 808:Src/main.c **** sConfig.Rank = ADC_REGULAR_RANK_4; 6488 .loc 2 808 19 is_stmt 0 view .LVU2080 6489 007a 0A23 movs r3, #10 6490 007c 0093 str r3, [sp] 809:Src/main.c **** if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 6491 .loc 2 809 3 is_stmt 1 view .LVU2081 809:Src/main.c **** if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 6492 .loc 2 809 16 is_stmt 0 view .LVU2082 6493 007e 0423 movs r3, #4 6494 0080 0193 str r3, [sp, #4] 810:Src/main.c **** { 6495 .loc 2 810 3 is_stmt 1 view .LVU2083 810:Src/main.c **** { 6496 .loc 2 810 7 is_stmt 0 view .LVU2084 6497 0082 6946 mov r1, sp 6498 0084 0D48 ldr r0, .L297 6499 0086 FFF7FEFF bl HAL_ADC_ConfigChannel 6500 .LVL532: 810:Src/main.c **** { 6501 .loc 2 810 6 view .LVU2085 ARM GAS /tmp/ccqopZd5.s page 481 6502 008a 98B9 cbnz r0, .L295 817:Src/main.c **** sConfig.Rank = ADC_REGULAR_RANK_5; 6503 .loc 2 817 3 is_stmt 1 view .LVU2086 817:Src/main.c **** sConfig.Rank = ADC_REGULAR_RANK_5; 6504 .loc 2 817 19 is_stmt 0 view .LVU2087 6505 008c 0B23 movs r3, #11 6506 008e 0093 str r3, [sp] 818:Src/main.c **** if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 6507 .loc 2 818 3 is_stmt 1 view .LVU2088 818:Src/main.c **** if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 6508 .loc 2 818 16 is_stmt 0 view .LVU2089 6509 0090 0523 movs r3, #5 6510 0092 0193 str r3, [sp, #4] 819:Src/main.c **** { 6511 .loc 2 819 3 is_stmt 1 view .LVU2090 819:Src/main.c **** { 6512 .loc 2 819 7 is_stmt 0 view .LVU2091 6513 0094 6946 mov r1, sp 6514 0096 0948 ldr r0, .L297 6515 0098 FFF7FEFF bl HAL_ADC_ConfigChannel 6516 .LVL533: 819:Src/main.c **** { 6517 .loc 2 819 6 view .LVU2092 6518 009c 60B9 cbnz r0, .L296 827:Src/main.c **** 6519 .loc 2 827 1 view .LVU2093 6520 009e 05B0 add sp, sp, #20 6521 .LCFI53: 6522 .cfi_remember_state 6523 .cfi_def_cfa_offset 4 6524 @ sp needed 6525 00a0 5DF804FB ldr pc, [sp], #4 6526 .L291: 6527 .LCFI54: 6528 .cfi_restore_state 775:Src/main.c **** } 6529 .loc 2 775 5 is_stmt 1 view .LVU2094 6530 00a4 FFF7FEFF bl Error_Handler 6531 .LVL534: 6532 .L292: 785:Src/main.c **** } 6533 .loc 2 785 5 view .LVU2095 6534 00a8 FFF7FEFF bl Error_Handler 6535 .LVL535: 6536 .L293: 794:Src/main.c **** } 6537 .loc 2 794 5 view .LVU2096 6538 00ac FFF7FEFF bl Error_Handler 6539 .LVL536: 6540 .L294: 803:Src/main.c **** } 6541 .loc 2 803 5 view .LVU2097 6542 00b0 FFF7FEFF bl Error_Handler 6543 .LVL537: 6544 .L295: 812:Src/main.c **** } 6545 .loc 2 812 5 view .LVU2098 ARM GAS /tmp/ccqopZd5.s page 482 6546 00b4 FFF7FEFF bl Error_Handler 6547 .LVL538: 6548 .L296: 821:Src/main.c **** } 6549 .loc 2 821 5 view .LVU2099 6550 00b8 FFF7FEFF bl Error_Handler 6551 .LVL539: 6552 .L298: 6553 .align 2 6554 .L297: 6555 00bc 00000000 .word .LANCHOR31 6556 00c0 00200140 .word 1073815552 6557 00c4 0100000F .word 251658241 6558 .cfi_endproc 6559 .LFE1188: 6561 .section .text.MX_ADC3_Init,"ax",%progbits 6562 .align 1 6563 .syntax unified 6564 .thumb 6565 .thumb_func 6566 .fpu fpv5-d16 6568 MX_ADC3_Init: 6569 .LFB1189: 835:Src/main.c **** 6570 .loc 2 835 1 view -0 6571 .cfi_startproc 6572 @ args = 0, pretend = 0, frame = 16 6573 @ frame_needed = 0, uses_anonymous_args = 0 6574 0000 00B5 push {lr} 6575 .LCFI55: 6576 .cfi_def_cfa_offset 4 6577 .cfi_offset 14, -4 6578 0002 85B0 sub sp, sp, #20 6579 .LCFI56: 6580 .cfi_def_cfa_offset 24 841:Src/main.c **** 6581 .loc 2 841 3 view .LVU2101 841:Src/main.c **** 6582 .loc 2 841 26 is_stmt 0 view .LVU2102 6583 0004 0023 movs r3, #0 6584 0006 0093 str r3, [sp] 6585 0008 0193 str r3, [sp, #4] 6586 000a 0293 str r3, [sp, #8] 6587 000c 0393 str r3, [sp, #12] 849:Src/main.c **** hadc3.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV8; 6588 .loc 2 849 3 is_stmt 1 view .LVU2103 849:Src/main.c **** hadc3.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV8; 6589 .loc 2 849 18 is_stmt 0 view .LVU2104 6590 000e 1448 ldr r0, .L305 6591 0010 144A ldr r2, .L305+4 6592 0012 0260 str r2, [r0] 850:Src/main.c **** hadc3.Init.Resolution = ADC_RESOLUTION_12B; 6593 .loc 2 850 3 is_stmt 1 view .LVU2105 850:Src/main.c **** hadc3.Init.Resolution = ADC_RESOLUTION_12B; 6594 .loc 2 850 29 is_stmt 0 view .LVU2106 6595 0014 4FF44032 mov r2, #196608 6596 0018 4260 str r2, [r0, #4] ARM GAS /tmp/ccqopZd5.s page 483 851:Src/main.c **** hadc3.Init.ScanConvMode = ADC_SCAN_DISABLE; 6597 .loc 2 851 3 is_stmt 1 view .LVU2107 851:Src/main.c **** hadc3.Init.ScanConvMode = ADC_SCAN_DISABLE; 6598 .loc 2 851 25 is_stmt 0 view .LVU2108 6599 001a 8360 str r3, [r0, #8] 852:Src/main.c **** hadc3.Init.ContinuousConvMode = DISABLE; 6600 .loc 2 852 3 is_stmt 1 view .LVU2109 852:Src/main.c **** hadc3.Init.ContinuousConvMode = DISABLE; 6601 .loc 2 852 27 is_stmt 0 view .LVU2110 6602 001c 0361 str r3, [r0, #16] 853:Src/main.c **** hadc3.Init.DiscontinuousConvMode = DISABLE; 6603 .loc 2 853 3 is_stmt 1 view .LVU2111 853:Src/main.c **** hadc3.Init.DiscontinuousConvMode = DISABLE; 6604 .loc 2 853 33 is_stmt 0 view .LVU2112 6605 001e 8361 str r3, [r0, #24] 854:Src/main.c **** hadc3.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE; 6606 .loc 2 854 3 is_stmt 1 view .LVU2113 854:Src/main.c **** hadc3.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE; 6607 .loc 2 854 36 is_stmt 0 view .LVU2114 6608 0020 80F82030 strb r3, [r0, #32] 855:Src/main.c **** hadc3.Init.ExternalTrigConv = ADC_SOFTWARE_START; 6609 .loc 2 855 3 is_stmt 1 view .LVU2115 855:Src/main.c **** hadc3.Init.ExternalTrigConv = ADC_SOFTWARE_START; 6610 .loc 2 855 35 is_stmt 0 view .LVU2116 6611 0024 C362 str r3, [r0, #44] 856:Src/main.c **** hadc3.Init.DataAlign = ADC_DATAALIGN_RIGHT; 6612 .loc 2 856 3 is_stmt 1 view .LVU2117 856:Src/main.c **** hadc3.Init.DataAlign = ADC_DATAALIGN_RIGHT; 6613 .loc 2 856 31 is_stmt 0 view .LVU2118 6614 0026 104A ldr r2, .L305+8 6615 0028 8262 str r2, [r0, #40] 857:Src/main.c **** hadc3.Init.NbrOfConversion = 1; 6616 .loc 2 857 3 is_stmt 1 view .LVU2119 857:Src/main.c **** hadc3.Init.NbrOfConversion = 1; 6617 .loc 2 857 24 is_stmt 0 view .LVU2120 6618 002a C360 str r3, [r0, #12] 858:Src/main.c **** hadc3.Init.DMAContinuousRequests = DISABLE; 6619 .loc 2 858 3 is_stmt 1 view .LVU2121 858:Src/main.c **** hadc3.Init.DMAContinuousRequests = DISABLE; 6620 .loc 2 858 30 is_stmt 0 view .LVU2122 6621 002c 0122 movs r2, #1 6622 002e C261 str r2, [r0, #28] 859:Src/main.c **** hadc3.Init.EOCSelection = ADC_EOC_SINGLE_CONV; 6623 .loc 2 859 3 is_stmt 1 view .LVU2123 859:Src/main.c **** hadc3.Init.EOCSelection = ADC_EOC_SINGLE_CONV; 6624 .loc 2 859 36 is_stmt 0 view .LVU2124 6625 0030 80F83030 strb r3, [r0, #48] 860:Src/main.c **** if (HAL_ADC_Init(&hadc3) != HAL_OK) 6626 .loc 2 860 3 is_stmt 1 view .LVU2125 860:Src/main.c **** if (HAL_ADC_Init(&hadc3) != HAL_OK) 6627 .loc 2 860 27 is_stmt 0 view .LVU2126 6628 0034 4261 str r2, [r0, #20] 861:Src/main.c **** { 6629 .loc 2 861 3 is_stmt 1 view .LVU2127 861:Src/main.c **** { 6630 .loc 2 861 7 is_stmt 0 view .LVU2128 6631 0036 FFF7FEFF bl HAL_ADC_Init ARM GAS /tmp/ccqopZd5.s page 484 6632 .LVL540: 861:Src/main.c **** { 6633 .loc 2 861 6 view .LVU2129 6634 003a 68B9 cbnz r0, .L303 868:Src/main.c **** sConfig.Rank = ADC_REGULAR_RANK_1; 6635 .loc 2 868 3 is_stmt 1 view .LVU2130 868:Src/main.c **** sConfig.Rank = ADC_REGULAR_RANK_1; 6636 .loc 2 868 19 is_stmt 0 view .LVU2131 6637 003c 0F23 movs r3, #15 6638 003e 0093 str r3, [sp] 869:Src/main.c **** sConfig.SamplingTime = ADC_SAMPLETIME_480CYCLES; 6639 .loc 2 869 3 is_stmt 1 view .LVU2132 869:Src/main.c **** sConfig.SamplingTime = ADC_SAMPLETIME_480CYCLES; 6640 .loc 2 869 16 is_stmt 0 view .LVU2133 6641 0040 0123 movs r3, #1 6642 0042 0193 str r3, [sp, #4] 870:Src/main.c **** if (HAL_ADC_ConfigChannel(&hadc3, &sConfig) != HAL_OK) 6643 .loc 2 870 3 is_stmt 1 view .LVU2134 870:Src/main.c **** if (HAL_ADC_ConfigChannel(&hadc3, &sConfig) != HAL_OK) 6644 .loc 2 870 24 is_stmt 0 view .LVU2135 6645 0044 0723 movs r3, #7 6646 0046 0293 str r3, [sp, #8] 871:Src/main.c **** { 6647 .loc 2 871 3 is_stmt 1 view .LVU2136 871:Src/main.c **** { 6648 .loc 2 871 7 is_stmt 0 view .LVU2137 6649 0048 6946 mov r1, sp 6650 004a 0548 ldr r0, .L305 6651 004c FFF7FEFF bl HAL_ADC_ConfigChannel 6652 .LVL541: 871:Src/main.c **** { 6653 .loc 2 871 6 view .LVU2138 6654 0050 20B9 cbnz r0, .L304 879:Src/main.c **** 6655 .loc 2 879 1 view .LVU2139 6656 0052 05B0 add sp, sp, #20 6657 .LCFI57: 6658 .cfi_remember_state 6659 .cfi_def_cfa_offset 4 6660 @ sp needed 6661 0054 5DF804FB ldr pc, [sp], #4 6662 .L303: 6663 .LCFI58: 6664 .cfi_restore_state 863:Src/main.c **** } 6665 .loc 2 863 5 is_stmt 1 view .LVU2140 6666 0058 FFF7FEFF bl Error_Handler 6667 .LVL542: 6668 .L304: 873:Src/main.c **** } 6669 .loc 2 873 5 view .LVU2141 6670 005c FFF7FEFF bl Error_Handler 6671 .LVL543: 6672 .L306: 6673 .align 2 6674 .L305: 6675 0060 00000000 .word .LANCHOR32 ARM GAS /tmp/ccqopZd5.s page 485 6676 0064 00220140 .word 1073816064 6677 0068 0100000F .word 251658241 6678 .cfi_endproc 6679 .LFE1189: 6681 .section .text.MX_USART1_UART_Init,"ax",%progbits 6682 .align 1 6683 .syntax unified 6684 .thumb 6685 .thumb_func 6686 .fpu fpv5-d16 6688 MX_USART1_UART_Init: 6689 .LFB1203: 1478:Src/main.c **** 6690 .loc 2 1478 1 view -0 6691 .cfi_startproc 6692 @ args = 0, pretend = 0, frame = 208 6693 @ frame_needed = 0, uses_anonymous_args = 0 6694 0000 2DE9F041 push {r4, r5, r6, r7, r8, lr} 6695 .LCFI59: 6696 .cfi_def_cfa_offset 24 6697 .cfi_offset 4, -24 6698 .cfi_offset 5, -20 6699 .cfi_offset 6, -16 6700 .cfi_offset 7, -12 6701 .cfi_offset 8, -8 6702 .cfi_offset 14, -4 6703 0004 B4B0 sub sp, sp, #208 6704 .LCFI60: 6705 .cfi_def_cfa_offset 232 1484:Src/main.c **** 6706 .loc 2 1484 3 view .LVU2143 1484:Src/main.c **** 6707 .loc 2 1484 24 is_stmt 0 view .LVU2144 6708 0006 0021 movs r1, #0 6709 0008 2D91 str r1, [sp, #180] 6710 000a 2E91 str r1, [sp, #184] 6711 000c 2F91 str r1, [sp, #188] 6712 000e 3091 str r1, [sp, #192] 6713 0010 3191 str r1, [sp, #196] 6714 0012 3291 str r1, [sp, #200] 6715 0014 3391 str r1, [sp, #204] 1486:Src/main.c **** RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; 6716 .loc 2 1486 3 is_stmt 1 view .LVU2145 1486:Src/main.c **** RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; 6717 .loc 2 1486 23 is_stmt 0 view .LVU2146 6718 0016 2791 str r1, [sp, #156] 6719 0018 2891 str r1, [sp, #160] 6720 001a 2991 str r1, [sp, #164] 6721 001c 2A91 str r1, [sp, #168] 6722 001e 2B91 str r1, [sp, #172] 6723 0020 2C91 str r1, [sp, #176] 1487:Src/main.c **** 6724 .loc 2 1487 3 is_stmt 1 view .LVU2147 1487:Src/main.c **** 6725 .loc 2 1487 28 is_stmt 0 view .LVU2148 6726 0022 9022 movs r2, #144 6727 0024 03A8 add r0, sp, #12 ARM GAS /tmp/ccqopZd5.s page 486 6728 0026 FFF7FEFF bl memset 6729 .LVL544: 1491:Src/main.c **** PeriphClkInitStruct.Usart1ClockSelection = RCC_USART1CLKSOURCE_PCLK2; 6730 .loc 2 1491 3 is_stmt 1 view .LVU2149 1491:Src/main.c **** PeriphClkInitStruct.Usart1ClockSelection = RCC_USART1CLKSOURCE_PCLK2; 6731 .loc 2 1491 44 is_stmt 0 view .LVU2150 6732 002a 4023 movs r3, #64 6733 002c 0393 str r3, [sp, #12] 1492:Src/main.c **** if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) 6734 .loc 2 1492 3 is_stmt 1 view .LVU2151 1493:Src/main.c **** { 6735 .loc 2 1493 3 view .LVU2152 1493:Src/main.c **** { 6736 .loc 2 1493 7 is_stmt 0 view .LVU2153 6737 002e 03A8 add r0, sp, #12 6738 0030 FFF7FEFF bl HAL_RCCEx_PeriphCLKConfig 6739 .LVL545: 1493:Src/main.c **** { 6740 .loc 2 1493 6 view .LVU2154 6741 0034 0028 cmp r0, #0 6742 0036 40F09E80 bne .L310 1499:Src/main.c **** 6743 .loc 2 1499 3 is_stmt 1 view .LVU2155 6744 .LVL546: 6745 .LBB507: 6746 .LBI507: 1587:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { 6747 .loc 3 1587 22 view .LVU2156 6748 .LBB508: 1589:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** SET_BIT(RCC->APB2ENR, Periphs); 6749 .loc 3 1589 3 view .LVU2157 1590:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Delay after an RCC peripheral clock enabling */ 6750 .loc 3 1590 3 view .LVU2158 6751 003a 504B ldr r3, .L311 6752 003c 5A6C ldr r2, [r3, #68] 6753 003e 42F01002 orr r2, r2, #16 6754 0042 5A64 str r2, [r3, #68] 1592:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; 6755 .loc 3 1592 3 view .LVU2159 1592:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; 6756 .loc 3 1592 12 is_stmt 0 view .LVU2160 6757 0044 5A6C ldr r2, [r3, #68] 6758 0046 02F01002 and r2, r2, #16 1592:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; 6759 .loc 3 1592 10 view .LVU2161 6760 004a 0292 str r2, [sp, #8] 6761 .loc 3 1593 3 is_stmt 1 view .LVU2162 6762 004c 029A ldr r2, [sp, #8] 6763 .LVL547: 6764 .loc 3 1593 3 is_stmt 0 view .LVU2163 6765 .LBE508: 6766 .LBE507: 1501:Src/main.c **** /**USART1 GPIO Configuration 6767 .loc 2 1501 3 is_stmt 1 view .LVU2164 6768 .LBB509: 6769 .LBI509: 309:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { ARM GAS /tmp/ccqopZd5.s page 487 6770 .loc 3 309 22 view .LVU2165 6771 .LBB510: 311:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** SET_BIT(RCC->AHB1ENR, Periphs); 6772 .loc 3 311 3 view .LVU2166 312:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Delay after an RCC peripheral clock enabling */ 6773 .loc 3 312 3 view .LVU2167 6774 004e 1A6B ldr r2, [r3, #48] 6775 0050 42F00102 orr r2, r2, #1 6776 0054 1A63 str r2, [r3, #48] 314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; 6777 .loc 3 314 3 view .LVU2168 314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; 6778 .loc 3 314 12 is_stmt 0 view .LVU2169 6779 0056 1B6B ldr r3, [r3, #48] 6780 0058 03F00103 and r3, r3, #1 314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; 6781 .loc 3 314 10 view .LVU2170 6782 005c 0193 str r3, [sp, #4] 315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } 6783 .loc 3 315 3 is_stmt 1 view .LVU2171 6784 005e 019B ldr r3, [sp, #4] 6785 .LVL548: 315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } 6786 .loc 3 315 3 is_stmt 0 view .LVU2172 6787 .LBE510: 6788 .LBE509: 1506:Src/main.c **** GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE; 6789 .loc 2 1506 3 is_stmt 1 view .LVU2173 1506:Src/main.c **** GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE; 6790 .loc 2 1506 23 is_stmt 0 view .LVU2174 6791 0060 4FF40073 mov r3, #512 6792 0064 2793 str r3, [sp, #156] 1507:Src/main.c **** GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH; 6793 .loc 2 1507 3 is_stmt 1 view .LVU2175 1507:Src/main.c **** GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH; 6794 .loc 2 1507 24 is_stmt 0 view .LVU2176 6795 0066 4FF00208 mov r8, #2 6796 006a CDF8A080 str r8, [sp, #160] 1508:Src/main.c **** GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; 6797 .loc 2 1508 3 is_stmt 1 view .LVU2177 1508:Src/main.c **** GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; 6798 .loc 2 1508 25 is_stmt 0 view .LVU2178 6799 006e 0327 movs r7, #3 6800 0070 2997 str r7, [sp, #164] 1509:Src/main.c **** GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; 6801 .loc 2 1509 3 is_stmt 1 view .LVU2179 1509:Src/main.c **** GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; 6802 .loc 2 1509 30 is_stmt 0 view .LVU2180 6803 0072 0024 movs r4, #0 6804 0074 2A94 str r4, [sp, #168] 1510:Src/main.c **** GPIO_InitStruct.Alternate = LL_GPIO_AF_7; 6805 .loc 2 1510 3 is_stmt 1 view .LVU2181 1510:Src/main.c **** GPIO_InitStruct.Alternate = LL_GPIO_AF_7; 6806 .loc 2 1510 24 is_stmt 0 view .LVU2182 6807 0076 2B94 str r4, [sp, #172] 1511:Src/main.c **** LL_GPIO_Init(GPIOA, &GPIO_InitStruct); 6808 .loc 2 1511 3 is_stmt 1 view .LVU2183 ARM GAS /tmp/ccqopZd5.s page 488 1511:Src/main.c **** LL_GPIO_Init(GPIOA, &GPIO_InitStruct); 6809 .loc 2 1511 29 is_stmt 0 view .LVU2184 6810 0078 0726 movs r6, #7 6811 007a 2C96 str r6, [sp, #176] 1512:Src/main.c **** 6812 .loc 2 1512 3 is_stmt 1 view .LVU2185 6813 007c 404D ldr r5, .L311+4 6814 007e 27A9 add r1, sp, #156 6815 0080 2846 mov r0, r5 6816 0082 FFF7FEFF bl LL_GPIO_Init 6817 .LVL549: 1514:Src/main.c **** GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE; 6818 .loc 2 1514 3 view .LVU2186 1514:Src/main.c **** GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE; 6819 .loc 2 1514 23 is_stmt 0 view .LVU2187 6820 0086 4FF48063 mov r3, #1024 6821 008a 2793 str r3, [sp, #156] 1515:Src/main.c **** GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH; 6822 .loc 2 1515 3 is_stmt 1 view .LVU2188 1515:Src/main.c **** GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH; 6823 .loc 2 1515 24 is_stmt 0 view .LVU2189 6824 008c CDF8A080 str r8, [sp, #160] 1516:Src/main.c **** GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; 6825 .loc 2 1516 3 is_stmt 1 view .LVU2190 1516:Src/main.c **** GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; 6826 .loc 2 1516 25 is_stmt 0 view .LVU2191 6827 0090 2997 str r7, [sp, #164] 1517:Src/main.c **** GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; 6828 .loc 2 1517 3 is_stmt 1 view .LVU2192 1517:Src/main.c **** GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; 6829 .loc 2 1517 30 is_stmt 0 view .LVU2193 6830 0092 2A94 str r4, [sp, #168] 1518:Src/main.c **** GPIO_InitStruct.Alternate = LL_GPIO_AF_7; 6831 .loc 2 1518 3 is_stmt 1 view .LVU2194 1518:Src/main.c **** GPIO_InitStruct.Alternate = LL_GPIO_AF_7; 6832 .loc 2 1518 24 is_stmt 0 view .LVU2195 6833 0094 2B94 str r4, [sp, #172] 1519:Src/main.c **** LL_GPIO_Init(GPIOA, &GPIO_InitStruct); 6834 .loc 2 1519 3 is_stmt 1 view .LVU2196 1519:Src/main.c **** LL_GPIO_Init(GPIOA, &GPIO_InitStruct); 6835 .loc 2 1519 29 is_stmt 0 view .LVU2197 6836 0096 2C96 str r6, [sp, #176] 1520:Src/main.c **** 6837 .loc 2 1520 3 is_stmt 1 view .LVU2198 6838 0098 27A9 add r1, sp, #156 6839 009a 2846 mov r0, r5 6840 009c FFF7FEFF bl LL_GPIO_Init 6841 .LVL550: 1525:Src/main.c **** 6842 .loc 2 1525 3 view .LVU2199 6843 .LBB511: 6844 .LBI511: 1032:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 6845 .loc 6 1032 22 view .LVU2200 6846 .LBB512: 1034:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 6847 .loc 6 1034 3 view .LVU2201 ARM GAS /tmp/ccqopZd5.s page 489 6848 00a0 384B ldr r3, .L311+8 6849 00a2 D3F8B820 ldr r2, [r3, #184] 6850 00a6 22F0F052 bic r2, r2, #503316480 6851 00aa 42F00062 orr r2, r2, #134217728 6852 00ae C3F8B820 str r2, [r3, #184] 6853 .LVL551: 1034:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 6854 .loc 6 1034 3 is_stmt 0 view .LVU2202 6855 .LBE512: 6856 .LBE511: 1527:Src/main.c **** 6857 .loc 2 1527 3 is_stmt 1 view .LVU2203 6858 .LBB513: 6859 .LBI513: 598:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 6860 .loc 6 598 22 view .LVU2204 6861 .LBB514: 600:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 6862 .loc 6 600 3 view .LVU2205 6863 00b2 D3F8B820 ldr r2, [r3, #184] 6864 00b6 22F0C002 bic r2, r2, #192 6865 00ba 42F04002 orr r2, r2, #64 6866 00be C3F8B820 str r2, [r3, #184] 6867 .LVL552: 600:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 6868 .loc 6 600 3 is_stmt 0 view .LVU2206 6869 .LBE514: 6870 .LBE513: 1529:Src/main.c **** 6871 .loc 2 1529 3 is_stmt 1 view .LVU2207 6872 .LBB515: 6873 .LBI515: 924:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 6874 .loc 6 924 22 view .LVU2208 6875 .LBB516: 926:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 6876 .loc 6 926 3 view .LVU2209 6877 00c2 D3F8B820 ldr r2, [r3, #184] 6878 00c6 42F44032 orr r2, r2, #196608 6879 00ca C3F8B820 str r2, [r3, #184] 6880 .LVL553: 926:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 6881 .loc 6 926 3 is_stmt 0 view .LVU2210 6882 .LBE516: 6883 .LBE515: 1531:Src/main.c **** 6884 .loc 2 1531 3 is_stmt 1 view .LVU2211 6885 .LBB517: 6886 .LBI517: 646:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 6887 .loc 6 646 22 view .LVU2212 6888 .LBB518: 648:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 6889 .loc 6 648 3 view .LVU2213 6890 00ce D3F8B820 ldr r2, [r3, #184] 6891 00d2 22F49072 bic r2, r2, #288 6892 00d6 C3F8B820 str r2, [r3, #184] ARM GAS /tmp/ccqopZd5.s page 490 6893 .LVL554: 648:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 6894 .loc 6 648 3 is_stmt 0 view .LVU2214 6895 .LBE518: 6896 .LBE517: 1533:Src/main.c **** 6897 .loc 2 1533 3 is_stmt 1 view .LVU2215 6898 .LBB519: 6899 .LBI519: 693:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 6900 .loc 6 693 22 view .LVU2216 6901 .LBB520: 695:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 6902 .loc 6 695 3 view .LVU2217 6903 00da D3F8B820 ldr r2, [r3, #184] 6904 00de 22F40072 bic r2, r2, #512 6905 00e2 C3F8B820 str r2, [r3, #184] 6906 .LVL555: 695:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 6907 .loc 6 695 3 is_stmt 0 view .LVU2218 6908 .LBE520: 6909 .LBE519: 1535:Src/main.c **** 6910 .loc 2 1535 3 is_stmt 1 view .LVU2219 6911 .LBB521: 6912 .LBI521: 738:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 6913 .loc 6 738 22 view .LVU2220 6914 .LBB522: 740:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 6915 .loc 6 740 3 view .LVU2221 6916 00e6 D3F8B820 ldr r2, [r3, #184] 6917 00ea 42F48062 orr r2, r2, #1024 6918 00ee C3F8B820 str r2, [r3, #184] 6919 .LVL556: 740:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 6920 .loc 6 740 3 is_stmt 0 view .LVU2222 6921 .LBE522: 6922 .LBE521: 1537:Src/main.c **** 6923 .loc 2 1537 3 is_stmt 1 view .LVU2223 6924 .LBB523: 6925 .LBI523: 784:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 6926 .loc 6 784 22 view .LVU2224 6927 .LBB524: 786:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 6928 .loc 6 786 3 view .LVU2225 6929 00f2 D3F8B820 ldr r2, [r3, #184] 6930 00f6 22F4C052 bic r2, r2, #6144 6931 00fa C3F8B820 str r2, [r3, #184] 6932 .LVL557: 786:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 6933 .loc 6 786 3 is_stmt 0 view .LVU2226 6934 .LBE524: 6935 .LBE523: 1539:Src/main.c **** ARM GAS /tmp/ccqopZd5.s page 491 6936 .loc 2 1539 3 is_stmt 1 view .LVU2227 6937 .LBB525: 6938 .LBI525: 831:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 6939 .loc 6 831 22 view .LVU2228 6940 .LBB526: 833:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 6941 .loc 6 833 3 view .LVU2229 6942 00fe D3F8B820 ldr r2, [r3, #184] 6943 0102 22F4C042 bic r2, r2, #24576 6944 0106 C3F8B820 str r2, [r3, #184] 6945 .LVL558: 833:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 6946 .loc 6 833 3 is_stmt 0 view .LVU2230 6947 .LBE526: 6948 .LBE525: 1541:Src/main.c **** 6949 .loc 2 1541 3 is_stmt 1 view .LVU2231 6950 .LBB527: 6951 .LBI527: 1299:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 6952 .loc 6 1299 22 view .LVU2232 6953 .LBB528: 1301:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 6954 .loc 6 1301 3 view .LVU2233 6955 010a D3F8CC20 ldr r2, [r3, #204] 6956 010e 22F00402 bic r2, r2, #4 6957 0112 C3F8CC20 str r2, [r3, #204] 6958 .LVL559: 1301:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 6959 .loc 6 1301 3 is_stmt 0 view .LVU2234 6960 .LBE528: 6961 .LBE527: 1544:Src/main.c **** NVIC_EnableIRQ(USART1_IRQn); 6962 .loc 2 1544 3 is_stmt 1 view .LVU2235 6963 .LBB529: 6964 .LBI529: 1884:Drivers/CMSIS/Include/core_cm7.h **** { 6965 .loc 1 1884 26 view .LVU2236 6966 .LBB530: 1886:Drivers/CMSIS/Include/core_cm7.h **** } 6967 .loc 1 1886 3 view .LVU2237 1886:Drivers/CMSIS/Include/core_cm7.h **** } 6968 .loc 1 1886 26 is_stmt 0 view .LVU2238 6969 0116 1C4B ldr r3, .L311+12 6970 0118 D868 ldr r0, [r3, #12] 6971 .LBE530: 6972 .LBE529: 1544:Src/main.c **** NVIC_EnableIRQ(USART1_IRQn); 6973 .loc 2 1544 3 view .LVU2239 6974 011a 2246 mov r2, r4 6975 011c 2146 mov r1, r4 6976 011e C0F30220 ubfx r0, r0, #8, #3 6977 0122 FFF7FEFF bl NVIC_EncodePriority 6978 .LVL560: 6979 .LBB531: 6980 .LBI531: ARM GAS /tmp/ccqopZd5.s page 492 2024:Drivers/CMSIS/Include/core_cm7.h **** { 6981 .loc 1 2024 22 is_stmt 1 view .LVU2240 6982 .LBB532: 2026:Drivers/CMSIS/Include/core_cm7.h **** { 6983 .loc 1 2026 3 view .LVU2241 2028:Drivers/CMSIS/Include/core_cm7.h **** } 6984 .loc 1 2028 5 view .LVU2242 2028:Drivers/CMSIS/Include/core_cm7.h **** } 6985 .loc 1 2028 49 is_stmt 0 view .LVU2243 6986 0126 0001 lsls r0, r0, #4 6987 .LVL561: 2028:Drivers/CMSIS/Include/core_cm7.h **** } 6988 .loc 1 2028 49 view .LVU2244 6989 0128 C0B2 uxtb r0, r0 2028:Drivers/CMSIS/Include/core_cm7.h **** } 6990 .loc 1 2028 47 view .LVU2245 6991 012a 184B ldr r3, .L311+16 6992 012c 83F82503 strb r0, [r3, #805] 6993 .LVL562: 2028:Drivers/CMSIS/Include/core_cm7.h **** } 6994 .loc 1 2028 47 view .LVU2246 6995 .LBE532: 6996 .LBE531: 1545:Src/main.c **** 6997 .loc 2 1545 3 is_stmt 1 view .LVU2247 6998 .LBB533: 6999 .LBI533: 1896:Drivers/CMSIS/Include/core_cm7.h **** { 7000 .loc 1 1896 22 view .LVU2248 7001 .LBB534: 1898:Drivers/CMSIS/Include/core_cm7.h **** { 7002 .loc 1 1898 3 view .LVU2249 1900:Drivers/CMSIS/Include/core_cm7.h **** } 7003 .loc 1 1900 5 view .LVU2250 1900:Drivers/CMSIS/Include/core_cm7.h **** } 7004 .loc 1 1900 43 is_stmt 0 view .LVU2251 7005 0130 2022 movs r2, #32 7006 0132 5A60 str r2, [r3, #4] 7007 .LVL563: 1900:Drivers/CMSIS/Include/core_cm7.h **** } 7008 .loc 1 1900 43 view .LVU2252 7009 .LBE534: 7010 .LBE533: 1550:Src/main.c **** USART_InitStruct.DataWidth = LL_USART_DATAWIDTH_8B; 7011 .loc 2 1550 3 is_stmt 1 view .LVU2253 1550:Src/main.c **** USART_InitStruct.DataWidth = LL_USART_DATAWIDTH_8B; 7012 .loc 2 1550 29 is_stmt 0 view .LVU2254 7013 0134 4FF4E133 mov r3, #115200 7014 0138 2D93 str r3, [sp, #180] 1551:Src/main.c **** USART_InitStruct.StopBits = LL_USART_STOPBITS_1; 7015 .loc 2 1551 3 is_stmt 1 view .LVU2255 1551:Src/main.c **** USART_InitStruct.StopBits = LL_USART_STOPBITS_1; 7016 .loc 2 1551 30 is_stmt 0 view .LVU2256 7017 013a 2E94 str r4, [sp, #184] 1552:Src/main.c **** USART_InitStruct.Parity = LL_USART_PARITY_NONE; 7018 .loc 2 1552 3 is_stmt 1 view .LVU2257 1552:Src/main.c **** USART_InitStruct.Parity = LL_USART_PARITY_NONE; ARM GAS /tmp/ccqopZd5.s page 493 7019 .loc 2 1552 29 is_stmt 0 view .LVU2258 7020 013c 2F94 str r4, [sp, #188] 1553:Src/main.c **** USART_InitStruct.TransferDirection = LL_USART_DIRECTION_TX_RX; 7021 .loc 2 1553 3 is_stmt 1 view .LVU2259 1553:Src/main.c **** USART_InitStruct.TransferDirection = LL_USART_DIRECTION_TX_RX; 7022 .loc 2 1553 27 is_stmt 0 view .LVU2260 7023 013e 3094 str r4, [sp, #192] 1554:Src/main.c **** USART_InitStruct.HardwareFlowControl = LL_USART_HWCONTROL_NONE; 7024 .loc 2 1554 3 is_stmt 1 view .LVU2261 1554:Src/main.c **** USART_InitStruct.HardwareFlowControl = LL_USART_HWCONTROL_NONE; 7025 .loc 2 1554 38 is_stmt 0 view .LVU2262 7026 0140 0C23 movs r3, #12 7027 0142 3193 str r3, [sp, #196] 1555:Src/main.c **** USART_InitStruct.OverSampling = LL_USART_OVERSAMPLING_16; 7028 .loc 2 1555 3 is_stmt 1 view .LVU2263 1555:Src/main.c **** USART_InitStruct.OverSampling = LL_USART_OVERSAMPLING_16; 7029 .loc 2 1555 40 is_stmt 0 view .LVU2264 7030 0144 3294 str r4, [sp, #200] 1556:Src/main.c **** LL_USART_Init(USART1, &USART_InitStruct); 7031 .loc 2 1556 3 is_stmt 1 view .LVU2265 1556:Src/main.c **** LL_USART_Init(USART1, &USART_InitStruct); 7032 .loc 2 1556 33 is_stmt 0 view .LVU2266 7033 0146 3394 str r4, [sp, #204] 1557:Src/main.c **** LL_USART_ConfigAsyncMode(USART1); 7034 .loc 2 1557 3 is_stmt 1 view .LVU2267 7035 0148 04F18044 add r4, r4, #1073741824 7036 014c 04F58834 add r4, r4, #69632 7037 0150 2DA9 add r1, sp, #180 7038 0152 2046 mov r0, r4 7039 0154 FFF7FEFF bl LL_USART_Init 7040 .LVL564: 1558:Src/main.c **** LL_USART_Enable(USART1); 7041 .loc 2 1558 3 view .LVU2268 7042 .LBB535: 7043 .LBI535: 2320:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 7044 .loc 7 2320 22 view .LVU2269 7045 .LBB536: 2326:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN | USART_CR3_HDSEL)); 7046 .loc 7 2326 3 view .LVU2270 7047 0158 6368 ldr r3, [r4, #4] 7048 015a 23F49043 bic r3, r3, #18432 7049 015e 6360 str r3, [r4, #4] 2327:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 7050 .loc 7 2327 3 view .LVU2271 7051 0160 A368 ldr r3, [r4, #8] 7052 0162 23F02A03 bic r3, r3, #42 7053 0166 A360 str r3, [r4, #8] 7054 .LVL565: 2327:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 7055 .loc 7 2327 3 is_stmt 0 view .LVU2272 7056 .LBE536: 7057 .LBE535: 1559:Src/main.c **** /* USER CODE BEGIN USART1_Init 2 */ 7058 .loc 2 1559 3 is_stmt 1 view .LVU2273 7059 .LBB537: 7060 .LBI537: ARM GAS /tmp/ccqopZd5.s page 494 560:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 7061 .loc 7 560 22 view .LVU2274 7062 .LBB538: 562:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 7063 .loc 7 562 3 view .LVU2275 7064 0168 2368 ldr r3, [r4] 7065 016a 43F00103 orr r3, r3, #1 7066 016e 2360 str r3, [r4] 7067 .LVL566: 562:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 7068 .loc 7 562 3 is_stmt 0 view .LVU2276 7069 .LBE538: 7070 .LBE537: 1564:Src/main.c **** 7071 .loc 2 1564 1 view .LVU2277 7072 0170 34B0 add sp, sp, #208 7073 .LCFI61: 7074 .cfi_remember_state 7075 .cfi_def_cfa_offset 24 7076 @ sp needed 7077 0172 BDE8F081 pop {r4, r5, r6, r7, r8, pc} 7078 .L310: 7079 .LCFI62: 7080 .cfi_restore_state 1495:Src/main.c **** } 7081 .loc 2 1495 5 is_stmt 1 view .LVU2278 7082 0176 FFF7FEFF bl Error_Handler 7083 .LVL567: 7084 .L312: 7085 017a 00BF .align 2 7086 .L311: 7087 017c 00380240 .word 1073887232 7088 0180 00000240 .word 1073872896 7089 0184 00640240 .word 1073898496 7090 0188 00ED00E0 .word -536810240 7091 018c 00E100E0 .word -536813312 7092 .cfi_endproc 7093 .LFE1203: 7095 .section .text.MX_TIM10_Init,"ax",%progbits 7096 .align 1 7097 .syntax unified 7098 .thumb 7099 .thumb_func 7100 .fpu fpv5-d16 7102 MX_TIM10_Init: 7103 .LFB1200: 1366:Src/main.c **** 7104 .loc 2 1366 1 view -0 7105 .cfi_startproc 7106 @ args = 0, pretend = 0, frame = 0 7107 @ frame_needed = 0, uses_anonymous_args = 0 7108 0000 08B5 push {r3, lr} 7109 .LCFI63: 7110 .cfi_def_cfa_offset 8 7111 .cfi_offset 3, -8 7112 .cfi_offset 14, -4 1375:Src/main.c **** htim10.Init.Prescaler = 183; ARM GAS /tmp/ccqopZd5.s page 495 7113 .loc 2 1375 3 view .LVU2280 1375:Src/main.c **** htim10.Init.Prescaler = 183; 7114 .loc 2 1375 19 is_stmt 0 view .LVU2281 7115 0002 0848 ldr r0, .L317 7116 0004 084B ldr r3, .L317+4 7117 0006 0360 str r3, [r0] 1376:Src/main.c **** htim10.Init.CounterMode = TIM_COUNTERMODE_UP; 7118 .loc 2 1376 3 is_stmt 1 view .LVU2282 1376:Src/main.c **** htim10.Init.CounterMode = TIM_COUNTERMODE_UP; 7119 .loc 2 1376 25 is_stmt 0 view .LVU2283 7120 0008 B723 movs r3, #183 7121 000a 4360 str r3, [r0, #4] 1377:Src/main.c **** htim10.Init.Period = 9; 7122 .loc 2 1377 3 is_stmt 1 view .LVU2284 1377:Src/main.c **** htim10.Init.Period = 9; 7123 .loc 2 1377 27 is_stmt 0 view .LVU2285 7124 000c 0023 movs r3, #0 7125 000e 8360 str r3, [r0, #8] 1378:Src/main.c **** htim10.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; 7126 .loc 2 1378 3 is_stmt 1 view .LVU2286 1378:Src/main.c **** htim10.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; 7127 .loc 2 1378 22 is_stmt 0 view .LVU2287 7128 0010 0922 movs r2, #9 7129 0012 C260 str r2, [r0, #12] 1379:Src/main.c **** htim10.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; 7130 .loc 2 1379 3 is_stmt 1 view .LVU2288 1379:Src/main.c **** htim10.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; 7131 .loc 2 1379 29 is_stmt 0 view .LVU2289 7132 0014 0361 str r3, [r0, #16] 1380:Src/main.c **** if (HAL_TIM_Base_Init(&htim10) != HAL_OK) 7133 .loc 2 1380 3 is_stmt 1 view .LVU2290 1380:Src/main.c **** if (HAL_TIM_Base_Init(&htim10) != HAL_OK) 7134 .loc 2 1380 33 is_stmt 0 view .LVU2291 7135 0016 8361 str r3, [r0, #24] 1381:Src/main.c **** { 7136 .loc 2 1381 3 is_stmt 1 view .LVU2292 1381:Src/main.c **** { 7137 .loc 2 1381 7 is_stmt 0 view .LVU2293 7138 0018 FFF7FEFF bl HAL_TIM_Base_Init 7139 .LVL568: 1381:Src/main.c **** { 7140 .loc 2 1381 6 view .LVU2294 7141 001c 00B9 cbnz r0, .L316 1389:Src/main.c **** 7142 .loc 2 1389 1 view .LVU2295 7143 001e 08BD pop {r3, pc} 7144 .L316: 1383:Src/main.c **** } 7145 .loc 2 1383 5 is_stmt 1 view .LVU2296 7146 0020 FFF7FEFF bl Error_Handler 7147 .LVL569: 7148 .L318: 7149 .align 2 7150 .L317: 7151 0024 00000000 .word .LANCHOR5 7152 0028 00440140 .word 1073824768 7153 .cfi_endproc ARM GAS /tmp/ccqopZd5.s page 496 7154 .LFE1200: 7156 .section .text.MX_UART8_Init,"ax",%progbits 7157 .align 1 7158 .syntax unified 7159 .thumb 7160 .thumb_func 7161 .fpu fpv5-d16 7163 MX_UART8_Init: 7164 .LFB1202: 1443:Src/main.c **** 7165 .loc 2 1443 1 view -0 7166 .cfi_startproc 7167 @ args = 0, pretend = 0, frame = 0 7168 @ frame_needed = 0, uses_anonymous_args = 0 7169 0000 08B5 push {r3, lr} 7170 .LCFI64: 7171 .cfi_def_cfa_offset 8 7172 .cfi_offset 3, -8 7173 .cfi_offset 14, -4 1452:Src/main.c **** huart8.Init.BaudRate = 115200; 7174 .loc 2 1452 3 view .LVU2298 1452:Src/main.c **** huart8.Init.BaudRate = 115200; 7175 .loc 2 1452 19 is_stmt 0 view .LVU2299 7176 0002 0B48 ldr r0, .L323 7177 0004 0B4B ldr r3, .L323+4 7178 0006 0360 str r3, [r0] 1453:Src/main.c **** huart8.Init.WordLength = UART_WORDLENGTH_8B; 7179 .loc 2 1453 3 is_stmt 1 view .LVU2300 1453:Src/main.c **** huart8.Init.WordLength = UART_WORDLENGTH_8B; 7180 .loc 2 1453 24 is_stmt 0 view .LVU2301 7181 0008 4FF4E133 mov r3, #115200 7182 000c 4360 str r3, [r0, #4] 1454:Src/main.c **** huart8.Init.StopBits = UART_STOPBITS_1; 7183 .loc 2 1454 3 is_stmt 1 view .LVU2302 1454:Src/main.c **** huart8.Init.StopBits = UART_STOPBITS_1; 7184 .loc 2 1454 26 is_stmt 0 view .LVU2303 7185 000e 0023 movs r3, #0 7186 0010 8360 str r3, [r0, #8] 1455:Src/main.c **** huart8.Init.Parity = UART_PARITY_NONE; 7187 .loc 2 1455 3 is_stmt 1 view .LVU2304 1455:Src/main.c **** huart8.Init.Parity = UART_PARITY_NONE; 7188 .loc 2 1455 24 is_stmt 0 view .LVU2305 7189 0012 C360 str r3, [r0, #12] 1456:Src/main.c **** huart8.Init.Mode = UART_MODE_TX_RX; 7190 .loc 2 1456 3 is_stmt 1 view .LVU2306 1456:Src/main.c **** huart8.Init.Mode = UART_MODE_TX_RX; 7191 .loc 2 1456 22 is_stmt 0 view .LVU2307 7192 0014 0361 str r3, [r0, #16] 1457:Src/main.c **** huart8.Init.HwFlowCtl = UART_HWCONTROL_NONE; 7193 .loc 2 1457 3 is_stmt 1 view .LVU2308 1457:Src/main.c **** huart8.Init.HwFlowCtl = UART_HWCONTROL_NONE; 7194 .loc 2 1457 20 is_stmt 0 view .LVU2309 7195 0016 0C22 movs r2, #12 7196 0018 4261 str r2, [r0, #20] 1458:Src/main.c **** huart8.Init.OverSampling = UART_OVERSAMPLING_16; 7197 .loc 2 1458 3 is_stmt 1 view .LVU2310 1458:Src/main.c **** huart8.Init.OverSampling = UART_OVERSAMPLING_16; ARM GAS /tmp/ccqopZd5.s page 497 7198 .loc 2 1458 25 is_stmt 0 view .LVU2311 7199 001a 8361 str r3, [r0, #24] 1459:Src/main.c **** huart8.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE; 7200 .loc 2 1459 3 is_stmt 1 view .LVU2312 1459:Src/main.c **** huart8.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE; 7201 .loc 2 1459 28 is_stmt 0 view .LVU2313 7202 001c C361 str r3, [r0, #28] 1460:Src/main.c **** huart8.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT; 7203 .loc 2 1460 3 is_stmt 1 view .LVU2314 1460:Src/main.c **** huart8.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT; 7204 .loc 2 1460 30 is_stmt 0 view .LVU2315 7205 001e 0362 str r3, [r0, #32] 1461:Src/main.c **** if (HAL_UART_Init(&huart8) != HAL_OK) 7206 .loc 2 1461 3 is_stmt 1 view .LVU2316 1461:Src/main.c **** if (HAL_UART_Init(&huart8) != HAL_OK) 7207 .loc 2 1461 38 is_stmt 0 view .LVU2317 7208 0020 4362 str r3, [r0, #36] 1462:Src/main.c **** { 7209 .loc 2 1462 3 is_stmt 1 view .LVU2318 1462:Src/main.c **** { 7210 .loc 2 1462 7 is_stmt 0 view .LVU2319 7211 0022 FFF7FEFF bl HAL_UART_Init 7212 .LVL570: 1462:Src/main.c **** { 7213 .loc 2 1462 6 view .LVU2320 7214 0026 00B9 cbnz r0, .L322 1470:Src/main.c **** 7215 .loc 2 1470 1 view .LVU2321 7216 0028 08BD pop {r3, pc} 7217 .L322: 1464:Src/main.c **** } 7218 .loc 2 1464 5 is_stmt 1 view .LVU2322 7219 002a FFF7FEFF bl Error_Handler 7220 .LVL571: 7221 .L324: 7222 002e 00BF .align 2 7223 .L323: 7224 0030 00000000 .word .LANCHOR35 7225 0034 007C0040 .word 1073773568 7226 .cfi_endproc 7227 .LFE1202: 7229 .section .text.MX_TIM8_Init,"ax",%progbits 7230 .align 1 7231 .syntax unified 7232 .thumb 7233 .thumb_func 7234 .fpu fpv5-d16 7236 MX_TIM8_Init: 7237 .LFB1199: 1319:Src/main.c **** 7238 .loc 2 1319 1 view -0 7239 .cfi_startproc 7240 @ args = 0, pretend = 0, frame = 32 7241 @ frame_needed = 0, uses_anonymous_args = 0 7242 0000 00B5 push {lr} 7243 .LCFI65: 7244 .cfi_def_cfa_offset 4 ARM GAS /tmp/ccqopZd5.s page 498 7245 .cfi_offset 14, -4 7246 0002 89B0 sub sp, sp, #36 7247 .LCFI66: 7248 .cfi_def_cfa_offset 40 1325:Src/main.c **** TIM_MasterConfigTypeDef sMasterConfig = {0}; 7249 .loc 2 1325 3 view .LVU2324 1325:Src/main.c **** TIM_MasterConfigTypeDef sMasterConfig = {0}; 7250 .loc 2 1325 26 is_stmt 0 view .LVU2325 7251 0004 0023 movs r3, #0 7252 0006 0493 str r3, [sp, #16] 7253 0008 0593 str r3, [sp, #20] 7254 000a 0693 str r3, [sp, #24] 7255 000c 0793 str r3, [sp, #28] 1326:Src/main.c **** 7256 .loc 2 1326 3 is_stmt 1 view .LVU2326 1326:Src/main.c **** 7257 .loc 2 1326 27 is_stmt 0 view .LVU2327 7258 000e 0193 str r3, [sp, #4] 7259 0010 0293 str r3, [sp, #8] 7260 0012 0393 str r3, [sp, #12] 1331:Src/main.c **** htim8.Init.Prescaler = 0; 7261 .loc 2 1331 3 is_stmt 1 view .LVU2328 1331:Src/main.c **** htim8.Init.Prescaler = 0; 7262 .loc 2 1331 18 is_stmt 0 view .LVU2329 7263 0014 1348 ldr r0, .L333 7264 0016 144A ldr r2, .L333+4 7265 0018 0260 str r2, [r0] 1332:Src/main.c **** htim8.Init.CounterMode = TIM_COUNTERMODE_UP; 7266 .loc 2 1332 3 is_stmt 1 view .LVU2330 1332:Src/main.c **** htim8.Init.CounterMode = TIM_COUNTERMODE_UP; 7267 .loc 2 1332 24 is_stmt 0 view .LVU2331 7268 001a 4360 str r3, [r0, #4] 1333:Src/main.c **** htim8.Init.Period = 91; 7269 .loc 2 1333 3 is_stmt 1 view .LVU2332 1333:Src/main.c **** htim8.Init.Period = 91; 7270 .loc 2 1333 26 is_stmt 0 view .LVU2333 7271 001c 8360 str r3, [r0, #8] 1334:Src/main.c **** htim8.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; 7272 .loc 2 1334 3 is_stmt 1 view .LVU2334 1334:Src/main.c **** htim8.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; 7273 .loc 2 1334 21 is_stmt 0 view .LVU2335 7274 001e 5B22 movs r2, #91 7275 0020 C260 str r2, [r0, #12] 1335:Src/main.c **** htim8.Init.RepetitionCounter = 0; 7276 .loc 2 1335 3 is_stmt 1 view .LVU2336 1335:Src/main.c **** htim8.Init.RepetitionCounter = 0; 7277 .loc 2 1335 28 is_stmt 0 view .LVU2337 7278 0022 0361 str r3, [r0, #16] 1336:Src/main.c **** htim8.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; 7279 .loc 2 1336 3 is_stmt 1 view .LVU2338 1336:Src/main.c **** htim8.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; 7280 .loc 2 1336 32 is_stmt 0 view .LVU2339 7281 0024 4361 str r3, [r0, #20] 1337:Src/main.c **** if (HAL_TIM_Base_Init(&htim8) != HAL_OK) 7282 .loc 2 1337 3 is_stmt 1 view .LVU2340 1337:Src/main.c **** if (HAL_TIM_Base_Init(&htim8) != HAL_OK) 7283 .loc 2 1337 32 is_stmt 0 view .LVU2341 ARM GAS /tmp/ccqopZd5.s page 499 7284 0026 8361 str r3, [r0, #24] 1338:Src/main.c **** { 7285 .loc 2 1338 3 is_stmt 1 view .LVU2342 1338:Src/main.c **** { 7286 .loc 2 1338 7 is_stmt 0 view .LVU2343 7287 0028 FFF7FEFF bl HAL_TIM_Base_Init 7288 .LVL572: 1338:Src/main.c **** { 7289 .loc 2 1338 6 view .LVU2344 7290 002c 98B9 cbnz r0, .L330 1342:Src/main.c **** if (HAL_TIM_ConfigClockSource(&htim8, &sClockSourceConfig) != HAL_OK) 7291 .loc 2 1342 3 is_stmt 1 view .LVU2345 1342:Src/main.c **** if (HAL_TIM_ConfigClockSource(&htim8, &sClockSourceConfig) != HAL_OK) 7292 .loc 2 1342 34 is_stmt 0 view .LVU2346 7293 002e 4FF48053 mov r3, #4096 7294 0032 0493 str r3, [sp, #16] 1343:Src/main.c **** { 7295 .loc 2 1343 3 is_stmt 1 view .LVU2347 1343:Src/main.c **** { 7296 .loc 2 1343 7 is_stmt 0 view .LVU2348 7297 0034 04A9 add r1, sp, #16 7298 0036 0B48 ldr r0, .L333 7299 0038 FFF7FEFF bl HAL_TIM_ConfigClockSource 7300 .LVL573: 1343:Src/main.c **** { 7301 .loc 2 1343 6 view .LVU2349 7302 003c 68B9 cbnz r0, .L331 1347:Src/main.c **** sMasterConfig.MasterOutputTrigger2 = TIM_TRGO2_RESET; 7303 .loc 2 1347 3 is_stmt 1 view .LVU2350 1347:Src/main.c **** sMasterConfig.MasterOutputTrigger2 = TIM_TRGO2_RESET; 7304 .loc 2 1347 37 is_stmt 0 view .LVU2351 7305 003e 0023 movs r3, #0 7306 0040 0193 str r3, [sp, #4] 1348:Src/main.c **** sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; 7307 .loc 2 1348 3 is_stmt 1 view .LVU2352 1348:Src/main.c **** sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; 7308 .loc 2 1348 38 is_stmt 0 view .LVU2353 7309 0042 0293 str r3, [sp, #8] 1349:Src/main.c **** if (HAL_TIMEx_MasterConfigSynchronization(&htim8, &sMasterConfig) != HAL_OK) 7310 .loc 2 1349 3 is_stmt 1 view .LVU2354 1349:Src/main.c **** if (HAL_TIMEx_MasterConfigSynchronization(&htim8, &sMasterConfig) != HAL_OK) 7311 .loc 2 1349 33 is_stmt 0 view .LVU2355 7312 0044 0393 str r3, [sp, #12] 1350:Src/main.c **** { 7313 .loc 2 1350 3 is_stmt 1 view .LVU2356 1350:Src/main.c **** { 7314 .loc 2 1350 7 is_stmt 0 view .LVU2357 7315 0046 01A9 add r1, sp, #4 7316 0048 0648 ldr r0, .L333 7317 004a FFF7FEFF bl HAL_TIMEx_MasterConfigSynchronization 7318 .LVL574: 1350:Src/main.c **** { 7319 .loc 2 1350 6 view .LVU2358 7320 004e 30B9 cbnz r0, .L332 1358:Src/main.c **** 7321 .loc 2 1358 1 view .LVU2359 7322 0050 09B0 add sp, sp, #36 ARM GAS /tmp/ccqopZd5.s page 500 7323 .LCFI67: 7324 .cfi_remember_state 7325 .cfi_def_cfa_offset 4 7326 @ sp needed 7327 0052 5DF804FB ldr pc, [sp], #4 7328 .L330: 7329 .LCFI68: 7330 .cfi_restore_state 1340:Src/main.c **** } 7331 .loc 2 1340 5 is_stmt 1 view .LVU2360 7332 0056 FFF7FEFF bl Error_Handler 7333 .LVL575: 7334 .L331: 1345:Src/main.c **** } 7335 .loc 2 1345 5 view .LVU2361 7336 005a FFF7FEFF bl Error_Handler 7337 .LVL576: 7338 .L332: 1352:Src/main.c **** } 7339 .loc 2 1352 5 view .LVU2362 7340 005e FFF7FEFF bl Error_Handler 7341 .LVL577: 7342 .L334: 7343 0062 00BF .align 2 7344 .L333: 7345 0064 00000000 .word .LANCHOR36 7346 0068 00040140 .word 1073808384 7347 .cfi_endproc 7348 .LFE1199: 7350 .section .text.MX_TIM11_Init,"ax",%progbits 7351 .align 1 7352 .syntax unified 7353 .thumb 7354 .thumb_func 7355 .fpu fpv5-d16 7357 MX_TIM11_Init: 7358 .LFB1201: 1397:Src/main.c **** 7359 .loc 2 1397 1 view -0 7360 .cfi_startproc 7361 @ args = 0, pretend = 0, frame = 32 7362 @ frame_needed = 0, uses_anonymous_args = 0 7363 0000 00B5 push {lr} 7364 .LCFI69: 7365 .cfi_def_cfa_offset 4 7366 .cfi_offset 14, -4 7367 0002 89B0 sub sp, sp, #36 7368 .LCFI70: 7369 .cfi_def_cfa_offset 40 1403:Src/main.c **** 7370 .loc 2 1403 3 view .LVU2364 1403:Src/main.c **** 7371 .loc 2 1403 22 is_stmt 0 view .LVU2365 7372 0004 0023 movs r3, #0 7373 0006 0193 str r3, [sp, #4] 7374 0008 0293 str r3, [sp, #8] 7375 000a 0393 str r3, [sp, #12] ARM GAS /tmp/ccqopZd5.s page 501 7376 000c 0493 str r3, [sp, #16] 7377 000e 0593 str r3, [sp, #20] 7378 0010 0693 str r3, [sp, #24] 7379 0012 0793 str r3, [sp, #28] 1408:Src/main.c **** htim11.Init.Prescaler = 0; 7380 .loc 2 1408 3 is_stmt 1 view .LVU2366 1408:Src/main.c **** htim11.Init.Prescaler = 0; 7381 .loc 2 1408 19 is_stmt 0 view .LVU2367 7382 0014 1548 ldr r0, .L343 7383 0016 164A ldr r2, .L343+4 7384 0018 0260 str r2, [r0] 1409:Src/main.c **** htim11.Init.CounterMode = TIM_COUNTERMODE_UP; 7385 .loc 2 1409 3 is_stmt 1 view .LVU2368 1409:Src/main.c **** htim11.Init.CounterMode = TIM_COUNTERMODE_UP; 7386 .loc 2 1409 25 is_stmt 0 view .LVU2369 7387 001a 4360 str r3, [r0, #4] 1410:Src/main.c **** htim11.Init.Period = 183; 7388 .loc 2 1410 3 is_stmt 1 view .LVU2370 1410:Src/main.c **** htim11.Init.Period = 183; 7389 .loc 2 1410 27 is_stmt 0 view .LVU2371 7390 001c 8360 str r3, [r0, #8] 1411:Src/main.c **** htim11.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; 7391 .loc 2 1411 3 is_stmt 1 view .LVU2372 1411:Src/main.c **** htim11.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; 7392 .loc 2 1411 22 is_stmt 0 view .LVU2373 7393 001e B722 movs r2, #183 7394 0020 C260 str r2, [r0, #12] 1412:Src/main.c **** htim11.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_ENABLE; 7395 .loc 2 1412 3 is_stmt 1 view .LVU2374 1412:Src/main.c **** htim11.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_ENABLE; 7396 .loc 2 1412 29 is_stmt 0 view .LVU2375 7397 0022 0361 str r3, [r0, #16] 1413:Src/main.c **** if (HAL_TIM_Base_Init(&htim11) != HAL_OK) 7398 .loc 2 1413 3 is_stmt 1 view .LVU2376 1413:Src/main.c **** if (HAL_TIM_Base_Init(&htim11) != HAL_OK) 7399 .loc 2 1413 33 is_stmt 0 view .LVU2377 7400 0024 8023 movs r3, #128 7401 0026 8361 str r3, [r0, #24] 1414:Src/main.c **** { 7402 .loc 2 1414 3 is_stmt 1 view .LVU2378 1414:Src/main.c **** { 7403 .loc 2 1414 7 is_stmt 0 view .LVU2379 7404 0028 FFF7FEFF bl HAL_TIM_Base_Init 7405 .LVL578: 1414:Src/main.c **** { 7406 .loc 2 1414 6 view .LVU2380 7407 002c B8B9 cbnz r0, .L340 1418:Src/main.c **** { 7408 .loc 2 1418 3 is_stmt 1 view .LVU2381 1418:Src/main.c **** { 7409 .loc 2 1418 7 is_stmt 0 view .LVU2382 7410 002e 0F48 ldr r0, .L343 7411 0030 FFF7FEFF bl HAL_TIM_PWM_Init 7412 .LVL579: 1418:Src/main.c **** { 7413 .loc 2 1418 6 view .LVU2383 7414 0034 A8B9 cbnz r0, .L341 ARM GAS /tmp/ccqopZd5.s page 502 1422:Src/main.c **** sConfigOC.Pulse = 91; 7415 .loc 2 1422 3 is_stmt 1 view .LVU2384 1422:Src/main.c **** sConfigOC.Pulse = 91; 7416 .loc 2 1422 20 is_stmt 0 view .LVU2385 7417 0036 6023 movs r3, #96 7418 0038 0193 str r3, [sp, #4] 1423:Src/main.c **** sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH; 7419 .loc 2 1423 3 is_stmt 1 view .LVU2386 1423:Src/main.c **** sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH; 7420 .loc 2 1423 19 is_stmt 0 view .LVU2387 7421 003a 5B23 movs r3, #91 7422 003c 0293 str r3, [sp, #8] 1424:Src/main.c **** sConfigOC.OCFastMode = TIM_OCFAST_ENABLE; 7423 .loc 2 1424 3 is_stmt 1 view .LVU2388 1424:Src/main.c **** sConfigOC.OCFastMode = TIM_OCFAST_ENABLE; 7424 .loc 2 1424 24 is_stmt 0 view .LVU2389 7425 003e 0022 movs r2, #0 7426 0040 0392 str r2, [sp, #12] 1425:Src/main.c **** if (HAL_TIM_PWM_ConfigChannel(&htim11, &sConfigOC, TIM_CHANNEL_1) != HAL_OK) 7427 .loc 2 1425 3 is_stmt 1 view .LVU2390 1425:Src/main.c **** if (HAL_TIM_PWM_ConfigChannel(&htim11, &sConfigOC, TIM_CHANNEL_1) != HAL_OK) 7428 .loc 2 1425 24 is_stmt 0 view .LVU2391 7429 0042 0423 movs r3, #4 7430 0044 0593 str r3, [sp, #20] 1426:Src/main.c **** { 7431 .loc 2 1426 3 is_stmt 1 view .LVU2392 1426:Src/main.c **** { 7432 .loc 2 1426 7 is_stmt 0 view .LVU2393 7433 0046 0DEB0301 add r1, sp, r3 7434 004a 0848 ldr r0, .L343 7435 004c FFF7FEFF bl HAL_TIM_PWM_ConfigChannel 7436 .LVL580: 1426:Src/main.c **** { 7437 .loc 2 1426 6 view .LVU2394 7438 0050 48B9 cbnz r0, .L342 1433:Src/main.c **** 7439 .loc 2 1433 3 is_stmt 1 view .LVU2395 7440 0052 0648 ldr r0, .L343 7441 0054 FFF7FEFF bl HAL_TIM_MspPostInit 7442 .LVL581: 1435:Src/main.c **** 7443 .loc 2 1435 1 is_stmt 0 view .LVU2396 7444 0058 09B0 add sp, sp, #36 7445 .LCFI71: 7446 .cfi_remember_state 7447 .cfi_def_cfa_offset 4 7448 @ sp needed 7449 005a 5DF804FB ldr pc, [sp], #4 7450 .L340: 7451 .LCFI72: 7452 .cfi_restore_state 1416:Src/main.c **** } 7453 .loc 2 1416 5 is_stmt 1 view .LVU2397 7454 005e FFF7FEFF bl Error_Handler 7455 .LVL582: 7456 .L341: 1420:Src/main.c **** } ARM GAS /tmp/ccqopZd5.s page 503 7457 .loc 2 1420 5 view .LVU2398 7458 0062 FFF7FEFF bl Error_Handler 7459 .LVL583: 7460 .L342: 1428:Src/main.c **** } 7461 .loc 2 1428 5 view .LVU2399 7462 0066 FFF7FEFF bl Error_Handler 7463 .LVL584: 7464 .L344: 7465 006a 00BF .align 2 7466 .L343: 7467 006c 00000000 .word .LANCHOR37 7468 0070 00480140 .word 1073825792 7469 .cfi_endproc 7470 .LFE1201: 7472 .section .text.SystemClock_Config,"ax",%progbits 7473 .align 1 7474 .global SystemClock_Config 7475 .syntax unified 7476 .thumb 7477 .thumb_func 7478 .fpu fpv5-d16 7480 SystemClock_Config: 7481 .LFB1187: 693:Src/main.c **** RCC_OscInitTypeDef RCC_OscInitStruct = {0}; 7482 .loc 2 693 1 view -0 7483 .cfi_startproc 7484 @ args = 0, pretend = 0, frame = 80 7485 @ frame_needed = 0, uses_anonymous_args = 0 7486 0000 00B5 push {lr} 7487 .LCFI73: 7488 .cfi_def_cfa_offset 4 7489 .cfi_offset 14, -4 7490 0002 95B0 sub sp, sp, #84 7491 .LCFI74: 7492 .cfi_def_cfa_offset 88 694:Src/main.c **** RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; 7493 .loc 2 694 3 view .LVU2401 694:Src/main.c **** RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; 7494 .loc 2 694 22 is_stmt 0 view .LVU2402 7495 0004 3422 movs r2, #52 7496 0006 0021 movs r1, #0 7497 0008 07A8 add r0, sp, #28 7498 000a FFF7FEFF bl memset 7499 .LVL585: 695:Src/main.c **** 7500 .loc 2 695 3 is_stmt 1 view .LVU2403 695:Src/main.c **** 7501 .loc 2 695 22 is_stmt 0 view .LVU2404 7502 000e 0023 movs r3, #0 7503 0010 0293 str r3, [sp, #8] 7504 0012 0393 str r3, [sp, #12] 7505 0014 0493 str r3, [sp, #16] 7506 0016 0593 str r3, [sp, #20] 7507 0018 0693 str r3, [sp, #24] 699:Src/main.c **** __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); 7508 .loc 2 699 3 is_stmt 1 view .LVU2405 ARM GAS /tmp/ccqopZd5.s page 504 7509 .LBB539: 699:Src/main.c **** __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); 7510 .loc 2 699 3 view .LVU2406 699:Src/main.c **** __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); 7511 .loc 2 699 3 view .LVU2407 7512 001a 244B ldr r3, .L353 7513 001c 1A6C ldr r2, [r3, #64] 7514 001e 42F08052 orr r2, r2, #268435456 7515 0022 1A64 str r2, [r3, #64] 699:Src/main.c **** __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); 7516 .loc 2 699 3 view .LVU2408 7517 0024 1B6C ldr r3, [r3, #64] 7518 0026 03F08053 and r3, r3, #268435456 7519 002a 0093 str r3, [sp] 699:Src/main.c **** __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); 7520 .loc 2 699 3 view .LVU2409 7521 002c 009B ldr r3, [sp] 7522 .LBE539: 699:Src/main.c **** __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); 7523 .loc 2 699 3 view .LVU2410 700:Src/main.c **** 7524 .loc 2 700 3 view .LVU2411 7525 .LBB540: 700:Src/main.c **** 7526 .loc 2 700 3 view .LVU2412 700:Src/main.c **** 7527 .loc 2 700 3 view .LVU2413 7528 002e 204B ldr r3, .L353+4 7529 0030 1A68 ldr r2, [r3] 7530 0032 42F44042 orr r2, r2, #49152 7531 0036 1A60 str r2, [r3] 700:Src/main.c **** 7532 .loc 2 700 3 view .LVU2414 7533 0038 1B68 ldr r3, [r3] 7534 003a 03F44043 and r3, r3, #49152 7535 003e 0193 str r3, [sp, #4] 700:Src/main.c **** 7536 .loc 2 700 3 view .LVU2415 7537 0040 019B ldr r3, [sp, #4] 7538 .LBE540: 700:Src/main.c **** 7539 .loc 2 700 3 view .LVU2416 705:Src/main.c **** RCC_OscInitStruct.HSEState = RCC_HSE_ON; 7540 .loc 2 705 3 view .LVU2417 705:Src/main.c **** RCC_OscInitStruct.HSEState = RCC_HSE_ON; 7541 .loc 2 705 36 is_stmt 0 view .LVU2418 7542 0042 0123 movs r3, #1 7543 0044 0793 str r3, [sp, #28] 706:Src/main.c **** RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; 7544 .loc 2 706 3 is_stmt 1 view .LVU2419 706:Src/main.c **** RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; 7545 .loc 2 706 30 is_stmt 0 view .LVU2420 7546 0046 4FF48033 mov r3, #65536 7547 004a 0893 str r3, [sp, #32] 707:Src/main.c **** RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; 7548 .loc 2 707 3 is_stmt 1 view .LVU2421 707:Src/main.c **** RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; ARM GAS /tmp/ccqopZd5.s page 505 7549 .loc 2 707 34 is_stmt 0 view .LVU2422 7550 004c 0223 movs r3, #2 7551 004e 0D93 str r3, [sp, #52] 708:Src/main.c **** RCC_OscInitStruct.PLL.PLLM = 25; 7552 .loc 2 708 3 is_stmt 1 view .LVU2423 708:Src/main.c **** RCC_OscInitStruct.PLL.PLLM = 25; 7553 .loc 2 708 35 is_stmt 0 view .LVU2424 7554 0050 4FF48002 mov r2, #4194304 7555 0054 0E92 str r2, [sp, #56] 709:Src/main.c **** RCC_OscInitStruct.PLL.PLLN = 368; 7556 .loc 2 709 3 is_stmt 1 view .LVU2425 709:Src/main.c **** RCC_OscInitStruct.PLL.PLLN = 368; 7557 .loc 2 709 30 is_stmt 0 view .LVU2426 7558 0056 1922 movs r2, #25 7559 0058 0F92 str r2, [sp, #60] 710:Src/main.c **** RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; 7560 .loc 2 710 3 is_stmt 1 view .LVU2427 710:Src/main.c **** RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; 7561 .loc 2 710 30 is_stmt 0 view .LVU2428 7562 005a 4FF4B872 mov r2, #368 7563 005e 1092 str r2, [sp, #64] 711:Src/main.c **** RCC_OscInitStruct.PLL.PLLQ = 8; 7564 .loc 2 711 3 is_stmt 1 view .LVU2429 711:Src/main.c **** RCC_OscInitStruct.PLL.PLLQ = 8; 7565 .loc 2 711 30 is_stmt 0 view .LVU2430 7566 0060 1193 str r3, [sp, #68] 712:Src/main.c **** RCC_OscInitStruct.PLL.PLLR = 2; 7567 .loc 2 712 3 is_stmt 1 view .LVU2431 712:Src/main.c **** RCC_OscInitStruct.PLL.PLLR = 2; 7568 .loc 2 712 30 is_stmt 0 view .LVU2432 7569 0062 0822 movs r2, #8 7570 0064 1292 str r2, [sp, #72] 713:Src/main.c **** if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) 7571 .loc 2 713 3 is_stmt 1 view .LVU2433 713:Src/main.c **** if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) 7572 .loc 2 713 30 is_stmt 0 view .LVU2434 7573 0066 1393 str r3, [sp, #76] 714:Src/main.c **** { 7574 .loc 2 714 3 is_stmt 1 view .LVU2435 714:Src/main.c **** { 7575 .loc 2 714 7 is_stmt 0 view .LVU2436 7576 0068 07A8 add r0, sp, #28 7577 006a FFF7FEFF bl HAL_RCC_OscConfig 7578 .LVL586: 714:Src/main.c **** { 7579 .loc 2 714 6 view .LVU2437 7580 006e B0B9 cbnz r0, .L350 721:Src/main.c **** { 7581 .loc 2 721 3 is_stmt 1 view .LVU2438 721:Src/main.c **** { 7582 .loc 2 721 7 is_stmt 0 view .LVU2439 7583 0070 FFF7FEFF bl HAL_PWREx_EnableOverDrive 7584 .LVL587: 721:Src/main.c **** { 7585 .loc 2 721 6 view .LVU2440 7586 0074 A8B9 cbnz r0, .L351 728:Src/main.c **** |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; ARM GAS /tmp/ccqopZd5.s page 506 7587 .loc 2 728 3 is_stmt 1 view .LVU2441 728:Src/main.c **** |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; 7588 .loc 2 728 31 is_stmt 0 view .LVU2442 7589 0076 0F23 movs r3, #15 7590 0078 0293 str r3, [sp, #8] 730:Src/main.c **** RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; 7591 .loc 2 730 3 is_stmt 1 view .LVU2443 730:Src/main.c **** RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; 7592 .loc 2 730 34 is_stmt 0 view .LVU2444 7593 007a 0223 movs r3, #2 7594 007c 0393 str r3, [sp, #12] 731:Src/main.c **** RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4; 7595 .loc 2 731 3 is_stmt 1 view .LVU2445 731:Src/main.c **** RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4; 7596 .loc 2 731 35 is_stmt 0 view .LVU2446 7597 007e 0023 movs r3, #0 7598 0080 0493 str r3, [sp, #16] 732:Src/main.c **** RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; 7599 .loc 2 732 3 is_stmt 1 view .LVU2447 732:Src/main.c **** RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; 7600 .loc 2 732 36 is_stmt 0 view .LVU2448 7601 0082 4FF4A053 mov r3, #5120 7602 0086 0593 str r3, [sp, #20] 733:Src/main.c **** 7603 .loc 2 733 3 is_stmt 1 view .LVU2449 733:Src/main.c **** 7604 .loc 2 733 36 is_stmt 0 view .LVU2450 7605 0088 4FF48053 mov r3, #4096 7606 008c 0693 str r3, [sp, #24] 735:Src/main.c **** { 7607 .loc 2 735 3 is_stmt 1 view .LVU2451 735:Src/main.c **** { 7608 .loc 2 735 7 is_stmt 0 view .LVU2452 7609 008e 0621 movs r1, #6 7610 0090 02A8 add r0, sp, #8 7611 0092 FFF7FEFF bl HAL_RCC_ClockConfig 7612 .LVL588: 735:Src/main.c **** { 7613 .loc 2 735 6 view .LVU2453 7614 0096 30B9 cbnz r0, .L352 739:Src/main.c **** 7615 .loc 2 739 1 view .LVU2454 7616 0098 15B0 add sp, sp, #84 7617 .LCFI75: 7618 .cfi_remember_state 7619 .cfi_def_cfa_offset 4 7620 @ sp needed 7621 009a 5DF804FB ldr pc, [sp], #4 7622 .L350: 7623 .LCFI76: 7624 .cfi_restore_state 716:Src/main.c **** } 7625 .loc 2 716 5 is_stmt 1 view .LVU2455 7626 009e FFF7FEFF bl Error_Handler 7627 .LVL589: 7628 .L351: 723:Src/main.c **** } ARM GAS /tmp/ccqopZd5.s page 507 7629 .loc 2 723 5 view .LVU2456 7630 00a2 FFF7FEFF bl Error_Handler 7631 .LVL590: 7632 .L352: 737:Src/main.c **** } 7633 .loc 2 737 5 view .LVU2457 7634 00a6 FFF7FEFF bl Error_Handler 7635 .LVL591: 7636 .L354: 7637 00aa 00BF .align 2 7638 .L353: 7639 00ac 00380240 .word 1073887232 7640 00b0 00700040 .word 1073770496 7641 .cfi_endproc 7642 .LFE1187: 7644 .section .text.main,"ax",%progbits 7645 .align 1 7646 .global main 7647 .syntax unified 7648 .thumb 7649 .thumb_func 7650 .fpu fpv5-d16 7652 main: 7653 .LFB1186: 127:Src/main.c **** 7654 .loc 2 127 1 view -0 7655 .cfi_startproc 7656 @ args = 0, pretend = 0, frame = 8 7657 @ frame_needed = 0, uses_anonymous_args = 0 7658 0000 2DE9F043 push {r4, r5, r6, r7, r8, r9, lr} 7659 .LCFI77: 7660 .cfi_def_cfa_offset 28 7661 .cfi_offset 4, -28 7662 .cfi_offset 5, -24 7663 .cfi_offset 6, -20 7664 .cfi_offset 7, -16 7665 .cfi_offset 8, -12 7666 .cfi_offset 9, -8 7667 .cfi_offset 14, -4 7668 0004 83B0 sub sp, sp, #12 7669 .LCFI78: 7670 .cfi_def_cfa_offset 40 130:Src/main.c **** /* USER CODE END 1 */ 7671 .loc 2 130 2 view .LVU2459 136:Src/main.c **** 7672 .loc 2 136 3 view .LVU2460 7673 0006 FFF7FEFF bl HAL_Init 7674 .LVL592: 143:Src/main.c **** 7675 .loc 2 143 3 view .LVU2461 7676 000a FFF7FEFF bl SystemClock_Config 7677 .LVL593: 150:Src/main.c **** MX_DMA_Init(); 7678 .loc 2 150 3 view .LVU2462 7679 000e FFF7FEFF bl MX_GPIO_Init 7680 .LVL594: 151:Src/main.c **** MX_SPI4_Init(); ARM GAS /tmp/ccqopZd5.s page 508 7681 .loc 2 151 3 view .LVU2463 7682 0012 FFF7FEFF bl MX_DMA_Init 7683 .LVL595: 152:Src/main.c **** MX_FATFS_Init(); 7684 .loc 2 152 3 view .LVU2464 7685 0016 FFF7FEFF bl MX_SPI4_Init 7686 .LVL596: 153:Src/main.c **** MX_TIM2_Init(); 7687 .loc 2 153 3 view .LVU2465 7688 001a FFF7FEFF bl MX_FATFS_Init 7689 .LVL597: 154:Src/main.c **** MX_TIM5_Init(); 7690 .loc 2 154 3 view .LVU2466 7691 001e FFF7FEFF bl MX_TIM2_Init 7692 .LVL598: 155:Src/main.c **** MX_ADC1_Init(); 7693 .loc 2 155 3 view .LVU2467 7694 0022 FFF7FEFF bl MX_TIM5_Init 7695 .LVL599: 156:Src/main.c **** MX_ADC3_Init(); 7696 .loc 2 156 3 view .LVU2468 7697 0026 FFF7FEFF bl MX_ADC1_Init 7698 .LVL600: 157:Src/main.c **** MX_SPI2_Init(); 7699 .loc 2 157 3 view .LVU2469 7700 002a FFF7FEFF bl MX_ADC3_Init 7701 .LVL601: 158:Src/main.c **** MX_SPI5_Init(); 7702 .loc 2 158 3 view .LVU2470 7703 002e FFF7FEFF bl MX_SPI2_Init 7704 .LVL602: 159:Src/main.c **** MX_SPI6_Init(); 7705 .loc 2 159 3 view .LVU2471 7706 0032 FFF7FEFF bl MX_SPI5_Init 7707 .LVL603: 160:Src/main.c **** MX_USART1_UART_Init(); 7708 .loc 2 160 3 view .LVU2472 7709 0036 FFF7FEFF bl MX_SPI6_Init 7710 .LVL604: 161:Src/main.c **** MX_SDMMC1_SD_Init(); 7711 .loc 2 161 3 view .LVU2473 7712 003a FFF7FEFF bl MX_USART1_UART_Init 7713 .LVL605: 162:Src/main.c **** MX_TIM7_Init(); 7714 .loc 2 162 3 view .LVU2474 7715 003e FFF7FEFF bl MX_SDMMC1_SD_Init 7716 .LVL606: 163:Src/main.c **** MX_TIM6_Init(); 7717 .loc 2 163 3 view .LVU2475 7718 0042 FFF7FEFF bl MX_TIM7_Init 7719 .LVL607: 164:Src/main.c **** MX_TIM10_Init(); 7720 .loc 2 164 3 view .LVU2476 7721 0046 FFF7FEFF bl MX_TIM6_Init 7722 .LVL608: 165:Src/main.c **** MX_UART8_Init(); 7723 .loc 2 165 3 view .LVU2477 ARM GAS /tmp/ccqopZd5.s page 509 7724 004a FFF7FEFF bl MX_TIM10_Init 7725 .LVL609: 166:Src/main.c **** MX_TIM8_Init(); 7726 .loc 2 166 3 view .LVU2478 7727 004e FFF7FEFF bl MX_UART8_Init 7728 .LVL610: 167:Src/main.c **** MX_TIM11_Init(); 7729 .loc 2 167 3 view .LVU2479 7730 0052 FFF7FEFF bl MX_TIM8_Init 7731 .LVL611: 168:Src/main.c **** /* USER CODE BEGIN 2 */ 7732 .loc 2 168 3 view .LVU2480 7733 0056 FFF7FEFF bl MX_TIM11_Init 7734 .LVL612: 170:Src/main.c **** HAL_TIM_Base_Start(&htim11); 7735 .loc 2 170 2 view .LVU2481 7736 005a FFF7FEFF bl Init_params 7737 .LVL613: 171:Src/main.c **** HAL_TIM_PWM_Start(&htim11, TIM_CHANNEL_1); //start modulating by Mach-Zander modulator 7738 .loc 2 171 2 view .LVU2482 7739 005e 784C ldr r4, .L420 7740 0060 2046 mov r0, r4 7741 0062 FFF7FEFF bl HAL_TIM_Base_Start 7742 .LVL614: 172:Src/main.c **** /* 7743 .loc 2 172 2 view .LVU2483 7744 0066 0021 movs r1, #0 7745 0068 2046 mov r0, r4 7746 006a FFF7FEFF bl HAL_TIM_PWM_Start 7747 .LVL615: 7748 006e 3FE0 b .L356 7749 .L412: 185:Src/main.c **** { 7750 .loc 2 185 85 is_stmt 0 discriminator 1 view .LVU2484 7751 0070 744B ldr r3, .L420+4 7752 0072 1B78 ldrb r3, [r3] @ zero_extendqisi2 185:Src/main.c **** { 7753 .loc 2 185 73 discriminator 1 view .LVU2485 7754 0074 002B cmp r3, #0 7755 0076 42D1 bne .L357 7756 .L358: 3073:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 7757 .loc 7 3073 3 is_stmt 1 view .LVU2486 7758 .LBB541: 7759 .LBB542: 3073:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 7760 .loc 7 3073 3 view .LVU2487 3073:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 7761 .loc 7 3073 3 view .LVU2488 3073:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 7762 .loc 7 3073 3 view .LVU2489 7763 0078 734B ldr r3, .L420+8 7764 .LVL616: 7765 .LBB543: 7766 .LBI543: 1068:Drivers/CMSIS/Include/cmsis_gcc.h **** { 7767 .loc 8 1068 31 view .LVU2490 ARM GAS /tmp/ccqopZd5.s page 510 7768 .LBB544: 1070:Drivers/CMSIS/Include/cmsis_gcc.h **** 7769 .loc 8 1070 5 view .LVU2491 1072:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 7770 .loc 8 1072 4 view .LVU2492 7771 .syntax unified 7772 @ 1072 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 7773 007a 53E8002F ldrex r2, [r3] 7774 @ 0 "" 2 7775 .LVL617: 1073:Drivers/CMSIS/Include/cmsis_gcc.h **** } 7776 .loc 8 1073 4 view .LVU2493 1073:Drivers/CMSIS/Include/cmsis_gcc.h **** } 7777 .loc 8 1073 4 is_stmt 0 view .LVU2494 7778 .thumb 7779 .syntax unified 7780 .LBE544: 7781 .LBE543: 3073:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 7782 .loc 7 3073 3 view .LVU2495 7783 007e 42F48072 orr r2, r2, #256 7784 .LVL618: 3073:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 7785 .loc 7 3073 3 is_stmt 1 view .LVU2496 7786 .LBB545: 7787 .LBI545: 1119:Drivers/CMSIS/Include/cmsis_gcc.h **** { 7788 .loc 8 1119 31 view .LVU2497 7789 .LBB546: 1121:Drivers/CMSIS/Include/cmsis_gcc.h **** 7790 .loc 8 1121 4 view .LVU2498 1123:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 7791 .loc 8 1123 4 view .LVU2499 7792 .syntax unified 7793 @ 1123 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 7794 0082 43E80021 strex r1, r2, [r3] 7795 @ 0 "" 2 7796 .LVL619: 7797 .loc 8 1124 4 view .LVU2500 7798 .loc 8 1124 4 is_stmt 0 view .LVU2501 7799 .thumb 7800 .syntax unified 7801 .LBE546: 7802 .LBE545: 3073:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 7803 .loc 7 3073 3 view .LVU2502 7804 0086 0029 cmp r1, #0 7805 0088 F6D1 bne .L358 7806 .LVL620: 7807 .L359: 3073:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 7808 .loc 7 3073 3 view .LVU2503 7809 .LBE542: 7810 .LBE541: 3040:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 7811 .loc 7 3040 3 is_stmt 1 view .LVU2504 7812 .LBB547: ARM GAS /tmp/ccqopZd5.s page 511 7813 .LBB548: 3040:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 7814 .loc 7 3040 3 view .LVU2505 3040:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 7815 .loc 7 3040 3 view .LVU2506 3040:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 7816 .loc 7 3040 3 view .LVU2507 7817 .LBB549: 7818 .LBI549: 1068:Drivers/CMSIS/Include/cmsis_gcc.h **** { 7819 .loc 8 1068 31 view .LVU2508 7820 .LBB550: 1070:Drivers/CMSIS/Include/cmsis_gcc.h **** 7821 .loc 8 1070 5 view .LVU2509 1072:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 7822 .loc 8 1072 4 view .LVU2510 7823 .syntax unified 7824 @ 1072 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 7825 008a 53E8002F ldrex r2, [r3] 7826 @ 0 "" 2 7827 .LVL621: 1073:Drivers/CMSIS/Include/cmsis_gcc.h **** } 7828 .loc 8 1073 4 view .LVU2511 1073:Drivers/CMSIS/Include/cmsis_gcc.h **** } 7829 .loc 8 1073 4 is_stmt 0 view .LVU2512 7830 .thumb 7831 .syntax unified 7832 .LBE550: 7833 .LBE549: 3040:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 7834 .loc 7 3040 3 view .LVU2513 7835 008e 42F02002 orr r2, r2, #32 7836 .LVL622: 3040:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 7837 .loc 7 3040 3 is_stmt 1 view .LVU2514 7838 .LBB551: 7839 .LBI551: 1119:Drivers/CMSIS/Include/cmsis_gcc.h **** { 7840 .loc 8 1119 31 view .LVU2515 7841 .LBB552: 1121:Drivers/CMSIS/Include/cmsis_gcc.h **** 7842 .loc 8 1121 4 view .LVU2516 1123:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 7843 .loc 8 1123 4 view .LVU2517 7844 .syntax unified 7845 @ 1123 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 7846 0092 43E80021 strex r1, r2, [r3] 7847 @ 0 "" 2 7848 .LVL623: 7849 .loc 8 1124 4 view .LVU2518 7850 .loc 8 1124 4 is_stmt 0 view .LVU2519 7851 .thumb 7852 .syntax unified 7853 .LBE552: 7854 .LBE551: 3040:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 7855 .loc 7 3040 3 view .LVU2520 ARM GAS /tmp/ccqopZd5.s page 512 7856 0096 0029 cmp r1, #0 7857 0098 F7D1 bne .L359 7858 .LVL624: 7859 .L360: 3040:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 7860 .loc 7 3040 3 view .LVU2521 7861 .LBE548: 7862 .LBE547: 3136:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 7863 .loc 7 3136 3 is_stmt 1 view .LVU2522 7864 .LBB553: 7865 .LBB554: 3136:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 7866 .loc 7 3136 3 view .LVU2523 3136:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 7867 .loc 7 3136 3 view .LVU2524 3136:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 7868 .loc 7 3136 3 view .LVU2525 7869 009a 6C4A ldr r2, .L420+12 7870 .LVL625: 7871 .LBB555: 7872 .LBI555: 1068:Drivers/CMSIS/Include/cmsis_gcc.h **** { 7873 .loc 8 1068 31 view .LVU2526 7874 .LBB556: 1070:Drivers/CMSIS/Include/cmsis_gcc.h **** 7875 .loc 8 1070 5 view .LVU2527 1072:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 7876 .loc 8 1072 4 view .LVU2528 7877 .syntax unified 7878 @ 1072 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 7879 009c 52E8003F ldrex r3, [r2] 7880 @ 0 "" 2 7881 .LVL626: 1073:Drivers/CMSIS/Include/cmsis_gcc.h **** } 7882 .loc 8 1073 4 view .LVU2529 1073:Drivers/CMSIS/Include/cmsis_gcc.h **** } 7883 .loc 8 1073 4 is_stmt 0 view .LVU2530 7884 .thumb 7885 .syntax unified 7886 .LBE556: 7887 .LBE555: 3136:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 7888 .loc 7 3136 3 view .LVU2531 7889 00a0 43F00103 orr r3, r3, #1 7890 .LVL627: 3136:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 7891 .loc 7 3136 3 is_stmt 1 view .LVU2532 7892 .LBB557: 7893 .LBI557: 1119:Drivers/CMSIS/Include/cmsis_gcc.h **** { 7894 .loc 8 1119 31 view .LVU2533 7895 .LBB558: 1121:Drivers/CMSIS/Include/cmsis_gcc.h **** 7896 .loc 8 1121 4 view .LVU2534 1123:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 7897 .loc 8 1123 4 view .LVU2535 ARM GAS /tmp/ccqopZd5.s page 513 7898 .syntax unified 7899 @ 1123 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 7900 00a4 42E80031 strex r1, r3, [r2] 7901 @ 0 "" 2 7902 .LVL628: 7903 .loc 8 1124 4 view .LVU2536 7904 .loc 8 1124 4 is_stmt 0 view .LVU2537 7905 .thumb 7906 .syntax unified 7907 .LBE558: 7908 .LBE557: 3136:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 7909 .loc 7 3136 3 view .LVU2538 7910 00a8 0029 cmp r1, #0 7911 00aa F6D1 bne .L360 7912 .LBE554: 7913 .LBE553: 3136:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 7914 .loc 7 3136 3 is_stmt 1 view .LVU2539 7915 .LVL629: 191:Src/main.c **** NVIC_EnableIRQ(USART1_IRQn);//In other case you have FE error flag... 7916 .loc 2 191 4 view .LVU2540 7917 .LBB559: 7918 .LBI559: 2024:Drivers/CMSIS/Include/core_cm7.h **** { 7919 .loc 1 2024 22 view .LVU2541 7920 .LBB560: 2026:Drivers/CMSIS/Include/core_cm7.h **** { 7921 .loc 1 2026 3 view .LVU2542 2028:Drivers/CMSIS/Include/core_cm7.h **** } 7922 .loc 1 2028 5 view .LVU2543 2028:Drivers/CMSIS/Include/core_cm7.h **** } 7923 .loc 1 2028 47 is_stmt 0 view .LVU2544 7924 00ac 684B ldr r3, .L420+16 7925 00ae 0022 movs r2, #0 7926 00b0 83F82523 strb r2, [r3, #805] 7927 .LVL630: 2028:Drivers/CMSIS/Include/core_cm7.h **** } 7928 .loc 1 2028 47 view .LVU2545 7929 .LBE560: 7930 .LBE559: 192:Src/main.c **** u_rx_flg = 1; 7931 .loc 2 192 4 is_stmt 1 view .LVU2546 7932 .LBB561: 7933 .LBI561: 1896:Drivers/CMSIS/Include/core_cm7.h **** { 7934 .loc 1 1896 22 view .LVU2547 7935 .LBB562: 1898:Drivers/CMSIS/Include/core_cm7.h **** { 7936 .loc 1 1898 3 view .LVU2548 1900:Drivers/CMSIS/Include/core_cm7.h **** } 7937 .loc 1 1900 5 view .LVU2549 1900:Drivers/CMSIS/Include/core_cm7.h **** } 7938 .loc 1 1900 43 is_stmt 0 view .LVU2550 7939 00b4 2022 movs r2, #32 7940 00b6 5A60 str r2, [r3, #4] 7941 .LVL631: ARM GAS /tmp/ccqopZd5.s page 514 1900:Drivers/CMSIS/Include/core_cm7.h **** } 7942 .loc 1 1900 43 view .LVU2551 7943 .LBE562: 7944 .LBE561: 193:Src/main.c **** } 7945 .loc 2 193 4 is_stmt 1 view .LVU2552 193:Src/main.c **** } 7946 .loc 2 193 13 is_stmt 0 view .LVU2553 7947 00b8 624B ldr r3, .L420+4 7948 00ba 0122 movs r2, #1 7949 00bc 1A70 strb r2, [r3] 7950 00be 1EE0 b .L357 7951 .L372: 203:Src/main.c **** task.current_param = task.min_param; 7952 .loc 2 203 6 is_stmt 1 view .LVU2554 203:Src/main.c **** task.current_param = task.min_param; 7953 .loc 2 203 20 is_stmt 0 view .LVU2555 7954 00c0 644B ldr r3, .L420+20 7955 00c2 0022 movs r2, #0 7956 00c4 1A70 strb r2, [r3] 204:Src/main.c **** Stop_TIM10(); 7957 .loc 2 204 6 is_stmt 1 view .LVU2556 204:Src/main.c **** Stop_TIM10(); 7958 .loc 2 204 31 is_stmt 0 view .LVU2557 7959 00c6 644B ldr r3, .L420+24 7960 00c8 5A68 ldr r2, [r3, #4] @ float 204:Src/main.c **** Stop_TIM10(); 7961 .loc 2 204 25 view .LVU2558 7962 00ca 1A61 str r2, [r3, #16] @ float 205:Src/main.c **** break; 7963 .loc 2 205 6 is_stmt 1 view .LVU2559 7964 00cc FFF7FEFF bl Stop_TIM10 7965 .LVL632: 206:Src/main.c **** case DECODE_ENABLE://1 - Decode rec. message 7966 .loc 2 206 5 view .LVU2560 7967 .L361: 632:Src/main.c **** { 7968 .loc 2 632 3 view .LVU2561 7969 00d0 624B ldr r3, .L420+28 7970 00d2 1B78 ldrb r3, [r3] @ zero_extendqisi2 7971 00d4 022B cmp r3, #2 7972 00d6 00F0FD83 beq .L401 7973 00da 032B cmp r3, #3 7974 00dc 00F03084 beq .L408 7975 00e0 012B cmp r3, #1 7976 00e2 00F0EC83 beq .L410 7977 .L403: 674:Src/main.c **** { 7978 .loc 2 674 5 view .LVU2562 674:Src/main.c **** { 7979 .loc 2 674 17 is_stmt 0 view .LVU2563 7980 00e6 5E4B ldr r3, .L420+32 7981 00e8 1B78 ldrb r3, [r3] @ zero_extendqisi2 674:Src/main.c **** { 7982 .loc 2 674 8 view .LVU2564 7983 00ea 012B cmp r3, #1 7984 00ec 00F02A84 beq .L411 ARM GAS /tmp/ccqopZd5.s page 515 7985 .L356: 183:Src/main.c **** { 7986 .loc 2 183 3 is_stmt 1 view .LVU2565 185:Src/main.c **** { 7987 .loc 2 185 3 view .LVU2566 185:Src/main.c **** { 7988 .loc 2 185 8 is_stmt 0 view .LVU2567 7989 00f0 4FF48071 mov r1, #256 7990 00f4 5B48 ldr r0, .L420+36 7991 00f6 FFF7FEFF bl HAL_GPIO_ReadPin 7992 .LVL633: 185:Src/main.c **** { 7993 .loc 2 185 6 view .LVU2568 7994 00fa 0128 cmp r0, #1 7995 00fc B8D0 beq .L412 7996 .L357: 200:Src/main.c **** { 7997 .loc 2 200 4 is_stmt 1 view .LVU2569 7998 00fe 5A4B ldr r3, .L420+40 7999 0100 1B78 ldrb r3, [r3] @ zero_extendqisi2 8000 0102 092B cmp r3, #9 8001 0104 E4D8 bhi .L361 8002 0106 01A2 adr r2, .L363 8003 0108 52F823F0 ldr pc, [r2, r3, lsl #2] 8004 .p2align 2 8005 .L363: 8006 010c C1000000 .word .L372+1 8007 0110 35010000 .word .L371+1 8008 0114 9F010000 .word .L370+1 8009 0118 D5010000 .word .L369+1 8010 011c 05020000 .word .L368+1 8011 0120 15020000 .word .L367+1 8012 0124 31020000 .word .L366+1 8013 0128 99020000 .word .L365+1 8014 012c E9030000 .word .L364+1 8015 0130 2F040000 .word .L362+1 8016 .p2align 1 8017 .L371: 208:Src/main.c **** if (CheckChecksum(COMMAND)) 8018 .loc 2 208 6 view .LVU2570 208:Src/main.c **** if (CheckChecksum(COMMAND)) 8019 .loc 2 208 18 is_stmt 0 view .LVU2571 8020 0134 4D4C ldr r4, .L420+44 8021 0136 0D21 movs r1, #13 8022 0138 2046 mov r0, r4 8023 013a FFF7FEFF bl CalculateChecksum 8024 .LVL634: 208:Src/main.c **** if (CheckChecksum(COMMAND)) 8025 .loc 2 208 16 view .LVU2572 8026 013e 4C4B ldr r3, .L420+48 8027 0140 1880 strh r0, [r3] @ movhi 209:Src/main.c **** { 8028 .loc 2 209 6 is_stmt 1 view .LVU2573 209:Src/main.c **** { 8029 .loc 2 209 10 is_stmt 0 view .LVU2574 8030 0142 2046 mov r0, r4 8031 0144 FFF7FEFF bl CheckChecksum ARM GAS /tmp/ccqopZd5.s page 516 8032 .LVL635: 209:Src/main.c **** { 8033 .loc 2 209 9 view .LVU2575 8034 0148 70B9 cbnz r0, .L413 222:Src/main.c **** CPU_state = DEFAULT_ENABLE; 8035 .loc 2 222 7 is_stmt 1 view .LVU2576 222:Src/main.c **** CPU_state = DEFAULT_ENABLE; 8036 .loc 2 222 21 is_stmt 0 view .LVU2577 8037 014a 4A4A ldr r2, .L420+52 8038 014c 1378 ldrb r3, [r2] @ zero_extendqisi2 8039 014e 43F00403 orr r3, r3, #4 8040 0152 1370 strb r3, [r2] 223:Src/main.c **** CPU_state_old = HALT;//Save main current cycle 8041 .loc 2 223 7 is_stmt 1 view .LVU2578 223:Src/main.c **** CPU_state_old = HALT;//Save main current cycle 8042 .loc 2 223 17 is_stmt 0 view .LVU2579 8043 0154 444B ldr r3, .L420+40 8044 0156 0222 movs r2, #2 8045 0158 1A70 strb r2, [r3] 224:Src/main.c **** } 8046 .loc 2 224 7 is_stmt 1 view .LVU2580 224:Src/main.c **** } 8047 .loc 2 224 21 is_stmt 0 view .LVU2581 8048 015a 3E4B ldr r3, .L420+20 8049 015c 0022 movs r2, #0 8050 015e 1A70 strb r2, [r3] 8051 .L374: 226:Src/main.c **** break; 8052 .loc 2 226 6 is_stmt 1 view .LVU2582 226:Src/main.c **** break; 8053 .loc 2 226 32 is_stmt 0 view .LVU2583 8054 0160 3E4B ldr r3, .L420+28 8055 0162 0122 movs r2, #1 8056 0164 1A70 strb r2, [r3] 227:Src/main.c **** case DEFAULT_ENABLE://2 - Go to HALT 8057 .loc 2 227 5 is_stmt 1 view .LVU2584 8058 0166 B3E7 b .L361 8059 .L413: 211:Src/main.c **** LL_SPI_Enable(SPI6);//Enable SPI for Laser2 DAC & TEC2 8060 .loc 2 211 7 view .LVU2585 8061 .LVL636: 8062 .LBB563: 8063 .LBI563: 358:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 8064 .loc 4 358 22 view .LVU2586 8065 .LBB564: 360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 8066 .loc 4 360 3 view .LVU2587 8067 0168 434A ldr r2, .L420+56 8068 016a 1368 ldr r3, [r2] 8069 016c 43F04003 orr r3, r3, #64 8070 0170 1360 str r3, [r2] 8071 .LVL637: 360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 8072 .loc 4 360 3 is_stmt 0 view .LVU2588 8073 .LBE564: 8074 .LBE563: ARM GAS /tmp/ccqopZd5.s page 517 212:Src/main.c **** Decode_uart(COMMAND, &LD1_curr_setup, &LD2_curr_setup, &Curr_setup); 8075 .loc 2 212 7 is_stmt 1 view .LVU2589 8076 .LBB565: 8077 .LBI565: 358:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 8078 .loc 4 358 22 view .LVU2590 8079 .LBB566: 360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 8080 .loc 4 360 3 view .LVU2591 8081 0172 02F58E32 add r2, r2, #72704 8082 0176 1368 ldr r3, [r2] 8083 0178 43F04003 orr r3, r3, #64 8084 017c 1360 str r3, [r2] 8085 .LVL638: 360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 8086 .loc 4 360 3 is_stmt 0 view .LVU2592 8087 .LBE566: 8088 .LBE565: 213:Src/main.c **** TO6_before = TO6; 8089 .loc 2 213 7 is_stmt 1 view .LVU2593 8090 017e 3F4B ldr r3, .L420+60 8091 0180 3F4A ldr r2, .L420+64 8092 0182 4049 ldr r1, .L420+68 8093 0184 2046 mov r0, r4 8094 0186 FFF7FEFF bl Decode_uart 8095 .LVL639: 214:Src/main.c **** //LD1_param.LD_TEMP_Before = LD1_param.LD_TEMP; 8096 .loc 2 214 7 view .LVU2594 214:Src/main.c **** //LD1_param.LD_TEMP_Before = LD1_param.LD_TEMP; 8097 .loc 2 214 18 is_stmt 0 view .LVU2595 8098 018a 3F4B ldr r3, .L420+72 8099 018c 1A68 ldr r2, [r3] 8100 018e 3F4B ldr r3, .L420+76 8101 0190 1A60 str r2, [r3] 217:Src/main.c **** CPU_state_old = WORK_ENABLE;//Save main current cycle 8102 .loc 2 217 7 is_stmt 1 view .LVU2596 217:Src/main.c **** CPU_state_old = WORK_ENABLE;//Save main current cycle 8103 .loc 2 217 17 is_stmt 0 view .LVU2597 8104 0192 0723 movs r3, #7 8105 0194 344A ldr r2, .L420+40 8106 0196 1370 strb r3, [r2] 218:Src/main.c **** } 8107 .loc 2 218 7 is_stmt 1 view .LVU2598 218:Src/main.c **** } 8108 .loc 2 218 21 is_stmt 0 view .LVU2599 8109 0198 2E4A ldr r2, .L420+20 8110 019a 1370 strb r3, [r2] 8111 019c E0E7 b .L374 8112 .L370: 230:Src/main.c **** Stop_TIM10(); 8113 .loc 2 230 6 is_stmt 1 view .LVU2600 230:Src/main.c **** Stop_TIM10(); 8114 .loc 2 230 31 is_stmt 0 view .LVU2601 8115 019e 2E4B ldr r3, .L420+24 8116 01a0 5A68 ldr r2, [r3, #4] @ float 230:Src/main.c **** Stop_TIM10(); 8117 .loc 2 230 25 view .LVU2602 ARM GAS /tmp/ccqopZd5.s page 518 8118 01a2 1A61 str r2, [r3, #16] @ float 231:Src/main.c **** Init_params(); 8119 .loc 2 231 6 is_stmt 1 view .LVU2603 8120 01a4 FFF7FEFF bl Stop_TIM10 8121 .LVL640: 232:Src/main.c **** LL_SPI_Disable(SPI2);//Disable SPI for Laser1 DAC & TEC1 8122 .loc 2 232 6 view .LVU2604 8123 01a8 FFF7FEFF bl Init_params 8124 .LVL641: 233:Src/main.c **** LL_SPI_Disable(SPI6);//Disable SPI for Laser2 DAC & TEC2 8125 .loc 2 233 6 view .LVU2605 8126 .LBB567: 8127 .LBI567: 370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 8128 .loc 4 370 22 view .LVU2606 8129 .LBB568: 372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 8130 .loc 4 372 3 view .LVU2607 8131 01ac 324A ldr r2, .L420+56 8132 01ae 1368 ldr r3, [r2] 8133 01b0 23F04003 bic r3, r3, #64 8134 01b4 1360 str r3, [r2] 8135 .LVL642: 372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 8136 .loc 4 372 3 is_stmt 0 view .LVU2608 8137 .LBE568: 8138 .LBE567: 234:Src/main.c **** CPU_state = HALT; 8139 .loc 2 234 6 is_stmt 1 view .LVU2609 8140 .LBB569: 8141 .LBI569: 370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 8142 .loc 4 370 22 view .LVU2610 8143 .LBB570: 372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 8144 .loc 4 372 3 view .LVU2611 8145 01b6 02F58E32 add r2, r2, #72704 8146 01ba 1368 ldr r3, [r2] 8147 01bc 23F04003 bic r3, r3, #64 8148 01c0 1360 str r3, [r2] 8149 .LVL643: 372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 8150 .loc 4 372 3 is_stmt 0 view .LVU2612 8151 .LBE570: 8152 .LBE569: 235:Src/main.c **** CPU_state_old = HALT;//Save main current cycle 8153 .loc 2 235 6 is_stmt 1 view .LVU2613 235:Src/main.c **** CPU_state_old = HALT;//Save main current cycle 8154 .loc 2 235 16 is_stmt 0 view .LVU2614 8155 01c2 0023 movs r3, #0 8156 01c4 284A ldr r2, .L420+40 8157 01c6 1370 strb r3, [r2] 236:Src/main.c **** UART_transmission_request = MESS_01; 8158 .loc 2 236 6 is_stmt 1 view .LVU2615 236:Src/main.c **** UART_transmission_request = MESS_01; 8159 .loc 2 236 20 is_stmt 0 view .LVU2616 8160 01c8 224A ldr r2, .L420+20 ARM GAS /tmp/ccqopZd5.s page 519 8161 01ca 1370 strb r3, [r2] 237:Src/main.c **** break; 8162 .loc 2 237 6 is_stmt 1 view .LVU2617 237:Src/main.c **** break; 8163 .loc 2 237 32 is_stmt 0 view .LVU2618 8164 01cc 234B ldr r3, .L420+28 8165 01ce 0122 movs r2, #1 8166 01d0 1A70 strb r2, [r3] 238:Src/main.c **** case TRANS_S_ENABLE://3 - Transmith saved packet Before this operation must to be defaulting! 8167 .loc 2 238 5 is_stmt 1 view .LVU2619 8168 01d2 7DE7 b .L361 8169 .L369: 240:Src/main.c **** State_Data[0]|=temp16&0xff; 8170 .loc 2 240 6 view .LVU2620 240:Src/main.c **** State_Data[0]|=temp16&0xff; 8171 .loc 2 240 15 is_stmt 0 view .LVU2621 8172 01d4 2E48 ldr r0, .L420+80 8173 01d6 FFF7FEFF bl SD_READ 8174 .LVL644: 240:Src/main.c **** State_Data[0]|=temp16&0xff; 8175 .loc 2 240 13 view .LVU2622 8176 01da 80B2 uxth r0, r0 8177 01dc 2D4B ldr r3, .L420+84 8178 01de 1880 strh r0, [r3] @ movhi 241:Src/main.c **** if (temp16==0) 8179 .loc 2 241 6 is_stmt 1 view .LVU2623 241:Src/main.c **** if (temp16==0) 8180 .loc 2 241 19 is_stmt 0 view .LVU2624 8181 01e0 244A ldr r2, .L420+52 8182 01e2 1378 ldrb r3, [r2] @ zero_extendqisi2 8183 01e4 0343 orrs r3, r3, r0 8184 01e6 1370 strb r3, [r2] 242:Src/main.c **** { 8185 .loc 2 242 6 is_stmt 1 view .LVU2625 242:Src/main.c **** { 8186 .loc 2 242 9 is_stmt 0 view .LVU2626 8187 01e8 40B9 cbnz r0, .L375 244:Src/main.c **** } 8188 .loc 2 244 7 is_stmt 1 view .LVU2627 244:Src/main.c **** } 8189 .loc 2 244 33 is_stmt 0 view .LVU2628 8190 01ea 1C4B ldr r3, .L420+28 8191 01ec 0322 movs r2, #3 8192 01ee 1A70 strb r2, [r3] 8193 .L376: 250:Src/main.c **** CPU_state = CPU_state_old;//Return to main current cycle 8194 .loc 2 250 6 is_stmt 1 view .LVU2629 250:Src/main.c **** CPU_state = CPU_state_old;//Return to main current cycle 8195 .loc 2 250 20 is_stmt 0 view .LVU2630 8196 01f0 0023 movs r3, #0 8197 01f2 184A ldr r2, .L420+20 8198 01f4 1370 strb r3, [r2] 251:Src/main.c **** break; 8199 .loc 2 251 6 is_stmt 1 view .LVU2631 251:Src/main.c **** break; 8200 .loc 2 251 16 is_stmt 0 view .LVU2632 8201 01f6 1C4A ldr r2, .L420+40 ARM GAS /tmp/ccqopZd5.s page 520 8202 01f8 1370 strb r3, [r2] 252:Src/main.c **** case TRANS_ENABLE://4 - Transmith current packet 8203 .loc 2 252 5 is_stmt 1 view .LVU2633 8204 01fa 69E7 b .L361 8205 .L375: 248:Src/main.c **** } 8206 .loc 2 248 7 view .LVU2634 248:Src/main.c **** } 8207 .loc 2 248 33 is_stmt 0 view .LVU2635 8208 01fc 174B ldr r3, .L420+28 8209 01fe 0122 movs r2, #1 8210 0200 1A70 strb r2, [r3] 8211 0202 F5E7 b .L376 8212 .L368: 254:Src/main.c **** CPU_state = CPU_state_old;//Return to main current cycle 8213 .loc 2 254 6 is_stmt 1 view .LVU2636 254:Src/main.c **** CPU_state = CPU_state_old;//Return to main current cycle 8214 .loc 2 254 32 is_stmt 0 view .LVU2637 8215 0204 154B ldr r3, .L420+28 8216 0206 0222 movs r2, #2 8217 0208 1A70 strb r2, [r3] 255:Src/main.c **** break; 8218 .loc 2 255 6 is_stmt 1 view .LVU2638 255:Src/main.c **** break; 8219 .loc 2 255 16 is_stmt 0 view .LVU2639 8220 020a 124B ldr r3, .L420+20 8221 020c 1A78 ldrb r2, [r3] @ zero_extendqisi2 8222 020e 164B ldr r3, .L420+40 8223 0210 1A70 strb r2, [r3] 256:Src/main.c **** case REMOVE_FILE://5 - Remove file from SD 8224 .loc 2 256 5 is_stmt 1 view .LVU2640 8225 0212 5DE7 b .L361 8226 .L367: 258:Src/main.c **** UART_transmission_request = MESS_01; 8227 .loc 2 258 6 view .LVU2641 258:Src/main.c **** UART_transmission_request = MESS_01; 8228 .loc 2 258 21 is_stmt 0 view .LVU2642 8229 0214 FFF7FEFF bl SD_REMOVE 8230 .LVL645: 258:Src/main.c **** UART_transmission_request = MESS_01; 8231 .loc 2 258 19 view .LVU2643 8232 0218 164A ldr r2, .L420+52 8233 021a 1378 ldrb r3, [r2] @ zero_extendqisi2 8234 021c 0343 orrs r3, r3, r0 8235 021e 1370 strb r3, [r2] 259:Src/main.c **** CPU_state = CPU_state_old; 8236 .loc 2 259 6 is_stmt 1 view .LVU2644 259:Src/main.c **** CPU_state = CPU_state_old; 8237 .loc 2 259 32 is_stmt 0 view .LVU2645 8238 0220 0E4B ldr r3, .L420+28 8239 0222 0122 movs r2, #1 8240 0224 1A70 strb r2, [r3] 260:Src/main.c **** break; 8241 .loc 2 260 6 is_stmt 1 view .LVU2646 260:Src/main.c **** break; 8242 .loc 2 260 16 is_stmt 0 view .LVU2647 8243 0226 0B4B ldr r3, .L420+20 ARM GAS /tmp/ccqopZd5.s page 521 8244 0228 1A78 ldrb r2, [r3] @ zero_extendqisi2 8245 022a 0F4B ldr r3, .L420+40 8246 022c 1A70 strb r2, [r3] 261:Src/main.c **** case STATE://6 - Transmith state message 8247 .loc 2 261 5 is_stmt 1 view .LVU2648 8248 022e 4FE7 b .L361 8249 .L366: 263:Src/main.c **** CPU_state = CPU_state_old;//Return to main current cycle 8250 .loc 2 263 6 view .LVU2649 263:Src/main.c **** CPU_state = CPU_state_old;//Return to main current cycle 8251 .loc 2 263 32 is_stmt 0 view .LVU2650 8252 0230 0A4B ldr r3, .L420+28 8253 0232 0122 movs r2, #1 8254 0234 1A70 strb r2, [r3] 264:Src/main.c **** break; 8255 .loc 2 264 6 is_stmt 1 view .LVU2651 264:Src/main.c **** break; 8256 .loc 2 264 16 is_stmt 0 view .LVU2652 8257 0236 074B ldr r3, .L420+20 8258 0238 1A78 ldrb r2, [r3] @ zero_extendqisi2 8259 023a 0B4B ldr r3, .L420+40 8260 023c 1A70 strb r2, [r3] 265:Src/main.c **** case WORK_ENABLE://7 - Main work cycle 8261 .loc 2 265 5 is_stmt 1 view .LVU2653 8262 023e 47E7 b .L361 8263 .L421: 8264 .align 2 8265 .L420: 8266 0240 00000000 .word .LANCHOR37 8267 0244 00000000 .word .LANCHOR17 8268 0248 00100140 .word 1073811456 8269 024c 08100140 .word 1073811464 8270 0250 00E100E0 .word -536813312 8271 0254 00000000 .word .LANCHOR38 8272 0258 00000000 .word .LANCHOR1 8273 025c 00000000 .word .LANCHOR40 8274 0260 00000000 .word .LANCHOR12 8275 0264 00000240 .word 1073872896 8276 0268 00000000 .word .LANCHOR30 8277 026c 00000000 .word .LANCHOR29 8278 0270 00000000 .word .LANCHOR34 8279 0274 00000000 .word .LANCHOR39 8280 0278 00380040 .word 1073756160 8281 027c 00000000 .word .LANCHOR22 8282 0280 00000000 .word .LANCHOR24 8283 0284 00000000 .word .LANCHOR23 8284 0288 00000000 .word .LANCHOR8 8285 028c 00000000 .word .LANCHOR10 8286 0290 00000000 .word .LANCHOR18 8287 0294 00000000 .word .LANCHOR41 8288 .L365: 267:Src/main.c **** Stop_TIM10(); 8289 .loc 2 267 6 view .LVU2654 267:Src/main.c **** Stop_TIM10(); 8290 .loc 2 267 31 is_stmt 0 view .LVU2655 8291 0298 794B ldr r3, .L422 8292 029a 5A68 ldr r2, [r3, #4] @ float ARM GAS /tmp/ccqopZd5.s page 522 267:Src/main.c **** Stop_TIM10(); 8293 .loc 2 267 25 view .LVU2656 8294 029c 1A61 str r2, [r3, #16] @ float 268:Src/main.c **** if (TO7>TO7_before)//Main work cycle go with the timer 7 (1000 us or 1 kHz) 8295 .loc 2 268 6 is_stmt 1 view .LVU2657 8296 029e FFF7FEFF bl Stop_TIM10 8297 .LVL646: 269:Src/main.c **** { 8298 .loc 2 269 6 view .LVU2658 269:Src/main.c **** { 8299 .loc 2 269 13 is_stmt 0 view .LVU2659 8300 02a2 784B ldr r3, .L422+4 8301 02a4 1B68 ldr r3, [r3] 8302 02a6 784A ldr r2, .L422+8 8303 02a8 1268 ldr r2, [r2] 269:Src/main.c **** { 8304 .loc 2 269 9 view .LVU2660 8305 02aa 9342 cmp r3, r2 8306 02ac 7FF610AF bls .L361 271:Src/main.c **** LD1_param.POWER = MPhD_T(1);//Get Data from monitor photodiode of LD1 8307 .loc 2 271 7 is_stmt 1 view .LVU2661 271:Src/main.c **** LD1_param.POWER = MPhD_T(1);//Get Data from monitor photodiode of LD1 8308 .loc 2 271 18 is_stmt 0 view .LVU2662 8309 02b0 754A ldr r2, .L422+8 8310 02b2 1360 str r3, [r2] 272:Src/main.c **** LD1_param.POWER = MPhD_T(1);//Get Data from monitor photodiode of LD1 8311 .loc 2 272 7 is_stmt 1 view .LVU2663 272:Src/main.c **** LD1_param.POWER = MPhD_T(1);//Get Data from monitor photodiode of LD1 8312 .loc 2 272 25 is_stmt 0 view .LVU2664 8313 02b4 0120 movs r0, #1 8314 02b6 FFF7FEFF bl MPhD_T 8315 .LVL647: 272:Src/main.c **** LD1_param.POWER = MPhD_T(1);//Get Data from monitor photodiode of LD1 8316 .loc 2 272 23 view .LVU2665 8317 02ba 744F ldr r7, .L422+12 8318 02bc 3881 strh r0, [r7, #8] @ movhi 273:Src/main.c **** LD2_param.POWER = MPhD_T(2);//Get Data from monitor photodiode of LD2 8319 .loc 2 273 7 is_stmt 1 view .LVU2666 273:Src/main.c **** LD2_param.POWER = MPhD_T(2);//Get Data from monitor photodiode of LD2 8320 .loc 2 273 25 is_stmt 0 view .LVU2667 8321 02be 0120 movs r0, #1 8322 02c0 FFF7FEFF bl MPhD_T 8323 .LVL648: 273:Src/main.c **** LD2_param.POWER = MPhD_T(2);//Get Data from monitor photodiode of LD2 8324 .loc 2 273 23 view .LVU2668 8325 02c4 3881 strh r0, [r7, #8] @ movhi 274:Src/main.c **** LD2_param.POWER = MPhD_T(2);//Get Data from monitor photodiode of LD2 8326 .loc 2 274 7 is_stmt 1 view .LVU2669 274:Src/main.c **** LD2_param.POWER = MPhD_T(2);//Get Data from monitor photodiode of LD2 8327 .loc 2 274 25 is_stmt 0 view .LVU2670 8328 02c6 0220 movs r0, #2 8329 02c8 FFF7FEFF bl MPhD_T 8330 .LVL649: 274:Src/main.c **** LD2_param.POWER = MPhD_T(2);//Get Data from monitor photodiode of LD2 8331 .loc 2 274 23 view .LVU2671 8332 02cc 704E ldr r6, .L422+16 8333 02ce 3081 strh r0, [r6, #8] @ movhi ARM GAS /tmp/ccqopZd5.s page 523 275:Src/main.c **** 8334 .loc 2 275 7 is_stmt 1 view .LVU2672 275:Src/main.c **** 8335 .loc 2 275 25 is_stmt 0 view .LVU2673 8336 02d0 0220 movs r0, #2 8337 02d2 FFF7FEFF bl MPhD_T 8338 .LVL650: 275:Src/main.c **** 8339 .loc 2 275 23 view .LVU2674 8340 02d6 3081 strh r0, [r6, #8] @ movhi 278:Src/main.c **** LD1_param.LD_CURR_TEMP = MPhD_T(3); 8341 .loc 2 278 7 is_stmt 1 view .LVU2675 278:Src/main.c **** LD1_param.LD_CURR_TEMP = MPhD_T(3); 8342 .loc 2 278 14 is_stmt 0 view .LVU2676 8343 02d8 0320 movs r0, #3 8344 02da FFF7FEFF bl MPhD_T 8345 .LVL651: 279:Src/main.c **** (void) MPhD_T(4); 8346 .loc 2 279 7 is_stmt 1 view .LVU2677 279:Src/main.c **** (void) MPhD_T(4); 8347 .loc 2 279 32 is_stmt 0 view .LVU2678 8348 02de 0320 movs r0, #3 8349 02e0 FFF7FEFF bl MPhD_T 8350 .LVL652: 279:Src/main.c **** (void) MPhD_T(4); 8351 .loc 2 279 30 view .LVU2679 8352 02e4 3880 strh r0, [r7] @ movhi 280:Src/main.c **** LD2_param.LD_CURR_TEMP = MPhD_T(4); 8353 .loc 2 280 7 is_stmt 1 view .LVU2680 280:Src/main.c **** LD2_param.LD_CURR_TEMP = MPhD_T(4); 8354 .loc 2 280 14 is_stmt 0 view .LVU2681 8355 02e6 0420 movs r0, #4 8356 02e8 FFF7FEFF bl MPhD_T 8357 .LVL653: 281:Src/main.c **** temp16=PID_Controller_Temp(&LD1_curr_setup, &LD1_param, 1); 8358 .loc 2 281 7 is_stmt 1 view .LVU2682 281:Src/main.c **** temp16=PID_Controller_Temp(&LD1_curr_setup, &LD1_param, 1); 8359 .loc 2 281 32 is_stmt 0 view .LVU2683 8360 02ec 0420 movs r0, #4 8361 02ee FFF7FEFF bl MPhD_T 8362 .LVL654: 281:Src/main.c **** temp16=PID_Controller_Temp(&LD1_curr_setup, &LD1_param, 1); 8363 .loc 2 281 30 view .LVU2684 8364 02f2 3080 strh r0, [r6] @ movhi 282:Src/main.c **** Set_LTEC(3, temp16);//Drive Laser TEC 1 8365 .loc 2 282 7 is_stmt 1 view .LVU2685 282:Src/main.c **** Set_LTEC(3, temp16);//Drive Laser TEC 1 8366 .loc 2 282 14 is_stmt 0 view .LVU2686 8367 02f4 DFF8CC81 ldr r8, .L422+68 8368 02f8 0122 movs r2, #1 8369 02fa 3946 mov r1, r7 8370 02fc 4046 mov r0, r8 8371 02fe FFF7FEFF bl PID_Controller_Temp 8372 .LVL655: 8373 0302 0146 mov r1, r0 282:Src/main.c **** Set_LTEC(3, temp16);//Drive Laser TEC 1 8374 .loc 2 282 13 view .LVU2687 ARM GAS /tmp/ccqopZd5.s page 524 8375 0304 634D ldr r5, .L422+20 8376 0306 2880 strh r0, [r5] @ movhi 283:Src/main.c **** temp16=PID_Controller_Temp(&LD2_curr_setup, &LD2_param, 2); 8377 .loc 2 283 7 is_stmt 1 view .LVU2688 8378 0308 0320 movs r0, #3 8379 030a FFF7FEFF bl Set_LTEC 8380 .LVL656: 284:Src/main.c **** Set_LTEC(4, temp16);//Drive Laser TEC 2 8381 .loc 2 284 7 view .LVU2689 284:Src/main.c **** Set_LTEC(4, temp16);//Drive Laser TEC 2 8382 .loc 2 284 14 is_stmt 0 view .LVU2690 8383 030e DFF8B091 ldr r9, .L422+64 8384 0312 0222 movs r2, #2 8385 0314 3146 mov r1, r6 8386 0316 4846 mov r0, r9 8387 0318 FFF7FEFF bl PID_Controller_Temp 8388 .LVL657: 8389 031c 0146 mov r1, r0 284:Src/main.c **** Set_LTEC(4, temp16);//Drive Laser TEC 2 8390 .loc 2 284 13 view .LVU2691 8391 031e 2880 strh r0, [r5] @ movhi 285:Src/main.c **** 8392 .loc 2 285 7 is_stmt 1 view .LVU2692 8393 0320 0420 movs r0, #4 8394 0322 FFF7FEFF bl Set_LTEC 8395 .LVL658: 287:Src/main.c **** Long_Data[2] = LD2_param.POWER;//Translate Data from monitor photodiode of LD2 to Long_Data 8396 .loc 2 287 7 view .LVU2693 287:Src/main.c **** Long_Data[2] = LD2_param.POWER;//Translate Data from monitor photodiode of LD2 to Long_Data 8397 .loc 2 287 31 is_stmt 0 view .LVU2694 8398 0326 3B89 ldrh r3, [r7, #8] 287:Src/main.c **** Long_Data[2] = LD2_param.POWER;//Translate Data from monitor photodiode of LD2 to Long_Data 8399 .loc 2 287 20 view .LVU2695 8400 0328 5B4C ldr r4, .L422+24 8401 032a 6380 strh r3, [r4, #2] @ movhi 288:Src/main.c **** 8402 .loc 2 288 7 is_stmt 1 view .LVU2696 288:Src/main.c **** 8403 .loc 2 288 31 is_stmt 0 view .LVU2697 8404 032c 3389 ldrh r3, [r6, #8] 288:Src/main.c **** 8405 .loc 2 288 20 view .LVU2698 8406 032e A380 strh r3, [r4, #4] @ movhi 290:Src/main.c **** Set_LTEC(2,LD2_curr_setup.CURRENT);//Drive Laser diode 2 8407 .loc 2 290 7 is_stmt 1 view .LVU2699 8408 0330 B8F80C10 ldrh r1, [r8, #12] 8409 0334 0120 movs r0, #1 8410 0336 FFF7FEFF bl Set_LTEC 8411 .LVL659: 291:Src/main.c **** 8412 .loc 2 291 7 view .LVU2700 8413 033a B9F80C10 ldrh r1, [r9, #12] 8414 033e 0220 movs r0, #2 8415 0340 FFF7FEFF bl Set_LTEC 8416 .LVL660: 295:Src/main.c **** temp16 = Get_ADC(1); 8417 .loc 2 295 7 view .LVU2701 ARM GAS /tmp/ccqopZd5.s page 525 295:Src/main.c **** temp16 = Get_ADC(1); 8418 .loc 2 295 16 is_stmt 0 view .LVU2702 8419 0344 0020 movs r0, #0 8420 0346 FFF7FEFF bl Get_ADC 8421 .LVL661: 295:Src/main.c **** temp16 = Get_ADC(1); 8422 .loc 2 295 14 view .LVU2703 8423 034a 2880 strh r0, [r5] @ movhi 296:Src/main.c **** Long_Data[7] = temp16; // PA2 -- 3V_monitor // PB1 -- U_Rt1_ext_Gain 8424 .loc 2 296 7 is_stmt 1 view .LVU2704 296:Src/main.c **** Long_Data[7] = temp16; // PA2 -- 3V_monitor // PB1 -- U_Rt1_ext_Gain 8425 .loc 2 296 16 is_stmt 0 view .LVU2705 8426 034c 0120 movs r0, #1 8427 034e FFF7FEFF bl Get_ADC 8428 .LVL662: 296:Src/main.c **** Long_Data[7] = temp16; // PA2 -- 3V_monitor // PB1 -- U_Rt1_ext_Gain 8429 .loc 2 296 14 view .LVU2706 8430 0352 2880 strh r0, [r5] @ movhi 297:Src/main.c **** 8431 .loc 2 297 7 is_stmt 1 view .LVU2707 297:Src/main.c **** 8432 .loc 2 297 20 is_stmt 0 view .LVU2708 8433 0354 E081 strh r0, [r4, #14] @ movhi 300:Src/main.c **** Long_Data[8] = temp16; // PB0 -- U_Rt2_ext_Gain // PB0 -- U_Rt2_ext_Gain 8434 .loc 2 300 7 is_stmt 1 view .LVU2709 300:Src/main.c **** Long_Data[8] = temp16; // PB0 -- U_Rt2_ext_Gain // PB0 -- U_Rt2_ext_Gain 8435 .loc 2 300 16 is_stmt 0 view .LVU2710 8436 0356 0120 movs r0, #1 8437 0358 FFF7FEFF bl Get_ADC 8438 .LVL663: 300:Src/main.c **** Long_Data[8] = temp16; // PB0 -- U_Rt2_ext_Gain // PB0 -- U_Rt2_ext_Gain 8439 .loc 2 300 14 view .LVU2711 8440 035c 2880 strh r0, [r5] @ movhi 301:Src/main.c **** 8441 .loc 2 301 7 is_stmt 1 view .LVU2712 301:Src/main.c **** 8442 .loc 2 301 20 is_stmt 0 view .LVU2713 8443 035e 2082 strh r0, [r4, #16] @ movhi 304:Src/main.c **** Long_Data[9] = temp16; // PB1 -- U_Rt1_ext_Gain // PA2 -- 3V_monitor 8444 .loc 2 304 7 is_stmt 1 view .LVU2714 304:Src/main.c **** Long_Data[9] = temp16; // PB1 -- U_Rt1_ext_Gain // PA2 -- 3V_monitor 8445 .loc 2 304 16 is_stmt 0 view .LVU2715 8446 0360 0120 movs r0, #1 8447 0362 FFF7FEFF bl Get_ADC 8448 .LVL664: 304:Src/main.c **** Long_Data[9] = temp16; // PB1 -- U_Rt1_ext_Gain // PA2 -- 3V_monitor 8449 .loc 2 304 14 view .LVU2716 8450 0366 2880 strh r0, [r5] @ movhi 305:Src/main.c **** 8451 .loc 2 305 7 is_stmt 1 view .LVU2717 305:Src/main.c **** 8452 .loc 2 305 20 is_stmt 0 view .LVU2718 8453 0368 6082 strh r0, [r4, #18] @ movhi 308:Src/main.c **** Long_Data[10] = temp16; // PC0 -- 5V1_monitor // PC0 -- 5V1_monitor 8454 .loc 2 308 7 is_stmt 1 view .LVU2719 308:Src/main.c **** Long_Data[10] = temp16; // PC0 -- 5V1_monitor // PC0 -- 5V1_monitor 8455 .loc 2 308 16 is_stmt 0 view .LVU2720 ARM GAS /tmp/ccqopZd5.s page 526 8456 036a 0120 movs r0, #1 8457 036c FFF7FEFF bl Get_ADC 8458 .LVL665: 308:Src/main.c **** Long_Data[10] = temp16; // PC0 -- 5V1_monitor // PC0 -- 5V1_monitor 8459 .loc 2 308 14 view .LVU2721 8460 0370 2880 strh r0, [r5] @ movhi 309:Src/main.c **** 8461 .loc 2 309 7 is_stmt 1 view .LVU2722 309:Src/main.c **** 8462 .loc 2 309 21 is_stmt 0 view .LVU2723 8463 0372 A082 strh r0, [r4, #20] @ movhi 312:Src/main.c **** Long_Data[11] = temp16; // PC1 -- 5V2_monitor // PC1 -- 5V2_monitor 8464 .loc 2 312 7 is_stmt 1 view .LVU2724 312:Src/main.c **** Long_Data[11] = temp16; // PC1 -- 5V2_monitor // PC1 -- 5V2_monitor 8465 .loc 2 312 16 is_stmt 0 view .LVU2725 8466 0374 0120 movs r0, #1 8467 0376 FFF7FEFF bl Get_ADC 8468 .LVL666: 312:Src/main.c **** Long_Data[11] = temp16; // PC1 -- 5V2_monitor // PC1 -- 5V2_monitor 8469 .loc 2 312 14 view .LVU2726 8470 037a 2880 strh r0, [r5] @ movhi 313:Src/main.c **** temp16 = Get_ADC(2); 8471 .loc 2 313 7 is_stmt 1 view .LVU2727 313:Src/main.c **** temp16 = Get_ADC(2); 8472 .loc 2 313 21 is_stmt 0 view .LVU2728 8473 037c E082 strh r0, [r4, #22] @ movhi 314:Src/main.c **** 8474 .loc 2 314 7 is_stmt 1 view .LVU2729 314:Src/main.c **** 8475 .loc 2 314 16 is_stmt 0 view .LVU2730 8476 037e 0220 movs r0, #2 8477 0380 FFF7FEFF bl Get_ADC 8478 .LVL667: 314:Src/main.c **** 8479 .loc 2 314 14 view .LVU2731 8480 0384 2880 strh r0, [r5] @ movhi 317:Src/main.c **** temp16 = Get_ADC(4); 8481 .loc 2 317 7 is_stmt 1 view .LVU2732 317:Src/main.c **** temp16 = Get_ADC(4); 8482 .loc 2 317 16 is_stmt 0 view .LVU2733 8483 0386 0320 movs r0, #3 8484 0388 FFF7FEFF bl Get_ADC 8485 .LVL668: 317:Src/main.c **** temp16 = Get_ADC(4); 8486 .loc 2 317 14 view .LVU2734 8487 038c 2880 strh r0, [r5] @ movhi 318:Src/main.c **** Long_Data[12] = temp16; 8488 .loc 2 318 7 is_stmt 1 view .LVU2735 318:Src/main.c **** Long_Data[12] = temp16; 8489 .loc 2 318 16 is_stmt 0 view .LVU2736 8490 038e 0420 movs r0, #4 8491 0390 FFF7FEFF bl Get_ADC 8492 .LVL669: 318:Src/main.c **** Long_Data[12] = temp16; 8493 .loc 2 318 14 view .LVU2737 8494 0394 2880 strh r0, [r5] @ movhi 319:Src/main.c **** temp16 = Get_ADC(5); ARM GAS /tmp/ccqopZd5.s page 527 8495 .loc 2 319 7 is_stmt 1 view .LVU2738 319:Src/main.c **** temp16 = Get_ADC(5); 8496 .loc 2 319 21 is_stmt 0 view .LVU2739 8497 0396 2083 strh r0, [r4, #24] @ movhi 320:Src/main.c **** 8498 .loc 2 320 7 is_stmt 1 view .LVU2740 320:Src/main.c **** 8499 .loc 2 320 16 is_stmt 0 view .LVU2741 8500 0398 0520 movs r0, #5 8501 039a FFF7FEFF bl Get_ADC 8502 .LVL670: 320:Src/main.c **** 8503 .loc 2 320 14 view .LVU2742 8504 039e 2880 strh r0, [r5] @ movhi 323:Src/main.c **** Long_Data[3] = (TO6_stop)&0xffff; 8505 .loc 2 323 7 is_stmt 1 view .LVU2743 323:Src/main.c **** Long_Data[3] = (TO6_stop)&0xffff; 8506 .loc 2 323 16 is_stmt 0 view .LVU2744 8507 03a0 3E4B ldr r3, .L422+28 8508 03a2 1B68 ldr r3, [r3] 8509 03a4 3E4A ldr r2, .L422+32 8510 03a6 1360 str r3, [r2] 324:Src/main.c **** Long_Data[4] = (TO6_stop>>16)&0xffff; 8511 .loc 2 324 7 is_stmt 1 view .LVU2745 324:Src/main.c **** Long_Data[4] = (TO6_stop>>16)&0xffff; 8512 .loc 2 324 20 is_stmt 0 view .LVU2746 8513 03a8 E380 strh r3, [r4, #6] @ movhi 325:Src/main.c **** 8514 .loc 2 325 7 is_stmt 1 view .LVU2747 325:Src/main.c **** 8515 .loc 2 325 31 is_stmt 0 view .LVU2748 8516 03aa 1B0C lsrs r3, r3, #16 325:Src/main.c **** 8517 .loc 2 325 20 view .LVU2749 8518 03ac 2381 strh r3, [r4, #8] @ movhi 328:Src/main.c **** 8519 .loc 2 328 7 is_stmt 1 view .LVU2750 328:Src/main.c **** 8520 .loc 2 328 31 is_stmt 0 view .LVU2751 8521 03ae 3B88 ldrh r3, [r7] 328:Src/main.c **** 8522 .loc 2 328 20 view .LVU2752 8523 03b0 6381 strh r3, [r4, #10] @ movhi 331:Src/main.c **** 8524 .loc 2 331 7 is_stmt 1 view .LVU2753 331:Src/main.c **** 8525 .loc 2 331 31 is_stmt 0 view .LVU2754 8526 03b2 3388 ldrh r3, [r6] 331:Src/main.c **** 8527 .loc 2 331 20 view .LVU2755 8528 03b4 A381 strh r3, [r4, #12] @ movhi 333:Src/main.c **** { 8529 .loc 2 333 7 is_stmt 1 view .LVU2756 333:Src/main.c **** { 8530 .loc 2 333 21 is_stmt 0 view .LVU2757 8531 03b6 3B4B ldr r3, .L422+36 8532 03b8 DB7A ldrb r3, [r3, #11] @ zero_extendqisi2 ARM GAS /tmp/ccqopZd5.s page 528 333:Src/main.c **** { 8533 .loc 2 333 10 view .LVU2758 8534 03ba 012B cmp r3, #1 8535 03bc 03D0 beq .L414 8536 .L377: 340:Src/main.c **** } 8537 .loc 2 340 7 is_stmt 1 view .LVU2759 340:Src/main.c **** } 8538 .loc 2 340 21 is_stmt 0 view .LVU2760 8539 03be 3A4B ldr r3, .L422+40 8540 03c0 0722 movs r2, #7 8541 03c2 1A70 strb r2, [r3] 8542 03c4 84E6 b .L361 8543 .L414: 335:Src/main.c **** Long_Data[DL_16-1] = CS_result; 8544 .loc 2 335 8 is_stmt 1 view .LVU2761 335:Src/main.c **** Long_Data[DL_16-1] = CS_result; 8545 .loc 2 335 20 is_stmt 0 view .LVU2762 8546 03c6 0D21 movs r1, #13 8547 03c8 A01C adds r0, r4, #2 8548 03ca FFF7FEFF bl CalculateChecksum 8549 .LVL671: 335:Src/main.c **** Long_Data[DL_16-1] = CS_result; 8550 .loc 2 335 18 view .LVU2763 8551 03ce 374A ldr r2, .L422+44 8552 03d0 1080 strh r0, [r2] @ movhi 336:Src/main.c **** temp16 = SD_SAVE(&Long_Data[0]); 8553 .loc 2 336 8 is_stmt 1 view .LVU2764 336:Src/main.c **** temp16 = SD_SAVE(&Long_Data[0]); 8554 .loc 2 336 27 is_stmt 0 view .LVU2765 8555 03d2 A083 strh r0, [r4, #28] @ movhi 337:Src/main.c **** State_Data[0]|=temp16&0xff; 8556 .loc 2 337 8 is_stmt 1 view .LVU2766 337:Src/main.c **** State_Data[0]|=temp16&0xff; 8557 .loc 2 337 17 is_stmt 0 view .LVU2767 8558 03d4 2046 mov r0, r4 8559 03d6 FFF7FEFF bl SD_SAVE 8560 .LVL672: 337:Src/main.c **** State_Data[0]|=temp16&0xff; 8561 .loc 2 337 15 view .LVU2768 8562 03da 83B2 uxth r3, r0 8563 03dc 2B80 strh r3, [r5] @ movhi 338:Src/main.c **** } 8564 .loc 2 338 8 is_stmt 1 view .LVU2769 338:Src/main.c **** } 8565 .loc 2 338 21 is_stmt 0 view .LVU2770 8566 03de 3449 ldr r1, .L422+48 8567 03e0 0A78 ldrb r2, [r1] @ zero_extendqisi2 8568 03e2 1343 orrs r3, r3, r2 8569 03e4 0B70 strb r3, [r1] 8570 03e6 EAE7 b .L377 8571 .L364: 344:Src/main.c **** { 8572 .loc 2 344 6 is_stmt 1 view .LVU2771 344:Src/main.c **** { 8573 .loc 2 344 10 is_stmt 0 view .LVU2772 8574 03e8 3248 ldr r0, .L422+52 ARM GAS /tmp/ccqopZd5.s page 529 8575 03ea FFF7FEFF bl CheckChecksum 8576 .LVL673: 344:Src/main.c **** { 8577 .loc 2 344 9 view .LVU2773 8578 03ee 70B9 cbnz r0, .L415 353:Src/main.c **** CPU_state = DEFAULT_ENABLE; 8579 .loc 2 353 7 is_stmt 1 view .LVU2774 353:Src/main.c **** CPU_state = DEFAULT_ENABLE; 8580 .loc 2 353 21 is_stmt 0 view .LVU2775 8581 03f0 2F4A ldr r2, .L422+48 8582 03f2 1378 ldrb r3, [r2] @ zero_extendqisi2 8583 03f4 43F00403 orr r3, r3, #4 8584 03f8 1370 strb r3, [r2] 354:Src/main.c **** CPU_state_old = HALT;//Save main current cycle 8585 .loc 2 354 7 is_stmt 1 view .LVU2776 354:Src/main.c **** CPU_state_old = HALT;//Save main current cycle 8586 .loc 2 354 17 is_stmt 0 view .LVU2777 8587 03fa 2F4B ldr r3, .L422+56 8588 03fc 0222 movs r2, #2 8589 03fe 1A70 strb r2, [r3] 355:Src/main.c **** } 8590 .loc 2 355 7 is_stmt 1 view .LVU2778 355:Src/main.c **** } 8591 .loc 2 355 21 is_stmt 0 view .LVU2779 8592 0400 294B ldr r3, .L422+40 8593 0402 0022 movs r2, #0 8594 0404 1A70 strb r2, [r3] 8595 .L379: 357:Src/main.c **** break; 8596 .loc 2 357 6 is_stmt 1 view .LVU2780 357:Src/main.c **** break; 8597 .loc 2 357 32 is_stmt 0 view .LVU2781 8598 0406 2D4B ldr r3, .L422+60 8599 0408 0122 movs r2, #1 8600 040a 1A70 strb r2, [r3] 358:Src/main.c **** case RUN_TASK: 8601 .loc 2 358 5 is_stmt 1 view .LVU2782 8602 040c 60E6 b .L361 8603 .L415: 346:Src/main.c **** TO6_before = TO6; 8604 .loc 2 346 7 view .LVU2783 8605 040e 254B ldr r3, .L422+36 8606 0410 2B4A ldr r2, .L422+64 8607 0412 2C49 ldr r1, .L422+68 8608 0414 2748 ldr r0, .L422+52 8609 0416 FFF7FEFF bl Decode_task 8610 .LVL674: 347:Src/main.c **** CPU_state = RUN_TASK; 8611 .loc 2 347 7 view .LVU2784 347:Src/main.c **** CPU_state = RUN_TASK; 8612 .loc 2 347 18 is_stmt 0 view .LVU2785 8613 041a 204B ldr r3, .L422+28 8614 041c 1A68 ldr r2, [r3] 8615 041e 2A4B ldr r3, .L422+72 8616 0420 1A60 str r2, [r3] 348:Src/main.c **** CPU_state_old = RUN_TASK;//Save main current cycle 8617 .loc 2 348 7 is_stmt 1 view .LVU2786 ARM GAS /tmp/ccqopZd5.s page 530 348:Src/main.c **** CPU_state_old = RUN_TASK;//Save main current cycle 8618 .loc 2 348 17 is_stmt 0 view .LVU2787 8619 0422 0923 movs r3, #9 8620 0424 244A ldr r2, .L422+56 8621 0426 1370 strb r3, [r2] 349:Src/main.c **** } 8622 .loc 2 349 7 is_stmt 1 view .LVU2788 349:Src/main.c **** } 8623 .loc 2 349 21 is_stmt 0 view .LVU2789 8624 0428 1F4A ldr r2, .L422+40 8625 042a 1370 strb r3, [r2] 8626 042c EBE7 b .L379 8627 .L362: 360:Src/main.c **** { 8628 .loc 2 360 6 is_stmt 1 view .LVU2790 360:Src/main.c **** { 8629 .loc 2 360 18 is_stmt 0 view .LVU2791 8630 042e 144B ldr r3, .L422 8631 0430 1B78 ldrb r3, [r3] @ zero_extendqisi2 8632 0432 012B cmp r3, #1 8633 0434 54D0 beq .L380 8634 0436 022B cmp r3, #2 8635 0438 00F01881 beq .L381 8636 .L382: 566:Src/main.c **** { 8637 .loc 2 566 6 is_stmt 1 view .LVU2792 566:Src/main.c **** { 8638 .loc 2 566 13 is_stmt 0 view .LVU2793 8639 043c 114B ldr r3, .L422+4 8640 043e 1B68 ldr r3, [r3] 8641 0440 114A ldr r2, .L422+8 8642 0442 1268 ldr r2, [r2] 566:Src/main.c **** { 8643 .loc 2 566 9 view .LVU2794 8644 0444 9342 cmp r3, r2 8645 0446 00F2E781 bhi .L416 8646 .L399: 618:Src/main.c **** 8647 .loc 2 618 27 is_stmt 1 discriminator 1 view .LVU2795 618:Src/main.c **** 8648 .loc 2 618 12 discriminator 1 view .LVU2796 618:Src/main.c **** 8649 .loc 2 618 13 is_stmt 0 discriminator 1 view .LVU2797 8650 044a 204B ldr r3, .L422+76 8651 044c 1B78 ldrb r3, [r3] @ zero_extendqisi2 618:Src/main.c **** 8652 .loc 2 618 12 discriminator 1 view .LVU2798 8653 044e 002B cmp r3, #0 8654 0450 FBD0 beq .L399 620:Src/main.c **** 8655 .loc 2 620 6 is_stmt 1 view .LVU2799 8656 0452 FFF7FEFF bl Stop_TIM10 8657 .LVL675: 622:Src/main.c **** { 8658 .loc 2 622 6 view .LVU2800 622:Src/main.c **** { 8659 .loc 2 622 14 is_stmt 0 view .LVU2801 ARM GAS /tmp/ccqopZd5.s page 531 8660 0456 0A4B ldr r3, .L422 8661 0458 DB8A ldrh r3, [r3, #22] 622:Src/main.c **** { 8662 .loc 2 622 9 view .LVU2802 8663 045a 032B cmp r3, #3 8664 045c 0BD9 bls .L400 624:Src/main.c **** TO10_counter = task.dt / 10; 8665 .loc 2 624 7 is_stmt 1 view .LVU2803 624:Src/main.c **** TO10_counter = task.dt / 10; 8666 .loc 2 624 26 is_stmt 0 view .LVU2804 8667 045e 1C4B ldr r3, .L422+80 8668 0460 1A68 ldr r2, [r3] 8669 0462 1C4B ldr r3, .L422+84 8670 0464 DA60 str r2, [r3, #12] 625:Src/main.c **** } 8671 .loc 2 625 7 is_stmt 1 view .LVU2805 625:Src/main.c **** } 8672 .loc 2 625 26 is_stmt 0 view .LVU2806 8673 0466 064B ldr r3, .L422 8674 0468 1B7D ldrb r3, [r3, #20] @ zero_extendqisi2 625:Src/main.c **** } 8675 .loc 2 625 30 view .LVU2807 8676 046a 1B4A ldr r2, .L422+88 8677 046c A2FB0323 umull r2, r3, r2, r3 8678 0470 DB08 lsrs r3, r3, #3 625:Src/main.c **** } 8679 .loc 2 625 20 view .LVU2808 8680 0472 1A4A ldr r2, .L422+92 8681 0474 1360 str r3, [r2] 8682 .L400: 628:Src/main.c **** break; 8683 .loc 2 628 6 is_stmt 1 view .LVU2809 628:Src/main.c **** break; 8684 .loc 2 628 20 is_stmt 0 view .LVU2810 8685 0476 0C4B ldr r3, .L422+40 8686 0478 0922 movs r2, #9 8687 047a 1A70 strb r2, [r3] 629:Src/main.c **** } 8688 .loc 2 629 9 is_stmt 1 view .LVU2811 8689 047c 28E6 b .L361 8690 .L423: 8691 047e 00BF .align 2 8692 .L422: 8693 0480 00000000 .word .LANCHOR1 8694 0484 00000000 .word .LANCHOR3 8695 0488 00000000 .word .LANCHOR9 8696 048c 00000000 .word .LANCHOR42 8697 0490 00000000 .word .LANCHOR43 8698 0494 00000000 .word .LANCHOR41 8699 0498 00000000 .word .LANCHOR18 8700 049c 00000000 .word .LANCHOR8 8701 04a0 00000000 .word .LANCHOR44 8702 04a4 00000000 .word .LANCHOR22 8703 04a8 00000000 .word .LANCHOR38 8704 04ac 00000000 .word .LANCHOR34 8705 04b0 00000000 .word .LANCHOR39 8706 04b4 00000000 .word .LANCHOR29 ARM GAS /tmp/ccqopZd5.s page 532 8707 04b8 00000000 .word .LANCHOR30 8708 04bc 00000000 .word .LANCHOR40 8709 04c0 00000000 .word .LANCHOR24 8710 04c4 00000000 .word .LANCHOR23 8711 04c8 00000000 .word .LANCHOR10 8712 04cc 00000000 .word .LANCHOR6 8713 04d0 00000000 .word .LANCHOR45 8714 04d4 00000000 .word .LANCHOR5 8715 04d8 CDCCCCCC .word -858993459 8716 04dc 00000000 .word .LANCHOR2 8717 .L380: 8718 .LBB571: 363:Src/main.c **** (void) MPhD_T(TT_CHANGE_TEMP_1); 8719 .loc 2 363 7 view .LVU2812 363:Src/main.c **** (void) MPhD_T(TT_CHANGE_TEMP_1); 8720 .loc 2 363 38 is_stmt 0 view .LVU2813 8721 04e0 BA4B ldr r3, .L424 8722 04e2 D3ED077A vldr.32 s15, [r3, #28] 363:Src/main.c **** (void) MPhD_T(TT_CHANGE_TEMP_1); 8723 .loc 2 363 7 view .LVU2814 8724 04e6 FCEEE77A vcvt.u32.f32 s15, s15 8725 04ea 17EE903A vmov r3, s15 @ int 8726 04ee 99B2 uxth r1, r3 8727 04f0 0220 movs r0, #2 8728 04f2 FFF7FEFF bl Set_LTEC 8729 .LVL676: 364:Src/main.c **** LD1_param.LD_CURR_TEMP = MPhD_T(TT_CHANGE_TEMP_1); 8730 .loc 2 364 7 is_stmt 1 view .LVU2815 364:Src/main.c **** LD1_param.LD_CURR_TEMP = MPhD_T(TT_CHANGE_TEMP_1); 8731 .loc 2 364 14 is_stmt 0 view .LVU2816 8732 04f6 0320 movs r0, #3 8733 04f8 FFF7FEFF bl MPhD_T 8734 .LVL677: 365:Src/main.c **** (void) MPhD_T(TT_CHANGE_TEMP_2); 8735 .loc 2 365 7 is_stmt 1 view .LVU2817 365:Src/main.c **** (void) MPhD_T(TT_CHANGE_TEMP_2); 8736 .loc 2 365 32 is_stmt 0 view .LVU2818 8737 04fc 0320 movs r0, #3 8738 04fe FFF7FEFF bl MPhD_T 8739 .LVL678: 365:Src/main.c **** (void) MPhD_T(TT_CHANGE_TEMP_2); 8740 .loc 2 365 30 view .LVU2819 8741 0502 B34C ldr r4, .L424+4 8742 0504 2080 strh r0, [r4] @ movhi 366:Src/main.c **** LD2_param.LD_CURR_TEMP = MPhD_T(TT_CHANGE_TEMP_2); 8743 .loc 2 366 7 is_stmt 1 view .LVU2820 366:Src/main.c **** LD2_param.LD_CURR_TEMP = MPhD_T(TT_CHANGE_TEMP_2); 8744 .loc 2 366 14 is_stmt 0 view .LVU2821 8745 0506 0420 movs r0, #4 8746 0508 FFF7FEFF bl MPhD_T 8747 .LVL679: 367:Src/main.c **** temp16=PID_Controller_Temp(&LD1_curr_setup, &LD1_param, 1); 8748 .loc 2 367 7 is_stmt 1 view .LVU2822 367:Src/main.c **** temp16=PID_Controller_Temp(&LD1_curr_setup, &LD1_param, 1); 8749 .loc 2 367 32 is_stmt 0 view .LVU2823 8750 050c 0420 movs r0, #4 8751 050e FFF7FEFF bl MPhD_T ARM GAS /tmp/ccqopZd5.s page 533 8752 .LVL680: 367:Src/main.c **** temp16=PID_Controller_Temp(&LD1_curr_setup, &LD1_param, 1); 8753 .loc 2 367 30 view .LVU2824 8754 0512 B04D ldr r5, .L424+8 8755 0514 2880 strh r0, [r5] @ movhi 368:Src/main.c **** Set_LTEC(TT_CHANGE_TEMP_1, temp16);//Drive Laser TEC 1 8756 .loc 2 368 7 is_stmt 1 view .LVU2825 368:Src/main.c **** Set_LTEC(TT_CHANGE_TEMP_1, temp16);//Drive Laser TEC 1 8757 .loc 2 368 14 is_stmt 0 view .LVU2826 8758 0516 0122 movs r2, #1 8759 0518 2146 mov r1, r4 8760 051a AF48 ldr r0, .L424+12 8761 051c FFF7FEFF bl PID_Controller_Temp 8762 .LVL681: 8763 0520 0146 mov r1, r0 368:Src/main.c **** Set_LTEC(TT_CHANGE_TEMP_1, temp16);//Drive Laser TEC 1 8764 .loc 2 368 13 view .LVU2827 8765 0522 AE4C ldr r4, .L424+16 8766 0524 2080 strh r0, [r4] @ movhi 369:Src/main.c **** temp16=PID_Controller_Temp(&LD2_curr_setup, &LD2_param, 2); 8767 .loc 2 369 7 is_stmt 1 view .LVU2828 8768 0526 0320 movs r0, #3 8769 0528 FFF7FEFF bl Set_LTEC 8770 .LVL682: 370:Src/main.c **** Set_LTEC(TT_CHANGE_TEMP_2, temp16);//Drive Laser TEC 2 8771 .loc 2 370 7 view .LVU2829 370:Src/main.c **** Set_LTEC(TT_CHANGE_TEMP_2, temp16);//Drive Laser TEC 2 8772 .loc 2 370 14 is_stmt 0 view .LVU2830 8773 052c 0222 movs r2, #2 8774 052e 2946 mov r1, r5 8775 0530 AB48 ldr r0, .L424+20 8776 0532 FFF7FEFF bl PID_Controller_Temp 8777 .LVL683: 8778 0536 0146 mov r1, r0 370:Src/main.c **** Set_LTEC(TT_CHANGE_TEMP_2, temp16);//Drive Laser TEC 2 8779 .loc 2 370 13 view .LVU2831 8780 0538 2080 strh r0, [r4] @ movhi 371:Src/main.c **** 8781 .loc 2 371 7 is_stmt 1 view .LVU2832 8782 053a 0420 movs r0, #4 8783 053c FFF7FEFF bl Set_LTEC 8784 .LVL684: 374:Src/main.c **** HAL_GPIO_WritePin(GPIOD, GPIO_PIN_7, GPIO_PIN_RESET); 8785 .loc 2 374 7 view .LVU2833 8786 0540 A84C ldr r4, .L424+24 8787 0542 0122 movs r2, #1 8788 0544 8021 movs r1, #128 8789 0546 2046 mov r0, r4 8790 0548 FFF7FEFF bl HAL_GPIO_WritePin 8791 .LVL685: 375:Src/main.c **** 8792 .loc 2 375 7 view .LVU2834 8793 054c 0022 movs r2, #0 8794 054e 8021 movs r1, #128 8795 0550 2046 mov r0, r4 8796 0552 FFF7FEFF bl HAL_GPIO_WritePin 8797 .LVL686: ARM GAS /tmp/ccqopZd5.s page 534 377:Src/main.c **** if (st != HAL_OK) 8798 .loc 2 377 7 view .LVU2835 377:Src/main.c **** if (st != HAL_OK) 8799 .loc 2 377 12 is_stmt 0 view .LVU2836 8800 0556 A448 ldr r0, .L424+28 8801 0558 FFF7FEFF bl HAL_TIM_Base_Start_IT 8802 .LVL687: 378:Src/main.c **** while(1); 8803 .loc 2 378 7 is_stmt 1 view .LVU2837 378:Src/main.c **** while(1); 8804 .loc 2 378 10 is_stmt 0 view .LVU2838 8805 055c 0028 cmp r0, #0 8806 055e 57D1 bne .L384 381:Src/main.c **** uint16_t trigger_counter = 0; 8807 .loc 2 381 7 is_stmt 1 view .LVU2839 8808 .LVL688: 382:Src/main.c **** uint16_t trigger_step = (uint8_t )((task.max_param - task.current_param)/task.delta_param * 1 8809 .loc 2 382 7 view .LVU2840 383:Src/main.c **** uint16_t task_sheduler = 0; 8810 .loc 2 383 7 view .LVU2841 383:Src/main.c **** uint16_t task_sheduler = 0; 8811 .loc 2 383 47 is_stmt 0 view .LVU2842 8812 0560 9A4B ldr r3, .L424 8813 0562 93ED027A vldr.32 s14, [r3, #8] 383:Src/main.c **** uint16_t task_sheduler = 0; 8814 .loc 2 383 64 view .LVU2843 8815 0566 D3ED047A vldr.32 s15, [r3, #16] 383:Src/main.c **** uint16_t task_sheduler = 0; 8816 .loc 2 383 58 view .LVU2844 8817 056a 37EE677A vsub.f32 s14, s14, s15 383:Src/main.c **** uint16_t task_sheduler = 0; 8818 .loc 2 383 84 view .LVU2845 8819 056e D3ED036A vldr.32 s13, [r3, #12] 383:Src/main.c **** uint16_t task_sheduler = 0; 8820 .loc 2 383 79 view .LVU2846 8821 0572 C7EE267A vdiv.f32 s15, s14, s13 383:Src/main.c **** uint16_t task_sheduler = 0; 8822 .loc 2 383 97 view .LVU2847 8823 0576 B2EE047A vmov.f32 s14, #1.0e+1 8824 057a 67EE877A vmul.f32 s15, s15, s14 383:Src/main.c **** uint16_t task_sheduler = 0; 8825 .loc 2 383 31 view .LVU2848 8826 057e FCEEE77A vcvt.u32.f32 s15, s15 8827 0582 CDED017A vstr.32 s15, [sp, #4] @ int 383:Src/main.c **** uint16_t task_sheduler = 0; 8828 .loc 2 383 16 view .LVU2849 8829 0586 9DF80450 ldrb r5, [sp, #4] @ zero_extendqisi2 8830 .LVL689: 384:Src/main.c **** HAL_TIM_PWM_Start(&htim11, TIM_CHANNEL_1); //start modulating by Mach-Zander modulator 8831 .loc 2 384 7 is_stmt 1 view .LVU2850 385:Src/main.c **** while (task.current_param < task.max_param) 8832 .loc 2 385 7 view .LVU2851 8833 058a 0021 movs r1, #0 8834 058c 9748 ldr r0, .L424+32 8835 .LVL690: 385:Src/main.c **** while (task.current_param < task.max_param) 8836 .loc 2 385 7 is_stmt 0 view .LVU2852 ARM GAS /tmp/ccqopZd5.s page 535 8837 058e FFF7FEFF bl HAL_TIM_PWM_Start 8838 .LVL691: 386:Src/main.c **** { 8839 .loc 2 386 7 is_stmt 1 view .LVU2853 382:Src/main.c **** uint16_t trigger_step = (uint8_t )((task.max_param - task.current_param)/task.delta_param * 1 8840 .loc 2 382 16 is_stmt 0 view .LVU2854 8841 0592 0026 movs r6, #0 381:Src/main.c **** uint16_t trigger_counter = 0; 8842 .loc 2 381 16 view .LVU2855 8843 0594 3446 mov r4, r6 8844 .LVL692: 8845 .L386: 386:Src/main.c **** { 8846 .loc 2 386 13 is_stmt 1 view .LVU2856 386:Src/main.c **** { 8847 .loc 2 386 18 is_stmt 0 view .LVU2857 8848 0596 8D4B ldr r3, .L424 8849 0598 D3ED047A vldr.32 s15, [r3, #16] 386:Src/main.c **** { 8850 .loc 2 386 39 view .LVU2858 8851 059c 93ED027A vldr.32 s14, [r3, #8] 386:Src/main.c **** { 8852 .loc 2 386 13 view .LVU2859 8853 05a0 F4EEC77A vcmpe.f32 s15, s14 8854 05a4 F1EE10FA vmrs APSR_nzcv, FPSCR 8855 05a8 39D5 bpl .L417 388:Src/main.c **** { 8856 .loc 2 388 8 is_stmt 1 view .LVU2860 388:Src/main.c **** { 8857 .loc 2 388 12 is_stmt 0 view .LVU2861 8858 05aa 914B ldr r3, .L424+36 8859 05ac 1B78 ldrb r3, [r3] @ zero_extendqisi2 388:Src/main.c **** { 8860 .loc 2 388 11 view .LVU2862 8861 05ae 002B cmp r3, #0 8862 05b0 F1D0 beq .L386 390:Src/main.c **** TIM11 -> CNT = 0; // to link modulator phase 8863 .loc 2 390 9 is_stmt 1 view .LVU2863 8864 05b2 FCEEE77A vcvt.u32.f32 s15, s15 8865 05b6 17EE903A vmov r3, s15 @ int 8866 05ba 99B2 uxth r1, r3 8867 05bc 0120 movs r0, #1 8868 05be FFF7FEFF bl Set_LTEC 8869 .LVL693: 391:Src/main.c **** task.current_param += task.delta_param; 8870 .loc 2 391 9 view .LVU2864 391:Src/main.c **** task.current_param += task.delta_param; 8871 .loc 2 391 22 is_stmt 0 view .LVU2865 8872 05c2 0027 movs r7, #0 8873 05c4 8B4B ldr r3, .L424+40 8874 05c6 5F62 str r7, [r3, #36] 392:Src/main.c **** TO10 = 0; 8875 .loc 2 392 9 is_stmt 1 view .LVU2866 392:Src/main.c **** TO10 = 0; 8876 .loc 2 392 35 is_stmt 0 view .LVU2867 8877 05c8 804B ldr r3, .L424 8878 05ca 93ED037A vldr.32 s14, [r3, #12] ARM GAS /tmp/ccqopZd5.s page 536 392:Src/main.c **** TO10 = 0; 8879 .loc 2 392 28 view .LVU2868 8880 05ce D3ED047A vldr.32 s15, [r3, #16] 8881 05d2 77EE877A vadd.f32 s15, s15, s14 8882 05d6 C3ED047A vstr.32 s15, [r3, #16] 393:Src/main.c **** TIM10_coflag = 0; 8883 .loc 2 393 9 is_stmt 1 view .LVU2869 393:Src/main.c **** TIM10_coflag = 0; 8884 .loc 2 393 14 is_stmt 0 view .LVU2870 8885 05da 874B ldr r3, .L424+44 8886 05dc 1F60 str r7, [r3] 394:Src/main.c **** 8887 .loc 2 394 9 is_stmt 1 view .LVU2871 394:Src/main.c **** 8888 .loc 2 394 22 is_stmt 0 view .LVU2872 8889 05de 844B ldr r3, .L424+36 8890 05e0 1F70 strb r7, [r3] 396:Src/main.c **** HAL_GPIO_WritePin(GPIOG, GPIO_PIN_9, GPIO_PIN_RESET); 8891 .loc 2 396 9 is_stmt 1 view .LVU2873 8892 05e2 DFF83082 ldr r8, .L424+72 8893 05e6 0122 movs r2, #1 8894 05e8 4FF40071 mov r1, #512 8895 05ec 4046 mov r0, r8 8896 05ee FFF7FEFF bl HAL_GPIO_WritePin 8897 .LVL694: 397:Src/main.c **** //* 8898 .loc 2 397 9 view .LVU2874 8899 05f2 3A46 mov r2, r7 8900 05f4 4FF40071 mov r1, #512 8901 05f8 4046 mov r0, r8 8902 05fa FFF7FEFF bl HAL_GPIO_WritePin 8903 .LVL695: 399:Src/main.c **** OUT_trigger(trigger_counter); 8904 .loc 2 399 9 view .LVU2875 399:Src/main.c **** OUT_trigger(trigger_counter); 8905 .loc 2 399 41 is_stmt 0 view .LVU2876 8906 05fe B4FBF5F3 udiv r3, r4, r5 8907 0602 05FB1343 mls r3, r5, r3, r4 8908 0606 9BB2 uxth r3, r3 399:Src/main.c **** OUT_trigger(trigger_counter); 8909 .loc 2 399 12 view .LVU2877 8910 0608 1BB1 cbz r3, .L418 8911 .L387: 403:Src/main.c **** //*/ 8912 .loc 2 403 9 is_stmt 1 view .LVU2878 8913 060a 0134 adds r4, r4, #1 8914 .LVL696: 403:Src/main.c **** //*/ 8915 .loc 2 403 9 is_stmt 0 view .LVU2879 8916 060c A4B2 uxth r4, r4 8917 .LVL697: 403:Src/main.c **** //*/ 8918 .loc 2 403 9 view .LVU2880 8919 060e C2E7 b .L386 8920 .LVL698: 8921 .L384: 379:Src/main.c **** ARM GAS /tmp/ccqopZd5.s page 537 8922 .loc 2 379 8 is_stmt 1 discriminator 1 view .LVU2881 379:Src/main.c **** 8923 .loc 2 379 16 discriminator 1 view .LVU2882 379:Src/main.c **** 8924 .loc 2 379 13 discriminator 1 view .LVU2883 8925 0610 FEE7 b .L384 8926 .LVL699: 8927 .L418: 400:Src/main.c **** ++trigger_counter; 8928 .loc 2 400 10 view .LVU2884 8929 0612 F0B2 uxtb r0, r6 8930 0614 FFF7FEFF bl OUT_trigger 8931 .LVL700: 401:Src/main.c **** } 8932 .loc 2 401 10 view .LVU2885 8933 0618 0136 adds r6, r6, #1 8934 .LVL701: 401:Src/main.c **** } 8935 .loc 2 401 10 is_stmt 0 view .LVU2886 8936 061a B6B2 uxth r6, r6 8937 .LVL702: 401:Src/main.c **** } 8938 .loc 2 401 10 view .LVU2887 8939 061c F5E7 b .L387 8940 .L417: 428:Src/main.c **** 8941 .loc 2 428 7 is_stmt 1 view .LVU2888 8942 061e 0021 movs r1, #0 8943 0620 7248 ldr r0, .L424+32 8944 0622 FFF7FEFF bl HAL_TIM_PWM_Stop 8945 .LVL703: 430:Src/main.c **** task.current_param = task.min_param; 8946 .loc 2 430 7 view .LVU2889 8947 0626 FFF7FEFF bl Stop_TIM10 8948 .LVL704: 431:Src/main.c **** Set_LTEC(TT_CHANGE_CURR_1, task.current_param); 8949 .loc 2 431 7 view .LVU2890 431:Src/main.c **** Set_LTEC(TT_CHANGE_CURR_1, task.current_param); 8950 .loc 2 431 32 is_stmt 0 view .LVU2891 8951 062a 684C ldr r4, .L424 8952 .LVL705: 431:Src/main.c **** Set_LTEC(TT_CHANGE_CURR_1, task.current_param); 8953 .loc 2 431 32 view .LVU2892 8954 062c D4ED017A vldr.32 s15, [r4, #4] 431:Src/main.c **** Set_LTEC(TT_CHANGE_CURR_1, task.current_param); 8955 .loc 2 431 26 view .LVU2893 8956 0630 C4ED047A vstr.32 s15, [r4, #16] 432:Src/main.c **** if (task.tau > 3) 8957 .loc 2 432 7 is_stmt 1 view .LVU2894 8958 0634 FCEEE77A vcvt.u32.f32 s15, s15 8959 0638 17EE903A vmov r3, s15 @ int 8960 063c 99B2 uxth r1, r3 8961 063e 0120 movs r0, #1 8962 0640 FFF7FEFF bl Set_LTEC 8963 .LVL706: 433:Src/main.c **** { 8964 .loc 2 433 7 view .LVU2895 ARM GAS /tmp/ccqopZd5.s page 538 433:Src/main.c **** { 8965 .loc 2 433 15 is_stmt 0 view .LVU2896 8966 0644 E38A ldrh r3, [r4, #22] 433:Src/main.c **** { 8967 .loc 2 433 10 view .LVU2897 8968 0646 032B cmp r3, #3 8969 0648 0CD9 bls .L389 435:Src/main.c **** htim10.Init.Period = 9999; 8970 .loc 2 435 8 is_stmt 1 view .LVU2898 435:Src/main.c **** htim10.Init.Period = 9999; 8971 .loc 2 435 34 is_stmt 0 view .LVU2899 8972 064a 674A ldr r2, .L424+28 8973 064c D068 ldr r0, [r2, #12] 435:Src/main.c **** htim10.Init.Period = 9999; 8974 .loc 2 435 21 view .LVU2900 8975 064e 6B49 ldr r1, .L424+48 8976 0650 0860 str r0, [r1] 436:Src/main.c **** TO10_counter = (task.tau - 1) * 100; 8977 .loc 2 436 8 is_stmt 1 view .LVU2901 436:Src/main.c **** TO10_counter = (task.tau - 1) * 100; 8978 .loc 2 436 27 is_stmt 0 view .LVU2902 8979 0652 42F20F71 movw r1, #9999 8980 0656 D160 str r1, [r2, #12] 437:Src/main.c **** } 8981 .loc 2 437 8 is_stmt 1 view .LVU2903 437:Src/main.c **** } 8982 .loc 2 437 33 is_stmt 0 view .LVU2904 8983 0658 013B subs r3, r3, #1 437:Src/main.c **** } 8984 .loc 2 437 38 view .LVU2905 8985 065a 6422 movs r2, #100 8986 065c 02FB03F3 mul r3, r2, r3 437:Src/main.c **** } 8987 .loc 2 437 21 view .LVU2906 8988 0660 674A ldr r2, .L424+52 8989 0662 1360 str r3, [r2] 8990 .L389: 439:Src/main.c **** break; 8991 .loc 2 439 7 is_stmt 1 view .LVU2907 8992 0664 6048 ldr r0, .L424+28 8993 0666 FFF7FEFF bl HAL_TIM_Base_Start_IT 8994 .LVL707: 440:Src/main.c **** case TT_CHANGE_CURR_2: 8995 .loc 2 440 6 view .LVU2908 8996 066a E7E6 b .L382 8997 .LVL708: 8998 .L381: 444:Src/main.c **** (void) MPhD_T(TT_CHANGE_TEMP_1); 8999 .loc 2 444 7 view .LVU2909 444:Src/main.c **** (void) MPhD_T(TT_CHANGE_TEMP_1); 9000 .loc 2 444 38 is_stmt 0 view .LVU2910 9001 066c 574B ldr r3, .L424 9002 066e D3ED077A vldr.32 s15, [r3, #28] 444:Src/main.c **** (void) MPhD_T(TT_CHANGE_TEMP_1); 9003 .loc 2 444 7 view .LVU2911 9004 0672 FCEEE77A vcvt.u32.f32 s15, s15 9005 0676 17EE903A vmov r3, s15 @ int ARM GAS /tmp/ccqopZd5.s page 539 9006 067a 99B2 uxth r1, r3 9007 067c 0120 movs r0, #1 9008 067e FFF7FEFF bl Set_LTEC 9009 .LVL709: 445:Src/main.c **** LD1_param.LD_CURR_TEMP = MPhD_T(TT_CHANGE_TEMP_1); 9010 .loc 2 445 7 is_stmt 1 view .LVU2912 445:Src/main.c **** LD1_param.LD_CURR_TEMP = MPhD_T(TT_CHANGE_TEMP_1); 9011 .loc 2 445 14 is_stmt 0 view .LVU2913 9012 0682 0320 movs r0, #3 9013 0684 FFF7FEFF bl MPhD_T 9014 .LVL710: 446:Src/main.c **** (void) MPhD_T(TT_CHANGE_TEMP_2); 9015 .loc 2 446 7 is_stmt 1 view .LVU2914 446:Src/main.c **** (void) MPhD_T(TT_CHANGE_TEMP_2); 9016 .loc 2 446 32 is_stmt 0 view .LVU2915 9017 0688 0320 movs r0, #3 9018 068a FFF7FEFF bl MPhD_T 9019 .LVL711: 446:Src/main.c **** (void) MPhD_T(TT_CHANGE_TEMP_2); 9020 .loc 2 446 30 view .LVU2916 9021 068e 504C ldr r4, .L424+4 9022 0690 2080 strh r0, [r4] @ movhi 447:Src/main.c **** LD2_param.LD_CURR_TEMP = MPhD_T(TT_CHANGE_TEMP_2); 9023 .loc 2 447 7 is_stmt 1 view .LVU2917 447:Src/main.c **** LD2_param.LD_CURR_TEMP = MPhD_T(TT_CHANGE_TEMP_2); 9024 .loc 2 447 14 is_stmt 0 view .LVU2918 9025 0692 0420 movs r0, #4 9026 0694 FFF7FEFF bl MPhD_T 9027 .LVL712: 448:Src/main.c **** temp16=PID_Controller_Temp(&LD1_curr_setup, &LD1_param, 1); 9028 .loc 2 448 7 is_stmt 1 view .LVU2919 448:Src/main.c **** temp16=PID_Controller_Temp(&LD1_curr_setup, &LD1_param, 1); 9029 .loc 2 448 32 is_stmt 0 view .LVU2920 9030 0698 0420 movs r0, #4 9031 069a FFF7FEFF bl MPhD_T 9032 .LVL713: 448:Src/main.c **** temp16=PID_Controller_Temp(&LD1_curr_setup, &LD1_param, 1); 9033 .loc 2 448 30 view .LVU2921 9034 069e 4D4D ldr r5, .L424+8 9035 06a0 2880 strh r0, [r5] @ movhi 449:Src/main.c **** Set_LTEC(TT_CHANGE_TEMP_1, temp16);//Drive Laser TEC 1 9036 .loc 2 449 7 is_stmt 1 view .LVU2922 449:Src/main.c **** Set_LTEC(TT_CHANGE_TEMP_1, temp16);//Drive Laser TEC 1 9037 .loc 2 449 14 is_stmt 0 view .LVU2923 9038 06a2 0122 movs r2, #1 9039 06a4 2146 mov r1, r4 9040 06a6 4C48 ldr r0, .L424+12 9041 06a8 FFF7FEFF bl PID_Controller_Temp 9042 .LVL714: 9043 06ac 0146 mov r1, r0 449:Src/main.c **** Set_LTEC(TT_CHANGE_TEMP_1, temp16);//Drive Laser TEC 1 9044 .loc 2 449 13 view .LVU2924 9045 06ae 4B4C ldr r4, .L424+16 9046 06b0 2080 strh r0, [r4] @ movhi 450:Src/main.c **** temp16=PID_Controller_Temp(&LD2_curr_setup, &LD2_param, 2); 9047 .loc 2 450 7 is_stmt 1 view .LVU2925 9048 06b2 0320 movs r0, #3 ARM GAS /tmp/ccqopZd5.s page 540 9049 06b4 FFF7FEFF bl Set_LTEC 9050 .LVL715: 451:Src/main.c **** Set_LTEC(TT_CHANGE_TEMP_2, temp16);//Drive Laser TEC 2 9051 .loc 2 451 7 view .LVU2926 451:Src/main.c **** Set_LTEC(TT_CHANGE_TEMP_2, temp16);//Drive Laser TEC 2 9052 .loc 2 451 14 is_stmt 0 view .LVU2927 9053 06b8 0222 movs r2, #2 9054 06ba 2946 mov r1, r5 9055 06bc 4848 ldr r0, .L424+20 9056 06be FFF7FEFF bl PID_Controller_Temp 9057 .LVL716: 9058 06c2 0146 mov r1, r0 451:Src/main.c **** Set_LTEC(TT_CHANGE_TEMP_2, temp16);//Drive Laser TEC 2 9059 .loc 2 451 13 view .LVU2928 9060 06c4 2080 strh r0, [r4] @ movhi 452:Src/main.c **** 9061 .loc 2 452 7 is_stmt 1 view .LVU2929 9062 06c6 0420 movs r0, #4 9063 06c8 FFF7FEFF bl Set_LTEC 9064 .LVL717: 454:Src/main.c **** LD_blinker.state = 0; // 0 -- disabled (do nothing); 1 -- update LD current; 2 -- blinking, L 9065 .loc 2 454 7 view .LVU2930 454:Src/main.c **** LD_blinker.state = 0; // 0 -- disabled (do nothing); 1 -- update LD current; 2 -- blinking, L 9066 .loc 2 454 28 is_stmt 0 view .LVU2931 9067 06cc 4D4B ldr r3, .L424+56 9068 06ce 0222 movs r2, #2 9069 06d0 1A70 strb r2, [r3] 455:Src/main.c **** //LD_blinker.param = task.current_param; 9070 .loc 2 455 7 is_stmt 1 view .LVU2932 455:Src/main.c **** //LD_blinker.param = task.current_param; 9071 .loc 2 455 24 is_stmt 0 view .LVU2933 9072 06d2 0022 movs r2, #0 9073 06d4 9A72 strb r2, [r3, #10] 457:Src/main.c **** LD_blinker.param = 1000; // LD2 current (in unspecified units) 9074 .loc 2 457 7 is_stmt 1 view .LVU2934 457:Src/main.c **** LD_blinker.param = 1000; // LD2 current (in unspecified units) 9075 .loc 2 457 24 is_stmt 0 view .LVU2935 9076 06d6 1A81 strh r2, [r3, #8] @ movhi 458:Src/main.c **** LD_blinker.signal_port = OUT_10_GPIO_Port; 9077 .loc 2 458 7 is_stmt 1 view .LVU2936 458:Src/main.c **** LD_blinker.signal_port = OUT_10_GPIO_Port; 9078 .loc 2 458 24 is_stmt 0 view .LVU2937 9079 06d8 4FF47A72 mov r2, #1000 9080 06dc 1A81 strh r2, [r3, #8] @ movhi 459:Src/main.c **** LD_blinker.signal_pin = OUT_10_Pin; 9081 .loc 2 459 7 is_stmt 1 view .LVU2938 459:Src/main.c **** LD_blinker.signal_pin = OUT_10_Pin; 9082 .loc 2 459 30 is_stmt 0 view .LVU2939 9083 06de 4A4A ldr r2, .L424+60 9084 06e0 5A60 str r2, [r3, #4] 460:Src/main.c **** 9085 .loc 2 460 7 is_stmt 1 view .LVU2940 460:Src/main.c **** 9086 .loc 2 460 29 is_stmt 0 view .LVU2941 9087 06e2 4FF48072 mov r2, #256 9088 06e6 5A80 strh r2, [r3, #2] @ movhi 462:Src/main.c **** //When it is too low -- Desktop app crashes (there is not so much compute sources on MCU ARM GAS /tmp/ccqopZd5.s page 541 9089 .loc 2 462 7 is_stmt 1 view .LVU2942 462:Src/main.c **** //When it is too low -- Desktop app crashes (there is not so much compute sources on MCU 9090 .loc 2 462 17 is_stmt 0 view .LVU2943 9091 06e8 484B ldr r3, .L424+64 9092 06ea 42F21072 movw r2, #10000 9093 06ee DA62 str r2, [r3, #44] 464:Src/main.c **** if (st != HAL_OK) 9094 .loc 2 464 7 is_stmt 1 view .LVU2944 464:Src/main.c **** if (st != HAL_OK) 9095 .loc 2 464 12 is_stmt 0 view .LVU2945 9096 06f0 4748 ldr r0, .L424+68 9097 06f2 FFF7FEFF bl HAL_TIM_Base_Start_IT 9098 .LVL718: 465:Src/main.c **** while(1); 9099 .loc 2 465 7 is_stmt 1 view .LVU2946 465:Src/main.c **** while(1); 9100 .loc 2 465 10 is_stmt 0 view .LVU2947 9101 06f6 78BB cbnz r0, .L391 470:Src/main.c **** uint32_t i = 10000; while (--i){} 9102 .loc 2 470 7 is_stmt 1 view .LVU2948 9103 06f8 0122 movs r2, #1 9104 06fa 8021 movs r1, #128 9105 06fc 3948 ldr r0, .L424+24 9106 .LVL719: 470:Src/main.c **** uint32_t i = 10000; while (--i){} 9107 .loc 2 470 7 is_stmt 0 view .LVU2949 9108 06fe FFF7FEFF bl HAL_GPIO_WritePin 9109 .LVL720: 471:Src/main.c **** HAL_GPIO_WritePin(GPIOD, GPIO_PIN_7, GPIO_PIN_RESET); 9110 .loc 2 471 7 is_stmt 1 view .LVU2950 471:Src/main.c **** HAL_GPIO_WritePin(GPIOD, GPIO_PIN_7, GPIO_PIN_RESET); 9111 .loc 2 471 27 view .LVU2951 471:Src/main.c **** HAL_GPIO_WritePin(GPIOD, GPIO_PIN_7, GPIO_PIN_RESET); 9112 .loc 2 471 16 is_stmt 0 view .LVU2952 9113 0702 42F21073 movw r3, #10000 9114 .LVL721: 9115 .L392: 471:Src/main.c **** HAL_GPIO_WritePin(GPIOD, GPIO_PIN_7, GPIO_PIN_RESET); 9116 .loc 2 471 39 is_stmt 1 discriminator 2 view .LVU2953 471:Src/main.c **** HAL_GPIO_WritePin(GPIOD, GPIO_PIN_7, GPIO_PIN_RESET); 9117 .loc 2 471 33 discriminator 2 view .LVU2954 471:Src/main.c **** HAL_GPIO_WritePin(GPIOD, GPIO_PIN_7, GPIO_PIN_RESET); 9118 .loc 2 471 33 is_stmt 0 discriminator 2 view .LVU2955 9119 0706 013B subs r3, r3, #1 9120 .LVL722: 471:Src/main.c **** HAL_GPIO_WritePin(GPIOD, GPIO_PIN_7, GPIO_PIN_RESET); 9121 .loc 2 471 33 discriminator 2 view .LVU2956 9122 0708 FDD1 bne .L392 472:Src/main.c **** LD_blinker.state = 2; 9123 .loc 2 472 7 is_stmt 1 view .LVU2957 9124 070a 0022 movs r2, #0 9125 070c 8021 movs r1, #128 9126 070e 3548 ldr r0, .L424+24 9127 0710 FFF7FEFF bl HAL_GPIO_WritePin 9128 .LVL723: 473:Src/main.c **** 9129 .loc 2 473 7 view .LVU2958 ARM GAS /tmp/ccqopZd5.s page 542 473:Src/main.c **** 9130 .loc 2 473 24 is_stmt 0 view .LVU2959 9131 0714 3B4B ldr r3, .L424+56 9132 0716 0222 movs r2, #2 9133 0718 9A72 strb r2, [r3, #10] 475:Src/main.c **** if (st != HAL_OK) 9134 .loc 2 475 7 is_stmt 1 view .LVU2960 475:Src/main.c **** if (st != HAL_OK) 9135 .loc 2 475 12 is_stmt 0 view .LVU2961 9136 071a 3348 ldr r0, .L424+28 9137 071c FFF7FEFF bl HAL_TIM_Base_Start_IT 9138 .LVL724: 476:Src/main.c **** while(1); 9139 .loc 2 476 7 is_stmt 1 view .LVU2962 476:Src/main.c **** while(1); 9140 .loc 2 476 10 is_stmt 0 view .LVU2963 9141 0720 D8B9 cbnz r0, .L394 9142 .L395: 478:Src/main.c **** { 9143 .loc 2 478 13 is_stmt 1 view .LVU2964 478:Src/main.c **** { 9144 .loc 2 478 18 is_stmt 0 view .LVU2965 9145 0722 2A4B ldr r3, .L424 9146 0724 D3ED047A vldr.32 s15, [r3, #16] 478:Src/main.c **** { 9147 .loc 2 478 39 view .LVU2966 9148 0728 93ED027A vldr.32 s14, [r3, #8] 478:Src/main.c **** { 9149 .loc 2 478 13 view .LVU2967 9150 072c F4EEC77A vcmpe.f32 s15, s14 9151 0730 F1EE10FA vmrs APSR_nzcv, FPSCR 9152 0734 12D5 bpl .L419 480:Src/main.c **** { 9153 .loc 2 480 8 is_stmt 1 view .LVU2968 480:Src/main.c **** { 9154 .loc 2 480 12 is_stmt 0 view .LVU2969 9155 0736 2E4B ldr r3, .L424+36 9156 0738 1B78 ldrb r3, [r3] @ zero_extendqisi2 480:Src/main.c **** { 9157 .loc 2 480 11 view .LVU2970 9158 073a 002B cmp r3, #0 9159 073c F1D0 beq .L395 485:Src/main.c **** TO10 = 0; 9160 .loc 2 485 9 is_stmt 1 view .LVU2971 485:Src/main.c **** TO10 = 0; 9161 .loc 2 485 35 is_stmt 0 view .LVU2972 9162 073e 234B ldr r3, .L424 9163 0740 93ED037A vldr.32 s14, [r3, #12] 485:Src/main.c **** TO10 = 0; 9164 .loc 2 485 28 view .LVU2973 9165 0744 77EE277A vadd.f32 s15, s14, s15 9166 0748 C3ED047A vstr.32 s15, [r3, #16] 486:Src/main.c **** TIM10_coflag = 0; 9167 .loc 2 486 9 is_stmt 1 view .LVU2974 486:Src/main.c **** TIM10_coflag = 0; 9168 .loc 2 486 14 is_stmt 0 view .LVU2975 9169 074c 0023 movs r3, #0 ARM GAS /tmp/ccqopZd5.s page 543 9170 074e 2A4A ldr r2, .L424+44 9171 0750 1360 str r3, [r2] 487:Src/main.c **** 9172 .loc 2 487 9 is_stmt 1 view .LVU2976 487:Src/main.c **** 9173 .loc 2 487 22 is_stmt 0 view .LVU2977 9174 0752 274A ldr r2, .L424+36 9175 0754 1370 strb r3, [r2] 9176 0756 E4E7 b .L395 9177 .L391: 466:Src/main.c **** // */ 9178 .loc 2 466 8 is_stmt 1 discriminator 2 view .LVU2978 466:Src/main.c **** // */ 9179 .loc 2 466 16 discriminator 2 view .LVU2979 466:Src/main.c **** // */ 9180 .loc 2 466 13 discriminator 2 view .LVU2980 9181 0758 FEE7 b .L391 9182 .L394: 477:Src/main.c **** while (task.current_param < task.max_param) 9183 .loc 2 477 8 discriminator 3 view .LVU2981 477:Src/main.c **** while (task.current_param < task.max_param) 9184 .loc 2 477 16 discriminator 3 view .LVU2982 477:Src/main.c **** while (task.current_param < task.max_param) 9185 .loc 2 477 13 discriminator 3 view .LVU2983 9186 075a FEE7 b .L394 9187 .L419: 492:Src/main.c **** HAL_GPIO_WritePin(GPIOD, GPIO_PIN_7, GPIO_PIN_SET); 9188 .loc 2 492 7 view .LVU2984 9189 075c 2248 ldr r0, .L424+28 9190 .LVL725: 492:Src/main.c **** HAL_GPIO_WritePin(GPIOD, GPIO_PIN_7, GPIO_PIN_SET); 9191 .loc 2 492 7 is_stmt 0 view .LVU2985 9192 075e FFF7FEFF bl HAL_TIM_Base_Stop 9193 .LVL726: 493:Src/main.c **** 9194 .loc 2 493 7 is_stmt 1 view .LVU2986 9195 0762 204C ldr r4, .L424+24 9196 0764 0122 movs r2, #1 9197 0766 8021 movs r1, #128 9198 0768 2046 mov r0, r4 9199 076a FFF7FEFF bl HAL_GPIO_WritePin 9200 .LVL727: 495:Src/main.c **** 9201 .loc 2 495 7 view .LVU2987 9202 076e 0022 movs r2, #0 9203 0770 8021 movs r1, #128 9204 0772 2046 mov r0, r4 9205 0774 FFF7FEFF bl HAL_GPIO_WritePin 9206 .LVL728: 497:Src/main.c **** TIM8->CNT = 0; 9207 .loc 2 497 7 view .LVU2988 9208 0778 2548 ldr r0, .L424+68 9209 077a FFF7FEFF bl HAL_TIM_Base_Stop_IT 9210 .LVL729: 498:Src/main.c **** 9211 .loc 2 498 7 view .LVU2989 498:Src/main.c **** ARM GAS /tmp/ccqopZd5.s page 544 9212 .loc 2 498 17 is_stmt 0 view .LVU2990 9213 077e 234B ldr r3, .L424+64 9214 0780 0022 movs r2, #0 9215 0782 5A62 str r2, [r3, #36] 500:Src/main.c **** task.current_param = task.min_param; 9216 .loc 2 500 7 is_stmt 1 view .LVU2991 9217 0784 FFF7FEFF bl Stop_TIM10 9218 .LVL730: 501:Src/main.c **** Set_LTEC(TT_CHANGE_CURR_2, task.current_param); 9219 .loc 2 501 7 view .LVU2992 501:Src/main.c **** Set_LTEC(TT_CHANGE_CURR_2, task.current_param); 9220 .loc 2 501 32 is_stmt 0 view .LVU2993 9221 0788 104C ldr r4, .L424 9222 078a D4ED017A vldr.32 s15, [r4, #4] 501:Src/main.c **** Set_LTEC(TT_CHANGE_CURR_2, task.current_param); 9223 .loc 2 501 26 view .LVU2994 9224 078e C4ED047A vstr.32 s15, [r4, #16] 502:Src/main.c **** if (task.tau > 3) 9225 .loc 2 502 7 is_stmt 1 view .LVU2995 9226 0792 FCEEE77A vcvt.u32.f32 s15, s15 9227 0796 17EE903A vmov r3, s15 @ int 9228 079a 99B2 uxth r1, r3 9229 079c 0220 movs r0, #2 9230 079e FFF7FEFF bl Set_LTEC 9231 .LVL731: 503:Src/main.c **** { 9232 .loc 2 503 7 view .LVU2996 503:Src/main.c **** { 9233 .loc 2 503 15 is_stmt 0 view .LVU2997 9234 07a2 E38A ldrh r3, [r4, #22] 503:Src/main.c **** { 9235 .loc 2 503 10 view .LVU2998 9236 07a4 032B cmp r3, #3 9237 07a6 0CD9 bls .L397 505:Src/main.c **** htim10.Init.Period = 9999; 9238 .loc 2 505 8 is_stmt 1 view .LVU2999 505:Src/main.c **** htim10.Init.Period = 9999; 9239 .loc 2 505 34 is_stmt 0 view .LVU3000 9240 07a8 0F4A ldr r2, .L424+28 9241 07aa D068 ldr r0, [r2, #12] 505:Src/main.c **** htim10.Init.Period = 9999; 9242 .loc 2 505 21 view .LVU3001 9243 07ac 1349 ldr r1, .L424+48 9244 07ae 0860 str r0, [r1] 506:Src/main.c **** TO10_counter = (task.tau - 1) * 100; 9245 .loc 2 506 8 is_stmt 1 view .LVU3002 506:Src/main.c **** TO10_counter = (task.tau - 1) * 100; 9246 .loc 2 506 27 is_stmt 0 view .LVU3003 9247 07b0 42F20F71 movw r1, #9999 9248 07b4 D160 str r1, [r2, #12] 507:Src/main.c **** } 9249 .loc 2 507 8 is_stmt 1 view .LVU3004 507:Src/main.c **** } 9250 .loc 2 507 33 is_stmt 0 view .LVU3005 9251 07b6 013B subs r3, r3, #1 507:Src/main.c **** } 9252 .loc 2 507 38 view .LVU3006 ARM GAS /tmp/ccqopZd5.s page 545 9253 07b8 6422 movs r2, #100 9254 07ba 02FB03F3 mul r3, r2, r3 507:Src/main.c **** } 9255 .loc 2 507 21 view .LVU3007 9256 07be 104A ldr r2, .L424+52 9257 07c0 1360 str r3, [r2] 9258 .L397: 509:Src/main.c **** 9259 .loc 2 509 7 is_stmt 1 view .LVU3008 9260 07c2 0948 ldr r0, .L424+28 9261 07c4 FFF7FEFF bl HAL_TIM_Base_Start_IT 9262 .LVL732: 557:Src/main.c **** case TT_CHANGE_TEMP_1: 9263 .loc 2 557 6 view .LVU3009 9264 07c8 38E6 b .L382 9265 .L425: 9266 07ca 00BF .align 2 9267 .L424: 9268 07cc 00000000 .word .LANCHOR1 9269 07d0 00000000 .word .LANCHOR42 9270 07d4 00000000 .word .LANCHOR43 9271 07d8 00000000 .word .LANCHOR23 9272 07dc 00000000 .word .LANCHOR41 9273 07e0 00000000 .word .LANCHOR24 9274 07e4 000C0240 .word 1073875968 9275 07e8 00000000 .word .LANCHOR5 9276 07ec 00000000 .word .LANCHOR37 9277 07f0 00000000 .word .LANCHOR6 9278 07f4 00480140 .word 1073825792 9279 07f8 00000000 .word .LANCHOR7 9280 07fc 00000000 .word .LANCHOR45 9281 0800 00000000 .word .LANCHOR2 9282 0804 00000000 .word .LANCHOR46 9283 0808 00040240 .word 1073873920 9284 080c 00040140 .word 1073808384 9285 0810 00000000 .word .LANCHOR36 9286 0814 00180240 .word 1073879040 9287 .L416: 557:Src/main.c **** case TT_CHANGE_TEMP_1: 9288 .loc 2 557 6 is_stmt 0 view .LVU3010 9289 .LBE571: 568:Src/main.c **** 9290 .loc 2 568 7 is_stmt 1 view .LVU3011 568:Src/main.c **** 9291 .loc 2 568 18 is_stmt 0 view .LVU3012 9292 0818 564A ldr r2, .L426 9293 081a 1360 str r3, [r2] 570:Src/main.c **** LD1_param.POWER = MPhD_T(1);//Get Data from monitor photodiode of LD1 9294 .loc 2 570 7 is_stmt 1 view .LVU3013 570:Src/main.c **** LD1_param.POWER = MPhD_T(1);//Get Data from monitor photodiode of LD1 9295 .loc 2 570 25 is_stmt 0 view .LVU3014 9296 081c 0120 movs r0, #1 9297 081e FFF7FEFF bl MPhD_T 9298 .LVL733: 570:Src/main.c **** LD1_param.POWER = MPhD_T(1);//Get Data from monitor photodiode of LD1 9299 .loc 2 570 23 view .LVU3015 9300 0822 554E ldr r6, .L426+4 ARM GAS /tmp/ccqopZd5.s page 546 9301 0824 3081 strh r0, [r6, #8] @ movhi 571:Src/main.c **** LD2_param.POWER = MPhD_T(2);//Get Data from monitor photodiode of LD2 9302 .loc 2 571 7 is_stmt 1 view .LVU3016 571:Src/main.c **** LD2_param.POWER = MPhD_T(2);//Get Data from monitor photodiode of LD2 9303 .loc 2 571 25 is_stmt 0 view .LVU3017 9304 0826 0120 movs r0, #1 9305 0828 FFF7FEFF bl MPhD_T 9306 .LVL734: 571:Src/main.c **** LD2_param.POWER = MPhD_T(2);//Get Data from monitor photodiode of LD2 9307 .loc 2 571 23 view .LVU3018 9308 082c 3081 strh r0, [r6, #8] @ movhi 572:Src/main.c **** LD2_param.POWER = MPhD_T(2);//Get Data from monitor photodiode of LD2 9309 .loc 2 572 7 is_stmt 1 view .LVU3019 572:Src/main.c **** LD2_param.POWER = MPhD_T(2);//Get Data from monitor photodiode of LD2 9310 .loc 2 572 25 is_stmt 0 view .LVU3020 9311 082e 0220 movs r0, #2 9312 0830 FFF7FEFF bl MPhD_T 9313 .LVL735: 572:Src/main.c **** LD2_param.POWER = MPhD_T(2);//Get Data from monitor photodiode of LD2 9314 .loc 2 572 23 view .LVU3021 9315 0834 514F ldr r7, .L426+8 9316 0836 3881 strh r0, [r7, #8] @ movhi 573:Src/main.c **** 9317 .loc 2 573 7 is_stmt 1 view .LVU3022 573:Src/main.c **** 9318 .loc 2 573 25 is_stmt 0 view .LVU3023 9319 0838 0220 movs r0, #2 9320 083a FFF7FEFF bl MPhD_T 9321 .LVL736: 573:Src/main.c **** 9322 .loc 2 573 23 view .LVU3024 9323 083e 3881 strh r0, [r7, #8] @ movhi 575:Src/main.c **** Long_Data[2] = LD2_param.POWER;//Translate Data from monitor photodiode of LD2 to Long_Data 9324 .loc 2 575 7 is_stmt 1 view .LVU3025 575:Src/main.c **** Long_Data[2] = LD2_param.POWER;//Translate Data from monitor photodiode of LD2 to Long_Data 9325 .loc 2 575 31 is_stmt 0 view .LVU3026 9326 0840 3389 ldrh r3, [r6, #8] 575:Src/main.c **** Long_Data[2] = LD2_param.POWER;//Translate Data from monitor photodiode of LD2 to Long_Data 9327 .loc 2 575 20 view .LVU3027 9328 0842 4F4C ldr r4, .L426+12 9329 0844 6380 strh r3, [r4, #2] @ movhi 576:Src/main.c **** 9330 .loc 2 576 7 is_stmt 1 view .LVU3028 576:Src/main.c **** 9331 .loc 2 576 20 is_stmt 0 view .LVU3029 9332 0846 A080 strh r0, [r4, #4] @ movhi 580:Src/main.c **** temp16 = Get_ADC(1); 9333 .loc 2 580 7 is_stmt 1 view .LVU3030 580:Src/main.c **** temp16 = Get_ADC(1); 9334 .loc 2 580 16 is_stmt 0 view .LVU3031 9335 0848 0020 movs r0, #0 9336 084a FFF7FEFF bl Get_ADC 9337 .LVL737: 580:Src/main.c **** temp16 = Get_ADC(1); 9338 .loc 2 580 14 view .LVU3032 9339 084e 4D4D ldr r5, .L426+16 9340 0850 2880 strh r0, [r5] @ movhi ARM GAS /tmp/ccqopZd5.s page 547 581:Src/main.c **** Long_Data[7] = temp16; 9341 .loc 2 581 7 is_stmt 1 view .LVU3033 581:Src/main.c **** Long_Data[7] = temp16; 9342 .loc 2 581 16 is_stmt 0 view .LVU3034 9343 0852 0120 movs r0, #1 9344 0854 FFF7FEFF bl Get_ADC 9345 .LVL738: 581:Src/main.c **** Long_Data[7] = temp16; 9346 .loc 2 581 14 view .LVU3035 9347 0858 2880 strh r0, [r5] @ movhi 582:Src/main.c **** 9348 .loc 2 582 7 is_stmt 1 view .LVU3036 582:Src/main.c **** 9349 .loc 2 582 20 is_stmt 0 view .LVU3037 9350 085a E081 strh r0, [r4, #14] @ movhi 585:Src/main.c **** Long_Data[8] = temp16; 9351 .loc 2 585 7 is_stmt 1 view .LVU3038 585:Src/main.c **** Long_Data[8] = temp16; 9352 .loc 2 585 16 is_stmt 0 view .LVU3039 9353 085c 0120 movs r0, #1 9354 085e FFF7FEFF bl Get_ADC 9355 .LVL739: 585:Src/main.c **** Long_Data[8] = temp16; 9356 .loc 2 585 14 view .LVU3040 9357 0862 2880 strh r0, [r5] @ movhi 586:Src/main.c **** 9358 .loc 2 586 7 is_stmt 1 view .LVU3041 586:Src/main.c **** 9359 .loc 2 586 20 is_stmt 0 view .LVU3042 9360 0864 2082 strh r0, [r4, #16] @ movhi 589:Src/main.c **** Long_Data[9] = temp16; 9361 .loc 2 589 7 is_stmt 1 view .LVU3043 589:Src/main.c **** Long_Data[9] = temp16; 9362 .loc 2 589 16 is_stmt 0 view .LVU3044 9363 0866 0120 movs r0, #1 9364 0868 FFF7FEFF bl Get_ADC 9365 .LVL740: 589:Src/main.c **** Long_Data[9] = temp16; 9366 .loc 2 589 14 view .LVU3045 9367 086c 2880 strh r0, [r5] @ movhi 590:Src/main.c **** 9368 .loc 2 590 7 is_stmt 1 view .LVU3046 590:Src/main.c **** 9369 .loc 2 590 20 is_stmt 0 view .LVU3047 9370 086e 6082 strh r0, [r4, #18] @ movhi 593:Src/main.c **** Long_Data[10] = temp16; 9371 .loc 2 593 7 is_stmt 1 view .LVU3048 593:Src/main.c **** Long_Data[10] = temp16; 9372 .loc 2 593 16 is_stmt 0 view .LVU3049 9373 0870 0120 movs r0, #1 9374 0872 FFF7FEFF bl Get_ADC 9375 .LVL741: 593:Src/main.c **** Long_Data[10] = temp16; 9376 .loc 2 593 14 view .LVU3050 9377 0876 2880 strh r0, [r5] @ movhi 594:Src/main.c **** 9378 .loc 2 594 7 is_stmt 1 view .LVU3051 ARM GAS /tmp/ccqopZd5.s page 548 594:Src/main.c **** 9379 .loc 2 594 21 is_stmt 0 view .LVU3052 9380 0878 A082 strh r0, [r4, #20] @ movhi 597:Src/main.c **** Long_Data[11] = temp16; 9381 .loc 2 597 7 is_stmt 1 view .LVU3053 597:Src/main.c **** Long_Data[11] = temp16; 9382 .loc 2 597 16 is_stmt 0 view .LVU3054 9383 087a 0120 movs r0, #1 9384 087c FFF7FEFF bl Get_ADC 9385 .LVL742: 597:Src/main.c **** Long_Data[11] = temp16; 9386 .loc 2 597 14 view .LVU3055 9387 0880 2880 strh r0, [r5] @ movhi 598:Src/main.c **** temp16 = Get_ADC(2); 9388 .loc 2 598 7 is_stmt 1 view .LVU3056 598:Src/main.c **** temp16 = Get_ADC(2); 9389 .loc 2 598 21 is_stmt 0 view .LVU3057 9390 0882 E082 strh r0, [r4, #22] @ movhi 599:Src/main.c **** 9391 .loc 2 599 7 is_stmt 1 view .LVU3058 599:Src/main.c **** 9392 .loc 2 599 16 is_stmt 0 view .LVU3059 9393 0884 0220 movs r0, #2 9394 0886 FFF7FEFF bl Get_ADC 9395 .LVL743: 599:Src/main.c **** 9396 .loc 2 599 14 view .LVU3060 9397 088a 2880 strh r0, [r5] @ movhi 602:Src/main.c **** temp16 = Get_ADC(4); 9398 .loc 2 602 7 is_stmt 1 view .LVU3061 602:Src/main.c **** temp16 = Get_ADC(4); 9399 .loc 2 602 16 is_stmt 0 view .LVU3062 9400 088c 0320 movs r0, #3 9401 088e FFF7FEFF bl Get_ADC 9402 .LVL744: 602:Src/main.c **** temp16 = Get_ADC(4); 9403 .loc 2 602 14 view .LVU3063 9404 0892 2880 strh r0, [r5] @ movhi 603:Src/main.c **** Long_Data[12] = temp16; 9405 .loc 2 603 7 is_stmt 1 view .LVU3064 603:Src/main.c **** Long_Data[12] = temp16; 9406 .loc 2 603 16 is_stmt 0 view .LVU3065 9407 0894 0420 movs r0, #4 9408 0896 FFF7FEFF bl Get_ADC 9409 .LVL745: 603:Src/main.c **** Long_Data[12] = temp16; 9410 .loc 2 603 14 view .LVU3066 9411 089a 2880 strh r0, [r5] @ movhi 604:Src/main.c **** temp16 = Get_ADC(5); 9412 .loc 2 604 7 is_stmt 1 view .LVU3067 604:Src/main.c **** temp16 = Get_ADC(5); 9413 .loc 2 604 21 is_stmt 0 view .LVU3068 9414 089c 2083 strh r0, [r4, #24] @ movhi 605:Src/main.c **** 9415 .loc 2 605 7 is_stmt 1 view .LVU3069 605:Src/main.c **** 9416 .loc 2 605 16 is_stmt 0 view .LVU3070 ARM GAS /tmp/ccqopZd5.s page 549 9417 089e 0520 movs r0, #5 9418 08a0 FFF7FEFF bl Get_ADC 9419 .LVL746: 605:Src/main.c **** 9420 .loc 2 605 14 view .LVU3071 9421 08a4 2880 strh r0, [r5] @ movhi 608:Src/main.c **** Long_Data[3] = (TO6_stop)&0xffff; 9422 .loc 2 608 7 is_stmt 1 view .LVU3072 608:Src/main.c **** Long_Data[3] = (TO6_stop)&0xffff; 9423 .loc 2 608 16 is_stmt 0 view .LVU3073 9424 08a6 384B ldr r3, .L426+20 9425 08a8 1B68 ldr r3, [r3] 9426 08aa 384A ldr r2, .L426+24 9427 08ac 1360 str r3, [r2] 609:Src/main.c **** Long_Data[4] = (TO6_stop>>16)&0xffff; 9428 .loc 2 609 7 is_stmt 1 view .LVU3074 609:Src/main.c **** Long_Data[4] = (TO6_stop>>16)&0xffff; 9429 .loc 2 609 20 is_stmt 0 view .LVU3075 9430 08ae E380 strh r3, [r4, #6] @ movhi 610:Src/main.c **** 9431 .loc 2 610 7 is_stmt 1 view .LVU3076 610:Src/main.c **** 9432 .loc 2 610 31 is_stmt 0 view .LVU3077 9433 08b0 1B0C lsrs r3, r3, #16 610:Src/main.c **** 9434 .loc 2 610 20 view .LVU3078 9435 08b2 2381 strh r3, [r4, #8] @ movhi 613:Src/main.c **** 9436 .loc 2 613 7 is_stmt 1 view .LVU3079 613:Src/main.c **** 9437 .loc 2 613 31 is_stmt 0 view .LVU3080 9438 08b4 3388 ldrh r3, [r6] 613:Src/main.c **** 9439 .loc 2 613 20 view .LVU3081 9440 08b6 6381 strh r3, [r4, #10] @ movhi 616:Src/main.c **** } 9441 .loc 2 616 7 is_stmt 1 view .LVU3082 616:Src/main.c **** } 9442 .loc 2 616 31 is_stmt 0 view .LVU3083 9443 08b8 3B88 ldrh r3, [r7] 616:Src/main.c **** } 9444 .loc 2 616 20 view .LVU3084 9445 08ba A381 strh r3, [r4, #12] @ movhi 9446 08bc C5E5 b .L399 9447 .L410: 635:Src/main.c **** //HAL_UART_Transmit(&huart1, State_Data, 2, 10); 9448 .loc 2 635 5 is_stmt 1 view .LVU3085 9449 08be 344C ldr r4, .L426+28 9450 08c0 0221 movs r1, #2 9451 08c2 2046 mov r0, r4 9452 08c4 FFF7FEFF bl USART_TX 9453 .LVL747: 637:Src/main.c **** State_Data[1]=0;//All OK! 9454 .loc 2 637 5 view .LVU3086 637:Src/main.c **** State_Data[1]=0;//All OK! 9455 .loc 2 637 18 is_stmt 0 view .LVU3087 9456 08c8 0023 movs r3, #0 ARM GAS /tmp/ccqopZd5.s page 550 9457 08ca 2370 strb r3, [r4] 638:Src/main.c **** UART_transmission_request = NO_MESS; 9458 .loc 2 638 5 is_stmt 1 view .LVU3088 638:Src/main.c **** UART_transmission_request = NO_MESS; 9459 .loc 2 638 18 is_stmt 0 view .LVU3089 9460 08cc 6370 strb r3, [r4, #1] 639:Src/main.c **** break; 9461 .loc 2 639 5 is_stmt 1 view .LVU3090 639:Src/main.c **** break; 9462 .loc 2 639 31 is_stmt 0 view .LVU3091 9463 08ce 314A ldr r2, .L426+32 9464 08d0 1370 strb r3, [r2] 640:Src/main.c **** case MESS_02://Transmith packet 9465 .loc 2 640 4 is_stmt 1 view .LVU3092 9466 08d2 08E4 b .L403 9467 .L401: 644:Src/main.c **** Long_Data[DL_16-1] = CS_result; 9468 .loc 2 644 5 view .LVU3093 644:Src/main.c **** Long_Data[DL_16-1] = CS_result; 9469 .loc 2 644 17 is_stmt 0 view .LVU3094 9470 08d4 2A4C ldr r4, .L426+12 9471 08d6 0D21 movs r1, #13 9472 08d8 A01C adds r0, r4, #2 9473 08da FFF7FEFF bl CalculateChecksum 9474 .LVL748: 644:Src/main.c **** Long_Data[DL_16-1] = CS_result; 9475 .loc 2 644 15 view .LVU3095 9476 08de 2E4B ldr r3, .L426+36 9477 08e0 1880 strh r0, [r3] @ movhi 645:Src/main.c **** 9478 .loc 2 645 5 is_stmt 1 view .LVU3096 645:Src/main.c **** 9479 .loc 2 645 24 is_stmt 0 view .LVU3097 9480 08e2 A083 strh r0, [r4, #28] @ movhi 647:Src/main.c **** { 9481 .loc 2 647 5 is_stmt 1 view .LVU3098 9482 .LBB572: 647:Src/main.c **** { 9483 .loc 2 647 10 view .LVU3099 9484 .LVL749: 647:Src/main.c **** { 9485 .loc 2 647 19 is_stmt 0 view .LVU3100 9486 08e4 0023 movs r3, #0 647:Src/main.c **** { 9487 .loc 2 647 5 view .LVU3101 9488 08e6 0BE0 b .L404 9489 .LVL750: 9490 .L405: 649:Src/main.c **** UART_DATA[i*2+1] = (Long_Data[i]>>8)&0xff; 9491 .loc 2 649 6 is_stmt 1 discriminator 3 view .LVU3102 649:Src/main.c **** UART_DATA[i*2+1] = (Long_Data[i]>>8)&0xff; 9492 .loc 2 649 33 is_stmt 0 discriminator 3 view .LVU3103 9493 08e8 254A ldr r2, .L426+12 9494 08ea 32F81320 ldrh r2, [r2, r3, lsl #1] 649:Src/main.c **** UART_DATA[i*2+1] = (Long_Data[i]>>8)&0xff; 9495 .loc 2 649 17 discriminator 3 view .LVU3104 9496 08ee 5900 lsls r1, r3, #1 ARM GAS /tmp/ccqopZd5.s page 551 649:Src/main.c **** UART_DATA[i*2+1] = (Long_Data[i]>>8)&0xff; 9497 .loc 2 649 21 discriminator 3 view .LVU3105 9498 08f0 2A48 ldr r0, .L426+40 9499 08f2 00F81320 strb r2, [r0, r3, lsl #1] 650:Src/main.c **** } 9500 .loc 2 650 6 is_stmt 1 discriminator 3 view .LVU3106 650:Src/main.c **** } 9501 .loc 2 650 19 is_stmt 0 discriminator 3 view .LVU3107 9502 08f6 0131 adds r1, r1, #1 650:Src/main.c **** } 9503 .loc 2 650 23 discriminator 3 view .LVU3108 9504 08f8 120A lsrs r2, r2, #8 9505 08fa 4254 strb r2, [r0, r1] 647:Src/main.c **** { 9506 .loc 2 647 37 is_stmt 1 discriminator 3 view .LVU3109 647:Src/main.c **** { 9507 .loc 2 647 38 is_stmt 0 discriminator 3 view .LVU3110 9508 08fc 0133 adds r3, r3, #1 9509 .LVL751: 647:Src/main.c **** { 9510 .loc 2 647 38 discriminator 3 view .LVU3111 9511 08fe 9BB2 uxth r3, r3 9512 .LVL752: 9513 .L404: 647:Src/main.c **** { 9514 .loc 2 647 26 is_stmt 1 discriminator 1 view .LVU3112 647:Src/main.c **** { 9515 .loc 2 647 5 is_stmt 0 discriminator 1 view .LVU3113 9516 0900 0E2B cmp r3, #14 9517 0902 F1D9 bls .L405 9518 .LBE572: 657:Src/main.c **** UART_transmission_request = NO_MESS; 9519 .loc 2 657 5 is_stmt 1 view .LVU3114 9520 0904 1E20 movs r0, #30 9521 0906 FFF7FEFF bl USART_TX_DMA 9522 .LVL753: 658:Src/main.c **** break; 9523 .loc 2 658 5 view .LVU3115 658:Src/main.c **** break; 9524 .loc 2 658 31 is_stmt 0 view .LVU3116 9525 090a 224B ldr r3, .L426+32 9526 090c 0022 movs r2, #0 9527 090e 1A70 strb r2, [r3] 659:Src/main.c **** case MESS_03://Transmith saved packet 9528 .loc 2 659 4 is_stmt 1 view .LVU3117 9529 0910 FFF7E9BB b .L403 9530 .LVL754: 9531 .L406: 9532 .LBB573: 663:Src/main.c **** UART_DATA[i*2+1] = (Long_Data[i]>>8)&0xff; 9533 .loc 2 663 6 discriminator 3 view .LVU3118 663:Src/main.c **** UART_DATA[i*2+1] = (Long_Data[i]>>8)&0xff; 9534 .loc 2 663 33 is_stmt 0 discriminator 3 view .LVU3119 9535 0914 1A4A ldr r2, .L426+12 9536 0916 32F81320 ldrh r2, [r2, r3, lsl #1] 663:Src/main.c **** UART_DATA[i*2+1] = (Long_Data[i]>>8)&0xff; 9537 .loc 2 663 17 discriminator 3 view .LVU3120 ARM GAS /tmp/ccqopZd5.s page 552 9538 091a 5900 lsls r1, r3, #1 663:Src/main.c **** UART_DATA[i*2+1] = (Long_Data[i]>>8)&0xff; 9539 .loc 2 663 21 discriminator 3 view .LVU3121 9540 091c 1F48 ldr r0, .L426+40 9541 091e 00F81320 strb r2, [r0, r3, lsl #1] 664:Src/main.c **** } 9542 .loc 2 664 6 is_stmt 1 discriminator 3 view .LVU3122 664:Src/main.c **** } 9543 .loc 2 664 19 is_stmt 0 discriminator 3 view .LVU3123 9544 0922 0131 adds r1, r1, #1 664:Src/main.c **** } 9545 .loc 2 664 23 discriminator 3 view .LVU3124 9546 0924 120A lsrs r2, r2, #8 9547 0926 4254 strb r2, [r0, r1] 661:Src/main.c **** { 9548 .loc 2 661 37 is_stmt 1 discriminator 3 view .LVU3125 661:Src/main.c **** { 9549 .loc 2 661 38 is_stmt 0 discriminator 3 view .LVU3126 9550 0928 0133 adds r3, r3, #1 9551 .LVL755: 661:Src/main.c **** { 9552 .loc 2 661 38 discriminator 3 view .LVU3127 9553 092a 9BB2 uxth r3, r3 9554 .LVL756: 9555 .L402: 661:Src/main.c **** { 9556 .loc 2 661 26 is_stmt 1 discriminator 1 view .LVU3128 661:Src/main.c **** { 9557 .loc 2 661 5 is_stmt 0 discriminator 1 view .LVU3129 9558 092c 0E2B cmp r3, #14 9559 092e F1D9 bls .L406 9560 .LBE573: 670:Src/main.c **** UART_transmission_request = NO_MESS; 9561 .loc 2 670 5 is_stmt 1 view .LVU3130 9562 0930 1E20 movs r0, #30 9563 0932 FFF7FEFF bl USART_TX_DMA 9564 .LVL757: 671:Src/main.c **** break; 9565 .loc 2 671 5 view .LVU3131 671:Src/main.c **** break; 9566 .loc 2 671 31 is_stmt 0 view .LVU3132 9567 0936 174B ldr r3, .L426+32 9568 0938 0022 movs r2, #0 9569 093a 1A70 strb r2, [r3] 672:Src/main.c **** } 9570 .loc 2 672 4 is_stmt 1 view .LVU3133 9571 093c FFF7D3BB b .L403 9572 .L408: 632:Src/main.c **** { 9573 .loc 2 632 3 is_stmt 0 view .LVU3134 9574 0940 0023 movs r3, #0 9575 0942 F3E7 b .L402 9576 .L411: 674:Src/main.c **** { 9577 .loc 2 674 28 discriminator 1 view .LVU3135 9578 0944 104B ldr r3, .L426+20 9579 0946 1B68 ldr r3, [r3] ARM GAS /tmp/ccqopZd5.s page 553 9580 0948 154A ldr r2, .L426+44 9581 094a 1268 ldr r2, [r2] 9582 094c 9B1A subs r3, r3, r2 674:Src/main.c **** { 9583 .loc 2 674 21 discriminator 1 view .LVU3136 9584 094e 642B cmp r3, #100 9585 0950 7FF6CEAB bls .L356 676:Src/main.c **** State_Data[0] |= UART_ERR;//timeout error! 9586 .loc 2 676 4 is_stmt 1 view .LVU3137 676:Src/main.c **** State_Data[0] |= UART_ERR;//timeout error! 9587 .loc 2 676 18 is_stmt 0 view .LVU3138 9588 0954 0022 movs r2, #0 9589 0956 134B ldr r3, .L426+48 9590 0958 1A80 strh r2, [r3] @ movhi 677:Src/main.c **** UART_transmission_request = MESS_01;//Send status 9591 .loc 2 677 4 is_stmt 1 view .LVU3139 677:Src/main.c **** UART_transmission_request = MESS_01;//Send status 9592 .loc 2 677 18 is_stmt 0 view .LVU3140 9593 095a 0D49 ldr r1, .L426+28 9594 095c 0B78 ldrb r3, [r1] @ zero_extendqisi2 9595 095e 43F00203 orr r3, r3, #2 9596 0962 0B70 strb r3, [r1] 678:Src/main.c **** flg_tmt = 0;//Reset timeout flag 9597 .loc 2 678 4 is_stmt 1 view .LVU3141 678:Src/main.c **** flg_tmt = 0;//Reset timeout flag 9598 .loc 2 678 30 is_stmt 0 view .LVU3142 9599 0964 0B4B ldr r3, .L426+32 9600 0966 0121 movs r1, #1 9601 0968 1970 strb r1, [r3] 679:Src/main.c **** } 9602 .loc 2 679 4 is_stmt 1 view .LVU3143 679:Src/main.c **** } 9603 .loc 2 679 12 is_stmt 0 view .LVU3144 9604 096a 0F4B ldr r3, .L426+52 9605 096c 1A70 strb r2, [r3] 9606 096e FFF7BFBB b .L356 9607 .L427: 9608 0972 00BF .align 2 9609 .L426: 9610 0974 00000000 .word .LANCHOR9 9611 0978 00000000 .word .LANCHOR42 9612 097c 00000000 .word .LANCHOR43 9613 0980 00000000 .word .LANCHOR18 9614 0984 00000000 .word .LANCHOR41 9615 0988 00000000 .word .LANCHOR8 9616 098c 00000000 .word .LANCHOR44 9617 0990 00000000 .word .LANCHOR39 9618 0994 00000000 .word .LANCHOR40 9619 0998 00000000 .word .LANCHOR34 9620 099c 00000000 .word .LANCHOR25 9621 09a0 00000000 .word .LANCHOR11 9622 09a4 00000000 .word .LANCHOR13 9623 09a8 00000000 .word .LANCHOR12 9624 .cfi_endproc 9625 .LFE1186: 9627 .global task 9628 .global LD_blinker ARM GAS /tmp/ccqopZd5.s page 554 9629 .global LD2_param 9630 .global LD1_param 9631 .global Def_setup 9632 .global Curr_setup 9633 .global LD2_def_setup 9634 .global LD1_def_setup 9635 .global LD2_curr_setup 9636 .global LD1_curr_setup 9637 .global sizeoffile 9638 .global fgoto 9639 .global test 9640 .global fresult 9641 .global COMMAND 9642 .global Long_Data 9643 .global temp16 9644 .global CS_result 9645 .global UART_header 9646 .global UART_rec_incr 9647 .global TIM10_coflag 9648 .global u_rx_flg 9649 .global u_tx_flg 9650 .global flg_tmt 9651 .global UART_DATA 9652 .global State_Data 9653 .global UART_transmission_request 9654 .global CPU_state_old 9655 .global CPU_state 9656 .global uart_buf 9657 .global TIM10_period 9658 .global TO10_counter 9659 .global TO10 9660 .global TO7_PID 9661 .global TO7_before 9662 .global TO7 9663 .global temp32 9664 .global SD_SLIDE 9665 .global SD_SEEK 9666 .global TO6_uart 9667 .global TO6_stop 9668 .global TO6_before 9669 .global TO6 9670 .global huart8 9671 .global htim11 9672 .global htim10 9673 .global htim8 9674 .global hsd1 9675 .global hadc3 9676 .global hadc1 9677 .section .bss.COMMAND,"aw",%nobits 9678 .align 2 9679 .set .LANCHOR29,. + 0 9682 COMMAND: 9683 0000 00000000 .space 30 9683 00000000 9683 00000000 9683 00000000 9683 00000000 ARM GAS /tmp/ccqopZd5.s page 555 9684 .section .bss.CPU_state,"aw",%nobits 9685 .set .LANCHOR30,. + 0 9688 CPU_state: 9689 0000 00 .space 1 9690 .section .bss.CPU_state_old,"aw",%nobits 9691 .set .LANCHOR38,. + 0 9694 CPU_state_old: 9695 0000 00 .space 1 9696 .section .bss.CS_result,"aw",%nobits 9697 .align 1 9698 .set .LANCHOR34,. + 0 9701 CS_result: 9702 0000 0000 .space 2 9703 .section .bss.Curr_setup,"aw",%nobits 9704 .align 2 9705 .set .LANCHOR22,. + 0 9708 Curr_setup: 9709 0000 00000000 .space 18 9709 00000000 9709 00000000 9709 00000000 9709 0000 9710 .section .bss.Def_setup,"aw",%nobits 9711 .align 2 9712 .set .LANCHOR19,. + 0 9715 Def_setup: 9716 0000 00000000 .space 18 9716 00000000 9716 00000000 9716 00000000 9716 0000 9717 .section .bss.LD1_curr_setup,"aw",%nobits 9718 .align 2 9719 .set .LANCHOR23,. + 0 9722 LD1_curr_setup: 9723 0000 00000000 .space 16 9723 00000000 9723 00000000 9723 00000000 9724 .section .bss.LD1_def_setup,"aw",%nobits 9725 .align 2 9726 .set .LANCHOR20,. + 0 9729 LD1_def_setup: 9730 0000 00000000 .space 16 9730 00000000 9730 00000000 9730 00000000 9731 .section .bss.LD1_param,"aw",%nobits 9732 .align 2 9733 .set .LANCHOR42,. + 0 9736 LD1_param: 9737 0000 00000000 .space 12 9737 00000000 9737 00000000 9738 .section .bss.LD2_curr_setup,"aw",%nobits 9739 .align 2 9740 .set .LANCHOR24,. + 0 ARM GAS /tmp/ccqopZd5.s page 556 9743 LD2_curr_setup: 9744 0000 00000000 .space 16 9744 00000000 9744 00000000 9744 00000000 9745 .section .bss.LD2_def_setup,"aw",%nobits 9746 .align 2 9747 .set .LANCHOR21,. + 0 9750 LD2_def_setup: 9751 0000 00000000 .space 16 9751 00000000 9751 00000000 9751 00000000 9752 .section .bss.LD2_param,"aw",%nobits 9753 .align 2 9754 .set .LANCHOR43,. + 0 9757 LD2_param: 9758 0000 00000000 .space 12 9758 00000000 9758 00000000 9759 .section .bss.LD_blinker,"aw",%nobits 9760 .align 2 9761 .set .LANCHOR46,. + 0 9764 LD_blinker: 9765 0000 00000000 .space 12 9765 00000000 9765 00000000 9766 .section .bss.Long_Data,"aw",%nobits 9767 .align 2 9768 .set .LANCHOR18,. + 0 9771 Long_Data: 9772 0000 00000000 .space 30 9772 00000000 9772 00000000 9772 00000000 9772 00000000 9773 .section .bss.SD_SEEK,"aw",%nobits 9774 .align 2 9775 .set .LANCHOR26,. + 0 9778 SD_SEEK: 9779 0000 00000000 .space 4 9780 .section .bss.SD_SLIDE,"aw",%nobits 9781 .align 2 9782 .set .LANCHOR27,. + 0 9785 SD_SLIDE: 9786 0000 00000000 .space 4 9787 .section .bss.State_Data,"aw",%nobits 9788 .align 2 9789 .set .LANCHOR39,. + 0 9792 State_Data: 9793 0000 0000 .space 2 9794 .section .bss.TIM10_coflag,"aw",%nobits 9795 .set .LANCHOR6,. + 0 9798 TIM10_coflag: 9799 0000 00 .space 1 9800 .section .bss.TIM10_period,"aw",%nobits 9801 .align 2 ARM GAS /tmp/ccqopZd5.s page 557 9802 .set .LANCHOR45,. + 0 9805 TIM10_period: 9806 0000 00000000 .space 4 9807 .section .bss.TO10,"aw",%nobits 9808 .align 2 9809 .set .LANCHOR7,. + 0 9812 TO10: 9813 0000 00000000 .space 4 9814 .section .bss.TO10_counter,"aw",%nobits 9815 .align 2 9816 .set .LANCHOR2,. + 0 9819 TO10_counter: 9820 0000 00000000 .space 4 9821 .section .bss.TO6,"aw",%nobits 9822 .align 2 9823 .set .LANCHOR8,. + 0 9826 TO6: 9827 0000 00000000 .space 4 9828 .section .bss.TO6_before,"aw",%nobits 9829 .align 2 9830 .set .LANCHOR10,. + 0 9833 TO6_before: 9834 0000 00000000 .space 4 9835 .section .bss.TO6_stop,"aw",%nobits 9836 .align 2 9837 .set .LANCHOR44,. + 0 9840 TO6_stop: 9841 0000 00000000 .space 4 9842 .section .bss.TO6_uart,"aw",%nobits 9843 .align 2 9844 .set .LANCHOR11,. + 0 9847 TO6_uart: 9848 0000 00000000 .space 4 9849 .section .bss.TO7,"aw",%nobits 9850 .align 2 9851 .set .LANCHOR3,. + 0 9854 TO7: 9855 0000 00000000 .space 4 9856 .section .bss.TO7_PID,"aw",%nobits 9857 .align 2 9858 .set .LANCHOR4,. + 0 9861 TO7_PID: 9862 0000 00000000 .space 4 9863 .section .bss.TO7_before,"aw",%nobits 9864 .align 2 9865 .set .LANCHOR9,. + 0 9868 TO7_before: 9869 0000 00000000 .space 4 9870 .section .bss.UART_DATA,"aw",%nobits 9871 .align 2 9872 .set .LANCHOR25,. + 0 9875 UART_DATA: 9876 0000 00000000 .space 30 9876 00000000 9876 00000000 9876 00000000 9876 00000000 ARM GAS /tmp/ccqopZd5.s page 558 9877 .section .bss.UART_header,"aw",%nobits 9878 .align 1 9879 .set .LANCHOR33,. + 0 9882 UART_header: 9883 0000 0000 .space 2 9884 .section .bss.UART_rec_incr,"aw",%nobits 9885 .align 1 9886 .set .LANCHOR13,. + 0 9889 UART_rec_incr: 9890 0000 0000 .space 2 9891 .section .bss.UART_transmission_request,"aw",%nobits 9892 .set .LANCHOR40,. + 0 9895 UART_transmission_request: 9896 0000 00 .space 1 9897 .section .bss.fgoto,"aw",%nobits 9898 .align 2 9899 .set .LANCHOR14,. + 0 9902 fgoto: 9903 0000 00000000 .space 4 9904 .section .bss.flg_tmt,"aw",%nobits 9905 .set .LANCHOR12,. + 0 9908 flg_tmt: 9909 0000 00 .space 1 9910 .section .bss.fresult,"aw",%nobits 9913 fresult: 9914 0000 00 .space 1 9915 .section .bss.hadc1,"aw",%nobits 9916 .align 2 9917 .set .LANCHOR31,. + 0 9920 hadc1: 9921 0000 00000000 .space 72 9921 00000000 9921 00000000 9921 00000000 9921 00000000 9922 .section .bss.hadc3,"aw",%nobits 9923 .align 2 9924 .set .LANCHOR32,. + 0 9927 hadc3: 9928 0000 00000000 .space 72 9928 00000000 9928 00000000 9928 00000000 9928 00000000 9929 .section .bss.hsd1,"aw",%nobits 9930 .align 2 9931 .set .LANCHOR0,. + 0 9934 hsd1: 9935 0000 00000000 .space 132 9935 00000000 9935 00000000 9935 00000000 9935 00000000 9936 .section .bss.htim10,"aw",%nobits 9937 .align 2 9938 .set .LANCHOR5,. + 0 9941 htim10: ARM GAS /tmp/ccqopZd5.s page 559 9942 0000 00000000 .space 76 9942 00000000 9942 00000000 9942 00000000 9942 00000000 9943 .section .bss.htim11,"aw",%nobits 9944 .align 2 9945 .set .LANCHOR37,. + 0 9948 htim11: 9949 0000 00000000 .space 76 9949 00000000 9949 00000000 9949 00000000 9949 00000000 9950 .section .bss.htim8,"aw",%nobits 9951 .align 2 9952 .set .LANCHOR36,. + 0 9955 htim8: 9956 0000 00000000 .space 76 9956 00000000 9956 00000000 9956 00000000 9956 00000000 9957 .section .bss.huart8,"aw",%nobits 9958 .align 2 9959 .set .LANCHOR35,. + 0 9962 huart8: 9963 0000 00000000 .space 136 9963 00000000 9963 00000000 9963 00000000 9963 00000000 9964 .section .bss.sizeoffile,"aw",%nobits 9965 .align 2 9966 .set .LANCHOR15,. + 0 9969 sizeoffile: 9970 0000 00000000 .space 4 9971 .section .bss.task,"aw",%nobits 9972 .align 2 9973 .set .LANCHOR1,. + 0 9976 task: 9977 0000 00000000 .space 52 9977 00000000 9977 00000000 9977 00000000 9977 00000000 9978 .section .bss.temp16,"aw",%nobits 9979 .align 1 9980 .set .LANCHOR41,. + 0 9983 temp16: 9984 0000 0000 .space 2 9985 .section .bss.temp32,"aw",%nobits 9986 .align 2 9989 temp32: 9990 0000 00000000 .space 4 9991 .section .bss.test,"aw",%nobits 9992 .align 2 ARM GAS /tmp/ccqopZd5.s page 560 9993 .set .LANCHOR28,. + 0 9996 test: 9997 0000 00000000 .space 4 9998 .section .bss.u_rx_flg,"aw",%nobits 9999 .set .LANCHOR17,. + 0 10002 u_rx_flg: 10003 0000 00 .space 1 10004 .section .bss.u_tx_flg,"aw",%nobits 10005 .set .LANCHOR16,. + 0 10008 u_tx_flg: 10009 0000 00 .space 1 10010 .section .bss.uart_buf,"aw",%nobits 10013 uart_buf: 10014 0000 00 .space 1 10015 .text 10016 .Letext0: 10017 .file 9 "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h" 10018 .file 10 "/usr/lib/gcc/arm-none-eabi/10.3.1/include/stdint.h" 10019 .file 11 "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h" 10020 .file 12 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h" 10021 .file 13 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h" 10022 .file 14 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h" 10023 .file 15 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h" 10024 .file 16 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h" 10025 .file 17 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h" 10026 .file 18 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_sdmmc.h" 10027 .file 19 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sd.h" 10028 .file 20 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h" 10029 .file 21 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h" 10030 .file 22 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h" 10031 .file 23 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h" 10032 .file 24 "Inc/main.h" 10033 .file 25 "Middlewares/Third_Party/FatFs/src/ff.h" 10034 .file 26 "Inc/File_Handling.h" 10035 .file 27 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h" 10036 .file 28 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h" 10037 .file 29 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h" 10038 .file 30 "Inc/fatfs.h" 10039 .file 31 "" ARM GAS /tmp/ccqopZd5.s page 561 DEFINED SYMBOLS *ABS*:0000000000000000 main.c /tmp/ccqopZd5.s:17 .text.NVIC_EncodePriority:0000000000000000 $t /tmp/ccqopZd5.s:24 .text.NVIC_EncodePriority:0000000000000000 NVIC_EncodePriority /tmp/ccqopZd5.s:84 .text.MX_SDMMC1_SD_Init:0000000000000000 $t /tmp/ccqopZd5.s:90 .text.MX_SDMMC1_SD_Init:0000000000000000 MX_SDMMC1_SD_Init /tmp/ccqopZd5.s:129 .text.MX_SDMMC1_SD_Init:000000000000001c $d /tmp/ccqopZd5.s:135 .text.MX_DMA_Init:0000000000000000 $t /tmp/ccqopZd5.s:141 .text.MX_DMA_Init:0000000000000000 MX_DMA_Init /tmp/ccqopZd5.s:237 .text.MX_DMA_Init:000000000000003c $d /tmp/ccqopZd5.s:244 .text.Decode_task:0000000000000000 $t /tmp/ccqopZd5.s:250 .text.Decode_task:0000000000000000 Decode_task /tmp/ccqopZd5.s:527 .text.Decode_task:0000000000000150 $d /tmp/ccqopZd5.s:537 .text.PID_Controller_Temp:0000000000000000 $t /tmp/ccqopZd5.s:543 .text.PID_Controller_Temp:0000000000000000 PID_Controller_Temp /tmp/ccqopZd5.s:712 .text.PID_Controller_Temp:00000000000000cc $d /tmp/ccqopZd5.s:722 .text.OUT_trigger:0000000000000000 $t /tmp/ccqopZd5.s:728 .text.OUT_trigger:0000000000000000 OUT_trigger /tmp/ccqopZd5.s:746 .text.OUT_trigger:000000000000000a $d /tmp/ccqopZd5.s:756 .text.OUT_trigger:0000000000000014 $t /tmp/ccqopZd5.s:952 .text.OUT_trigger:000000000000011c $d /tmp/ccqopZd5.s:958 .text.MPhD_T:0000000000000000 $t /tmp/ccqopZd5.s:964 .text.MPhD_T:0000000000000000 MPhD_T /tmp/ccqopZd5.s:1576 .text.MPhD_T:0000000000000214 $d /tmp/ccqopZd5.s:1586 .text.Stop_TIM10:0000000000000000 $t /tmp/ccqopZd5.s:1592 .text.Stop_TIM10:0000000000000000 Stop_TIM10 /tmp/ccqopZd5.s:1621 .text.Stop_TIM10:0000000000000014 $d /tmp/ccqopZd5.s:1628 .text.MX_GPIO_Init:0000000000000000 $t /tmp/ccqopZd5.s:1634 .text.MX_GPIO_Init:0000000000000000 MX_GPIO_Init /tmp/ccqopZd5.s:2083 .text.MX_GPIO_Init:0000000000000228 $d /tmp/ccqopZd5.s:2095 .text.MX_SPI4_Init:0000000000000000 $t /tmp/ccqopZd5.s:2101 .text.MX_SPI4_Init:0000000000000000 MX_SPI4_Init /tmp/ccqopZd5.s:2306 .text.MX_SPI4_Init:00000000000000c8 $d /tmp/ccqopZd5.s:2313 .text.MX_SPI2_Init:0000000000000000 $t /tmp/ccqopZd5.s:2319 .text.MX_SPI2_Init:0000000000000000 MX_SPI2_Init /tmp/ccqopZd5.s:2524 .text.MX_SPI2_Init:00000000000000c4 $d /tmp/ccqopZd5.s:2531 .text.MX_SPI5_Init:0000000000000000 $t /tmp/ccqopZd5.s:2537 .text.MX_SPI5_Init:0000000000000000 MX_SPI5_Init /tmp/ccqopZd5.s:2742 .text.MX_SPI5_Init:00000000000000c4 $d /tmp/ccqopZd5.s:2749 .text.MX_SPI6_Init:0000000000000000 $t /tmp/ccqopZd5.s:2755 .text.MX_SPI6_Init:0000000000000000 MX_SPI6_Init /tmp/ccqopZd5.s:2960 .text.MX_SPI6_Init:00000000000000c4 $d /tmp/ccqopZd5.s:2967 .text.MX_TIM2_Init:0000000000000000 $t /tmp/ccqopZd5.s:2973 .text.MX_TIM2_Init:0000000000000000 MX_TIM2_Init /tmp/ccqopZd5.s:3151 .text.MX_TIM2_Init:0000000000000088 $d /tmp/ccqopZd5.s:3160 .text.MX_TIM5_Init:0000000000000000 $t /tmp/ccqopZd5.s:3166 .text.MX_TIM5_Init:0000000000000000 MX_TIM5_Init /tmp/ccqopZd5.s:3343 .text.MX_TIM5_Init:0000000000000084 $d /tmp/ccqopZd5.s:3352 .text.MX_TIM7_Init:0000000000000000 $t /tmp/ccqopZd5.s:3358 .text.MX_TIM7_Init:0000000000000000 MX_TIM7_Init /tmp/ccqopZd5.s:3519 .text.MX_TIM7_Init:000000000000007c $d /tmp/ccqopZd5.s:3527 .text.MX_TIM6_Init:0000000000000000 $t /tmp/ccqopZd5.s:3533 .text.MX_TIM6_Init:0000000000000000 MX_TIM6_Init /tmp/ccqopZd5.s:3694 .text.MX_TIM6_Init:000000000000007c $d /tmp/ccqopZd5.s:3702 .rodata.Init_params.str1.4:0000000000000000 $d /tmp/ccqopZd5.s:3709 .text.Init_params:0000000000000000 $t /tmp/ccqopZd5.s:3715 .text.Init_params:0000000000000000 Init_params ARM GAS /tmp/ccqopZd5.s page 562 /tmp/ccqopZd5.s:4358 .text.Init_params:0000000000000278 $d /tmp/ccqopZd5.s:4397 .text.Get_ADC:0000000000000000 $t /tmp/ccqopZd5.s:4403 .text.Get_ADC:0000000000000000 Get_ADC /tmp/ccqopZd5.s:4423 .text.Get_ADC:000000000000000c $d /tmp/ccqopZd5.s:4429 .text.Get_ADC:0000000000000012 $t /tmp/ccqopZd5.s:4527 .text.Get_ADC:0000000000000068 $d /tmp/ccqopZd5.s:4533 .text.Set_LTEC:0000000000000000 $t /tmp/ccqopZd5.s:4540 .text.Set_LTEC:0000000000000000 Set_LTEC /tmp/ccqopZd5.s:4565 .text.Set_LTEC:000000000000000e $d /tmp/ccqopZd5.s:4569 .text.Set_LTEC:0000000000000012 $t /tmp/ccqopZd5.s:4977 .text.Set_LTEC:0000000000000148 $d /tmp/ccqopZd5.s:4985 .text.Decode_uart:0000000000000000 $t /tmp/ccqopZd5.s:4991 .text.Decode_uart:0000000000000000 Decode_uart /tmp/ccqopZd5.s:5554 .text.Decode_uart:00000000000002cc $d /tmp/ccqopZd5.s:5569 .text.Advanced_Controller_Temp:0000000000000000 $t /tmp/ccqopZd5.s:5576 .text.Advanced_Controller_Temp:0000000000000000 Advanced_Controller_Temp /tmp/ccqopZd5.s:5745 .text.Advanced_Controller_Temp:00000000000000cc $d /tmp/ccqopZd5.s:5755 .text.CalculateChecksum:0000000000000000 $t /tmp/ccqopZd5.s:5762 .text.CalculateChecksum:0000000000000000 CalculateChecksum /tmp/ccqopZd5.s:5809 .text.CheckChecksum:0000000000000000 $t /tmp/ccqopZd5.s:5816 .text.CheckChecksum:0000000000000000 CheckChecksum /tmp/ccqopZd5.s:5878 .text.CheckChecksum:000000000000003c $d /tmp/ccqopZd5.s:5885 .rodata.SD_SAVE.str1.4:0000000000000000 $d /tmp/ccqopZd5.s:5889 .text.SD_SAVE:0000000000000000 $t /tmp/ccqopZd5.s:5896 .text.SD_SAVE:0000000000000000 SD_SAVE /tmp/ccqopZd5.s:5965 .text.SD_SAVE:0000000000000030 $d /tmp/ccqopZd5.s:5972 .text.SD_READ:0000000000000000 $t /tmp/ccqopZd5.s:5979 .text.SD_READ:0000000000000000 SD_READ /tmp/ccqopZd5.s:6057 .text.SD_READ:000000000000003c $d /tmp/ccqopZd5.s:6065 .text.SD_REMOVE:0000000000000000 $t /tmp/ccqopZd5.s:6072 .text.SD_REMOVE:0000000000000000 SD_REMOVE /tmp/ccqopZd5.s:6140 .text.SD_REMOVE:0000000000000034 $d /tmp/ccqopZd5.s:6147 .text.USART_TX:0000000000000000 $t /tmp/ccqopZd5.s:6154 .text.USART_TX:0000000000000000 USART_TX /tmp/ccqopZd5.s:6231 .text.USART_TX:0000000000000028 $d /tmp/ccqopZd5.s:6236 .text.USART_TX_DMA:0000000000000000 $t /tmp/ccqopZd5.s:6243 .text.USART_TX_DMA:0000000000000000 USART_TX_DMA /tmp/ccqopZd5.s:6315 .text.USART_TX_DMA:0000000000000038 $d /tmp/ccqopZd5.s:6322 .text.Error_Handler:0000000000000000 $t /tmp/ccqopZd5.s:6329 .text.Error_Handler:0000000000000000 Error_Handler /tmp/ccqopZd5.s:6360 .text.MX_ADC1_Init:0000000000000000 $t /tmp/ccqopZd5.s:6366 .text.MX_ADC1_Init:0000000000000000 MX_ADC1_Init /tmp/ccqopZd5.s:6555 .text.MX_ADC1_Init:00000000000000bc $d /tmp/ccqopZd5.s:6562 .text.MX_ADC3_Init:0000000000000000 $t /tmp/ccqopZd5.s:6568 .text.MX_ADC3_Init:0000000000000000 MX_ADC3_Init /tmp/ccqopZd5.s:6675 .text.MX_ADC3_Init:0000000000000060 $d /tmp/ccqopZd5.s:6682 .text.MX_USART1_UART_Init:0000000000000000 $t /tmp/ccqopZd5.s:6688 .text.MX_USART1_UART_Init:0000000000000000 MX_USART1_UART_Init /tmp/ccqopZd5.s:7087 .text.MX_USART1_UART_Init:000000000000017c $d /tmp/ccqopZd5.s:7096 .text.MX_TIM10_Init:0000000000000000 $t /tmp/ccqopZd5.s:7102 .text.MX_TIM10_Init:0000000000000000 MX_TIM10_Init /tmp/ccqopZd5.s:7151 .text.MX_TIM10_Init:0000000000000024 $d /tmp/ccqopZd5.s:7157 .text.MX_UART8_Init:0000000000000000 $t /tmp/ccqopZd5.s:7163 .text.MX_UART8_Init:0000000000000000 MX_UART8_Init /tmp/ccqopZd5.s:7224 .text.MX_UART8_Init:0000000000000030 $d /tmp/ccqopZd5.s:7230 .text.MX_TIM8_Init:0000000000000000 $t /tmp/ccqopZd5.s:7236 .text.MX_TIM8_Init:0000000000000000 MX_TIM8_Init ARM GAS /tmp/ccqopZd5.s page 563 /tmp/ccqopZd5.s:7345 .text.MX_TIM8_Init:0000000000000064 $d /tmp/ccqopZd5.s:7351 .text.MX_TIM11_Init:0000000000000000 $t /tmp/ccqopZd5.s:7357 .text.MX_TIM11_Init:0000000000000000 MX_TIM11_Init /tmp/ccqopZd5.s:7467 .text.MX_TIM11_Init:000000000000006c $d /tmp/ccqopZd5.s:7473 .text.SystemClock_Config:0000000000000000 $t /tmp/ccqopZd5.s:7480 .text.SystemClock_Config:0000000000000000 SystemClock_Config /tmp/ccqopZd5.s:7639 .text.SystemClock_Config:00000000000000ac $d /tmp/ccqopZd5.s:7645 .text.main:0000000000000000 $t /tmp/ccqopZd5.s:7652 .text.main:0000000000000000 main /tmp/ccqopZd5.s:8006 .text.main:000000000000010c $d /tmp/ccqopZd5.s:8016 .text.main:0000000000000134 $t /tmp/ccqopZd5.s:8266 .text.main:0000000000000240 $d /tmp/ccqopZd5.s:8291 .text.main:0000000000000298 $t /tmp/ccqopZd5.s:8693 .text.main:0000000000000480 $d /tmp/ccqopZd5.s:8721 .text.main:00000000000004e0 $t /tmp/ccqopZd5.s:9268 .text.main:00000000000007cc $d /tmp/ccqopZd5.s:9292 .text.main:0000000000000818 $t /tmp/ccqopZd5.s:9610 .text.main:0000000000000974 $d /tmp/ccqopZd5.s:9976 .bss.task:0000000000000000 task /tmp/ccqopZd5.s:9764 .bss.LD_blinker:0000000000000000 LD_blinker /tmp/ccqopZd5.s:9757 .bss.LD2_param:0000000000000000 LD2_param /tmp/ccqopZd5.s:9736 .bss.LD1_param:0000000000000000 LD1_param /tmp/ccqopZd5.s:9715 .bss.Def_setup:0000000000000000 Def_setup /tmp/ccqopZd5.s:9708 .bss.Curr_setup:0000000000000000 Curr_setup /tmp/ccqopZd5.s:9750 .bss.LD2_def_setup:0000000000000000 LD2_def_setup /tmp/ccqopZd5.s:9729 .bss.LD1_def_setup:0000000000000000 LD1_def_setup /tmp/ccqopZd5.s:9743 .bss.LD2_curr_setup:0000000000000000 LD2_curr_setup /tmp/ccqopZd5.s:9722 .bss.LD1_curr_setup:0000000000000000 LD1_curr_setup /tmp/ccqopZd5.s:9969 .bss.sizeoffile:0000000000000000 sizeoffile /tmp/ccqopZd5.s:9902 .bss.fgoto:0000000000000000 fgoto /tmp/ccqopZd5.s:9996 .bss.test:0000000000000000 test /tmp/ccqopZd5.s:9913 .bss.fresult:0000000000000000 fresult /tmp/ccqopZd5.s:9682 .bss.COMMAND:0000000000000000 COMMAND /tmp/ccqopZd5.s:9771 .bss.Long_Data:0000000000000000 Long_Data /tmp/ccqopZd5.s:9983 .bss.temp16:0000000000000000 temp16 /tmp/ccqopZd5.s:9701 .bss.CS_result:0000000000000000 CS_result /tmp/ccqopZd5.s:9882 .bss.UART_header:0000000000000000 UART_header /tmp/ccqopZd5.s:9889 .bss.UART_rec_incr:0000000000000000 UART_rec_incr /tmp/ccqopZd5.s:9798 .bss.TIM10_coflag:0000000000000000 TIM10_coflag /tmp/ccqopZd5.s:10002 .bss.u_rx_flg:0000000000000000 u_rx_flg /tmp/ccqopZd5.s:10008 .bss.u_tx_flg:0000000000000000 u_tx_flg /tmp/ccqopZd5.s:9908 .bss.flg_tmt:0000000000000000 flg_tmt /tmp/ccqopZd5.s:9875 .bss.UART_DATA:0000000000000000 UART_DATA /tmp/ccqopZd5.s:9792 .bss.State_Data:0000000000000000 State_Data /tmp/ccqopZd5.s:9895 .bss.UART_transmission_request:0000000000000000 UART_transmission_request /tmp/ccqopZd5.s:9694 .bss.CPU_state_old:0000000000000000 CPU_state_old /tmp/ccqopZd5.s:9688 .bss.CPU_state:0000000000000000 CPU_state /tmp/ccqopZd5.s:10013 .bss.uart_buf:0000000000000000 uart_buf /tmp/ccqopZd5.s:9805 .bss.TIM10_period:0000000000000000 TIM10_period /tmp/ccqopZd5.s:9819 .bss.TO10_counter:0000000000000000 TO10_counter /tmp/ccqopZd5.s:9812 .bss.TO10:0000000000000000 TO10 /tmp/ccqopZd5.s:9861 .bss.TO7_PID:0000000000000000 TO7_PID /tmp/ccqopZd5.s:9868 .bss.TO7_before:0000000000000000 TO7_before /tmp/ccqopZd5.s:9854 .bss.TO7:0000000000000000 TO7 /tmp/ccqopZd5.s:9989 .bss.temp32:0000000000000000 temp32 /tmp/ccqopZd5.s:9785 .bss.SD_SLIDE:0000000000000000 SD_SLIDE /tmp/ccqopZd5.s:9778 .bss.SD_SEEK:0000000000000000 SD_SEEK ARM GAS /tmp/ccqopZd5.s page 564 /tmp/ccqopZd5.s:9847 .bss.TO6_uart:0000000000000000 TO6_uart /tmp/ccqopZd5.s:9840 .bss.TO6_stop:0000000000000000 TO6_stop /tmp/ccqopZd5.s:9833 .bss.TO6_before:0000000000000000 TO6_before /tmp/ccqopZd5.s:9826 .bss.TO6:0000000000000000 TO6 /tmp/ccqopZd5.s:9962 .bss.huart8:0000000000000000 huart8 /tmp/ccqopZd5.s:9948 .bss.htim11:0000000000000000 htim11 /tmp/ccqopZd5.s:9941 .bss.htim10:0000000000000000 htim10 /tmp/ccqopZd5.s:9955 .bss.htim8:0000000000000000 htim8 /tmp/ccqopZd5.s:9934 .bss.hsd1:0000000000000000 hsd1 /tmp/ccqopZd5.s:9927 .bss.hadc3:0000000000000000 hadc3 /tmp/ccqopZd5.s:9920 .bss.hadc1:0000000000000000 hadc1 /tmp/ccqopZd5.s:9678 .bss.COMMAND:0000000000000000 $d /tmp/ccqopZd5.s:9689 .bss.CPU_state:0000000000000000 $d /tmp/ccqopZd5.s:9695 .bss.CPU_state_old:0000000000000000 $d /tmp/ccqopZd5.s:9697 .bss.CS_result:0000000000000000 $d /tmp/ccqopZd5.s:9704 .bss.Curr_setup:0000000000000000 $d /tmp/ccqopZd5.s:9711 .bss.Def_setup:0000000000000000 $d /tmp/ccqopZd5.s:9718 .bss.LD1_curr_setup:0000000000000000 $d /tmp/ccqopZd5.s:9725 .bss.LD1_def_setup:0000000000000000 $d /tmp/ccqopZd5.s:9732 .bss.LD1_param:0000000000000000 $d /tmp/ccqopZd5.s:9739 .bss.LD2_curr_setup:0000000000000000 $d /tmp/ccqopZd5.s:9746 .bss.LD2_def_setup:0000000000000000 $d /tmp/ccqopZd5.s:9753 .bss.LD2_param:0000000000000000 $d /tmp/ccqopZd5.s:9760 .bss.LD_blinker:0000000000000000 $d /tmp/ccqopZd5.s:9767 .bss.Long_Data:0000000000000000 $d /tmp/ccqopZd5.s:9774 .bss.SD_SEEK:0000000000000000 $d /tmp/ccqopZd5.s:9781 .bss.SD_SLIDE:0000000000000000 $d /tmp/ccqopZd5.s:9788 .bss.State_Data:0000000000000000 $d /tmp/ccqopZd5.s:9799 .bss.TIM10_coflag:0000000000000000 $d /tmp/ccqopZd5.s:9801 .bss.TIM10_period:0000000000000000 $d /tmp/ccqopZd5.s:9808 .bss.TO10:0000000000000000 $d /tmp/ccqopZd5.s:9815 .bss.TO10_counter:0000000000000000 $d /tmp/ccqopZd5.s:9822 .bss.TO6:0000000000000000 $d /tmp/ccqopZd5.s:9829 .bss.TO6_before:0000000000000000 $d /tmp/ccqopZd5.s:9836 .bss.TO6_stop:0000000000000000 $d /tmp/ccqopZd5.s:9843 .bss.TO6_uart:0000000000000000 $d /tmp/ccqopZd5.s:9850 .bss.TO7:0000000000000000 $d /tmp/ccqopZd5.s:9857 .bss.TO7_PID:0000000000000000 $d /tmp/ccqopZd5.s:9864 .bss.TO7_before:0000000000000000 $d /tmp/ccqopZd5.s:9871 .bss.UART_DATA:0000000000000000 $d /tmp/ccqopZd5.s:9878 .bss.UART_header:0000000000000000 $d /tmp/ccqopZd5.s:9885 .bss.UART_rec_incr:0000000000000000 $d /tmp/ccqopZd5.s:9896 .bss.UART_transmission_request:0000000000000000 $d /tmp/ccqopZd5.s:9898 .bss.fgoto:0000000000000000 $d /tmp/ccqopZd5.s:9909 .bss.flg_tmt:0000000000000000 $d /tmp/ccqopZd5.s:9914 .bss.fresult:0000000000000000 $d /tmp/ccqopZd5.s:9916 .bss.hadc1:0000000000000000 $d /tmp/ccqopZd5.s:9923 .bss.hadc3:0000000000000000 $d /tmp/ccqopZd5.s:9930 .bss.hsd1:0000000000000000 $d /tmp/ccqopZd5.s:9937 .bss.htim10:0000000000000000 $d /tmp/ccqopZd5.s:9944 .bss.htim11:0000000000000000 $d /tmp/ccqopZd5.s:9951 .bss.htim8:0000000000000000 $d /tmp/ccqopZd5.s:9958 .bss.huart8:0000000000000000 $d /tmp/ccqopZd5.s:9965 .bss.sizeoffile:0000000000000000 $d /tmp/ccqopZd5.s:9972 .bss.task:0000000000000000 $d /tmp/ccqopZd5.s:9979 .bss.temp16:0000000000000000 $d /tmp/ccqopZd5.s:9986 .bss.temp32:0000000000000000 $d ARM GAS /tmp/ccqopZd5.s page 565 /tmp/ccqopZd5.s:9992 .bss.test:0000000000000000 $d /tmp/ccqopZd5.s:10003 .bss.u_rx_flg:0000000000000000 $d /tmp/ccqopZd5.s:10009 .bss.u_tx_flg:0000000000000000 $d /tmp/ccqopZd5.s:10014 .bss.uart_buf:0000000000000000 $d UNDEFINED SYMBOLS HAL_GPIO_WritePin HAL_TIM_Base_Stop_IT HAL_GPIO_Init memset LL_GPIO_Init LL_SPI_Init LL_TIM_Init HAL_GPIO_ReadPin Mount_SD Seek_Read_File Unmount_SD HAL_ADC_Start HAL_ADC_PollForConversion HAL_ADC_GetValue HAL_ADC_Stop Remove_File Create_File Write_File_byte Update_File_byte HAL_ADC_Init HAL_ADC_ConfigChannel HAL_RCCEx_PeriphCLKConfig LL_USART_Init HAL_TIM_Base_Init HAL_UART_Init HAL_TIM_ConfigClockSource HAL_TIMEx_MasterConfigSynchronization HAL_TIM_PWM_Init HAL_TIM_PWM_ConfigChannel HAL_TIM_MspPostInit HAL_RCC_OscConfig HAL_PWREx_EnableOverDrive HAL_RCC_ClockConfig HAL_Init MX_FATFS_Init HAL_TIM_Base_Start HAL_TIM_PWM_Start HAL_TIM_Base_Start_IT HAL_TIM_PWM_Stop HAL_TIM_Base_Stop