ARM GAS /tmp/ccemvyj9.s page 1 1 .cpu cortex-m7 2 .arch armv7e-m 3 .fpu fpv5-d16 4 .eabi_attribute 28, 1 5 .eabi_attribute 20, 1 6 .eabi_attribute 21, 1 7 .eabi_attribute 23, 3 8 .eabi_attribute 24, 1 9 .eabi_attribute 25, 1 10 .eabi_attribute 26, 1 11 .eabi_attribute 30, 1 12 .eabi_attribute 34, 1 13 .eabi_attribute 18, 4 14 .file "stm32f7xx_hal_rcc.c" 15 .text 16 .Ltext0: 17 .cfi_sections .debug_frame 18 .file 1 "Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c" 19 .section .text.HAL_RCC_DeInit,"ax",%progbits 20 .align 1 21 .global HAL_RCC_DeInit 22 .syntax unified 23 .thumb 24 .thumb_func 26 HAL_RCC_DeInit: 27 .LFB141: 1:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /** 2:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** ****************************************************************************** 3:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * @file stm32f7xx_hal_rcc.c 4:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * @author MCD Application Team 5:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * @brief RCC HAL module driver. 6:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * This file provides firmware functions to manage the following 7:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * functionalities of the Reset and Clock Control (RCC) peripheral: 8:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * + Initialization and de-initialization functions 9:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * + Peripheral Control functions 10:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * 11:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** @verbatim 12:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** ============================================================================== 13:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** ##### RCC specific features ##### 14:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** ============================================================================== 15:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** [..] 16:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** After reset the device is running from Internal High Speed oscillator 17:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** (HSI 16MHz) with Flash 0 wait state, Flash prefetch buffer, D-Cache 18:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** and I-Cache are disabled, and all peripherals are off except internal 19:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** SRAM, Flash and JTAG. 20:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** (+) There is no prescaler on High speed (AHB) and Low speed (APB) buses; 21:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** all peripherals mapped on these buses are running at HSI speed. 22:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** (+) The clock for all peripherals is switched off, except the SRAM and FLASH. 23:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** (+) All GPIOs are in input floating state, except the JTAG pins which 24:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** are assigned to be used for debug purpose. 25:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 26:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** [..] 27:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** Once the device started from reset, the user application has to: 28:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** (+) Configure the clock source to be used to drive the System clock 29:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** (if the application needs higher frequency/performance) 30:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** (+) Configure the System clock frequency and Flash settings 31:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** (+) Configure the AHB and APB buses prescalers ARM GAS /tmp/ccemvyj9.s page 2 32:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** (+) Enable the clock for the peripheral(s) to be used 33:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** (+) Configure the clock source(s) for peripherals which clocks are not 34:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** derived from the System clock (I2S, RTC, ADC, USB OTG FS/SDIO/RNG) 35:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 36:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** ##### RCC Limitations ##### 37:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** ============================================================================== 38:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** [..] 39:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** A delay between an RCC peripheral clock enable and the effective peripheral 40:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** enabling should be taken into account in order to manage the peripheral read/write 41:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** from/to registers. 42:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** (+) This delay depends on the peripheral mapping. 43:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** (+) If peripheral is mapped on AHB: the delay is 2 AHB clock cycle 44:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** after the clock enable bit is set on the hardware register 45:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** (+) If peripheral is mapped on APB: the delay is 2 APB clock cycle 46:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** after the clock enable bit is set on the hardware register 47:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 48:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** [..] 49:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** Implemented Workaround: 50:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** (+) For AHB & APB peripherals, a dummy read to the peripheral register has been 51:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** inserted in each __HAL_RCC_PPP_CLK_ENABLE() macro. 52:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 53:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** @endverbatim 54:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** ****************************************************************************** 55:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * @attention 56:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * 57:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * Copyright (c) 2017 STMicroelectronics. 58:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * All rights reserved. 59:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * 60:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * This software is licensed under terms that can be found in the LICENSE file in 61:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * the root directory of this software component. 62:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * If no LICENSE file comes with this software, it is provided AS-IS. 63:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** ****************************************************************************** 64:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** */ 65:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 66:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Includes ------------------------------------------------------------------*/ 67:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** #include "stm32f7xx_hal.h" 68:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 69:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /** @addtogroup STM32F7xx_HAL_Driver 70:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * @{ 71:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** */ 72:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 73:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /** @defgroup RCC RCC 74:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * @brief RCC HAL module driver 75:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * @{ 76:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** */ 77:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 78:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** #ifdef HAL_RCC_MODULE_ENABLED 79:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 80:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Private typedef -----------------------------------------------------------*/ 81:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Private define ------------------------------------------------------------*/ 82:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Private macro -------------------------------------------------------------*/ 83:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /** @defgroup RCC_Private_Macros RCC Private Macros 84:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * @{ 85:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** */ 86:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 87:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** #define MCO1_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE() 88:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** #define MCO1_GPIO_PORT GPIOA ARM GAS /tmp/ccemvyj9.s page 3 89:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** #define MCO1_PIN GPIO_PIN_8 90:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 91:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** #define MCO2_CLK_ENABLE() __HAL_RCC_GPIOC_CLK_ENABLE() 92:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** #define MCO2_GPIO_PORT GPIOC 93:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** #define MCO2_PIN GPIO_PIN_9 94:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 95:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /** 96:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * @} 97:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** */ 98:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Private variables ---------------------------------------------------------*/ 99:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /** @defgroup RCC_Private_Variables RCC Private Variables 100:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * @{ 101:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** */ 102:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 103:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /** 104:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * @} 105:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** */ 106:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 107:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Private function prototypes -----------------------------------------------*/ 108:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Exported functions ---------------------------------------------------------*/ 109:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 110:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /** @defgroup RCC_Exported_Functions RCC Exported Functions 111:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * @{ 112:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** */ 113:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 114:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /** @defgroup RCC_Exported_Functions_Group1 Initialization and de-initialization functions 115:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * @brief Initialization and Configuration functions 116:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * 117:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** @verbatim 118:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** =============================================================================== 119:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** ##### Initialization and de-initialization functions ##### 120:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** =============================================================================== 121:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** [..] 122:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** This section provides functions allowing to configure the internal/external oscillators 123:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** (HSE, HSI, LSE, LSI, PLL, CSS and MCO) and the System buses clocks (SYSCLK, AHB, APB1 124:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** and APB2). 125:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 126:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** [..] Internal/external clock and PLL configuration 127:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** (#) HSI (high-speed internal), 16 MHz factory-trimmed RC used directly or through 128:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** the PLL as System clock source. 129:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 130:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** (#) LSI (low-speed internal), 32 KHz low consumption RC used as IWDG and/or RTC 131:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** clock source. 132:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 133:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** (#) HSE (high-speed external), 4 to 26 MHz crystal oscillator used directly or 134:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** through the PLL as System clock source. Can be used also as RTC clock source. 135:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 136:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** (#) LSE (low-speed external), 32 KHz oscillator used as RTC clock source. 137:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 138:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** (#) PLL (clocked by HSI or HSE), featuring two different output clocks: 139:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** (++) The first output is used to generate the high speed system clock (up to 216 MHz) 140:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** (++) The second output is used to generate the clock for the USB OTG FS (48 MHz), 141:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** the random analog generator (<=48 MHz) and the SDIO (<= 48 MHz). 142:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 143:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** (#) CSS (Clock security system), once enable using the function HAL_RCC_EnableCSS() 144:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** and if a HSE clock failure occurs(HSE used directly or through PLL as System 145:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** clock source), the System clock is automatically switched to HSI and an interrupt ARM GAS /tmp/ccemvyj9.s page 4 146:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** is generated if enabled. The interrupt is linked to the Cortex-M7 NMI 147:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** (Non-Maskable Interrupt) exception vector. 148:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 149:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** (#) MCO1 (microcontroller clock output), used to output HSI, LSE, HSE or PLL 150:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** clock (through a configurable prescaler) on PA8 pin. 151:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 152:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** (#) MCO2 (microcontroller clock output), used to output HSE, PLL, SYSCLK or PLLI2S 153:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** clock (through a configurable prescaler) on PC9 pin. 154:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 155:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** [..] System, AHB and APB buses clocks configuration 156:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** (#) Several clock sources can be used to drive the System clock (SYSCLK): HSI, 157:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** HSE and PLL. 158:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** The AHB clock (HCLK) is derived from System clock through configurable 159:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** prescaler and used to clock the CPU, memory and peripherals mapped 160:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** on AHB bus (DMA, GPIO...). APB1 (PCLK1) and APB2 (PCLK2) clocks are derived 161:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** from AHB clock through configurable prescalers and used to clock 162:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** the peripherals mapped on these buses. You can use 163:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** "HAL_RCC_GetSysClockFreq()" function to retrieve the frequencies of these clocks. 164:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 165:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** -@- All the peripheral clocks are derived from the System clock (SYSCLK) except: 166:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** (+@) I2S: the I2S clock can be derived either from a specific PLL (PLLI2S) or 167:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** from an external clock mapped on the I2S_CKIN pin. 168:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** You have to use __HAL_RCC_PLLI2S_CONFIG() macro to configure this clock. 169:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** (+@) SAI: the SAI clock can be derived either from a specific PLL (PLLI2S) or (PLLSAI) o 170:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** from an external clock mapped on the I2S_CKIN pin. 171:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** You have to use __HAL_RCC_PLLI2S_CONFIG() macro to configure this clock. 172:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** (+@) RTC: the RTC clock can be derived either from the LSI, LSE or HSE clock 173:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** divided by 2 to 31. You have to use __HAL_RCC_RTC_CONFIG() and __HAL_RCC_RTC_ENABLE() 174:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** macros to configure this clock. 175:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** (+@) USB OTG FS, SDIO and RTC: USB OTG FS require a frequency equal to 48 MHz 176:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** to work correctly, while the SDIO require a frequency equal or lower than 177:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** to 48. This clock is derived of the main PLL through PLLQ divider. 178:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** (+@) IWDG clock which is always the LSI clock. 179:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** @endverbatim 180:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * @{ 181:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** */ 182:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 183:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /** 184:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * @brief Resets the RCC clock configuration to the default reset state. 185:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * @note The default reset state of the clock configuration is given below: 186:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * - HSI ON and used as system clock source 187:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * - HSE, PLL, PLLI2S and PLLSAI OFF 188:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * - AHB, APB1 and APB2 prescaler set to 1. 189:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * - CSS, MCO1 and MCO2 OFF 190:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * - All interrupts disabled 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * @note This function doesn't modify the configuration of the 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * - Peripheral clocks 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * - LSI, LSE and RTC clocks 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * @retval None 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** */ 196:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** HAL_StatusTypeDef HAL_RCC_DeInit(void) 197:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 28 .loc 1 197 1 view -0 29 .cfi_startproc 30 @ args = 0, pretend = 0, frame = 0 31 @ frame_needed = 0, uses_anonymous_args = 0 32 0000 38B5 push {r3, r4, r5, lr} ARM GAS /tmp/ccemvyj9.s page 5 33 .LCFI0: 34 .cfi_def_cfa_offset 16 35 .cfi_offset 3, -16 36 .cfi_offset 4, -12 37 .cfi_offset 5, -8 38 .cfi_offset 14, -4 198:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** uint32_t tickstart; 39 .loc 1 198 3 view .LVU1 199:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 200:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Get Start Tick */ 201:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** tickstart = HAL_GetTick(); 40 .loc 1 201 3 view .LVU2 41 .loc 1 201 15 is_stmt 0 view .LVU3 42 0002 FFF7FEFF bl HAL_GetTick 43 .LVL0: 44 0006 0446 mov r4, r0 45 .LVL1: 202:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 203:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Set HSION bit to the reset value */ 204:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** SET_BIT(RCC->CR, RCC_CR_HSION); 46 .loc 1 204 3 is_stmt 1 view .LVU4 47 0008 4E4A ldr r2, .L28 48 000a 1368 ldr r3, [r2] 49 000c 43F00103 orr r3, r3, #1 50 0010 1360 str r3, [r2] 205:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 206:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Wait till HSI is ready */ 207:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == RESET) 51 .loc 1 207 3 view .LVU5 52 .LVL2: 53 .L2: 54 .loc 1 207 43 view .LVU6 55 .loc 1 207 10 is_stmt 0 view .LVU7 56 0012 4C4B ldr r3, .L28 57 0014 1B68 ldr r3, [r3] 58 .loc 1 207 43 view .LVU8 59 0016 13F0020F tst r3, #2 60 001a 06D1 bne .L22 208:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 209:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) 61 .loc 1 209 5 is_stmt 1 view .LVU9 62 .loc 1 209 10 is_stmt 0 view .LVU10 63 001c FFF7FEFF bl HAL_GetTick 64 .LVL3: 65 .loc 1 209 24 discriminator 1 view .LVU11 66 0020 001B subs r0, r0, r4 67 .loc 1 209 8 discriminator 1 view .LVU12 68 0022 0228 cmp r0, #2 69 0024 F5D9 bls .L2 210:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 211:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** return HAL_TIMEOUT; 70 .loc 1 211 14 view .LVU13 71 0026 0320 movs r0, #3 72 .L3: 212:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } 213:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } 214:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** ARM GAS /tmp/ccemvyj9.s page 6 215:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Set HSITRIM[4:0] bits to the reset value */ 216:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** SET_BIT(RCC->CR, RCC_CR_HSITRIM_4); 217:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 218:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Get Start Tick */ 219:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** tickstart = HAL_GetTick(); 220:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 221:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Reset CFGR register */ 222:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** CLEAR_REG(RCC->CFGR); 223:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 224:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Wait till clock switch is ready */ 225:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** while (READ_BIT(RCC->CFGR, RCC_CFGR_SWS) != RESET) 226:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 227:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) 228:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 229:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** return HAL_TIMEOUT; 230:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } 231:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } 232:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 233:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Get Start Tick */ 234:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** tickstart = HAL_GetTick(); 235:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 236:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Clear HSEON, HSEBYP and CSSON bits */ 237:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** CLEAR_BIT(RCC->CR, RCC_CR_HSEON | RCC_CR_HSEBYP | RCC_CR_CSSON); 238:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 239:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Wait till HSE is disabled */ 240:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** while (READ_BIT(RCC->CR, RCC_CR_HSERDY) != RESET) 241:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 242:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) 243:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 244:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** return HAL_TIMEOUT; 245:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } 246:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } 247:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 248:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Get Start Tick */ 249:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** tickstart = HAL_GetTick(); 250:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 251:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Clear PLLON bit */ 252:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** CLEAR_BIT(RCC->CR, RCC_CR_PLLON); 253:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 254:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Wait till PLL is disabled */ 255:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != RESET) 256:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 257:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 258:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 259:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** return HAL_TIMEOUT; 260:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } 261:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } 262:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 263:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Get Start Tick */ 264:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** tickstart = HAL_GetTick(); 265:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 266:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Reset PLLI2SON bit */ 267:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** CLEAR_BIT(RCC->CR, RCC_CR_PLLI2SON); 268:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 269:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Wait till PLLI2S is disabled */ 270:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** while (READ_BIT(RCC->CR, RCC_CR_PLLI2SRDY) != RESET) 271:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { ARM GAS /tmp/ccemvyj9.s page 7 272:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** if ((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE) 273:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 274:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** return HAL_TIMEOUT; 275:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } 276:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } 277:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 278:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Get Start Tick */ 279:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** tickstart = HAL_GetTick(); 280:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 281:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Reset PLLSAI bit */ 282:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** CLEAR_BIT(RCC->CR, RCC_CR_PLLSAION); 283:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 284:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Wait till PLLSAI is disabled */ 285:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** while (READ_BIT(RCC->CR, RCC_CR_PLLSAIRDY) != RESET) 286:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 287:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** if ((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE) 288:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 289:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** return HAL_TIMEOUT; 290:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } 291:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } 292:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 293:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Once PLL, PLLI2S and PLLSAI are OFF, reset PLLCFGR register to default value */ 294:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** RCC->PLLCFGR = RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLN_6 | RCC_PLLCFGR_PLLN_7 | RCC_PLLCFGR_PLLQ_2 295:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 296:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Reset PLLI2SCFGR register to default value */ 297:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** RCC->PLLI2SCFGR = RCC_PLLI2SCFGR_PLLI2SN_6 | RCC_PLLI2SCFGR_PLLI2SN_7 | RCC_PLLI2SCFGR_PLLI2SQ_2 298:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 299:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Reset PLLSAICFGR register to default value */ 300:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** RCC->PLLSAICFGR = RCC_PLLSAICFGR_PLLSAIN_6 | RCC_PLLSAICFGR_PLLSAIN_7 | RCC_PLLSAICFGR_PLLSAIQ_2 301:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 302:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Disable all interrupts */ 303:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** CLEAR_BIT(RCC->CIR, RCC_CIR_LSIRDYIE | RCC_CIR_LSERDYIE | RCC_CIR_HSIRDYIE | RCC_CIR_HSERDYIE | R 304:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 305:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Clear all interrupt flags */ 306:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** SET_BIT(RCC->CIR, RCC_CIR_LSIRDYC | RCC_CIR_LSERDYC | RCC_CIR_HSIRDYC | RCC_CIR_HSERDYC | RCC_CIR 307:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 308:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Clear LSION bit */ 309:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** CLEAR_BIT(RCC->CSR, RCC_CSR_LSION); 310:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 311:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Reset all CSR flags */ 312:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** SET_BIT(RCC->CSR, RCC_CSR_RMVF); 313:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 314:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Update the SystemCoreClock global variable */ 315:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** SystemCoreClock = HSI_VALUE; 316:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 317:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Adapt Systick interrupt period */ 318:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** if (HAL_InitTick(uwTickPrio) != HAL_OK) 319:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 320:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** return HAL_ERROR; 321:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } 322:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** else 323:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 324:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** return HAL_OK; 325:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } 326:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } 73 .loc 1 326 1 view .LVU14 74 0028 38BD pop {r3, r4, r5, pc} ARM GAS /tmp/ccemvyj9.s page 8 75 .LVL4: 76 .L22: 216:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 77 .loc 1 216 3 is_stmt 1 view .LVU15 78 002a 464D ldr r5, .L28 79 002c 2B68 ldr r3, [r5] 80 002e 43F08003 orr r3, r3, #128 81 0032 2B60 str r3, [r5] 219:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 82 .loc 1 219 3 view .LVU16 219:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 83 .loc 1 219 15 is_stmt 0 view .LVU17 84 0034 FFF7FEFF bl HAL_GetTick 85 .LVL5: 86 0038 0446 mov r4, r0 87 .LVL6: 222:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 88 .loc 1 222 3 is_stmt 1 view .LVU18 89 003a 0023 movs r3, #0 90 003c AB60 str r3, [r5, #8] 225:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 91 .loc 1 225 3 view .LVU19 92 .LVL7: 93 .L5: 225:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 94 .loc 1 225 44 view .LVU20 225:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 95 .loc 1 225 10 is_stmt 0 view .LVU21 96 003e 414B ldr r3, .L28 97 0040 9B68 ldr r3, [r3, #8] 225:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 98 .loc 1 225 44 view .LVU22 99 0042 13F00C0F tst r3, #12 100 0046 08D0 beq .L23 227:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 101 .loc 1 227 5 is_stmt 1 view .LVU23 227:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 102 .loc 1 227 10 is_stmt 0 view .LVU24 103 0048 FFF7FEFF bl HAL_GetTick 104 .LVL8: 227:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 105 .loc 1 227 24 discriminator 1 view .LVU25 106 004c 001B subs r0, r0, r4 227:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 107 .loc 1 227 8 discriminator 1 view .LVU26 108 004e 41F28833 movw r3, #5000 109 0052 9842 cmp r0, r3 110 0054 F3D9 bls .L5 229:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } 111 .loc 1 229 14 view .LVU27 112 0056 0320 movs r0, #3 113 0058 E6E7 b .L3 114 .L23: 234:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 115 .loc 1 234 3 is_stmt 1 view .LVU28 234:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 116 .loc 1 234 15 is_stmt 0 view .LVU29 ARM GAS /tmp/ccemvyj9.s page 9 117 005a FFF7FEFF bl HAL_GetTick 118 .LVL9: 119 005e 0446 mov r4, r0 120 .LVL10: 237:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 121 .loc 1 237 3 is_stmt 1 view .LVU30 122 0060 384A ldr r2, .L28 123 0062 1368 ldr r3, [r2] 124 0064 23F45023 bic r3, r3, #851968 125 0068 1360 str r3, [r2] 240:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 126 .loc 1 240 3 view .LVU31 127 .LVL11: 128 .L7: 240:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 129 .loc 1 240 43 view .LVU32 240:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 130 .loc 1 240 10 is_stmt 0 view .LVU33 131 006a 364B ldr r3, .L28 132 006c 1B68 ldr r3, [r3] 240:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 133 .loc 1 240 43 view .LVU34 134 006e 13F4003F tst r3, #131072 135 0072 06D0 beq .L24 242:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 136 .loc 1 242 5 is_stmt 1 view .LVU35 242:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 137 .loc 1 242 10 is_stmt 0 view .LVU36 138 0074 FFF7FEFF bl HAL_GetTick 139 .LVL12: 242:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 140 .loc 1 242 24 discriminator 1 view .LVU37 141 0078 001B subs r0, r0, r4 242:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 142 .loc 1 242 8 discriminator 1 view .LVU38 143 007a 6428 cmp r0, #100 144 007c F5D9 bls .L7 244:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } 145 .loc 1 244 14 view .LVU39 146 007e 0320 movs r0, #3 147 0080 D2E7 b .L3 148 .L24: 249:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 149 .loc 1 249 3 is_stmt 1 view .LVU40 249:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 150 .loc 1 249 15 is_stmt 0 view .LVU41 151 0082 FFF7FEFF bl HAL_GetTick 152 .LVL13: 153 0086 0446 mov r4, r0 154 .LVL14: 252:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 155 .loc 1 252 3 is_stmt 1 view .LVU42 156 0088 2E4A ldr r2, .L28 157 008a 1368 ldr r3, [r2] 158 008c 23F08073 bic r3, r3, #16777216 159 0090 1360 str r3, [r2] 255:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { ARM GAS /tmp/ccemvyj9.s page 10 160 .loc 1 255 3 view .LVU43 161 .LVL15: 162 .L9: 255:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 163 .loc 1 255 43 view .LVU44 255:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 164 .loc 1 255 10 is_stmt 0 view .LVU45 165 0092 2C4B ldr r3, .L28 166 0094 1B68 ldr r3, [r3] 255:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 167 .loc 1 255 43 view .LVU46 168 0096 13F0007F tst r3, #33554432 169 009a 06D0 beq .L25 257:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 170 .loc 1 257 5 is_stmt 1 view .LVU47 257:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 171 .loc 1 257 10 is_stmt 0 view .LVU48 172 009c FFF7FEFF bl HAL_GetTick 173 .LVL16: 257:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 174 .loc 1 257 24 discriminator 1 view .LVU49 175 00a0 001B subs r0, r0, r4 257:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 176 .loc 1 257 8 discriminator 1 view .LVU50 177 00a2 0228 cmp r0, #2 178 00a4 F5D9 bls .L9 259:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } 179 .loc 1 259 14 view .LVU51 180 00a6 0320 movs r0, #3 181 00a8 BEE7 b .L3 182 .L25: 264:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 183 .loc 1 264 3 is_stmt 1 view .LVU52 264:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 184 .loc 1 264 15 is_stmt 0 view .LVU53 185 00aa FFF7FEFF bl HAL_GetTick 186 .LVL17: 187 00ae 0446 mov r4, r0 188 .LVL18: 267:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 189 .loc 1 267 3 is_stmt 1 view .LVU54 190 00b0 244A ldr r2, .L28 191 00b2 1368 ldr r3, [r2] 192 00b4 23F08063 bic r3, r3, #67108864 193 00b8 1360 str r3, [r2] 270:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 194 .loc 1 270 3 view .LVU55 195 .LVL19: 196 .L11: 270:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 197 .loc 1 270 46 view .LVU56 270:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 198 .loc 1 270 10 is_stmt 0 view .LVU57 199 00ba 224B ldr r3, .L28 200 00bc 1B68 ldr r3, [r3] 270:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 201 .loc 1 270 46 view .LVU58 ARM GAS /tmp/ccemvyj9.s page 11 202 00be 13F0006F tst r3, #134217728 203 00c2 06D0 beq .L26 272:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 204 .loc 1 272 5 is_stmt 1 view .LVU59 272:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 205 .loc 1 272 10 is_stmt 0 view .LVU60 206 00c4 FFF7FEFF bl HAL_GetTick 207 .LVL20: 272:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 208 .loc 1 272 24 discriminator 1 view .LVU61 209 00c8 001B subs r0, r0, r4 272:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 210 .loc 1 272 8 discriminator 1 view .LVU62 211 00ca 6428 cmp r0, #100 212 00cc F5D9 bls .L11 274:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } 213 .loc 1 274 14 view .LVU63 214 00ce 0320 movs r0, #3 215 00d0 AAE7 b .L3 216 .L26: 279:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 217 .loc 1 279 3 is_stmt 1 view .LVU64 279:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 218 .loc 1 279 15 is_stmt 0 view .LVU65 219 00d2 FFF7FEFF bl HAL_GetTick 220 .LVL21: 221 00d6 0446 mov r4, r0 222 .LVL22: 282:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 223 .loc 1 282 3 is_stmt 1 view .LVU66 224 00d8 1A4A ldr r2, .L28 225 00da 1368 ldr r3, [r2] 226 00dc 23F08053 bic r3, r3, #268435456 227 00e0 1360 str r3, [r2] 285:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 228 .loc 1 285 3 view .LVU67 229 .LVL23: 230 .L13: 285:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 231 .loc 1 285 46 view .LVU68 285:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 232 .loc 1 285 10 is_stmt 0 view .LVU69 233 00e2 184B ldr r3, .L28 234 00e4 1B68 ldr r3, [r3] 285:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 235 .loc 1 285 46 view .LVU70 236 00e6 13F0005F tst r3, #536870912 237 00ea 06D0 beq .L27 287:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 238 .loc 1 287 5 is_stmt 1 view .LVU71 287:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 239 .loc 1 287 10 is_stmt 0 view .LVU72 240 00ec FFF7FEFF bl HAL_GetTick 241 .LVL24: 287:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 242 .loc 1 287 24 discriminator 1 view .LVU73 243 00f0 001B subs r0, r0, r4 ARM GAS /tmp/ccemvyj9.s page 12 287:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 244 .loc 1 287 8 discriminator 1 view .LVU74 245 00f2 6428 cmp r0, #100 246 00f4 F5D9 bls .L13 289:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } 247 .loc 1 289 14 view .LVU75 248 00f6 0320 movs r0, #3 249 00f8 96E7 b .L3 250 .L27: 294:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 251 .loc 1 294 3 is_stmt 1 view .LVU76 294:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 252 .loc 1 294 16 is_stmt 0 view .LVU77 253 00fa 124B ldr r3, .L28 254 00fc 124A ldr r2, .L28+4 255 00fe 5A60 str r2, [r3, #4] 297:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 256 .loc 1 297 3 is_stmt 1 view .LVU78 297:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 257 .loc 1 297 19 is_stmt 0 view .LVU79 258 0100 103A subs r2, r2, #16 259 0102 C3F88420 str r2, [r3, #132] 300:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 260 .loc 1 300 3 is_stmt 1 view .LVU80 300:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 261 .loc 1 300 19 is_stmt 0 view .LVU81 262 0106 C3F88820 str r2, [r3, #136] 303:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 263 .loc 1 303 3 is_stmt 1 view .LVU82 264 010a DA68 ldr r2, [r3, #12] 265 010c 22F4FE42 bic r2, r2, #32512 266 0110 DA60 str r2, [r3, #12] 306:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 267 .loc 1 306 3 view .LVU83 268 0112 DA68 ldr r2, [r3, #12] 269 0114 42F47F02 orr r2, r2, #16711680 270 0118 DA60 str r2, [r3, #12] 309:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 271 .loc 1 309 3 view .LVU84 272 011a 5A6F ldr r2, [r3, #116] 273 011c 22F00102 bic r2, r2, #1 274 0120 5A67 str r2, [r3, #116] 312:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 275 .loc 1 312 3 view .LVU85 276 0122 5A6F ldr r2, [r3, #116] 277 0124 42F08072 orr r2, r2, #16777216 278 0128 5A67 str r2, [r3, #116] 315:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 279 .loc 1 315 3 view .LVU86 315:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 280 .loc 1 315 19 is_stmt 0 view .LVU87 281 012a 084B ldr r3, .L28+8 282 012c 084A ldr r2, .L28+12 283 012e 1A60 str r2, [r3] 318:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 284 .loc 1 318 3 is_stmt 1 view .LVU88 318:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { ARM GAS /tmp/ccemvyj9.s page 13 285 .loc 1 318 7 is_stmt 0 view .LVU89 286 0130 084B ldr r3, .L28+16 287 0132 1868 ldr r0, [r3] 288 0134 FFF7FEFF bl HAL_InitTick 289 .LVL25: 318:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 290 .loc 1 318 6 discriminator 1 view .LVU90 291 0138 0028 cmp r0, #0 292 013a 3FF475AF beq .L3 320:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } 293 .loc 1 320 12 view .LVU91 294 013e 0120 movs r0, #1 295 0140 72E7 b .L3 296 .L29: 297 0142 00BF .align 2 298 .L28: 299 0144 00380240 .word 1073887232 300 0148 10300024 .word 603992080 301 014c 00000000 .word SystemCoreClock 302 0150 0024F400 .word 16000000 303 0154 00000000 .word uwTickPrio 304 .cfi_endproc 305 .LFE141: 307 .section .text.HAL_RCC_OscConfig,"ax",%progbits 308 .align 1 309 .global HAL_RCC_OscConfig 310 .syntax unified 311 .thumb 312 .thumb_func 314 HAL_RCC_OscConfig: 315 .LVL26: 316 .LFB142: 327:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 328:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /** 329:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * @brief Initializes the RCC Oscillators according to the specified parameters in the 330:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * RCC_OscInitTypeDef. 331:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * @param RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that 332:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * contains the configuration information for the RCC Oscillators. 333:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * @note The PLL is not disabled when used as system clock. 334:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not 335:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * supported by this function. User should request a transition to LSE Off 336:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * first and then LSE On or LSE Bypass. 337:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not 338:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * supported by this function. User should request a transition to HSE Off 339:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * first and then HSE On or HSE Bypass. 340:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * @retval HAL status 341:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** */ 342:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) 343:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 317 .loc 1 343 1 is_stmt 1 view -0 318 .cfi_startproc 319 @ args = 0, pretend = 0, frame = 8 320 @ frame_needed = 0, uses_anonymous_args = 0 344:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** uint32_t tickstart; 321 .loc 1 344 3 view .LVU93 345:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** uint32_t pll_config; 322 .loc 1 345 3 view .LVU94 ARM GAS /tmp/ccemvyj9.s page 14 346:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** FlagStatus pwrclkchanged = RESET; 323 .loc 1 346 3 view .LVU95 347:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 348:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Check Null pointer */ 349:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** if (RCC_OscInitStruct == NULL) 324 .loc 1 349 3 view .LVU96 325 .loc 1 349 6 is_stmt 0 view .LVU97 326 0000 0028 cmp r0, #0 327 0002 00F00682 beq .L82 343:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** uint32_t tickstart; 328 .loc 1 343 1 view .LVU98 329 0006 70B5 push {r4, r5, r6, lr} 330 .LCFI1: 331 .cfi_def_cfa_offset 16 332 .cfi_offset 4, -16 333 .cfi_offset 5, -12 334 .cfi_offset 6, -8 335 .cfi_offset 14, -4 336 0008 82B0 sub sp, sp, #8 337 .LCFI2: 338 .cfi_def_cfa_offset 24 339 000a 0446 mov r4, r0 350:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 351:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** return HAL_ERROR; 352:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } 353:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 354:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Check the parameters */ 355:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); 340 .loc 1 355 3 is_stmt 1 view .LVU99 356:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 357:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /*------------------------------- HSE Configuration ------------------------*/ 358:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) 341 .loc 1 358 3 view .LVU100 342 .loc 1 358 26 is_stmt 0 view .LVU101 343 000c 0368 ldr r3, [r0] 344 .loc 1 358 6 view .LVU102 345 000e 13F0010F tst r3, #1 346 0012 29D0 beq .L32 359:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 360:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Check the parameters */ 361:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState)); 347 .loc 1 361 5 is_stmt 1 view .LVU103 362:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* When the HSE is used as system clock or clock source for PLL, It can not be disabled */ 363:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE) 348 .loc 1 363 5 view .LVU104 349 .loc 1 363 10 is_stmt 0 view .LVU105 350 0014 954B ldr r3, .L124 351 0016 9B68 ldr r3, [r3, #8] 352 0018 03F00C03 and r3, r3, #12 353 .loc 1 363 8 view .LVU106 354 001c 042B cmp r3, #4 355 001e 1AD0 beq .L33 364:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && ((RCC->PLLCFGR & R 356 .loc 1 364 14 view .LVU107 357 0020 924B ldr r3, .L124 358 0022 9B68 ldr r3, [r3, #8] 359 0024 03F00C03 and r3, r3, #12 ARM GAS /tmp/ccemvyj9.s page 15 360 .loc 1 364 9 view .LVU108 361 0028 082B cmp r3, #8 362 002a 0FD0 beq .L110 363 .L34: 365:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 366:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE 367:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 368:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** return HAL_ERROR; 369:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } 370:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } 371:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** else 372:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 373:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Set the new HSE configuration ---------------------------------------*/ 374:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); 364 .loc 1 374 7 is_stmt 1 view .LVU109 365 .loc 1 374 7 view .LVU110 366 002c 6368 ldr r3, [r4, #4] 367 002e B3F5803F cmp r3, #65536 368 0032 40D0 beq .L111 369 .loc 1 374 7 discriminator 2 view .LVU111 370 0034 002B cmp r3, #0 371 0036 54D1 bne .L37 372 .loc 1 374 7 discriminator 4 view .LVU112 373 0038 8C4B ldr r3, .L124 374 003a 1A68 ldr r2, [r3] 375 003c 22F48032 bic r2, r2, #65536 376 0040 1A60 str r2, [r3] 377 .loc 1 374 7 discriminator 4 view .LVU113 378 0042 1A68 ldr r2, [r3] 379 0044 22F48022 bic r2, r2, #262144 380 0048 1A60 str r2, [r3] 381 004a 39E0 b .L36 382 .L110: 364:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && ((RCC->PLLCFGR & R 383 .loc 1 364 87 is_stmt 0 discriminator 1 view .LVU114 384 004c 874B ldr r3, .L124 385 004e 5B68 ldr r3, [r3, #4] 364:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && ((RCC->PLLCFGR & R 386 .loc 1 364 79 discriminator 1 view .LVU115 387 0050 13F4800F tst r3, #4194304 388 0054 EAD0 beq .L34 389 .L33: 366:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 390 .loc 1 366 7 is_stmt 1 view .LVU116 366:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 391 .loc 1 366 12 is_stmt 0 view .LVU117 392 0056 854B ldr r3, .L124 393 0058 1B68 ldr r3, [r3] 366:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 394 .loc 1 366 10 view .LVU118 395 005a 13F4003F tst r3, #131072 396 005e 03D0 beq .L32 366:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 397 .loc 1 366 79 discriminator 1 view .LVU119 398 0060 6368 ldr r3, [r4, #4] 366:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 399 .loc 1 366 58 discriminator 1 view .LVU120 ARM GAS /tmp/ccemvyj9.s page 16 400 0062 002B cmp r3, #0 401 0064 00F0D781 beq .L112 402 .LVL27: 403 .L32: 375:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 376:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Check the HSE State */ 377:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** if (RCC_OscInitStruct->HSEState != RCC_HSE_OFF) 378:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 379:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Get Start Tick*/ 380:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** tickstart = HAL_GetTick(); 381:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 382:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Wait till HSE is ready */ 383:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) 384:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 385:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) 386:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 387:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** return HAL_TIMEOUT; 388:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } 389:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } 390:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } 391:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** else 392:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 393:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Get Start Tick*/ 394:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** tickstart = HAL_GetTick(); 395:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 396:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Wait till HSE is bypassed or disabled */ 397:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) 398:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 399:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) 400:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 401:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** return HAL_TIMEOUT; 402:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } 403:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } 404:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } 405:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } 406:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } 407:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /*----------------------------- HSI Configuration --------------------------*/ 408:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) 404 .loc 1 408 3 is_stmt 1 view .LVU121 405 .loc 1 408 26 is_stmt 0 view .LVU122 406 0068 2368 ldr r3, [r4] 407 .loc 1 408 6 view .LVU123 408 006a 13F0020F tst r3, #2 409 006e 74D0 beq .L44 409:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 410:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Check the parameters */ 411:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState)); 410 .loc 1 411 5 is_stmt 1 view .LVU124 412:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue)); 411 .loc 1 412 5 view .LVU125 413:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 414:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock * 415:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI) 412 .loc 1 415 5 view .LVU126 413 .loc 1 415 10 is_stmt 0 view .LVU127 414 0070 7E4B ldr r3, .L124 415 0072 9B68 ldr r3, [r3, #8] ARM GAS /tmp/ccemvyj9.s page 17 416 .loc 1 415 8 view .LVU128 417 0074 13F00C0F tst r3, #12 418 0078 5ED0 beq .L45 416:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && ((RCC->PLLCFGR & R 419 .loc 1 416 14 view .LVU129 420 007a 7C4B ldr r3, .L124 421 007c 9B68 ldr r3, [r3, #8] 422 007e 03F00C03 and r3, r3, #12 423 .loc 1 416 9 view .LVU130 424 0082 082B cmp r3, #8 425 0084 53D0 beq .L113 426 .L46: 417:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 418:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* When HSI is used as system clock it will not disabled */ 419:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI 420:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 421:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** return HAL_ERROR; 422:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } 423:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Otherwise, just the calibration is allowed */ 424:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** else 425:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 426:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ 427:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 428:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } 429:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } 430:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** else 431:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 432:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Check the HSI State */ 433:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** if ((RCC_OscInitStruct->HSIState) != RCC_HSI_OFF) 427 .loc 1 433 7 is_stmt 1 view .LVU131 428 .loc 1 433 29 is_stmt 0 view .LVU132 429 0086 E368 ldr r3, [r4, #12] 430 .loc 1 433 10 view .LVU133 431 0088 002B cmp r3, #0 432 008a 00F08980 beq .L48 434:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 435:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Enable the Internal High Speed oscillator (HSI). */ 436:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** __HAL_RCC_HSI_ENABLE(); 433 .loc 1 436 9 is_stmt 1 view .LVU134 434 008e 774A ldr r2, .L124 435 0090 1368 ldr r3, [r2] 436 0092 43F00103 orr r3, r3, #1 437 0096 1360 str r3, [r2] 437:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 438:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Get Start Tick*/ 439:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** tickstart = HAL_GetTick(); 438 .loc 1 439 9 view .LVU135 439 .loc 1 439 21 is_stmt 0 view .LVU136 440 0098 FFF7FEFF bl HAL_GetTick 441 .LVL28: 442 009c 0546 mov r5, r0 443 .LVL29: 440:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 441:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Wait till HSI is ready */ 442:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) 444 .loc 1 442 9 is_stmt 1 view .LVU137 445 .L49: ARM GAS /tmp/ccemvyj9.s page 18 446 .loc 1 442 52 view .LVU138 447 .loc 1 442 16 is_stmt 0 view .LVU139 448 009e 734B ldr r3, .L124 449 00a0 1B68 ldr r3, [r3] 450 .loc 1 442 52 view .LVU140 451 00a2 13F0020F tst r3, #2 452 00a6 72D1 bne .L114 443:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 444:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) 453 .loc 1 444 11 is_stmt 1 view .LVU141 454 .loc 1 444 16 is_stmt 0 view .LVU142 455 00a8 FFF7FEFF bl HAL_GetTick 456 .LVL30: 457 .loc 1 444 30 discriminator 1 view .LVU143 458 00ac 401B subs r0, r0, r5 459 .loc 1 444 14 discriminator 1 view .LVU144 460 00ae 0228 cmp r0, #2 461 00b0 F5D9 bls .L49 445:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 446:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** return HAL_TIMEOUT; 462 .loc 1 446 20 view .LVU145 463 00b2 0320 movs r0, #3 464 00b4 B4E1 b .L31 465 .LVL31: 466 .L111: 374:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 467 .loc 1 374 7 is_stmt 1 discriminator 1 view .LVU146 468 00b6 6D4A ldr r2, .L124 469 00b8 1368 ldr r3, [r2] 470 00ba 43F48033 orr r3, r3, #65536 471 00be 1360 str r3, [r2] 472 .L36: 374:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 473 .loc 1 374 7 discriminator 10 view .LVU147 377:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 474 .loc 1 377 7 view .LVU148 377:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 475 .loc 1 377 28 is_stmt 0 view .LVU149 476 00c0 6368 ldr r3, [r4, #4] 377:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 477 .loc 1 377 10 view .LVU150 478 00c2 2BB3 cbz r3, .L39 380:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 479 .loc 1 380 9 is_stmt 1 view .LVU151 380:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 480 .loc 1 380 21 is_stmt 0 view .LVU152 481 00c4 FFF7FEFF bl HAL_GetTick 482 .LVL32: 380:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 483 .loc 1 380 21 view .LVU153 484 00c8 0546 mov r5, r0 485 .LVL33: 383:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 486 .loc 1 383 9 is_stmt 1 view .LVU154 487 .L40: 383:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 488 .loc 1 383 52 view .LVU155 ARM GAS /tmp/ccemvyj9.s page 19 383:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 489 .loc 1 383 16 is_stmt 0 view .LVU156 490 00ca 684B ldr r3, .L124 491 00cc 1B68 ldr r3, [r3] 383:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 492 .loc 1 383 52 view .LVU157 493 00ce 13F4003F tst r3, #131072 494 00d2 C9D1 bne .L32 385:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 495 .loc 1 385 11 is_stmt 1 view .LVU158 385:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 496 .loc 1 385 16 is_stmt 0 view .LVU159 497 00d4 FFF7FEFF bl HAL_GetTick 498 .LVL34: 385:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 499 .loc 1 385 30 discriminator 1 view .LVU160 500 00d8 401B subs r0, r0, r5 385:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 501 .loc 1 385 14 discriminator 1 view .LVU161 502 00da 6428 cmp r0, #100 503 00dc F5D9 bls .L40 387:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } 504 .loc 1 387 20 view .LVU162 505 00de 0320 movs r0, #3 506 00e0 9EE1 b .L31 507 .LVL35: 508 .L37: 374:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 509 .loc 1 374 7 is_stmt 1 discriminator 5 view .LVU163 510 00e2 B3F5A02F cmp r3, #327680 511 00e6 09D0 beq .L115 374:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 512 .loc 1 374 7 discriminator 8 view .LVU164 513 00e8 604B ldr r3, .L124 514 00ea 1A68 ldr r2, [r3] 515 00ec 22F48032 bic r2, r2, #65536 516 00f0 1A60 str r2, [r3] 374:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 517 .loc 1 374 7 discriminator 8 view .LVU165 518 00f2 1A68 ldr r2, [r3] 519 00f4 22F48022 bic r2, r2, #262144 520 00f8 1A60 str r2, [r3] 521 00fa E1E7 b .L36 522 .L115: 374:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 523 .loc 1 374 7 discriminator 7 view .LVU166 524 00fc 5B4B ldr r3, .L124 525 00fe 1A68 ldr r2, [r3] 526 0100 42F48022 orr r2, r2, #262144 527 0104 1A60 str r2, [r3] 374:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 528 .loc 1 374 7 discriminator 7 view .LVU167 529 0106 1A68 ldr r2, [r3] 530 0108 42F48032 orr r2, r2, #65536 531 010c 1A60 str r2, [r3] 532 010e D7E7 b .L36 533 .L39: ARM GAS /tmp/ccemvyj9.s page 20 394:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 534 .loc 1 394 9 view .LVU168 394:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 535 .loc 1 394 21 is_stmt 0 view .LVU169 536 0110 FFF7FEFF bl HAL_GetTick 537 .LVL36: 394:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 538 .loc 1 394 21 view .LVU170 539 0114 0546 mov r5, r0 540 .LVL37: 397:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 541 .loc 1 397 9 is_stmt 1 view .LVU171 542 .L42: 397:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 543 .loc 1 397 52 view .LVU172 397:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 544 .loc 1 397 16 is_stmt 0 view .LVU173 545 0116 554B ldr r3, .L124 546 0118 1B68 ldr r3, [r3] 397:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 547 .loc 1 397 52 view .LVU174 548 011a 13F4003F tst r3, #131072 549 011e A3D0 beq .L32 399:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 550 .loc 1 399 11 is_stmt 1 view .LVU175 399:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 551 .loc 1 399 16 is_stmt 0 view .LVU176 552 0120 FFF7FEFF bl HAL_GetTick 553 .LVL38: 399:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 554 .loc 1 399 30 discriminator 1 view .LVU177 555 0124 401B subs r0, r0, r5 399:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 556 .loc 1 399 14 discriminator 1 view .LVU178 557 0126 6428 cmp r0, #100 558 0128 F5D9 bls .L42 401:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } 559 .loc 1 401 20 view .LVU179 560 012a 0320 movs r0, #3 561 012c 78E1 b .L31 562 .LVL39: 563 .L113: 416:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 564 .loc 1 416 87 discriminator 1 view .LVU180 565 012e 4F4B ldr r3, .L124 566 0130 5B68 ldr r3, [r3, #4] 416:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 567 .loc 1 416 79 discriminator 1 view .LVU181 568 0132 13F4800F tst r3, #4194304 569 0136 A6D1 bne .L46 570 .L45: 419:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 571 .loc 1 419 7 is_stmt 1 view .LVU182 419:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 572 .loc 1 419 12 is_stmt 0 view .LVU183 573 0138 4C4B ldr r3, .L124 574 013a 1B68 ldr r3, [r3] ARM GAS /tmp/ccemvyj9.s page 21 419:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 575 .loc 1 419 10 view .LVU184 576 013c 13F0020F tst r3, #2 577 0140 03D0 beq .L47 419:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 578 .loc 1 419 79 discriminator 1 view .LVU185 579 0142 E368 ldr r3, [r4, #12] 419:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 580 .loc 1 419 58 discriminator 1 view .LVU186 581 0144 012B cmp r3, #1 582 0146 40F06881 bne .L86 583 .L47: 427:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } 584 .loc 1 427 9 is_stmt 1 view .LVU187 585 014a 484A ldr r2, .L124 586 014c 1368 ldr r3, [r2] 587 014e 23F0F803 bic r3, r3, #248 588 0152 2169 ldr r1, [r4, #16] 589 0154 43EAC103 orr r3, r3, r1, lsl #3 590 0158 1360 str r3, [r2] 591 .L44: 447:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } 448:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } 449:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 450:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ 451:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 452:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } 453:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** else 454:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 455:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Disable the Internal High Speed oscillator (HSI). */ 456:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** __HAL_RCC_HSI_DISABLE(); 457:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 458:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Get Start Tick*/ 459:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** tickstart = HAL_GetTick(); 460:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 461:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Wait till HSI is ready */ 462:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) 463:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 464:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) 465:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 466:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** return HAL_TIMEOUT; 467:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } 468:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } 469:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } 470:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } 471:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } 472:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /*------------------------------ LSI Configuration -------------------------*/ 473:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) 592 .loc 1 473 3 view .LVU188 593 .loc 1 473 26 is_stmt 0 view .LVU189 594 015a 2368 ldr r3, [r4] 595 .loc 1 473 6 view .LVU190 596 015c 13F0080F tst r3, #8 597 0160 46D0 beq .L53 474:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 475:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Check the parameters */ 476:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState)); ARM GAS /tmp/ccemvyj9.s page 22 598 .loc 1 476 5 is_stmt 1 view .LVU191 477:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 478:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Check the LSI State */ 479:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** if ((RCC_OscInitStruct->LSIState) != RCC_LSI_OFF) 599 .loc 1 479 5 view .LVU192 600 .loc 1 479 27 is_stmt 0 view .LVU193 601 0162 6369 ldr r3, [r4, #20] 602 .loc 1 479 8 view .LVU194 603 0164 83B3 cbz r3, .L54 480:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 481:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Enable the Internal Low Speed oscillator (LSI). */ 482:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** __HAL_RCC_LSI_ENABLE(); 604 .loc 1 482 7 is_stmt 1 view .LVU195 605 0166 414A ldr r2, .L124 606 0168 536F ldr r3, [r2, #116] 607 016a 43F00103 orr r3, r3, #1 608 016e 5367 str r3, [r2, #116] 483:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 484:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Get Start Tick*/ 485:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** tickstart = HAL_GetTick(); 609 .loc 1 485 7 view .LVU196 610 .loc 1 485 19 is_stmt 0 view .LVU197 611 0170 FFF7FEFF bl HAL_GetTick 612 .LVL40: 613 0174 0546 mov r5, r0 614 .LVL41: 486:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 487:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Wait till LSI is ready */ 488:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET) 615 .loc 1 488 7 is_stmt 1 view .LVU198 616 .L55: 617 .loc 1 488 50 view .LVU199 618 .loc 1 488 14 is_stmt 0 view .LVU200 619 0176 3D4B ldr r3, .L124 620 0178 5B6F ldr r3, [r3, #116] 621 .loc 1 488 50 view .LVU201 622 017a 13F0020F tst r3, #2 623 017e 37D1 bne .L53 489:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 490:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) 624 .loc 1 490 9 is_stmt 1 view .LVU202 625 .loc 1 490 14 is_stmt 0 view .LVU203 626 0180 FFF7FEFF bl HAL_GetTick 627 .LVL42: 628 .loc 1 490 28 discriminator 1 view .LVU204 629 0184 401B subs r0, r0, r5 630 .loc 1 490 12 discriminator 1 view .LVU205 631 0186 0228 cmp r0, #2 632 0188 F5D9 bls .L55 491:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 492:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** return HAL_TIMEOUT; 633 .loc 1 492 18 view .LVU206 634 018a 0320 movs r0, #3 635 018c 48E1 b .L31 636 .L114: 451:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } 637 .loc 1 451 9 is_stmt 1 view .LVU207 ARM GAS /tmp/ccemvyj9.s page 23 638 018e 374A ldr r2, .L124 639 0190 1368 ldr r3, [r2] 640 0192 23F0F803 bic r3, r3, #248 641 0196 2169 ldr r1, [r4, #16] 642 0198 43EAC103 orr r3, r3, r1, lsl #3 643 019c 1360 str r3, [r2] 644 019e DCE7 b .L44 645 .LVL43: 646 .L48: 456:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 647 .loc 1 456 9 view .LVU208 648 01a0 324A ldr r2, .L124 649 01a2 1368 ldr r3, [r2] 650 01a4 23F00103 bic r3, r3, #1 651 01a8 1360 str r3, [r2] 459:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 652 .loc 1 459 9 view .LVU209 459:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 653 .loc 1 459 21 is_stmt 0 view .LVU210 654 01aa FFF7FEFF bl HAL_GetTick 655 .LVL44: 656 01ae 0546 mov r5, r0 657 .LVL45: 462:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 658 .loc 1 462 9 is_stmt 1 view .LVU211 659 .L51: 462:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 660 .loc 1 462 52 view .LVU212 462:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 661 .loc 1 462 16 is_stmt 0 view .LVU213 662 01b0 2E4B ldr r3, .L124 663 01b2 1B68 ldr r3, [r3] 462:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 664 .loc 1 462 52 view .LVU214 665 01b4 13F0020F tst r3, #2 666 01b8 CFD0 beq .L44 464:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 667 .loc 1 464 11 is_stmt 1 view .LVU215 464:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 668 .loc 1 464 16 is_stmt 0 view .LVU216 669 01ba FFF7FEFF bl HAL_GetTick 670 .LVL46: 464:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 671 .loc 1 464 30 discriminator 1 view .LVU217 672 01be 401B subs r0, r0, r5 464:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 673 .loc 1 464 14 discriminator 1 view .LVU218 674 01c0 0228 cmp r0, #2 675 01c2 F5D9 bls .L51 466:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } 676 .loc 1 466 20 view .LVU219 677 01c4 0320 movs r0, #3 678 01c6 2BE1 b .L31 679 .LVL47: 680 .L54: 493:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } 494:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } ARM GAS /tmp/ccemvyj9.s page 24 495:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } 496:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** else 497:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 498:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Disable the Internal Low Speed oscillator (LSI). */ 499:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** __HAL_RCC_LSI_DISABLE(); 681 .loc 1 499 7 is_stmt 1 view .LVU220 682 01c8 284A ldr r2, .L124 683 01ca 536F ldr r3, [r2, #116] 684 01cc 23F00103 bic r3, r3, #1 685 01d0 5367 str r3, [r2, #116] 500:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 501:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Get Start Tick*/ 502:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** tickstart = HAL_GetTick(); 686 .loc 1 502 7 view .LVU221 687 .loc 1 502 19 is_stmt 0 view .LVU222 688 01d2 FFF7FEFF bl HAL_GetTick 689 .LVL48: 690 01d6 0546 mov r5, r0 691 .LVL49: 503:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 504:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Wait till LSI is ready */ 505:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET) 692 .loc 1 505 7 is_stmt 1 view .LVU223 693 .L57: 694 .loc 1 505 50 view .LVU224 695 .loc 1 505 14 is_stmt 0 view .LVU225 696 01d8 244B ldr r3, .L124 697 01da 5B6F ldr r3, [r3, #116] 698 .loc 1 505 50 view .LVU226 699 01dc 13F0020F tst r3, #2 700 01e0 06D0 beq .L53 506:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 507:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) 701 .loc 1 507 9 is_stmt 1 view .LVU227 702 .loc 1 507 14 is_stmt 0 view .LVU228 703 01e2 FFF7FEFF bl HAL_GetTick 704 .LVL50: 705 .loc 1 507 28 discriminator 1 view .LVU229 706 01e6 401B subs r0, r0, r5 707 .loc 1 507 12 discriminator 1 view .LVU230 708 01e8 0228 cmp r0, #2 709 01ea F5D9 bls .L57 508:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 509:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** return HAL_TIMEOUT; 710 .loc 1 509 18 view .LVU231 711 01ec 0320 movs r0, #3 712 01ee 17E1 b .L31 713 .LVL51: 714 .L53: 510:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } 511:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } 512:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } 513:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } 514:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /*------------------------------ LSE Configuration -------------------------*/ 515:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) 715 .loc 1 515 3 is_stmt 1 view .LVU232 716 .loc 1 515 26 is_stmt 0 view .LVU233 ARM GAS /tmp/ccemvyj9.s page 25 717 01f0 2368 ldr r3, [r4] 718 .loc 1 515 6 view .LVU234 719 01f2 13F0040F tst r3, #4 720 01f6 7DD0 beq .L59 516:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 517:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Check the parameters */ 518:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState)); 721 .loc 1 518 5 is_stmt 1 view .LVU235 519:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 520:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Update LSE configuration in Backup Domain control register */ 521:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Requires to enable write access to Backup Domain of necessary */ 522:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** if (__HAL_RCC_PWR_IS_CLK_DISABLED()) 722 .loc 1 522 5 view .LVU236 723 .loc 1 522 9 is_stmt 0 view .LVU237 724 01f8 1C4B ldr r3, .L124 725 01fa 1B6C ldr r3, [r3, #64] 726 .loc 1 522 8 view .LVU238 727 01fc 13F0805F tst r3, #268435456 728 0200 1ED1 bne .L91 523:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 524:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Enable Power Clock*/ 525:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** __HAL_RCC_PWR_CLK_ENABLE(); 729 .loc 1 525 7 is_stmt 1 view .LVU239 730 .LBB4: 731 .loc 1 525 7 view .LVU240 732 .loc 1 525 7 view .LVU241 733 0202 1A4B ldr r3, .L124 734 0204 1A6C ldr r2, [r3, #64] 735 0206 42F08052 orr r2, r2, #268435456 736 020a 1A64 str r2, [r3, #64] 737 .loc 1 525 7 view .LVU242 738 020c 1B6C ldr r3, [r3, #64] 739 020e 03F08053 and r3, r3, #268435456 740 0212 0193 str r3, [sp, #4] 741 .loc 1 525 7 view .LVU243 742 0214 019B ldr r3, [sp, #4] 743 .LBE4: 744 .loc 1 525 7 view .LVU244 526:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** pwrclkchanged = SET; 745 .loc 1 526 7 view .LVU245 746 .LVL52: 747 .loc 1 526 21 is_stmt 0 view .LVU246 748 0216 0125 movs r5, #1 749 .LVL53: 750 .L60: 527:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } 528:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 529:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** if (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP)) 751 .loc 1 529 5 is_stmt 1 view .LVU247 752 .loc 1 529 9 is_stmt 0 view .LVU248 753 0218 154B ldr r3, .L124+4 754 021a 1B68 ldr r3, [r3] 755 .loc 1 529 8 view .LVU249 756 021c 13F4807F tst r3, #256 757 0220 10D0 beq .L116 758 .L61: 530:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { ARM GAS /tmp/ccemvyj9.s page 26 531:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Enable write access to Backup domain */ 532:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** PWR->CR1 |= PWR_CR1_DBP; 533:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 534:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Wait for Backup domain Write protection disable */ 535:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** tickstart = HAL_GetTick(); 536:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 537:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** while (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP)) 538:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 539:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) 540:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 541:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** return HAL_TIMEOUT; 542:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } 543:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } 544:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } 545:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 546:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Set the new LSE configuration -----------------------------------------*/ 547:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); 759 .loc 1 547 5 is_stmt 1 view .LVU250 760 .loc 1 547 5 view .LVU251 761 0222 A368 ldr r3, [r4, #8] 762 0224 012B cmp r3, #1 763 0226 25D0 beq .L117 764 .loc 1 547 5 discriminator 2 view .LVU252 765 0228 002B cmp r3, #0 766 022a 3BD1 bne .L66 767 .loc 1 547 5 discriminator 4 view .LVU253 768 022c 0F4B ldr r3, .L124 769 022e 1A6F ldr r2, [r3, #112] 770 0230 22F00102 bic r2, r2, #1 771 0234 1A67 str r2, [r3, #112] 772 .loc 1 547 5 discriminator 4 view .LVU254 773 0236 1A6F ldr r2, [r3, #112] 774 0238 22F00402 bic r2, r2, #4 775 023c 1A67 str r2, [r3, #112] 776 023e 1EE0 b .L65 777 .LVL54: 778 .L91: 346:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 779 .loc 1 346 14 is_stmt 0 view .LVU255 780 0240 0025 movs r5, #0 781 0242 E9E7 b .L60 782 .LVL55: 783 .L116: 532:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 784 .loc 1 532 7 is_stmt 1 view .LVU256 532:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 785 .loc 1 532 10 is_stmt 0 view .LVU257 786 0244 0A4A ldr r2, .L124+4 787 0246 1368 ldr r3, [r2] 532:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 788 .loc 1 532 16 view .LVU258 789 0248 43F48073 orr r3, r3, #256 790 024c 1360 str r3, [r2] 535:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 791 .loc 1 535 7 is_stmt 1 view .LVU259 535:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 792 .loc 1 535 19 is_stmt 0 view .LVU260 ARM GAS /tmp/ccemvyj9.s page 27 793 024e FFF7FEFF bl HAL_GetTick 794 .LVL56: 795 0252 0646 mov r6, r0 796 .LVL57: 537:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 797 .loc 1 537 7 is_stmt 1 view .LVU261 798 .L62: 537:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 799 .loc 1 537 14 view .LVU262 800 0254 064B ldr r3, .L124+4 801 0256 1B68 ldr r3, [r3] 802 0258 13F4807F tst r3, #256 803 025c E1D1 bne .L61 539:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 804 .loc 1 539 9 view .LVU263 539:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 805 .loc 1 539 14 is_stmt 0 view .LVU264 806 025e FFF7FEFF bl HAL_GetTick 807 .LVL58: 539:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 808 .loc 1 539 28 discriminator 1 view .LVU265 809 0262 801B subs r0, r0, r6 539:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 810 .loc 1 539 12 discriminator 1 view .LVU266 811 0264 6428 cmp r0, #100 812 0266 F5D9 bls .L62 541:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } 813 .loc 1 541 18 view .LVU267 814 0268 0320 movs r0, #3 815 026a D9E0 b .L31 816 .L125: 817 .align 2 818 .L124: 819 026c 00380240 .word 1073887232 820 0270 00700040 .word 1073770496 821 .LVL59: 822 .L117: 823 .loc 1 547 5 is_stmt 1 discriminator 1 view .LVU268 824 0274 724A ldr r2, .L126 825 0276 136F ldr r3, [r2, #112] 826 0278 43F00103 orr r3, r3, #1 827 027c 1367 str r3, [r2, #112] 828 .L65: 829 .loc 1 547 5 discriminator 10 view .LVU269 548:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Check the LSE State */ 549:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** if ((RCC_OscInitStruct->LSEState) != RCC_LSE_OFF) 830 .loc 1 549 5 view .LVU270 831 .loc 1 549 27 is_stmt 0 view .LVU271 832 027e A368 ldr r3, [r4, #8] 833 .loc 1 549 8 view .LVU272 834 0280 33B3 cbz r3, .L68 550:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 551:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Get Start Tick*/ 552:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** tickstart = HAL_GetTick(); 835 .loc 1 552 7 is_stmt 1 view .LVU273 836 .loc 1 552 19 is_stmt 0 view .LVU274 837 0282 FFF7FEFF bl HAL_GetTick ARM GAS /tmp/ccemvyj9.s page 28 838 .LVL60: 839 0286 0646 mov r6, r0 840 .LVL61: 553:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 554:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Wait till LSE is ready */ 555:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) 841 .loc 1 555 7 is_stmt 1 view .LVU275 842 .L69: 843 .loc 1 555 50 view .LVU276 844 .loc 1 555 14 is_stmt 0 view .LVU277 845 0288 6D4B ldr r3, .L126 846 028a 1B6F ldr r3, [r3, #112] 847 .loc 1 555 50 view .LVU278 848 028c 13F0020F tst r3, #2 849 0290 2FD1 bne .L71 556:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 557:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 850 .loc 1 557 9 is_stmt 1 view .LVU279 851 .loc 1 557 14 is_stmt 0 view .LVU280 852 0292 FFF7FEFF bl HAL_GetTick 853 .LVL62: 854 .loc 1 557 28 discriminator 1 view .LVU281 855 0296 801B subs r0, r0, r6 856 .loc 1 557 12 discriminator 1 view .LVU282 857 0298 41F28833 movw r3, #5000 858 029c 9842 cmp r0, r3 859 029e F3D9 bls .L69 558:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 559:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** return HAL_TIMEOUT; 860 .loc 1 559 18 view .LVU283 861 02a0 0320 movs r0, #3 862 02a2 BDE0 b .L31 863 .LVL63: 864 .L66: 547:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Check the LSE State */ 865 .loc 1 547 5 is_stmt 1 discriminator 5 view .LVU284 866 02a4 052B cmp r3, #5 867 02a6 09D0 beq .L118 547:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Check the LSE State */ 868 .loc 1 547 5 discriminator 8 view .LVU285 869 02a8 654B ldr r3, .L126 870 02aa 1A6F ldr r2, [r3, #112] 871 02ac 22F00102 bic r2, r2, #1 872 02b0 1A67 str r2, [r3, #112] 547:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Check the LSE State */ 873 .loc 1 547 5 discriminator 8 view .LVU286 874 02b2 1A6F ldr r2, [r3, #112] 875 02b4 22F00402 bic r2, r2, #4 876 02b8 1A67 str r2, [r3, #112] 877 02ba E0E7 b .L65 878 .L118: 547:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Check the LSE State */ 879 .loc 1 547 5 discriminator 7 view .LVU287 880 02bc 604B ldr r3, .L126 881 02be 1A6F ldr r2, [r3, #112] 882 02c0 42F00402 orr r2, r2, #4 883 02c4 1A67 str r2, [r3, #112] ARM GAS /tmp/ccemvyj9.s page 29 547:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Check the LSE State */ 884 .loc 1 547 5 discriminator 7 view .LVU288 885 02c6 1A6F ldr r2, [r3, #112] 886 02c8 42F00102 orr r2, r2, #1 887 02cc 1A67 str r2, [r3, #112] 888 02ce D6E7 b .L65 889 .L68: 560:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } 561:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } 562:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } 563:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** else 564:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 565:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Get Start Tick*/ 566:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** tickstart = HAL_GetTick(); 890 .loc 1 566 7 view .LVU289 891 .loc 1 566 19 is_stmt 0 view .LVU290 892 02d0 FFF7FEFF bl HAL_GetTick 893 .LVL64: 894 02d4 0646 mov r6, r0 895 .LVL65: 567:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 568:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Wait till LSE is ready */ 569:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) 896 .loc 1 569 7 is_stmt 1 view .LVU291 897 .L72: 898 .loc 1 569 50 view .LVU292 899 .loc 1 569 14 is_stmt 0 view .LVU293 900 02d6 5A4B ldr r3, .L126 901 02d8 1B6F ldr r3, [r3, #112] 902 .loc 1 569 50 view .LVU294 903 02da 13F0020F tst r3, #2 904 02de 08D0 beq .L71 570:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 571:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 905 .loc 1 571 9 is_stmt 1 view .LVU295 906 .loc 1 571 14 is_stmt 0 view .LVU296 907 02e0 FFF7FEFF bl HAL_GetTick 908 .LVL66: 909 .loc 1 571 28 discriminator 1 view .LVU297 910 02e4 801B subs r0, r0, r6 911 .loc 1 571 12 discriminator 1 view .LVU298 912 02e6 41F28833 movw r3, #5000 913 02ea 9842 cmp r0, r3 914 02ec F3D9 bls .L72 572:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 573:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** return HAL_TIMEOUT; 915 .loc 1 573 18 view .LVU299 916 02ee 0320 movs r0, #3 917 02f0 96E0 b .L31 918 .L71: 574:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } 575:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } 576:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } 577:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 578:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Restore clock configuration if changed */ 579:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** if (pwrclkchanged == SET) 919 .loc 1 579 5 is_stmt 1 view .LVU300 ARM GAS /tmp/ccemvyj9.s page 30 920 .loc 1 579 8 is_stmt 0 view .LVU301 921 02f2 FDB9 cbnz r5, .L119 922 .LVL67: 923 .L59: 580:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 581:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** __HAL_RCC_PWR_CLK_DISABLE(); 582:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } 583:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } 584:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /*-------------------------------- PLL Configuration -----------------------*/ 585:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Check the parameters */ 586:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState)); 924 .loc 1 586 3 is_stmt 1 view .LVU302 587:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE) 925 .loc 1 587 3 view .LVU303 926 .loc 1 587 30 is_stmt 0 view .LVU304 927 02f4 A369 ldr r3, [r4, #24] 928 .loc 1 587 6 view .LVU305 929 02f6 002B cmp r3, #0 930 02f8 00F09180 beq .L95 588:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 589:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Check if the PLL is used as system clock or not */ 590:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** if (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK) 931 .loc 1 590 5 is_stmt 1 view .LVU306 932 .loc 1 590 9 is_stmt 0 view .LVU307 933 02fc 504A ldr r2, .L126 934 02fe 9268 ldr r2, [r2, #8] 935 0300 02F00C02 and r2, r2, #12 936 .loc 1 590 8 view .LVU308 937 0304 082A cmp r2, #8 938 0306 59D0 beq .L74 591:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 592:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON) 939 .loc 1 592 7 is_stmt 1 view .LVU309 940 .loc 1 592 10 is_stmt 0 view .LVU310 941 0308 022B cmp r3, #2 942 030a 19D0 beq .L120 593:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 594:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Check the parameters */ 595:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource)); 596:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** assert_param(IS_RCC_PLLM_VALUE(RCC_OscInitStruct->PLL.PLLM)); 597:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** assert_param(IS_RCC_PLLN_VALUE(RCC_OscInitStruct->PLL.PLLN)); 598:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP)); 599:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ)); 600:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** #if defined (RCC_PLLCFGR_PLLR) 601:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR)); 602:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** #endif 603:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 604:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Disable the main PLL. */ 605:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** __HAL_RCC_PLL_DISABLE(); 606:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 607:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Get Start Tick*/ 608:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** tickstart = HAL_GetTick(); 609:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 610:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Wait till PLL is ready */ 611:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) 612:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 613:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) ARM GAS /tmp/ccemvyj9.s page 31 614:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 615:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** return HAL_TIMEOUT; 616:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } 617:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } 618:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 619:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Configure the main PLL clock source, multiplication and division factors. */ 620:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** #if defined (RCC_PLLCFGR_PLLR) 621:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource, 622:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** RCC_OscInitStruct->PLL.PLLM, 623:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** RCC_OscInitStruct->PLL.PLLN, 624:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** RCC_OscInitStruct->PLL.PLLP, 625:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** RCC_OscInitStruct->PLL.PLLQ, 626:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** RCC_OscInitStruct->PLL.PLLR); 627:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** #else 628:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource, 629:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** RCC_OscInitStruct->PLL.PLLM, 630:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** RCC_OscInitStruct->PLL.PLLN, 631:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** RCC_OscInitStruct->PLL.PLLP, 632:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** RCC_OscInitStruct->PLL.PLLQ); 633:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** #endif 634:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 635:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Enable the main PLL. */ 636:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** __HAL_RCC_PLL_ENABLE(); 637:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 638:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Get Start Tick*/ 639:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** tickstart = HAL_GetTick(); 640:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 641:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Wait till PLL is ready */ 642:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) 643:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 644:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 645:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 646:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** return HAL_TIMEOUT; 647:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } 648:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } 649:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } 650:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** else 651:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 652:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Disable the main PLL. */ 653:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** __HAL_RCC_PLL_DISABLE(); 943 .loc 1 653 9 is_stmt 1 view .LVU311 944 030c 4C4A ldr r2, .L126 945 030e 1368 ldr r3, [r2] 946 0310 23F08073 bic r3, r3, #16777216 947 0314 1360 str r3, [r2] 654:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 655:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Get Start Tick*/ 656:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** tickstart = HAL_GetTick(); 948 .loc 1 656 9 view .LVU312 949 .loc 1 656 21 is_stmt 0 view .LVU313 950 0316 FFF7FEFF bl HAL_GetTick 951 .LVL68: 952 031a 0446 mov r4, r0 953 .LVL69: 657:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 658:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Wait till PLL is ready */ 659:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) ARM GAS /tmp/ccemvyj9.s page 32 954 .loc 1 659 9 is_stmt 1 view .LVU314 955 .L80: 956 .loc 1 659 52 view .LVU315 957 .loc 1 659 16 is_stmt 0 view .LVU316 958 031c 484B ldr r3, .L126 959 031e 1B68 ldr r3, [r3] 960 .loc 1 659 52 view .LVU317 961 0320 13F0007F tst r3, #33554432 962 0324 48D0 beq .L121 660:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 661:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 963 .loc 1 661 11 is_stmt 1 view .LVU318 964 .loc 1 661 16 is_stmt 0 view .LVU319 965 0326 FFF7FEFF bl HAL_GetTick 966 .LVL70: 967 .loc 1 661 30 discriminator 1 view .LVU320 968 032a 001B subs r0, r0, r4 969 .loc 1 661 14 discriminator 1 view .LVU321 970 032c 0228 cmp r0, #2 971 032e F5D9 bls .L80 662:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 663:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** return HAL_TIMEOUT; 972 .loc 1 663 20 view .LVU322 973 0330 0320 movs r0, #3 974 0332 75E0 b .L31 975 .LVL71: 976 .L119: 581:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } 977 .loc 1 581 7 is_stmt 1 view .LVU323 978 0334 424A ldr r2, .L126 979 0336 136C ldr r3, [r2, #64] 980 0338 23F08053 bic r3, r3, #268435456 981 033c 1364 str r3, [r2, #64] 982 033e D9E7 b .L59 983 .LVL72: 984 .L120: 595:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** assert_param(IS_RCC_PLLM_VALUE(RCC_OscInitStruct->PLL.PLLM)); 985 .loc 1 595 9 view .LVU324 596:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** assert_param(IS_RCC_PLLN_VALUE(RCC_OscInitStruct->PLL.PLLN)); 986 .loc 1 596 9 view .LVU325 597:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP)); 987 .loc 1 597 9 view .LVU326 598:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ)); 988 .loc 1 598 9 view .LVU327 599:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** #if defined (RCC_PLLCFGR_PLLR) 989 .loc 1 599 9 view .LVU328 601:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** #endif 990 .loc 1 601 9 view .LVU329 605:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 991 .loc 1 605 9 view .LVU330 992 0340 3F4A ldr r2, .L126 993 0342 1368 ldr r3, [r2] 994 0344 23F08073 bic r3, r3, #16777216 995 0348 1360 str r3, [r2] 608:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 996 .loc 1 608 9 view .LVU331 608:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** ARM GAS /tmp/ccemvyj9.s page 33 997 .loc 1 608 21 is_stmt 0 view .LVU332 998 034a FFF7FEFF bl HAL_GetTick 999 .LVL73: 1000 034e 0546 mov r5, r0 1001 .LVL74: 611:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 1002 .loc 1 611 9 is_stmt 1 view .LVU333 1003 .L76: 611:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 1004 .loc 1 611 52 view .LVU334 611:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 1005 .loc 1 611 16 is_stmt 0 view .LVU335 1006 0350 3B4B ldr r3, .L126 1007 0352 1B68 ldr r3, [r3] 611:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 1008 .loc 1 611 52 view .LVU336 1009 0354 13F0007F tst r3, #33554432 1010 0358 06D0 beq .L122 613:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 1011 .loc 1 613 11 is_stmt 1 view .LVU337 613:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 1012 .loc 1 613 16 is_stmt 0 view .LVU338 1013 035a FFF7FEFF bl HAL_GetTick 1014 .LVL75: 613:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 1015 .loc 1 613 30 discriminator 1 view .LVU339 1016 035e 401B subs r0, r0, r5 613:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 1017 .loc 1 613 14 discriminator 1 view .LVU340 1018 0360 0228 cmp r0, #2 1019 0362 F5D9 bls .L76 615:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } 1020 .loc 1 615 20 view .LVU341 1021 0364 0320 movs r0, #3 1022 0366 5BE0 b .L31 1023 .L122: 621:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** RCC_OscInitStruct->PLL.PLLM, 1024 .loc 1 621 9 is_stmt 1 view .LVU342 1025 0368 E369 ldr r3, [r4, #28] 1026 036a 226A ldr r2, [r4, #32] 1027 036c 1343 orrs r3, r3, r2 1028 036e 626A ldr r2, [r4, #36] 1029 0370 43EA8213 orr r3, r3, r2, lsl #6 1030 0374 A26A ldr r2, [r4, #40] 1031 0376 5208 lsrs r2, r2, #1 1032 0378 013A subs r2, r2, #1 1033 037a 43EA0243 orr r3, r3, r2, lsl #16 1034 037e E26A ldr r2, [r4, #44] 1035 0380 43EA0263 orr r3, r3, r2, lsl #24 1036 0384 226B ldr r2, [r4, #48] 1037 0386 43EA0273 orr r3, r3, r2, lsl #28 1038 038a 2D4A ldr r2, .L126 1039 038c 5360 str r3, [r2, #4] 636:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 1040 .loc 1 636 9 view .LVU343 1041 038e 1368 ldr r3, [r2] 1042 0390 43F08073 orr r3, r3, #16777216 ARM GAS /tmp/ccemvyj9.s page 34 1043 0394 1360 str r3, [r2] 639:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 1044 .loc 1 639 9 view .LVU344 639:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 1045 .loc 1 639 21 is_stmt 0 view .LVU345 1046 0396 FFF7FEFF bl HAL_GetTick 1047 .LVL76: 1048 039a 0446 mov r4, r0 1049 .LVL77: 642:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 1050 .loc 1 642 9 is_stmt 1 view .LVU346 1051 .L78: 642:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 1052 .loc 1 642 52 view .LVU347 642:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 1053 .loc 1 642 16 is_stmt 0 view .LVU348 1054 039c 284B ldr r3, .L126 1055 039e 1B68 ldr r3, [r3] 642:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 1056 .loc 1 642 52 view .LVU349 1057 03a0 13F0007F tst r3, #33554432 1058 03a4 06D1 bne .L123 644:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 1059 .loc 1 644 11 is_stmt 1 view .LVU350 644:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 1060 .loc 1 644 16 is_stmt 0 view .LVU351 1061 03a6 FFF7FEFF bl HAL_GetTick 1062 .LVL78: 644:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 1063 .loc 1 644 30 discriminator 1 view .LVU352 1064 03aa 001B subs r0, r0, r4 644:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 1065 .loc 1 644 14 discriminator 1 view .LVU353 1066 03ac 0228 cmp r0, #2 1067 03ae F5D9 bls .L78 646:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } 1068 .loc 1 646 20 view .LVU354 1069 03b0 0320 movs r0, #3 1070 03b2 35E0 b .L31 1071 .L123: 664:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } 665:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } 666:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } 667:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } 668:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** else 669:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 670:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Do not return HAL_ERROR if request repeats the current configuration */ 671:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** pll_config = RCC->PLLCFGR; 672:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** #if defined (RCC_PLLCFGR_PLLR) 673:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) || 674:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** (READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || 675:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** (READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != RCC_OscInitStruct->PLL.PLLM) || 676:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** (READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PL 677:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** (READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != ((((RCC_OscInitStruct->PLL.PLLP) >> 1U) - 1U) 678:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** (READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PL 679:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** (READ_BIT(pll_config, RCC_PLLCFGR_PLLR) != (RCC_OscInitStruct->PLL.PLLR << RCC_PLLCFGR_PL 680:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** #else ARM GAS /tmp/ccemvyj9.s page 35 681:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) || 682:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** (READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || 683:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** (READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != RCC_OscInitStruct->PLL.PLLM) || 684:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** (READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PL 685:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** (READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != ((((RCC_OscInitStruct->PLL.PLLP) >> 1U) - 1U) 686:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** (READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PL 687:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** #endif 688:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 689:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** return HAL_ERROR; 690:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } 691:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } 692:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } 693:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** return HAL_OK; 1072 .loc 1 693 10 view .LVU355 1073 03b4 0020 movs r0, #0 1074 03b6 33E0 b .L31 1075 .L121: 1076 .loc 1 693 10 view .LVU356 1077 03b8 0020 movs r0, #0 1078 03ba 31E0 b .L31 1079 .LVL79: 1080 .L74: 671:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** #if defined (RCC_PLLCFGR_PLLR) 1081 .loc 1 671 7 is_stmt 1 view .LVU357 671:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** #if defined (RCC_PLLCFGR_PLLR) 1082 .loc 1 671 18 is_stmt 0 view .LVU358 1083 03bc 204A ldr r2, .L126 1084 03be 5268 ldr r2, [r2, #4] 1085 .LVL80: 673:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** (READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || 1086 .loc 1 673 7 is_stmt 1 view .LVU359 673:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** (READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || 1087 .loc 1 673 10 is_stmt 0 view .LVU360 1088 03c0 012B cmp r3, #1 1089 03c2 2FD0 beq .L99 674:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** (READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != RCC_OscInitStruct->PLL.PLLM) || 1090 .loc 1 674 12 view .LVU361 1091 03c4 02F48003 and r3, r2, #4194304 674:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** (READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != RCC_OscInitStruct->PLL.PLLM) || 1092 .loc 1 674 78 view .LVU362 1093 03c8 E169 ldr r1, [r4, #28] 673:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** (READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || 1094 .loc 1 673 62 discriminator 1 view .LVU363 1095 03ca 8B42 cmp r3, r1 1096 03cc 2CD1 bne .L100 675:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** (READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PL 1097 .loc 1 675 12 view .LVU364 1098 03ce 02F03F03 and r3, r2, #63 675:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** (READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PL 1099 .loc 1 675 76 view .LVU365 1100 03d2 216A ldr r1, [r4, #32] 674:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** (READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != RCC_OscInitStruct->PLL.PLLM) || 1101 .loc 1 674 90 view .LVU366 1102 03d4 8B42 cmp r3, r1 1103 03d6 29D1 bne .L101 676:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** (READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != ((((RCC_OscInitStruct->PLL.PLLP) >> 1U) - 1U) 1104 .loc 1 676 77 view .LVU367 ARM GAS /tmp/ccemvyj9.s page 36 1105 03d8 616A ldr r1, [r4, #36] 675:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** (READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PL 1106 .loc 1 675 83 view .LVU368 1107 03da 47F6C073 movw r3, #32704 1108 03de 1340 ands r3, r3, r2 1109 03e0 B3EB811F cmp r3, r1, lsl #6 1110 03e4 24D1 bne .L102 677:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** (READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PL 1111 .loc 1 677 12 view .LVU369 1112 03e6 02F44031 and r1, r2, #196608 677:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** (READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PL 1113 .loc 1 677 80 view .LVU370 1114 03ea A36A ldr r3, [r4, #40] 677:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** (READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PL 1115 .loc 1 677 87 view .LVU371 1116 03ec 5B08 lsrs r3, r3, #1 677:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** (READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PL 1117 .loc 1 677 94 view .LVU372 1118 03ee 013B subs r3, r3, #1 676:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** (READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != ((((RCC_OscInitStruct->PLL.PLLP) >> 1U) - 1U) 1119 .loc 1 676 109 view .LVU373 1120 03f0 B1EB034F cmp r1, r3, lsl #16 1121 03f4 1ED1 bne .L103 678:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** (READ_BIT(pll_config, RCC_PLLCFGR_PLLR) != (RCC_OscInitStruct->PLL.PLLR << RCC_PLLCFGR_PL 1122 .loc 1 678 12 view .LVU374 1123 03f6 02F07063 and r3, r2, #251658240 678:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** (READ_BIT(pll_config, RCC_PLLCFGR_PLLR) != (RCC_OscInitStruct->PLL.PLLR << RCC_PLLCFGR_PL 1124 .loc 1 678 77 view .LVU375 1125 03fa E16A ldr r1, [r4, #44] 677:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** (READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PL 1126 .loc 1 677 126 view .LVU376 1127 03fc B3EB016F cmp r3, r1, lsl #24 1128 0400 1AD1 bne .L104 679:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** #else 1129 .loc 1 679 12 view .LVU377 1130 0402 02F0E042 and r2, r2, #1879048192 1131 .LVL81: 679:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** #else 1132 .loc 1 679 77 view .LVU378 1133 0406 236B ldr r3, [r4, #48] 678:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** (READ_BIT(pll_config, RCC_PLLCFGR_PLLR) != (RCC_OscInitStruct->PLL.PLLR << RCC_PLLCFGR_PL 1134 .loc 1 678 109 view .LVU379 1135 0408 B2EB037F cmp r2, r3, lsl #28 1136 040c 16D1 bne .L105 1137 .loc 1 693 10 view .LVU380 1138 040e 0020 movs r0, #0 1139 0410 06E0 b .L31 1140 .LVL82: 1141 .L82: 1142 .LCFI3: 1143 .cfi_def_cfa_offset 0 1144 .cfi_restore 4 1145 .cfi_restore 5 1146 .cfi_restore 6 1147 .cfi_restore 14 351:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } 1148 .loc 1 351 12 view .LVU381 ARM GAS /tmp/ccemvyj9.s page 37 1149 0412 0120 movs r0, #1 1150 .LVL83: 694:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } 1151 .loc 1 694 1 view .LVU382 1152 0414 7047 bx lr 1153 .LVL84: 1154 .L112: 1155 .LCFI4: 1156 .cfi_def_cfa_offset 24 1157 .cfi_offset 4, -16 1158 .cfi_offset 5, -12 1159 .cfi_offset 6, -8 1160 .cfi_offset 14, -4 368:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } 1161 .loc 1 368 16 view .LVU383 1162 0416 0120 movs r0, #1 1163 .LVL85: 368:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } 1164 .loc 1 368 16 view .LVU384 1165 0418 02E0 b .L31 1166 .L86: 421:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } 1167 .loc 1 421 16 view .LVU385 1168 041a 0120 movs r0, #1 1169 041c 00E0 b .L31 1170 .LVL86: 1171 .L95: 693:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } 1172 .loc 1 693 10 view .LVU386 1173 041e 0020 movs r0, #0 1174 .LVL87: 1175 .L31: 1176 .loc 1 694 1 view .LVU387 1177 0420 02B0 add sp, sp, #8 1178 .LCFI5: 1179 .cfi_remember_state 1180 .cfi_def_cfa_offset 16 1181 @ sp needed 1182 0422 70BD pop {r4, r5, r6, pc} 1183 .LVL88: 1184 .L99: 1185 .LCFI6: 1186 .cfi_restore_state 689:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } 1187 .loc 1 689 16 view .LVU388 1188 0424 0120 movs r0, #1 1189 0426 FBE7 b .L31 1190 .L100: 689:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } 1191 .loc 1 689 16 view .LVU389 1192 0428 0120 movs r0, #1 1193 042a F9E7 b .L31 1194 .L101: 1195 042c 0120 movs r0, #1 1196 042e F7E7 b .L31 1197 .L102: 1198 0430 0120 movs r0, #1 ARM GAS /tmp/ccemvyj9.s page 38 1199 0432 F5E7 b .L31 1200 .L103: 1201 0434 0120 movs r0, #1 1202 0436 F3E7 b .L31 1203 .L104: 1204 0438 0120 movs r0, #1 1205 043a F1E7 b .L31 1206 .LVL89: 1207 .L105: 689:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } 1208 .loc 1 689 16 view .LVU390 1209 043c 0120 movs r0, #1 1210 043e EFE7 b .L31 1211 .L127: 1212 .align 2 1213 .L126: 1214 0440 00380240 .word 1073887232 1215 .cfi_endproc 1216 .LFE142: 1218 .section .text.HAL_RCC_MCOConfig,"ax",%progbits 1219 .align 1 1220 .global HAL_RCC_MCOConfig 1221 .syntax unified 1222 .thumb 1223 .thumb_func 1225 HAL_RCC_MCOConfig: 1226 .LVL90: 1227 .LFB144: 695:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 696:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /** 697:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * @brief Initializes the CPU, AHB and APB buses clocks according to the specified 698:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * parameters in the RCC_ClkInitStruct. 699:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * @param RCC_ClkInitStruct pointer to an RCC_OscInitTypeDef structure that 700:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * contains the configuration information for the RCC peripheral. 701:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * @param FLatency FLASH Latency, this parameter depend on device selected 702:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * 703:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency 704:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * and updated by HAL_RCC_GetHCLKFreq() function called within this function 705:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * 706:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * @note The HSI is used (enabled by hardware) as system clock source after 707:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * startup from Reset, wake-up from STOP and STANDBY mode, or in case 708:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * of failure of the HSE used directly or indirectly as system clock 709:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * (if the Clock Security System CSS is enabled). 710:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * 711:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * @note A switch from one clock source to another occurs only if the target 712:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * clock source is ready (clock stable after startup delay or PLL locked). 713:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * If a clock source which is not yet ready is selected, the switch will 714:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * occur when the clock source will be ready. 715:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * You can use HAL_RCC_GetClockConfig() function to know which clock is 716:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * currently used as system clock source. 717:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * @note Depending on the device voltage range, the software has to set correctly 718:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency 719:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * (for more details refer to section above "Initialization/de-initialization functions") 720:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * @retval None 721:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** */ 722:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) 723:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { ARM GAS /tmp/ccemvyj9.s page 39 724:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** uint32_t tickstart = 0; 725:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 726:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Check Null pointer */ 727:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** if (RCC_ClkInitStruct == NULL) 728:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 729:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** return HAL_ERROR; 730:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } 731:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 732:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Check the parameters */ 733:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** assert_param(IS_RCC_CLOCKTYPE(RCC_ClkInitStruct->ClockType)); 734:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** assert_param(IS_FLASH_LATENCY(FLatency)); 735:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 736:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* To correctly read data from FLASH memory, the number of wait states (LATENCY) 737:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** must be correctly programmed according to the frequency of the CPU clock 738:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** (HCLK) and the supply voltage of the device. */ 739:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 740:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Increasing the CPU frequency */ 741:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** if (FLatency > __HAL_FLASH_GET_LATENCY()) 742:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 743:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ 744:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** __HAL_FLASH_SET_LATENCY(FLatency); 745:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 746:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Check that the new number of wait states is taken into account to access the Flash 747:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** memory by reading the FLASH_ACR register */ 748:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** if (__HAL_FLASH_GET_LATENCY() != FLatency) 749:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 750:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** return HAL_ERROR; 751:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } 752:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } 753:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 754:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /*-------------------------- HCLK Configuration --------------------------*/ 755:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) 756:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 757:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Set the highest APBx dividers in order to ensure that we do not go through 758:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** a non-spec phase whatever we decrease or increase HCLK. */ 759:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) 760:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 761:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16); 762:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } 763:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 764:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) 765:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 766:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, (RCC_HCLK_DIV16 << 3)); 767:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } 768:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 769:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Set the new HCLK clock divider */ 770:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); 771:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); 772:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } 773:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 774:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /*------------------------- SYSCLK Configuration ---------------------------*/ 775:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) 776:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 777:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource)); 778:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 779:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* HSE is selected as System Clock Source */ 780:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) ARM GAS /tmp/ccemvyj9.s page 40 781:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 782:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Check the HSE ready flag */ 783:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) 784:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 785:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** return HAL_ERROR; 786:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } 787:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } 788:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* PLL is selected as System Clock Source */ 789:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) 790:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 791:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Check the PLL ready flag */ 792:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** if (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) 793:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 794:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** return HAL_ERROR; 795:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } 796:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } 797:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* HSI is selected as System Clock Source */ 798:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** else 799:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 800:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Check the HSI ready flag */ 801:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) 802:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 803:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** return HAL_ERROR; 804:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } 805:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } 806:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 807:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource); 808:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 809:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Get Start Tick*/ 810:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** tickstart = HAL_GetTick(); 811:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 812:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) 813:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 814:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) 815:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 816:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** return HAL_TIMEOUT; 817:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } 818:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } 819:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } 820:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 821:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Decreasing the number of wait states because of lower CPU frequency */ 822:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** if (FLatency < __HAL_FLASH_GET_LATENCY()) 823:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 824:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ 825:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** __HAL_FLASH_SET_LATENCY(FLatency); 826:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 827:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Check that the new number of wait states is taken into account to access the Flash 828:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** memory by reading the FLASH_ACR register */ 829:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** if (__HAL_FLASH_GET_LATENCY() != FLatency) 830:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 831:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** return HAL_ERROR; 832:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } 833:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } 834:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 835:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /*-------------------------- PCLK1 Configuration ---------------------------*/ 836:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) 837:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { ARM GAS /tmp/ccemvyj9.s page 41 838:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider)); 839:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider); 840:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } 841:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 842:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /*-------------------------- PCLK2 Configuration ---------------------------*/ 843:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) 844:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 845:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider)); 846:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3)); 847:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } 848:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 849:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Update the SystemCoreClock global variable */ 850:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE) >> RCC_C 851:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 852:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Configure the source of time base considering new system clocks settings*/ 853:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** HAL_InitTick(uwTickPrio); 854:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 855:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** return HAL_OK; 856:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } 857:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 858:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /** 859:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * @} 860:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** */ 861:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 862:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /** @defgroup RCC_Exported_Functions_Group2 Peripheral Control functions 863:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * @brief RCC clocks control functions 864:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * 865:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** @verbatim 866:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** =============================================================================== 867:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** ##### Peripheral Control functions ##### 868:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** =============================================================================== 869:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** [..] 870:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** This subsection provides a set of functions allowing to control the RCC Clocks 871:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** frequencies. 872:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 873:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** @endverbatim 874:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * @{ 875:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** */ 876:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 877:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /** 878:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * @brief Selects the clock source to output on MCO1 pin(PA8) or on MCO2 pin(PC9). 879:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * @note PA8/PC9 should be configured in alternate function mode. 880:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * @param RCC_MCOx specifies the output direction for the clock source. 881:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * This parameter can be one of the following values: 882:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * @arg RCC_MCO1: Clock source to output on MCO1 pin(PA8). 883:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * @arg RCC_MCO2: Clock source to output on MCO2 pin(PC9). 884:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * @param RCC_MCOSource specifies the clock source to output. 885:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * This parameter can be one of the following values: 886:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * @arg RCC_MCO1SOURCE_HSI: HSI clock selected as MCO1 source 887:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * @arg RCC_MCO1SOURCE_LSE: LSE clock selected as MCO1 source 888:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * @arg RCC_MCO1SOURCE_HSE: HSE clock selected as MCO1 source 889:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * @arg RCC_MCO1SOURCE_PLLCLK: main PLL clock selected as MCO1 source 890:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * @arg RCC_MCO2SOURCE_SYSCLK: System clock (SYSCLK) selected as MCO2 source 891:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * @arg RCC_MCO2SOURCE_PLLI2SCLK: PLLI2S clock selected as MCO2 source 892:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * @arg RCC_MCO2SOURCE_HSE: HSE clock selected as MCO2 source 893:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * @arg RCC_MCO2SOURCE_PLLCLK: main PLL clock selected as MCO2 source 894:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * @param RCC_MCODiv specifies the MCOx prescaler. ARM GAS /tmp/ccemvyj9.s page 42 895:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * This parameter can be one of the following values: 896:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * @arg RCC_MCODIV_1: no division applied to MCOx clock 897:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * @arg RCC_MCODIV_2: division by 2 applied to MCOx clock 898:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * @arg RCC_MCODIV_3: division by 3 applied to MCOx clock 899:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * @arg RCC_MCODIV_4: division by 4 applied to MCOx clock 900:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * @arg RCC_MCODIV_5: division by 5 applied to MCOx clock 901:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * @retval None 902:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** */ 903:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv) 904:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 1228 .loc 1 904 1 is_stmt 1 view -0 1229 .cfi_startproc 1230 @ args = 0, pretend = 0, frame = 32 1231 @ frame_needed = 0, uses_anonymous_args = 0 1232 .loc 1 904 1 is_stmt 0 view .LVU392 1233 0000 70B5 push {r4, r5, r6, lr} 1234 .LCFI7: 1235 .cfi_def_cfa_offset 16 1236 .cfi_offset 4, -16 1237 .cfi_offset 5, -12 1238 .cfi_offset 6, -8 1239 .cfi_offset 14, -4 1240 0002 88B0 sub sp, sp, #32 1241 .LCFI8: 1242 .cfi_def_cfa_offset 48 1243 0004 0C46 mov r4, r1 1244 0006 1546 mov r5, r2 905:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** GPIO_InitTypeDef GPIO_InitStruct; 1245 .loc 1 905 3 is_stmt 1 view .LVU393 906:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Check the parameters */ 907:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** assert_param(IS_RCC_MCO(RCC_MCOx)); 1246 .loc 1 907 3 view .LVU394 908:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** assert_param(IS_RCC_MCODIV(RCC_MCODiv)); 1247 .loc 1 908 3 view .LVU395 909:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* RCC_MCO1 */ 910:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** if (RCC_MCOx == RCC_MCO1) 1248 .loc 1 910 3 view .LVU396 1249 .loc 1 910 6 is_stmt 0 view .LVU397 1250 0008 F8B9 cbnz r0, .L129 911:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 912:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** assert_param(IS_RCC_MCO1SOURCE(RCC_MCOSource)); 1251 .loc 1 912 5 is_stmt 1 view .LVU398 913:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 914:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* MCO1 Clock Enable */ 915:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** MCO1_CLK_ENABLE(); 1252 .loc 1 915 5 view .LVU399 1253 .LBB5: 1254 .loc 1 915 5 view .LVU400 1255 .loc 1 915 5 view .LVU401 1256 000a 204E ldr r6, .L132 1257 000c 336B ldr r3, [r6, #48] 1258 000e 43F00103 orr r3, r3, #1 1259 0012 3363 str r3, [r6, #48] 1260 .loc 1 915 5 view .LVU402 1261 0014 336B ldr r3, [r6, #48] 1262 0016 03F00103 and r3, r3, #1 1263 001a 0193 str r3, [sp, #4] ARM GAS /tmp/ccemvyj9.s page 43 1264 .loc 1 915 5 view .LVU403 1265 001c 019B ldr r3, [sp, #4] 1266 .LBE5: 1267 .loc 1 915 5 view .LVU404 916:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 917:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Configure the MCO1 pin in alternate function mode */ 918:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** GPIO_InitStruct.Pin = MCO1_PIN; 1268 .loc 1 918 5 view .LVU405 1269 .loc 1 918 25 is_stmt 0 view .LVU406 1270 001e 4FF48073 mov r3, #256 1271 0022 0393 str r3, [sp, #12] 919:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 1272 .loc 1 919 5 is_stmt 1 view .LVU407 1273 .loc 1 919 26 is_stmt 0 view .LVU408 1274 0024 0223 movs r3, #2 1275 0026 0493 str r3, [sp, #16] 920:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** GPIO_InitStruct.Speed = GPIO_SPEED_HIGH; 1276 .loc 1 920 5 is_stmt 1 view .LVU409 1277 .loc 1 920 27 is_stmt 0 view .LVU410 1278 0028 0323 movs r3, #3 1279 002a 0693 str r3, [sp, #24] 921:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** GPIO_InitStruct.Pull = GPIO_NOPULL; 1280 .loc 1 921 5 is_stmt 1 view .LVU411 1281 .loc 1 921 26 is_stmt 0 view .LVU412 1282 002c 0023 movs r3, #0 1283 002e 0593 str r3, [sp, #20] 922:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** GPIO_InitStruct.Alternate = GPIO_AF0_MCO; 1284 .loc 1 922 5 is_stmt 1 view .LVU413 1285 .loc 1 922 31 is_stmt 0 view .LVU414 1286 0030 0793 str r3, [sp, #28] 923:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** HAL_GPIO_Init(MCO1_GPIO_PORT, &GPIO_InitStruct); 1287 .loc 1 923 5 is_stmt 1 view .LVU415 1288 0032 03A9 add r1, sp, #12 1289 .LVL91: 1290 .loc 1 923 5 is_stmt 0 view .LVU416 1291 0034 1648 ldr r0, .L132+4 1292 .LVL92: 1293 .loc 1 923 5 view .LVU417 1294 0036 FFF7FEFF bl HAL_GPIO_Init 1295 .LVL93: 924:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 925:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Mask MCO1 and MCO1PRE[2:0] bits then Select MCO1 clock source and prescaler */ 926:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO1 | RCC_CFGR_MCO1PRE), (RCC_MCOSource | RCC_MCODiv)); 1296 .loc 1 926 5 is_stmt 1 view .LVU418 1297 003a B368 ldr r3, [r6, #8] 1298 003c 23F0EC63 bic r3, r3, #123731968 1299 0040 2543 orrs r5, r5, r4 1300 .LVL94: 1301 .loc 1 926 5 is_stmt 0 view .LVU419 1302 0042 1D43 orrs r5, r5, r3 1303 0044 B560 str r5, [r6, #8] 1304 .LVL95: 1305 .L128: 927:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } 928:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** else 929:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 930:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** assert_param(IS_RCC_MCO2SOURCE(RCC_MCOSource)); ARM GAS /tmp/ccemvyj9.s page 44 931:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 932:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* MCO2 Clock Enable */ 933:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** MCO2_CLK_ENABLE(); 934:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 935:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Configure the MCO2 pin in alternate function mode */ 936:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** GPIO_InitStruct.Pin = MCO2_PIN; 937:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 938:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** GPIO_InitStruct.Speed = GPIO_SPEED_HIGH; 939:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** GPIO_InitStruct.Pull = GPIO_NOPULL; 940:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** GPIO_InitStruct.Alternate = GPIO_AF0_MCO; 941:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** HAL_GPIO_Init(MCO2_GPIO_PORT, &GPIO_InitStruct); 942:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 943:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Mask MCO2 and MCO2PRE[2:0] bits then Select MCO2 clock source and prescaler */ 944:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO2 | RCC_CFGR_MCO2PRE), (RCC_MCOSource | (RCC_MCODiv << 3))); 945:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } 946:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } 1306 .loc 1 946 1 view .LVU420 1307 0046 08B0 add sp, sp, #32 1308 .LCFI9: 1309 .cfi_remember_state 1310 .cfi_def_cfa_offset 16 1311 @ sp needed 1312 0048 70BD pop {r4, r5, r6, pc} 1313 .LVL96: 1314 .L129: 1315 .LCFI10: 1316 .cfi_restore_state 930:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 1317 .loc 1 930 5 is_stmt 1 view .LVU421 933:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 1318 .loc 1 933 5 view .LVU422 1319 .LBB6: 933:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 1320 .loc 1 933 5 view .LVU423 933:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 1321 .loc 1 933 5 view .LVU424 1322 004a 104E ldr r6, .L132 1323 004c 336B ldr r3, [r6, #48] 1324 004e 43F00403 orr r3, r3, #4 1325 0052 3363 str r3, [r6, #48] 933:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 1326 .loc 1 933 5 view .LVU425 1327 0054 336B ldr r3, [r6, #48] 1328 0056 03F00403 and r3, r3, #4 1329 005a 0293 str r3, [sp, #8] 933:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 1330 .loc 1 933 5 view .LVU426 1331 005c 029B ldr r3, [sp, #8] 1332 .LBE6: 933:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 1333 .loc 1 933 5 view .LVU427 936:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 1334 .loc 1 936 5 view .LVU428 936:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 1335 .loc 1 936 25 is_stmt 0 view .LVU429 1336 005e 4FF40073 mov r3, #512 1337 0062 0393 str r3, [sp, #12] ARM GAS /tmp/ccemvyj9.s page 45 937:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** GPIO_InitStruct.Speed = GPIO_SPEED_HIGH; 1338 .loc 1 937 5 is_stmt 1 view .LVU430 937:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** GPIO_InitStruct.Speed = GPIO_SPEED_HIGH; 1339 .loc 1 937 26 is_stmt 0 view .LVU431 1340 0064 0223 movs r3, #2 1341 0066 0493 str r3, [sp, #16] 938:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** GPIO_InitStruct.Pull = GPIO_NOPULL; 1342 .loc 1 938 5 is_stmt 1 view .LVU432 938:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** GPIO_InitStruct.Pull = GPIO_NOPULL; 1343 .loc 1 938 27 is_stmt 0 view .LVU433 1344 0068 0323 movs r3, #3 1345 006a 0693 str r3, [sp, #24] 939:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** GPIO_InitStruct.Alternate = GPIO_AF0_MCO; 1346 .loc 1 939 5 is_stmt 1 view .LVU434 939:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** GPIO_InitStruct.Alternate = GPIO_AF0_MCO; 1347 .loc 1 939 26 is_stmt 0 view .LVU435 1348 006c 0023 movs r3, #0 1349 006e 0593 str r3, [sp, #20] 940:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** HAL_GPIO_Init(MCO2_GPIO_PORT, &GPIO_InitStruct); 1350 .loc 1 940 5 is_stmt 1 view .LVU436 940:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** HAL_GPIO_Init(MCO2_GPIO_PORT, &GPIO_InitStruct); 1351 .loc 1 940 31 is_stmt 0 view .LVU437 1352 0070 0793 str r3, [sp, #28] 941:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 1353 .loc 1 941 5 is_stmt 1 view .LVU438 1354 0072 03A9 add r1, sp, #12 1355 .LVL97: 941:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 1356 .loc 1 941 5 is_stmt 0 view .LVU439 1357 0074 0748 ldr r0, .L132+8 1358 .LVL98: 941:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 1359 .loc 1 941 5 view .LVU440 1360 0076 FFF7FEFF bl HAL_GPIO_Init 1361 .LVL99: 944:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } 1362 .loc 1 944 5 is_stmt 1 view .LVU441 1363 007a B368 ldr r3, [r6, #8] 1364 007c 23F07843 bic r3, r3, #-134217728 1365 0080 44EAC504 orr r4, r4, r5, lsl #3 1366 .LVL100: 944:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } 1367 .loc 1 944 5 is_stmt 0 view .LVU442 1368 0084 1C43 orrs r4, r4, r3 1369 0086 B460 str r4, [r6, #8] 1370 .loc 1 946 1 view .LVU443 1371 0088 DDE7 b .L128 1372 .L133: 1373 008a 00BF .align 2 1374 .L132: 1375 008c 00380240 .word 1073887232 1376 0090 00000240 .word 1073872896 1377 0094 00080240 .word 1073874944 1378 .cfi_endproc 1379 .LFE144: 1381 .section .text.HAL_RCC_EnableCSS,"ax",%progbits 1382 .align 1 ARM GAS /tmp/ccemvyj9.s page 46 1383 .global HAL_RCC_EnableCSS 1384 .syntax unified 1385 .thumb 1386 .thumb_func 1388 HAL_RCC_EnableCSS: 1389 .LFB145: 947:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 948:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /** 949:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * @brief Enables the Clock Security System. 950:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * @note If a failure is detected on the HSE oscillator clock, this oscillator 951:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * is automatically disabled and an interrupt is generated to inform the 952:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * software about the failure (Clock Security System Interrupt, CSSI), 953:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * allowing the MCU to perform rescue operations. The CSSI is linked to 954:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * the Cortex-M7 NMI (Non-Maskable Interrupt) exception vector. 955:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * @retval None 956:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** */ 957:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** void HAL_RCC_EnableCSS(void) 958:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 1390 .loc 1 958 1 is_stmt 1 view -0 1391 .cfi_startproc 1392 @ args = 0, pretend = 0, frame = 0 1393 @ frame_needed = 0, uses_anonymous_args = 0 1394 @ link register save eliminated. 959:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** SET_BIT(RCC->CR, RCC_CR_CSSON); 1395 .loc 1 959 3 view .LVU445 1396 0000 024A ldr r2, .L135 1397 0002 1368 ldr r3, [r2] 1398 0004 43F40023 orr r3, r3, #524288 1399 0008 1360 str r3, [r2] 960:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } 1400 .loc 1 960 1 is_stmt 0 view .LVU446 1401 000a 7047 bx lr 1402 .L136: 1403 .align 2 1404 .L135: 1405 000c 00380240 .word 1073887232 1406 .cfi_endproc 1407 .LFE145: 1409 .section .text.HAL_RCC_DisableCSS,"ax",%progbits 1410 .align 1 1411 .global HAL_RCC_DisableCSS 1412 .syntax unified 1413 .thumb 1414 .thumb_func 1416 HAL_RCC_DisableCSS: 1417 .LFB146: 961:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 962:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /** 963:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * @brief Disables the Clock Security System. 964:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * @retval None 965:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** */ 966:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** void HAL_RCC_DisableCSS(void) 967:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 1418 .loc 1 967 1 is_stmt 1 view -0 1419 .cfi_startproc 1420 @ args = 0, pretend = 0, frame = 0 1421 @ frame_needed = 0, uses_anonymous_args = 0 ARM GAS /tmp/ccemvyj9.s page 47 1422 @ link register save eliminated. 968:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** CLEAR_BIT(RCC->CR, RCC_CR_CSSON); 1423 .loc 1 968 3 view .LVU448 1424 0000 024A ldr r2, .L138 1425 0002 1368 ldr r3, [r2] 1426 0004 23F40023 bic r3, r3, #524288 1427 0008 1360 str r3, [r2] 969:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } 1428 .loc 1 969 1 is_stmt 0 view .LVU449 1429 000a 7047 bx lr 1430 .L139: 1431 .align 2 1432 .L138: 1433 000c 00380240 .word 1073887232 1434 .cfi_endproc 1435 .LFE146: 1437 .global __aeabi_uldivmod 1438 .section .text.HAL_RCC_GetSysClockFreq,"ax",%progbits 1439 .align 1 1440 .global HAL_RCC_GetSysClockFreq 1441 .syntax unified 1442 .thumb 1443 .thumb_func 1445 HAL_RCC_GetSysClockFreq: 1446 .LFB147: 970:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 971:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /** 972:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * @brief Returns the SYSCLK frequency 973:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * 974:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * @note The system frequency computed by this function is not the real 975:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * frequency in the chip. It is calculated based on the predefined 976:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * constant and the selected clock source: 977:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(*) 978:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(**) 979:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * @note If SYSCLK source is PLL, function returns values based on HSE_VALUE(**) 980:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * or HSI_VALUE(*) multiplied/divided by the PLL factors. 981:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * @note (*) HSI_VALUE is a constant defined in stm32f7xx_hal_conf.h file (default value 982:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * 16 MHz) but the real value may vary depending on the variations 983:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * in voltage and temperature. 984:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * @note (**) HSE_VALUE is a constant defined in stm32f7xx_hal_conf.h file (default value 985:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * 25 MHz), user has to ensure that HSE_VALUE is same as the real 986:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * frequency of the crystal used. Otherwise, this function may 987:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * have wrong result. 988:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * 989:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * @note The result of this function could be not correct when using fractional 990:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * value for HSE crystal. 991:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * 992:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * @note This function can be used by the user application to compute the 993:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * baudrate for the communication peripherals or configure other parameters. 994:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * 995:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * @note Each time SYSCLK changes, this function must be called to update the 996:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * right SYSCLK value. Otherwise, any configuration based on this function will be incorre 997:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * 998:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * 999:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * @retval SYSCLK frequency 1000:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** */ 1001:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** uint32_t HAL_RCC_GetSysClockFreq(void) ARM GAS /tmp/ccemvyj9.s page 48 1002:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 1447 .loc 1 1002 1 is_stmt 1 view -0 1448 .cfi_startproc 1449 @ args = 0, pretend = 0, frame = 0 1450 @ frame_needed = 0, uses_anonymous_args = 0 1451 0000 08B5 push {r3, lr} 1452 .LCFI11: 1453 .cfi_def_cfa_offset 8 1454 .cfi_offset 3, -8 1455 .cfi_offset 14, -4 1003:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** uint32_t pllm = 0, pllvco = 0, pllp = 0; 1456 .loc 1 1003 3 view .LVU451 1457 .LVL101: 1004:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** uint32_t sysclockfreq = 0; 1458 .loc 1 1004 3 view .LVU452 1005:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 1006:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Get SYSCLK source -------------------------------------------------------*/ 1007:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** switch (RCC->CFGR & RCC_CFGR_SWS) 1459 .loc 1 1007 3 view .LVU453 1460 .loc 1 1007 14 is_stmt 0 view .LVU454 1461 0002 264B ldr r3, .L147 1462 0004 9B68 ldr r3, [r3, #8] 1463 .loc 1 1007 21 view .LVU455 1464 0006 03F00C03 and r3, r3, #12 1465 .loc 1 1007 3 view .LVU456 1466 000a 042B cmp r3, #4 1467 000c 41D0 beq .L144 1468 000e 082B cmp r3, #8 1469 0010 41D1 bne .L145 1008:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 1009:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** case RCC_SYSCLKSOURCE_STATUS_HSI: /* HSI used as system clock source */ 1010:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 1011:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** sysclockfreq = HSI_VALUE; 1012:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** break; 1013:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } 1014:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** case RCC_SYSCLKSOURCE_STATUS_HSE: /* HSE used as system clock source */ 1015:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 1016:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** sysclockfreq = HSE_VALUE; 1017:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** break; 1018:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } 1019:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** case RCC_SYSCLKSOURCE_STATUS_PLLCLK: /* PLL used as system clock source */ 1020:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 1021:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN 1022:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** SYSCLK = PLL_VCO / PLLP */ 1023:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; 1470 .loc 1 1023 7 is_stmt 1 view .LVU457 1471 .loc 1 1023 17 is_stmt 0 view .LVU458 1472 0012 224B ldr r3, .L147 1473 0014 5A68 ldr r2, [r3, #4] 1474 .loc 1 1023 12 view .LVU459 1475 0016 02F03F02 and r2, r2, #63 1476 .LVL102: 1024:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** if (__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLCFGR_PLLSRC_HSI) 1477 .loc 1 1024 7 is_stmt 1 view .LVU460 1478 .loc 1 1024 11 is_stmt 0 view .LVU461 1479 001a 5B68 ldr r3, [r3, #4] 1480 .loc 1 1024 10 view .LVU462 ARM GAS /tmp/ccemvyj9.s page 49 1481 001c 13F4800F tst r3, #4194304 1482 0020 12D0 beq .L142 1025:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 1026:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* HSE used as PLL clock source */ 1027:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** pllvco = (uint32_t)((((uint64_t) HSE_VALUE * ((uint64_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) 1483 .loc 1 1027 9 is_stmt 1 view .LVU463 1484 .loc 1 1027 70 is_stmt 0 view .LVU464 1485 0022 1E4B ldr r3, .L147 1486 0024 5968 ldr r1, [r3, #4] 1487 .loc 1 1027 55 view .LVU465 1488 0026 C1F38811 ubfx r1, r1, #6, #9 1489 .loc 1 1027 52 view .LVU466 1490 002a 1D48 ldr r0, .L147+4 1491 .loc 1 1027 128 view .LVU467 1492 002c 0023 movs r3, #0 1493 002e A1FB0001 umull r0, r1, r1, r0 1494 0032 FFF7FEFF bl __aeabi_uldivmod 1495 .LVL103: 1496 .L143: 1028:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } 1029:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** else 1030:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 1031:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* HSI used as PLL clock source */ 1032:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** pllvco = (uint32_t)((((uint64_t) HSI_VALUE * ((uint64_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) 1033:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } 1034:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** pllp = ((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >> RCC_PLLCFGR_PLLP_Pos) + 1) * 2); 1497 .loc 1 1034 7 is_stmt 1 view .LVU468 1498 .loc 1 1034 21 is_stmt 0 view .LVU469 1499 0036 194B ldr r3, .L147 1500 0038 5B68 ldr r3, [r3, #4] 1501 .loc 1 1034 51 view .LVU470 1502 003a C3F30143 ubfx r3, r3, #16, #2 1503 .loc 1 1034 76 view .LVU471 1504 003e 0133 adds r3, r3, #1 1505 .loc 1 1034 12 view .LVU472 1506 0040 5B00 lsls r3, r3, #1 1507 .LVL104: 1035:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 1036:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** sysclockfreq = pllvco / pllp; 1508 .loc 1 1036 7 is_stmt 1 view .LVU473 1509 .loc 1 1036 20 is_stmt 0 view .LVU474 1510 0042 B0FBF3F0 udiv r0, r0, r3 1511 .LVL105: 1037:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** break; 1512 .loc 1 1037 7 is_stmt 1 view .LVU475 1513 .L140: 1038:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } 1039:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** default: 1040:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 1041:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** sysclockfreq = HSI_VALUE; 1042:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** break; 1043:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } 1044:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } 1045:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** return sysclockfreq; 1046:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } 1514 .loc 1 1046 1 is_stmt 0 view .LVU476 1515 0046 08BD pop {r3, pc} ARM GAS /tmp/ccemvyj9.s page 50 1516 .LVL106: 1517 .L142: 1032:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } 1518 .loc 1 1032 9 is_stmt 1 view .LVU477 1032:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } 1519 .loc 1 1032 70 is_stmt 0 view .LVU478 1520 0048 144B ldr r3, .L147 1521 004a 5868 ldr r0, [r3, #4] 1032:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } 1522 .loc 1 1032 55 view .LVU479 1523 004c C0F38810 ubfx r0, r0, #6, #9 1032:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } 1524 .loc 1 1032 52 view .LVU480 1525 0050 4FEA401C lsl ip, r0, #5 1526 0054 BCEB000C subs ip, ip, r0 1527 0058 6EEB0E0E sbc lr, lr, lr 1528 005c 4FEA8E13 lsl r3, lr, #6 1529 0060 43EA9C63 orr r3, r3, ip, lsr #26 1530 0064 4FEA8C11 lsl r1, ip, #6 1531 0068 B1EB0C01 subs r1, r1, ip 1532 006c 63EB0E03 sbc r3, r3, lr 1533 0070 DB00 lsls r3, r3, #3 1534 0072 43EA5173 orr r3, r3, r1, lsr #29 1535 0076 C900 lsls r1, r1, #3 1536 0078 11EB000C adds ip, r1, r0 1537 007c 43F10003 adc r3, r3, #0 1538 0080 9902 lsls r1, r3, #10 1032:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } 1539 .loc 1 1032 128 view .LVU481 1540 0082 0023 movs r3, #0 1541 0084 4FEA8C20 lsl r0, ip, #10 1542 0088 41EA9C51 orr r1, r1, ip, lsr #22 1543 008c FFF7FEFF bl __aeabi_uldivmod 1544 .LVL107: 1032:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } 1545 .loc 1 1032 128 view .LVU482 1546 0090 D1E7 b .L143 1547 .LVL108: 1548 .L144: 1016:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** break; 1549 .loc 1 1016 20 view .LVU483 1550 0092 0348 ldr r0, .L147+4 1551 0094 D7E7 b .L140 1552 .L145: 1007:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 1553 .loc 1 1007 3 view .LVU484 1554 0096 0348 ldr r0, .L147+8 1555 .LVL109: 1045:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } 1556 .loc 1 1045 3 is_stmt 1 view .LVU485 1045:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } 1557 .loc 1 1045 10 is_stmt 0 view .LVU486 1558 0098 D5E7 b .L140 1559 .L148: 1560 009a 00BF .align 2 1561 .L147: 1562 009c 00380240 .word 1073887232 ARM GAS /tmp/ccemvyj9.s page 51 1563 00a0 40787D01 .word 25000000 1564 00a4 0024F400 .word 16000000 1565 .cfi_endproc 1566 .LFE147: 1568 .section .text.HAL_RCC_ClockConfig,"ax",%progbits 1569 .align 1 1570 .global HAL_RCC_ClockConfig 1571 .syntax unified 1572 .thumb 1573 .thumb_func 1575 HAL_RCC_ClockConfig: 1576 .LVL110: 1577 .LFB143: 723:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** uint32_t tickstart = 0; 1578 .loc 1 723 1 is_stmt 1 view -0 1579 .cfi_startproc 1580 @ args = 0, pretend = 0, frame = 0 1581 @ frame_needed = 0, uses_anonymous_args = 0 724:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 1582 .loc 1 724 3 view .LVU488 727:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 1583 .loc 1 727 3 view .LVU489 727:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 1584 .loc 1 727 6 is_stmt 0 view .LVU490 1585 0000 0028 cmp r0, #0 1586 0002 00F0A080 beq .L164 723:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** uint32_t tickstart = 0; 1587 .loc 1 723 1 view .LVU491 1588 0006 70B5 push {r4, r5, r6, lr} 1589 .LCFI12: 1590 .cfi_def_cfa_offset 16 1591 .cfi_offset 4, -16 1592 .cfi_offset 5, -12 1593 .cfi_offset 6, -8 1594 .cfi_offset 14, -4 1595 0008 0D46 mov r5, r1 1596 000a 0446 mov r4, r0 733:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** assert_param(IS_FLASH_LATENCY(FLatency)); 1597 .loc 1 733 3 is_stmt 1 view .LVU492 734:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 1598 .loc 1 734 3 view .LVU493 741:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 1599 .loc 1 741 3 view .LVU494 741:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 1600 .loc 1 741 18 is_stmt 0 view .LVU495 1601 000c 524B ldr r3, .L177 1602 000e 1B68 ldr r3, [r3] 1603 0010 03F00F03 and r3, r3, #15 741:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 1604 .loc 1 741 6 view .LVU496 1605 0014 8B42 cmp r3, r1 1606 0016 0BD2 bcs .L151 744:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 1607 .loc 1 744 5 is_stmt 1 view .LVU497 1608 0018 4F4A ldr r2, .L177 1609 001a 1368 ldr r3, [r2] 1610 001c 23F00F03 bic r3, r3, #15 ARM GAS /tmp/ccemvyj9.s page 52 1611 0020 0B43 orrs r3, r3, r1 1612 0022 1360 str r3, [r2] 748:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 1613 .loc 1 748 5 view .LVU498 748:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 1614 .loc 1 748 9 is_stmt 0 view .LVU499 1615 0024 1368 ldr r3, [r2] 1616 0026 03F00F03 and r3, r3, #15 748:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 1617 .loc 1 748 8 view .LVU500 1618 002a 8B42 cmp r3, r1 1619 002c 40F08D80 bne .L165 1620 .L151: 755:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 1621 .loc 1 755 3 is_stmt 1 view .LVU501 755:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 1622 .loc 1 755 26 is_stmt 0 view .LVU502 1623 0030 2368 ldr r3, [r4] 755:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 1624 .loc 1 755 6 view .LVU503 1625 0032 13F0020F tst r3, #2 1626 0036 17D0 beq .L152 759:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 1627 .loc 1 759 5 is_stmt 1 view .LVU504 759:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 1628 .loc 1 759 8 is_stmt 0 view .LVU505 1629 0038 13F0040F tst r3, #4 1630 003c 04D0 beq .L153 761:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } 1631 .loc 1 761 7 is_stmt 1 view .LVU506 1632 003e 474A ldr r2, .L177+4 1633 0040 9368 ldr r3, [r2, #8] 1634 0042 43F4E053 orr r3, r3, #7168 1635 0046 9360 str r3, [r2, #8] 1636 .L153: 764:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 1637 .loc 1 764 5 view .LVU507 764:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 1638 .loc 1 764 28 is_stmt 0 view .LVU508 1639 0048 2368 ldr r3, [r4] 764:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 1640 .loc 1 764 8 view .LVU509 1641 004a 13F0080F tst r3, #8 1642 004e 04D0 beq .L154 766:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } 1643 .loc 1 766 7 is_stmt 1 view .LVU510 1644 0050 424A ldr r2, .L177+4 1645 0052 9368 ldr r3, [r2, #8] 1646 0054 43F46043 orr r3, r3, #57344 1647 0058 9360 str r3, [r2, #8] 1648 .L154: 770:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); 1649 .loc 1 770 5 view .LVU511 771:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } 1650 .loc 1 771 5 view .LVU512 1651 005a 404A ldr r2, .L177+4 1652 005c 9368 ldr r3, [r2, #8] ARM GAS /tmp/ccemvyj9.s page 53 1653 005e 23F0F003 bic r3, r3, #240 1654 0062 A168 ldr r1, [r4, #8] 1655 .LVL111: 771:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } 1656 .loc 1 771 5 is_stmt 0 view .LVU513 1657 0064 0B43 orrs r3, r3, r1 1658 0066 9360 str r3, [r2, #8] 1659 .L152: 775:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 1660 .loc 1 775 3 is_stmt 1 view .LVU514 775:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 1661 .loc 1 775 26 is_stmt 0 view .LVU515 1662 0068 2368 ldr r3, [r4] 775:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 1663 .loc 1 775 6 view .LVU516 1664 006a 13F0010F tst r3, #1 1665 006e 31D0 beq .L155 777:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 1666 .loc 1 777 5 is_stmt 1 view .LVU517 780:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 1667 .loc 1 780 5 view .LVU518 780:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 1668 .loc 1 780 26 is_stmt 0 view .LVU519 1669 0070 6368 ldr r3, [r4, #4] 780:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 1670 .loc 1 780 8 view .LVU520 1671 0072 012B cmp r3, #1 1672 0074 20D0 beq .L175 789:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 1673 .loc 1 789 10 is_stmt 1 view .LVU521 789:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 1674 .loc 1 789 13 is_stmt 0 view .LVU522 1675 0076 022B cmp r3, #2 1676 0078 25D0 beq .L176 801:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 1677 .loc 1 801 7 is_stmt 1 view .LVU523 801:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 1678 .loc 1 801 11 is_stmt 0 view .LVU524 1679 007a 384A ldr r2, .L177+4 1680 007c 1268 ldr r2, [r2] 801:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 1681 .loc 1 801 10 view .LVU525 1682 007e 12F0020F tst r2, #2 1683 0082 64D0 beq .L168 1684 .L157: 807:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 1685 .loc 1 807 5 is_stmt 1 view .LVU526 1686 0084 3549 ldr r1, .L177+4 1687 0086 8A68 ldr r2, [r1, #8] 1688 0088 22F00302 bic r2, r2, #3 1689 008c 1343 orrs r3, r3, r2 1690 008e 8B60 str r3, [r1, #8] 810:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 1691 .loc 1 810 5 view .LVU527 810:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 1692 .loc 1 810 17 is_stmt 0 view .LVU528 1693 0090 FFF7FEFF bl HAL_GetTick ARM GAS /tmp/ccemvyj9.s page 54 1694 .LVL112: 810:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 1695 .loc 1 810 17 view .LVU529 1696 0094 0646 mov r6, r0 1697 .LVL113: 812:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 1698 .loc 1 812 5 is_stmt 1 view .LVU530 1699 .L159: 812:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 1700 .loc 1 812 42 view .LVU531 812:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 1701 .loc 1 812 12 is_stmt 0 view .LVU532 1702 0096 314B ldr r3, .L177+4 1703 0098 9B68 ldr r3, [r3, #8] 1704 009a 03F00C03 and r3, r3, #12 812:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 1705 .loc 1 812 63 view .LVU533 1706 009e 6268 ldr r2, [r4, #4] 812:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 1707 .loc 1 812 42 view .LVU534 1708 00a0 B3EB820F cmp r3, r2, lsl #2 1709 00a4 16D0 beq .L155 814:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 1710 .loc 1 814 7 is_stmt 1 view .LVU535 814:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 1711 .loc 1 814 12 is_stmt 0 view .LVU536 1712 00a6 FFF7FEFF bl HAL_GetTick 1713 .LVL114: 814:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 1714 .loc 1 814 26 discriminator 1 view .LVU537 1715 00aa 801B subs r0, r0, r6 814:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 1716 .loc 1 814 10 discriminator 1 view .LVU538 1717 00ac 41F28833 movw r3, #5000 1718 00b0 9842 cmp r0, r3 1719 00b2 F0D9 bls .L159 816:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } 1720 .loc 1 816 16 view .LVU539 1721 00b4 0320 movs r0, #3 1722 00b6 45E0 b .L150 1723 .LVL115: 1724 .L175: 783:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 1725 .loc 1 783 7 is_stmt 1 view .LVU540 783:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 1726 .loc 1 783 11 is_stmt 0 view .LVU541 1727 00b8 284A ldr r2, .L177+4 1728 00ba 1268 ldr r2, [r2] 783:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 1729 .loc 1 783 10 view .LVU542 1730 00bc 12F4003F tst r2, #131072 1731 00c0 E0D1 bne .L157 785:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } 1732 .loc 1 785 16 view .LVU543 1733 00c2 0120 movs r0, #1 1734 .LVL116: 785:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } ARM GAS /tmp/ccemvyj9.s page 55 1735 .loc 1 785 16 view .LVU544 1736 00c4 3EE0 b .L150 1737 .LVL117: 1738 .L176: 792:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 1739 .loc 1 792 7 is_stmt 1 view .LVU545 792:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 1740 .loc 1 792 11 is_stmt 0 view .LVU546 1741 00c6 254A ldr r2, .L177+4 1742 00c8 1268 ldr r2, [r2] 792:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 1743 .loc 1 792 10 view .LVU547 1744 00ca 12F0007F tst r2, #33554432 1745 00ce D9D1 bne .L157 794:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } 1746 .loc 1 794 16 view .LVU548 1747 00d0 0120 movs r0, #1 1748 .LVL118: 794:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } 1749 .loc 1 794 16 view .LVU549 1750 00d2 37E0 b .L150 1751 .LVL119: 1752 .L155: 822:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 1753 .loc 1 822 3 is_stmt 1 view .LVU550 822:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 1754 .loc 1 822 18 is_stmt 0 view .LVU551 1755 00d4 204B ldr r3, .L177 1756 00d6 1B68 ldr r3, [r3] 1757 00d8 03F00F03 and r3, r3, #15 822:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 1758 .loc 1 822 6 view .LVU552 1759 00dc AB42 cmp r3, r5 1760 00de 0AD9 bls .L161 825:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 1761 .loc 1 825 5 is_stmt 1 view .LVU553 1762 00e0 1D4A ldr r2, .L177 1763 00e2 1368 ldr r3, [r2] 1764 00e4 23F00F03 bic r3, r3, #15 1765 00e8 2B43 orrs r3, r3, r5 1766 00ea 1360 str r3, [r2] 829:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 1767 .loc 1 829 5 view .LVU554 829:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 1768 .loc 1 829 9 is_stmt 0 view .LVU555 1769 00ec 1368 ldr r3, [r2] 1770 00ee 03F00F03 and r3, r3, #15 829:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 1771 .loc 1 829 8 view .LVU556 1772 00f2 AB42 cmp r3, r5 1773 00f4 2DD1 bne .L170 1774 .L161: 836:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 1775 .loc 1 836 3 is_stmt 1 view .LVU557 836:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 1776 .loc 1 836 26 is_stmt 0 view .LVU558 1777 00f6 2368 ldr r3, [r4] ARM GAS /tmp/ccemvyj9.s page 56 836:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 1778 .loc 1 836 6 view .LVU559 1779 00f8 13F0040F tst r3, #4 1780 00fc 06D0 beq .L162 838:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider); 1781 .loc 1 838 5 is_stmt 1 view .LVU560 839:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } 1782 .loc 1 839 5 view .LVU561 1783 00fe 174A ldr r2, .L177+4 1784 0100 9368 ldr r3, [r2, #8] 1785 0102 23F4E053 bic r3, r3, #7168 1786 0106 E168 ldr r1, [r4, #12] 1787 0108 0B43 orrs r3, r3, r1 1788 010a 9360 str r3, [r2, #8] 1789 .L162: 843:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 1790 .loc 1 843 3 view .LVU562 843:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 1791 .loc 1 843 26 is_stmt 0 view .LVU563 1792 010c 2368 ldr r3, [r4] 843:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 1793 .loc 1 843 6 view .LVU564 1794 010e 13F0080F tst r3, #8 1795 0112 07D0 beq .L163 845:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3)); 1796 .loc 1 845 5 is_stmt 1 view .LVU565 846:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } 1797 .loc 1 846 5 view .LVU566 1798 0114 114A ldr r2, .L177+4 1799 0116 9368 ldr r3, [r2, #8] 1800 0118 23F46043 bic r3, r3, #57344 1801 011c 2169 ldr r1, [r4, #16] 1802 011e 43EAC103 orr r3, r3, r1, lsl #3 1803 0122 9360 str r3, [r2, #8] 1804 .L163: 850:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 1805 .loc 1 850 3 view .LVU567 850:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 1806 .loc 1 850 21 is_stmt 0 view .LVU568 1807 0124 FFF7FEFF bl HAL_RCC_GetSysClockFreq 1808 .LVL120: 850:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 1809 .loc 1 850 68 discriminator 1 view .LVU569 1810 0128 0C4B ldr r3, .L177+4 1811 012a 9B68 ldr r3, [r3, #8] 850:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 1812 .loc 1 850 92 discriminator 1 view .LVU570 1813 012c C3F30313 ubfx r3, r3, #4, #4 850:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 1814 .loc 1 850 63 discriminator 1 view .LVU571 1815 0130 0B4A ldr r2, .L177+8 1816 0132 D35C ldrb r3, [r2, r3] @ zero_extendqisi2 850:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 1817 .loc 1 850 47 discriminator 1 view .LVU572 1818 0134 D840 lsrs r0, r0, r3 850:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 1819 .loc 1 850 19 discriminator 1 view .LVU573 ARM GAS /tmp/ccemvyj9.s page 57 1820 0136 0B4B ldr r3, .L177+12 1821 0138 1860 str r0, [r3] 853:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 1822 .loc 1 853 3 is_stmt 1 view .LVU574 1823 013a 0B4B ldr r3, .L177+16 1824 013c 1868 ldr r0, [r3] 1825 013e FFF7FEFF bl HAL_InitTick 1826 .LVL121: 855:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } 1827 .loc 1 855 3 view .LVU575 855:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } 1828 .loc 1 855 10 is_stmt 0 view .LVU576 1829 0142 0020 movs r0, #0 1830 .L150: 856:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 1831 .loc 1 856 1 view .LVU577 1832 0144 70BD pop {r4, r5, r6, pc} 1833 .LVL122: 1834 .L164: 1835 .LCFI13: 1836 .cfi_def_cfa_offset 0 1837 .cfi_restore 4 1838 .cfi_restore 5 1839 .cfi_restore 6 1840 .cfi_restore 14 729:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } 1841 .loc 1 729 12 view .LVU578 1842 0146 0120 movs r0, #1 1843 .LVL123: 856:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 1844 .loc 1 856 1 view .LVU579 1845 0148 7047 bx lr 1846 .LVL124: 1847 .L165: 1848 .LCFI14: 1849 .cfi_def_cfa_offset 16 1850 .cfi_offset 4, -16 1851 .cfi_offset 5, -12 1852 .cfi_offset 6, -8 1853 .cfi_offset 14, -4 750:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } 1854 .loc 1 750 14 view .LVU580 1855 014a 0120 movs r0, #1 1856 .LVL125: 750:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } 1857 .loc 1 750 14 view .LVU581 1858 014c FAE7 b .L150 1859 .LVL126: 1860 .L168: 803:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } 1861 .loc 1 803 16 view .LVU582 1862 014e 0120 movs r0, #1 1863 .LVL127: 803:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } 1864 .loc 1 803 16 view .LVU583 1865 0150 F8E7 b .L150 1866 .LVL128: ARM GAS /tmp/ccemvyj9.s page 58 1867 .L170: 831:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } 1868 .loc 1 831 14 view .LVU584 1869 0152 0120 movs r0, #1 1870 0154 F6E7 b .L150 1871 .L178: 1872 0156 00BF .align 2 1873 .L177: 1874 0158 003C0240 .word 1073888256 1875 015c 00380240 .word 1073887232 1876 0160 00000000 .word AHBPrescTable 1877 0164 00000000 .word SystemCoreClock 1878 0168 00000000 .word uwTickPrio 1879 .cfi_endproc 1880 .LFE143: 1882 .section .text.HAL_RCC_GetHCLKFreq,"ax",%progbits 1883 .align 1 1884 .global HAL_RCC_GetHCLKFreq 1885 .syntax unified 1886 .thumb 1887 .thumb_func 1889 HAL_RCC_GetHCLKFreq: 1890 .LFB148: 1047:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 1048:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /** 1049:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * @brief Returns the HCLK frequency 1050:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * @note Each time HCLK changes, this function must be called to update the 1051:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * right HCLK value. Otherwise, any configuration based on this function will be incorrect 1052:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency. 1053:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * @retval HCLK frequency 1054:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** */ 1055:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** uint32_t HAL_RCC_GetHCLKFreq(void) 1056:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 1891 .loc 1 1056 1 is_stmt 1 view -0 1892 .cfi_startproc 1893 @ args = 0, pretend = 0, frame = 0 1894 @ frame_needed = 0, uses_anonymous_args = 0 1895 @ link register save eliminated. 1057:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** return SystemCoreClock; 1896 .loc 1 1057 3 view .LVU586 1058:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } 1897 .loc 1 1058 1 is_stmt 0 view .LVU587 1898 0000 014B ldr r3, .L180 1899 0002 1868 ldr r0, [r3] 1900 0004 7047 bx lr 1901 .L181: 1902 0006 00BF .align 2 1903 .L180: 1904 0008 00000000 .word SystemCoreClock 1905 .cfi_endproc 1906 .LFE148: 1908 .section .text.HAL_RCC_GetPCLK1Freq,"ax",%progbits 1909 .align 1 1910 .global HAL_RCC_GetPCLK1Freq 1911 .syntax unified 1912 .thumb 1913 .thumb_func ARM GAS /tmp/ccemvyj9.s page 59 1915 HAL_RCC_GetPCLK1Freq: 1916 .LFB149: 1059:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 1060:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /** 1061:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * @brief Returns the PCLK1 frequency 1062:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * @note Each time PCLK1 changes, this function must be called to update the 1063:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * right PCLK1 value. Otherwise, any configuration based on this function will be incorrec 1064:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * @retval PCLK1 frequency 1065:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** */ 1066:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** uint32_t HAL_RCC_GetPCLK1Freq(void) 1067:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 1917 .loc 1 1067 1 is_stmt 1 view -0 1918 .cfi_startproc 1919 @ args = 0, pretend = 0, frame = 0 1920 @ frame_needed = 0, uses_anonymous_args = 0 1921 0000 08B5 push {r3, lr} 1922 .LCFI15: 1923 .cfi_def_cfa_offset 8 1924 .cfi_offset 3, -8 1925 .cfi_offset 14, -4 1068:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/ 1069:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_Pos 1926 .loc 1 1069 3 view .LVU589 1927 .loc 1 1069 11 is_stmt 0 view .LVU590 1928 0002 FFF7FEFF bl HAL_RCC_GetHCLKFreq 1929 .LVL129: 1930 .loc 1 1069 54 discriminator 1 view .LVU591 1931 0006 044B ldr r3, .L184 1932 0008 9B68 ldr r3, [r3, #8] 1933 .loc 1 1069 79 discriminator 1 view .LVU592 1934 000a C3F38223 ubfx r3, r3, #10, #3 1935 .loc 1 1069 49 discriminator 1 view .LVU593 1936 000e 034A ldr r2, .L184+4 1937 0010 D35C ldrb r3, [r2, r3] @ zero_extendqisi2 1070:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } 1938 .loc 1 1070 1 view .LVU594 1939 0012 D840 lsrs r0, r0, r3 1940 0014 08BD pop {r3, pc} 1941 .L185: 1942 0016 00BF .align 2 1943 .L184: 1944 0018 00380240 .word 1073887232 1945 001c 00000000 .word APBPrescTable 1946 .cfi_endproc 1947 .LFE149: 1949 .section .text.HAL_RCC_GetPCLK2Freq,"ax",%progbits 1950 .align 1 1951 .global HAL_RCC_GetPCLK2Freq 1952 .syntax unified 1953 .thumb 1954 .thumb_func 1956 HAL_RCC_GetPCLK2Freq: 1957 .LFB150: 1071:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 1072:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /** 1073:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * @brief Returns the PCLK2 frequency 1074:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * @note Each time PCLK2 changes, this function must be called to update the ARM GAS /tmp/ccemvyj9.s page 60 1075:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * right PCLK2 value. Otherwise, any configuration based on this function will be incorrec 1076:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * @retval PCLK2 frequency 1077:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** */ 1078:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** uint32_t HAL_RCC_GetPCLK2Freq(void) 1079:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 1958 .loc 1 1079 1 is_stmt 1 view -0 1959 .cfi_startproc 1960 @ args = 0, pretend = 0, frame = 0 1961 @ frame_needed = 0, uses_anonymous_args = 0 1962 0000 08B5 push {r3, lr} 1963 .LCFI16: 1964 .cfi_def_cfa_offset 8 1965 .cfi_offset 3, -8 1966 .cfi_offset 14, -4 1080:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/ 1081:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_Pos 1967 .loc 1 1081 3 view .LVU596 1968 .loc 1 1081 11 is_stmt 0 view .LVU597 1969 0002 FFF7FEFF bl HAL_RCC_GetHCLKFreq 1970 .LVL130: 1971 .loc 1 1081 54 discriminator 1 view .LVU598 1972 0006 044B ldr r3, .L188 1973 0008 9B68 ldr r3, [r3, #8] 1974 .loc 1 1081 79 discriminator 1 view .LVU599 1975 000a C3F34233 ubfx r3, r3, #13, #3 1976 .loc 1 1081 49 discriminator 1 view .LVU600 1977 000e 034A ldr r2, .L188+4 1978 0010 D35C ldrb r3, [r2, r3] @ zero_extendqisi2 1082:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } 1979 .loc 1 1082 1 view .LVU601 1980 0012 D840 lsrs r0, r0, r3 1981 0014 08BD pop {r3, pc} 1982 .L189: 1983 0016 00BF .align 2 1984 .L188: 1985 0018 00380240 .word 1073887232 1986 001c 00000000 .word APBPrescTable 1987 .cfi_endproc 1988 .LFE150: 1990 .section .text.HAL_RCC_GetOscConfig,"ax",%progbits 1991 .align 1 1992 .global HAL_RCC_GetOscConfig 1993 .syntax unified 1994 .thumb 1995 .thumb_func 1997 HAL_RCC_GetOscConfig: 1998 .LVL131: 1999 .LFB151: 1083:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 1084:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /** 1085:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * @brief Configures the RCC_OscInitStruct according to the internal 1086:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * RCC configuration registers. 1087:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * @param RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that 1088:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * will be configured. 1089:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * @retval None 1090:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** */ 1091:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) ARM GAS /tmp/ccemvyj9.s page 61 1092:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 2000 .loc 1 1092 1 is_stmt 1 view -0 2001 .cfi_startproc 2002 @ args = 0, pretend = 0, frame = 0 2003 @ frame_needed = 0, uses_anonymous_args = 0 2004 @ link register save eliminated. 1093:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Set all possible values for the Oscillator type parameter ---------------*/ 1094:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLA 2005 .loc 1 1094 3 view .LVU603 2006 .loc 1 1094 37 is_stmt 0 view .LVU604 2007 0000 0F23 movs r3, #15 2008 0002 0360 str r3, [r0] 1095:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 1096:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Get the HSE configuration -----------------------------------------------*/ 1097:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** if ((RCC->CR & RCC_CR_HSEBYP) == RCC_CR_HSEBYP) 2009 .loc 1 1097 3 is_stmt 1 view .LVU605 2010 .loc 1 1097 11 is_stmt 0 view .LVU606 2011 0004 354B ldr r3, .L203 2012 0006 1B68 ldr r3, [r3] 2013 .loc 1 1097 6 view .LVU607 2014 0008 13F4802F tst r3, #262144 2015 000c 46D0 beq .L191 1098:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 1099:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS; 2016 .loc 1 1099 5 is_stmt 1 view .LVU608 2017 .loc 1 1099 33 is_stmt 0 view .LVU609 2018 000e 4FF4A023 mov r3, #327680 2019 0012 4360 str r3, [r0, #4] 2020 .L192: 1100:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } 1101:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** else if ((RCC->CR & RCC_CR_HSEON) == RCC_CR_HSEON) 1102:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 1103:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** RCC_OscInitStruct->HSEState = RCC_HSE_ON; 1104:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } 1105:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** else 1106:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 1107:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** RCC_OscInitStruct->HSEState = RCC_HSE_OFF; 1108:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } 1109:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 1110:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Get the HSI configuration -----------------------------------------------*/ 1111:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** if ((RCC->CR & RCC_CR_HSION) == RCC_CR_HSION) 2021 .loc 1 1111 3 is_stmt 1 view .LVU610 2022 .loc 1 1111 11 is_stmt 0 view .LVU611 2023 0014 314B ldr r3, .L203 2024 0016 1B68 ldr r3, [r3] 2025 .loc 1 1111 6 view .LVU612 2026 0018 13F0010F tst r3, #1 2027 001c 4AD0 beq .L194 1112:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 1113:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** RCC_OscInitStruct->HSIState = RCC_HSI_ON; 2028 .loc 1 1113 5 is_stmt 1 view .LVU613 2029 .loc 1 1113 33 is_stmt 0 view .LVU614 2030 001e 0123 movs r3, #1 2031 0020 C360 str r3, [r0, #12] 2032 .L195: 1114:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } 1115:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** else ARM GAS /tmp/ccemvyj9.s page 62 1116:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 1117:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** RCC_OscInitStruct->HSIState = RCC_HSI_OFF; 1118:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } 1119:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 1120:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** RCC_OscInitStruct->HSICalibrationValue = (uint32_t)((RCC->CR & RCC_CR_HSITRIM) >> RCC_CR_HSITRIM_ 2033 .loc 1 1120 3 is_stmt 1 view .LVU615 2034 .loc 1 1120 59 is_stmt 0 view .LVU616 2035 0022 2E4A ldr r2, .L203 2036 0024 1368 ldr r3, [r2] 2037 .loc 1 1120 44 view .LVU617 2038 0026 C3F3C403 ubfx r3, r3, #3, #5 2039 .loc 1 1120 42 view .LVU618 2040 002a 0361 str r3, [r0, #16] 1121:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 1122:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Get the LSE configuration -----------------------------------------------*/ 1123:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** if ((RCC->BDCR & RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP) 2041 .loc 1 1123 3 is_stmt 1 view .LVU619 2042 .loc 1 1123 11 is_stmt 0 view .LVU620 2043 002c 136F ldr r3, [r2, #112] 2044 .loc 1 1123 6 view .LVU621 2045 002e 13F0040F tst r3, #4 2046 0032 42D0 beq .L196 1124:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 1125:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS; 2047 .loc 1 1125 5 is_stmt 1 view .LVU622 2048 .loc 1 1125 33 is_stmt 0 view .LVU623 2049 0034 0523 movs r3, #5 2050 0036 8360 str r3, [r0, #8] 2051 .L197: 1126:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } 1127:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** else if ((RCC->BDCR & RCC_BDCR_LSEON) == RCC_BDCR_LSEON) 1128:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 1129:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** RCC_OscInitStruct->LSEState = RCC_LSE_ON; 1130:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } 1131:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** else 1132:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 1133:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** RCC_OscInitStruct->LSEState = RCC_LSE_OFF; 1134:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } 1135:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 1136:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Get the LSI configuration -----------------------------------------------*/ 1137:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** if ((RCC->CSR & RCC_CSR_LSION) == RCC_CSR_LSION) 2052 .loc 1 1137 3 is_stmt 1 view .LVU624 2053 .loc 1 1137 11 is_stmt 0 view .LVU625 2054 0038 284B ldr r3, .L203 2055 003a 5B6F ldr r3, [r3, #116] 2056 .loc 1 1137 6 view .LVU626 2057 003c 13F0010F tst r3, #1 2058 0040 46D0 beq .L199 1138:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 1139:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** RCC_OscInitStruct->LSIState = RCC_LSI_ON; 2059 .loc 1 1139 5 is_stmt 1 view .LVU627 2060 .loc 1 1139 33 is_stmt 0 view .LVU628 2061 0042 0123 movs r3, #1 2062 0044 4361 str r3, [r0, #20] 2063 .L200: 1140:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } 1141:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** else ARM GAS /tmp/ccemvyj9.s page 63 1142:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 1143:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** RCC_OscInitStruct->LSIState = RCC_LSI_OFF; 1144:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } 1145:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 1146:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Get the PLL configuration -----------------------------------------------*/ 1147:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** if ((RCC->CR & RCC_CR_PLLON) == RCC_CR_PLLON) 2064 .loc 1 1147 3 is_stmt 1 view .LVU629 2065 .loc 1 1147 11 is_stmt 0 view .LVU630 2066 0046 254B ldr r3, .L203 2067 0048 1B68 ldr r3, [r3] 2068 .loc 1 1147 6 view .LVU631 2069 004a 13F0807F tst r3, #16777216 2070 004e 42D0 beq .L201 1148:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 1149:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** RCC_OscInitStruct->PLL.PLLState = RCC_PLL_ON; 2071 .loc 1 1149 5 is_stmt 1 view .LVU632 2072 .loc 1 1149 37 is_stmt 0 view .LVU633 2073 0050 0223 movs r3, #2 2074 0052 8361 str r3, [r0, #24] 2075 .L202: 1150:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } 1151:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** else 1152:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 1153:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** RCC_OscInitStruct->PLL.PLLState = RCC_PLL_OFF; 1154:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } 1155:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** RCC_OscInitStruct->PLL.PLLSource = (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC); 2076 .loc 1 1155 3 is_stmt 1 view .LVU634 2077 .loc 1 1155 52 is_stmt 0 view .LVU635 2078 0054 214A ldr r2, .L203 2079 0056 5368 ldr r3, [r2, #4] 2080 .loc 1 1155 38 view .LVU636 2081 0058 03F48003 and r3, r3, #4194304 2082 .loc 1 1155 36 view .LVU637 2083 005c C361 str r3, [r0, #28] 1156:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** RCC_OscInitStruct->PLL.PLLM = (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM); 2084 .loc 1 1156 3 is_stmt 1 view .LVU638 2085 .loc 1 1156 47 is_stmt 0 view .LVU639 2086 005e 5368 ldr r3, [r2, #4] 2087 .loc 1 1156 33 view .LVU640 2088 0060 03F03F03 and r3, r3, #63 2089 .loc 1 1156 31 view .LVU641 2090 0064 0362 str r3, [r0, #32] 1157:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** RCC_OscInitStruct->PLL.PLLN = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Po 2091 .loc 1 1157 3 is_stmt 1 view .LVU642 2092 .loc 1 1157 48 is_stmt 0 view .LVU643 2093 0066 5368 ldr r3, [r2, #4] 2094 .loc 1 1157 33 view .LVU644 2095 0068 C3F38813 ubfx r3, r3, #6, #9 2096 .loc 1 1157 31 view .LVU645 2097 006c 4362 str r3, [r0, #36] 1158:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** RCC_OscInitStruct->PLL.PLLP = (uint32_t)((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) + RCC_PLLCFGR_PLLP_0 2098 .loc 1 1158 3 is_stmt 1 view .LVU646 2099 .loc 1 1158 50 is_stmt 0 view .LVU647 2100 006e 5368 ldr r3, [r2, #4] 2101 .loc 1 1158 60 view .LVU648 2102 0070 03F44033 and r3, r3, #196608 2103 .loc 1 1158 80 view .LVU649 ARM GAS /tmp/ccemvyj9.s page 64 2104 0074 03F58033 add r3, r3, #65536 2105 .loc 1 1158 33 view .LVU650 2106 0078 DB0B lsrs r3, r3, #15 2107 .loc 1 1158 31 view .LVU651 2108 007a 8362 str r3, [r0, #40] 1159:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** RCC_OscInitStruct->PLL.PLLQ = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLQ) >> RCC_PLLCFGR_PLLQ_Po 2109 .loc 1 1159 3 is_stmt 1 view .LVU652 2110 .loc 1 1159 48 is_stmt 0 view .LVU653 2111 007c 5368 ldr r3, [r2, #4] 2112 .loc 1 1159 33 view .LVU654 2113 007e C3F30363 ubfx r3, r3, #24, #4 2114 .loc 1 1159 31 view .LVU655 2115 0082 C362 str r3, [r0, #44] 1160:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** #if defined (RCC_PLLCFGR_PLLR) 1161:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** RCC_OscInitStruct->PLL.PLLR = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> POSITION_VAL(RCC_PL 2116 .loc 1 1161 3 is_stmt 1 view .LVU656 2117 .loc 1 1161 48 is_stmt 0 view .LVU657 2118 0084 5368 ldr r3, [r2, #4] 2119 .loc 1 1161 58 view .LVU658 2120 0086 03F0E043 and r3, r3, #1879048192 2121 .LVL132: 2122 .LBB7: 2123 .LBI7: 2124 .file 2 "Drivers/CMSIS/Include/cmsis_gcc.h" 1:Drivers/CMSIS/Include/cmsis_gcc.h **** /**************************************************************************//** 2:Drivers/CMSIS/Include/cmsis_gcc.h **** * @file cmsis_gcc.h 3:Drivers/CMSIS/Include/cmsis_gcc.h **** * @brief CMSIS compiler GCC header file 4:Drivers/CMSIS/Include/cmsis_gcc.h **** * @version V5.0.4 5:Drivers/CMSIS/Include/cmsis_gcc.h **** * @date 09. April 2018 6:Drivers/CMSIS/Include/cmsis_gcc.h **** ******************************************************************************/ 7:Drivers/CMSIS/Include/cmsis_gcc.h **** /* 8:Drivers/CMSIS/Include/cmsis_gcc.h **** * Copyright (c) 2009-2018 Arm Limited. All rights reserved. 9:Drivers/CMSIS/Include/cmsis_gcc.h **** * 10:Drivers/CMSIS/Include/cmsis_gcc.h **** * SPDX-License-Identifier: Apache-2.0 11:Drivers/CMSIS/Include/cmsis_gcc.h **** * 12:Drivers/CMSIS/Include/cmsis_gcc.h **** * Licensed under the Apache License, Version 2.0 (the License); you may 13:Drivers/CMSIS/Include/cmsis_gcc.h **** * not use this file except in compliance with the License. 14:Drivers/CMSIS/Include/cmsis_gcc.h **** * You may obtain a copy of the License at 15:Drivers/CMSIS/Include/cmsis_gcc.h **** * 16:Drivers/CMSIS/Include/cmsis_gcc.h **** * www.apache.org/licenses/LICENSE-2.0 17:Drivers/CMSIS/Include/cmsis_gcc.h **** * 18:Drivers/CMSIS/Include/cmsis_gcc.h **** * Unless required by applicable law or agreed to in writing, software 19:Drivers/CMSIS/Include/cmsis_gcc.h **** * distributed under the License is distributed on an AS IS BASIS, WITHOUT 20:Drivers/CMSIS/Include/cmsis_gcc.h **** * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 21:Drivers/CMSIS/Include/cmsis_gcc.h **** * See the License for the specific language governing permissions and 22:Drivers/CMSIS/Include/cmsis_gcc.h **** * limitations under the License. 23:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 24:Drivers/CMSIS/Include/cmsis_gcc.h **** 25:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __CMSIS_GCC_H 26:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_H 27:Drivers/CMSIS/Include/cmsis_gcc.h **** 28:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ignore some GCC warnings */ 29:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push 30:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wsign-conversion" 31:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wconversion" 32:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wunused-parameter" 33:Drivers/CMSIS/Include/cmsis_gcc.h **** ARM GAS /tmp/ccemvyj9.s page 65 34:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Fallback for __has_builtin */ 35:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __has_builtin 36:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __has_builtin(x) (0) 37:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 38:Drivers/CMSIS/Include/cmsis_gcc.h **** 39:Drivers/CMSIS/Include/cmsis_gcc.h **** /* CMSIS compiler specific defines */ 40:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __ASM 41:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __ASM __asm 42:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 43:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __INLINE 44:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __INLINE inline 45:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 46:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __STATIC_INLINE 47:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __STATIC_INLINE static inline 48:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 49:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __STATIC_FORCEINLINE 50:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline 51:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 52:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __NO_RETURN 53:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __NO_RETURN __attribute__((__noreturn__)) 54:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 55:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __USED 56:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __USED __attribute__((used)) 57:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 58:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __WEAK 59:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __WEAK __attribute__((weak)) 60:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 61:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PACKED 62:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PACKED __attribute__((packed, aligned(1))) 63:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 64:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PACKED_STRUCT 65:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) 66:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 67:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PACKED_UNION 68:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PACKED_UNION union __attribute__((packed, aligned(1))) 69:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 70:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT32 /* deprecated */ 71:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push 72:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" 73:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" 74:Drivers/CMSIS/Include/cmsis_gcc.h **** struct __attribute__((packed)) T_UINT32 { uint32_t v; }; 75:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop 76:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) 77:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 78:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT16_WRITE 79:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push 80:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" 81:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" 82:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; 83:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop 84:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))- 85:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 86:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT16_READ 87:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push 88:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" 89:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" 90:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; ARM GAS /tmp/ccemvyj9.s page 66 91:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop 92:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(add 93:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 94:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT32_WRITE 95:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push 96:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" 97:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" 98:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; 99:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop 100:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))- 101:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 102:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT32_READ 103:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push 104:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" 105:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" 106:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; 107:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop 108:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(add 109:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 110:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __ALIGNED 111:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __ALIGNED(x) __attribute__((aligned(x))) 112:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 113:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __RESTRICT 114:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __RESTRICT __restrict 115:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 116:Drivers/CMSIS/Include/cmsis_gcc.h **** 117:Drivers/CMSIS/Include/cmsis_gcc.h **** 118:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ########################### Core Function Access ########################### */ 119:Drivers/CMSIS/Include/cmsis_gcc.h **** /** \ingroup CMSIS_Core_FunctionInterface 120:Drivers/CMSIS/Include/cmsis_gcc.h **** \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions 121:Drivers/CMSIS/Include/cmsis_gcc.h **** @{ 122:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 123:Drivers/CMSIS/Include/cmsis_gcc.h **** 124:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 125:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Enable IRQ Interrupts 126:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Enables IRQ interrupts by clearing the I-bit in the CPSR. 127:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes. 128:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 129:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __enable_irq(void) 130:Drivers/CMSIS/Include/cmsis_gcc.h **** { 131:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsie i" : : : "memory"); 132:Drivers/CMSIS/Include/cmsis_gcc.h **** } 133:Drivers/CMSIS/Include/cmsis_gcc.h **** 134:Drivers/CMSIS/Include/cmsis_gcc.h **** 135:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 136:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Disable IRQ Interrupts 137:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Disables IRQ interrupts by setting the I-bit in the CPSR. 138:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes. 139:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 140:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __disable_irq(void) 141:Drivers/CMSIS/Include/cmsis_gcc.h **** { 142:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsid i" : : : "memory"); 143:Drivers/CMSIS/Include/cmsis_gcc.h **** } 144:Drivers/CMSIS/Include/cmsis_gcc.h **** 145:Drivers/CMSIS/Include/cmsis_gcc.h **** 146:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 147:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Control Register ARM GAS /tmp/ccemvyj9.s page 67 148:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the Control Register. 149:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Control Register value 150:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 151:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_CONTROL(void) 152:Drivers/CMSIS/Include/cmsis_gcc.h **** { 153:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 154:Drivers/CMSIS/Include/cmsis_gcc.h **** 155:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, control" : "=r" (result) ); 156:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 157:Drivers/CMSIS/Include/cmsis_gcc.h **** } 158:Drivers/CMSIS/Include/cmsis_gcc.h **** 159:Drivers/CMSIS/Include/cmsis_gcc.h **** 160:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) 161:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 162:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Control Register (non-secure) 163:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the non-secure Control Register when in secure mode. 164:Drivers/CMSIS/Include/cmsis_gcc.h **** \return non-secure Control Register value 165:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 166:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) 167:Drivers/CMSIS/Include/cmsis_gcc.h **** { 168:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 169:Drivers/CMSIS/Include/cmsis_gcc.h **** 170:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); 171:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 172:Drivers/CMSIS/Include/cmsis_gcc.h **** } 173:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 174:Drivers/CMSIS/Include/cmsis_gcc.h **** 175:Drivers/CMSIS/Include/cmsis_gcc.h **** 176:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 177:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Control Register 178:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Writes the given value to the Control Register. 179:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] control Control Register value to set 180:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 181:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) 182:Drivers/CMSIS/Include/cmsis_gcc.h **** { 183:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); 184:Drivers/CMSIS/Include/cmsis_gcc.h **** } 185:Drivers/CMSIS/Include/cmsis_gcc.h **** 186:Drivers/CMSIS/Include/cmsis_gcc.h **** 187:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) 188:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 189:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Control Register (non-secure) 190:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Writes the given value to the non-secure Control Register when in secure state. 191:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] control Control Register value to set 192:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 193:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) 194:Drivers/CMSIS/Include/cmsis_gcc.h **** { 195:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); 196:Drivers/CMSIS/Include/cmsis_gcc.h **** } 197:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 198:Drivers/CMSIS/Include/cmsis_gcc.h **** 199:Drivers/CMSIS/Include/cmsis_gcc.h **** 200:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 201:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get IPSR Register 202:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the IPSR Register. 203:Drivers/CMSIS/Include/cmsis_gcc.h **** \return IPSR Register value 204:Drivers/CMSIS/Include/cmsis_gcc.h **** */ ARM GAS /tmp/ccemvyj9.s page 68 205:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_IPSR(void) 206:Drivers/CMSIS/Include/cmsis_gcc.h **** { 207:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 208:Drivers/CMSIS/Include/cmsis_gcc.h **** 209:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); 210:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 211:Drivers/CMSIS/Include/cmsis_gcc.h **** } 212:Drivers/CMSIS/Include/cmsis_gcc.h **** 213:Drivers/CMSIS/Include/cmsis_gcc.h **** 214:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 215:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get APSR Register 216:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the APSR Register. 217:Drivers/CMSIS/Include/cmsis_gcc.h **** \return APSR Register value 218:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 219:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_APSR(void) 220:Drivers/CMSIS/Include/cmsis_gcc.h **** { 221:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 222:Drivers/CMSIS/Include/cmsis_gcc.h **** 223:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, apsr" : "=r" (result) ); 224:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 225:Drivers/CMSIS/Include/cmsis_gcc.h **** } 226:Drivers/CMSIS/Include/cmsis_gcc.h **** 227:Drivers/CMSIS/Include/cmsis_gcc.h **** 228:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 229:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get xPSR Register 230:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the xPSR Register. 231:Drivers/CMSIS/Include/cmsis_gcc.h **** \return xPSR Register value 232:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 233:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_xPSR(void) 234:Drivers/CMSIS/Include/cmsis_gcc.h **** { 235:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 236:Drivers/CMSIS/Include/cmsis_gcc.h **** 237:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); 238:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 239:Drivers/CMSIS/Include/cmsis_gcc.h **** } 240:Drivers/CMSIS/Include/cmsis_gcc.h **** 241:Drivers/CMSIS/Include/cmsis_gcc.h **** 242:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 243:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Process Stack Pointer 244:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Process Stack Pointer (PSP). 245:Drivers/CMSIS/Include/cmsis_gcc.h **** \return PSP Register value 246:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 247:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_PSP(void) 248:Drivers/CMSIS/Include/cmsis_gcc.h **** { 249:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 250:Drivers/CMSIS/Include/cmsis_gcc.h **** 251:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, psp" : "=r" (result) ); 252:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 253:Drivers/CMSIS/Include/cmsis_gcc.h **** } 254:Drivers/CMSIS/Include/cmsis_gcc.h **** 255:Drivers/CMSIS/Include/cmsis_gcc.h **** 256:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) 257:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 258:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Process Stack Pointer (non-secure) 259:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure s 260:Drivers/CMSIS/Include/cmsis_gcc.h **** \return PSP Register value 261:Drivers/CMSIS/Include/cmsis_gcc.h **** */ ARM GAS /tmp/ccemvyj9.s page 69 262:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) 263:Drivers/CMSIS/Include/cmsis_gcc.h **** { 264:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 265:Drivers/CMSIS/Include/cmsis_gcc.h **** 266:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); 267:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 268:Drivers/CMSIS/Include/cmsis_gcc.h **** } 269:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 270:Drivers/CMSIS/Include/cmsis_gcc.h **** 271:Drivers/CMSIS/Include/cmsis_gcc.h **** 272:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 273:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Process Stack Pointer 274:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Process Stack Pointer (PSP). 275:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfProcStack Process Stack Pointer value to set 276:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 277:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) 278:Drivers/CMSIS/Include/cmsis_gcc.h **** { 279:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); 280:Drivers/CMSIS/Include/cmsis_gcc.h **** } 281:Drivers/CMSIS/Include/cmsis_gcc.h **** 282:Drivers/CMSIS/Include/cmsis_gcc.h **** 283:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) 284:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 285:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Process Stack Pointer (non-secure) 286:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure sta 287:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfProcStack Process Stack Pointer value to set 288:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 289:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) 290:Drivers/CMSIS/Include/cmsis_gcc.h **** { 291:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); 292:Drivers/CMSIS/Include/cmsis_gcc.h **** } 293:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 294:Drivers/CMSIS/Include/cmsis_gcc.h **** 295:Drivers/CMSIS/Include/cmsis_gcc.h **** 296:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 297:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Main Stack Pointer 298:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Main Stack Pointer (MSP). 299:Drivers/CMSIS/Include/cmsis_gcc.h **** \return MSP Register value 300:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 301:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_MSP(void) 302:Drivers/CMSIS/Include/cmsis_gcc.h **** { 303:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 304:Drivers/CMSIS/Include/cmsis_gcc.h **** 305:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, msp" : "=r" (result) ); 306:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 307:Drivers/CMSIS/Include/cmsis_gcc.h **** } 308:Drivers/CMSIS/Include/cmsis_gcc.h **** 309:Drivers/CMSIS/Include/cmsis_gcc.h **** 310:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) 311:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 312:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Main Stack Pointer (non-secure) 313:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure stat 314:Drivers/CMSIS/Include/cmsis_gcc.h **** \return MSP Register value 315:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 316:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) 317:Drivers/CMSIS/Include/cmsis_gcc.h **** { 318:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; ARM GAS /tmp/ccemvyj9.s page 70 319:Drivers/CMSIS/Include/cmsis_gcc.h **** 320:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); 321:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 322:Drivers/CMSIS/Include/cmsis_gcc.h **** } 323:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 324:Drivers/CMSIS/Include/cmsis_gcc.h **** 325:Drivers/CMSIS/Include/cmsis_gcc.h **** 326:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 327:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Main Stack Pointer 328:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Main Stack Pointer (MSP). 329:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfMainStack Main Stack Pointer value to set 330:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 331:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) 332:Drivers/CMSIS/Include/cmsis_gcc.h **** { 333:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); 334:Drivers/CMSIS/Include/cmsis_gcc.h **** } 335:Drivers/CMSIS/Include/cmsis_gcc.h **** 336:Drivers/CMSIS/Include/cmsis_gcc.h **** 337:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) 338:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 339:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Main Stack Pointer (non-secure) 340:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. 341:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfMainStack Main Stack Pointer value to set 342:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 343:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) 344:Drivers/CMSIS/Include/cmsis_gcc.h **** { 345:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); 346:Drivers/CMSIS/Include/cmsis_gcc.h **** } 347:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 348:Drivers/CMSIS/Include/cmsis_gcc.h **** 349:Drivers/CMSIS/Include/cmsis_gcc.h **** 350:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) 351:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 352:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Stack Pointer (non-secure) 353:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. 354:Drivers/CMSIS/Include/cmsis_gcc.h **** \return SP Register value 355:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 356:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) 357:Drivers/CMSIS/Include/cmsis_gcc.h **** { 358:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 359:Drivers/CMSIS/Include/cmsis_gcc.h **** 360:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); 361:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 362:Drivers/CMSIS/Include/cmsis_gcc.h **** } 363:Drivers/CMSIS/Include/cmsis_gcc.h **** 364:Drivers/CMSIS/Include/cmsis_gcc.h **** 365:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 366:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Stack Pointer (non-secure) 367:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. 368:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfStack Stack Pointer value to set 369:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 370:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) 371:Drivers/CMSIS/Include/cmsis_gcc.h **** { 372:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); 373:Drivers/CMSIS/Include/cmsis_gcc.h **** } 374:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 375:Drivers/CMSIS/Include/cmsis_gcc.h **** ARM GAS /tmp/ccemvyj9.s page 71 376:Drivers/CMSIS/Include/cmsis_gcc.h **** 377:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 378:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Priority Mask 379:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current state of the priority mask bit from the Priority Mask Register. 380:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Priority Mask value 381:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 382:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) 383:Drivers/CMSIS/Include/cmsis_gcc.h **** { 384:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 385:Drivers/CMSIS/Include/cmsis_gcc.h **** 386:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); 387:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 388:Drivers/CMSIS/Include/cmsis_gcc.h **** } 389:Drivers/CMSIS/Include/cmsis_gcc.h **** 390:Drivers/CMSIS/Include/cmsis_gcc.h **** 391:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) 392:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 393:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Priority Mask (non-secure) 394:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current state of the non-secure priority mask bit from the Priority Mask Reg 395:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Priority Mask value 396:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 397:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) 398:Drivers/CMSIS/Include/cmsis_gcc.h **** { 399:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 400:Drivers/CMSIS/Include/cmsis_gcc.h **** 401:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, primask_ns" : "=r" (result) :: "memory"); 402:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 403:Drivers/CMSIS/Include/cmsis_gcc.h **** } 404:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 405:Drivers/CMSIS/Include/cmsis_gcc.h **** 406:Drivers/CMSIS/Include/cmsis_gcc.h **** 407:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 408:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Priority Mask 409:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Priority Mask Register. 410:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] priMask Priority Mask 411:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 412:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) 413:Drivers/CMSIS/Include/cmsis_gcc.h **** { 414:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); 415:Drivers/CMSIS/Include/cmsis_gcc.h **** } 416:Drivers/CMSIS/Include/cmsis_gcc.h **** 417:Drivers/CMSIS/Include/cmsis_gcc.h **** 418:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) 419:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 420:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Priority Mask (non-secure) 421:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Priority Mask Register when in secure state. 422:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] priMask Priority Mask 423:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 424:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) 425:Drivers/CMSIS/Include/cmsis_gcc.h **** { 426:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); 427:Drivers/CMSIS/Include/cmsis_gcc.h **** } 428:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 429:Drivers/CMSIS/Include/cmsis_gcc.h **** 430:Drivers/CMSIS/Include/cmsis_gcc.h **** 431:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ 432:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ ARM GAS /tmp/ccemvyj9.s page 72 433:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) 434:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 435:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Enable FIQ 436:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Enables FIQ interrupts by clearing the F-bit in the CPSR. 437:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes. 438:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 439:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __enable_fault_irq(void) 440:Drivers/CMSIS/Include/cmsis_gcc.h **** { 441:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsie f" : : : "memory"); 442:Drivers/CMSIS/Include/cmsis_gcc.h **** } 443:Drivers/CMSIS/Include/cmsis_gcc.h **** 444:Drivers/CMSIS/Include/cmsis_gcc.h **** 445:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 446:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Disable FIQ 447:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Disables FIQ interrupts by setting the F-bit in the CPSR. 448:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes. 449:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 450:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __disable_fault_irq(void) 451:Drivers/CMSIS/Include/cmsis_gcc.h **** { 452:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsid f" : : : "memory"); 453:Drivers/CMSIS/Include/cmsis_gcc.h **** } 454:Drivers/CMSIS/Include/cmsis_gcc.h **** 455:Drivers/CMSIS/Include/cmsis_gcc.h **** 456:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 457:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Base Priority 458:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Base Priority register. 459:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Base Priority register value 460:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 461:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) 462:Drivers/CMSIS/Include/cmsis_gcc.h **** { 463:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 464:Drivers/CMSIS/Include/cmsis_gcc.h **** 465:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, basepri" : "=r" (result) ); 466:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 467:Drivers/CMSIS/Include/cmsis_gcc.h **** } 468:Drivers/CMSIS/Include/cmsis_gcc.h **** 469:Drivers/CMSIS/Include/cmsis_gcc.h **** 470:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) 471:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 472:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Base Priority (non-secure) 473:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Base Priority register when in secure state. 474:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Base Priority register value 475:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 476:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) 477:Drivers/CMSIS/Include/cmsis_gcc.h **** { 478:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 479:Drivers/CMSIS/Include/cmsis_gcc.h **** 480:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); 481:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 482:Drivers/CMSIS/Include/cmsis_gcc.h **** } 483:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 484:Drivers/CMSIS/Include/cmsis_gcc.h **** 485:Drivers/CMSIS/Include/cmsis_gcc.h **** 486:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 487:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Base Priority 488:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Base Priority register. 489:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] basePri Base Priority value to set ARM GAS /tmp/ccemvyj9.s page 73 490:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 491:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) 492:Drivers/CMSIS/Include/cmsis_gcc.h **** { 493:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); 494:Drivers/CMSIS/Include/cmsis_gcc.h **** } 495:Drivers/CMSIS/Include/cmsis_gcc.h **** 496:Drivers/CMSIS/Include/cmsis_gcc.h **** 497:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) 498:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 499:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Base Priority (non-secure) 500:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Base Priority register when in secure state. 501:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] basePri Base Priority value to set 502:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 503:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) 504:Drivers/CMSIS/Include/cmsis_gcc.h **** { 505:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); 506:Drivers/CMSIS/Include/cmsis_gcc.h **** } 507:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 508:Drivers/CMSIS/Include/cmsis_gcc.h **** 509:Drivers/CMSIS/Include/cmsis_gcc.h **** 510:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 511:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Base Priority with condition 512:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Base Priority register only if BASEPRI masking is disable 513:Drivers/CMSIS/Include/cmsis_gcc.h **** or the new value increases the BASEPRI priority level. 514:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] basePri Base Priority value to set 515:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 516:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) 517:Drivers/CMSIS/Include/cmsis_gcc.h **** { 518:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); 519:Drivers/CMSIS/Include/cmsis_gcc.h **** } 520:Drivers/CMSIS/Include/cmsis_gcc.h **** 521:Drivers/CMSIS/Include/cmsis_gcc.h **** 522:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 523:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Fault Mask 524:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Fault Mask register. 525:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Fault Mask register value 526:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 527:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) 528:Drivers/CMSIS/Include/cmsis_gcc.h **** { 529:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 530:Drivers/CMSIS/Include/cmsis_gcc.h **** 531:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); 532:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 533:Drivers/CMSIS/Include/cmsis_gcc.h **** } 534:Drivers/CMSIS/Include/cmsis_gcc.h **** 535:Drivers/CMSIS/Include/cmsis_gcc.h **** 536:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) 537:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 538:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Fault Mask (non-secure) 539:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Fault Mask register when in secure state. 540:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Fault Mask register value 541:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 542:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) 543:Drivers/CMSIS/Include/cmsis_gcc.h **** { 544:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 545:Drivers/CMSIS/Include/cmsis_gcc.h **** 546:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); ARM GAS /tmp/ccemvyj9.s page 74 547:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 548:Drivers/CMSIS/Include/cmsis_gcc.h **** } 549:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 550:Drivers/CMSIS/Include/cmsis_gcc.h **** 551:Drivers/CMSIS/Include/cmsis_gcc.h **** 552:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 553:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Fault Mask 554:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Fault Mask register. 555:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] faultMask Fault Mask value to set 556:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 557:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) 558:Drivers/CMSIS/Include/cmsis_gcc.h **** { 559:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); 560:Drivers/CMSIS/Include/cmsis_gcc.h **** } 561:Drivers/CMSIS/Include/cmsis_gcc.h **** 562:Drivers/CMSIS/Include/cmsis_gcc.h **** 563:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) 564:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 565:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Fault Mask (non-secure) 566:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Fault Mask register when in secure state. 567:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] faultMask Fault Mask value to set 568:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 569:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) 570:Drivers/CMSIS/Include/cmsis_gcc.h **** { 571:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); 572:Drivers/CMSIS/Include/cmsis_gcc.h **** } 573:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 574:Drivers/CMSIS/Include/cmsis_gcc.h **** 575:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ 576:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ 577:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ 578:Drivers/CMSIS/Include/cmsis_gcc.h **** 579:Drivers/CMSIS/Include/cmsis_gcc.h **** 580:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ 581:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) 582:Drivers/CMSIS/Include/cmsis_gcc.h **** 583:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 584:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Process Stack Pointer Limit 585:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure 586:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence zero is returned always in non-secure 587:Drivers/CMSIS/Include/cmsis_gcc.h **** mode. 588:Drivers/CMSIS/Include/cmsis_gcc.h **** 589:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). 590:Drivers/CMSIS/Include/cmsis_gcc.h **** \return PSPLIM Register value 591:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 592:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) 593:Drivers/CMSIS/Include/cmsis_gcc.h **** { 594:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ 595:Drivers/CMSIS/Include/cmsis_gcc.h **** (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) 596:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure PSPLIM is RAZ/WI 597:Drivers/CMSIS/Include/cmsis_gcc.h **** return 0U; 598:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 599:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 600:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, psplim" : "=r" (result) ); 601:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; 602:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 603:Drivers/CMSIS/Include/cmsis_gcc.h **** } ARM GAS /tmp/ccemvyj9.s page 75 604:Drivers/CMSIS/Include/cmsis_gcc.h **** 605:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) 606:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 607:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Process Stack Pointer Limit (non-secure) 608:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure 609:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence zero is returned always. 610:Drivers/CMSIS/Include/cmsis_gcc.h **** 611:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in 612:Drivers/CMSIS/Include/cmsis_gcc.h **** \return PSPLIM Register value 613:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 614:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) 615:Drivers/CMSIS/Include/cmsis_gcc.h **** { 616:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) 617:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure PSPLIM is RAZ/WI 618:Drivers/CMSIS/Include/cmsis_gcc.h **** return 0U; 619:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 620:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 621:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); 622:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; 623:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 624:Drivers/CMSIS/Include/cmsis_gcc.h **** } 625:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 626:Drivers/CMSIS/Include/cmsis_gcc.h **** 627:Drivers/CMSIS/Include/cmsis_gcc.h **** 628:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 629:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Process Stack Pointer Limit 630:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure 631:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence the write is silently ignored in non-secure 632:Drivers/CMSIS/Include/cmsis_gcc.h **** mode. 633:Drivers/CMSIS/Include/cmsis_gcc.h **** 634:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). 635:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set 636:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 637:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) 638:Drivers/CMSIS/Include/cmsis_gcc.h **** { 639:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ 640:Drivers/CMSIS/Include/cmsis_gcc.h **** (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) 641:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure PSPLIM is RAZ/WI 642:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)ProcStackPtrLimit; 643:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 644:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); 645:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 646:Drivers/CMSIS/Include/cmsis_gcc.h **** } 647:Drivers/CMSIS/Include/cmsis_gcc.h **** 648:Drivers/CMSIS/Include/cmsis_gcc.h **** 649:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) 650:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 651:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Process Stack Pointer (non-secure) 652:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure 653:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence the write is silently ignored. 654:Drivers/CMSIS/Include/cmsis_gcc.h **** 655:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in s 656:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set 657:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 658:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) 659:Drivers/CMSIS/Include/cmsis_gcc.h **** { 660:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) ARM GAS /tmp/ccemvyj9.s page 76 661:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure PSPLIM is RAZ/WI 662:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)ProcStackPtrLimit; 663:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 664:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); 665:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 666:Drivers/CMSIS/Include/cmsis_gcc.h **** } 667:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 668:Drivers/CMSIS/Include/cmsis_gcc.h **** 669:Drivers/CMSIS/Include/cmsis_gcc.h **** 670:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 671:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Main Stack Pointer Limit 672:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure 673:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence zero is returned always in non-secure 674:Drivers/CMSIS/Include/cmsis_gcc.h **** mode. 675:Drivers/CMSIS/Include/cmsis_gcc.h **** 676:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). 677:Drivers/CMSIS/Include/cmsis_gcc.h **** \return MSPLIM Register value 678:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 679:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) 680:Drivers/CMSIS/Include/cmsis_gcc.h **** { 681:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ 682:Drivers/CMSIS/Include/cmsis_gcc.h **** (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) 683:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure MSPLIM is RAZ/WI 684:Drivers/CMSIS/Include/cmsis_gcc.h **** return 0U; 685:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 686:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 687:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, msplim" : "=r" (result) ); 688:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; 689:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 690:Drivers/CMSIS/Include/cmsis_gcc.h **** } 691:Drivers/CMSIS/Include/cmsis_gcc.h **** 692:Drivers/CMSIS/Include/cmsis_gcc.h **** 693:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) 694:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 695:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Main Stack Pointer Limit (non-secure) 696:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure 697:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence zero is returned always. 698:Drivers/CMSIS/Include/cmsis_gcc.h **** 699:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in sec 700:Drivers/CMSIS/Include/cmsis_gcc.h **** \return MSPLIM Register value 701:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 702:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) 703:Drivers/CMSIS/Include/cmsis_gcc.h **** { 704:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) 705:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure MSPLIM is RAZ/WI 706:Drivers/CMSIS/Include/cmsis_gcc.h **** return 0U; 707:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 708:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 709:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); 710:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; 711:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 712:Drivers/CMSIS/Include/cmsis_gcc.h **** } 713:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 714:Drivers/CMSIS/Include/cmsis_gcc.h **** 715:Drivers/CMSIS/Include/cmsis_gcc.h **** 716:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 717:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Main Stack Pointer Limit ARM GAS /tmp/ccemvyj9.s page 77 718:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure 719:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence the write is silently ignored in non-secure 720:Drivers/CMSIS/Include/cmsis_gcc.h **** mode. 721:Drivers/CMSIS/Include/cmsis_gcc.h **** 722:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). 723:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set 724:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 725:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) 726:Drivers/CMSIS/Include/cmsis_gcc.h **** { 727:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ 728:Drivers/CMSIS/Include/cmsis_gcc.h **** (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) 729:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure MSPLIM is RAZ/WI 730:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)MainStackPtrLimit; 731:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 732:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); 733:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 734:Drivers/CMSIS/Include/cmsis_gcc.h **** } 735:Drivers/CMSIS/Include/cmsis_gcc.h **** 736:Drivers/CMSIS/Include/cmsis_gcc.h **** 737:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) 738:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 739:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Main Stack Pointer Limit (non-secure) 740:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure 741:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence the write is silently ignored. 742:Drivers/CMSIS/Include/cmsis_gcc.h **** 743:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secu 744:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] MainStackPtrLimit Main Stack Pointer value to set 745:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 746:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) 747:Drivers/CMSIS/Include/cmsis_gcc.h **** { 748:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) 749:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure MSPLIM is RAZ/WI 750:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)MainStackPtrLimit; 751:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 752:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); 753:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 754:Drivers/CMSIS/Include/cmsis_gcc.h **** } 755:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 756:Drivers/CMSIS/Include/cmsis_gcc.h **** 757:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ 758:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ 759:Drivers/CMSIS/Include/cmsis_gcc.h **** 760:Drivers/CMSIS/Include/cmsis_gcc.h **** 761:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 762:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get FPSCR 763:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Floating Point Status/Control register. 764:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Floating Point Status/Control register value 765:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 766:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_FPSCR(void) 767:Drivers/CMSIS/Include/cmsis_gcc.h **** { 768:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ 769:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) 770:Drivers/CMSIS/Include/cmsis_gcc.h **** #if __has_builtin(__builtin_arm_get_fpscr) 771:Drivers/CMSIS/Include/cmsis_gcc.h **** // Re-enable using built-in when GCC has been fixed 772:Drivers/CMSIS/Include/cmsis_gcc.h **** // || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) 773:Drivers/CMSIS/Include/cmsis_gcc.h **** /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ 774:Drivers/CMSIS/Include/cmsis_gcc.h **** return __builtin_arm_get_fpscr(); ARM GAS /tmp/ccemvyj9.s page 78 775:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 776:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 777:Drivers/CMSIS/Include/cmsis_gcc.h **** 778:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); 779:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 780:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 781:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 782:Drivers/CMSIS/Include/cmsis_gcc.h **** return(0U); 783:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 784:Drivers/CMSIS/Include/cmsis_gcc.h **** } 785:Drivers/CMSIS/Include/cmsis_gcc.h **** 786:Drivers/CMSIS/Include/cmsis_gcc.h **** 787:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 788:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set FPSCR 789:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Floating Point Status/Control register. 790:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] fpscr Floating Point Status/Control value to set 791:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 792:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) 793:Drivers/CMSIS/Include/cmsis_gcc.h **** { 794:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ 795:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) 796:Drivers/CMSIS/Include/cmsis_gcc.h **** #if __has_builtin(__builtin_arm_set_fpscr) 797:Drivers/CMSIS/Include/cmsis_gcc.h **** // Re-enable using built-in when GCC has been fixed 798:Drivers/CMSIS/Include/cmsis_gcc.h **** // || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) 799:Drivers/CMSIS/Include/cmsis_gcc.h **** /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ 800:Drivers/CMSIS/Include/cmsis_gcc.h **** __builtin_arm_set_fpscr(fpscr); 801:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 802:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory"); 803:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 804:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 805:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)fpscr; 806:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 807:Drivers/CMSIS/Include/cmsis_gcc.h **** } 808:Drivers/CMSIS/Include/cmsis_gcc.h **** 809:Drivers/CMSIS/Include/cmsis_gcc.h **** 810:Drivers/CMSIS/Include/cmsis_gcc.h **** /*@} end of CMSIS_Core_RegAccFunctions */ 811:Drivers/CMSIS/Include/cmsis_gcc.h **** 812:Drivers/CMSIS/Include/cmsis_gcc.h **** 813:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ########################## Core Instruction Access ######################### */ 814:Drivers/CMSIS/Include/cmsis_gcc.h **** /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface 815:Drivers/CMSIS/Include/cmsis_gcc.h **** Access to dedicated instructions 816:Drivers/CMSIS/Include/cmsis_gcc.h **** @{ 817:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 818:Drivers/CMSIS/Include/cmsis_gcc.h **** 819:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Define macros for porting to both thumb1 and thumb2. 820:Drivers/CMSIS/Include/cmsis_gcc.h **** * For thumb1, use low register (r0-r7), specified by constraint "l" 821:Drivers/CMSIS/Include/cmsis_gcc.h **** * Otherwise, use general registers, specified by constraint "r" */ 822:Drivers/CMSIS/Include/cmsis_gcc.h **** #if defined (__thumb__) && !defined (__thumb2__) 823:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_OUT_REG(r) "=l" (r) 824:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_RW_REG(r) "+l" (r) 825:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_USE_REG(r) "l" (r) 826:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 827:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_OUT_REG(r) "=r" (r) 828:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_RW_REG(r) "+r" (r) 829:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_USE_REG(r) "r" (r) 830:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 831:Drivers/CMSIS/Include/cmsis_gcc.h **** ARM GAS /tmp/ccemvyj9.s page 79 832:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 833:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief No Operation 834:Drivers/CMSIS/Include/cmsis_gcc.h **** \details No Operation does nothing. This instruction can be used for code alignment purposes. 835:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 836:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __NOP() __ASM volatile ("nop") 837:Drivers/CMSIS/Include/cmsis_gcc.h **** 838:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 839:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Wait For Interrupt 840:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Wait For Interrupt is a hint instruction that suspends execution until one of a number o 841:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 842:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __WFI() __ASM volatile ("wfi") 843:Drivers/CMSIS/Include/cmsis_gcc.h **** 844:Drivers/CMSIS/Include/cmsis_gcc.h **** 845:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 846:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Wait For Event 847:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Wait For Event is a hint instruction that permits the processor to enter 848:Drivers/CMSIS/Include/cmsis_gcc.h **** a low-power state until one of a number of events occurs. 849:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 850:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __WFE() __ASM volatile ("wfe") 851:Drivers/CMSIS/Include/cmsis_gcc.h **** 852:Drivers/CMSIS/Include/cmsis_gcc.h **** 853:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 854:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Send Event 855:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. 856:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 857:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __SEV() __ASM volatile ("sev") 858:Drivers/CMSIS/Include/cmsis_gcc.h **** 859:Drivers/CMSIS/Include/cmsis_gcc.h **** 860:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 861:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Instruction Synchronization Barrier 862:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Instruction Synchronization Barrier flushes the pipeline in the processor, 863:Drivers/CMSIS/Include/cmsis_gcc.h **** so that all instructions following the ISB are fetched from cache or memory, 864:Drivers/CMSIS/Include/cmsis_gcc.h **** after the instruction has been completed. 865:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 866:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __ISB(void) 867:Drivers/CMSIS/Include/cmsis_gcc.h **** { 868:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("isb 0xF":::"memory"); 869:Drivers/CMSIS/Include/cmsis_gcc.h **** } 870:Drivers/CMSIS/Include/cmsis_gcc.h **** 871:Drivers/CMSIS/Include/cmsis_gcc.h **** 872:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 873:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Data Synchronization Barrier 874:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Acts as a special kind of Data Memory Barrier. 875:Drivers/CMSIS/Include/cmsis_gcc.h **** It completes when all explicit memory accesses before this instruction complete. 876:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 877:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __DSB(void) 878:Drivers/CMSIS/Include/cmsis_gcc.h **** { 879:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("dsb 0xF":::"memory"); 880:Drivers/CMSIS/Include/cmsis_gcc.h **** } 881:Drivers/CMSIS/Include/cmsis_gcc.h **** 882:Drivers/CMSIS/Include/cmsis_gcc.h **** 883:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 884:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Data Memory Barrier 885:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Ensures the apparent order of the explicit memory operations before 886:Drivers/CMSIS/Include/cmsis_gcc.h **** and after the instruction, without ensuring their completion. 887:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 888:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __DMB(void) ARM GAS /tmp/ccemvyj9.s page 80 889:Drivers/CMSIS/Include/cmsis_gcc.h **** { 890:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("dmb 0xF":::"memory"); 891:Drivers/CMSIS/Include/cmsis_gcc.h **** } 892:Drivers/CMSIS/Include/cmsis_gcc.h **** 893:Drivers/CMSIS/Include/cmsis_gcc.h **** 894:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 895:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Reverse byte order (32 bit) 896:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x785 897:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to reverse 898:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Reversed value 899:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 900:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __REV(uint32_t value) 901:Drivers/CMSIS/Include/cmsis_gcc.h **** { 902:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) 903:Drivers/CMSIS/Include/cmsis_gcc.h **** return __builtin_bswap32(value); 904:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 905:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 906:Drivers/CMSIS/Include/cmsis_gcc.h **** 907:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); 908:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; 909:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 910:Drivers/CMSIS/Include/cmsis_gcc.h **** } 911:Drivers/CMSIS/Include/cmsis_gcc.h **** 912:Drivers/CMSIS/Include/cmsis_gcc.h **** 913:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 914:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Reverse byte order (16 bit) 915:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 916:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to reverse 917:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Reversed value 918:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 919:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __REV16(uint32_t value) 920:Drivers/CMSIS/Include/cmsis_gcc.h **** { 921:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 922:Drivers/CMSIS/Include/cmsis_gcc.h **** 923:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); 924:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; 925:Drivers/CMSIS/Include/cmsis_gcc.h **** } 926:Drivers/CMSIS/Include/cmsis_gcc.h **** 927:Drivers/CMSIS/Include/cmsis_gcc.h **** 928:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 929:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Reverse byte order (16 bit) 930:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For exam 931:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to reverse 932:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Reversed value 933:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 934:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE int16_t __REVSH(int16_t value) 935:Drivers/CMSIS/Include/cmsis_gcc.h **** { 936:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) 937:Drivers/CMSIS/Include/cmsis_gcc.h **** return (int16_t)__builtin_bswap16(value); 938:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 939:Drivers/CMSIS/Include/cmsis_gcc.h **** int16_t result; 940:Drivers/CMSIS/Include/cmsis_gcc.h **** 941:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); 942:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; 943:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 944:Drivers/CMSIS/Include/cmsis_gcc.h **** } 945:Drivers/CMSIS/Include/cmsis_gcc.h **** ARM GAS /tmp/ccemvyj9.s page 81 946:Drivers/CMSIS/Include/cmsis_gcc.h **** 947:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 948:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Rotate Right in unsigned value (32 bit) 949:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Rotate Right (immediate) provides the value of the contents of a register rotated by a v 950:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] op1 Value to rotate 951:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] op2 Number of Bits to rotate 952:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Rotated value 953:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 954:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) 955:Drivers/CMSIS/Include/cmsis_gcc.h **** { 956:Drivers/CMSIS/Include/cmsis_gcc.h **** op2 %= 32U; 957:Drivers/CMSIS/Include/cmsis_gcc.h **** if (op2 == 0U) 958:Drivers/CMSIS/Include/cmsis_gcc.h **** { 959:Drivers/CMSIS/Include/cmsis_gcc.h **** return op1; 960:Drivers/CMSIS/Include/cmsis_gcc.h **** } 961:Drivers/CMSIS/Include/cmsis_gcc.h **** return (op1 >> op2) | (op1 << (32U - op2)); 962:Drivers/CMSIS/Include/cmsis_gcc.h **** } 963:Drivers/CMSIS/Include/cmsis_gcc.h **** 964:Drivers/CMSIS/Include/cmsis_gcc.h **** 965:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 966:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Breakpoint 967:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Causes the processor to enter Debug state. 968:Drivers/CMSIS/Include/cmsis_gcc.h **** Debug tools can use this to investigate system state when the instruction at a particula 969:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value is ignored by the processor. 970:Drivers/CMSIS/Include/cmsis_gcc.h **** If required, a debugger can use it to store additional information about the break 971:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 972:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __BKPT(value) __ASM volatile ("bkpt "#value) 973:Drivers/CMSIS/Include/cmsis_gcc.h **** 974:Drivers/CMSIS/Include/cmsis_gcc.h **** 975:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 976:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Reverse bit order of value 977:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Reverses the bit order of the given value. 978:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to reverse 979:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Reversed value 980:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 981:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value) 2125 .loc 2 981 31 is_stmt 1 view .LVU659 2126 .LBB8: 982:Drivers/CMSIS/Include/cmsis_gcc.h **** { 983:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 2127 .loc 2 983 3 view .LVU660 984:Drivers/CMSIS/Include/cmsis_gcc.h **** 985:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ 986:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ 987:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) 988:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 2128 .loc 2 988 4 view .LVU661 2129 008a 4FF0E042 mov r2, #1879048192 2130 .syntax unified 2131 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 2132 008e 92FAA2F2 rbit r2, r2 2133 @ 0 "" 2 2134 .LVL133: 989:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 990:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ 991:Drivers/CMSIS/Include/cmsis_gcc.h **** 992:Drivers/CMSIS/Include/cmsis_gcc.h **** result = value; /* r will be reversed bits of v; first get LSB of v */ ARM GAS /tmp/ccemvyj9.s page 82 993:Drivers/CMSIS/Include/cmsis_gcc.h **** for (value >>= 1U; value != 0U; value >>= 1U) 994:Drivers/CMSIS/Include/cmsis_gcc.h **** { 995:Drivers/CMSIS/Include/cmsis_gcc.h **** result <<= 1U; 996:Drivers/CMSIS/Include/cmsis_gcc.h **** result |= value & 1U; 997:Drivers/CMSIS/Include/cmsis_gcc.h **** s--; 998:Drivers/CMSIS/Include/cmsis_gcc.h **** } 999:Drivers/CMSIS/Include/cmsis_gcc.h **** result <<= s; /* shift when v's highest bits are zero */ 1000:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 1001:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; 2135 .loc 2 1001 3 view .LVU662 2136 .loc 2 1001 3 is_stmt 0 view .LVU663 2137 .thumb 2138 .syntax unified 2139 .LBE8: 2140 .LBE7: 2141 .loc 1 1161 33 discriminator 2 view .LVU664 2142 0092 B2FA82F2 clz r2, r2 2143 0096 D340 lsrs r3, r3, r2 2144 .loc 1 1161 31 discriminator 2 view .LVU665 2145 0098 0363 str r3, [r0, #48] 1162:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** #endif 1163:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } 2146 .loc 1 1163 1 view .LVU666 2147 009a 7047 bx lr 2148 .L191: 1101:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 2149 .loc 1 1101 8 is_stmt 1 view .LVU667 1101:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 2150 .loc 1 1101 16 is_stmt 0 view .LVU668 2151 009c 0F4B ldr r3, .L203 2152 009e 1B68 ldr r3, [r3] 1101:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 2153 .loc 1 1101 11 view .LVU669 2154 00a0 13F4803F tst r3, #65536 2155 00a4 03D0 beq .L193 1103:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } 2156 .loc 1 1103 5 is_stmt 1 view .LVU670 1103:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } 2157 .loc 1 1103 33 is_stmt 0 view .LVU671 2158 00a6 4FF48033 mov r3, #65536 2159 00aa 4360 str r3, [r0, #4] 2160 00ac B2E7 b .L192 2161 .L193: 1107:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } 2162 .loc 1 1107 5 is_stmt 1 view .LVU672 1107:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } 2163 .loc 1 1107 33 is_stmt 0 view .LVU673 2164 00ae 0023 movs r3, #0 2165 00b0 4360 str r3, [r0, #4] 2166 00b2 AFE7 b .L192 2167 .L194: 1117:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } 2168 .loc 1 1117 5 is_stmt 1 view .LVU674 1117:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } 2169 .loc 1 1117 33 is_stmt 0 view .LVU675 2170 00b4 0023 movs r3, #0 2171 00b6 C360 str r3, [r0, #12] ARM GAS /tmp/ccemvyj9.s page 83 2172 00b8 B3E7 b .L195 2173 .L196: 1127:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 2174 .loc 1 1127 8 is_stmt 1 view .LVU676 1127:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 2175 .loc 1 1127 16 is_stmt 0 view .LVU677 2176 00ba 084B ldr r3, .L203 2177 00bc 1B6F ldr r3, [r3, #112] 1127:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 2178 .loc 1 1127 11 view .LVU678 2179 00be 13F0010F tst r3, #1 2180 00c2 02D0 beq .L198 1129:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } 2181 .loc 1 1129 5 is_stmt 1 view .LVU679 1129:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } 2182 .loc 1 1129 33 is_stmt 0 view .LVU680 2183 00c4 0123 movs r3, #1 2184 00c6 8360 str r3, [r0, #8] 2185 00c8 B6E7 b .L197 2186 .L198: 1133:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } 2187 .loc 1 1133 5 is_stmt 1 view .LVU681 1133:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } 2188 .loc 1 1133 33 is_stmt 0 view .LVU682 2189 00ca 0023 movs r3, #0 2190 00cc 8360 str r3, [r0, #8] 2191 00ce B3E7 b .L197 2192 .L199: 1143:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } 2193 .loc 1 1143 5 is_stmt 1 view .LVU683 1143:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } 2194 .loc 1 1143 33 is_stmt 0 view .LVU684 2195 00d0 0023 movs r3, #0 2196 00d2 4361 str r3, [r0, #20] 2197 00d4 B7E7 b .L200 2198 .L201: 1153:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } 2199 .loc 1 1153 5 is_stmt 1 view .LVU685 1153:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } 2200 .loc 1 1153 37 is_stmt 0 view .LVU686 2201 00d6 0123 movs r3, #1 2202 00d8 8361 str r3, [r0, #24] 2203 00da BBE7 b .L202 2204 .L204: 2205 .align 2 2206 .L203: 2207 00dc 00380240 .word 1073887232 2208 .cfi_endproc 2209 .LFE151: 2211 .section .text.HAL_RCC_GetClockConfig,"ax",%progbits 2212 .align 1 2213 .global HAL_RCC_GetClockConfig 2214 .syntax unified 2215 .thumb 2216 .thumb_func 2218 HAL_RCC_GetClockConfig: 2219 .LVL134: ARM GAS /tmp/ccemvyj9.s page 84 2220 .LFB152: 1164:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 1165:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /** 1166:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * @brief Configures the RCC_ClkInitStruct according to the internal 1167:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * RCC configuration registers. 1168:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * @param RCC_ClkInitStruct pointer to an RCC_ClkInitTypeDef structure that 1169:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * will be configured. 1170:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * @param pFLatency Pointer on the Flash Latency. 1171:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * @retval None 1172:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** */ 1173:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency) 1174:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 2221 .loc 1 1174 1 is_stmt 1 view -0 2222 .cfi_startproc 2223 @ args = 0, pretend = 0, frame = 0 2224 @ frame_needed = 0, uses_anonymous_args = 0 2225 @ link register save eliminated. 1175:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Set all possible values for the Clock type parameter --------------------*/ 1176:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | 2226 .loc 1 1176 3 view .LVU688 2227 .loc 1 1176 32 is_stmt 0 view .LVU689 2228 0000 0F23 movs r3, #15 2229 0002 0360 str r3, [r0] 1177:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 1178:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Get the SYSCLK configuration --------------------------------------------*/ 1179:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** RCC_ClkInitStruct->SYSCLKSource = (uint32_t)(RCC->CFGR & RCC_CFGR_SW); 2230 .loc 1 1179 3 is_stmt 1 view .LVU690 2231 .loc 1 1179 51 is_stmt 0 view .LVU691 2232 0004 0B4B ldr r3, .L206 2233 0006 9A68 ldr r2, [r3, #8] 2234 .loc 1 1179 37 view .LVU692 2235 0008 02F00302 and r2, r2, #3 2236 .loc 1 1179 35 view .LVU693 2237 000c 4260 str r2, [r0, #4] 1180:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 1181:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Get the HCLK configuration ----------------------------------------------*/ 1182:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_HPRE); 2238 .loc 1 1182 3 is_stmt 1 view .LVU694 2239 .loc 1 1182 52 is_stmt 0 view .LVU695 2240 000e 9A68 ldr r2, [r3, #8] 2241 .loc 1 1182 38 view .LVU696 2242 0010 02F0F002 and r2, r2, #240 2243 .loc 1 1182 36 view .LVU697 2244 0014 8260 str r2, [r0, #8] 1183:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 1184:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Get the APB1 configuration ----------------------------------------------*/ 1185:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_PPRE1); 2245 .loc 1 1185 3 is_stmt 1 view .LVU698 2246 .loc 1 1185 53 is_stmt 0 view .LVU699 2247 0016 9A68 ldr r2, [r3, #8] 2248 .loc 1 1185 39 view .LVU700 2249 0018 02F4E052 and r2, r2, #7168 2250 .loc 1 1185 37 view .LVU701 2251 001c C260 str r2, [r0, #12] 1186:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 1187:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Get the APB2 configuration ----------------------------------------------*/ 1188:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** RCC_ClkInitStruct->APB2CLKDivider = (uint32_t)((RCC->CFGR & RCC_CFGR_PPRE2) >> 3); ARM GAS /tmp/ccemvyj9.s page 85 2252 .loc 1 1188 3 is_stmt 1 view .LVU702 2253 .loc 1 1188 54 is_stmt 0 view .LVU703 2254 001e 9B68 ldr r3, [r3, #8] 2255 .loc 1 1188 39 view .LVU704 2256 0020 DB08 lsrs r3, r3, #3 2257 0022 03F4E053 and r3, r3, #7168 2258 .loc 1 1188 37 view .LVU705 2259 0026 0361 str r3, [r0, #16] 1189:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 1190:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Get the Flash Wait State (Latency) configuration ------------------------*/ 1191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** *pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY); 2260 .loc 1 1191 3 is_stmt 1 view .LVU706 2261 .loc 1 1191 32 is_stmt 0 view .LVU707 2262 0028 034B ldr r3, .L206+4 2263 002a 1B68 ldr r3, [r3] 2264 .loc 1 1191 16 view .LVU708 2265 002c 03F00F03 and r3, r3, #15 2266 .loc 1 1191 14 view .LVU709 2267 0030 0B60 str r3, [r1] 1192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } 2268 .loc 1 1192 1 view .LVU710 2269 0032 7047 bx lr 2270 .L207: 2271 .align 2 2272 .L206: 2273 0034 00380240 .word 1073887232 2274 0038 003C0240 .word 1073888256 2275 .cfi_endproc 2276 .LFE152: 2278 .section .text.HAL_RCC_CSSCallback,"ax",%progbits 2279 .align 1 2280 .weak HAL_RCC_CSSCallback 2281 .syntax unified 2282 .thumb 2283 .thumb_func 2285 HAL_RCC_CSSCallback: 2286 .LFB154: 1193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 1194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /** 1195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * @brief This function handles the RCC CSS interrupt request. 1196:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * @note This API should be called under the NMI_Handler(). 1197:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * @retval None 1198:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** */ 1199:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** void HAL_RCC_NMI_IRQHandler(void) 1200:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 1201:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Check RCC CSSF flag */ 1202:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** if (__HAL_RCC_GET_IT(RCC_IT_CSS)) 1203:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 1204:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* RCC Clock Security System interrupt user callback */ 1205:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** HAL_RCC_CSSCallback(); 1206:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 1207:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Clear RCC CSS pending bit */ 1208:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** __HAL_RCC_CLEAR_IT(RCC_IT_CSS); 1209:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } 1210:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } 1211:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 1212:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /** ARM GAS /tmp/ccemvyj9.s page 86 1213:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * @brief RCC Clock Security System interrupt callback 1214:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * @retval None 1215:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** */ 1216:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** __weak void HAL_RCC_CSSCallback(void) 1217:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 2287 .loc 1 1217 1 is_stmt 1 view -0 2288 .cfi_startproc 2289 @ args = 0, pretend = 0, frame = 0 2290 @ frame_needed = 0, uses_anonymous_args = 0 2291 @ link register save eliminated. 1218:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* NOTE : This function Should not be modified, when the callback is needed, 1219:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** the HAL_RCC_CSSCallback could be implemented in the user file 1220:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** */ 1221:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } 2292 .loc 1 1221 1 view .LVU712 2293 0000 7047 bx lr 2294 .cfi_endproc 2295 .LFE154: 2297 .section .text.HAL_RCC_NMI_IRQHandler,"ax",%progbits 2298 .align 1 2299 .global HAL_RCC_NMI_IRQHandler 2300 .syntax unified 2301 .thumb 2302 .thumb_func 2304 HAL_RCC_NMI_IRQHandler: 2305 .LFB153: 1200:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Check RCC CSSF flag */ 2306 .loc 1 1200 1 view -0 2307 .cfi_startproc 2308 @ args = 0, pretend = 0, frame = 0 2309 @ frame_needed = 0, uses_anonymous_args = 0 2310 0000 08B5 push {r3, lr} 2311 .LCFI17: 2312 .cfi_def_cfa_offset 8 2313 .cfi_offset 3, -8 2314 .cfi_offset 14, -4 1202:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 2315 .loc 1 1202 3 view .LVU714 1202:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 2316 .loc 1 1202 7 is_stmt 0 view .LVU715 2317 0002 064B ldr r3, .L213 2318 0004 DB68 ldr r3, [r3, #12] 1202:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { 2319 .loc 1 1202 6 view .LVU716 2320 0006 13F0800F tst r3, #128 2321 000a 00D1 bne .L212 2322 .L209: 1210:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 2323 .loc 1 1210 1 view .LVU717 2324 000c 08BD pop {r3, pc} 2325 .L212: 1205:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 2326 .loc 1 1205 5 is_stmt 1 view .LVU718 2327 000e FFF7FEFF bl HAL_RCC_CSSCallback 2328 .LVL135: 1208:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } 2329 .loc 1 1208 5 view .LVU719 ARM GAS /tmp/ccemvyj9.s page 87 2330 0012 024B ldr r3, .L213 2331 0014 8022 movs r2, #128 2332 0016 9A73 strb r2, [r3, #14] 1210:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** 2333 .loc 1 1210 1 is_stmt 0 view .LVU720 2334 0018 F8E7 b .L209 2335 .L214: 2336 001a 00BF .align 2 2337 .L213: 2338 001c 00380240 .word 1073887232 2339 .cfi_endproc 2340 .LFE153: 2342 .text 2343 .Letext0: 2344 .file 3 "/usr/lib/gcc/arm-none-eabi/13.2.1/include/stdint.h" 2345 .file 4 "Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h" 2346 .file 5 "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h" 2347 .file 6 "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h" 2348 .file 7 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h" 2349 .file 8 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h" 2350 .file 9 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h" 2351 .file 10 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h" 2352 .file 11 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h" ARM GAS /tmp/ccemvyj9.s page 88 DEFINED SYMBOLS *ABS*:00000000 stm32f7xx_hal_rcc.c /tmp/ccemvyj9.s:20 .text.HAL_RCC_DeInit:00000000 $t /tmp/ccemvyj9.s:26 .text.HAL_RCC_DeInit:00000000 HAL_RCC_DeInit /tmp/ccemvyj9.s:299 .text.HAL_RCC_DeInit:00000144 $d /tmp/ccemvyj9.s:308 .text.HAL_RCC_OscConfig:00000000 $t /tmp/ccemvyj9.s:314 .text.HAL_RCC_OscConfig:00000000 HAL_RCC_OscConfig /tmp/ccemvyj9.s:819 .text.HAL_RCC_OscConfig:0000026c $d /tmp/ccemvyj9.s:824 .text.HAL_RCC_OscConfig:00000274 $t /tmp/ccemvyj9.s:1214 .text.HAL_RCC_OscConfig:00000440 $d /tmp/ccemvyj9.s:1219 .text.HAL_RCC_MCOConfig:00000000 $t /tmp/ccemvyj9.s:1225 .text.HAL_RCC_MCOConfig:00000000 HAL_RCC_MCOConfig /tmp/ccemvyj9.s:1375 .text.HAL_RCC_MCOConfig:0000008c $d /tmp/ccemvyj9.s:1382 .text.HAL_RCC_EnableCSS:00000000 $t /tmp/ccemvyj9.s:1388 .text.HAL_RCC_EnableCSS:00000000 HAL_RCC_EnableCSS /tmp/ccemvyj9.s:1405 .text.HAL_RCC_EnableCSS:0000000c $d /tmp/ccemvyj9.s:1410 .text.HAL_RCC_DisableCSS:00000000 $t /tmp/ccemvyj9.s:1416 .text.HAL_RCC_DisableCSS:00000000 HAL_RCC_DisableCSS /tmp/ccemvyj9.s:1433 .text.HAL_RCC_DisableCSS:0000000c $d /tmp/ccemvyj9.s:1439 .text.HAL_RCC_GetSysClockFreq:00000000 $t /tmp/ccemvyj9.s:1445 .text.HAL_RCC_GetSysClockFreq:00000000 HAL_RCC_GetSysClockFreq /tmp/ccemvyj9.s:1562 .text.HAL_RCC_GetSysClockFreq:0000009c $d /tmp/ccemvyj9.s:1569 .text.HAL_RCC_ClockConfig:00000000 $t /tmp/ccemvyj9.s:1575 .text.HAL_RCC_ClockConfig:00000000 HAL_RCC_ClockConfig /tmp/ccemvyj9.s:1874 .text.HAL_RCC_ClockConfig:00000158 $d /tmp/ccemvyj9.s:1883 .text.HAL_RCC_GetHCLKFreq:00000000 $t /tmp/ccemvyj9.s:1889 .text.HAL_RCC_GetHCLKFreq:00000000 HAL_RCC_GetHCLKFreq /tmp/ccemvyj9.s:1904 .text.HAL_RCC_GetHCLKFreq:00000008 $d /tmp/ccemvyj9.s:1909 .text.HAL_RCC_GetPCLK1Freq:00000000 $t /tmp/ccemvyj9.s:1915 .text.HAL_RCC_GetPCLK1Freq:00000000 HAL_RCC_GetPCLK1Freq /tmp/ccemvyj9.s:1944 .text.HAL_RCC_GetPCLK1Freq:00000018 $d /tmp/ccemvyj9.s:1950 .text.HAL_RCC_GetPCLK2Freq:00000000 $t /tmp/ccemvyj9.s:1956 .text.HAL_RCC_GetPCLK2Freq:00000000 HAL_RCC_GetPCLK2Freq /tmp/ccemvyj9.s:1985 .text.HAL_RCC_GetPCLK2Freq:00000018 $d /tmp/ccemvyj9.s:1991 .text.HAL_RCC_GetOscConfig:00000000 $t /tmp/ccemvyj9.s:1997 .text.HAL_RCC_GetOscConfig:00000000 HAL_RCC_GetOscConfig /tmp/ccemvyj9.s:2207 .text.HAL_RCC_GetOscConfig:000000dc $d /tmp/ccemvyj9.s:2212 .text.HAL_RCC_GetClockConfig:00000000 $t /tmp/ccemvyj9.s:2218 .text.HAL_RCC_GetClockConfig:00000000 HAL_RCC_GetClockConfig /tmp/ccemvyj9.s:2273 .text.HAL_RCC_GetClockConfig:00000034 $d /tmp/ccemvyj9.s:2279 .text.HAL_RCC_CSSCallback:00000000 $t /tmp/ccemvyj9.s:2285 .text.HAL_RCC_CSSCallback:00000000 HAL_RCC_CSSCallback /tmp/ccemvyj9.s:2298 .text.HAL_RCC_NMI_IRQHandler:00000000 $t /tmp/ccemvyj9.s:2304 .text.HAL_RCC_NMI_IRQHandler:00000000 HAL_RCC_NMI_IRQHandler /tmp/ccemvyj9.s:2338 .text.HAL_RCC_NMI_IRQHandler:0000001c $d UNDEFINED SYMBOLS HAL_GetTick HAL_InitTick SystemCoreClock uwTickPrio HAL_GPIO_Init __aeabi_uldivmod AHBPrescTable APBPrescTable