ARM GAS /tmp/cc4hZZNo.s page 1 1 .cpu cortex-m7 2 .eabi_attribute 28, 1 3 .eabi_attribute 20, 1 4 .eabi_attribute 21, 1 5 .eabi_attribute 23, 3 6 .eabi_attribute 24, 1 7 .eabi_attribute 25, 1 8 .eabi_attribute 26, 1 9 .eabi_attribute 30, 1 10 .eabi_attribute 34, 1 11 .eabi_attribute 18, 4 12 .file "system_stm32f7xx.c" 13 .text 14 .Ltext0: 15 .cfi_sections .debug_frame 16 .section .text.SystemInit,"ax",%progbits 17 .align 1 18 .global SystemInit 19 .arch armv7e-m 20 .syntax unified 21 .thumb 22 .thumb_func 23 .fpu fpv5-d16 25 SystemInit: 26 .LFB141: 27 .file 1 "Src/system_stm32f7xx.c" 1:Src/system_stm32f7xx.c **** /** 2:Src/system_stm32f7xx.c **** ****************************************************************************** 3:Src/system_stm32f7xx.c **** * @file system_stm32f7xx.c 4:Src/system_stm32f7xx.c **** * @author MCD Application Team 5:Src/system_stm32f7xx.c **** * @brief CMSIS Cortex-M7 Device Peripheral Access Layer System Source File. 6:Src/system_stm32f7xx.c **** * 7:Src/system_stm32f7xx.c **** * This file provides two functions and one global variable to be called from 8:Src/system_stm32f7xx.c **** * user application: 9:Src/system_stm32f7xx.c **** * - SystemInit(): This function is called at startup just after reset and 10:Src/system_stm32f7xx.c **** * before branch to main program. This call is made inside 11:Src/system_stm32f7xx.c **** * the "startup_stm32f7xx.s" file. 12:Src/system_stm32f7xx.c **** * 13:Src/system_stm32f7xx.c **** * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used 14:Src/system_stm32f7xx.c **** * by the user application to setup the SysTick 15:Src/system_stm32f7xx.c **** * timer or configure other parameters. 16:Src/system_stm32f7xx.c **** * 17:Src/system_stm32f7xx.c **** * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must 18:Src/system_stm32f7xx.c **** * be called whenever the core clock is changed 19:Src/system_stm32f7xx.c **** * during program execution. 20:Src/system_stm32f7xx.c **** * 21:Src/system_stm32f7xx.c **** * 22:Src/system_stm32f7xx.c **** ****************************************************************************** 23:Src/system_stm32f7xx.c **** * @attention 24:Src/system_stm32f7xx.c **** * 25:Src/system_stm32f7xx.c **** * Copyright (c) 2016 STMicroelectronics. 26:Src/system_stm32f7xx.c **** * All rights reserved. 27:Src/system_stm32f7xx.c **** * 28:Src/system_stm32f7xx.c **** * This software is licensed under terms that can be found in the LICENSE file 29:Src/system_stm32f7xx.c **** * in the root directory of this software component. 30:Src/system_stm32f7xx.c **** * If no LICENSE file comes with this software, it is provided AS-IS. 31:Src/system_stm32f7xx.c **** * ARM GAS /tmp/cc4hZZNo.s page 2 32:Src/system_stm32f7xx.c **** ****************************************************************************** 33:Src/system_stm32f7xx.c **** */ 34:Src/system_stm32f7xx.c **** 35:Src/system_stm32f7xx.c **** /** @addtogroup CMSIS 36:Src/system_stm32f7xx.c **** * @{ 37:Src/system_stm32f7xx.c **** */ 38:Src/system_stm32f7xx.c **** 39:Src/system_stm32f7xx.c **** /** @addtogroup stm32f7xx_system 40:Src/system_stm32f7xx.c **** * @{ 41:Src/system_stm32f7xx.c **** */ 42:Src/system_stm32f7xx.c **** 43:Src/system_stm32f7xx.c **** /** @addtogroup STM32F7xx_System_Private_Includes 44:Src/system_stm32f7xx.c **** * @{ 45:Src/system_stm32f7xx.c **** */ 46:Src/system_stm32f7xx.c **** 47:Src/system_stm32f7xx.c **** #include "stm32f7xx.h" 48:Src/system_stm32f7xx.c **** 49:Src/system_stm32f7xx.c **** #if !defined (HSE_VALUE) 50:Src/system_stm32f7xx.c **** #define HSE_VALUE ((uint32_t)25000000) /*!< Default value of the External oscillator in Hz */ 51:Src/system_stm32f7xx.c **** #endif /* HSE_VALUE */ 52:Src/system_stm32f7xx.c **** 53:Src/system_stm32f7xx.c **** #if !defined (HSI_VALUE) 54:Src/system_stm32f7xx.c **** #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/ 55:Src/system_stm32f7xx.c **** #endif /* HSI_VALUE */ 56:Src/system_stm32f7xx.c **** 57:Src/system_stm32f7xx.c **** /** 58:Src/system_stm32f7xx.c **** * @} 59:Src/system_stm32f7xx.c **** */ 60:Src/system_stm32f7xx.c **** 61:Src/system_stm32f7xx.c **** /** @addtogroup STM32F7xx_System_Private_TypesDefinitions 62:Src/system_stm32f7xx.c **** * @{ 63:Src/system_stm32f7xx.c **** */ 64:Src/system_stm32f7xx.c **** 65:Src/system_stm32f7xx.c **** /** 66:Src/system_stm32f7xx.c **** * @} 67:Src/system_stm32f7xx.c **** */ 68:Src/system_stm32f7xx.c **** 69:Src/system_stm32f7xx.c **** /** @addtogroup STM32F7xx_System_Private_Defines 70:Src/system_stm32f7xx.c **** * @{ 71:Src/system_stm32f7xx.c **** */ 72:Src/system_stm32f7xx.c **** 73:Src/system_stm32f7xx.c **** /************************* Miscellaneous Configuration ************************/ 74:Src/system_stm32f7xx.c **** 75:Src/system_stm32f7xx.c **** /* Note: Following vector table addresses must be defined in line with linker 76:Src/system_stm32f7xx.c **** configuration. */ 77:Src/system_stm32f7xx.c **** /*!< Uncomment the following line if you need to relocate the vector table 78:Src/system_stm32f7xx.c **** anywhere in Flash or Sram, else the vector table is kept at the automatic 79:Src/system_stm32f7xx.c **** remap of boot address selected */ 80:Src/system_stm32f7xx.c **** /* #define USER_VECT_TAB_ADDRESS */ 81:Src/system_stm32f7xx.c **** 82:Src/system_stm32f7xx.c **** #if defined(USER_VECT_TAB_ADDRESS) 83:Src/system_stm32f7xx.c **** /*!< Uncomment the following line if you need to relocate your vector Table 84:Src/system_stm32f7xx.c **** in Sram else user remap will be done in Flash. */ 85:Src/system_stm32f7xx.c **** /* #define VECT_TAB_SRAM */ 86:Src/system_stm32f7xx.c **** #if defined(VECT_TAB_SRAM) 87:Src/system_stm32f7xx.c **** #define VECT_TAB_BASE_ADDRESS RAMDTCM_BASE /*!< Vector Table base address field. 88:Src/system_stm32f7xx.c **** This value must be a multiple of 0x200. */ ARM GAS /tmp/cc4hZZNo.s page 3 89:Src/system_stm32f7xx.c **** #define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field. 90:Src/system_stm32f7xx.c **** This value must be a multiple of 0x200. */ 91:Src/system_stm32f7xx.c **** #else 92:Src/system_stm32f7xx.c **** #define VECT_TAB_BASE_ADDRESS FLASH_BASE /*!< Vector Table base address field. 93:Src/system_stm32f7xx.c **** This value must be a multiple of 0x200. */ 94:Src/system_stm32f7xx.c **** #define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field. 95:Src/system_stm32f7xx.c **** This value must be a multiple of 0x200. */ 96:Src/system_stm32f7xx.c **** #endif /* VECT_TAB_SRAM */ 97:Src/system_stm32f7xx.c **** #endif /* USER_VECT_TAB_ADDRESS */ 98:Src/system_stm32f7xx.c **** /******************************************************************************/ 99:Src/system_stm32f7xx.c **** 100:Src/system_stm32f7xx.c **** /** 101:Src/system_stm32f7xx.c **** * @} 102:Src/system_stm32f7xx.c **** */ 103:Src/system_stm32f7xx.c **** 104:Src/system_stm32f7xx.c **** /** @addtogroup STM32F7xx_System_Private_Macros 105:Src/system_stm32f7xx.c **** * @{ 106:Src/system_stm32f7xx.c **** */ 107:Src/system_stm32f7xx.c **** 108:Src/system_stm32f7xx.c **** /** 109:Src/system_stm32f7xx.c **** * @} 110:Src/system_stm32f7xx.c **** */ 111:Src/system_stm32f7xx.c **** 112:Src/system_stm32f7xx.c **** /** @addtogroup STM32F7xx_System_Private_Variables 113:Src/system_stm32f7xx.c **** * @{ 114:Src/system_stm32f7xx.c **** */ 115:Src/system_stm32f7xx.c **** 116:Src/system_stm32f7xx.c **** /* This variable is updated in three ways: 117:Src/system_stm32f7xx.c **** 1) by calling CMSIS function SystemCoreClockUpdate() 118:Src/system_stm32f7xx.c **** 2) by calling HAL API function HAL_RCC_GetHCLKFreq() 119:Src/system_stm32f7xx.c **** 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency 120:Src/system_stm32f7xx.c **** Note: If you use this function to configure the system clock; then there 121:Src/system_stm32f7xx.c **** is no need to call the 2 first functions listed above, since SystemCoreClock 122:Src/system_stm32f7xx.c **** variable is updated automatically. 123:Src/system_stm32f7xx.c **** */ 124:Src/system_stm32f7xx.c **** uint32_t SystemCoreClock = 16000000; 125:Src/system_stm32f7xx.c **** const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; 126:Src/system_stm32f7xx.c **** const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4}; 127:Src/system_stm32f7xx.c **** 128:Src/system_stm32f7xx.c **** /** 129:Src/system_stm32f7xx.c **** * @} 130:Src/system_stm32f7xx.c **** */ 131:Src/system_stm32f7xx.c **** 132:Src/system_stm32f7xx.c **** /** @addtogroup STM32F7xx_System_Private_FunctionPrototypes 133:Src/system_stm32f7xx.c **** * @{ 134:Src/system_stm32f7xx.c **** */ 135:Src/system_stm32f7xx.c **** 136:Src/system_stm32f7xx.c **** /** 137:Src/system_stm32f7xx.c **** * @} 138:Src/system_stm32f7xx.c **** */ 139:Src/system_stm32f7xx.c **** 140:Src/system_stm32f7xx.c **** /** @addtogroup STM32F7xx_System_Private_Functions 141:Src/system_stm32f7xx.c **** * @{ 142:Src/system_stm32f7xx.c **** */ 143:Src/system_stm32f7xx.c **** 144:Src/system_stm32f7xx.c **** /** 145:Src/system_stm32f7xx.c **** * @brief Setup the microcontroller system ARM GAS /tmp/cc4hZZNo.s page 4 146:Src/system_stm32f7xx.c **** * Initialize the Embedded Flash Interface, the PLL and update the 147:Src/system_stm32f7xx.c **** * SystemFrequency variable. 148:Src/system_stm32f7xx.c **** * @param None 149:Src/system_stm32f7xx.c **** * @retval None 150:Src/system_stm32f7xx.c **** */ 151:Src/system_stm32f7xx.c **** void SystemInit(void) 152:Src/system_stm32f7xx.c **** { 28 .loc 1 152 1 view -0 29 .cfi_startproc 30 @ args = 0, pretend = 0, frame = 0 31 @ frame_needed = 0, uses_anonymous_args = 0 32 @ link register save eliminated. 153:Src/system_stm32f7xx.c **** /* FPU settings ------------------------------------------------------------*/ 154:Src/system_stm32f7xx.c **** #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) 155:Src/system_stm32f7xx.c **** SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ 33 .loc 1 155 3 view .LVU1 34 .loc 1 155 14 is_stmt 0 view .LVU2 35 0000 034A ldr r2, .L2 36 0002 D2F88830 ldr r3, [r2, #136] 37 0006 43F47003 orr r3, r3, #15728640 38 000a C2F88830 str r3, [r2, #136] 156:Src/system_stm32f7xx.c **** #endif 157:Src/system_stm32f7xx.c **** 158:Src/system_stm32f7xx.c **** /* Configure the Vector Table location -------------------------------------*/ 159:Src/system_stm32f7xx.c **** #if defined(USER_VECT_TAB_ADDRESS) 160:Src/system_stm32f7xx.c **** SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM 161:Src/system_stm32f7xx.c **** #endif /* USER_VECT_TAB_ADDRESS */ 162:Src/system_stm32f7xx.c **** } 39 .loc 1 162 1 view .LVU3 40 000e 7047 bx lr 41 .L3: 42 .align 2 43 .L2: 44 0010 00ED00E0 .word -536810240 45 .cfi_endproc 46 .LFE141: 48 .section .text.SystemCoreClockUpdate,"ax",%progbits 49 .align 1 50 .global SystemCoreClockUpdate 51 .syntax unified 52 .thumb 53 .thumb_func 54 .fpu fpv5-d16 56 SystemCoreClockUpdate: 57 .LFB142: 163:Src/system_stm32f7xx.c **** 164:Src/system_stm32f7xx.c **** /** 165:Src/system_stm32f7xx.c **** * @brief Update SystemCoreClock variable according to Clock Register Values. 166:Src/system_stm32f7xx.c **** * The SystemCoreClock variable contains the core clock (HCLK), it can 167:Src/system_stm32f7xx.c **** * be used by the user application to setup the SysTick timer or configure 168:Src/system_stm32f7xx.c **** * other parameters. 169:Src/system_stm32f7xx.c **** * 170:Src/system_stm32f7xx.c **** * @note Each time the core clock (HCLK) changes, this function must be called 171:Src/system_stm32f7xx.c **** * to update SystemCoreClock variable value. Otherwise, any configuration 172:Src/system_stm32f7xx.c **** * based on this variable will be incorrect. 173:Src/system_stm32f7xx.c **** * 174:Src/system_stm32f7xx.c **** * @note - The system frequency computed by this function is not the real ARM GAS /tmp/cc4hZZNo.s page 5 175:Src/system_stm32f7xx.c **** * frequency in the chip. It is calculated based on the predefined 176:Src/system_stm32f7xx.c **** * constant and the selected clock source: 177:Src/system_stm32f7xx.c **** * 178:Src/system_stm32f7xx.c **** * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) 179:Src/system_stm32f7xx.c **** * 180:Src/system_stm32f7xx.c **** * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) 181:Src/system_stm32f7xx.c **** * 182:Src/system_stm32f7xx.c **** * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) 183:Src/system_stm32f7xx.c **** * or HSI_VALUE(*) multiplied/divided by the PLL factors. 184:Src/system_stm32f7xx.c **** * 185:Src/system_stm32f7xx.c **** * (*) HSI_VALUE is a constant defined in stm32f7xx_hal_conf.h file (default value 186:Src/system_stm32f7xx.c **** * 16 MHz) but the real value may vary depending on the variations 187:Src/system_stm32f7xx.c **** * in voltage and temperature. 188:Src/system_stm32f7xx.c **** * 189:Src/system_stm32f7xx.c **** * (**) HSE_VALUE is a constant defined in stm32f7xx_hal_conf.h file (default value 190:Src/system_stm32f7xx.c **** * 25 MHz), user has to ensure that HSE_VALUE is same as the real 191:Src/system_stm32f7xx.c **** * frequency of the crystal used. Otherwise, this function may 192:Src/system_stm32f7xx.c **** * have wrong result. 193:Src/system_stm32f7xx.c **** * 194:Src/system_stm32f7xx.c **** * - The result of this function could be not correct when using fractional 195:Src/system_stm32f7xx.c **** * value for HSE crystal. 196:Src/system_stm32f7xx.c **** * 197:Src/system_stm32f7xx.c **** * @param None 198:Src/system_stm32f7xx.c **** * @retval None 199:Src/system_stm32f7xx.c **** */ 200:Src/system_stm32f7xx.c **** void SystemCoreClockUpdate(void) 201:Src/system_stm32f7xx.c **** { 58 .loc 1 201 1 is_stmt 1 view -0 59 .cfi_startproc 60 @ args = 0, pretend = 0, frame = 0 61 @ frame_needed = 0, uses_anonymous_args = 0 62 @ link register save eliminated. 202:Src/system_stm32f7xx.c **** uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2; 63 .loc 1 202 3 view .LVU5 64 .LVL0: 203:Src/system_stm32f7xx.c **** 204:Src/system_stm32f7xx.c **** /* Get SYSCLK source -------------------------------------------------------*/ 205:Src/system_stm32f7xx.c **** tmp = RCC->CFGR & RCC_CFGR_SWS; 65 .loc 1 205 3 view .LVU6 66 .loc 1 205 12 is_stmt 0 view .LVU7 67 0000 224B ldr r3, .L12 68 0002 9B68 ldr r3, [r3, #8] 69 .loc 1 205 7 view .LVU8 70 0004 03F00C03 and r3, r3, #12 71 .LVL1: 206:Src/system_stm32f7xx.c **** 207:Src/system_stm32f7xx.c **** switch (tmp) 72 .loc 1 207 3 is_stmt 1 view .LVU9 73 0008 042B cmp r3, #4 74 000a 14D0 beq .L5 75 000c 082B cmp r3, #8 76 000e 16D0 beq .L6 77 0010 1BB1 cbz r3, .L11 208:Src/system_stm32f7xx.c **** { 209:Src/system_stm32f7xx.c **** case 0x00: /* HSI used as system clock source */ 210:Src/system_stm32f7xx.c **** SystemCoreClock = HSI_VALUE; 211:Src/system_stm32f7xx.c **** break; ARM GAS /tmp/cc4hZZNo.s page 6 212:Src/system_stm32f7xx.c **** case 0x04: /* HSE used as system clock source */ 213:Src/system_stm32f7xx.c **** SystemCoreClock = HSE_VALUE; 214:Src/system_stm32f7xx.c **** break; 215:Src/system_stm32f7xx.c **** case 0x08: /* PLL used as system clock source */ 216:Src/system_stm32f7xx.c **** 217:Src/system_stm32f7xx.c **** /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N 218:Src/system_stm32f7xx.c **** SYSCLK = PLL_VCO / PLL_P 219:Src/system_stm32f7xx.c **** */ 220:Src/system_stm32f7xx.c **** pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22; 221:Src/system_stm32f7xx.c **** pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; 222:Src/system_stm32f7xx.c **** 223:Src/system_stm32f7xx.c **** if (pllsource != 0) 224:Src/system_stm32f7xx.c **** { 225:Src/system_stm32f7xx.c **** /* HSE used as PLL clock source */ 226:Src/system_stm32f7xx.c **** pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); 227:Src/system_stm32f7xx.c **** } 228:Src/system_stm32f7xx.c **** else 229:Src/system_stm32f7xx.c **** { 230:Src/system_stm32f7xx.c **** /* HSI used as PLL clock source */ 231:Src/system_stm32f7xx.c **** pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); 232:Src/system_stm32f7xx.c **** } 233:Src/system_stm32f7xx.c **** 234:Src/system_stm32f7xx.c **** pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2; 235:Src/system_stm32f7xx.c **** SystemCoreClock = pllvco/pllp; 236:Src/system_stm32f7xx.c **** break; 237:Src/system_stm32f7xx.c **** default: 238:Src/system_stm32f7xx.c **** SystemCoreClock = HSI_VALUE; 78 .loc 1 238 7 view .LVU10 79 .loc 1 238 23 is_stmt 0 view .LVU11 80 0012 1F4B ldr r3, .L12+4 81 .LVL2: 82 .loc 1 238 23 view .LVU12 83 0014 1F4A ldr r2, .L12+8 84 0016 1A60 str r2, [r3] 239:Src/system_stm32f7xx.c **** break; 85 .loc 1 239 7 is_stmt 1 view .LVU13 86 0018 02E0 b .L8 87 .LVL3: 88 .L11: 210:Src/system_stm32f7xx.c **** break; 89 .loc 1 210 7 view .LVU14 210:Src/system_stm32f7xx.c **** break; 90 .loc 1 210 23 is_stmt 0 view .LVU15 91 001a 1D4B ldr r3, .L12+4 92 .LVL4: 210:Src/system_stm32f7xx.c **** break; 93 .loc 1 210 23 view .LVU16 94 001c 1D4A ldr r2, .L12+8 95 001e 1A60 str r2, [r3] 211:Src/system_stm32f7xx.c **** case 0x04: /* HSE used as system clock source */ 96 .loc 1 211 7 is_stmt 1 view .LVU17 97 .LVL5: 98 .L8: 240:Src/system_stm32f7xx.c **** } 241:Src/system_stm32f7xx.c **** /* Compute HCLK frequency --------------------------------------------------*/ 242:Src/system_stm32f7xx.c **** /* Get HCLK prescaler */ 243:Src/system_stm32f7xx.c **** tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; ARM GAS /tmp/cc4hZZNo.s page 7 99 .loc 1 243 3 view .LVU18 100 .loc 1 243 28 is_stmt 0 view .LVU19 101 0020 1A4B ldr r3, .L12 102 0022 9B68 ldr r3, [r3, #8] 103 .loc 1 243 52 view .LVU20 104 0024 C3F30313 ubfx r3, r3, #4, #4 105 .loc 1 243 22 view .LVU21 106 0028 1B4A ldr r2, .L12+12 107 002a D15C ldrb r1, [r2, r3] @ zero_extendqisi2 108 .LVL6: 244:Src/system_stm32f7xx.c **** /* HCLK frequency */ 245:Src/system_stm32f7xx.c **** SystemCoreClock >>= tmp; 109 .loc 1 245 3 is_stmt 1 view .LVU22 110 .loc 1 245 19 is_stmt 0 view .LVU23 111 002c 184A ldr r2, .L12+4 112 002e 1368 ldr r3, [r2] 113 0030 CB40 lsrs r3, r3, r1 114 0032 1360 str r3, [r2] 246:Src/system_stm32f7xx.c **** } 115 .loc 1 246 1 view .LVU24 116 0034 7047 bx lr 117 .LVL7: 118 .L5: 213:Src/system_stm32f7xx.c **** break; 119 .loc 1 213 7 is_stmt 1 view .LVU25 213:Src/system_stm32f7xx.c **** break; 120 .loc 1 213 23 is_stmt 0 view .LVU26 121 0036 164B ldr r3, .L12+4 122 .LVL8: 213:Src/system_stm32f7xx.c **** break; 123 .loc 1 213 23 view .LVU27 124 0038 184A ldr r2, .L12+16 125 003a 1A60 str r2, [r3] 214:Src/system_stm32f7xx.c **** case 0x08: /* PLL used as system clock source */ 126 .loc 1 214 7 is_stmt 1 view .LVU28 127 003c F0E7 b .L8 128 .LVL9: 129 .L6: 220:Src/system_stm32f7xx.c **** pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; 130 .loc 1 220 7 view .LVU29 220:Src/system_stm32f7xx.c **** pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; 131 .loc 1 220 23 is_stmt 0 view .LVU30 132 003e 134B ldr r3, .L12 133 .LVL10: 220:Src/system_stm32f7xx.c **** pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; 134 .loc 1 220 23 view .LVU31 135 0040 5968 ldr r1, [r3, #4] 136 .LVL11: 221:Src/system_stm32f7xx.c **** 137 .loc 1 221 7 is_stmt 1 view .LVU32 221:Src/system_stm32f7xx.c **** 138 .loc 1 221 17 is_stmt 0 view .LVU33 139 0042 5A68 ldr r2, [r3, #4] 221:Src/system_stm32f7xx.c **** 140 .loc 1 221 12 view .LVU34 141 0044 02F03F02 and r2, r2, #63 142 .LVL12: ARM GAS /tmp/cc4hZZNo.s page 8 223:Src/system_stm32f7xx.c **** { 143 .loc 1 223 7 is_stmt 1 view .LVU35 223:Src/system_stm32f7xx.c **** { 144 .loc 1 223 10 is_stmt 0 view .LVU36 145 0048 11F4800F tst r1, #4194304 146 004c 13D0 beq .L9 226:Src/system_stm32f7xx.c **** } 147 .loc 1 226 9 is_stmt 1 view .LVU37 226:Src/system_stm32f7xx.c **** } 148 .loc 1 226 29 is_stmt 0 view .LVU38 149 004e 134B ldr r3, .L12+16 150 0050 B3FBF2F3 udiv r3, r3, r2 226:Src/system_stm32f7xx.c **** } 151 .loc 1 226 44 view .LVU39 152 0054 0D4A ldr r2, .L12 153 .LVL13: 226:Src/system_stm32f7xx.c **** } 154 .loc 1 226 44 view .LVU40 155 0056 5268 ldr r2, [r2, #4] 226:Src/system_stm32f7xx.c **** } 156 .loc 1 226 74 view .LVU41 157 0058 C2F38812 ubfx r2, r2, #6, #9 226:Src/system_stm32f7xx.c **** } 158 .loc 1 226 16 view .LVU42 159 005c 02FB03F3 mul r3, r2, r3 160 .LVL14: 161 .L10: 234:Src/system_stm32f7xx.c **** SystemCoreClock = pllvco/pllp; 162 .loc 1 234 7 is_stmt 1 view .LVU43 234:Src/system_stm32f7xx.c **** SystemCoreClock = pllvco/pllp; 163 .loc 1 234 20 is_stmt 0 view .LVU44 164 0060 0A4A ldr r2, .L12 165 0062 5268 ldr r2, [r2, #4] 234:Src/system_stm32f7xx.c **** SystemCoreClock = pllvco/pllp; 166 .loc 1 234 50 view .LVU45 167 0064 C2F30142 ubfx r2, r2, #16, #2 234:Src/system_stm32f7xx.c **** SystemCoreClock = pllvco/pllp; 168 .loc 1 234 56 view .LVU46 169 0068 0132 adds r2, r2, #1 234:Src/system_stm32f7xx.c **** SystemCoreClock = pllvco/pllp; 170 .loc 1 234 12 view .LVU47 171 006a 5200 lsls r2, r2, #1 172 .LVL15: 235:Src/system_stm32f7xx.c **** break; 173 .loc 1 235 7 is_stmt 1 view .LVU48 235:Src/system_stm32f7xx.c **** break; 174 .loc 1 235 31 is_stmt 0 view .LVU49 175 006c B3FBF2F3 udiv r3, r3, r2 176 .LVL16: 235:Src/system_stm32f7xx.c **** break; 177 .loc 1 235 23 view .LVU50 178 0070 074A ldr r2, .L12+4 179 .LVL17: 235:Src/system_stm32f7xx.c **** break; 180 .loc 1 235 23 view .LVU51 181 0072 1360 str r3, [r2] 236:Src/system_stm32f7xx.c **** default: ARM GAS /tmp/cc4hZZNo.s page 9 182 .loc 1 236 7 is_stmt 1 view .LVU52 183 0074 D4E7 b .L8 184 .LVL18: 185 .L9: 231:Src/system_stm32f7xx.c **** } 186 .loc 1 231 9 view .LVU53 231:Src/system_stm32f7xx.c **** } 187 .loc 1 231 29 is_stmt 0 view .LVU54 188 0076 074B ldr r3, .L12+8 189 0078 B3FBF2F3 udiv r3, r3, r2 231:Src/system_stm32f7xx.c **** } 190 .loc 1 231 44 view .LVU55 191 007c 034A ldr r2, .L12 192 .LVL19: 231:Src/system_stm32f7xx.c **** } 193 .loc 1 231 44 view .LVU56 194 007e 5268 ldr r2, [r2, #4] 231:Src/system_stm32f7xx.c **** } 195 .loc 1 231 74 view .LVU57 196 0080 C2F38812 ubfx r2, r2, #6, #9 231:Src/system_stm32f7xx.c **** } 197 .loc 1 231 16 view .LVU58 198 0084 02FB03F3 mul r3, r2, r3 199 .LVL20: 231:Src/system_stm32f7xx.c **** } 200 .loc 1 231 16 view .LVU59 201 0088 EAE7 b .L10 202 .L13: 203 008a 00BF .align 2 204 .L12: 205 008c 00380240 .word 1073887232 206 0090 00000000 .word .LANCHOR0 207 0094 0024F400 .word 16000000 208 0098 00000000 .word .LANCHOR1 209 009c 40787D01 .word 25000000 210 .cfi_endproc 211 .LFE142: 213 .global APBPrescTable 214 .global AHBPrescTable 215 .global SystemCoreClock 216 .section .data.SystemCoreClock,"aw" 217 .align 2 218 .set .LANCHOR0,. + 0 221 SystemCoreClock: 222 0000 0024F400 .word 16000000 223 .section .rodata.AHBPrescTable,"a" 224 .align 2 225 .set .LANCHOR1,. + 0 228 AHBPrescTable: 229 0000 00000000 .ascii "\000\000\000\000\000\000\000\000\001\002\003\004\006" 229 00000000 229 01020304 229 06 230 000d 070809 .ascii "\007\010\011" 231 .section .rodata.APBPrescTable,"a" 232 .align 2 235 APBPrescTable: ARM GAS /tmp/cc4hZZNo.s page 10 236 0000 00000000 .ascii "\000\000\000\000\001\002\003\004" 236 01020304 237 .text 238 .Letext0: 239 .file 2 "/usr/lib/gcc/arm-none-eabi/10.3.1/include/stdint.h" 240 .file 3 "Drivers/CMSIS/Include/core_cm7.h" 241 .file 4 "Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h" 242 .file 5 "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h" ARM GAS /tmp/cc4hZZNo.s page 11 DEFINED SYMBOLS *ABS*:0000000000000000 system_stm32f7xx.c /tmp/cc4hZZNo.s:17 .text.SystemInit:0000000000000000 $t /tmp/cc4hZZNo.s:25 .text.SystemInit:0000000000000000 SystemInit /tmp/cc4hZZNo.s:44 .text.SystemInit:0000000000000010 $d /tmp/cc4hZZNo.s:49 .text.SystemCoreClockUpdate:0000000000000000 $t /tmp/cc4hZZNo.s:56 .text.SystemCoreClockUpdate:0000000000000000 SystemCoreClockUpdate /tmp/cc4hZZNo.s:205 .text.SystemCoreClockUpdate:000000000000008c $d /tmp/cc4hZZNo.s:235 .rodata.APBPrescTable:0000000000000000 APBPrescTable /tmp/cc4hZZNo.s:228 .rodata.AHBPrescTable:0000000000000000 AHBPrescTable /tmp/cc4hZZNo.s:221 .data.SystemCoreClock:0000000000000000 SystemCoreClock /tmp/cc4hZZNo.s:217 .data.SystemCoreClock:0000000000000000 $d /tmp/cc4hZZNo.s:224 .rodata.AHBPrescTable:0000000000000000 $d /tmp/cc4hZZNo.s:232 .rodata.APBPrescTable:0000000000000000 $d NO UNDEFINED SYMBOLS