ARM GAS /tmp/ccdsDELB.s page 1 1 .cpu cortex-m7 2 .eabi_attribute 28, 1 3 .eabi_attribute 20, 1 4 .eabi_attribute 21, 1 5 .eabi_attribute 23, 3 6 .eabi_attribute 24, 1 7 .eabi_attribute 25, 1 8 .eabi_attribute 26, 1 9 .eabi_attribute 30, 1 10 .eabi_attribute 34, 1 11 .eabi_attribute 18, 4 12 .file "main.c" 13 .text 14 .Ltext0: 15 .cfi_sections .debug_frame 16 .section .text.NVIC_EncodePriority,"ax",%progbits 17 .align 1 18 .arch armv7e-m 19 .syntax unified 20 .thumb 21 .thumb_func 22 .fpu fpv5-d16 24 NVIC_EncodePriority: 25 .LVL0: 26 .LFB113: 27 .file 1 "Drivers/CMSIS/Include/core_cm7.h" 1:Drivers/CMSIS/Include/core_cm7.h **** /**************************************************************************//** 2:Drivers/CMSIS/Include/core_cm7.h **** * @file core_cm7.h 3:Drivers/CMSIS/Include/core_cm7.h **** * @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File 4:Drivers/CMSIS/Include/core_cm7.h **** * @version V5.0.8 5:Drivers/CMSIS/Include/core_cm7.h **** * @date 04. June 2018 6:Drivers/CMSIS/Include/core_cm7.h **** ******************************************************************************/ 7:Drivers/CMSIS/Include/core_cm7.h **** /* 8:Drivers/CMSIS/Include/core_cm7.h **** * Copyright (c) 2009-2018 Arm Limited. All rights reserved. 9:Drivers/CMSIS/Include/core_cm7.h **** * 10:Drivers/CMSIS/Include/core_cm7.h **** * SPDX-License-Identifier: Apache-2.0 11:Drivers/CMSIS/Include/core_cm7.h **** * 12:Drivers/CMSIS/Include/core_cm7.h **** * Licensed under the Apache License, Version 2.0 (the License); you may 13:Drivers/CMSIS/Include/core_cm7.h **** * not use this file except in compliance with the License. 14:Drivers/CMSIS/Include/core_cm7.h **** * You may obtain a copy of the License at 15:Drivers/CMSIS/Include/core_cm7.h **** * 16:Drivers/CMSIS/Include/core_cm7.h **** * www.apache.org/licenses/LICENSE-2.0 17:Drivers/CMSIS/Include/core_cm7.h **** * 18:Drivers/CMSIS/Include/core_cm7.h **** * Unless required by applicable law or agreed to in writing, software 19:Drivers/CMSIS/Include/core_cm7.h **** * distributed under the License is distributed on an AS IS BASIS, WITHOUT 20:Drivers/CMSIS/Include/core_cm7.h **** * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 21:Drivers/CMSIS/Include/core_cm7.h **** * See the License for the specific language governing permissions and 22:Drivers/CMSIS/Include/core_cm7.h **** * limitations under the License. 23:Drivers/CMSIS/Include/core_cm7.h **** */ 24:Drivers/CMSIS/Include/core_cm7.h **** 25:Drivers/CMSIS/Include/core_cm7.h **** #if defined ( __ICCARM__ ) 26:Drivers/CMSIS/Include/core_cm7.h **** #pragma system_include /* treat file as system include file for MISRA check */ 27:Drivers/CMSIS/Include/core_cm7.h **** #elif defined (__clang__) 28:Drivers/CMSIS/Include/core_cm7.h **** #pragma clang system_header /* treat file as system include file */ 29:Drivers/CMSIS/Include/core_cm7.h **** #endif 30:Drivers/CMSIS/Include/core_cm7.h **** 31:Drivers/CMSIS/Include/core_cm7.h **** #ifndef __CORE_CM7_H_GENERIC ARM GAS /tmp/ccdsDELB.s page 2 32:Drivers/CMSIS/Include/core_cm7.h **** #define __CORE_CM7_H_GENERIC 33:Drivers/CMSIS/Include/core_cm7.h **** 34:Drivers/CMSIS/Include/core_cm7.h **** #include 35:Drivers/CMSIS/Include/core_cm7.h **** 36:Drivers/CMSIS/Include/core_cm7.h **** #ifdef __cplusplus 37:Drivers/CMSIS/Include/core_cm7.h **** extern "C" { 38:Drivers/CMSIS/Include/core_cm7.h **** #endif 39:Drivers/CMSIS/Include/core_cm7.h **** 40:Drivers/CMSIS/Include/core_cm7.h **** /** 41:Drivers/CMSIS/Include/core_cm7.h **** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions 42:Drivers/CMSIS/Include/core_cm7.h **** CMSIS violates the following MISRA-C:2004 rules: 43:Drivers/CMSIS/Include/core_cm7.h **** 44:Drivers/CMSIS/Include/core_cm7.h **** \li Required Rule 8.5, object/function definition in header file.
45:Drivers/CMSIS/Include/core_cm7.h **** Function definitions in header files are used to allow 'inlining'. 46:Drivers/CMSIS/Include/core_cm7.h **** 47:Drivers/CMSIS/Include/core_cm7.h **** \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
48:Drivers/CMSIS/Include/core_cm7.h **** Unions are used for effective representation of core registers. 49:Drivers/CMSIS/Include/core_cm7.h **** 50:Drivers/CMSIS/Include/core_cm7.h **** \li Advisory Rule 19.7, Function-like macro defined.
51:Drivers/CMSIS/Include/core_cm7.h **** Function-like macros are used to allow more efficient code. 52:Drivers/CMSIS/Include/core_cm7.h **** */ 53:Drivers/CMSIS/Include/core_cm7.h **** 54:Drivers/CMSIS/Include/core_cm7.h **** 55:Drivers/CMSIS/Include/core_cm7.h **** /******************************************************************************* 56:Drivers/CMSIS/Include/core_cm7.h **** * CMSIS definitions 57:Drivers/CMSIS/Include/core_cm7.h **** ******************************************************************************/ 58:Drivers/CMSIS/Include/core_cm7.h **** /** 59:Drivers/CMSIS/Include/core_cm7.h **** \ingroup Cortex_M7 60:Drivers/CMSIS/Include/core_cm7.h **** @{ 61:Drivers/CMSIS/Include/core_cm7.h **** */ 62:Drivers/CMSIS/Include/core_cm7.h **** 63:Drivers/CMSIS/Include/core_cm7.h **** #include "cmsis_version.h" 64:Drivers/CMSIS/Include/core_cm7.h **** 65:Drivers/CMSIS/Include/core_cm7.h **** /* CMSIS CM7 definitions */ 66:Drivers/CMSIS/Include/core_cm7.h **** #define __CM7_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:1 67:Drivers/CMSIS/Include/core_cm7.h **** #define __CM7_CMSIS_VERSION_SUB ( __CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0 68:Drivers/CMSIS/Include/core_cm7.h **** #define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16U) | \ 69:Drivers/CMSIS/Include/core_cm7.h **** __CM7_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS 70:Drivers/CMSIS/Include/core_cm7.h **** 71:Drivers/CMSIS/Include/core_cm7.h **** #define __CORTEX_M (7U) /*!< Cortex-M Core */ 72:Drivers/CMSIS/Include/core_cm7.h **** 73:Drivers/CMSIS/Include/core_cm7.h **** /** __FPU_USED indicates whether an FPU is used or not. 74:Drivers/CMSIS/Include/core_cm7.h **** For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and fun 75:Drivers/CMSIS/Include/core_cm7.h **** */ 76:Drivers/CMSIS/Include/core_cm7.h **** #if defined ( __CC_ARM ) 77:Drivers/CMSIS/Include/core_cm7.h **** #if defined __TARGET_FPU_VFP 78:Drivers/CMSIS/Include/core_cm7.h **** #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) 79:Drivers/CMSIS/Include/core_cm7.h **** #define __FPU_USED 1U 80:Drivers/CMSIS/Include/core_cm7.h **** #else 81:Drivers/CMSIS/Include/core_cm7.h **** #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT) 82:Drivers/CMSIS/Include/core_cm7.h **** #define __FPU_USED 0U 83:Drivers/CMSIS/Include/core_cm7.h **** #endif 84:Drivers/CMSIS/Include/core_cm7.h **** #else 85:Drivers/CMSIS/Include/core_cm7.h **** #define __FPU_USED 0U 86:Drivers/CMSIS/Include/core_cm7.h **** #endif 87:Drivers/CMSIS/Include/core_cm7.h **** 88:Drivers/CMSIS/Include/core_cm7.h **** #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) ARM GAS /tmp/ccdsDELB.s page 3 89:Drivers/CMSIS/Include/core_cm7.h **** #if defined __ARM_PCS_VFP 90:Drivers/CMSIS/Include/core_cm7.h **** #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) 91:Drivers/CMSIS/Include/core_cm7.h **** #define __FPU_USED 1U 92:Drivers/CMSIS/Include/core_cm7.h **** #else 93:Drivers/CMSIS/Include/core_cm7.h **** #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESEN 94:Drivers/CMSIS/Include/core_cm7.h **** #define __FPU_USED 0U 95:Drivers/CMSIS/Include/core_cm7.h **** #endif 96:Drivers/CMSIS/Include/core_cm7.h **** #else 97:Drivers/CMSIS/Include/core_cm7.h **** #define __FPU_USED 0U 98:Drivers/CMSIS/Include/core_cm7.h **** #endif 99:Drivers/CMSIS/Include/core_cm7.h **** 100:Drivers/CMSIS/Include/core_cm7.h **** #elif defined ( __GNUC__ ) 101:Drivers/CMSIS/Include/core_cm7.h **** #if defined (__VFP_FP__) && !defined(__SOFTFP__) 102:Drivers/CMSIS/Include/core_cm7.h **** #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) 103:Drivers/CMSIS/Include/core_cm7.h **** #define __FPU_USED 1U 104:Drivers/CMSIS/Include/core_cm7.h **** #else 105:Drivers/CMSIS/Include/core_cm7.h **** #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT) 106:Drivers/CMSIS/Include/core_cm7.h **** #define __FPU_USED 0U 107:Drivers/CMSIS/Include/core_cm7.h **** #endif 108:Drivers/CMSIS/Include/core_cm7.h **** #else 109:Drivers/CMSIS/Include/core_cm7.h **** #define __FPU_USED 0U 110:Drivers/CMSIS/Include/core_cm7.h **** #endif 111:Drivers/CMSIS/Include/core_cm7.h **** 112:Drivers/CMSIS/Include/core_cm7.h **** #elif defined ( __ICCARM__ ) 113:Drivers/CMSIS/Include/core_cm7.h **** #if defined __ARMVFP__ 114:Drivers/CMSIS/Include/core_cm7.h **** #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) 115:Drivers/CMSIS/Include/core_cm7.h **** #define __FPU_USED 1U 116:Drivers/CMSIS/Include/core_cm7.h **** #else 117:Drivers/CMSIS/Include/core_cm7.h **** #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT) 118:Drivers/CMSIS/Include/core_cm7.h **** #define __FPU_USED 0U 119:Drivers/CMSIS/Include/core_cm7.h **** #endif 120:Drivers/CMSIS/Include/core_cm7.h **** #else 121:Drivers/CMSIS/Include/core_cm7.h **** #define __FPU_USED 0U 122:Drivers/CMSIS/Include/core_cm7.h **** #endif 123:Drivers/CMSIS/Include/core_cm7.h **** 124:Drivers/CMSIS/Include/core_cm7.h **** #elif defined ( __TI_ARM__ ) 125:Drivers/CMSIS/Include/core_cm7.h **** #if defined __TI_VFP_SUPPORT__ 126:Drivers/CMSIS/Include/core_cm7.h **** #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) 127:Drivers/CMSIS/Include/core_cm7.h **** #define __FPU_USED 1U 128:Drivers/CMSIS/Include/core_cm7.h **** #else 129:Drivers/CMSIS/Include/core_cm7.h **** #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT) 130:Drivers/CMSIS/Include/core_cm7.h **** #define __FPU_USED 0U 131:Drivers/CMSIS/Include/core_cm7.h **** #endif 132:Drivers/CMSIS/Include/core_cm7.h **** #else 133:Drivers/CMSIS/Include/core_cm7.h **** #define __FPU_USED 0U 134:Drivers/CMSIS/Include/core_cm7.h **** #endif 135:Drivers/CMSIS/Include/core_cm7.h **** 136:Drivers/CMSIS/Include/core_cm7.h **** #elif defined ( __TASKING__ ) 137:Drivers/CMSIS/Include/core_cm7.h **** #if defined __FPU_VFP__ 138:Drivers/CMSIS/Include/core_cm7.h **** #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) 139:Drivers/CMSIS/Include/core_cm7.h **** #define __FPU_USED 1U 140:Drivers/CMSIS/Include/core_cm7.h **** #else 141:Drivers/CMSIS/Include/core_cm7.h **** #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT) 142:Drivers/CMSIS/Include/core_cm7.h **** #define __FPU_USED 0U 143:Drivers/CMSIS/Include/core_cm7.h **** #endif 144:Drivers/CMSIS/Include/core_cm7.h **** #else 145:Drivers/CMSIS/Include/core_cm7.h **** #define __FPU_USED 0U ARM GAS /tmp/ccdsDELB.s page 4 146:Drivers/CMSIS/Include/core_cm7.h **** #endif 147:Drivers/CMSIS/Include/core_cm7.h **** 148:Drivers/CMSIS/Include/core_cm7.h **** #elif defined ( __CSMC__ ) 149:Drivers/CMSIS/Include/core_cm7.h **** #if ( __CSMC__ & 0x400U) 150:Drivers/CMSIS/Include/core_cm7.h **** #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) 151:Drivers/CMSIS/Include/core_cm7.h **** #define __FPU_USED 1U 152:Drivers/CMSIS/Include/core_cm7.h **** #else 153:Drivers/CMSIS/Include/core_cm7.h **** #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT) 154:Drivers/CMSIS/Include/core_cm7.h **** #define __FPU_USED 0U 155:Drivers/CMSIS/Include/core_cm7.h **** #endif 156:Drivers/CMSIS/Include/core_cm7.h **** #else 157:Drivers/CMSIS/Include/core_cm7.h **** #define __FPU_USED 0U 158:Drivers/CMSIS/Include/core_cm7.h **** #endif 159:Drivers/CMSIS/Include/core_cm7.h **** 160:Drivers/CMSIS/Include/core_cm7.h **** #endif 161:Drivers/CMSIS/Include/core_cm7.h **** 162:Drivers/CMSIS/Include/core_cm7.h **** #include "cmsis_compiler.h" /* CMSIS compiler specific defines */ 163:Drivers/CMSIS/Include/core_cm7.h **** 164:Drivers/CMSIS/Include/core_cm7.h **** 165:Drivers/CMSIS/Include/core_cm7.h **** #ifdef __cplusplus 166:Drivers/CMSIS/Include/core_cm7.h **** } 167:Drivers/CMSIS/Include/core_cm7.h **** #endif 168:Drivers/CMSIS/Include/core_cm7.h **** 169:Drivers/CMSIS/Include/core_cm7.h **** #endif /* __CORE_CM7_H_GENERIC */ 170:Drivers/CMSIS/Include/core_cm7.h **** 171:Drivers/CMSIS/Include/core_cm7.h **** #ifndef __CMSIS_GENERIC 172:Drivers/CMSIS/Include/core_cm7.h **** 173:Drivers/CMSIS/Include/core_cm7.h **** #ifndef __CORE_CM7_H_DEPENDANT 174:Drivers/CMSIS/Include/core_cm7.h **** #define __CORE_CM7_H_DEPENDANT 175:Drivers/CMSIS/Include/core_cm7.h **** 176:Drivers/CMSIS/Include/core_cm7.h **** #ifdef __cplusplus 177:Drivers/CMSIS/Include/core_cm7.h **** extern "C" { 178:Drivers/CMSIS/Include/core_cm7.h **** #endif 179:Drivers/CMSIS/Include/core_cm7.h **** 180:Drivers/CMSIS/Include/core_cm7.h **** /* check device defines and use defaults */ 181:Drivers/CMSIS/Include/core_cm7.h **** #if defined __CHECK_DEVICE_DEFINES 182:Drivers/CMSIS/Include/core_cm7.h **** #ifndef __CM7_REV 183:Drivers/CMSIS/Include/core_cm7.h **** #define __CM7_REV 0x0000U 184:Drivers/CMSIS/Include/core_cm7.h **** #warning "__CM7_REV not defined in device header file; using default!" 185:Drivers/CMSIS/Include/core_cm7.h **** #endif 186:Drivers/CMSIS/Include/core_cm7.h **** 187:Drivers/CMSIS/Include/core_cm7.h **** #ifndef __FPU_PRESENT 188:Drivers/CMSIS/Include/core_cm7.h **** #define __FPU_PRESENT 0U 189:Drivers/CMSIS/Include/core_cm7.h **** #warning "__FPU_PRESENT not defined in device header file; using default!" 190:Drivers/CMSIS/Include/core_cm7.h **** #endif 191:Drivers/CMSIS/Include/core_cm7.h **** 192:Drivers/CMSIS/Include/core_cm7.h **** #ifndef __MPU_PRESENT 193:Drivers/CMSIS/Include/core_cm7.h **** #define __MPU_PRESENT 0U 194:Drivers/CMSIS/Include/core_cm7.h **** #warning "__MPU_PRESENT not defined in device header file; using default!" 195:Drivers/CMSIS/Include/core_cm7.h **** #endif 196:Drivers/CMSIS/Include/core_cm7.h **** 197:Drivers/CMSIS/Include/core_cm7.h **** #ifndef __ICACHE_PRESENT 198:Drivers/CMSIS/Include/core_cm7.h **** #define __ICACHE_PRESENT 0U 199:Drivers/CMSIS/Include/core_cm7.h **** #warning "__ICACHE_PRESENT not defined in device header file; using default!" 200:Drivers/CMSIS/Include/core_cm7.h **** #endif 201:Drivers/CMSIS/Include/core_cm7.h **** 202:Drivers/CMSIS/Include/core_cm7.h **** #ifndef __DCACHE_PRESENT ARM GAS /tmp/ccdsDELB.s page 5 203:Drivers/CMSIS/Include/core_cm7.h **** #define __DCACHE_PRESENT 0U 204:Drivers/CMSIS/Include/core_cm7.h **** #warning "__DCACHE_PRESENT not defined in device header file; using default!" 205:Drivers/CMSIS/Include/core_cm7.h **** #endif 206:Drivers/CMSIS/Include/core_cm7.h **** 207:Drivers/CMSIS/Include/core_cm7.h **** #ifndef __DTCM_PRESENT 208:Drivers/CMSIS/Include/core_cm7.h **** #define __DTCM_PRESENT 0U 209:Drivers/CMSIS/Include/core_cm7.h **** #warning "__DTCM_PRESENT not defined in device header file; using default!" 210:Drivers/CMSIS/Include/core_cm7.h **** #endif 211:Drivers/CMSIS/Include/core_cm7.h **** 212:Drivers/CMSIS/Include/core_cm7.h **** #ifndef __NVIC_PRIO_BITS 213:Drivers/CMSIS/Include/core_cm7.h **** #define __NVIC_PRIO_BITS 3U 214:Drivers/CMSIS/Include/core_cm7.h **** #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" 215:Drivers/CMSIS/Include/core_cm7.h **** #endif 216:Drivers/CMSIS/Include/core_cm7.h **** 217:Drivers/CMSIS/Include/core_cm7.h **** #ifndef __Vendor_SysTickConfig 218:Drivers/CMSIS/Include/core_cm7.h **** #define __Vendor_SysTickConfig 0U 219:Drivers/CMSIS/Include/core_cm7.h **** #warning "__Vendor_SysTickConfig not defined in device header file; using default!" 220:Drivers/CMSIS/Include/core_cm7.h **** #endif 221:Drivers/CMSIS/Include/core_cm7.h **** #endif 222:Drivers/CMSIS/Include/core_cm7.h **** 223:Drivers/CMSIS/Include/core_cm7.h **** /* IO definitions (access restrictions to peripheral registers) */ 224:Drivers/CMSIS/Include/core_cm7.h **** /** 225:Drivers/CMSIS/Include/core_cm7.h **** \defgroup CMSIS_glob_defs CMSIS Global Defines 226:Drivers/CMSIS/Include/core_cm7.h **** 227:Drivers/CMSIS/Include/core_cm7.h **** IO Type Qualifiers are used 228:Drivers/CMSIS/Include/core_cm7.h **** \li to specify the access to peripheral variables. 229:Drivers/CMSIS/Include/core_cm7.h **** \li for automatic generation of peripheral register debug information. 230:Drivers/CMSIS/Include/core_cm7.h **** */ 231:Drivers/CMSIS/Include/core_cm7.h **** #ifdef __cplusplus 232:Drivers/CMSIS/Include/core_cm7.h **** #define __I volatile /*!< Defines 'read only' permissions */ 233:Drivers/CMSIS/Include/core_cm7.h **** #else 234:Drivers/CMSIS/Include/core_cm7.h **** #define __I volatile const /*!< Defines 'read only' permissions */ 235:Drivers/CMSIS/Include/core_cm7.h **** #endif 236:Drivers/CMSIS/Include/core_cm7.h **** #define __O volatile /*!< Defines 'write only' permissions */ 237:Drivers/CMSIS/Include/core_cm7.h **** #define __IO volatile /*!< Defines 'read / write' permissions */ 238:Drivers/CMSIS/Include/core_cm7.h **** 239:Drivers/CMSIS/Include/core_cm7.h **** /* following defines should be used for structure members */ 240:Drivers/CMSIS/Include/core_cm7.h **** #define __IM volatile const /*! Defines 'read only' structure member permissions */ 241:Drivers/CMSIS/Include/core_cm7.h **** #define __OM volatile /*! Defines 'write only' structure member permissions */ 242:Drivers/CMSIS/Include/core_cm7.h **** #define __IOM volatile /*! Defines 'read / write' structure member permissions */ 243:Drivers/CMSIS/Include/core_cm7.h **** 244:Drivers/CMSIS/Include/core_cm7.h **** /*@} end of group Cortex_M7 */ 245:Drivers/CMSIS/Include/core_cm7.h **** 246:Drivers/CMSIS/Include/core_cm7.h **** 247:Drivers/CMSIS/Include/core_cm7.h **** 248:Drivers/CMSIS/Include/core_cm7.h **** /******************************************************************************* 249:Drivers/CMSIS/Include/core_cm7.h **** * Register Abstraction 250:Drivers/CMSIS/Include/core_cm7.h **** Core Register contain: 251:Drivers/CMSIS/Include/core_cm7.h **** - Core Register 252:Drivers/CMSIS/Include/core_cm7.h **** - Core NVIC Register 253:Drivers/CMSIS/Include/core_cm7.h **** - Core SCB Register 254:Drivers/CMSIS/Include/core_cm7.h **** - Core SysTick Register 255:Drivers/CMSIS/Include/core_cm7.h **** - Core Debug Register 256:Drivers/CMSIS/Include/core_cm7.h **** - Core MPU Register 257:Drivers/CMSIS/Include/core_cm7.h **** - Core FPU Register 258:Drivers/CMSIS/Include/core_cm7.h **** ******************************************************************************/ 259:Drivers/CMSIS/Include/core_cm7.h **** /** ARM GAS /tmp/ccdsDELB.s page 6 260:Drivers/CMSIS/Include/core_cm7.h **** \defgroup CMSIS_core_register Defines and Type Definitions 261:Drivers/CMSIS/Include/core_cm7.h **** \brief Type definitions and defines for Cortex-M processor based devices. 262:Drivers/CMSIS/Include/core_cm7.h **** */ 263:Drivers/CMSIS/Include/core_cm7.h **** 264:Drivers/CMSIS/Include/core_cm7.h **** /** 265:Drivers/CMSIS/Include/core_cm7.h **** \ingroup CMSIS_core_register 266:Drivers/CMSIS/Include/core_cm7.h **** \defgroup CMSIS_CORE Status and Control Registers 267:Drivers/CMSIS/Include/core_cm7.h **** \brief Core Register type definitions. 268:Drivers/CMSIS/Include/core_cm7.h **** @{ 269:Drivers/CMSIS/Include/core_cm7.h **** */ 270:Drivers/CMSIS/Include/core_cm7.h **** 271:Drivers/CMSIS/Include/core_cm7.h **** /** 272:Drivers/CMSIS/Include/core_cm7.h **** \brief Union type to access the Application Program Status Register (APSR). 273:Drivers/CMSIS/Include/core_cm7.h **** */ 274:Drivers/CMSIS/Include/core_cm7.h **** typedef union 275:Drivers/CMSIS/Include/core_cm7.h **** { 276:Drivers/CMSIS/Include/core_cm7.h **** struct 277:Drivers/CMSIS/Include/core_cm7.h **** { 278:Drivers/CMSIS/Include/core_cm7.h **** uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ 279:Drivers/CMSIS/Include/core_cm7.h **** uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ 280:Drivers/CMSIS/Include/core_cm7.h **** uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ 281:Drivers/CMSIS/Include/core_cm7.h **** uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ 282:Drivers/CMSIS/Include/core_cm7.h **** uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ 283:Drivers/CMSIS/Include/core_cm7.h **** uint32_t C:1; /*!< bit: 29 Carry condition code flag */ 284:Drivers/CMSIS/Include/core_cm7.h **** uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ 285:Drivers/CMSIS/Include/core_cm7.h **** uint32_t N:1; /*!< bit: 31 Negative condition code flag */ 286:Drivers/CMSIS/Include/core_cm7.h **** } b; /*!< Structure used for bit access */ 287:Drivers/CMSIS/Include/core_cm7.h **** uint32_t w; /*!< Type used for word access */ 288:Drivers/CMSIS/Include/core_cm7.h **** } APSR_Type; 289:Drivers/CMSIS/Include/core_cm7.h **** 290:Drivers/CMSIS/Include/core_cm7.h **** /* APSR Register Definitions */ 291:Drivers/CMSIS/Include/core_cm7.h **** #define APSR_N_Pos 31U /*!< APSR 292:Drivers/CMSIS/Include/core_cm7.h **** #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR 293:Drivers/CMSIS/Include/core_cm7.h **** 294:Drivers/CMSIS/Include/core_cm7.h **** #define APSR_Z_Pos 30U /*!< APSR 295:Drivers/CMSIS/Include/core_cm7.h **** #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR 296:Drivers/CMSIS/Include/core_cm7.h **** 297:Drivers/CMSIS/Include/core_cm7.h **** #define APSR_C_Pos 29U /*!< APSR 298:Drivers/CMSIS/Include/core_cm7.h **** #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR 299:Drivers/CMSIS/Include/core_cm7.h **** 300:Drivers/CMSIS/Include/core_cm7.h **** #define APSR_V_Pos 28U /*!< APSR 301:Drivers/CMSIS/Include/core_cm7.h **** #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR 302:Drivers/CMSIS/Include/core_cm7.h **** 303:Drivers/CMSIS/Include/core_cm7.h **** #define APSR_Q_Pos 27U /*!< APSR 304:Drivers/CMSIS/Include/core_cm7.h **** #define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR 305:Drivers/CMSIS/Include/core_cm7.h **** 306:Drivers/CMSIS/Include/core_cm7.h **** #define APSR_GE_Pos 16U /*!< APSR 307:Drivers/CMSIS/Include/core_cm7.h **** #define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR 308:Drivers/CMSIS/Include/core_cm7.h **** 309:Drivers/CMSIS/Include/core_cm7.h **** 310:Drivers/CMSIS/Include/core_cm7.h **** /** 311:Drivers/CMSIS/Include/core_cm7.h **** \brief Union type to access the Interrupt Program Status Register (IPSR). 312:Drivers/CMSIS/Include/core_cm7.h **** */ 313:Drivers/CMSIS/Include/core_cm7.h **** typedef union 314:Drivers/CMSIS/Include/core_cm7.h **** { 315:Drivers/CMSIS/Include/core_cm7.h **** struct 316:Drivers/CMSIS/Include/core_cm7.h **** { ARM GAS /tmp/ccdsDELB.s page 7 317:Drivers/CMSIS/Include/core_cm7.h **** uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ 318:Drivers/CMSIS/Include/core_cm7.h **** uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ 319:Drivers/CMSIS/Include/core_cm7.h **** } b; /*!< Structure used for bit access */ 320:Drivers/CMSIS/Include/core_cm7.h **** uint32_t w; /*!< Type used for word access */ 321:Drivers/CMSIS/Include/core_cm7.h **** } IPSR_Type; 322:Drivers/CMSIS/Include/core_cm7.h **** 323:Drivers/CMSIS/Include/core_cm7.h **** /* IPSR Register Definitions */ 324:Drivers/CMSIS/Include/core_cm7.h **** #define IPSR_ISR_Pos 0U /*!< IPSR 325:Drivers/CMSIS/Include/core_cm7.h **** #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR 326:Drivers/CMSIS/Include/core_cm7.h **** 327:Drivers/CMSIS/Include/core_cm7.h **** 328:Drivers/CMSIS/Include/core_cm7.h **** /** 329:Drivers/CMSIS/Include/core_cm7.h **** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). 330:Drivers/CMSIS/Include/core_cm7.h **** */ 331:Drivers/CMSIS/Include/core_cm7.h **** typedef union 332:Drivers/CMSIS/Include/core_cm7.h **** { 333:Drivers/CMSIS/Include/core_cm7.h **** struct 334:Drivers/CMSIS/Include/core_cm7.h **** { 335:Drivers/CMSIS/Include/core_cm7.h **** uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ 336:Drivers/CMSIS/Include/core_cm7.h **** uint32_t _reserved0:1; /*!< bit: 9 Reserved */ 337:Drivers/CMSIS/Include/core_cm7.h **** uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ 338:Drivers/CMSIS/Include/core_cm7.h **** uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ 339:Drivers/CMSIS/Include/core_cm7.h **** uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ 340:Drivers/CMSIS/Include/core_cm7.h **** uint32_t T:1; /*!< bit: 24 Thumb bit */ 341:Drivers/CMSIS/Include/core_cm7.h **** uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ 342:Drivers/CMSIS/Include/core_cm7.h **** uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ 343:Drivers/CMSIS/Include/core_cm7.h **** uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ 344:Drivers/CMSIS/Include/core_cm7.h **** uint32_t C:1; /*!< bit: 29 Carry condition code flag */ 345:Drivers/CMSIS/Include/core_cm7.h **** uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ 346:Drivers/CMSIS/Include/core_cm7.h **** uint32_t N:1; /*!< bit: 31 Negative condition code flag */ 347:Drivers/CMSIS/Include/core_cm7.h **** } b; /*!< Structure used for bit access */ 348:Drivers/CMSIS/Include/core_cm7.h **** uint32_t w; /*!< Type used for word access */ 349:Drivers/CMSIS/Include/core_cm7.h **** } xPSR_Type; 350:Drivers/CMSIS/Include/core_cm7.h **** 351:Drivers/CMSIS/Include/core_cm7.h **** /* xPSR Register Definitions */ 352:Drivers/CMSIS/Include/core_cm7.h **** #define xPSR_N_Pos 31U /*!< xPSR 353:Drivers/CMSIS/Include/core_cm7.h **** #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR 354:Drivers/CMSIS/Include/core_cm7.h **** 355:Drivers/CMSIS/Include/core_cm7.h **** #define xPSR_Z_Pos 30U /*!< xPSR 356:Drivers/CMSIS/Include/core_cm7.h **** #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR 357:Drivers/CMSIS/Include/core_cm7.h **** 358:Drivers/CMSIS/Include/core_cm7.h **** #define xPSR_C_Pos 29U /*!< xPSR 359:Drivers/CMSIS/Include/core_cm7.h **** #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR 360:Drivers/CMSIS/Include/core_cm7.h **** 361:Drivers/CMSIS/Include/core_cm7.h **** #define xPSR_V_Pos 28U /*!< xPSR 362:Drivers/CMSIS/Include/core_cm7.h **** #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR 363:Drivers/CMSIS/Include/core_cm7.h **** 364:Drivers/CMSIS/Include/core_cm7.h **** #define xPSR_Q_Pos 27U /*!< xPSR 365:Drivers/CMSIS/Include/core_cm7.h **** #define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR 366:Drivers/CMSIS/Include/core_cm7.h **** 367:Drivers/CMSIS/Include/core_cm7.h **** #define xPSR_ICI_IT_2_Pos 25U /*!< xPSR 368:Drivers/CMSIS/Include/core_cm7.h **** #define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR 369:Drivers/CMSIS/Include/core_cm7.h **** 370:Drivers/CMSIS/Include/core_cm7.h **** #define xPSR_T_Pos 24U /*!< xPSR 371:Drivers/CMSIS/Include/core_cm7.h **** #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR 372:Drivers/CMSIS/Include/core_cm7.h **** 373:Drivers/CMSIS/Include/core_cm7.h **** #define xPSR_GE_Pos 16U /*!< xPSR ARM GAS /tmp/ccdsDELB.s page 8 374:Drivers/CMSIS/Include/core_cm7.h **** #define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR 375:Drivers/CMSIS/Include/core_cm7.h **** 376:Drivers/CMSIS/Include/core_cm7.h **** #define xPSR_ICI_IT_1_Pos 10U /*!< xPSR 377:Drivers/CMSIS/Include/core_cm7.h **** #define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR 378:Drivers/CMSIS/Include/core_cm7.h **** 379:Drivers/CMSIS/Include/core_cm7.h **** #define xPSR_ISR_Pos 0U /*!< xPSR 380:Drivers/CMSIS/Include/core_cm7.h **** #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR 381:Drivers/CMSIS/Include/core_cm7.h **** 382:Drivers/CMSIS/Include/core_cm7.h **** 383:Drivers/CMSIS/Include/core_cm7.h **** /** 384:Drivers/CMSIS/Include/core_cm7.h **** \brief Union type to access the Control Registers (CONTROL). 385:Drivers/CMSIS/Include/core_cm7.h **** */ 386:Drivers/CMSIS/Include/core_cm7.h **** typedef union 387:Drivers/CMSIS/Include/core_cm7.h **** { 388:Drivers/CMSIS/Include/core_cm7.h **** struct 389:Drivers/CMSIS/Include/core_cm7.h **** { 390:Drivers/CMSIS/Include/core_cm7.h **** uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ 391:Drivers/CMSIS/Include/core_cm7.h **** uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ 392:Drivers/CMSIS/Include/core_cm7.h **** uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ 393:Drivers/CMSIS/Include/core_cm7.h **** uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ 394:Drivers/CMSIS/Include/core_cm7.h **** } b; /*!< Structure used for bit access */ 395:Drivers/CMSIS/Include/core_cm7.h **** uint32_t w; /*!< Type used for word access */ 396:Drivers/CMSIS/Include/core_cm7.h **** } CONTROL_Type; 397:Drivers/CMSIS/Include/core_cm7.h **** 398:Drivers/CMSIS/Include/core_cm7.h **** /* CONTROL Register Definitions */ 399:Drivers/CMSIS/Include/core_cm7.h **** #define CONTROL_FPCA_Pos 2U /*!< CONT 400:Drivers/CMSIS/Include/core_cm7.h **** #define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONT 401:Drivers/CMSIS/Include/core_cm7.h **** 402:Drivers/CMSIS/Include/core_cm7.h **** #define CONTROL_SPSEL_Pos 1U /*!< CONT 403:Drivers/CMSIS/Include/core_cm7.h **** #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONT 404:Drivers/CMSIS/Include/core_cm7.h **** 405:Drivers/CMSIS/Include/core_cm7.h **** #define CONTROL_nPRIV_Pos 0U /*!< CONT 406:Drivers/CMSIS/Include/core_cm7.h **** #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONT 407:Drivers/CMSIS/Include/core_cm7.h **** 408:Drivers/CMSIS/Include/core_cm7.h **** /*@} end of group CMSIS_CORE */ 409:Drivers/CMSIS/Include/core_cm7.h **** 410:Drivers/CMSIS/Include/core_cm7.h **** 411:Drivers/CMSIS/Include/core_cm7.h **** /** 412:Drivers/CMSIS/Include/core_cm7.h **** \ingroup CMSIS_core_register 413:Drivers/CMSIS/Include/core_cm7.h **** \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) 414:Drivers/CMSIS/Include/core_cm7.h **** \brief Type definitions for the NVIC Registers 415:Drivers/CMSIS/Include/core_cm7.h **** @{ 416:Drivers/CMSIS/Include/core_cm7.h **** */ 417:Drivers/CMSIS/Include/core_cm7.h **** 418:Drivers/CMSIS/Include/core_cm7.h **** /** 419:Drivers/CMSIS/Include/core_cm7.h **** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). 420:Drivers/CMSIS/Include/core_cm7.h **** */ 421:Drivers/CMSIS/Include/core_cm7.h **** typedef struct 422:Drivers/CMSIS/Include/core_cm7.h **** { 423:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ 424:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED0[24U]; 425:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register 426:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RSERVED1[24U]; 427:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register * 428:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED2[24U]; 429:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register 430:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED3[24U]; ARM GAS /tmp/ccdsDELB.s page 9 431:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ 432:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED4[56U]; 433:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bi 434:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED5[644U]; 435:Drivers/CMSIS/Include/core_cm7.h **** __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Regis 436:Drivers/CMSIS/Include/core_cm7.h **** } NVIC_Type; 437:Drivers/CMSIS/Include/core_cm7.h **** 438:Drivers/CMSIS/Include/core_cm7.h **** /* Software Triggered Interrupt Register Definitions */ 439:Drivers/CMSIS/Include/core_cm7.h **** #define NVIC_STIR_INTID_Pos 0U /*!< STIR: I 440:Drivers/CMSIS/Include/core_cm7.h **** #define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: I 441:Drivers/CMSIS/Include/core_cm7.h **** 442:Drivers/CMSIS/Include/core_cm7.h **** /*@} end of group CMSIS_NVIC */ 443:Drivers/CMSIS/Include/core_cm7.h **** 444:Drivers/CMSIS/Include/core_cm7.h **** 445:Drivers/CMSIS/Include/core_cm7.h **** /** 446:Drivers/CMSIS/Include/core_cm7.h **** \ingroup CMSIS_core_register 447:Drivers/CMSIS/Include/core_cm7.h **** \defgroup CMSIS_SCB System Control Block (SCB) 448:Drivers/CMSIS/Include/core_cm7.h **** \brief Type definitions for the System Control Block Registers 449:Drivers/CMSIS/Include/core_cm7.h **** @{ 450:Drivers/CMSIS/Include/core_cm7.h **** */ 451:Drivers/CMSIS/Include/core_cm7.h **** 452:Drivers/CMSIS/Include/core_cm7.h **** /** 453:Drivers/CMSIS/Include/core_cm7.h **** \brief Structure type to access the System Control Block (SCB). 454:Drivers/CMSIS/Include/core_cm7.h **** */ 455:Drivers/CMSIS/Include/core_cm7.h **** typedef struct 456:Drivers/CMSIS/Include/core_cm7.h **** { 457:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ 458:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Regi 459:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ 460:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset 461:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ 462:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register * 463:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registe 464:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State 465:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Regist 466:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ 467:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ 468:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register 469:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ 470:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register 471:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ 472:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ 473:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ 474:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t ID_MFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ 475:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t ID_ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Regis 476:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED0[1U]; 477:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ 478:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ 479:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ 480:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ 481:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Regis 482:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED3[93U]; 483:Drivers/CMSIS/Include/core_cm7.h **** __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Reg 484:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED4[15U]; 485:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 486:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 487:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 ARM GAS /tmp/ccdsDELB.s page 10 488:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED5[1U]; 489:Drivers/CMSIS/Include/core_cm7.h **** __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ 490:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED6[1U]; 491:Drivers/CMSIS/Include/core_cm7.h **** __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU 492:Drivers/CMSIS/Include/core_cm7.h **** __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC 493:Drivers/CMSIS/Include/core_cm7.h **** __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ 494:Drivers/CMSIS/Include/core_cm7.h **** __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ 495:Drivers/CMSIS/Include/core_cm7.h **** __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ 496:Drivers/CMSIS/Include/core_cm7.h **** __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ 497:Drivers/CMSIS/Include/core_cm7.h **** __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by 498:Drivers/CMSIS/Include/core_cm7.h **** __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by 499:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED7[6U]; 500:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memo 501:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Cont 502:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ 503:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ 504:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ 505:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED8[1U]; 506:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Regis 507:Drivers/CMSIS/Include/core_cm7.h **** } SCB_Type; 508:Drivers/CMSIS/Include/core_cm7.h **** 509:Drivers/CMSIS/Include/core_cm7.h **** /* SCB CPUID Register Definitions */ 510:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB 511:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB 512:Drivers/CMSIS/Include/core_cm7.h **** 513:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB 514:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB 515:Drivers/CMSIS/Include/core_cm7.h **** 516:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB 517:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB 518:Drivers/CMSIS/Include/core_cm7.h **** 519:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB 520:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB 521:Drivers/CMSIS/Include/core_cm7.h **** 522:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CPUID_REVISION_Pos 0U /*!< SCB 523:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB 524:Drivers/CMSIS/Include/core_cm7.h **** 525:Drivers/CMSIS/Include/core_cm7.h **** /* SCB Interrupt Control State Register Definitions */ 526:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB 527:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB 528:Drivers/CMSIS/Include/core_cm7.h **** 529:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB 530:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB 531:Drivers/CMSIS/Include/core_cm7.h **** 532:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB 533:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB 534:Drivers/CMSIS/Include/core_cm7.h **** 535:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB 536:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB 537:Drivers/CMSIS/Include/core_cm7.h **** 538:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB 539:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB 540:Drivers/CMSIS/Include/core_cm7.h **** 541:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB 542:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB 543:Drivers/CMSIS/Include/core_cm7.h **** 544:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ARM GAS /tmp/ccdsDELB.s page 11 545:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB 546:Drivers/CMSIS/Include/core_cm7.h **** 547:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB 548:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB 549:Drivers/CMSIS/Include/core_cm7.h **** 550:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB 551:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB 552:Drivers/CMSIS/Include/core_cm7.h **** 553:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB 554:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB 555:Drivers/CMSIS/Include/core_cm7.h **** 556:Drivers/CMSIS/Include/core_cm7.h **** /* SCB Vector Table Offset Register Definitions */ 557:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB 558:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB 559:Drivers/CMSIS/Include/core_cm7.h **** 560:Drivers/CMSIS/Include/core_cm7.h **** /* SCB Application Interrupt and Reset Control Register Definitions */ 561:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB 562:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB 563:Drivers/CMSIS/Include/core_cm7.h **** 564:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB 565:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB 566:Drivers/CMSIS/Include/core_cm7.h **** 567:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB 568:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB 569:Drivers/CMSIS/Include/core_cm7.h **** 570:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB 571:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB 572:Drivers/CMSIS/Include/core_cm7.h **** 573:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB 574:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB 575:Drivers/CMSIS/Include/core_cm7.h **** 576:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB 577:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB 578:Drivers/CMSIS/Include/core_cm7.h **** 579:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB 580:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB 581:Drivers/CMSIS/Include/core_cm7.h **** 582:Drivers/CMSIS/Include/core_cm7.h **** /* SCB System Control Register Definitions */ 583:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB 584:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB 585:Drivers/CMSIS/Include/core_cm7.h **** 586:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB 587:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB 588:Drivers/CMSIS/Include/core_cm7.h **** 589:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB 590:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB 591:Drivers/CMSIS/Include/core_cm7.h **** 592:Drivers/CMSIS/Include/core_cm7.h **** /* SCB Configuration Control Register Definitions */ 593:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCR_BP_Pos 18U /*!< SCB 594:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB 595:Drivers/CMSIS/Include/core_cm7.h **** 596:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCR_IC_Pos 17U /*!< SCB 597:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB 598:Drivers/CMSIS/Include/core_cm7.h **** 599:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCR_DC_Pos 16U /*!< SCB 600:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB 601:Drivers/CMSIS/Include/core_cm7.h **** ARM GAS /tmp/ccdsDELB.s page 12 602:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCR_STKALIGN_Pos 9U /*!< SCB 603:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB 604:Drivers/CMSIS/Include/core_cm7.h **** 605:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB 606:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB 607:Drivers/CMSIS/Include/core_cm7.h **** 608:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB 609:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB 610:Drivers/CMSIS/Include/core_cm7.h **** 611:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB 612:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB 613:Drivers/CMSIS/Include/core_cm7.h **** 614:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB 615:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB 616:Drivers/CMSIS/Include/core_cm7.h **** 617:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB 618:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB 619:Drivers/CMSIS/Include/core_cm7.h **** 620:Drivers/CMSIS/Include/core_cm7.h **** /* SCB System Handler Control and State Register Definitions */ 621:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB 622:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB 623:Drivers/CMSIS/Include/core_cm7.h **** 624:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB 625:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB 626:Drivers/CMSIS/Include/core_cm7.h **** 627:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB 628:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB 629:Drivers/CMSIS/Include/core_cm7.h **** 630:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB 631:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB 632:Drivers/CMSIS/Include/core_cm7.h **** 633:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB 634:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB 635:Drivers/CMSIS/Include/core_cm7.h **** 636:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB 637:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB 638:Drivers/CMSIS/Include/core_cm7.h **** 639:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB 640:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB 641:Drivers/CMSIS/Include/core_cm7.h **** 642:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB 643:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB 644:Drivers/CMSIS/Include/core_cm7.h **** 645:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB 646:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB 647:Drivers/CMSIS/Include/core_cm7.h **** 648:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB 649:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB 650:Drivers/CMSIS/Include/core_cm7.h **** 651:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB 652:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB 653:Drivers/CMSIS/Include/core_cm7.h **** 654:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB 655:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB 656:Drivers/CMSIS/Include/core_cm7.h **** 657:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB 658:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB ARM GAS /tmp/ccdsDELB.s page 13 659:Drivers/CMSIS/Include/core_cm7.h **** 660:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB 661:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB 662:Drivers/CMSIS/Include/core_cm7.h **** 663:Drivers/CMSIS/Include/core_cm7.h **** /* SCB Configurable Fault Status Register Definitions */ 664:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB 665:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB 666:Drivers/CMSIS/Include/core_cm7.h **** 667:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB 668:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB 669:Drivers/CMSIS/Include/core_cm7.h **** 670:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB 671:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB 672:Drivers/CMSIS/Include/core_cm7.h **** 673:Drivers/CMSIS/Include/core_cm7.h **** /* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ 674:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB 675:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB 676:Drivers/CMSIS/Include/core_cm7.h **** 677:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB 678:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB 679:Drivers/CMSIS/Include/core_cm7.h **** 680:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB 681:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB 682:Drivers/CMSIS/Include/core_cm7.h **** 683:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB 684:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB 685:Drivers/CMSIS/Include/core_cm7.h **** 686:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB 687:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB 688:Drivers/CMSIS/Include/core_cm7.h **** 689:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB 690:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB 691:Drivers/CMSIS/Include/core_cm7.h **** 692:Drivers/CMSIS/Include/core_cm7.h **** /* BusFault Status Register (part of SCB Configurable Fault Status Register) */ 693:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB 694:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB 695:Drivers/CMSIS/Include/core_cm7.h **** 696:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB 697:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB 698:Drivers/CMSIS/Include/core_cm7.h **** 699:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB 700:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB 701:Drivers/CMSIS/Include/core_cm7.h **** 702:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB 703:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB 704:Drivers/CMSIS/Include/core_cm7.h **** 705:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB 706:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB 707:Drivers/CMSIS/Include/core_cm7.h **** 708:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB 709:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB 710:Drivers/CMSIS/Include/core_cm7.h **** 711:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB 712:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB 713:Drivers/CMSIS/Include/core_cm7.h **** 714:Drivers/CMSIS/Include/core_cm7.h **** /* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ 715:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB ARM GAS /tmp/ccdsDELB.s page 14 716:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB 717:Drivers/CMSIS/Include/core_cm7.h **** 718:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB 719:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB 720:Drivers/CMSIS/Include/core_cm7.h **** 721:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB 722:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB 723:Drivers/CMSIS/Include/core_cm7.h **** 724:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB 725:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB 726:Drivers/CMSIS/Include/core_cm7.h **** 727:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB 728:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB 729:Drivers/CMSIS/Include/core_cm7.h **** 730:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB 731:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB 732:Drivers/CMSIS/Include/core_cm7.h **** 733:Drivers/CMSIS/Include/core_cm7.h **** /* SCB Hard Fault Status Register Definitions */ 734:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB 735:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB 736:Drivers/CMSIS/Include/core_cm7.h **** 737:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_HFSR_FORCED_Pos 30U /*!< SCB 738:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB 739:Drivers/CMSIS/Include/core_cm7.h **** 740:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB 741:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB 742:Drivers/CMSIS/Include/core_cm7.h **** 743:Drivers/CMSIS/Include/core_cm7.h **** /* SCB Debug Fault Status Register Definitions */ 744:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB 745:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB 746:Drivers/CMSIS/Include/core_cm7.h **** 747:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DFSR_VCATCH_Pos 3U /*!< SCB 748:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB 749:Drivers/CMSIS/Include/core_cm7.h **** 750:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB 751:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB 752:Drivers/CMSIS/Include/core_cm7.h **** 753:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DFSR_BKPT_Pos 1U /*!< SCB 754:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB 755:Drivers/CMSIS/Include/core_cm7.h **** 756:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DFSR_HALTED_Pos 0U /*!< SCB 757:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB 758:Drivers/CMSIS/Include/core_cm7.h **** 759:Drivers/CMSIS/Include/core_cm7.h **** /* SCB Cache Level ID Register Definitions */ 760:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CLIDR_LOUU_Pos 27U /*!< SCB 761:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB 762:Drivers/CMSIS/Include/core_cm7.h **** 763:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CLIDR_LOC_Pos 24U /*!< SCB 764:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB 765:Drivers/CMSIS/Include/core_cm7.h **** 766:Drivers/CMSIS/Include/core_cm7.h **** /* SCB Cache Type Register Definitions */ 767:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CTR_FORMAT_Pos 29U /*!< SCB 768:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB 769:Drivers/CMSIS/Include/core_cm7.h **** 770:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CTR_CWG_Pos 24U /*!< SCB 771:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB 772:Drivers/CMSIS/Include/core_cm7.h **** ARM GAS /tmp/ccdsDELB.s page 15 773:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CTR_ERG_Pos 20U /*!< SCB 774:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB 775:Drivers/CMSIS/Include/core_cm7.h **** 776:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CTR_DMINLINE_Pos 16U /*!< SCB 777:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB 778:Drivers/CMSIS/Include/core_cm7.h **** 779:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CTR_IMINLINE_Pos 0U /*!< SCB 780:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB 781:Drivers/CMSIS/Include/core_cm7.h **** 782:Drivers/CMSIS/Include/core_cm7.h **** /* SCB Cache Size ID Register Definitions */ 783:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCSIDR_WT_Pos 31U /*!< SCB 784:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB 785:Drivers/CMSIS/Include/core_cm7.h **** 786:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCSIDR_WB_Pos 30U /*!< SCB 787:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB 788:Drivers/CMSIS/Include/core_cm7.h **** 789:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCSIDR_RA_Pos 29U /*!< SCB 790:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB 791:Drivers/CMSIS/Include/core_cm7.h **** 792:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCSIDR_WA_Pos 28U /*!< SCB 793:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB 794:Drivers/CMSIS/Include/core_cm7.h **** 795:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB 796:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB 797:Drivers/CMSIS/Include/core_cm7.h **** 798:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB 799:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB 800:Drivers/CMSIS/Include/core_cm7.h **** 801:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB 802:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB 803:Drivers/CMSIS/Include/core_cm7.h **** 804:Drivers/CMSIS/Include/core_cm7.h **** /* SCB Cache Size Selection Register Definitions */ 805:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB 806:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB 807:Drivers/CMSIS/Include/core_cm7.h **** 808:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CSSELR_IND_Pos 0U /*!< SCB 809:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB 810:Drivers/CMSIS/Include/core_cm7.h **** 811:Drivers/CMSIS/Include/core_cm7.h **** /* SCB Software Triggered Interrupt Register Definitions */ 812:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_STIR_INTID_Pos 0U /*!< SCB 813:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB 814:Drivers/CMSIS/Include/core_cm7.h **** 815:Drivers/CMSIS/Include/core_cm7.h **** /* SCB D-Cache Invalidate by Set-way Register Definitions */ 816:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DCISW_WAY_Pos 30U /*!< SCB 817:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB 818:Drivers/CMSIS/Include/core_cm7.h **** 819:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DCISW_SET_Pos 5U /*!< SCB 820:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB 821:Drivers/CMSIS/Include/core_cm7.h **** 822:Drivers/CMSIS/Include/core_cm7.h **** /* SCB D-Cache Clean by Set-way Register Definitions */ 823:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DCCSW_WAY_Pos 30U /*!< SCB 824:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB 825:Drivers/CMSIS/Include/core_cm7.h **** 826:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DCCSW_SET_Pos 5U /*!< SCB 827:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB 828:Drivers/CMSIS/Include/core_cm7.h **** 829:Drivers/CMSIS/Include/core_cm7.h **** /* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ ARM GAS /tmp/ccdsDELB.s page 16 830:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DCCISW_WAY_Pos 30U /*!< SCB 831:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB 832:Drivers/CMSIS/Include/core_cm7.h **** 833:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DCCISW_SET_Pos 5U /*!< SCB 834:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB 835:Drivers/CMSIS/Include/core_cm7.h **** 836:Drivers/CMSIS/Include/core_cm7.h **** /* Instruction Tightly-Coupled Memory Control Register Definitions */ 837:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ITCMCR_SZ_Pos 3U /*!< SCB 838:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB 839:Drivers/CMSIS/Include/core_cm7.h **** 840:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB 841:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB 842:Drivers/CMSIS/Include/core_cm7.h **** 843:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ITCMCR_RMW_Pos 1U /*!< SCB 844:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB 845:Drivers/CMSIS/Include/core_cm7.h **** 846:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ITCMCR_EN_Pos 0U /*!< SCB 847:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB 848:Drivers/CMSIS/Include/core_cm7.h **** 849:Drivers/CMSIS/Include/core_cm7.h **** /* Data Tightly-Coupled Memory Control Register Definitions */ 850:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DTCMCR_SZ_Pos 3U /*!< SCB 851:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB 852:Drivers/CMSIS/Include/core_cm7.h **** 853:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB 854:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB 855:Drivers/CMSIS/Include/core_cm7.h **** 856:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DTCMCR_RMW_Pos 1U /*!< SCB 857:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB 858:Drivers/CMSIS/Include/core_cm7.h **** 859:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DTCMCR_EN_Pos 0U /*!< SCB 860:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB 861:Drivers/CMSIS/Include/core_cm7.h **** 862:Drivers/CMSIS/Include/core_cm7.h **** /* AHBP Control Register Definitions */ 863:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AHBPCR_SZ_Pos 1U /*!< SCB 864:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB 865:Drivers/CMSIS/Include/core_cm7.h **** 866:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AHBPCR_EN_Pos 0U /*!< SCB 867:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB 868:Drivers/CMSIS/Include/core_cm7.h **** 869:Drivers/CMSIS/Include/core_cm7.h **** /* L1 Cache Control Register Definitions */ 870:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CACR_FORCEWT_Pos 2U /*!< SCB 871:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB 872:Drivers/CMSIS/Include/core_cm7.h **** 873:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CACR_ECCEN_Pos 1U /*!< SCB 874:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB 875:Drivers/CMSIS/Include/core_cm7.h **** 876:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CACR_SIWT_Pos 0U /*!< SCB 877:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB 878:Drivers/CMSIS/Include/core_cm7.h **** 879:Drivers/CMSIS/Include/core_cm7.h **** /* AHBS Control Register Definitions */ 880:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB 881:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB 882:Drivers/CMSIS/Include/core_cm7.h **** 883:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB 884:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB 885:Drivers/CMSIS/Include/core_cm7.h **** 886:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AHBSCR_CTL_Pos 0U /*!< SCB ARM GAS /tmp/ccdsDELB.s page 17 887:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB 888:Drivers/CMSIS/Include/core_cm7.h **** 889:Drivers/CMSIS/Include/core_cm7.h **** /* Auxiliary Bus Fault Status Register Definitions */ 890:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB 891:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB 892:Drivers/CMSIS/Include/core_cm7.h **** 893:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ABFSR_EPPB_Pos 4U /*!< SCB 894:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB 895:Drivers/CMSIS/Include/core_cm7.h **** 896:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ABFSR_AXIM_Pos 3U /*!< SCB 897:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB 898:Drivers/CMSIS/Include/core_cm7.h **** 899:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ABFSR_AHBP_Pos 2U /*!< SCB 900:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB 901:Drivers/CMSIS/Include/core_cm7.h **** 902:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ABFSR_DTCM_Pos 1U /*!< SCB 903:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB 904:Drivers/CMSIS/Include/core_cm7.h **** 905:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ABFSR_ITCM_Pos 0U /*!< SCB 906:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB 907:Drivers/CMSIS/Include/core_cm7.h **** 908:Drivers/CMSIS/Include/core_cm7.h **** /*@} end of group CMSIS_SCB */ 909:Drivers/CMSIS/Include/core_cm7.h **** 910:Drivers/CMSIS/Include/core_cm7.h **** 911:Drivers/CMSIS/Include/core_cm7.h **** /** 912:Drivers/CMSIS/Include/core_cm7.h **** \ingroup CMSIS_core_register 913:Drivers/CMSIS/Include/core_cm7.h **** \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) 914:Drivers/CMSIS/Include/core_cm7.h **** \brief Type definitions for the System Control and ID Register not in the SCB 915:Drivers/CMSIS/Include/core_cm7.h **** @{ 916:Drivers/CMSIS/Include/core_cm7.h **** */ 917:Drivers/CMSIS/Include/core_cm7.h **** 918:Drivers/CMSIS/Include/core_cm7.h **** /** 919:Drivers/CMSIS/Include/core_cm7.h **** \brief Structure type to access the System Control and ID Register not in the SCB. 920:Drivers/CMSIS/Include/core_cm7.h **** */ 921:Drivers/CMSIS/Include/core_cm7.h **** typedef struct 922:Drivers/CMSIS/Include/core_cm7.h **** { 923:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED0[1U]; 924:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Regist 925:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ 926:Drivers/CMSIS/Include/core_cm7.h **** } SCnSCB_Type; 927:Drivers/CMSIS/Include/core_cm7.h **** 928:Drivers/CMSIS/Include/core_cm7.h **** /* Interrupt Controller Type Register Definitions */ 929:Drivers/CMSIS/Include/core_cm7.h **** #define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: I 930:Drivers/CMSIS/Include/core_cm7.h **** #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: I 931:Drivers/CMSIS/Include/core_cm7.h **** 932:Drivers/CMSIS/Include/core_cm7.h **** /* Auxiliary Control Register Definitions */ 933:Drivers/CMSIS/Include/core_cm7.h **** #define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12U /*!< ACTLR: 934:Drivers/CMSIS/Include/core_cm7.h **** #define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: 935:Drivers/CMSIS/Include/core_cm7.h **** 936:Drivers/CMSIS/Include/core_cm7.h **** #define SCnSCB_ACTLR_DISRAMODE_Pos 11U /*!< ACTLR: 937:Drivers/CMSIS/Include/core_cm7.h **** #define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) /*!< ACTLR: 938:Drivers/CMSIS/Include/core_cm7.h **** 939:Drivers/CMSIS/Include/core_cm7.h **** #define SCnSCB_ACTLR_FPEXCODIS_Pos 10U /*!< ACTLR: 940:Drivers/CMSIS/Include/core_cm7.h **** #define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: 941:Drivers/CMSIS/Include/core_cm7.h **** 942:Drivers/CMSIS/Include/core_cm7.h **** #define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: 943:Drivers/CMSIS/Include/core_cm7.h **** #define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: ARM GAS /tmp/ccdsDELB.s page 18 944:Drivers/CMSIS/Include/core_cm7.h **** 945:Drivers/CMSIS/Include/core_cm7.h **** #define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: 946:Drivers/CMSIS/Include/core_cm7.h **** #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: 947:Drivers/CMSIS/Include/core_cm7.h **** 948:Drivers/CMSIS/Include/core_cm7.h **** /*@} end of group CMSIS_SCnotSCB */ 949:Drivers/CMSIS/Include/core_cm7.h **** 950:Drivers/CMSIS/Include/core_cm7.h **** 951:Drivers/CMSIS/Include/core_cm7.h **** /** 952:Drivers/CMSIS/Include/core_cm7.h **** \ingroup CMSIS_core_register 953:Drivers/CMSIS/Include/core_cm7.h **** \defgroup CMSIS_SysTick System Tick Timer (SysTick) 954:Drivers/CMSIS/Include/core_cm7.h **** \brief Type definitions for the System Timer Registers. 955:Drivers/CMSIS/Include/core_cm7.h **** @{ 956:Drivers/CMSIS/Include/core_cm7.h **** */ 957:Drivers/CMSIS/Include/core_cm7.h **** 958:Drivers/CMSIS/Include/core_cm7.h **** /** 959:Drivers/CMSIS/Include/core_cm7.h **** \brief Structure type to access the System Timer (SysTick). 960:Drivers/CMSIS/Include/core_cm7.h **** */ 961:Drivers/CMSIS/Include/core_cm7.h **** typedef struct 962:Drivers/CMSIS/Include/core_cm7.h **** { 963:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Regis 964:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ 965:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register * 966:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ 967:Drivers/CMSIS/Include/core_cm7.h **** } SysTick_Type; 968:Drivers/CMSIS/Include/core_cm7.h **** 969:Drivers/CMSIS/Include/core_cm7.h **** /* SysTick Control / Status Register Definitions */ 970:Drivers/CMSIS/Include/core_cm7.h **** #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysT 971:Drivers/CMSIS/Include/core_cm7.h **** #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysT 972:Drivers/CMSIS/Include/core_cm7.h **** 973:Drivers/CMSIS/Include/core_cm7.h **** #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysT 974:Drivers/CMSIS/Include/core_cm7.h **** #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysT 975:Drivers/CMSIS/Include/core_cm7.h **** 976:Drivers/CMSIS/Include/core_cm7.h **** #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysT 977:Drivers/CMSIS/Include/core_cm7.h **** #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysT 978:Drivers/CMSIS/Include/core_cm7.h **** 979:Drivers/CMSIS/Include/core_cm7.h **** #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysT 980:Drivers/CMSIS/Include/core_cm7.h **** #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysT 981:Drivers/CMSIS/Include/core_cm7.h **** 982:Drivers/CMSIS/Include/core_cm7.h **** /* SysTick Reload Register Definitions */ 983:Drivers/CMSIS/Include/core_cm7.h **** #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysT 984:Drivers/CMSIS/Include/core_cm7.h **** #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysT 985:Drivers/CMSIS/Include/core_cm7.h **** 986:Drivers/CMSIS/Include/core_cm7.h **** /* SysTick Current Register Definitions */ 987:Drivers/CMSIS/Include/core_cm7.h **** #define SysTick_VAL_CURRENT_Pos 0U /*!< SysT 988:Drivers/CMSIS/Include/core_cm7.h **** #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysT 989:Drivers/CMSIS/Include/core_cm7.h **** 990:Drivers/CMSIS/Include/core_cm7.h **** /* SysTick Calibration Register Definitions */ 991:Drivers/CMSIS/Include/core_cm7.h **** #define SysTick_CALIB_NOREF_Pos 31U /*!< SysT 992:Drivers/CMSIS/Include/core_cm7.h **** #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysT 993:Drivers/CMSIS/Include/core_cm7.h **** 994:Drivers/CMSIS/Include/core_cm7.h **** #define SysTick_CALIB_SKEW_Pos 30U /*!< SysT 995:Drivers/CMSIS/Include/core_cm7.h **** #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysT 996:Drivers/CMSIS/Include/core_cm7.h **** 997:Drivers/CMSIS/Include/core_cm7.h **** #define SysTick_CALIB_TENMS_Pos 0U /*!< SysT 998:Drivers/CMSIS/Include/core_cm7.h **** #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysT 999:Drivers/CMSIS/Include/core_cm7.h **** 1000:Drivers/CMSIS/Include/core_cm7.h **** /*@} end of group CMSIS_SysTick */ ARM GAS /tmp/ccdsDELB.s page 19 1001:Drivers/CMSIS/Include/core_cm7.h **** 1002:Drivers/CMSIS/Include/core_cm7.h **** 1003:Drivers/CMSIS/Include/core_cm7.h **** /** 1004:Drivers/CMSIS/Include/core_cm7.h **** \ingroup CMSIS_core_register 1005:Drivers/CMSIS/Include/core_cm7.h **** \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) 1006:Drivers/CMSIS/Include/core_cm7.h **** \brief Type definitions for the Instrumentation Trace Macrocell (ITM) 1007:Drivers/CMSIS/Include/core_cm7.h **** @{ 1008:Drivers/CMSIS/Include/core_cm7.h **** */ 1009:Drivers/CMSIS/Include/core_cm7.h **** 1010:Drivers/CMSIS/Include/core_cm7.h **** /** 1011:Drivers/CMSIS/Include/core_cm7.h **** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). 1012:Drivers/CMSIS/Include/core_cm7.h **** */ 1013:Drivers/CMSIS/Include/core_cm7.h **** typedef struct 1014:Drivers/CMSIS/Include/core_cm7.h **** { 1015:Drivers/CMSIS/Include/core_cm7.h **** __OM union 1016:Drivers/CMSIS/Include/core_cm7.h **** { 1017:Drivers/CMSIS/Include/core_cm7.h **** __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ 1018:Drivers/CMSIS/Include/core_cm7.h **** __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ 1019:Drivers/CMSIS/Include/core_cm7.h **** __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ 1020:Drivers/CMSIS/Include/core_cm7.h **** } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ 1021:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED0[864U]; 1022:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ 1023:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED1[15U]; 1024:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ 1025:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED2[15U]; 1026:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ 1027:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED3[29U]; 1028:Drivers/CMSIS/Include/core_cm7.h **** __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register * 1029:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ 1030:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Reg 1031:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED4[43U]; 1032:Drivers/CMSIS/Include/core_cm7.h **** __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ 1033:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ 1034:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED5[6U]; 1035:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Re 1036:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Re 1037:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Re 1038:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Re 1039:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Re 1040:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Re 1041:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Re 1042:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Re 1043:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Re 1044:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Re 1045:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Re 1046:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Re 1047:Drivers/CMSIS/Include/core_cm7.h **** } ITM_Type; 1048:Drivers/CMSIS/Include/core_cm7.h **** 1049:Drivers/CMSIS/Include/core_cm7.h **** /* ITM Trace Privilege Register Definitions */ 1050:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM 1051:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM 1052:Drivers/CMSIS/Include/core_cm7.h **** 1053:Drivers/CMSIS/Include/core_cm7.h **** /* ITM Trace Control Register Definitions */ 1054:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TCR_BUSY_Pos 23U /*!< ITM 1055:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM 1056:Drivers/CMSIS/Include/core_cm7.h **** 1057:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TCR_TraceBusID_Pos 16U /*!< ITM ARM GAS /tmp/ccdsDELB.s page 20 1058:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM 1059:Drivers/CMSIS/Include/core_cm7.h **** 1060:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM 1061:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM 1062:Drivers/CMSIS/Include/core_cm7.h **** 1063:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TCR_TSPrescale_Pos 8U /*!< ITM 1064:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM 1065:Drivers/CMSIS/Include/core_cm7.h **** 1066:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TCR_SWOENA_Pos 4U /*!< ITM 1067:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM 1068:Drivers/CMSIS/Include/core_cm7.h **** 1069:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TCR_DWTENA_Pos 3U /*!< ITM 1070:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM 1071:Drivers/CMSIS/Include/core_cm7.h **** 1072:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TCR_SYNCENA_Pos 2U /*!< ITM 1073:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM 1074:Drivers/CMSIS/Include/core_cm7.h **** 1075:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TCR_TSENA_Pos 1U /*!< ITM 1076:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM 1077:Drivers/CMSIS/Include/core_cm7.h **** 1078:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TCR_ITMENA_Pos 0U /*!< ITM 1079:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM 1080:Drivers/CMSIS/Include/core_cm7.h **** 1081:Drivers/CMSIS/Include/core_cm7.h **** /* ITM Integration Write Register Definitions */ 1082:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM 1083:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM 1084:Drivers/CMSIS/Include/core_cm7.h **** 1085:Drivers/CMSIS/Include/core_cm7.h **** /* ITM Integration Read Register Definitions */ 1086:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_IRR_ATREADYM_Pos 0U /*!< ITM 1087:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM 1088:Drivers/CMSIS/Include/core_cm7.h **** 1089:Drivers/CMSIS/Include/core_cm7.h **** /* ITM Integration Mode Control Register Definitions */ 1090:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM 1091:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM 1092:Drivers/CMSIS/Include/core_cm7.h **** 1093:Drivers/CMSIS/Include/core_cm7.h **** /* ITM Lock Status Register Definitions */ 1094:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_LSR_ByteAcc_Pos 2U /*!< ITM 1095:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM 1096:Drivers/CMSIS/Include/core_cm7.h **** 1097:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_LSR_Access_Pos 1U /*!< ITM 1098:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM 1099:Drivers/CMSIS/Include/core_cm7.h **** 1100:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_LSR_Present_Pos 0U /*!< ITM 1101:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM 1102:Drivers/CMSIS/Include/core_cm7.h **** 1103:Drivers/CMSIS/Include/core_cm7.h **** /*@}*/ /* end of group CMSIS_ITM */ 1104:Drivers/CMSIS/Include/core_cm7.h **** 1105:Drivers/CMSIS/Include/core_cm7.h **** 1106:Drivers/CMSIS/Include/core_cm7.h **** /** 1107:Drivers/CMSIS/Include/core_cm7.h **** \ingroup CMSIS_core_register 1108:Drivers/CMSIS/Include/core_cm7.h **** \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) 1109:Drivers/CMSIS/Include/core_cm7.h **** \brief Type definitions for the Data Watchpoint and Trace (DWT) 1110:Drivers/CMSIS/Include/core_cm7.h **** @{ 1111:Drivers/CMSIS/Include/core_cm7.h **** */ 1112:Drivers/CMSIS/Include/core_cm7.h **** 1113:Drivers/CMSIS/Include/core_cm7.h **** /** 1114:Drivers/CMSIS/Include/core_cm7.h **** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). ARM GAS /tmp/ccdsDELB.s page 21 1115:Drivers/CMSIS/Include/core_cm7.h **** */ 1116:Drivers/CMSIS/Include/core_cm7.h **** typedef struct 1117:Drivers/CMSIS/Include/core_cm7.h **** { 1118:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ 1119:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ 1120:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ 1121:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Registe 1122:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ 1123:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ 1124:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Registe 1125:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register 1126:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ 1127:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ 1128:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ 1129:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED0[1U]; 1130:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ 1131:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ 1132:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ 1133:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED1[1U]; 1134:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ 1135:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ 1136:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ 1137:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED2[1U]; 1138:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ 1139:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ 1140:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ 1141:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED3[981U]; 1142:Drivers/CMSIS/Include/core_cm7.h **** __OM uint32_t LAR; /*!< Offset: 0xFB0 ( W) Lock Access Register */ 1143:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ 1144:Drivers/CMSIS/Include/core_cm7.h **** } DWT_Type; 1145:Drivers/CMSIS/Include/core_cm7.h **** 1146:Drivers/CMSIS/Include/core_cm7.h **** /* DWT Control Register Definitions */ 1147:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTR 1148:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTR 1149:Drivers/CMSIS/Include/core_cm7.h **** 1150:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTR 1151:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTR 1152:Drivers/CMSIS/Include/core_cm7.h **** 1153:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTR 1154:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTR 1155:Drivers/CMSIS/Include/core_cm7.h **** 1156:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTR 1157:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTR 1158:Drivers/CMSIS/Include/core_cm7.h **** 1159:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTR 1160:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTR 1161:Drivers/CMSIS/Include/core_cm7.h **** 1162:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTR 1163:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTR 1164:Drivers/CMSIS/Include/core_cm7.h **** 1165:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTR 1166:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTR 1167:Drivers/CMSIS/Include/core_cm7.h **** 1168:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTR 1169:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTR 1170:Drivers/CMSIS/Include/core_cm7.h **** 1171:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTR ARM GAS /tmp/ccdsDELB.s page 22 1172:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTR 1173:Drivers/CMSIS/Include/core_cm7.h **** 1174:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTR 1175:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTR 1176:Drivers/CMSIS/Include/core_cm7.h **** 1177:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTR 1178:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTR 1179:Drivers/CMSIS/Include/core_cm7.h **** 1180:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTR 1181:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTR 1182:Drivers/CMSIS/Include/core_cm7.h **** 1183:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTR 1184:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTR 1185:Drivers/CMSIS/Include/core_cm7.h **** 1186:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTR 1187:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTR 1188:Drivers/CMSIS/Include/core_cm7.h **** 1189:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTR 1190:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTR 1191:Drivers/CMSIS/Include/core_cm7.h **** 1192:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTR 1193:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTR 1194:Drivers/CMSIS/Include/core_cm7.h **** 1195:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTR 1196:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTR 1197:Drivers/CMSIS/Include/core_cm7.h **** 1198:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTR 1199:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTR 1200:Drivers/CMSIS/Include/core_cm7.h **** 1201:Drivers/CMSIS/Include/core_cm7.h **** /* DWT CPI Count Register Definitions */ 1202:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPI 1203:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPI 1204:Drivers/CMSIS/Include/core_cm7.h **** 1205:Drivers/CMSIS/Include/core_cm7.h **** /* DWT Exception Overhead Count Register Definitions */ 1206:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXC 1207:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXC 1208:Drivers/CMSIS/Include/core_cm7.h **** 1209:Drivers/CMSIS/Include/core_cm7.h **** /* DWT Sleep Count Register Definitions */ 1210:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLE 1211:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLE 1212:Drivers/CMSIS/Include/core_cm7.h **** 1213:Drivers/CMSIS/Include/core_cm7.h **** /* DWT LSU Count Register Definitions */ 1214:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSU 1215:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSU 1216:Drivers/CMSIS/Include/core_cm7.h **** 1217:Drivers/CMSIS/Include/core_cm7.h **** /* DWT Folded-instruction Count Register Definitions */ 1218:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOL 1219:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOL 1220:Drivers/CMSIS/Include/core_cm7.h **** 1221:Drivers/CMSIS/Include/core_cm7.h **** /* DWT Comparator Mask Register Definitions */ 1222:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_MASK_MASK_Pos 0U /*!< DWT MAS 1223:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MAS 1224:Drivers/CMSIS/Include/core_cm7.h **** 1225:Drivers/CMSIS/Include/core_cm7.h **** /* DWT Comparator Function Register Definitions */ 1226:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUN 1227:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUN 1228:Drivers/CMSIS/Include/core_cm7.h **** ARM GAS /tmp/ccdsDELB.s page 23 1229:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUN 1230:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUN 1231:Drivers/CMSIS/Include/core_cm7.h **** 1232:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUN 1233:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUN 1234:Drivers/CMSIS/Include/core_cm7.h **** 1235:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUN 1236:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUN 1237:Drivers/CMSIS/Include/core_cm7.h **** 1238:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUN 1239:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUN 1240:Drivers/CMSIS/Include/core_cm7.h **** 1241:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUN 1242:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUN 1243:Drivers/CMSIS/Include/core_cm7.h **** 1244:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUN 1245:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUN 1246:Drivers/CMSIS/Include/core_cm7.h **** 1247:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUN 1248:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUN 1249:Drivers/CMSIS/Include/core_cm7.h **** 1250:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUN 1251:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUN 1252:Drivers/CMSIS/Include/core_cm7.h **** 1253:Drivers/CMSIS/Include/core_cm7.h **** /*@}*/ /* end of group CMSIS_DWT */ 1254:Drivers/CMSIS/Include/core_cm7.h **** 1255:Drivers/CMSIS/Include/core_cm7.h **** 1256:Drivers/CMSIS/Include/core_cm7.h **** /** 1257:Drivers/CMSIS/Include/core_cm7.h **** \ingroup CMSIS_core_register 1258:Drivers/CMSIS/Include/core_cm7.h **** \defgroup CMSIS_TPI Trace Port Interface (TPI) 1259:Drivers/CMSIS/Include/core_cm7.h **** \brief Type definitions for the Trace Port Interface (TPI) 1260:Drivers/CMSIS/Include/core_cm7.h **** @{ 1261:Drivers/CMSIS/Include/core_cm7.h **** */ 1262:Drivers/CMSIS/Include/core_cm7.h **** 1263:Drivers/CMSIS/Include/core_cm7.h **** /** 1264:Drivers/CMSIS/Include/core_cm7.h **** \brief Structure type to access the Trace Port Interface Register (TPI). 1265:Drivers/CMSIS/Include/core_cm7.h **** */ 1266:Drivers/CMSIS/Include/core_cm7.h **** typedef struct 1267:Drivers/CMSIS/Include/core_cm7.h **** { 1268:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Reg 1269:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Regis 1270:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED0[2U]; 1271:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Reg 1272:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED1[55U]; 1273:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register * 1274:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED2[131U]; 1275:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Regis 1276:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Regi 1277:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counte 1278:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED3[759U]; 1279:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ 1280:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ 1281:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ 1282:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED4[1U]; 1283:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ 1284:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ 1285:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ ARM GAS /tmp/ccdsDELB.s page 24 1286:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED5[39U]; 1287:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ 1288:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ 1289:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED7[8U]; 1290:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ 1291:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ 1292:Drivers/CMSIS/Include/core_cm7.h **** } TPI_Type; 1293:Drivers/CMSIS/Include/core_cm7.h **** 1294:Drivers/CMSIS/Include/core_cm7.h **** /* TPI Asynchronous Clock Prescaler Register Definitions */ 1295:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACP 1296:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACP 1297:Drivers/CMSIS/Include/core_cm7.h **** 1298:Drivers/CMSIS/Include/core_cm7.h **** /* TPI Selected Pin Protocol Register Definitions */ 1299:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPP 1300:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPP 1301:Drivers/CMSIS/Include/core_cm7.h **** 1302:Drivers/CMSIS/Include/core_cm7.h **** /* TPI Formatter and Flush Status Register Definitions */ 1303:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFS 1304:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFS 1305:Drivers/CMSIS/Include/core_cm7.h **** 1306:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFS 1307:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFS 1308:Drivers/CMSIS/Include/core_cm7.h **** 1309:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFS 1310:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFS 1311:Drivers/CMSIS/Include/core_cm7.h **** 1312:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFS 1313:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFS 1314:Drivers/CMSIS/Include/core_cm7.h **** 1315:Drivers/CMSIS/Include/core_cm7.h **** /* TPI Formatter and Flush Control Register Definitions */ 1316:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFC 1317:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFC 1318:Drivers/CMSIS/Include/core_cm7.h **** 1319:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFC 1320:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFC 1321:Drivers/CMSIS/Include/core_cm7.h **** 1322:Drivers/CMSIS/Include/core_cm7.h **** /* TPI TRIGGER Register Definitions */ 1323:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRI 1324:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRI 1325:Drivers/CMSIS/Include/core_cm7.h **** 1326:Drivers/CMSIS/Include/core_cm7.h **** /* TPI Integration ETM Data Register Definitions (FIFO0) */ 1327:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIF 1328:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIF 1329:Drivers/CMSIS/Include/core_cm7.h **** 1330:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIF 1331:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIF 1332:Drivers/CMSIS/Include/core_cm7.h **** 1333:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIF 1334:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIF 1335:Drivers/CMSIS/Include/core_cm7.h **** 1336:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIF 1337:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIF 1338:Drivers/CMSIS/Include/core_cm7.h **** 1339:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIF 1340:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIF 1341:Drivers/CMSIS/Include/core_cm7.h **** 1342:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIF ARM GAS /tmp/ccdsDELB.s page 25 1343:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIF 1344:Drivers/CMSIS/Include/core_cm7.h **** 1345:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIF 1346:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIF 1347:Drivers/CMSIS/Include/core_cm7.h **** 1348:Drivers/CMSIS/Include/core_cm7.h **** /* TPI ITATBCTR2 Register Definitions */ 1349:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITA 1350:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITA 1351:Drivers/CMSIS/Include/core_cm7.h **** 1352:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITA 1353:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITA 1354:Drivers/CMSIS/Include/core_cm7.h **** 1355:Drivers/CMSIS/Include/core_cm7.h **** /* TPI Integration ITM Data Register Definitions (FIFO1) */ 1356:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIF 1357:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIF 1358:Drivers/CMSIS/Include/core_cm7.h **** 1359:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIF 1360:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIF 1361:Drivers/CMSIS/Include/core_cm7.h **** 1362:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIF 1363:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIF 1364:Drivers/CMSIS/Include/core_cm7.h **** 1365:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIF 1366:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIF 1367:Drivers/CMSIS/Include/core_cm7.h **** 1368:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIF 1369:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIF 1370:Drivers/CMSIS/Include/core_cm7.h **** 1371:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIF 1372:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIF 1373:Drivers/CMSIS/Include/core_cm7.h **** 1374:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIF 1375:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIF 1376:Drivers/CMSIS/Include/core_cm7.h **** 1377:Drivers/CMSIS/Include/core_cm7.h **** /* TPI ITATBCTR0 Register Definitions */ 1378:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITA 1379:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITA 1380:Drivers/CMSIS/Include/core_cm7.h **** 1381:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITA 1382:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITA 1383:Drivers/CMSIS/Include/core_cm7.h **** 1384:Drivers/CMSIS/Include/core_cm7.h **** /* TPI Integration Mode Control Register Definitions */ 1385:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITC 1386:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITC 1387:Drivers/CMSIS/Include/core_cm7.h **** 1388:Drivers/CMSIS/Include/core_cm7.h **** /* TPI DEVID Register Definitions */ 1389:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEV 1390:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEV 1391:Drivers/CMSIS/Include/core_cm7.h **** 1392:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEV 1393:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEV 1394:Drivers/CMSIS/Include/core_cm7.h **** 1395:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEV 1396:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEV 1397:Drivers/CMSIS/Include/core_cm7.h **** 1398:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEV 1399:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEV ARM GAS /tmp/ccdsDELB.s page 26 1400:Drivers/CMSIS/Include/core_cm7.h **** 1401:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEV 1402:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEV 1403:Drivers/CMSIS/Include/core_cm7.h **** 1404:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEV 1405:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEV 1406:Drivers/CMSIS/Include/core_cm7.h **** 1407:Drivers/CMSIS/Include/core_cm7.h **** /* TPI DEVTYPE Register Definitions */ 1408:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEV 1409:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEV 1410:Drivers/CMSIS/Include/core_cm7.h **** 1411:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEV 1412:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEV 1413:Drivers/CMSIS/Include/core_cm7.h **** 1414:Drivers/CMSIS/Include/core_cm7.h **** /*@}*/ /* end of group CMSIS_TPI */ 1415:Drivers/CMSIS/Include/core_cm7.h **** 1416:Drivers/CMSIS/Include/core_cm7.h **** 1417:Drivers/CMSIS/Include/core_cm7.h **** #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) 1418:Drivers/CMSIS/Include/core_cm7.h **** /** 1419:Drivers/CMSIS/Include/core_cm7.h **** \ingroup CMSIS_core_register 1420:Drivers/CMSIS/Include/core_cm7.h **** \defgroup CMSIS_MPU Memory Protection Unit (MPU) 1421:Drivers/CMSIS/Include/core_cm7.h **** \brief Type definitions for the Memory Protection Unit (MPU) 1422:Drivers/CMSIS/Include/core_cm7.h **** @{ 1423:Drivers/CMSIS/Include/core_cm7.h **** */ 1424:Drivers/CMSIS/Include/core_cm7.h **** 1425:Drivers/CMSIS/Include/core_cm7.h **** /** 1426:Drivers/CMSIS/Include/core_cm7.h **** \brief Structure type to access the Memory Protection Unit (MPU). 1427:Drivers/CMSIS/Include/core_cm7.h **** */ 1428:Drivers/CMSIS/Include/core_cm7.h **** typedef struct 1429:Drivers/CMSIS/Include/core_cm7.h **** { 1430:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ 1431:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ 1432:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ 1433:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register 1434:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Re 1435:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address 1436:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and 1437:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address 1438:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and 1439:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address 1440:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and 1441:Drivers/CMSIS/Include/core_cm7.h **** } MPU_Type; 1442:Drivers/CMSIS/Include/core_cm7.h **** 1443:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_TYPE_RALIASES 4U 1444:Drivers/CMSIS/Include/core_cm7.h **** 1445:Drivers/CMSIS/Include/core_cm7.h **** /* MPU Type Register Definitions */ 1446:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_TYPE_IREGION_Pos 16U /*!< MPU 1447:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU 1448:Drivers/CMSIS/Include/core_cm7.h **** 1449:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_TYPE_DREGION_Pos 8U /*!< MPU 1450:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU 1451:Drivers/CMSIS/Include/core_cm7.h **** 1452:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU 1453:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU 1454:Drivers/CMSIS/Include/core_cm7.h **** 1455:Drivers/CMSIS/Include/core_cm7.h **** /* MPU Control Register Definitions */ 1456:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU ARM GAS /tmp/ccdsDELB.s page 27 1457:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU 1458:Drivers/CMSIS/Include/core_cm7.h **** 1459:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU 1460:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU 1461:Drivers/CMSIS/Include/core_cm7.h **** 1462:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU 1463:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU 1464:Drivers/CMSIS/Include/core_cm7.h **** 1465:Drivers/CMSIS/Include/core_cm7.h **** /* MPU Region Number Register Definitions */ 1466:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RNR_REGION_Pos 0U /*!< MPU 1467:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU 1468:Drivers/CMSIS/Include/core_cm7.h **** 1469:Drivers/CMSIS/Include/core_cm7.h **** /* MPU Region Base Address Register Definitions */ 1470:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RBAR_ADDR_Pos 5U /*!< MPU 1471:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU 1472:Drivers/CMSIS/Include/core_cm7.h **** 1473:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RBAR_VALID_Pos 4U /*!< MPU 1474:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU 1475:Drivers/CMSIS/Include/core_cm7.h **** 1476:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RBAR_REGION_Pos 0U /*!< MPU 1477:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU 1478:Drivers/CMSIS/Include/core_cm7.h **** 1479:Drivers/CMSIS/Include/core_cm7.h **** /* MPU Region Attribute and Size Register Definitions */ 1480:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RASR_ATTRS_Pos 16U /*!< MPU 1481:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU 1482:Drivers/CMSIS/Include/core_cm7.h **** 1483:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RASR_XN_Pos 28U /*!< MPU 1484:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU 1485:Drivers/CMSIS/Include/core_cm7.h **** 1486:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RASR_AP_Pos 24U /*!< MPU 1487:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU 1488:Drivers/CMSIS/Include/core_cm7.h **** 1489:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RASR_TEX_Pos 19U /*!< MPU 1490:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU 1491:Drivers/CMSIS/Include/core_cm7.h **** 1492:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RASR_S_Pos 18U /*!< MPU 1493:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU 1494:Drivers/CMSIS/Include/core_cm7.h **** 1495:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RASR_C_Pos 17U /*!< MPU 1496:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU 1497:Drivers/CMSIS/Include/core_cm7.h **** 1498:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RASR_B_Pos 16U /*!< MPU 1499:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU 1500:Drivers/CMSIS/Include/core_cm7.h **** 1501:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RASR_SRD_Pos 8U /*!< MPU 1502:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU 1503:Drivers/CMSIS/Include/core_cm7.h **** 1504:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RASR_SIZE_Pos 1U /*!< MPU 1505:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU 1506:Drivers/CMSIS/Include/core_cm7.h **** 1507:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RASR_ENABLE_Pos 0U /*!< MPU 1508:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU 1509:Drivers/CMSIS/Include/core_cm7.h **** 1510:Drivers/CMSIS/Include/core_cm7.h **** /*@} end of group CMSIS_MPU */ 1511:Drivers/CMSIS/Include/core_cm7.h **** #endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */ 1512:Drivers/CMSIS/Include/core_cm7.h **** 1513:Drivers/CMSIS/Include/core_cm7.h **** ARM GAS /tmp/ccdsDELB.s page 28 1514:Drivers/CMSIS/Include/core_cm7.h **** /** 1515:Drivers/CMSIS/Include/core_cm7.h **** \ingroup CMSIS_core_register 1516:Drivers/CMSIS/Include/core_cm7.h **** \defgroup CMSIS_FPU Floating Point Unit (FPU) 1517:Drivers/CMSIS/Include/core_cm7.h **** \brief Type definitions for the Floating Point Unit (FPU) 1518:Drivers/CMSIS/Include/core_cm7.h **** @{ 1519:Drivers/CMSIS/Include/core_cm7.h **** */ 1520:Drivers/CMSIS/Include/core_cm7.h **** 1521:Drivers/CMSIS/Include/core_cm7.h **** /** 1522:Drivers/CMSIS/Include/core_cm7.h **** \brief Structure type to access the Floating Point Unit (FPU). 1523:Drivers/CMSIS/Include/core_cm7.h **** */ 1524:Drivers/CMSIS/Include/core_cm7.h **** typedef struct 1525:Drivers/CMSIS/Include/core_cm7.h **** { 1526:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED0[1U]; 1527:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control R 1528:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address R 1529:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Co 1530:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 1531:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 1532:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 1533:Drivers/CMSIS/Include/core_cm7.h **** } FPU_Type; 1534:Drivers/CMSIS/Include/core_cm7.h **** 1535:Drivers/CMSIS/Include/core_cm7.h **** /* Floating-Point Context Control Register Definitions */ 1536:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCC 1537:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCC 1538:Drivers/CMSIS/Include/core_cm7.h **** 1539:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCC 1540:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCC 1541:Drivers/CMSIS/Include/core_cm7.h **** 1542:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCC 1543:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCC 1544:Drivers/CMSIS/Include/core_cm7.h **** 1545:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCC 1546:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCC 1547:Drivers/CMSIS/Include/core_cm7.h **** 1548:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCC 1549:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCC 1550:Drivers/CMSIS/Include/core_cm7.h **** 1551:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCC 1552:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCC 1553:Drivers/CMSIS/Include/core_cm7.h **** 1554:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPCCR_THREAD_Pos 3U /*!< FPCC 1555:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCC 1556:Drivers/CMSIS/Include/core_cm7.h **** 1557:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPCCR_USER_Pos 1U /*!< FPCC 1558:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCC 1559:Drivers/CMSIS/Include/core_cm7.h **** 1560:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCC 1561:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCC 1562:Drivers/CMSIS/Include/core_cm7.h **** 1563:Drivers/CMSIS/Include/core_cm7.h **** /* Floating-Point Context Address Register Definitions */ 1564:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCA 1565:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCA 1566:Drivers/CMSIS/Include/core_cm7.h **** 1567:Drivers/CMSIS/Include/core_cm7.h **** /* Floating-Point Default Status Control Register Definitions */ 1568:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPDSCR_AHP_Pos 26U /*!< FPDS 1569:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDS 1570:Drivers/CMSIS/Include/core_cm7.h **** ARM GAS /tmp/ccdsDELB.s page 29 1571:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPDSCR_DN_Pos 25U /*!< FPDS 1572:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDS 1573:Drivers/CMSIS/Include/core_cm7.h **** 1574:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPDSCR_FZ_Pos 24U /*!< FPDS 1575:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDS 1576:Drivers/CMSIS/Include/core_cm7.h **** 1577:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPDSCR_RMode_Pos 22U /*!< FPDS 1578:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDS 1579:Drivers/CMSIS/Include/core_cm7.h **** 1580:Drivers/CMSIS/Include/core_cm7.h **** /* Media and FP Feature Register 0 Definitions */ 1581:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR 1582:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR 1583:Drivers/CMSIS/Include/core_cm7.h **** 1584:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR 1585:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR 1586:Drivers/CMSIS/Include/core_cm7.h **** 1587:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR 1588:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR 1589:Drivers/CMSIS/Include/core_cm7.h **** 1590:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR0_Divide_Pos 16U /*!< MVFR 1591:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR 1592:Drivers/CMSIS/Include/core_cm7.h **** 1593:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR 1594:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR 1595:Drivers/CMSIS/Include/core_cm7.h **** 1596:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR 1597:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR 1598:Drivers/CMSIS/Include/core_cm7.h **** 1599:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR 1600:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR 1601:Drivers/CMSIS/Include/core_cm7.h **** 1602:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR 1603:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR 1604:Drivers/CMSIS/Include/core_cm7.h **** 1605:Drivers/CMSIS/Include/core_cm7.h **** /* Media and FP Feature Register 1 Definitions */ 1606:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR 1607:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR 1608:Drivers/CMSIS/Include/core_cm7.h **** 1609:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR 1610:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR 1611:Drivers/CMSIS/Include/core_cm7.h **** 1612:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR 1613:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR 1614:Drivers/CMSIS/Include/core_cm7.h **** 1615:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR 1616:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR 1617:Drivers/CMSIS/Include/core_cm7.h **** 1618:Drivers/CMSIS/Include/core_cm7.h **** /* Media and FP Feature Register 2 Definitions */ 1619:Drivers/CMSIS/Include/core_cm7.h **** 1620:Drivers/CMSIS/Include/core_cm7.h **** /*@} end of group CMSIS_FPU */ 1621:Drivers/CMSIS/Include/core_cm7.h **** 1622:Drivers/CMSIS/Include/core_cm7.h **** 1623:Drivers/CMSIS/Include/core_cm7.h **** /** 1624:Drivers/CMSIS/Include/core_cm7.h **** \ingroup CMSIS_core_register 1625:Drivers/CMSIS/Include/core_cm7.h **** \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) 1626:Drivers/CMSIS/Include/core_cm7.h **** \brief Type definitions for the Core Debug Registers 1627:Drivers/CMSIS/Include/core_cm7.h **** @{ ARM GAS /tmp/ccdsDELB.s page 30 1628:Drivers/CMSIS/Include/core_cm7.h **** */ 1629:Drivers/CMSIS/Include/core_cm7.h **** 1630:Drivers/CMSIS/Include/core_cm7.h **** /** 1631:Drivers/CMSIS/Include/core_cm7.h **** \brief Structure type to access the Core Debug Register (CoreDebug). 1632:Drivers/CMSIS/Include/core_cm7.h **** */ 1633:Drivers/CMSIS/Include/core_cm7.h **** typedef struct 1634:Drivers/CMSIS/Include/core_cm7.h **** { 1635:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status 1636:Drivers/CMSIS/Include/core_cm7.h **** __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Reg 1637:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Registe 1638:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Cont 1639:Drivers/CMSIS/Include/core_cm7.h **** } CoreDebug_Type; 1640:Drivers/CMSIS/Include/core_cm7.h **** 1641:Drivers/CMSIS/Include/core_cm7.h **** /* Debug Halting Control and Status Register Definitions */ 1642:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< Core 1643:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< Core 1644:Drivers/CMSIS/Include/core_cm7.h **** 1645:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< Core 1646:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< Core 1647:Drivers/CMSIS/Include/core_cm7.h **** 1648:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< Core 1649:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< Core 1650:Drivers/CMSIS/Include/core_cm7.h **** 1651:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< Core 1652:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< Core 1653:Drivers/CMSIS/Include/core_cm7.h **** 1654:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< Core 1655:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< Core 1656:Drivers/CMSIS/Include/core_cm7.h **** 1657:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< Core 1658:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< Core 1659:Drivers/CMSIS/Include/core_cm7.h **** 1660:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< Core 1661:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< Core 1662:Drivers/CMSIS/Include/core_cm7.h **** 1663:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< Core 1664:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< Core 1665:Drivers/CMSIS/Include/core_cm7.h **** 1666:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< Core 1667:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< Core 1668:Drivers/CMSIS/Include/core_cm7.h **** 1669:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< Core 1670:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< Core 1671:Drivers/CMSIS/Include/core_cm7.h **** 1672:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< Core 1673:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< Core 1674:Drivers/CMSIS/Include/core_cm7.h **** 1675:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< Core 1676:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< Core 1677:Drivers/CMSIS/Include/core_cm7.h **** 1678:Drivers/CMSIS/Include/core_cm7.h **** /* Debug Core Register Selector Register Definitions */ 1679:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< Core 1680:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< Core 1681:Drivers/CMSIS/Include/core_cm7.h **** 1682:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< Core 1683:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< Core 1684:Drivers/CMSIS/Include/core_cm7.h **** ARM GAS /tmp/ccdsDELB.s page 31 1685:Drivers/CMSIS/Include/core_cm7.h **** /* Debug Exception and Monitor Control Register Definitions */ 1686:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< Core 1687:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< Core 1688:Drivers/CMSIS/Include/core_cm7.h **** 1689:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< Core 1690:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< Core 1691:Drivers/CMSIS/Include/core_cm7.h **** 1692:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< Core 1693:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< Core 1694:Drivers/CMSIS/Include/core_cm7.h **** 1695:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< Core 1696:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< Core 1697:Drivers/CMSIS/Include/core_cm7.h **** 1698:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< Core 1699:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< Core 1700:Drivers/CMSIS/Include/core_cm7.h **** 1701:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< Core 1702:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< Core 1703:Drivers/CMSIS/Include/core_cm7.h **** 1704:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< Core 1705:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< Core 1706:Drivers/CMSIS/Include/core_cm7.h **** 1707:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< Core 1708:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< Core 1709:Drivers/CMSIS/Include/core_cm7.h **** 1710:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< Core 1711:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< Core 1712:Drivers/CMSIS/Include/core_cm7.h **** 1713:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< Core 1714:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< Core 1715:Drivers/CMSIS/Include/core_cm7.h **** 1716:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< Core 1717:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< Core 1718:Drivers/CMSIS/Include/core_cm7.h **** 1719:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< Core 1720:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< Core 1721:Drivers/CMSIS/Include/core_cm7.h **** 1722:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< Core 1723:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< Core 1724:Drivers/CMSIS/Include/core_cm7.h **** 1725:Drivers/CMSIS/Include/core_cm7.h **** /*@} end of group CMSIS_CoreDebug */ 1726:Drivers/CMSIS/Include/core_cm7.h **** 1727:Drivers/CMSIS/Include/core_cm7.h **** 1728:Drivers/CMSIS/Include/core_cm7.h **** /** 1729:Drivers/CMSIS/Include/core_cm7.h **** \ingroup CMSIS_core_register 1730:Drivers/CMSIS/Include/core_cm7.h **** \defgroup CMSIS_core_bitfield Core register bit field macros 1731:Drivers/CMSIS/Include/core_cm7.h **** \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). 1732:Drivers/CMSIS/Include/core_cm7.h **** @{ 1733:Drivers/CMSIS/Include/core_cm7.h **** */ 1734:Drivers/CMSIS/Include/core_cm7.h **** 1735:Drivers/CMSIS/Include/core_cm7.h **** /** 1736:Drivers/CMSIS/Include/core_cm7.h **** \brief Mask and shift a bit field value for use in a register bit range. 1737:Drivers/CMSIS/Include/core_cm7.h **** \param[in] field Name of the register bit field. 1738:Drivers/CMSIS/Include/core_cm7.h **** \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. 1739:Drivers/CMSIS/Include/core_cm7.h **** \return Masked and shifted value. 1740:Drivers/CMSIS/Include/core_cm7.h **** */ 1741:Drivers/CMSIS/Include/core_cm7.h **** #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) ARM GAS /tmp/ccdsDELB.s page 32 1742:Drivers/CMSIS/Include/core_cm7.h **** 1743:Drivers/CMSIS/Include/core_cm7.h **** /** 1744:Drivers/CMSIS/Include/core_cm7.h **** \brief Mask and shift a register value to extract a bit filed value. 1745:Drivers/CMSIS/Include/core_cm7.h **** \param[in] field Name of the register bit field. 1746:Drivers/CMSIS/Include/core_cm7.h **** \param[in] value Value of register. This parameter is interpreted as an uint32_t type. 1747:Drivers/CMSIS/Include/core_cm7.h **** \return Masked and shifted bit field value. 1748:Drivers/CMSIS/Include/core_cm7.h **** */ 1749:Drivers/CMSIS/Include/core_cm7.h **** #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) 1750:Drivers/CMSIS/Include/core_cm7.h **** 1751:Drivers/CMSIS/Include/core_cm7.h **** /*@} end of group CMSIS_core_bitfield */ 1752:Drivers/CMSIS/Include/core_cm7.h **** 1753:Drivers/CMSIS/Include/core_cm7.h **** 1754:Drivers/CMSIS/Include/core_cm7.h **** /** 1755:Drivers/CMSIS/Include/core_cm7.h **** \ingroup CMSIS_core_register 1756:Drivers/CMSIS/Include/core_cm7.h **** \defgroup CMSIS_core_base Core Definitions 1757:Drivers/CMSIS/Include/core_cm7.h **** \brief Definitions for base addresses, unions, and structures. 1758:Drivers/CMSIS/Include/core_cm7.h **** @{ 1759:Drivers/CMSIS/Include/core_cm7.h **** */ 1760:Drivers/CMSIS/Include/core_cm7.h **** 1761:Drivers/CMSIS/Include/core_cm7.h **** /* Memory mapping of Core Hardware */ 1762:Drivers/CMSIS/Include/core_cm7.h **** #define SCS_BASE (0xE000E000UL) /*!< System Control Space Bas 1763:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ 1764:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ 1765:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ 1766:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address 1767:Drivers/CMSIS/Include/core_cm7.h **** #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ 1768:Drivers/CMSIS/Include/core_cm7.h **** #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ 1769:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Bas 1770:Drivers/CMSIS/Include/core_cm7.h **** 1771:Drivers/CMSIS/Include/core_cm7.h **** #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register 1772:Drivers/CMSIS/Include/core_cm7.h **** #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct 1773:Drivers/CMSIS/Include/core_cm7.h **** #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration st 1774:Drivers/CMSIS/Include/core_cm7.h **** #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struc 1775:Drivers/CMSIS/Include/core_cm7.h **** #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct 1776:Drivers/CMSIS/Include/core_cm7.h **** #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct 1777:Drivers/CMSIS/Include/core_cm7.h **** #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct 1778:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration 1779:Drivers/CMSIS/Include/core_cm7.h **** 1780:Drivers/CMSIS/Include/core_cm7.h **** #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) 1781:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit * 1782:Drivers/CMSIS/Include/core_cm7.h **** #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit * 1783:Drivers/CMSIS/Include/core_cm7.h **** #endif 1784:Drivers/CMSIS/Include/core_cm7.h **** 1785:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ 1786:Drivers/CMSIS/Include/core_cm7.h **** #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ 1787:Drivers/CMSIS/Include/core_cm7.h **** 1788:Drivers/CMSIS/Include/core_cm7.h **** /*@} */ 1789:Drivers/CMSIS/Include/core_cm7.h **** 1790:Drivers/CMSIS/Include/core_cm7.h **** 1791:Drivers/CMSIS/Include/core_cm7.h **** 1792:Drivers/CMSIS/Include/core_cm7.h **** /******************************************************************************* 1793:Drivers/CMSIS/Include/core_cm7.h **** * Hardware Abstraction Layer 1794:Drivers/CMSIS/Include/core_cm7.h **** Core Function Interface contains: 1795:Drivers/CMSIS/Include/core_cm7.h **** - Core NVIC Functions 1796:Drivers/CMSIS/Include/core_cm7.h **** - Core SysTick Functions 1797:Drivers/CMSIS/Include/core_cm7.h **** - Core Debug Functions 1798:Drivers/CMSIS/Include/core_cm7.h **** - Core Register Access Functions ARM GAS /tmp/ccdsDELB.s page 33 1799:Drivers/CMSIS/Include/core_cm7.h **** ******************************************************************************/ 1800:Drivers/CMSIS/Include/core_cm7.h **** /** 1801:Drivers/CMSIS/Include/core_cm7.h **** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference 1802:Drivers/CMSIS/Include/core_cm7.h **** */ 1803:Drivers/CMSIS/Include/core_cm7.h **** 1804:Drivers/CMSIS/Include/core_cm7.h **** 1805:Drivers/CMSIS/Include/core_cm7.h **** 1806:Drivers/CMSIS/Include/core_cm7.h **** /* ########################## NVIC functions #################################### */ 1807:Drivers/CMSIS/Include/core_cm7.h **** /** 1808:Drivers/CMSIS/Include/core_cm7.h **** \ingroup CMSIS_Core_FunctionInterface 1809:Drivers/CMSIS/Include/core_cm7.h **** \defgroup CMSIS_Core_NVICFunctions NVIC Functions 1810:Drivers/CMSIS/Include/core_cm7.h **** \brief Functions that manage interrupts and exceptions via the NVIC. 1811:Drivers/CMSIS/Include/core_cm7.h **** @{ 1812:Drivers/CMSIS/Include/core_cm7.h **** */ 1813:Drivers/CMSIS/Include/core_cm7.h **** 1814:Drivers/CMSIS/Include/core_cm7.h **** #ifdef CMSIS_NVIC_VIRTUAL 1815:Drivers/CMSIS/Include/core_cm7.h **** #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE 1816:Drivers/CMSIS/Include/core_cm7.h **** #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" 1817:Drivers/CMSIS/Include/core_cm7.h **** #endif 1818:Drivers/CMSIS/Include/core_cm7.h **** #include CMSIS_NVIC_VIRTUAL_HEADER_FILE 1819:Drivers/CMSIS/Include/core_cm7.h **** #else 1820:Drivers/CMSIS/Include/core_cm7.h **** #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping 1821:Drivers/CMSIS/Include/core_cm7.h **** #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping 1822:Drivers/CMSIS/Include/core_cm7.h **** #define NVIC_EnableIRQ __NVIC_EnableIRQ 1823:Drivers/CMSIS/Include/core_cm7.h **** #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ 1824:Drivers/CMSIS/Include/core_cm7.h **** #define NVIC_DisableIRQ __NVIC_DisableIRQ 1825:Drivers/CMSIS/Include/core_cm7.h **** #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ 1826:Drivers/CMSIS/Include/core_cm7.h **** #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ 1827:Drivers/CMSIS/Include/core_cm7.h **** #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ 1828:Drivers/CMSIS/Include/core_cm7.h **** #define NVIC_GetActive __NVIC_GetActive 1829:Drivers/CMSIS/Include/core_cm7.h **** #define NVIC_SetPriority __NVIC_SetPriority 1830:Drivers/CMSIS/Include/core_cm7.h **** #define NVIC_GetPriority __NVIC_GetPriority 1831:Drivers/CMSIS/Include/core_cm7.h **** #define NVIC_SystemReset __NVIC_SystemReset 1832:Drivers/CMSIS/Include/core_cm7.h **** #endif /* CMSIS_NVIC_VIRTUAL */ 1833:Drivers/CMSIS/Include/core_cm7.h **** 1834:Drivers/CMSIS/Include/core_cm7.h **** #ifdef CMSIS_VECTAB_VIRTUAL 1835:Drivers/CMSIS/Include/core_cm7.h **** #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE 1836:Drivers/CMSIS/Include/core_cm7.h **** #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" 1837:Drivers/CMSIS/Include/core_cm7.h **** #endif 1838:Drivers/CMSIS/Include/core_cm7.h **** #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE 1839:Drivers/CMSIS/Include/core_cm7.h **** #else 1840:Drivers/CMSIS/Include/core_cm7.h **** #define NVIC_SetVector __NVIC_SetVector 1841:Drivers/CMSIS/Include/core_cm7.h **** #define NVIC_GetVector __NVIC_GetVector 1842:Drivers/CMSIS/Include/core_cm7.h **** #endif /* (CMSIS_VECTAB_VIRTUAL) */ 1843:Drivers/CMSIS/Include/core_cm7.h **** 1844:Drivers/CMSIS/Include/core_cm7.h **** #define NVIC_USER_IRQ_OFFSET 16 1845:Drivers/CMSIS/Include/core_cm7.h **** 1846:Drivers/CMSIS/Include/core_cm7.h **** 1847:Drivers/CMSIS/Include/core_cm7.h **** /* The following EXC_RETURN values are saved the LR on exception entry */ 1848:Drivers/CMSIS/Include/core_cm7.h **** #define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after ret 1849:Drivers/CMSIS/Include/core_cm7.h **** #define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after retu 1850:Drivers/CMSIS/Include/core_cm7.h **** #define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after retu 1851:Drivers/CMSIS/Include/core_cm7.h **** #define EXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after ret 1852:Drivers/CMSIS/Include/core_cm7.h **** #define EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after retu 1853:Drivers/CMSIS/Include/core_cm7.h **** #define EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after retu 1854:Drivers/CMSIS/Include/core_cm7.h **** 1855:Drivers/CMSIS/Include/core_cm7.h **** ARM GAS /tmp/ccdsDELB.s page 34 1856:Drivers/CMSIS/Include/core_cm7.h **** /** 1857:Drivers/CMSIS/Include/core_cm7.h **** \brief Set Priority Grouping 1858:Drivers/CMSIS/Include/core_cm7.h **** \details Sets the priority grouping field using the required unlock sequence. 1859:Drivers/CMSIS/Include/core_cm7.h **** The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. 1860:Drivers/CMSIS/Include/core_cm7.h **** Only values from 0..7 are used. 1861:Drivers/CMSIS/Include/core_cm7.h **** In case of a conflict between priority grouping and available 1862:Drivers/CMSIS/Include/core_cm7.h **** priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. 1863:Drivers/CMSIS/Include/core_cm7.h **** \param [in] PriorityGroup Priority grouping field. 1864:Drivers/CMSIS/Include/core_cm7.h **** */ 1865:Drivers/CMSIS/Include/core_cm7.h **** __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) 1866:Drivers/CMSIS/Include/core_cm7.h **** { 1867:Drivers/CMSIS/Include/core_cm7.h **** uint32_t reg_value; 1868:Drivers/CMSIS/Include/core_cm7.h **** uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 a 1869:Drivers/CMSIS/Include/core_cm7.h **** 1870:Drivers/CMSIS/Include/core_cm7.h **** reg_value = SCB->AIRCR; /* read old register 1871:Drivers/CMSIS/Include/core_cm7.h **** reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to chan 1872:Drivers/CMSIS/Include/core_cm7.h **** reg_value = (reg_value | 1873:Drivers/CMSIS/Include/core_cm7.h **** ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | 1874:Drivers/CMSIS/Include/core_cm7.h **** (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key a 1875:Drivers/CMSIS/Include/core_cm7.h **** SCB->AIRCR = reg_value; 1876:Drivers/CMSIS/Include/core_cm7.h **** } 1877:Drivers/CMSIS/Include/core_cm7.h **** 1878:Drivers/CMSIS/Include/core_cm7.h **** 1879:Drivers/CMSIS/Include/core_cm7.h **** /** 1880:Drivers/CMSIS/Include/core_cm7.h **** \brief Get Priority Grouping 1881:Drivers/CMSIS/Include/core_cm7.h **** \details Reads the priority grouping field from the NVIC Interrupt Controller. 1882:Drivers/CMSIS/Include/core_cm7.h **** \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). 1883:Drivers/CMSIS/Include/core_cm7.h **** */ 1884:Drivers/CMSIS/Include/core_cm7.h **** __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) 1885:Drivers/CMSIS/Include/core_cm7.h **** { 1886:Drivers/CMSIS/Include/core_cm7.h **** return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); 1887:Drivers/CMSIS/Include/core_cm7.h **** } 1888:Drivers/CMSIS/Include/core_cm7.h **** 1889:Drivers/CMSIS/Include/core_cm7.h **** 1890:Drivers/CMSIS/Include/core_cm7.h **** /** 1891:Drivers/CMSIS/Include/core_cm7.h **** \brief Enable Interrupt 1892:Drivers/CMSIS/Include/core_cm7.h **** \details Enables a device specific interrupt in the NVIC interrupt controller. 1893:Drivers/CMSIS/Include/core_cm7.h **** \param [in] IRQn Device specific interrupt number. 1894:Drivers/CMSIS/Include/core_cm7.h **** \note IRQn must not be negative. 1895:Drivers/CMSIS/Include/core_cm7.h **** */ 1896:Drivers/CMSIS/Include/core_cm7.h **** __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) 1897:Drivers/CMSIS/Include/core_cm7.h **** { 1898:Drivers/CMSIS/Include/core_cm7.h **** if ((int32_t)(IRQn) >= 0) 1899:Drivers/CMSIS/Include/core_cm7.h **** { 1900:Drivers/CMSIS/Include/core_cm7.h **** NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 1901:Drivers/CMSIS/Include/core_cm7.h **** } 1902:Drivers/CMSIS/Include/core_cm7.h **** } 1903:Drivers/CMSIS/Include/core_cm7.h **** 1904:Drivers/CMSIS/Include/core_cm7.h **** 1905:Drivers/CMSIS/Include/core_cm7.h **** /** 1906:Drivers/CMSIS/Include/core_cm7.h **** \brief Get Interrupt Enable status 1907:Drivers/CMSIS/Include/core_cm7.h **** \details Returns a device specific interrupt enable status from the NVIC interrupt controller. 1908:Drivers/CMSIS/Include/core_cm7.h **** \param [in] IRQn Device specific interrupt number. 1909:Drivers/CMSIS/Include/core_cm7.h **** \return 0 Interrupt is not enabled. 1910:Drivers/CMSIS/Include/core_cm7.h **** \return 1 Interrupt is enabled. 1911:Drivers/CMSIS/Include/core_cm7.h **** \note IRQn must not be negative. 1912:Drivers/CMSIS/Include/core_cm7.h **** */ ARM GAS /tmp/ccdsDELB.s page 35 1913:Drivers/CMSIS/Include/core_cm7.h **** __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) 1914:Drivers/CMSIS/Include/core_cm7.h **** { 1915:Drivers/CMSIS/Include/core_cm7.h **** if ((int32_t)(IRQn) >= 0) 1916:Drivers/CMSIS/Include/core_cm7.h **** { 1917:Drivers/CMSIS/Include/core_cm7.h **** return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL) 1918:Drivers/CMSIS/Include/core_cm7.h **** } 1919:Drivers/CMSIS/Include/core_cm7.h **** else 1920:Drivers/CMSIS/Include/core_cm7.h **** { 1921:Drivers/CMSIS/Include/core_cm7.h **** return(0U); 1922:Drivers/CMSIS/Include/core_cm7.h **** } 1923:Drivers/CMSIS/Include/core_cm7.h **** } 1924:Drivers/CMSIS/Include/core_cm7.h **** 1925:Drivers/CMSIS/Include/core_cm7.h **** 1926:Drivers/CMSIS/Include/core_cm7.h **** /** 1927:Drivers/CMSIS/Include/core_cm7.h **** \brief Disable Interrupt 1928:Drivers/CMSIS/Include/core_cm7.h **** \details Disables a device specific interrupt in the NVIC interrupt controller. 1929:Drivers/CMSIS/Include/core_cm7.h **** \param [in] IRQn Device specific interrupt number. 1930:Drivers/CMSIS/Include/core_cm7.h **** \note IRQn must not be negative. 1931:Drivers/CMSIS/Include/core_cm7.h **** */ 1932:Drivers/CMSIS/Include/core_cm7.h **** __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) 1933:Drivers/CMSIS/Include/core_cm7.h **** { 1934:Drivers/CMSIS/Include/core_cm7.h **** if ((int32_t)(IRQn) >= 0) 1935:Drivers/CMSIS/Include/core_cm7.h **** { 1936:Drivers/CMSIS/Include/core_cm7.h **** NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 1937:Drivers/CMSIS/Include/core_cm7.h **** __DSB(); 1938:Drivers/CMSIS/Include/core_cm7.h **** __ISB(); 1939:Drivers/CMSIS/Include/core_cm7.h **** } 1940:Drivers/CMSIS/Include/core_cm7.h **** } 1941:Drivers/CMSIS/Include/core_cm7.h **** 1942:Drivers/CMSIS/Include/core_cm7.h **** 1943:Drivers/CMSIS/Include/core_cm7.h **** /** 1944:Drivers/CMSIS/Include/core_cm7.h **** \brief Get Pending Interrupt 1945:Drivers/CMSIS/Include/core_cm7.h **** \details Reads the NVIC pending register and returns the pending bit for the specified device spe 1946:Drivers/CMSIS/Include/core_cm7.h **** \param [in] IRQn Device specific interrupt number. 1947:Drivers/CMSIS/Include/core_cm7.h **** \return 0 Interrupt status is not pending. 1948:Drivers/CMSIS/Include/core_cm7.h **** \return 1 Interrupt status is pending. 1949:Drivers/CMSIS/Include/core_cm7.h **** \note IRQn must not be negative. 1950:Drivers/CMSIS/Include/core_cm7.h **** */ 1951:Drivers/CMSIS/Include/core_cm7.h **** __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) 1952:Drivers/CMSIS/Include/core_cm7.h **** { 1953:Drivers/CMSIS/Include/core_cm7.h **** if ((int32_t)(IRQn) >= 0) 1954:Drivers/CMSIS/Include/core_cm7.h **** { 1955:Drivers/CMSIS/Include/core_cm7.h **** return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL) 1956:Drivers/CMSIS/Include/core_cm7.h **** } 1957:Drivers/CMSIS/Include/core_cm7.h **** else 1958:Drivers/CMSIS/Include/core_cm7.h **** { 1959:Drivers/CMSIS/Include/core_cm7.h **** return(0U); 1960:Drivers/CMSIS/Include/core_cm7.h **** } 1961:Drivers/CMSIS/Include/core_cm7.h **** } 1962:Drivers/CMSIS/Include/core_cm7.h **** 1963:Drivers/CMSIS/Include/core_cm7.h **** 1964:Drivers/CMSIS/Include/core_cm7.h **** /** 1965:Drivers/CMSIS/Include/core_cm7.h **** \brief Set Pending Interrupt 1966:Drivers/CMSIS/Include/core_cm7.h **** \details Sets the pending bit of a device specific interrupt in the NVIC pending register. 1967:Drivers/CMSIS/Include/core_cm7.h **** \param [in] IRQn Device specific interrupt number. 1968:Drivers/CMSIS/Include/core_cm7.h **** \note IRQn must not be negative. 1969:Drivers/CMSIS/Include/core_cm7.h **** */ ARM GAS /tmp/ccdsDELB.s page 36 1970:Drivers/CMSIS/Include/core_cm7.h **** __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) 1971:Drivers/CMSIS/Include/core_cm7.h **** { 1972:Drivers/CMSIS/Include/core_cm7.h **** if ((int32_t)(IRQn) >= 0) 1973:Drivers/CMSIS/Include/core_cm7.h **** { 1974:Drivers/CMSIS/Include/core_cm7.h **** NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 1975:Drivers/CMSIS/Include/core_cm7.h **** } 1976:Drivers/CMSIS/Include/core_cm7.h **** } 1977:Drivers/CMSIS/Include/core_cm7.h **** 1978:Drivers/CMSIS/Include/core_cm7.h **** 1979:Drivers/CMSIS/Include/core_cm7.h **** /** 1980:Drivers/CMSIS/Include/core_cm7.h **** \brief Clear Pending Interrupt 1981:Drivers/CMSIS/Include/core_cm7.h **** \details Clears the pending bit of a device specific interrupt in the NVIC pending register. 1982:Drivers/CMSIS/Include/core_cm7.h **** \param [in] IRQn Device specific interrupt number. 1983:Drivers/CMSIS/Include/core_cm7.h **** \note IRQn must not be negative. 1984:Drivers/CMSIS/Include/core_cm7.h **** */ 1985:Drivers/CMSIS/Include/core_cm7.h **** __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) 1986:Drivers/CMSIS/Include/core_cm7.h **** { 1987:Drivers/CMSIS/Include/core_cm7.h **** if ((int32_t)(IRQn) >= 0) 1988:Drivers/CMSIS/Include/core_cm7.h **** { 1989:Drivers/CMSIS/Include/core_cm7.h **** NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 1990:Drivers/CMSIS/Include/core_cm7.h **** } 1991:Drivers/CMSIS/Include/core_cm7.h **** } 1992:Drivers/CMSIS/Include/core_cm7.h **** 1993:Drivers/CMSIS/Include/core_cm7.h **** 1994:Drivers/CMSIS/Include/core_cm7.h **** /** 1995:Drivers/CMSIS/Include/core_cm7.h **** \brief Get Active Interrupt 1996:Drivers/CMSIS/Include/core_cm7.h **** \details Reads the active register in the NVIC and returns the active bit for the device specific 1997:Drivers/CMSIS/Include/core_cm7.h **** \param [in] IRQn Device specific interrupt number. 1998:Drivers/CMSIS/Include/core_cm7.h **** \return 0 Interrupt status is not active. 1999:Drivers/CMSIS/Include/core_cm7.h **** \return 1 Interrupt status is active. 2000:Drivers/CMSIS/Include/core_cm7.h **** \note IRQn must not be negative. 2001:Drivers/CMSIS/Include/core_cm7.h **** */ 2002:Drivers/CMSIS/Include/core_cm7.h **** __STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) 2003:Drivers/CMSIS/Include/core_cm7.h **** { 2004:Drivers/CMSIS/Include/core_cm7.h **** if ((int32_t)(IRQn) >= 0) 2005:Drivers/CMSIS/Include/core_cm7.h **** { 2006:Drivers/CMSIS/Include/core_cm7.h **** return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL) 2007:Drivers/CMSIS/Include/core_cm7.h **** } 2008:Drivers/CMSIS/Include/core_cm7.h **** else 2009:Drivers/CMSIS/Include/core_cm7.h **** { 2010:Drivers/CMSIS/Include/core_cm7.h **** return(0U); 2011:Drivers/CMSIS/Include/core_cm7.h **** } 2012:Drivers/CMSIS/Include/core_cm7.h **** } 2013:Drivers/CMSIS/Include/core_cm7.h **** 2014:Drivers/CMSIS/Include/core_cm7.h **** 2015:Drivers/CMSIS/Include/core_cm7.h **** /** 2016:Drivers/CMSIS/Include/core_cm7.h **** \brief Set Interrupt Priority 2017:Drivers/CMSIS/Include/core_cm7.h **** \details Sets the priority of a device specific interrupt or a processor exception. 2018:Drivers/CMSIS/Include/core_cm7.h **** The interrupt number can be positive to specify a device specific interrupt, 2019:Drivers/CMSIS/Include/core_cm7.h **** or negative to specify a processor exception. 2020:Drivers/CMSIS/Include/core_cm7.h **** \param [in] IRQn Interrupt number. 2021:Drivers/CMSIS/Include/core_cm7.h **** \param [in] priority Priority to set. 2022:Drivers/CMSIS/Include/core_cm7.h **** \note The priority cannot be set for every processor exception. 2023:Drivers/CMSIS/Include/core_cm7.h **** */ 2024:Drivers/CMSIS/Include/core_cm7.h **** __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) 2025:Drivers/CMSIS/Include/core_cm7.h **** { 2026:Drivers/CMSIS/Include/core_cm7.h **** if ((int32_t)(IRQn) >= 0) ARM GAS /tmp/ccdsDELB.s page 37 2027:Drivers/CMSIS/Include/core_cm7.h **** { 2028:Drivers/CMSIS/Include/core_cm7.h **** NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & ( 2029:Drivers/CMSIS/Include/core_cm7.h **** } 2030:Drivers/CMSIS/Include/core_cm7.h **** else 2031:Drivers/CMSIS/Include/core_cm7.h **** { 2032:Drivers/CMSIS/Include/core_cm7.h **** SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & ( 2033:Drivers/CMSIS/Include/core_cm7.h **** } 2034:Drivers/CMSIS/Include/core_cm7.h **** } 2035:Drivers/CMSIS/Include/core_cm7.h **** 2036:Drivers/CMSIS/Include/core_cm7.h **** 2037:Drivers/CMSIS/Include/core_cm7.h **** /** 2038:Drivers/CMSIS/Include/core_cm7.h **** \brief Get Interrupt Priority 2039:Drivers/CMSIS/Include/core_cm7.h **** \details Reads the priority of a device specific interrupt or a processor exception. 2040:Drivers/CMSIS/Include/core_cm7.h **** The interrupt number can be positive to specify a device specific interrupt, 2041:Drivers/CMSIS/Include/core_cm7.h **** or negative to specify a processor exception. 2042:Drivers/CMSIS/Include/core_cm7.h **** \param [in] IRQn Interrupt number. 2043:Drivers/CMSIS/Include/core_cm7.h **** \return Interrupt Priority. 2044:Drivers/CMSIS/Include/core_cm7.h **** Value is aligned automatically to the implemented priority bits of the microc 2045:Drivers/CMSIS/Include/core_cm7.h **** */ 2046:Drivers/CMSIS/Include/core_cm7.h **** __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) 2047:Drivers/CMSIS/Include/core_cm7.h **** { 2048:Drivers/CMSIS/Include/core_cm7.h **** 2049:Drivers/CMSIS/Include/core_cm7.h **** if ((int32_t)(IRQn) >= 0) 2050:Drivers/CMSIS/Include/core_cm7.h **** { 2051:Drivers/CMSIS/Include/core_cm7.h **** return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); 2052:Drivers/CMSIS/Include/core_cm7.h **** } 2053:Drivers/CMSIS/Include/core_cm7.h **** else 2054:Drivers/CMSIS/Include/core_cm7.h **** { 2055:Drivers/CMSIS/Include/core_cm7.h **** return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); 2056:Drivers/CMSIS/Include/core_cm7.h **** } 2057:Drivers/CMSIS/Include/core_cm7.h **** } 2058:Drivers/CMSIS/Include/core_cm7.h **** 2059:Drivers/CMSIS/Include/core_cm7.h **** 2060:Drivers/CMSIS/Include/core_cm7.h **** /** 2061:Drivers/CMSIS/Include/core_cm7.h **** \brief Encode Priority 2062:Drivers/CMSIS/Include/core_cm7.h **** \details Encodes the priority for an interrupt with the given priority group, 2063:Drivers/CMSIS/Include/core_cm7.h **** preemptive priority value, and subpriority value. 2064:Drivers/CMSIS/Include/core_cm7.h **** In case of a conflict between priority grouping and available 2065:Drivers/CMSIS/Include/core_cm7.h **** priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. 2066:Drivers/CMSIS/Include/core_cm7.h **** \param [in] PriorityGroup Used priority group. 2067:Drivers/CMSIS/Include/core_cm7.h **** \param [in] PreemptPriority Preemptive priority value (starting from 0). 2068:Drivers/CMSIS/Include/core_cm7.h **** \param [in] SubPriority Subpriority value (starting from 0). 2069:Drivers/CMSIS/Include/core_cm7.h **** \return Encoded priority. Value can be used in the function \ref NVIC_SetP 2070:Drivers/CMSIS/Include/core_cm7.h **** */ 2071:Drivers/CMSIS/Include/core_cm7.h **** __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uin 2072:Drivers/CMSIS/Include/core_cm7.h **** { 28 .loc 1 2072 1 view -0 29 .cfi_startproc 30 @ args = 0, pretend = 0, frame = 0 31 @ frame_needed = 0, uses_anonymous_args = 0 32 @ link register save eliminated. 2073:Drivers/CMSIS/Include/core_cm7.h **** uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used 33 .loc 1 2073 3 view .LVU1 34 .loc 1 2073 12 is_stmt 0 view .LVU2 35 0000 00F00700 and r0, r0, #7 36 .LVL1: 2074:Drivers/CMSIS/Include/core_cm7.h **** uint32_t PreemptPriorityBits; ARM GAS /tmp/ccdsDELB.s page 38 37 .loc 1 2074 3 is_stmt 1 view .LVU3 2075:Drivers/CMSIS/Include/core_cm7.h **** uint32_t SubPriorityBits; 38 .loc 1 2075 3 view .LVU4 2076:Drivers/CMSIS/Include/core_cm7.h **** 2077:Drivers/CMSIS/Include/core_cm7.h **** PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NV 39 .loc 1 2077 3 view .LVU5 40 .loc 1 2077 31 is_stmt 0 view .LVU6 41 0004 C0F1070C rsb ip, r0, #7 42 .loc 1 2077 23 view .LVU7 43 0008 BCF1040F cmp ip, #4 44 000c 28BF it cs 45 000e 4FF0040C movcs ip, #4 46 .LVL2: 2078:Drivers/CMSIS/Include/core_cm7.h **** SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint 47 .loc 1 2078 3 is_stmt 1 view .LVU8 48 .loc 1 2078 44 is_stmt 0 view .LVU9 49 0012 031D adds r3, r0, #4 50 .loc 1 2078 109 view .LVU10 51 0014 062B cmp r3, #6 52 0016 0CD9 bls .L3 53 .loc 1 2078 109 discriminator 1 view .LVU11 54 0018 C31E subs r3, r0, #3 55 .L2: 56 .LVL3: 2079:Drivers/CMSIS/Include/core_cm7.h **** 2080:Drivers/CMSIS/Include/core_cm7.h **** return ( 57 .loc 1 2080 3 is_stmt 1 discriminator 4 view .LVU12 2081:Drivers/CMSIS/Include/core_cm7.h **** ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits 58 .loc 1 2081 30 is_stmt 0 discriminator 4 view .LVU13 59 001a 4FF0FF30 mov r0, #-1 60 .LVL4: 61 .loc 1 2081 30 discriminator 4 view .LVU14 62 001e 00FA0CFC lsl ip, r0, ip 63 .LVL5: 64 .loc 1 2081 30 discriminator 4 view .LVU15 65 0022 21EA0C01 bic r1, r1, ip 66 .LVL6: 67 .loc 1 2081 82 discriminator 4 view .LVU16 68 0026 9940 lsls r1, r1, r3 2082:Drivers/CMSIS/Include/core_cm7.h **** ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) 69 .loc 1 2082 30 discriminator 4 view .LVU17 70 0028 9840 lsls r0, r0, r3 71 002a 22EA0000 bic r0, r2, r0 2083:Drivers/CMSIS/Include/core_cm7.h **** ); 2084:Drivers/CMSIS/Include/core_cm7.h **** } 72 .loc 1 2084 1 discriminator 4 view .LVU18 73 002e 0843 orrs r0, r0, r1 74 0030 7047 bx lr 75 .LVL7: 76 .L3: 2078:Drivers/CMSIS/Include/core_cm7.h **** 77 .loc 1 2078 109 view .LVU19 78 0032 0023 movs r3, #0 79 0034 F1E7 b .L2 80 .cfi_endproc 81 .LFE113: 83 .section .text.MX_SDMMC1_SD_Init,"ax",%progbits ARM GAS /tmp/ccdsDELB.s page 39 84 .align 1 85 .syntax unified 86 .thumb 87 .thumb_func 88 .fpu fpv5-d16 90 MX_SDMMC1_SD_Init: 91 .LFB1190: 92 .file 2 "Src/main.c" 1:Src/main.c **** /* USER CODE BEGIN Header */ 2:Src/main.c **** /** 3:Src/main.c **** ****************************************************************************** 4:Src/main.c **** * @file : main.c 5:Src/main.c **** * @brief : Main program body 6:Src/main.c **** ****************************************************************************** 7:Src/main.c **** * @attention 8:Src/main.c **** * 9:Src/main.c **** * Copyright (c) 2023 STMicroelectronics. 10:Src/main.c **** * All rights reserved. 11:Src/main.c **** * 12:Src/main.c **** * This software is licensed under terms that can be found in the LICENSE file 13:Src/main.c **** * in the root directory of this software component. 14:Src/main.c **** * If no LICENSE file comes with this software, it is provided AS-IS. 15:Src/main.c **** * 16:Src/main.c **** ****************************************************************************** 17:Src/main.c **** */ 18:Src/main.c **** /* USER CODE END Header */ 19:Src/main.c **** /* Includes ------------------------------------------------------------------*/ 20:Src/main.c **** #include "main.h" 21:Src/main.c **** #include "fatfs.h" 22:Src/main.c **** 23:Src/main.c **** /* Private includes ----------------------------------------------------------*/ 24:Src/main.c **** /* USER CODE BEGIN Includes */ 25:Src/main.c **** // #include "math.h" 26:Src/main.c **** #include "File_Handling.h" 27:Src/main.c **** #include 28:Src/main.c **** /* USER CODE END Includes */ 29:Src/main.c **** 30:Src/main.c **** /* Private typedef -----------------------------------------------------------*/ 31:Src/main.c **** /* USER CODE BEGIN PTD */ 32:Src/main.c **** 33:Src/main.c **** /* USER CODE END PTD */ 34:Src/main.c **** 35:Src/main.c **** /* Private define ------------------------------------------------------------*/ 36:Src/main.c **** /* USER CODE BEGIN PD */ 37:Src/main.c **** /* USER CODE END PD */ 38:Src/main.c **** 39:Src/main.c **** /* Private macro -------------------------------------------------------------*/ 40:Src/main.c **** /* USER CODE BEGIN PM */ 41:Src/main.c **** 42:Src/main.c **** /* USER CODE END PM */ 43:Src/main.c **** 44:Src/main.c **** /* Private variables ---------------------------------------------------------*/ 45:Src/main.c **** ADC_HandleTypeDef hadc1; 46:Src/main.c **** ADC_HandleTypeDef hadc3; 47:Src/main.c **** 48:Src/main.c **** SD_HandleTypeDef hsd1; 49:Src/main.c **** ARM GAS /tmp/ccdsDELB.s page 40 50:Src/main.c **** TIM_HandleTypeDef htim10; 51:Src/main.c **** 52:Src/main.c **** /* USER CODE BEGIN PV */ 53:Src/main.c **** uint32_t TO6, TO6_before, TO6_stop, TO6_uart, SD_SEEK, SD_SLIDE, temp32, TO7, TO7_before, TO7_PID, 54:Src/main.c **** uint8_t uart_buf, CPU_state, CPU_state_old, UART_transmission_request, State_Data[2], UART_DATA[DL_ 55:Src/main.c **** uint16_t UART_rec_incr, UART_header, CS_result, temp16, Long_Data[DL_16], COMMAND[CL_16];//, SD_mat 56:Src/main.c **** FRESULT fresult; // result 57:Src/main.c **** int test; 58:Src/main.c **** unsigned long fgoto, sizeoffile;//file pointer of the file object & size of file FPGA_RECEIVE_DATA_ 59:Src/main.c **** 60:Src/main.c **** LDx_SetupTypeDef LD1_curr_setup, LD2_curr_setup, LD1_def_setup, LD2_def_setup; 61:Src/main.c **** Work_SetupTypeDef Curr_setup, Def_setup; 62:Src/main.c **** LDx_ParamTypeDef LD1_param, LD2_param; 63:Src/main.c **** 64:Src/main.c **** task_t task; 65:Src/main.c **** 66:Src/main.c **** /* USER CODE END PV */ 67:Src/main.c **** 68:Src/main.c **** /* Private function prototypes -----------------------------------------------*/ 69:Src/main.c **** void SystemClock_Config(void); 70:Src/main.c **** static void MX_GPIO_Init(void); 71:Src/main.c **** static void MX_DMA_Init(void); 72:Src/main.c **** static void MX_SPI4_Init(void); 73:Src/main.c **** static void MX_TIM2_Init(void); 74:Src/main.c **** static void MX_TIM5_Init(void); 75:Src/main.c **** static void MX_ADC1_Init(void); 76:Src/main.c **** static void MX_ADC3_Init(void); 77:Src/main.c **** static void MX_SPI2_Init(void); 78:Src/main.c **** static void MX_SPI5_Init(void); 79:Src/main.c **** static void MX_SPI6_Init(void); 80:Src/main.c **** static void MX_USART1_UART_Init(void); 81:Src/main.c **** static void MX_SDMMC1_SD_Init(void); 82:Src/main.c **** static void MX_TIM7_Init(void); 83:Src/main.c **** static void MX_TIM6_Init(void); 84:Src/main.c **** static void MX_TIM10_Init(void); 85:Src/main.c **** /* USER CODE BEGIN PFP */ 86:Src/main.c **** static void Init_params(void); 87:Src/main.c **** static void Decode_uart(uint16_t *Command, LDx_SetupTypeDef *LD1_curr_setup, LDx_SetupTypeDef *LD2_ 88:Src/main.c **** static void Decode_task(uint16_t *Command, LDx_SetupTypeDef *LD1_curr_setup, LDx_SetupTypeDef *LD2_ 89:Src/main.c **** static void Set_LTEC(uint8_t num, uint16_t DATA); 90:Src/main.c **** static uint16_t MPhD_T(uint8_t num); 91:Src/main.c **** static uint16_t Get_ADC(uint8_t num); 92:Src/main.c **** static uint16_t PID_Controller_Temp(LDx_SetupTypeDef * LDx_curr_setup, LDx_ParamTypeDef * LDx_resul 93:Src/main.c **** uint8_t CheckChecksum(uint16_t *pbuff); 94:Src/main.c **** uint16_t CalculateChecksum(uint16_t *pbuff, uint16_t len); 95:Src/main.c **** //int SD_Init(void); 96:Src/main.c **** int SD_SAVE(uint16_t *pbuff); 97:Src/main.c **** //uint32_t Get_Length(void); 98:Src/main.c **** int SD_READ(uint16_t *pbuff); 99:Src/main.c **** int SD_REMOVE(void); 100:Src/main.c **** void USART_TX (uint8_t* dt, uint16_t sz); 101:Src/main.c **** void USART_TX_DMA (uint16_t sz); 102:Src/main.c **** static void Stop_TIM10(); 103:Src/main.c **** /* USER CODE END PFP */ 104:Src/main.c **** 105:Src/main.c **** /* Private user code ---------------------------------------------------------*/ 106:Src/main.c **** /* USER CODE BEGIN 0 */ ARM GAS /tmp/ccdsDELB.s page 41 107:Src/main.c **** 108:Src/main.c **** /* USER CODE END 0 */ 109:Src/main.c **** 110:Src/main.c **** /** 111:Src/main.c **** * @brief The application entry point. 112:Src/main.c **** * @retval int 113:Src/main.c **** */ 114:Src/main.c **** int main(void) 115:Src/main.c **** { 116:Src/main.c **** /* USER CODE BEGIN 1 */ 117:Src/main.c **** HAL_StatusTypeDef st; 118:Src/main.c **** /* USER CODE END 1 */ 119:Src/main.c **** 120:Src/main.c **** /* MCU Configuration--------------------------------------------------------*/ 121:Src/main.c **** 122:Src/main.c **** /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ 123:Src/main.c **** HAL_Init(); 124:Src/main.c **** 125:Src/main.c **** /* USER CODE BEGIN Init */ 126:Src/main.c **** /*I hope you don't forget that first - MX_DMA_Init(); and than - MX_USART1_UART_Init();*/ 127:Src/main.c **** /* USER CODE END Init */ 128:Src/main.c **** 129:Src/main.c **** /* Configure the system clock */ 130:Src/main.c **** SystemClock_Config(); 131:Src/main.c **** 132:Src/main.c **** /* USER CODE BEGIN SysInit */ 133:Src/main.c **** 134:Src/main.c **** /* USER CODE END SysInit */ 135:Src/main.c **** 136:Src/main.c **** /* Initialize all configured peripherals */ 137:Src/main.c **** MX_GPIO_Init(); 138:Src/main.c **** MX_DMA_Init(); 139:Src/main.c **** MX_SPI4_Init(); 140:Src/main.c **** MX_FATFS_Init(); 141:Src/main.c **** MX_TIM2_Init(); 142:Src/main.c **** MX_TIM5_Init(); 143:Src/main.c **** MX_ADC1_Init(); 144:Src/main.c **** MX_ADC3_Init(); 145:Src/main.c **** MX_SPI2_Init(); 146:Src/main.c **** MX_SPI5_Init(); 147:Src/main.c **** MX_SPI6_Init(); 148:Src/main.c **** MX_USART1_UART_Init(); 149:Src/main.c **** MX_SDMMC1_SD_Init(); 150:Src/main.c **** MX_TIM7_Init(); 151:Src/main.c **** MX_TIM6_Init(); 152:Src/main.c **** MX_TIM10_Init(); 153:Src/main.c **** /* USER CODE BEGIN 2 */ 154:Src/main.c **** Init_params(); 155:Src/main.c **** /* USER CODE END 2 */ 156:Src/main.c **** 157:Src/main.c **** /* Infinite loop */ 158:Src/main.c **** /* USER CODE BEGIN WHILE */ 159:Src/main.c **** while (1) 160:Src/main.c **** { 161:Src/main.c **** if ((HAL_GPIO_ReadPin(USB_FLAG_GPIO_Port, USB_FLAG_Pin)==GPIO_PIN_SET)&&(u_rx_flg == 0)) 162:Src/main.c **** { 163:Src/main.c **** //NVIC_DisableIRQ(USART1_IRQn); ARM GAS /tmp/ccdsDELB.s page 42 164:Src/main.c **** LL_USART_EnableIT_PE(USART1); 165:Src/main.c **** LL_USART_EnableIT_RXNE(USART1); 166:Src/main.c **** LL_USART_EnableIT_ERROR(USART1); 167:Src/main.c **** NVIC_SetPriority(USART1_IRQn, 0); 168:Src/main.c **** NVIC_EnableIRQ(USART1_IRQn);//In other case you have FE error flag... 169:Src/main.c **** u_rx_flg = 1; 170:Src/main.c **** } 171:Src/main.c **** // else 172:Src/main.c **** // { 173:Src/main.c **** // //NVIC_DisableIRQ(USART1_IRQn); 174:Src/main.c **** // u_rx_flg = 0; 175:Src/main.c **** // } 176:Src/main.c **** switch (CPU_state) 177:Src/main.c **** { 178:Src/main.c **** case HALT://0 - Default state 179:Src/main.c **** CPU_state_old = HALT;//Save main current cycle 180:Src/main.c **** task.current_param = task.min_param; 181:Src/main.c **** Stop_TIM10(); 182:Src/main.c **** break; 183:Src/main.c **** case DECODE_ENABLE://1 - Decode rec. message 184:Src/main.c **** CS_result = CalculateChecksum(COMMAND, CL_16-2); 185:Src/main.c **** if (CheckChecksum(COMMAND)) 186:Src/main.c **** { 187:Src/main.c **** LL_SPI_Enable(SPI2);//Enable SPI for Laser1 DAC & TEC1 188:Src/main.c **** LL_SPI_Enable(SPI6);//Enable SPI for Laser2 DAC & TEC2 189:Src/main.c **** Decode_uart(COMMAND, &LD1_curr_setup, &LD2_curr_setup, &Curr_setup); 190:Src/main.c **** TO6_before = TO6; 191:Src/main.c **** //LD1_param.LD_TEMP_Before = LD1_param.LD_TEMP; 192:Src/main.c **** //LD2_param.LD_TEMP_Before = LD2_param.LD_TEMP; 193:Src/main.c **** CPU_state = WORK_ENABLE; 194:Src/main.c **** CPU_state_old = WORK_ENABLE;//Save main current cycle 195:Src/main.c **** } 196:Src/main.c **** else 197:Src/main.c **** { 198:Src/main.c **** State_Data[0] |= UART_DECODE_ERR; 199:Src/main.c **** CPU_state = DEFAULT_ENABLE; 200:Src/main.c **** CPU_state_old = HALT;//Save main current cycle 201:Src/main.c **** } 202:Src/main.c **** UART_transmission_request = MESS_01; 203:Src/main.c **** break; 204:Src/main.c **** case DEFAULT_ENABLE://2 - Go to HALT 205:Src/main.c **** //Set current setup to default 206:Src/main.c **** task.current_param = task.min_param; 207:Src/main.c **** Stop_TIM10(); 208:Src/main.c **** Init_params(); 209:Src/main.c **** LL_SPI_Disable(SPI2);//Disable SPI for Laser1 DAC & TEC1 210:Src/main.c **** LL_SPI_Disable(SPI6);//Disable SPI for Laser2 DAC & TEC2 211:Src/main.c **** CPU_state = HALT; 212:Src/main.c **** CPU_state_old = HALT;//Save main current cycle 213:Src/main.c **** UART_transmission_request = MESS_01; 214:Src/main.c **** break; 215:Src/main.c **** case TRANS_S_ENABLE://3 - Transmith saved packet Before this operation must to be defaulting! 216:Src/main.c **** temp16 = SD_READ(&Long_Data[0]); 217:Src/main.c **** State_Data[0]|=temp16&0xff; 218:Src/main.c **** if (temp16==0) 219:Src/main.c **** { 220:Src/main.c **** UART_transmission_request = MESS_03; ARM GAS /tmp/ccdsDELB.s page 43 221:Src/main.c **** } 222:Src/main.c **** else 223:Src/main.c **** { 224:Src/main.c **** UART_transmission_request = MESS_01; 225:Src/main.c **** } 226:Src/main.c **** CPU_state_old = HALT; 227:Src/main.c **** CPU_state = CPU_state_old;//Return to main current cycle 228:Src/main.c **** break; 229:Src/main.c **** case TRANS_ENABLE://4 - Transmith current packet 230:Src/main.c **** UART_transmission_request = MESS_02; 231:Src/main.c **** CPU_state = CPU_state_old;//Return to main current cycle 232:Src/main.c **** break; 233:Src/main.c **** case REMOVE_FILE://5 - Remove file from SD 234:Src/main.c **** State_Data[0]|=SD_REMOVE()&0xff; 235:Src/main.c **** UART_transmission_request = MESS_01; 236:Src/main.c **** CPU_state = CPU_state_old; 237:Src/main.c **** break; 238:Src/main.c **** case STATE://6 - Transmith state message 239:Src/main.c **** UART_transmission_request = MESS_01; 240:Src/main.c **** CPU_state = CPU_state_old;//Return to main current cycle 241:Src/main.c **** break; 242:Src/main.c **** case WORK_ENABLE://7 - Main work cycle 243:Src/main.c **** task.current_param = task.min_param; 244:Src/main.c **** Stop_TIM10(); 245:Src/main.c **** if (TO7>TO7_before)//Main work cycle go with the timer 7 (1000 us or 1 kHz) 246:Src/main.c **** { 247:Src/main.c **** TO7_before = TO7; 248:Src/main.c **** LD1_param.POWER = MPhD_T(1);//Get Data from monitor photodiode of LD1 249:Src/main.c **** LD1_param.POWER = MPhD_T(1);//Get Data from monitor photodiode of LD1 250:Src/main.c **** LD2_param.POWER = MPhD_T(2);//Get Data from monitor photodiode of LD2 251:Src/main.c **** LD2_param.POWER = MPhD_T(2);//Get Data from monitor photodiode of LD2 252:Src/main.c **** 253:Src/main.c **** //Correct temperature in all pulses 254:Src/main.c **** (void) MPhD_T(3); 255:Src/main.c **** LD1_param.LD_CURR_TEMP = MPhD_T(3); 256:Src/main.c **** (void) MPhD_T(4); 257:Src/main.c **** LD2_param.LD_CURR_TEMP = MPhD_T(4); 258:Src/main.c **** temp16=PID_Controller_Temp(&LD1_curr_setup, &LD1_param, 1); 259:Src/main.c **** Set_LTEC(3, temp16);//Drive Laser TEC 1 260:Src/main.c **** temp16=PID_Controller_Temp(&LD2_curr_setup, &LD2_param, 2); 261:Src/main.c **** Set_LTEC(4, temp16);//Drive Laser TEC 2 262:Src/main.c **** 263:Src/main.c **** Long_Data[1] = LD1_param.POWER;//Translate Data from monitor photodiode of LD1 to Long_Data 264:Src/main.c **** Long_Data[2] = LD2_param.POWER;//Translate Data from monitor photodiode of LD2 to Long_Data 265:Src/main.c **** 266:Src/main.c **** Set_LTEC(1,LD1_curr_setup.CURRENT);//Drive Laser diode 1 267:Src/main.c **** Set_LTEC(2,LD2_curr_setup.CURRENT);//Drive Laser diode 2 268:Src/main.c **** 269:Src/main.c **** //Prepare DATA of internals ADCs 270:Src/main.c **** //Put the temperature of LD2 to Long_Data: 271:Src/main.c **** temp16 = Get_ADC(0); 272:Src/main.c **** temp16 = Get_ADC(1); 273:Src/main.c **** Long_Data[7] = temp16; 274:Src/main.c **** 275:Src/main.c **** //Put the temperature of LD2 to Long_Data: 276:Src/main.c **** temp16 = Get_ADC(1); 277:Src/main.c **** Long_Data[8] = temp16; ARM GAS /tmp/ccdsDELB.s page 44 278:Src/main.c **** 279:Src/main.c **** //Put the temperature of LD2 to Long_Data: 280:Src/main.c **** temp16 = Get_ADC(1); 281:Src/main.c **** Long_Data[9] = temp16; 282:Src/main.c **** 283:Src/main.c **** //Put the temperature of LD2 to Long_Data: 284:Src/main.c **** temp16 = Get_ADC(1); 285:Src/main.c **** Long_Data[10] = temp16; 286:Src/main.c **** 287:Src/main.c **** //Put the temperature of LD2 to Long_Data: 288:Src/main.c **** temp16 = Get_ADC(1); 289:Src/main.c **** Long_Data[11] = temp16; 290:Src/main.c **** temp16 = Get_ADC(2); 291:Src/main.c **** 292:Src/main.c **** //Put the temperature of LD2 to Long_Data: 293:Src/main.c **** temp16 = Get_ADC(3); 294:Src/main.c **** temp16 = Get_ADC(4); 295:Src/main.c **** Long_Data[12] = temp16; 296:Src/main.c **** temp16 = Get_ADC(5); 297:Src/main.c **** 298:Src/main.c **** //Put the timer tick to Long_Data: 299:Src/main.c **** TO6_stop = TO6; 300:Src/main.c **** Long_Data[3] = (TO6_stop)&0xffff; 301:Src/main.c **** Long_Data[4] = (TO6_stop>>16)&0xffff; 302:Src/main.c **** 303:Src/main.c **** //Put the average temperature of LD1 to Long_Data: 304:Src/main.c **** Long_Data[5] = LD1_param.LD_CURR_TEMP; 305:Src/main.c **** 306:Src/main.c **** //Put the average temperature of LD2 to Long_Data: 307:Src/main.c **** Long_Data[6] = LD2_param.LD_CURR_TEMP; 308:Src/main.c **** 309:Src/main.c **** if (Curr_setup.SD_EN==1) 310:Src/main.c **** { 311:Src/main.c **** CS_result = CalculateChecksum(&Long_Data[1], DL_16-2); 312:Src/main.c **** Long_Data[DL_16-1] = CS_result; 313:Src/main.c **** temp16 = SD_SAVE(&Long_Data[0]); 314:Src/main.c **** State_Data[0]|=temp16&0xff; 315:Src/main.c **** } 316:Src/main.c **** CPU_state_old = WORK_ENABLE;//Save main current cycle 317:Src/main.c **** } 318:Src/main.c **** break; 319:Src/main.c **** case DECODE_TASK: 320:Src/main.c **** if (CheckChecksum(COMMAND)) 321:Src/main.c **** { 322:Src/main.c **** Decode_task(COMMAND, &LD1_curr_setup, &LD2_curr_setup, &Curr_setup); 323:Src/main.c **** TO6_before = TO6; 324:Src/main.c **** CPU_state = RUN_TASK; 325:Src/main.c **** CPU_state_old = RUN_TASK;//Save main current cycle 326:Src/main.c **** } 327:Src/main.c **** else 328:Src/main.c **** { 329:Src/main.c **** State_Data[0] |= UART_DECODE_ERR; 330:Src/main.c **** CPU_state = DEFAULT_ENABLE; 331:Src/main.c **** CPU_state_old = HALT;//Save main current cycle 332:Src/main.c **** } 333:Src/main.c **** UART_transmission_request = MESS_01; 334:Src/main.c **** break; ARM GAS /tmp/ccdsDELB.s page 45 335:Src/main.c **** case RUN_TASK: 336:Src/main.c **** switch (task.task_type) 337:Src/main.c **** { 338:Src/main.c **** case TT_CHANGE_CURR_1: 339:Src/main.c **** Set_LTEC(TT_CHANGE_CURR_2, task.curr); 340:Src/main.c **** (void) MPhD_T(TT_CHANGE_TEMP_1); 341:Src/main.c **** LD1_param.LD_CURR_TEMP = MPhD_T(TT_CHANGE_TEMP_1); 342:Src/main.c **** (void) MPhD_T(TT_CHANGE_TEMP_2); 343:Src/main.c **** LD2_param.LD_CURR_TEMP = MPhD_T(TT_CHANGE_TEMP_2); 344:Src/main.c **** temp16=PID_Controller_Temp(&LD1_curr_setup, &LD1_param, 1); 345:Src/main.c **** Set_LTEC(TT_CHANGE_TEMP_1, temp16);//Drive Laser TEC 1 346:Src/main.c **** temp16=PID_Controller_Temp(&LD2_curr_setup, &LD2_param, 2); 347:Src/main.c **** Set_LTEC(TT_CHANGE_TEMP_2, temp16);//Drive Laser TEC 2 348:Src/main.c **** 349:Src/main.c **** // Toggle pin for oscilloscope 350:Src/main.c **** HAL_GPIO_WritePin(GPIOD, GPIO_PIN_7, GPIO_PIN_SET); 351:Src/main.c **** HAL_GPIO_WritePin(GPIOD, GPIO_PIN_7, GPIO_PIN_RESET); 352:Src/main.c **** 353:Src/main.c **** st = HAL_TIM_Base_Start_IT(&htim10); 354:Src/main.c **** if (st != HAL_OK) 355:Src/main.c **** while(1); 356:Src/main.c **** while (task.current_param < task.max_param) 357:Src/main.c **** { 358:Src/main.c **** if (TIM10_coflag) 359:Src/main.c **** { 360:Src/main.c **** Set_LTEC(TT_CHANGE_CURR_1, task.current_param); 361:Src/main.c **** task.current_param += task.delta_param; 362:Src/main.c **** TO10 = 0; 363:Src/main.c **** TIM10_coflag = 0; 364:Src/main.c **** } 365:Src/main.c **** } 366:Src/main.c **** Stop_TIM10(); 367:Src/main.c **** task.current_param = task.min_param; 368:Src/main.c **** Set_LTEC(TT_CHANGE_CURR_1, task.current_param); 369:Src/main.c **** if (task.tau > 3) 370:Src/main.c **** { 371:Src/main.c **** TIM10_period = htim10.Init.Period; 372:Src/main.c **** htim10.Init.Period = 9999; 373:Src/main.c **** TO10_counter = (task.tau - 1) * 100; 374:Src/main.c **** } 375:Src/main.c **** HAL_TIM_Base_Start_IT(&htim10); 376:Src/main.c **** break; 377:Src/main.c **** case TT_CHANGE_CURR_2: 378:Src/main.c **** Set_LTEC(TT_CHANGE_CURR_1, task.curr); 379:Src/main.c **** (void) MPhD_T(TT_CHANGE_TEMP_1); 380:Src/main.c **** LD1_param.LD_CURR_TEMP = MPhD_T(TT_CHANGE_TEMP_1); 381:Src/main.c **** (void) MPhD_T(TT_CHANGE_TEMP_2); 382:Src/main.c **** LD2_param.LD_CURR_TEMP = MPhD_T(TT_CHANGE_TEMP_2); 383:Src/main.c **** temp16=PID_Controller_Temp(&LD1_curr_setup, &LD1_param, 1); 384:Src/main.c **** Set_LTEC(TT_CHANGE_TEMP_1, temp16);//Drive Laser TEC 1 385:Src/main.c **** temp16=PID_Controller_Temp(&LD2_curr_setup, &LD2_param, 2); 386:Src/main.c **** Set_LTEC(TT_CHANGE_TEMP_2, temp16);//Drive Laser TEC 2 387:Src/main.c **** 388:Src/main.c **** // Toggle pin for oscilloscope 389:Src/main.c **** HAL_GPIO_WritePin(GPIOD, GPIO_PIN_7, GPIO_PIN_SET); 390:Src/main.c **** HAL_GPIO_WritePin(GPIOD, GPIO_PIN_7, GPIO_PIN_RESET); 391:Src/main.c **** ARM GAS /tmp/ccdsDELB.s page 46 392:Src/main.c **** st = HAL_TIM_Base_Start_IT(&htim10); 393:Src/main.c **** if (st != HAL_OK) 394:Src/main.c **** while(1); 395:Src/main.c **** while (task.current_param < task.max_param) 396:Src/main.c **** { 397:Src/main.c **** if (TIM10_coflag) 398:Src/main.c **** { 399:Src/main.c **** Set_LTEC(TT_CHANGE_CURR_2, task.current_param); 400:Src/main.c **** task.current_param += task.delta_param; 401:Src/main.c **** TO10 = 0; 402:Src/main.c **** TIM10_coflag = 0; 403:Src/main.c **** } 404:Src/main.c **** } 405:Src/main.c **** Stop_TIM10(); 406:Src/main.c **** task.current_param = task.min_param; 407:Src/main.c **** Set_LTEC(TT_CHANGE_CURR_2, task.current_param); 408:Src/main.c **** if (task.tau > 3) 409:Src/main.c **** { 410:Src/main.c **** TIM10_period = htim10.Init.Period; 411:Src/main.c **** htim10.Init.Period = 9999; 412:Src/main.c **** TO10_counter = (task.tau - 1) * 100; 413:Src/main.c **** } 414:Src/main.c **** HAL_TIM_Base_Start_IT(&htim10); 415:Src/main.c **** break; 416:Src/main.c **** case TT_CHANGE_TEMP_1: 417:Src/main.c **** // isn't implemented 418:Src/main.c **** break; 419:Src/main.c **** case TT_CHANGE_TEMP_2: 420:Src/main.c **** // isn't implemented 421:Src/main.c **** break; 422:Src/main.c **** } 423:Src/main.c **** 424:Src/main.c **** if (TO7>TO7_before) 425:Src/main.c **** { 426:Src/main.c **** TO7_before = TO7; 427:Src/main.c **** 428:Src/main.c **** LD1_param.POWER = MPhD_T(1);//Get Data from monitor photodiode of LD1 429:Src/main.c **** LD1_param.POWER = MPhD_T(1);//Get Data from monitor photodiode of LD1 430:Src/main.c **** LD2_param.POWER = MPhD_T(2);//Get Data from monitor photodiode of LD2 431:Src/main.c **** LD2_param.POWER = MPhD_T(2);//Get Data from monitor photodiode of LD2 432:Src/main.c **** 433:Src/main.c **** Long_Data[1] = LD1_param.POWER;//Translate Data from monitor photodiode of LD1 to Long_Data 434:Src/main.c **** Long_Data[2] = LD2_param.POWER;//Translate Data from monitor photodiode of LD2 to Long_Data 435:Src/main.c **** 436:Src/main.c **** //Prepare DATA of internals ADCs 437:Src/main.c **** //Put the temperature of LD2 to Long_Data: 438:Src/main.c **** temp16 = Get_ADC(0); 439:Src/main.c **** temp16 = Get_ADC(1); 440:Src/main.c **** Long_Data[7] = temp16; 441:Src/main.c **** 442:Src/main.c **** //Put the temperature of LD2 to Long_Data: 443:Src/main.c **** temp16 = Get_ADC(1); 444:Src/main.c **** Long_Data[8] = temp16; 445:Src/main.c **** 446:Src/main.c **** //Put the temperature of LD2 to Long_Data: 447:Src/main.c **** temp16 = Get_ADC(1); 448:Src/main.c **** Long_Data[9] = temp16; ARM GAS /tmp/ccdsDELB.s page 47 449:Src/main.c **** 450:Src/main.c **** //Put the temperature of LD2 to Long_Data: 451:Src/main.c **** temp16 = Get_ADC(1); 452:Src/main.c **** Long_Data[10] = temp16; 453:Src/main.c **** 454:Src/main.c **** //Put the temperature of LD2 to Long_Data: 455:Src/main.c **** temp16 = Get_ADC(1); 456:Src/main.c **** Long_Data[11] = temp16; 457:Src/main.c **** temp16 = Get_ADC(2); 458:Src/main.c **** 459:Src/main.c **** //Put the temperature of LD2 to Long_Data: 460:Src/main.c **** temp16 = Get_ADC(3); 461:Src/main.c **** temp16 = Get_ADC(4); 462:Src/main.c **** Long_Data[12] = temp16; 463:Src/main.c **** temp16 = Get_ADC(5); 464:Src/main.c **** 465:Src/main.c **** //Put the timer tick to Long_Data: 466:Src/main.c **** TO6_stop = TO6; 467:Src/main.c **** Long_Data[3] = (TO6_stop)&0xffff; 468:Src/main.c **** Long_Data[4] = (TO6_stop>>16)&0xffff; 469:Src/main.c **** 470:Src/main.c **** //Put the average temperature of LD1 to Long_Data: 471:Src/main.c **** Long_Data[5] = LD1_param.LD_CURR_TEMP; 472:Src/main.c **** 473:Src/main.c **** //Put the average temperature of LD2 to Long_Data: 474:Src/main.c **** Long_Data[6] = LD2_param.LD_CURR_TEMP; 475:Src/main.c **** } 476:Src/main.c **** while (!TIM10_coflag); 477:Src/main.c **** 478:Src/main.c **** Stop_TIM10(); 479:Src/main.c **** 480:Src/main.c **** if (task.tau > 3) 481:Src/main.c **** { 482:Src/main.c **** htim10.Init.Period = TIM10_period; 483:Src/main.c **** TO10_counter = task.dt / 10 - 1; 484:Src/main.c **** } 485:Src/main.c **** 486:Src/main.c **** CPU_state_old = RUN_TASK; 487:Src/main.c **** break; 488:Src/main.c **** } 489:Src/main.c **** 490:Src/main.c **** switch (UART_transmission_request) 491:Src/main.c **** { 492:Src/main.c **** case MESS_01://Default state 493:Src/main.c **** USART_TX(State_Data,2); 494:Src/main.c **** //HAL_UART_Transmit(&huart1, State_Data, 2, 10); 495:Src/main.c **** State_Data[0]=0; 496:Src/main.c **** State_Data[1]=0;//All OK! 497:Src/main.c **** UART_transmission_request = NO_MESS; 498:Src/main.c **** break; 499:Src/main.c **** case MESS_02://Transmith packet 500:Src/main.c **** 501:Src/main.c **** //Find CS and put to Long_Data: 502:Src/main.c **** CS_result = CalculateChecksum(&Long_Data[1], DL_16-2); 503:Src/main.c **** Long_Data[DL_16-1] = CS_result; 504:Src/main.c **** 505:Src/main.c **** for (uint16_t i = 0; i < DL_16; i++) ARM GAS /tmp/ccdsDELB.s page 48 506:Src/main.c **** { 507:Src/main.c **** UART_DATA[i*2] = (Long_Data[i])&0xff; 508:Src/main.c **** UART_DATA[i*2+1] = (Long_Data[i]>>8)&0xff; 509:Src/main.c **** } 510:Src/main.c **** //HAL_NVIC_SetPriority(DMA2_Stream7_IRQn, 0, 0); 511:Src/main.c **** //HAL_NVIC_EnableIRQ(DMA2_Stream7_IRQn); 512:Src/main.c **** //HAL_UART_Transmit_DMA(&huart1, UART_DATA, DL_8); 513:Src/main.c **** //huart1.gState = HAL_UART_STATE_READY; 514:Src/main.c **** //hdma_usart1_tx.State=HAL_DMA_STATE_BUSY; 515:Src/main.c **** USART_TX_DMA (DL_8);//Send data by USART using DMA 516:Src/main.c **** UART_transmission_request = NO_MESS; 517:Src/main.c **** break; 518:Src/main.c **** case MESS_03://Transmith saved packet 519:Src/main.c **** for (uint16_t i = 0; i < DL_16; i++) 520:Src/main.c **** { 521:Src/main.c **** UART_DATA[i*2] = (Long_Data[i])&0xff; 522:Src/main.c **** UART_DATA[i*2+1] = (Long_Data[i]>>8)&0xff; 523:Src/main.c **** } 524:Src/main.c **** //HAL_NVIC_EnableIRQ(DMA2_Stream7_IRQn); 525:Src/main.c **** //HAL_UART_Transmit_DMA(&huart1, UART_DATA, DL_8); 526:Src/main.c **** //huart1.gState = HAL_UART_STATE_READY; 527:Src/main.c **** //hdma_usart1_tx.State=HAL_DMA_STATE_BUSY; 528:Src/main.c **** USART_TX_DMA (DL_8);//Send data by USART using DMA 529:Src/main.c **** UART_transmission_request = NO_MESS; 530:Src/main.c **** break; 531:Src/main.c **** } 532:Src/main.c **** if ((flg_tmt==1)&&((TO6-TO6_uart)>100))//Uart timeout handle. if timeout beetween zero byte of 533:Src/main.c **** { 534:Src/main.c **** UART_rec_incr = 0;//Reset uart command counter 535:Src/main.c **** State_Data[0] |= UART_ERR;//timeout error! 536:Src/main.c **** UART_transmission_request = MESS_01;//Send status 537:Src/main.c **** flg_tmt = 0;//Reset timeout flag 538:Src/main.c **** } 539:Src/main.c **** /* USER CODE END WHILE */ 540:Src/main.c **** 541:Src/main.c **** /* USER CODE BEGIN 3 */ 542:Src/main.c **** } 543:Src/main.c **** /* USER CODE END 3 */ 544:Src/main.c **** } 545:Src/main.c **** 546:Src/main.c **** /** 547:Src/main.c **** * @brief System Clock Configuration 548:Src/main.c **** * @retval None 549:Src/main.c **** */ 550:Src/main.c **** void SystemClock_Config(void) 551:Src/main.c **** { 552:Src/main.c **** RCC_OscInitTypeDef RCC_OscInitStruct = {0}; 553:Src/main.c **** RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; 554:Src/main.c **** 555:Src/main.c **** /** Configure the main internal regulator output voltage 556:Src/main.c **** */ 557:Src/main.c **** __HAL_RCC_PWR_CLK_ENABLE(); 558:Src/main.c **** __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); 559:Src/main.c **** 560:Src/main.c **** /** Initializes the RCC Oscillators according to the specified parameters 561:Src/main.c **** * in the RCC_OscInitTypeDef structure. 562:Src/main.c **** */ ARM GAS /tmp/ccdsDELB.s page 49 563:Src/main.c **** RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; 564:Src/main.c **** RCC_OscInitStruct.HSEState = RCC_HSE_ON; 565:Src/main.c **** RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; 566:Src/main.c **** RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; 567:Src/main.c **** RCC_OscInitStruct.PLL.PLLM = 25; 568:Src/main.c **** RCC_OscInitStruct.PLL.PLLN = 368; 569:Src/main.c **** RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; 570:Src/main.c **** RCC_OscInitStruct.PLL.PLLQ = 8; 571:Src/main.c **** RCC_OscInitStruct.PLL.PLLR = 2; 572:Src/main.c **** if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) 573:Src/main.c **** { 574:Src/main.c **** Error_Handler(); 575:Src/main.c **** } 576:Src/main.c **** 577:Src/main.c **** /** Activate the Over-Drive mode 578:Src/main.c **** */ 579:Src/main.c **** if (HAL_PWREx_EnableOverDrive() != HAL_OK) 580:Src/main.c **** { 581:Src/main.c **** Error_Handler(); 582:Src/main.c **** } 583:Src/main.c **** 584:Src/main.c **** /** Initializes the CPU, AHB and APB buses clocks 585:Src/main.c **** */ 586:Src/main.c **** RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK 587:Src/main.c **** |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; 588:Src/main.c **** RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; 589:Src/main.c **** RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; 590:Src/main.c **** RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4; 591:Src/main.c **** RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; 592:Src/main.c **** 593:Src/main.c **** if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_6) != HAL_OK) 594:Src/main.c **** { 595:Src/main.c **** Error_Handler(); 596:Src/main.c **** } 597:Src/main.c **** } 598:Src/main.c **** 599:Src/main.c **** /** 600:Src/main.c **** * @brief ADC1 Initialization Function 601:Src/main.c **** * @param None 602:Src/main.c **** * @retval None 603:Src/main.c **** */ 604:Src/main.c **** static void MX_ADC1_Init(void) 605:Src/main.c **** { 606:Src/main.c **** 607:Src/main.c **** /* USER CODE BEGIN ADC1_Init 0 */ 608:Src/main.c **** 609:Src/main.c **** /* USER CODE END ADC1_Init 0 */ 610:Src/main.c **** 611:Src/main.c **** ADC_ChannelConfTypeDef sConfig = {0}; 612:Src/main.c **** 613:Src/main.c **** /* USER CODE BEGIN ADC1_Init 1 */ 614:Src/main.c **** 615:Src/main.c **** /* USER CODE END ADC1_Init 1 */ 616:Src/main.c **** 617:Src/main.c **** /** Configure the global features of the ADC (Clock, Resolution, Data Alignment and number of con 618:Src/main.c **** */ 619:Src/main.c **** hadc1.Instance = ADC1; ARM GAS /tmp/ccdsDELB.s page 50 620:Src/main.c **** hadc1.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV8; 621:Src/main.c **** hadc1.Init.Resolution = ADC_RESOLUTION_12B; 622:Src/main.c **** hadc1.Init.ScanConvMode = ADC_SCAN_ENABLE; 623:Src/main.c **** hadc1.Init.ContinuousConvMode = DISABLE; 624:Src/main.c **** hadc1.Init.DiscontinuousConvMode = DISABLE; 625:Src/main.c **** hadc1.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE; 626:Src/main.c **** hadc1.Init.ExternalTrigConv = ADC_SOFTWARE_START; 627:Src/main.c **** hadc1.Init.DataAlign = ADC_DATAALIGN_RIGHT; 628:Src/main.c **** hadc1.Init.NbrOfConversion = 5; 629:Src/main.c **** hadc1.Init.DMAContinuousRequests = DISABLE; 630:Src/main.c **** hadc1.Init.EOCSelection = ADC_EOC_SINGLE_CONV; 631:Src/main.c **** if (HAL_ADC_Init(&hadc1) != HAL_OK) 632:Src/main.c **** { 633:Src/main.c **** Error_Handler(); 634:Src/main.c **** } 635:Src/main.c **** 636:Src/main.c **** /** Configure for the selected ADC regular channel its corresponding rank in the sequencer and it 637:Src/main.c **** */ 638:Src/main.c **** sConfig.Channel = ADC_CHANNEL_9; 639:Src/main.c **** sConfig.Rank = ADC_REGULAR_RANK_1; 640:Src/main.c **** sConfig.SamplingTime = ADC_SAMPLETIME_480CYCLES; 641:Src/main.c **** if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 642:Src/main.c **** { 643:Src/main.c **** Error_Handler(); 644:Src/main.c **** } 645:Src/main.c **** 646:Src/main.c **** /** Configure for the selected ADC regular channel its corresponding rank in the sequencer and it 647:Src/main.c **** */ 648:Src/main.c **** sConfig.Channel = ADC_CHANNEL_8; 649:Src/main.c **** sConfig.Rank = ADC_REGULAR_RANK_2; 650:Src/main.c **** if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 651:Src/main.c **** { 652:Src/main.c **** Error_Handler(); 653:Src/main.c **** } 654:Src/main.c **** 655:Src/main.c **** /** Configure for the selected ADC regular channel its corresponding rank in the sequencer and it 656:Src/main.c **** */ 657:Src/main.c **** sConfig.Channel = ADC_CHANNEL_2; 658:Src/main.c **** sConfig.Rank = ADC_REGULAR_RANK_3; 659:Src/main.c **** if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 660:Src/main.c **** { 661:Src/main.c **** Error_Handler(); 662:Src/main.c **** } 663:Src/main.c **** 664:Src/main.c **** /** Configure for the selected ADC regular channel its corresponding rank in the sequencer and it 665:Src/main.c **** */ 666:Src/main.c **** sConfig.Channel = ADC_CHANNEL_10; 667:Src/main.c **** sConfig.Rank = ADC_REGULAR_RANK_4; 668:Src/main.c **** if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 669:Src/main.c **** { 670:Src/main.c **** Error_Handler(); 671:Src/main.c **** } 672:Src/main.c **** 673:Src/main.c **** /** Configure for the selected ADC regular channel its corresponding rank in the sequencer and it 674:Src/main.c **** */ 675:Src/main.c **** sConfig.Channel = ADC_CHANNEL_11; 676:Src/main.c **** sConfig.Rank = ADC_REGULAR_RANK_5; ARM GAS /tmp/ccdsDELB.s page 51 677:Src/main.c **** if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 678:Src/main.c **** { 679:Src/main.c **** Error_Handler(); 680:Src/main.c **** } 681:Src/main.c **** /* USER CODE BEGIN ADC1_Init 2 */ 682:Src/main.c **** 683:Src/main.c **** /* USER CODE END ADC1_Init 2 */ 684:Src/main.c **** 685:Src/main.c **** } 686:Src/main.c **** 687:Src/main.c **** /** 688:Src/main.c **** * @brief ADC3 Initialization Function 689:Src/main.c **** * @param None 690:Src/main.c **** * @retval None 691:Src/main.c **** */ 692:Src/main.c **** static void MX_ADC3_Init(void) 693:Src/main.c **** { 694:Src/main.c **** 695:Src/main.c **** /* USER CODE BEGIN ADC3_Init 0 */ 696:Src/main.c **** 697:Src/main.c **** /* USER CODE END ADC3_Init 0 */ 698:Src/main.c **** 699:Src/main.c **** ADC_ChannelConfTypeDef sConfig = {0}; 700:Src/main.c **** 701:Src/main.c **** /* USER CODE BEGIN ADC3_Init 1 */ 702:Src/main.c **** 703:Src/main.c **** /* USER CODE END ADC3_Init 1 */ 704:Src/main.c **** 705:Src/main.c **** /** Configure the global features of the ADC (Clock, Resolution, Data Alignment and number of con 706:Src/main.c **** */ 707:Src/main.c **** hadc3.Instance = ADC3; 708:Src/main.c **** hadc3.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV8; 709:Src/main.c **** hadc3.Init.Resolution = ADC_RESOLUTION_12B; 710:Src/main.c **** hadc3.Init.ScanConvMode = ADC_SCAN_DISABLE; 711:Src/main.c **** hadc3.Init.ContinuousConvMode = DISABLE; 712:Src/main.c **** hadc3.Init.DiscontinuousConvMode = DISABLE; 713:Src/main.c **** hadc3.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE; 714:Src/main.c **** hadc3.Init.ExternalTrigConv = ADC_SOFTWARE_START; 715:Src/main.c **** hadc3.Init.DataAlign = ADC_DATAALIGN_RIGHT; 716:Src/main.c **** hadc3.Init.NbrOfConversion = 1; 717:Src/main.c **** hadc3.Init.DMAContinuousRequests = DISABLE; 718:Src/main.c **** hadc3.Init.EOCSelection = ADC_EOC_SINGLE_CONV; 719:Src/main.c **** if (HAL_ADC_Init(&hadc3) != HAL_OK) 720:Src/main.c **** { 721:Src/main.c **** Error_Handler(); 722:Src/main.c **** } 723:Src/main.c **** 724:Src/main.c **** /** Configure for the selected ADC regular channel its corresponding rank in the sequencer and it 725:Src/main.c **** */ 726:Src/main.c **** sConfig.Channel = ADC_CHANNEL_15; 727:Src/main.c **** sConfig.Rank = ADC_REGULAR_RANK_1; 728:Src/main.c **** sConfig.SamplingTime = ADC_SAMPLETIME_480CYCLES; 729:Src/main.c **** if (HAL_ADC_ConfigChannel(&hadc3, &sConfig) != HAL_OK) 730:Src/main.c **** { 731:Src/main.c **** Error_Handler(); 732:Src/main.c **** } 733:Src/main.c **** /* USER CODE BEGIN ADC3_Init 2 */ ARM GAS /tmp/ccdsDELB.s page 52 734:Src/main.c **** 735:Src/main.c **** /* USER CODE END ADC3_Init 2 */ 736:Src/main.c **** 737:Src/main.c **** } 738:Src/main.c **** 739:Src/main.c **** /** 740:Src/main.c **** * @brief SDMMC1 Initialization Function 741:Src/main.c **** * @param None 742:Src/main.c **** * @retval None 743:Src/main.c **** */ 744:Src/main.c **** static void MX_SDMMC1_SD_Init(void) 745:Src/main.c **** { 93 .loc 2 745 1 is_stmt 1 view -0 94 .cfi_startproc 95 @ args = 0, pretend = 0, frame = 0 96 @ frame_needed = 0, uses_anonymous_args = 0 97 @ link register save eliminated. 746:Src/main.c **** 747:Src/main.c **** /* USER CODE BEGIN SDMMC1_Init 0 */ 748:Src/main.c **** 749:Src/main.c **** /* USER CODE END SDMMC1_Init 0 */ 750:Src/main.c **** 751:Src/main.c **** /* USER CODE BEGIN SDMMC1_Init 1 */ 752:Src/main.c **** 753:Src/main.c **** /* USER CODE END SDMMC1_Init 1 */ 754:Src/main.c **** hsd1.Instance = SDMMC1; 98 .loc 2 754 3 view .LVU21 99 .loc 2 754 17 is_stmt 0 view .LVU22 100 0000 064B ldr r3, .L5 101 0002 074A ldr r2, .L5+4 102 0004 1A60 str r2, [r3] 755:Src/main.c **** hsd1.Init.ClockEdge = SDMMC_CLOCK_EDGE_RISING; 103 .loc 2 755 3 is_stmt 1 view .LVU23 104 .loc 2 755 23 is_stmt 0 view .LVU24 105 0006 0022 movs r2, #0 106 0008 5A60 str r2, [r3, #4] 756:Src/main.c **** hsd1.Init.ClockBypass = SDMMC_CLOCK_BYPASS_DISABLE; 107 .loc 2 756 3 is_stmt 1 view .LVU25 108 .loc 2 756 25 is_stmt 0 view .LVU26 109 000a 9A60 str r2, [r3, #8] 757:Src/main.c **** hsd1.Init.ClockPowerSave = SDMMC_CLOCK_POWER_SAVE_DISABLE; 110 .loc 2 757 3 is_stmt 1 view .LVU27 111 .loc 2 757 28 is_stmt 0 view .LVU28 112 000c DA60 str r2, [r3, #12] 758:Src/main.c **** hsd1.Init.BusWide = SDMMC_BUS_WIDE_4B; 113 .loc 2 758 3 is_stmt 1 view .LVU29 114 .loc 2 758 21 is_stmt 0 view .LVU30 115 000e 4FF40061 mov r1, #2048 116 0012 1961 str r1, [r3, #16] 759:Src/main.c **** hsd1.Init.HardwareFlowControl = SDMMC_HARDWARE_FLOW_CONTROL_DISABLE; 117 .loc 2 759 3 is_stmt 1 view .LVU31 118 .loc 2 759 33 is_stmt 0 view .LVU32 119 0014 5A61 str r2, [r3, #20] 760:Src/main.c **** hsd1.Init.ClockDiv = 20; 120 .loc 2 760 3 is_stmt 1 view .LVU33 121 .loc 2 760 22 is_stmt 0 view .LVU34 122 0016 1422 movs r2, #20 ARM GAS /tmp/ccdsDELB.s page 53 123 0018 9A61 str r2, [r3, #24] 761:Src/main.c **** /* USER CODE BEGIN SDMMC1_Init 2 */ 762:Src/main.c **** 763:Src/main.c **** /* USER CODE END SDMMC1_Init 2 */ 764:Src/main.c **** 765:Src/main.c **** } 124 .loc 2 765 1 view .LVU35 125 001a 7047 bx lr 126 .L6: 127 .align 2 128 .L5: 129 001c 00000000 .word .LANCHOR0 130 0020 002C0140 .word 1073818624 131 .cfi_endproc 132 .LFE1190: 134 .section .text.MX_DMA_Init,"ax",%progbits 135 .align 1 136 .syntax unified 137 .thumb 138 .thumb_func 139 .fpu fpv5-d16 141 MX_DMA_Init: 142 .LFB1201: 766:Src/main.c **** 767:Src/main.c **** /** 768:Src/main.c **** * @brief SPI2 Initialization Function 769:Src/main.c **** * @param None 770:Src/main.c **** * @retval None 771:Src/main.c **** */ 772:Src/main.c **** static void MX_SPI2_Init(void) 773:Src/main.c **** { 774:Src/main.c **** 775:Src/main.c **** /* USER CODE BEGIN SPI2_Init 0 */ 776:Src/main.c **** 777:Src/main.c **** /* USER CODE END SPI2_Init 0 */ 778:Src/main.c **** 779:Src/main.c **** LL_SPI_InitTypeDef SPI_InitStruct = {0}; 780:Src/main.c **** 781:Src/main.c **** LL_GPIO_InitTypeDef GPIO_InitStruct = {0}; 782:Src/main.c **** 783:Src/main.c **** /* Peripheral clock enable */ 784:Src/main.c **** LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_SPI2); 785:Src/main.c **** 786:Src/main.c **** LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_GPIOB); 787:Src/main.c **** /**SPI2 GPIO Configuration 788:Src/main.c **** PB13 ------> SPI2_SCK 789:Src/main.c **** PB15 ------> SPI2_MOSI 790:Src/main.c **** */ 791:Src/main.c **** GPIO_InitStruct.Pin = LL_GPIO_PIN_13; 792:Src/main.c **** GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE; 793:Src/main.c **** GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH; 794:Src/main.c **** GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; 795:Src/main.c **** GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; 796:Src/main.c **** GPIO_InitStruct.Alternate = LL_GPIO_AF_5; 797:Src/main.c **** LL_GPIO_Init(GPIOB, &GPIO_InitStruct); 798:Src/main.c **** 799:Src/main.c **** GPIO_InitStruct.Pin = LL_GPIO_PIN_15; ARM GAS /tmp/ccdsDELB.s page 54 800:Src/main.c **** GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE; 801:Src/main.c **** GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH; 802:Src/main.c **** GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; 803:Src/main.c **** GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; 804:Src/main.c **** GPIO_InitStruct.Alternate = LL_GPIO_AF_5; 805:Src/main.c **** LL_GPIO_Init(GPIOB, &GPIO_InitStruct); 806:Src/main.c **** 807:Src/main.c **** /* USER CODE BEGIN SPI2_Init 1 */ 808:Src/main.c **** 809:Src/main.c **** /* USER CODE END SPI2_Init 1 */ 810:Src/main.c **** /* SPI2 parameter configuration*/ 811:Src/main.c **** SPI_InitStruct.TransferDirection = LL_SPI_FULL_DUPLEX; 812:Src/main.c **** SPI_InitStruct.Mode = LL_SPI_MODE_MASTER; 813:Src/main.c **** SPI_InitStruct.DataWidth = LL_SPI_DATAWIDTH_16BIT; 814:Src/main.c **** SPI_InitStruct.ClockPolarity = LL_SPI_POLARITY_HIGH; 815:Src/main.c **** SPI_InitStruct.ClockPhase = LL_SPI_PHASE_2EDGE; 816:Src/main.c **** SPI_InitStruct.NSS = LL_SPI_NSS_SOFT; 817:Src/main.c **** SPI_InitStruct.BaudRate = LL_SPI_BAUDRATEPRESCALER_DIV8; 818:Src/main.c **** SPI_InitStruct.BitOrder = LL_SPI_MSB_FIRST; 819:Src/main.c **** SPI_InitStruct.CRCCalculation = LL_SPI_CRCCALCULATION_DISABLE; 820:Src/main.c **** SPI_InitStruct.CRCPoly = 7; 821:Src/main.c **** LL_SPI_Init(SPI2, &SPI_InitStruct); 822:Src/main.c **** LL_SPI_SetStandard(SPI2, LL_SPI_PROTOCOL_MOTOROLA); 823:Src/main.c **** LL_SPI_DisableNSSPulseMgt(SPI2); 824:Src/main.c **** /* USER CODE BEGIN SPI2_Init 2 */ 825:Src/main.c **** 826:Src/main.c **** /* USER CODE END SPI2_Init 2 */ 827:Src/main.c **** 828:Src/main.c **** } 829:Src/main.c **** 830:Src/main.c **** /** 831:Src/main.c **** * @brief SPI4 Initialization Function 832:Src/main.c **** * @param None 833:Src/main.c **** * @retval None 834:Src/main.c **** */ 835:Src/main.c **** static void MX_SPI4_Init(void) 836:Src/main.c **** { 837:Src/main.c **** 838:Src/main.c **** /* USER CODE BEGIN SPI4_Init 0 */ 839:Src/main.c **** 840:Src/main.c **** /* USER CODE END SPI4_Init 0 */ 841:Src/main.c **** 842:Src/main.c **** LL_SPI_InitTypeDef SPI_InitStruct = {0}; 843:Src/main.c **** 844:Src/main.c **** LL_GPIO_InitTypeDef GPIO_InitStruct = {0}; 845:Src/main.c **** 846:Src/main.c **** /* Peripheral clock enable */ 847:Src/main.c **** LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_SPI4); 848:Src/main.c **** 849:Src/main.c **** LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_GPIOE); 850:Src/main.c **** /**SPI4 GPIO Configuration 851:Src/main.c **** PE12 ------> SPI4_SCK 852:Src/main.c **** PE13 ------> SPI4_MISO 853:Src/main.c **** */ 854:Src/main.c **** GPIO_InitStruct.Pin = LL_GPIO_PIN_12; 855:Src/main.c **** GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE; 856:Src/main.c **** GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH; ARM GAS /tmp/ccdsDELB.s page 55 857:Src/main.c **** GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; 858:Src/main.c **** GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; 859:Src/main.c **** GPIO_InitStruct.Alternate = LL_GPIO_AF_5; 860:Src/main.c **** LL_GPIO_Init(GPIOE, &GPIO_InitStruct); 861:Src/main.c **** 862:Src/main.c **** GPIO_InitStruct.Pin = LL_GPIO_PIN_13; 863:Src/main.c **** GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE; 864:Src/main.c **** GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH; 865:Src/main.c **** GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; 866:Src/main.c **** GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; 867:Src/main.c **** GPIO_InitStruct.Alternate = LL_GPIO_AF_5; 868:Src/main.c **** LL_GPIO_Init(GPIOE, &GPIO_InitStruct); 869:Src/main.c **** 870:Src/main.c **** /* USER CODE BEGIN SPI4_Init 1 */ 871:Src/main.c **** 872:Src/main.c **** /* USER CODE END SPI4_Init 1 */ 873:Src/main.c **** /* SPI4 parameter configuration*/ 874:Src/main.c **** SPI_InitStruct.TransferDirection = LL_SPI_SIMPLEX_RX; 875:Src/main.c **** SPI_InitStruct.Mode = LL_SPI_MODE_MASTER; 876:Src/main.c **** SPI_InitStruct.DataWidth = LL_SPI_DATAWIDTH_16BIT; 877:Src/main.c **** SPI_InitStruct.ClockPolarity = LL_SPI_POLARITY_HIGH; 878:Src/main.c **** SPI_InitStruct.ClockPhase = LL_SPI_PHASE_1EDGE; 879:Src/main.c **** SPI_InitStruct.NSS = LL_SPI_NSS_SOFT; 880:Src/main.c **** SPI_InitStruct.BaudRate = LL_SPI_BAUDRATEPRESCALER_DIV16; 881:Src/main.c **** SPI_InitStruct.BitOrder = LL_SPI_MSB_FIRST; 882:Src/main.c **** SPI_InitStruct.CRCCalculation = LL_SPI_CRCCALCULATION_DISABLE; 883:Src/main.c **** SPI_InitStruct.CRCPoly = 7; 884:Src/main.c **** LL_SPI_Init(SPI4, &SPI_InitStruct); 885:Src/main.c **** LL_SPI_SetStandard(SPI4, LL_SPI_PROTOCOL_MOTOROLA); 886:Src/main.c **** LL_SPI_DisableNSSPulseMgt(SPI4); 887:Src/main.c **** /* USER CODE BEGIN SPI4_Init 2 */ 888:Src/main.c **** 889:Src/main.c **** /* USER CODE END SPI4_Init 2 */ 890:Src/main.c **** 891:Src/main.c **** } 892:Src/main.c **** 893:Src/main.c **** /** 894:Src/main.c **** * @brief SPI5 Initialization Function 895:Src/main.c **** * @param None 896:Src/main.c **** * @retval None 897:Src/main.c **** */ 898:Src/main.c **** static void MX_SPI5_Init(void) 899:Src/main.c **** { 900:Src/main.c **** 901:Src/main.c **** /* USER CODE BEGIN SPI5_Init 0 */ 902:Src/main.c **** 903:Src/main.c **** /* USER CODE END SPI5_Init 0 */ 904:Src/main.c **** 905:Src/main.c **** LL_SPI_InitTypeDef SPI_InitStruct = {0}; 906:Src/main.c **** 907:Src/main.c **** LL_GPIO_InitTypeDef GPIO_InitStruct = {0}; 908:Src/main.c **** 909:Src/main.c **** /* Peripheral clock enable */ 910:Src/main.c **** LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_SPI5); 911:Src/main.c **** 912:Src/main.c **** LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_GPIOF); 913:Src/main.c **** /**SPI5 GPIO Configuration ARM GAS /tmp/ccdsDELB.s page 56 914:Src/main.c **** PF7 ------> SPI5_SCK 915:Src/main.c **** PF8 ------> SPI5_MISO 916:Src/main.c **** */ 917:Src/main.c **** GPIO_InitStruct.Pin = LL_GPIO_PIN_7; 918:Src/main.c **** GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE; 919:Src/main.c **** GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH; 920:Src/main.c **** GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; 921:Src/main.c **** GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; 922:Src/main.c **** GPIO_InitStruct.Alternate = LL_GPIO_AF_5; 923:Src/main.c **** LL_GPIO_Init(GPIOF, &GPIO_InitStruct); 924:Src/main.c **** 925:Src/main.c **** GPIO_InitStruct.Pin = LL_GPIO_PIN_8; 926:Src/main.c **** GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE; 927:Src/main.c **** GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH; 928:Src/main.c **** GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; 929:Src/main.c **** GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; 930:Src/main.c **** GPIO_InitStruct.Alternate = LL_GPIO_AF_5; 931:Src/main.c **** LL_GPIO_Init(GPIOF, &GPIO_InitStruct); 932:Src/main.c **** 933:Src/main.c **** /* USER CODE BEGIN SPI5_Init 1 */ 934:Src/main.c **** 935:Src/main.c **** /* USER CODE END SPI5_Init 1 */ 936:Src/main.c **** /* SPI5 parameter configuration*/ 937:Src/main.c **** SPI_InitStruct.TransferDirection = LL_SPI_SIMPLEX_RX; 938:Src/main.c **** SPI_InitStruct.Mode = LL_SPI_MODE_MASTER; 939:Src/main.c **** SPI_InitStruct.DataWidth = LL_SPI_DATAWIDTH_16BIT; 940:Src/main.c **** SPI_InitStruct.ClockPolarity = LL_SPI_POLARITY_HIGH; 941:Src/main.c **** SPI_InitStruct.ClockPhase = LL_SPI_PHASE_1EDGE; 942:Src/main.c **** SPI_InitStruct.NSS = LL_SPI_NSS_SOFT; 943:Src/main.c **** SPI_InitStruct.BaudRate = LL_SPI_BAUDRATEPRESCALER_DIV16; 944:Src/main.c **** SPI_InitStruct.BitOrder = LL_SPI_MSB_FIRST; 945:Src/main.c **** SPI_InitStruct.CRCCalculation = LL_SPI_CRCCALCULATION_DISABLE; 946:Src/main.c **** SPI_InitStruct.CRCPoly = 7; 947:Src/main.c **** LL_SPI_Init(SPI5, &SPI_InitStruct); 948:Src/main.c **** LL_SPI_SetStandard(SPI5, LL_SPI_PROTOCOL_MOTOROLA); 949:Src/main.c **** LL_SPI_DisableNSSPulseMgt(SPI5); 950:Src/main.c **** /* USER CODE BEGIN SPI5_Init 2 */ 951:Src/main.c **** 952:Src/main.c **** /* USER CODE END SPI5_Init 2 */ 953:Src/main.c **** 954:Src/main.c **** } 955:Src/main.c **** 956:Src/main.c **** /** 957:Src/main.c **** * @brief SPI6 Initialization Function 958:Src/main.c **** * @param None 959:Src/main.c **** * @retval None 960:Src/main.c **** */ 961:Src/main.c **** static void MX_SPI6_Init(void) 962:Src/main.c **** { 963:Src/main.c **** 964:Src/main.c **** /* USER CODE BEGIN SPI6_Init 0 */ 965:Src/main.c **** 966:Src/main.c **** /* USER CODE END SPI6_Init 0 */ 967:Src/main.c **** 968:Src/main.c **** LL_SPI_InitTypeDef SPI_InitStruct = {0}; 969:Src/main.c **** 970:Src/main.c **** LL_GPIO_InitTypeDef GPIO_InitStruct = {0}; ARM GAS /tmp/ccdsDELB.s page 57 971:Src/main.c **** 972:Src/main.c **** /* Peripheral clock enable */ 973:Src/main.c **** LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_SPI6); 974:Src/main.c **** 975:Src/main.c **** LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_GPIOA); 976:Src/main.c **** /**SPI6 GPIO Configuration 977:Src/main.c **** PA5 ------> SPI6_SCK 978:Src/main.c **** PA7 ------> SPI6_MOSI 979:Src/main.c **** */ 980:Src/main.c **** GPIO_InitStruct.Pin = LL_GPIO_PIN_5; 981:Src/main.c **** GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE; 982:Src/main.c **** GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH; 983:Src/main.c **** GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; 984:Src/main.c **** GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; 985:Src/main.c **** GPIO_InitStruct.Alternate = LL_GPIO_AF_8; 986:Src/main.c **** LL_GPIO_Init(GPIOA, &GPIO_InitStruct); 987:Src/main.c **** 988:Src/main.c **** GPIO_InitStruct.Pin = LL_GPIO_PIN_7; 989:Src/main.c **** GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE; 990:Src/main.c **** GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH; 991:Src/main.c **** GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; 992:Src/main.c **** GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; 993:Src/main.c **** GPIO_InitStruct.Alternate = LL_GPIO_AF_8; 994:Src/main.c **** LL_GPIO_Init(GPIOA, &GPIO_InitStruct); 995:Src/main.c **** 996:Src/main.c **** /* USER CODE BEGIN SPI6_Init 1 */ 997:Src/main.c **** 998:Src/main.c **** /* USER CODE END SPI6_Init 1 */ 999:Src/main.c **** /* SPI6 parameter configuration*/ 1000:Src/main.c **** SPI_InitStruct.TransferDirection = LL_SPI_FULL_DUPLEX; 1001:Src/main.c **** SPI_InitStruct.Mode = LL_SPI_MODE_MASTER; 1002:Src/main.c **** SPI_InitStruct.DataWidth = LL_SPI_DATAWIDTH_16BIT; 1003:Src/main.c **** SPI_InitStruct.ClockPolarity = LL_SPI_POLARITY_HIGH; 1004:Src/main.c **** SPI_InitStruct.ClockPhase = LL_SPI_PHASE_2EDGE; 1005:Src/main.c **** SPI_InitStruct.NSS = LL_SPI_NSS_SOFT; 1006:Src/main.c **** SPI_InitStruct.BaudRate = LL_SPI_BAUDRATEPRESCALER_DIV16; 1007:Src/main.c **** SPI_InitStruct.BitOrder = LL_SPI_MSB_FIRST; 1008:Src/main.c **** SPI_InitStruct.CRCCalculation = LL_SPI_CRCCALCULATION_DISABLE; 1009:Src/main.c **** SPI_InitStruct.CRCPoly = 7; 1010:Src/main.c **** LL_SPI_Init(SPI6, &SPI_InitStruct); 1011:Src/main.c **** LL_SPI_SetStandard(SPI6, LL_SPI_PROTOCOL_MOTOROLA); 1012:Src/main.c **** LL_SPI_DisableNSSPulseMgt(SPI6); 1013:Src/main.c **** /* USER CODE BEGIN SPI6_Init 2 */ 1014:Src/main.c **** 1015:Src/main.c **** /* USER CODE END SPI6_Init 2 */ 1016:Src/main.c **** 1017:Src/main.c **** } 1018:Src/main.c **** 1019:Src/main.c **** /** 1020:Src/main.c **** * @brief TIM2 Initialization Function 1021:Src/main.c **** * @param None 1022:Src/main.c **** * @retval None 1023:Src/main.c **** */ 1024:Src/main.c **** static void MX_TIM2_Init(void) 1025:Src/main.c **** { 1026:Src/main.c **** 1027:Src/main.c **** /* USER CODE BEGIN TIM2_Init 0 */ ARM GAS /tmp/ccdsDELB.s page 58 1028:Src/main.c **** 1029:Src/main.c **** /* USER CODE END TIM2_Init 0 */ 1030:Src/main.c **** 1031:Src/main.c **** LL_TIM_InitTypeDef TIM_InitStruct = {0}; 1032:Src/main.c **** 1033:Src/main.c **** /* Peripheral clock enable */ 1034:Src/main.c **** LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_TIM2); 1035:Src/main.c **** 1036:Src/main.c **** /* TIM2 interrupt Init */ 1037:Src/main.c **** NVIC_SetPriority(TIM2_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(),0, 0)); 1038:Src/main.c **** NVIC_EnableIRQ(TIM2_IRQn); 1039:Src/main.c **** 1040:Src/main.c **** /* USER CODE BEGIN TIM2_Init 1 */ 1041:Src/main.c **** 1042:Src/main.c **** /* USER CODE END TIM2_Init 1 */ 1043:Src/main.c **** TIM_InitStruct.Prescaler = 1000; 1044:Src/main.c **** TIM_InitStruct.CounterMode = LL_TIM_COUNTERMODE_UP; 1045:Src/main.c **** TIM_InitStruct.Autoreload = 840000; 1046:Src/main.c **** TIM_InitStruct.ClockDivision = LL_TIM_CLOCKDIVISION_DIV1; 1047:Src/main.c **** LL_TIM_Init(TIM2, &TIM_InitStruct); 1048:Src/main.c **** LL_TIM_DisableARRPreload(TIM2); 1049:Src/main.c **** LL_TIM_SetClockSource(TIM2, LL_TIM_CLOCKSOURCE_INTERNAL); 1050:Src/main.c **** LL_TIM_SetTriggerOutput(TIM2, LL_TIM_TRGO_RESET); 1051:Src/main.c **** LL_TIM_DisableMasterSlaveMode(TIM2); 1052:Src/main.c **** /* USER CODE BEGIN TIM2_Init 2 */ 1053:Src/main.c **** 1054:Src/main.c **** /* USER CODE END TIM2_Init 2 */ 1055:Src/main.c **** 1056:Src/main.c **** } 1057:Src/main.c **** 1058:Src/main.c **** /** 1059:Src/main.c **** * @brief TIM5 Initialization Function 1060:Src/main.c **** * @param None 1061:Src/main.c **** * @retval None 1062:Src/main.c **** */ 1063:Src/main.c **** static void MX_TIM5_Init(void) 1064:Src/main.c **** { 1065:Src/main.c **** 1066:Src/main.c **** /* USER CODE BEGIN TIM5_Init 0 */ 1067:Src/main.c **** 1068:Src/main.c **** /* USER CODE END TIM5_Init 0 */ 1069:Src/main.c **** 1070:Src/main.c **** LL_TIM_InitTypeDef TIM_InitStruct = {0}; 1071:Src/main.c **** 1072:Src/main.c **** /* Peripheral clock enable */ 1073:Src/main.c **** LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_TIM5); 1074:Src/main.c **** 1075:Src/main.c **** /* TIM5 interrupt Init */ 1076:Src/main.c **** NVIC_SetPriority(TIM5_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(),0, 0)); 1077:Src/main.c **** NVIC_EnableIRQ(TIM5_IRQn); 1078:Src/main.c **** 1079:Src/main.c **** /* USER CODE BEGIN TIM5_Init 1 */ 1080:Src/main.c **** 1081:Src/main.c **** /* USER CODE END TIM5_Init 1 */ 1082:Src/main.c **** TIM_InitStruct.Prescaler = 10000; 1083:Src/main.c **** TIM_InitStruct.CounterMode = LL_TIM_COUNTERMODE_UP; 1084:Src/main.c **** TIM_InitStruct.Autoreload = 560; ARM GAS /tmp/ccdsDELB.s page 59 1085:Src/main.c **** TIM_InitStruct.ClockDivision = LL_TIM_CLOCKDIVISION_DIV1; 1086:Src/main.c **** LL_TIM_Init(TIM5, &TIM_InitStruct); 1087:Src/main.c **** LL_TIM_DisableARRPreload(TIM5); 1088:Src/main.c **** LL_TIM_SetClockSource(TIM5, LL_TIM_CLOCKSOURCE_INTERNAL); 1089:Src/main.c **** LL_TIM_SetTriggerOutput(TIM5, LL_TIM_TRGO_RESET); 1090:Src/main.c **** LL_TIM_DisableMasterSlaveMode(TIM5); 1091:Src/main.c **** /* USER CODE BEGIN TIM5_Init 2 */ 1092:Src/main.c **** 1093:Src/main.c **** /* USER CODE END TIM5_Init 2 */ 1094:Src/main.c **** 1095:Src/main.c **** } 1096:Src/main.c **** 1097:Src/main.c **** /** 1098:Src/main.c **** * @brief TIM6 Initialization Function 1099:Src/main.c **** * @param None 1100:Src/main.c **** * @retval None 1101:Src/main.c **** */ 1102:Src/main.c **** static void MX_TIM6_Init(void) 1103:Src/main.c **** { 1104:Src/main.c **** 1105:Src/main.c **** /* USER CODE BEGIN TIM6_Init 0 */ 1106:Src/main.c **** 1107:Src/main.c **** /* USER CODE END TIM6_Init 0 */ 1108:Src/main.c **** 1109:Src/main.c **** LL_TIM_InitTypeDef TIM_InitStruct = {0}; 1110:Src/main.c **** 1111:Src/main.c **** /* Peripheral clock enable */ 1112:Src/main.c **** LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_TIM6); 1113:Src/main.c **** 1114:Src/main.c **** /* TIM6 interrupt Init */ 1115:Src/main.c **** NVIC_SetPriority(TIM6_DAC_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(),0, 0)); 1116:Src/main.c **** NVIC_EnableIRQ(TIM6_DAC_IRQn); 1117:Src/main.c **** 1118:Src/main.c **** /* USER CODE BEGIN TIM6_Init 1 */ 1119:Src/main.c **** 1120:Src/main.c **** /* USER CODE END TIM6_Init 1 */ 1121:Src/main.c **** TIM_InitStruct.Prescaler = 45999; 1122:Src/main.c **** TIM_InitStruct.CounterMode = LL_TIM_COUNTERMODE_UP; 1123:Src/main.c **** TIM_InitStruct.Autoreload = 19; 1124:Src/main.c **** LL_TIM_Init(TIM6, &TIM_InitStruct); 1125:Src/main.c **** LL_TIM_DisableARRPreload(TIM6); 1126:Src/main.c **** LL_TIM_SetTriggerOutput(TIM6, LL_TIM_TRGO_ENABLE); 1127:Src/main.c **** LL_TIM_DisableMasterSlaveMode(TIM6); 1128:Src/main.c **** /* USER CODE BEGIN TIM6_Init 2 */ 1129:Src/main.c **** 1130:Src/main.c **** /* USER CODE END TIM6_Init 2 */ 1131:Src/main.c **** 1132:Src/main.c **** } 1133:Src/main.c **** 1134:Src/main.c **** /** 1135:Src/main.c **** * @brief TIM7 Initialization Function 1136:Src/main.c **** * @param None 1137:Src/main.c **** * @retval None 1138:Src/main.c **** */ 1139:Src/main.c **** static void MX_TIM7_Init(void) 1140:Src/main.c **** { 1141:Src/main.c **** ARM GAS /tmp/ccdsDELB.s page 60 1142:Src/main.c **** /* USER CODE BEGIN TIM7_Init 0 */ 1143:Src/main.c **** 1144:Src/main.c **** /* USER CODE END TIM7_Init 0 */ 1145:Src/main.c **** 1146:Src/main.c **** LL_TIM_InitTypeDef TIM_InitStruct = {0}; 1147:Src/main.c **** 1148:Src/main.c **** /* Peripheral clock enable */ 1149:Src/main.c **** LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_TIM7); 1150:Src/main.c **** 1151:Src/main.c **** /* TIM7 interrupt Init */ 1152:Src/main.c **** NVIC_SetPriority(TIM7_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(),0, 0)); 1153:Src/main.c **** NVIC_EnableIRQ(TIM7_IRQn); 1154:Src/main.c **** 1155:Src/main.c **** /* USER CODE BEGIN TIM7_Init 1 */ 1156:Src/main.c **** 1157:Src/main.c **** /* USER CODE END TIM7_Init 1 */ 1158:Src/main.c **** TIM_InitStruct.Prescaler = 919; 1159:Src/main.c **** TIM_InitStruct.CounterMode = LL_TIM_COUNTERMODE_UP; 1160:Src/main.c **** TIM_InitStruct.Autoreload = 99; 1161:Src/main.c **** LL_TIM_Init(TIM7, &TIM_InitStruct); 1162:Src/main.c **** LL_TIM_DisableARRPreload(TIM7); 1163:Src/main.c **** LL_TIM_SetTriggerOutput(TIM7, LL_TIM_TRGO_ENABLE); 1164:Src/main.c **** LL_TIM_DisableMasterSlaveMode(TIM7); 1165:Src/main.c **** /* USER CODE BEGIN TIM7_Init 2 */ 1166:Src/main.c **** 1167:Src/main.c **** /* USER CODE END TIM7_Init 2 */ 1168:Src/main.c **** 1169:Src/main.c **** } 1170:Src/main.c **** 1171:Src/main.c **** /** 1172:Src/main.c **** * @brief TIM10 Initialization Function 1173:Src/main.c **** * @param None 1174:Src/main.c **** * @retval None 1175:Src/main.c **** */ 1176:Src/main.c **** static void MX_TIM10_Init(void) 1177:Src/main.c **** { 1178:Src/main.c **** 1179:Src/main.c **** /* USER CODE BEGIN TIM10_Init 0 */ 1180:Src/main.c **** 1181:Src/main.c **** /* USER CODE END TIM10_Init 0 */ 1182:Src/main.c **** 1183:Src/main.c **** /* USER CODE BEGIN TIM10_Init 1 */ 1184:Src/main.c **** 1185:Src/main.c **** /* USER CODE END TIM10_Init 1 */ 1186:Src/main.c **** htim10.Instance = TIM10; 1187:Src/main.c **** htim10.Init.Prescaler = 183; 1188:Src/main.c **** htim10.Init.CounterMode = TIM_COUNTERMODE_UP; 1189:Src/main.c **** htim10.Init.Period = 9; 1190:Src/main.c **** htim10.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; 1191:Src/main.c **** htim10.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; 1192:Src/main.c **** if (HAL_TIM_Base_Init(&htim10) != HAL_OK) 1193:Src/main.c **** { 1194:Src/main.c **** Error_Handler(); 1195:Src/main.c **** } 1196:Src/main.c **** /* USER CODE BEGIN TIM10_Init 2 */ 1197:Src/main.c **** 1198:Src/main.c **** /* USER CODE END TIM10_Init 2 */ ARM GAS /tmp/ccdsDELB.s page 61 1199:Src/main.c **** 1200:Src/main.c **** } 1201:Src/main.c **** 1202:Src/main.c **** /** 1203:Src/main.c **** * @brief USART1 Initialization Function 1204:Src/main.c **** * @param None 1205:Src/main.c **** * @retval None 1206:Src/main.c **** */ 1207:Src/main.c **** static void MX_USART1_UART_Init(void) 1208:Src/main.c **** { 1209:Src/main.c **** 1210:Src/main.c **** /* USER CODE BEGIN USART1_Init 0 */ 1211:Src/main.c **** 1212:Src/main.c **** /* USER CODE END USART1_Init 0 */ 1213:Src/main.c **** 1214:Src/main.c **** LL_USART_InitTypeDef USART_InitStruct = {0}; 1215:Src/main.c **** 1216:Src/main.c **** LL_GPIO_InitTypeDef GPIO_InitStruct = {0}; 1217:Src/main.c **** RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; 1218:Src/main.c **** 1219:Src/main.c **** /** Initializes the peripherals clock 1220:Src/main.c **** */ 1221:Src/main.c **** PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USART1; 1222:Src/main.c **** PeriphClkInitStruct.Usart1ClockSelection = RCC_USART1CLKSOURCE_PCLK2; 1223:Src/main.c **** if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) 1224:Src/main.c **** { 1225:Src/main.c **** Error_Handler(); 1226:Src/main.c **** } 1227:Src/main.c **** 1228:Src/main.c **** /* Peripheral clock enable */ 1229:Src/main.c **** LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_USART1); 1230:Src/main.c **** 1231:Src/main.c **** LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_GPIOA); 1232:Src/main.c **** /**USART1 GPIO Configuration 1233:Src/main.c **** PA9 ------> USART1_TX 1234:Src/main.c **** PA10 ------> USART1_RX 1235:Src/main.c **** */ 1236:Src/main.c **** GPIO_InitStruct.Pin = LL_GPIO_PIN_9; 1237:Src/main.c **** GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE; 1238:Src/main.c **** GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH; 1239:Src/main.c **** GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; 1240:Src/main.c **** GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; 1241:Src/main.c **** GPIO_InitStruct.Alternate = LL_GPIO_AF_7; 1242:Src/main.c **** LL_GPIO_Init(GPIOA, &GPIO_InitStruct); 1243:Src/main.c **** 1244:Src/main.c **** GPIO_InitStruct.Pin = LL_GPIO_PIN_10; 1245:Src/main.c **** GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE; 1246:Src/main.c **** GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH; 1247:Src/main.c **** GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; 1248:Src/main.c **** GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; 1249:Src/main.c **** GPIO_InitStruct.Alternate = LL_GPIO_AF_7; 1250:Src/main.c **** LL_GPIO_Init(GPIOA, &GPIO_InitStruct); 1251:Src/main.c **** 1252:Src/main.c **** /* USART1 DMA Init */ 1253:Src/main.c **** 1254:Src/main.c **** /* USART1_TX Init */ 1255:Src/main.c **** LL_DMA_SetChannelSelection(DMA2, LL_DMA_STREAM_7, LL_DMA_CHANNEL_4); ARM GAS /tmp/ccdsDELB.s page 62 1256:Src/main.c **** 1257:Src/main.c **** LL_DMA_SetDataTransferDirection(DMA2, LL_DMA_STREAM_7, LL_DMA_DIRECTION_MEMORY_TO_PERIPH); 1258:Src/main.c **** 1259:Src/main.c **** LL_DMA_SetStreamPriorityLevel(DMA2, LL_DMA_STREAM_7, LL_DMA_PRIORITY_VERYHIGH); 1260:Src/main.c **** 1261:Src/main.c **** LL_DMA_SetMode(DMA2, LL_DMA_STREAM_7, LL_DMA_MODE_NORMAL); 1262:Src/main.c **** 1263:Src/main.c **** LL_DMA_SetPeriphIncMode(DMA2, LL_DMA_STREAM_7, LL_DMA_PERIPH_NOINCREMENT); 1264:Src/main.c **** 1265:Src/main.c **** LL_DMA_SetMemoryIncMode(DMA2, LL_DMA_STREAM_7, LL_DMA_MEMORY_INCREMENT); 1266:Src/main.c **** 1267:Src/main.c **** LL_DMA_SetPeriphSize(DMA2, LL_DMA_STREAM_7, LL_DMA_PDATAALIGN_BYTE); 1268:Src/main.c **** 1269:Src/main.c **** LL_DMA_SetMemorySize(DMA2, LL_DMA_STREAM_7, LL_DMA_MDATAALIGN_BYTE); 1270:Src/main.c **** 1271:Src/main.c **** LL_DMA_DisableFifoMode(DMA2, LL_DMA_STREAM_7); 1272:Src/main.c **** 1273:Src/main.c **** /* USART1 interrupt Init */ 1274:Src/main.c **** NVIC_SetPriority(USART1_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(),0, 0)); 1275:Src/main.c **** NVIC_EnableIRQ(USART1_IRQn); 1276:Src/main.c **** 1277:Src/main.c **** /* USER CODE BEGIN USART1_Init 1 */ 1278:Src/main.c **** 1279:Src/main.c **** /* USER CODE END USART1_Init 1 */ 1280:Src/main.c **** USART_InitStruct.BaudRate = 115200; 1281:Src/main.c **** USART_InitStruct.DataWidth = LL_USART_DATAWIDTH_8B; 1282:Src/main.c **** USART_InitStruct.StopBits = LL_USART_STOPBITS_1; 1283:Src/main.c **** USART_InitStruct.Parity = LL_USART_PARITY_NONE; 1284:Src/main.c **** USART_InitStruct.TransferDirection = LL_USART_DIRECTION_TX_RX; 1285:Src/main.c **** USART_InitStruct.HardwareFlowControl = LL_USART_HWCONTROL_NONE; 1286:Src/main.c **** USART_InitStruct.OverSampling = LL_USART_OVERSAMPLING_16; 1287:Src/main.c **** LL_USART_Init(USART1, &USART_InitStruct); 1288:Src/main.c **** LL_USART_ConfigAsyncMode(USART1); 1289:Src/main.c **** LL_USART_Enable(USART1); 1290:Src/main.c **** /* USER CODE BEGIN USART1_Init 2 */ 1291:Src/main.c **** 1292:Src/main.c **** /* USER CODE END USART1_Init 2 */ 1293:Src/main.c **** 1294:Src/main.c **** } 1295:Src/main.c **** 1296:Src/main.c **** /** 1297:Src/main.c **** * Enable DMA controller clock 1298:Src/main.c **** */ 1299:Src/main.c **** static void MX_DMA_Init(void) 1300:Src/main.c **** { 143 .loc 2 1300 1 is_stmt 1 view -0 144 .cfi_startproc 145 @ args = 0, pretend = 0, frame = 8 146 @ frame_needed = 0, uses_anonymous_args = 0 147 0000 00B5 push {lr} 148 .LCFI0: 149 .cfi_def_cfa_offset 4 150 .cfi_offset 14, -4 151 0002 83B0 sub sp, sp, #12 152 .LCFI1: 153 .cfi_def_cfa_offset 16 1301:Src/main.c **** ARM GAS /tmp/ccdsDELB.s page 63 1302:Src/main.c **** /* Init with LL driver */ 1303:Src/main.c **** /* DMA controller clock enable */ 1304:Src/main.c **** LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_DMA2); 154 .loc 2 1304 3 view .LVU37 155 .LVL8: 156 .LBB293: 157 .LBI293: 158 .file 3 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h" 1:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** 2:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** ****************************************************************************** 3:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @file stm32f7xx_ll_bus.h 4:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @author MCD Application Team 5:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Header file of BUS LL module. 6:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 7:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** @verbatim 8:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** ##### RCC Limitations ##### 9:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** ============================================================================== 10:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** [..] 11:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** A delay between an RCC peripheral clock enable and the effective peripheral 12:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** enabling should be taken into account in order to manage the peripheral read/write 13:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** from/to registers. 14:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (+) This delay depends on the peripheral mapping. 15:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (++) AHB & APB peripherals, 1 dummy read is necessary 16:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 17:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** [..] 18:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** Workarounds: 19:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (#) For AHB & APB peripherals, a dummy read to the peripheral register has been 20:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** inserted in each LL_{BUS}_GRP{x}_EnableClock() function. 21:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 22:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** @endverbatim 23:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** ****************************************************************************** 24:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @attention 25:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * 26:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * Copyright (c) 2017 STMicroelectronics. 27:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * All rights reserved. 28:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * 29:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * This software is licensed under terms that can be found in the LICENSE file in 30:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * the root directory of this software component. 31:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * If no LICENSE file comes with this software, it is provided AS-IS. 32:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** ****************************************************************************** 33:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ 34:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 35:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Define to prevent recursive inclusion -------------------------------------*/ 36:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #ifndef __STM32F7xx_LL_BUS_H 37:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define __STM32F7xx_LL_BUS_H 38:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 39:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #ifdef __cplusplus 40:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** extern "C" { 41:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif 42:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 43:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Includes ------------------------------------------------------------------*/ 44:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #include "stm32f7xx.h" 45:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 46:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** @addtogroup STM32F7xx_LL_Driver 47:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @{ 48:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ 49:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** ARM GAS /tmp/ccdsDELB.s page 64 50:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(RCC) 51:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 52:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** @defgroup BUS_LL BUS 53:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @{ 54:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ 55:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 56:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Private types -------------------------------------------------------------*/ 57:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Private variables ---------------------------------------------------------*/ 58:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Private constants ---------------------------------------------------------*/ 59:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Private macros ------------------------------------------------------------*/ 60:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Exported types ------------------------------------------------------------*/ 61:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Exported constants --------------------------------------------------------*/ 62:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** @defgroup BUS_LL_Exported_Constants BUS Exported Constants 63:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @{ 64:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ 65:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 66:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** @defgroup BUS_LL_EC_AHB1_GRP1_PERIPH AHB1 GRP1 PERIPH 67:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @{ 68:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ 69:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_ALL 0xFFFFFFFFU 70:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_GPIOA RCC_AHB1ENR_GPIOAEN 71:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_GPIOB RCC_AHB1ENR_GPIOBEN 72:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_GPIOC RCC_AHB1ENR_GPIOCEN 73:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_GPIOD RCC_AHB1ENR_GPIODEN 74:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_GPIOE RCC_AHB1ENR_GPIOEEN 75:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_GPIOF RCC_AHB1ENR_GPIOFEN 76:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_GPIOG RCC_AHB1ENR_GPIOGEN 77:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_GPIOH RCC_AHB1ENR_GPIOHEN 78:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_GPIOI RCC_AHB1ENR_GPIOIEN 79:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(GPIOJ) 80:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_GPIOJ RCC_AHB1ENR_GPIOJEN 81:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* GPIOJ */ 82:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(GPIOK) 83:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_GPIOK RCC_AHB1ENR_GPIOKEN 84:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* GPIOK */ 85:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_CRC RCC_AHB1ENR_CRCEN 86:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_BKPSRAM RCC_AHB1ENR_BKPSRAMEN 87:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_DTCMRAM RCC_AHB1ENR_DTCMRAMEN 88:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_DMA1 RCC_AHB1ENR_DMA1EN 89:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_DMA2 RCC_AHB1ENR_DMA2EN 90:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(DMA2D) 91:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_DMA2D RCC_AHB1ENR_DMA2DEN 92:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* DMA2D */ 93:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(ETH) 94:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_ETHMAC RCC_AHB1ENR_ETHMACEN 95:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_ETHMACTX RCC_AHB1ENR_ETHMACTXEN 96:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_ETHMACRX RCC_AHB1ENR_ETHMACRXEN 97:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_ETHMACPTP RCC_AHB1ENR_ETHMACPTPEN 98:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* ETH */ 99:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_OTGHS RCC_AHB1ENR_OTGHSEN 100:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_OTGHSULPI RCC_AHB1ENR_OTGHSULPIEN 101:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_AXI RCC_AHB1LPENR_AXILPEN 102:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_FLITF RCC_AHB1LPENR_FLITFLPEN 103:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_SRAM1 RCC_AHB1LPENR_SRAM1LPEN 104:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_SRAM2 RCC_AHB1LPENR_SRAM2LPEN 105:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** 106:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @} ARM GAS /tmp/ccdsDELB.s page 65 107:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ 108:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 109:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** @defgroup BUS_LL_EC_AHB2_GRP1_PERIPH AHB2 GRP1 PERIPH 110:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @{ 111:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ 112:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB2_GRP1_PERIPH_ALL 0xFFFFFFFFU 113:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(DCMI) 114:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB2_GRP1_PERIPH_DCMI RCC_AHB2ENR_DCMIEN 115:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* DCMI */ 116:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(JPEG) 117:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB2_GRP1_PERIPH_JPEG RCC_AHB2ENR_JPEGEN 118:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* JPEG */ 119:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(CRYP) 120:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB2_GRP1_PERIPH_CRYP RCC_AHB2ENR_CRYPEN 121:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* CRYP */ 122:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(AES) 123:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB2_GRP1_PERIPH_AES RCC_AHB2ENR_AESEN 124:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* AES */ 125:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(HASH) 126:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB2_GRP1_PERIPH_HASH RCC_AHB2ENR_HASHEN 127:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* HASH */ 128:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB2_GRP1_PERIPH_RNG RCC_AHB2ENR_RNGEN 129:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB2_GRP1_PERIPH_OTGFS RCC_AHB2ENR_OTGFSEN 130:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** 131:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @} 132:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ 133:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 134:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** @defgroup BUS_LL_EC_AHB3_GRP1_PERIPH AHB3 GRP1 PERIPH 135:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @{ 136:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ 137:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB3_GRP1_PERIPH_ALL 0xFFFFFFFFU 138:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB3_GRP1_PERIPH_FMC RCC_AHB3ENR_FMCEN 139:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB3_GRP1_PERIPH_QSPI RCC_AHB3ENR_QSPIEN 140:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** 141:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @} 142:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ 143:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 144:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** @defgroup BUS_LL_EC_APB1_GRP1_PERIPH APB1 GRP1 PERIPH 145:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @{ 146:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ 147:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_ALL 0xFFFFFFFFU 148:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_TIM2 RCC_APB1ENR_TIM2EN 149:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_TIM3 RCC_APB1ENR_TIM3EN 150:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_TIM4 RCC_APB1ENR_TIM4EN 151:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_TIM5 RCC_APB1ENR_TIM5EN 152:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_TIM6 RCC_APB1ENR_TIM6EN 153:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_TIM7 RCC_APB1ENR_TIM7EN 154:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_TIM12 RCC_APB1ENR_TIM12EN 155:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_TIM13 RCC_APB1ENR_TIM13EN 156:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_TIM14 RCC_APB1ENR_TIM14EN 157:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_LPTIM1 RCC_APB1ENR_LPTIM1EN 158:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_WWDG RCC_APB1ENR_WWDGEN 159:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_SPI2 RCC_APB1ENR_SPI2EN 160:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_SPI3 RCC_APB1ENR_SPI3EN 161:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(SPDIFRX) 162:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_SPDIFRX RCC_APB1ENR_SPDIFRXEN 163:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* SPDIFRX */ ARM GAS /tmp/ccdsDELB.s page 66 164:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_USART2 RCC_APB1ENR_USART2EN 165:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_USART3 RCC_APB1ENR_USART3EN 166:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_UART4 RCC_APB1ENR_UART4EN 167:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_UART5 RCC_APB1ENR_UART5EN 168:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_I2C1 RCC_APB1ENR_I2C1EN 169:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_I2C2 RCC_APB1ENR_I2C2EN 170:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_I2C3 RCC_APB1ENR_I2C3EN 171:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(I2C4) 172:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_I2C4 RCC_APB1ENR_I2C4EN 173:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* I2C4 */ 174:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_CAN1 RCC_APB1ENR_CAN1EN 175:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(CAN2) 176:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_CAN2 RCC_APB1ENR_CAN2EN 177:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* CAN2 */ 178:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(CAN3) 179:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_CAN3 RCC_APB1ENR_CAN3EN 180:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* CAN3 */ 181:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(CEC) 182:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_CEC RCC_APB1ENR_CECEN 183:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* CEC */ 184:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_PWR RCC_APB1ENR_PWREN 185:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_DAC1 RCC_APB1ENR_DACEN 186:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_UART7 RCC_APB1ENR_UART7EN 187:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_UART8 RCC_APB1ENR_UART8EN 188:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(RCC_APB1ENR_RTCEN) 189:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_RTCAPB RCC_APB1ENR_RTCEN 190:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* RCC_APB1ENR_RTCEN */ 191:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** 192:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @} 193:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ 194:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 195:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** @defgroup BUS_LL_EC_APB2_GRP1_PERIPH APB2 GRP1 PERIPH 196:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @{ 197:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ 198:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_ALL 0xFFFFFFFFU 199:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_TIM1 RCC_APB2ENR_TIM1EN 200:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_TIM8 RCC_APB2ENR_TIM8EN 201:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_USART1 RCC_APB2ENR_USART1EN 202:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_USART6 RCC_APB2ENR_USART6EN 203:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_ADC1 RCC_APB2ENR_ADC1EN 204:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_ADC2 RCC_APB2ENR_ADC2EN 205:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_ADC3 RCC_APB2ENR_ADC3EN 206:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_SDMMC1 RCC_APB2ENR_SDMMC1EN 207:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(SDMMC2) 208:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_SDMMC2 RCC_APB2ENR_SDMMC2EN 209:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* SDMMC2 */ 210:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_SPI1 RCC_APB2ENR_SPI1EN 211:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_SPI4 RCC_APB2ENR_SPI4EN 212:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_SYSCFG RCC_APB2ENR_SYSCFGEN 213:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_TIM9 RCC_APB2ENR_TIM9EN 214:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_TIM10 RCC_APB2ENR_TIM10EN 215:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_TIM11 RCC_APB2ENR_TIM11EN 216:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_SPI5 RCC_APB2ENR_SPI5EN 217:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(SPI6) 218:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_SPI6 RCC_APB2ENR_SPI6EN 219:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* SPI6 */ 220:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_SAI1 RCC_APB2ENR_SAI1EN ARM GAS /tmp/ccdsDELB.s page 67 221:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_SAI2 RCC_APB2ENR_SAI2EN 222:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(LTDC) 223:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_LTDC RCC_APB2ENR_LTDCEN 224:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* LTDC */ 225:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(DSI) 226:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_DSI RCC_APB2ENR_DSIEN 227:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* DSI */ 228:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(DFSDM1_Channel0) 229:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_DFSDM1 RCC_APB2ENR_DFSDM1EN 230:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* DFSDM1_Channel0 */ 231:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(MDIOS) 232:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_MDIO RCC_APB2ENR_MDIOEN 233:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* MDIOS */ 234:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(USB_HS_PHYC) 235:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_OTGPHYC RCC_APB2ENR_OTGPHYCEN 236:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* USB_HS_PHYC */ 237:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_ADC RCC_APB2RSTR_ADCRST 238:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** 239:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @} 240:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ 241:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 242:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** 243:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @} 244:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ 245:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 246:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Exported macro ------------------------------------------------------------*/ 247:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Exported functions --------------------------------------------------------*/ 248:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** @defgroup BUS_LL_Exported_Functions BUS Exported Functions 249:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @{ 250:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ 251:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 252:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** @defgroup BUS_LL_EF_AHB1 AHB1 253:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @{ 254:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ 255:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 256:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** 257:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Enable AHB1 peripherals clock. 258:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll AHB1ENR GPIOAEN LL_AHB1_GRP1_EnableClock\n 259:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOBEN LL_AHB1_GRP1_EnableClock\n 260:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOCEN LL_AHB1_GRP1_EnableClock\n 261:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIODEN LL_AHB1_GRP1_EnableClock\n 262:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOEEN LL_AHB1_GRP1_EnableClock\n 263:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOFEN LL_AHB1_GRP1_EnableClock\n 264:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOGEN LL_AHB1_GRP1_EnableClock\n 265:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOHEN LL_AHB1_GRP1_EnableClock\n 266:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOIEN LL_AHB1_GRP1_EnableClock\n 267:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOJEN LL_AHB1_GRP1_EnableClock\n 268:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOKEN LL_AHB1_GRP1_EnableClock\n 269:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR CRCEN LL_AHB1_GRP1_EnableClock\n 270:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR BKPSRAMEN LL_AHB1_GRP1_EnableClock\n 271:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR DTCMRAMEN LL_AHB1_GRP1_EnableClock\n 272:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR DMA1EN LL_AHB1_GRP1_EnableClock\n 273:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR DMA2EN LL_AHB1_GRP1_EnableClock\n 274:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR DMA2DEN LL_AHB1_GRP1_EnableClock\n 275:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR ETHMACEN LL_AHB1_GRP1_EnableClock\n 276:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR ETHMACTXEN LL_AHB1_GRP1_EnableClock\n 277:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR ETHMACRXEN LL_AHB1_GRP1_EnableClock\n ARM GAS /tmp/ccdsDELB.s page 68 278:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR ETHMACPTPEN LL_AHB1_GRP1_EnableClock\n 279:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR OTGHSEN LL_AHB1_GRP1_EnableClock\n 280:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR OTGHSULPIEN LL_AHB1_GRP1_EnableClock 281:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: 282:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA 283:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB 284:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC 285:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD 286:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE 287:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF 288:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG 289:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH 290:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI 291:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*) 292:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*) 293:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRC 294:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM 295:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DTCMRAM 296:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 298:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*) 299:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*) 300:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*) 301:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*) 302:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACPTP (*) 303:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS 304:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHSULPI 305:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * 306:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. 307:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval None 308:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ 309:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs) 159 .loc 3 309 22 view .LVU38 160 .LBB294: 310:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { 311:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __IO uint32_t tmpreg; 161 .loc 3 311 3 view .LVU39 312:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** SET_BIT(RCC->AHB1ENR, Periphs); 162 .loc 3 312 3 view .LVU40 163 0004 0D4B ldr r3, .L9 164 0006 1A6B ldr r2, [r3, #48] 165 0008 42F48002 orr r2, r2, #4194304 166 000c 1A63 str r2, [r3, #48] 313:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Delay after an RCC peripheral clock enabling */ 314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** tmpreg = READ_BIT(RCC->AHB1ENR, Periphs); 167 .loc 3 314 3 view .LVU41 168 .loc 3 314 12 is_stmt 0 view .LVU42 169 000e 1B6B ldr r3, [r3, #48] 170 0010 03F48003 and r3, r3, #4194304 171 .loc 3 314 10 view .LVU43 172 0014 0193 str r3, [sp, #4] 315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; 173 .loc 3 315 3 is_stmt 1 view .LVU44 174 0016 019B ldr r3, [sp, #4] 175 .LVL9: 176 .loc 3 315 3 is_stmt 0 view .LVU45 177 .LBE294: ARM GAS /tmp/ccdsDELB.s page 69 178 .LBE293: 1305:Src/main.c **** 1306:Src/main.c **** /* DMA interrupt init */ 1307:Src/main.c **** /* DMA2_Stream7_IRQn interrupt configuration */ 1308:Src/main.c **** NVIC_SetPriority(DMA2_Stream7_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(),0, 0)); 179 .loc 2 1308 3 is_stmt 1 view .LVU46 180 .LBB295: 181 .LBI295: 1884:Drivers/CMSIS/Include/core_cm7.h **** { 182 .loc 1 1884 26 view .LVU47 183 .LBB296: 1886:Drivers/CMSIS/Include/core_cm7.h **** } 184 .loc 1 1886 3 view .LVU48 1886:Drivers/CMSIS/Include/core_cm7.h **** } 185 .loc 1 1886 26 is_stmt 0 view .LVU49 186 0018 094B ldr r3, .L9+4 187 001a D868 ldr r0, [r3, #12] 188 .LBE296: 189 .LBE295: 190 .loc 2 1308 3 view .LVU50 191 001c 0022 movs r2, #0 192 001e 1146 mov r1, r2 193 0020 C0F30220 ubfx r0, r0, #8, #3 194 0024 FFF7FEFF bl NVIC_EncodePriority 195 .LVL10: 196 .LBB297: 197 .LBI297: 2024:Drivers/CMSIS/Include/core_cm7.h **** { 198 .loc 1 2024 22 is_stmt 1 view .LVU51 199 .LBB298: 2026:Drivers/CMSIS/Include/core_cm7.h **** { 200 .loc 1 2026 3 view .LVU52 2028:Drivers/CMSIS/Include/core_cm7.h **** } 201 .loc 1 2028 5 view .LVU53 2028:Drivers/CMSIS/Include/core_cm7.h **** } 202 .loc 1 2028 49 is_stmt 0 view .LVU54 203 0028 0001 lsls r0, r0, #4 204 .LVL11: 2028:Drivers/CMSIS/Include/core_cm7.h **** } 205 .loc 1 2028 49 view .LVU55 206 002a C0B2 uxtb r0, r0 2028:Drivers/CMSIS/Include/core_cm7.h **** } 207 .loc 1 2028 47 view .LVU56 208 002c 054B ldr r3, .L9+8 209 002e 83F84603 strb r0, [r3, #838] 210 .LVL12: 2028:Drivers/CMSIS/Include/core_cm7.h **** } 211 .loc 1 2028 47 view .LVU57 212 .LBE298: 213 .LBE297: 1309:Src/main.c **** NVIC_EnableIRQ(DMA2_Stream7_IRQn); 214 .loc 2 1309 3 is_stmt 1 view .LVU58 215 .LBB299: 216 .LBI299: 1896:Drivers/CMSIS/Include/core_cm7.h **** { 217 .loc 1 1896 22 view .LVU59 218 .LBB300: ARM GAS /tmp/ccdsDELB.s page 70 1898:Drivers/CMSIS/Include/core_cm7.h **** { 219 .loc 1 1898 3 view .LVU60 1900:Drivers/CMSIS/Include/core_cm7.h **** } 220 .loc 1 1900 5 view .LVU61 1900:Drivers/CMSIS/Include/core_cm7.h **** } 221 .loc 1 1900 43 is_stmt 0 view .LVU62 222 0032 4022 movs r2, #64 223 0034 9A60 str r2, [r3, #8] 224 .LVL13: 1900:Drivers/CMSIS/Include/core_cm7.h **** } 225 .loc 1 1900 43 view .LVU63 226 .LBE300: 227 .LBE299: 1310:Src/main.c **** 1311:Src/main.c **** } 228 .loc 2 1311 1 view .LVU64 229 0036 03B0 add sp, sp, #12 230 .LCFI2: 231 .cfi_def_cfa_offset 4 232 @ sp needed 233 0038 5DF804FB ldr pc, [sp], #4 234 .L10: 235 .align 2 236 .L9: 237 003c 00380240 .word 1073887232 238 0040 00ED00E0 .word -536810240 239 0044 00E100E0 .word -536813312 240 .cfi_endproc 241 .LFE1201: 243 .section .text.Decode_task,"ax",%progbits 244 .align 1 245 .syntax unified 246 .thumb 247 .thumb_func 248 .fpu fpv5-d16 250 Decode_task: 251 .LVL14: 252 .LFB1205: 1312:Src/main.c **** 1313:Src/main.c **** /** 1314:Src/main.c **** * @brief GPIO Initialization Function 1315:Src/main.c **** * @param None 1316:Src/main.c **** * @retval None 1317:Src/main.c **** */ 1318:Src/main.c **** static void MX_GPIO_Init(void) 1319:Src/main.c **** { 1320:Src/main.c **** GPIO_InitTypeDef GPIO_InitStruct = {0}; 1321:Src/main.c **** /* USER CODE BEGIN MX_GPIO_Init_1 */ 1322:Src/main.c **** /* USER CODE END MX_GPIO_Init_1 */ 1323:Src/main.c **** 1324:Src/main.c **** /* GPIO Ports Clock Enable */ 1325:Src/main.c **** __HAL_RCC_GPIOF_CLK_ENABLE(); 1326:Src/main.c **** __HAL_RCC_GPIOH_CLK_ENABLE(); 1327:Src/main.c **** __HAL_RCC_GPIOC_CLK_ENABLE(); 1328:Src/main.c **** __HAL_RCC_GPIOA_CLK_ENABLE(); 1329:Src/main.c **** __HAL_RCC_GPIOB_CLK_ENABLE(); 1330:Src/main.c **** __HAL_RCC_GPIOE_CLK_ENABLE(); ARM GAS /tmp/ccdsDELB.s page 71 1331:Src/main.c **** __HAL_RCC_GPIOD_CLK_ENABLE(); 1332:Src/main.c **** 1333:Src/main.c **** /*Configure GPIO pin Output Level */ 1334:Src/main.c **** HAL_GPIO_WritePin(GPIOF, ADC_MPD2_CS_Pin|SPI5_CNV_Pin|ADC_ThrLD2_CS_Pin, GPIO_PIN_RESET); 1335:Src/main.c **** 1336:Src/main.c **** /*Configure GPIO pin Output Level */ 1337:Src/main.c **** HAL_GPIO_WritePin(GPIOC, EN_5V2_Pin|EN_5V1_Pin|LD2_EN_Pin|TEC2_PD_Pin, GPIO_PIN_RESET); 1338:Src/main.c **** 1339:Src/main.c **** /*Configure GPIO pin Output Level */ 1340:Src/main.c **** HAL_GPIO_WritePin(GPIOA, TECEN1_Pin|TECEN2_Pin|REF2_ON_Pin|DAC_LD2_CS_Pin, GPIO_PIN_RESET); 1341:Src/main.c **** 1342:Src/main.c **** /*Configure GPIO pin Output Level */ 1343:Src/main.c **** HAL_GPIO_WritePin(DAC_TEC2_CS_GPIO_Port, DAC_TEC2_CS_Pin, GPIO_PIN_SET); 1344:Src/main.c **** 1345:Src/main.c **** /*Configure GPIO pin Output Level */ 1346:Src/main.c **** HAL_GPIO_WritePin(GPIOE, ADC_MPD1_CS_Pin|ADC_ThrLD1_CS_Pin, GPIO_PIN_RESET); 1347:Src/main.c **** 1348:Src/main.c **** /*Configure GPIO pin Output Level */ 1349:Src/main.c **** HAL_GPIO_WritePin(SPI4_CNV_GPIO_Port, SPI4_CNV_Pin, GPIO_PIN_SET); 1350:Src/main.c **** 1351:Src/main.c **** /*Configure GPIO pin Output Level */ 1352:Src/main.c **** HAL_GPIO_WritePin(GPIOB, REF0_EN_Pin|TEC1_PD_Pin|DAC_LD1_CS_Pin, GPIO_PIN_RESET); 1353:Src/main.c **** 1354:Src/main.c **** /*Configure GPIO pin Output Level */ 1355:Src/main.c **** HAL_GPIO_WritePin(DAC_TEC1_CS_GPIO_Port, DAC_TEC1_CS_Pin, GPIO_PIN_SET); 1356:Src/main.c **** 1357:Src/main.c **** /*Configure GPIO pin Output Level */ 1358:Src/main.c **** HAL_GPIO_WritePin(GPIOD, LD1_EN_Pin|TEST_01_Pin|GPIO_PIN_7, GPIO_PIN_RESET); 1359:Src/main.c **** 1360:Src/main.c **** /*Configure GPIO pins : ADC_MPD2_CS_Pin SPI5_CNV_Pin ADC_ThrLD2_CS_Pin */ 1361:Src/main.c **** GPIO_InitStruct.Pin = ADC_MPD2_CS_Pin|SPI5_CNV_Pin|ADC_ThrLD2_CS_Pin; 1362:Src/main.c **** GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 1363:Src/main.c **** GPIO_InitStruct.Pull = GPIO_NOPULL; 1364:Src/main.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 1365:Src/main.c **** HAL_GPIO_Init(GPIOF, &GPIO_InitStruct); 1366:Src/main.c **** 1367:Src/main.c **** /*Configure GPIO pins : EN_5V2_Pin LD2_EN_Pin TEC2_PD_Pin */ 1368:Src/main.c **** GPIO_InitStruct.Pin = EN_5V2_Pin|LD2_EN_Pin|TEC2_PD_Pin; 1369:Src/main.c **** GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 1370:Src/main.c **** GPIO_InitStruct.Pull = GPIO_NOPULL; 1371:Src/main.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 1372:Src/main.c **** HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); 1373:Src/main.c **** 1374:Src/main.c **** /*Configure GPIO pin : EN_5V1_Pin */ 1375:Src/main.c **** GPIO_InitStruct.Pin = EN_5V1_Pin; 1376:Src/main.c **** GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 1377:Src/main.c **** GPIO_InitStruct.Pull = GPIO_NOPULL; 1378:Src/main.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; 1379:Src/main.c **** HAL_GPIO_Init(EN_5V1_GPIO_Port, &GPIO_InitStruct); 1380:Src/main.c **** 1381:Src/main.c **** /*Configure GPIO pins : TECEN1_Pin TECEN2_Pin REF2_ON_Pin DAC_TEC2_CS_Pin 1382:Src/main.c **** DAC_LD2_CS_Pin */ 1383:Src/main.c **** GPIO_InitStruct.Pin = TECEN1_Pin|TECEN2_Pin|REF2_ON_Pin|DAC_TEC2_CS_Pin 1384:Src/main.c **** |DAC_LD2_CS_Pin; 1385:Src/main.c **** GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 1386:Src/main.c **** GPIO_InitStruct.Pull = GPIO_NOPULL; 1387:Src/main.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; ARM GAS /tmp/ccdsDELB.s page 72 1388:Src/main.c **** HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 1389:Src/main.c **** 1390:Src/main.c **** /*Configure GPIO pins : TEC2_FLAG1_Pin TEC2_FLAG2_Pin TEC1_FLAG1_Pin TEC1_FLAG2_Pin */ 1391:Src/main.c **** GPIO_InitStruct.Pin = TEC2_FLAG1_Pin|TEC2_FLAG2_Pin|TEC1_FLAG1_Pin|TEC1_FLAG2_Pin; 1392:Src/main.c **** GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 1393:Src/main.c **** GPIO_InitStruct.Pull = GPIO_NOPULL; 1394:Src/main.c **** HAL_GPIO_Init(GPIOF, &GPIO_InitStruct); 1395:Src/main.c **** 1396:Src/main.c **** /*Configure GPIO pins : ADC_MPD1_CS_Pin ADC_ThrLD1_CS_Pin */ 1397:Src/main.c **** GPIO_InitStruct.Pin = ADC_MPD1_CS_Pin|ADC_ThrLD1_CS_Pin; 1398:Src/main.c **** GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 1399:Src/main.c **** GPIO_InitStruct.Pull = GPIO_NOPULL; 1400:Src/main.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 1401:Src/main.c **** HAL_GPIO_Init(GPIOE, &GPIO_InitStruct); 1402:Src/main.c **** 1403:Src/main.c **** /*Configure GPIO pin : SPI4_CNV_Pin */ 1404:Src/main.c **** GPIO_InitStruct.Pin = SPI4_CNV_Pin; 1405:Src/main.c **** GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 1406:Src/main.c **** GPIO_InitStruct.Pull = GPIO_NOPULL; 1407:Src/main.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; 1408:Src/main.c **** HAL_GPIO_Init(SPI4_CNV_GPIO_Port, &GPIO_InitStruct); 1409:Src/main.c **** 1410:Src/main.c **** /*Configure GPIO pins : REF0_EN_Pin TEC1_PD_Pin DAC_TEC1_CS_Pin DAC_LD1_CS_Pin */ 1411:Src/main.c **** GPIO_InitStruct.Pin = REF0_EN_Pin|TEC1_PD_Pin|DAC_TEC1_CS_Pin|DAC_LD1_CS_Pin; 1412:Src/main.c **** GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 1413:Src/main.c **** GPIO_InitStruct.Pull = GPIO_NOPULL; 1414:Src/main.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 1415:Src/main.c **** HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 1416:Src/main.c **** 1417:Src/main.c **** /*Configure GPIO pins : LD1_EN_Pin TEST_01_Pin PD7 */ 1418:Src/main.c **** GPIO_InitStruct.Pin = LD1_EN_Pin|TEST_01_Pin|GPIO_PIN_7; 1419:Src/main.c **** GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 1420:Src/main.c **** GPIO_InitStruct.Pull = GPIO_NOPULL; 1421:Src/main.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 1422:Src/main.c **** HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); 1423:Src/main.c **** 1424:Src/main.c **** /*Configure GPIO pin : USB_FLAG_Pin */ 1425:Src/main.c **** GPIO_InitStruct.Pin = USB_FLAG_Pin; 1426:Src/main.c **** GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 1427:Src/main.c **** GPIO_InitStruct.Pull = GPIO_NOPULL; 1428:Src/main.c **** HAL_GPIO_Init(USB_FLAG_GPIO_Port, &GPIO_InitStruct); 1429:Src/main.c **** 1430:Src/main.c **** /*Configure GPIO pin : SDMMC1_EN_Pin */ 1431:Src/main.c **** GPIO_InitStruct.Pin = SDMMC1_EN_Pin; 1432:Src/main.c **** GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 1433:Src/main.c **** GPIO_InitStruct.Pull = GPIO_NOPULL; 1434:Src/main.c **** HAL_GPIO_Init(SDMMC1_EN_GPIO_Port, &GPIO_InitStruct); 1435:Src/main.c **** 1436:Src/main.c **** /*Configure GPIO pin : FPGA_CONF_DONE_Pin */ 1437:Src/main.c **** GPIO_InitStruct.Pin = FPGA_CONF_DONE_Pin; 1438:Src/main.c **** GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 1439:Src/main.c **** GPIO_InitStruct.Pull = GPIO_NOPULL; 1440:Src/main.c **** HAL_GPIO_Init(FPGA_CONF_DONE_GPIO_Port, &GPIO_InitStruct); 1441:Src/main.c **** 1442:Src/main.c **** /* USER CODE BEGIN MX_GPIO_Init_2 */ 1443:Src/main.c **** /* USER CODE END MX_GPIO_Init_2 */ 1444:Src/main.c **** } ARM GAS /tmp/ccdsDELB.s page 73 1445:Src/main.c **** 1446:Src/main.c **** /* USER CODE BEGIN 4 */ 1447:Src/main.c **** 1448:Src/main.c **** //void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart) { 1449:Src/main.c **** 1450:Src/main.c **** // UART_transmission_request = NO_MESS; 1451:Src/main.c **** 1452:Src/main.c **** //} 1453:Src/main.c **** 1454:Src/main.c **** static void Init_params(void) 1455:Src/main.c **** { 1456:Src/main.c **** TO6 = 0; 1457:Src/main.c **** TO7 = 0; 1458:Src/main.c **** TO7_before = 0; 1459:Src/main.c **** TO6_before = 0; 1460:Src/main.c **** TO6_uart = 0; 1461:Src/main.c **** flg_tmt = 0; 1462:Src/main.c **** UART_rec_incr = 0; 1463:Src/main.c **** fgoto = 0; 1464:Src/main.c **** sizeoffile = 0; 1465:Src/main.c **** u_tx_flg = 0; 1466:Src/main.c **** u_rx_flg = 0; 1467:Src/main.c **** //State_Data[0]=0; 1468:Src/main.c **** //State_Data[1]=0;//All OK! 1469:Src/main.c **** for (uint16_t i=0; iWORK_EN = ((uint8_t)((*temp2)>>0))&0x01; 1621:Src/main.c **** Curr_setup->U5V1_EN = ((uint8_t)((*temp2)>>1))&0x01; 1622:Src/main.c **** Curr_setup->U5V2_EN = ((uint8_t)((*temp2)>>2))&0x01; 1623:Src/main.c **** Curr_setup->LD1_EN = ((uint8_t)((*temp2)>>3))&0x01; 1624:Src/main.c **** Curr_setup->LD2_EN = ((uint8_t)((*temp2)>>4))&0x01; 1625:Src/main.c **** Curr_setup->REF1_EN = ((uint8_t)((*temp2)>>5))&0x01; 1626:Src/main.c **** Curr_setup->REF2_EN = ((uint8_t)((*temp2)>>6))&0x01; 1627:Src/main.c **** Curr_setup->TEC1_EN = ((uint8_t)((*temp2)>>7))&0x01; 1628:Src/main.c **** Curr_setup->TEC2_EN = ((uint8_t)((*temp2)>>8))&0x01; 1629:Src/main.c **** Curr_setup->TS1_EN = ((uint8_t)((*temp2)>>9))&0x01; 1630:Src/main.c **** Curr_setup->TS2_EN = ((uint8_t)((*temp2)>>10))&0x01; 1631:Src/main.c **** Curr_setup->SD_EN = ((uint8_t)((*temp2)>>11))&0x01; 1632:Src/main.c **** Curr_setup->PI1_RD = ((uint8_t)((*temp2)>>12))&0x01; 1633:Src/main.c **** Curr_setup->PI2_RD = ((uint8_t)((*temp2)>>13))&0x01; 1634:Src/main.c **** 1635:Src/main.c **** temp2++; 1636:Src/main.c **** LD1_curr_setup->LD_TEMP = (uint16_t)(*temp2); 1637:Src/main.c **** temp2++; 1638:Src/main.c **** LD2_curr_setup->LD_TEMP = (uint16_t)(*temp2); 1639:Src/main.c **** temp2++; 1640:Src/main.c **** temp2++; 1641:Src/main.c **** temp2++; 1642:Src/main.c **** Curr_setup->AVERAGES = (uint16_t)(*temp2); 1643:Src/main.c **** temp2++; 1644:Src/main.c **** LD1_curr_setup->P_coef_temp = (float)((uint16_t)(*temp2))/((float)(256));//(float)(1/(float)((uint 1645:Src/main.c **** temp2++; 1646:Src/main.c **** LD1_curr_setup->I_coef_temp = (float)((uint16_t)(*temp2))/((float)(256));//(float)(1/(float)((uint 1647:Src/main.c **** temp2++; 1648:Src/main.c **** LD2_curr_setup->P_coef_temp = (float)((uint16_t)(*temp2))/((float)(256));//(float)(1/(float)((uint 1649:Src/main.c **** temp2++; 1650:Src/main.c **** LD2_curr_setup->I_coef_temp = (float)((uint16_t)(*temp2))/((float)(256));//(float)(1/(float)((uint 1651:Src/main.c **** temp2++; 1652:Src/main.c **** Long_Data[13] = (uint16_t)(*temp2);//Message ID 1653:Src/main.c **** temp2++; 1654:Src/main.c **** LD1_curr_setup->CURRENT = (uint16_t)(*temp2); 1655:Src/main.c **** temp2++; 1656:Src/main.c **** LD2_curr_setup->CURRENT = (uint16_t)(*temp2); 1657:Src/main.c **** temp2++; 1658:Src/main.c **** 1659:Src/main.c **** if (Curr_setup->U5V1_EN) 1660:Src/main.c **** { 1661:Src/main.c **** HAL_GPIO_WritePin(EN_5V1_GPIO_Port, EN_5V1_Pin, GPIO_PIN_SET); 1662:Src/main.c **** } 1663:Src/main.c **** else 1664:Src/main.c **** { 1665:Src/main.c **** HAL_GPIO_WritePin(EN_5V1_GPIO_Port, EN_5V1_Pin, GPIO_PIN_RESET); 1666:Src/main.c **** } 1667:Src/main.c **** 1668:Src/main.c **** if (Curr_setup->U5V2_EN) 1669:Src/main.c **** { 1670:Src/main.c **** HAL_GPIO_WritePin(EN_5V2_GPIO_Port, EN_5V2_Pin, GPIO_PIN_SET); 1671:Src/main.c **** } 1672:Src/main.c **** else ARM GAS /tmp/ccdsDELB.s page 77 1673:Src/main.c **** { 1674:Src/main.c **** HAL_GPIO_WritePin(EN_5V2_GPIO_Port, EN_5V2_Pin, GPIO_PIN_RESET); 1675:Src/main.c **** } 1676:Src/main.c **** 1677:Src/main.c **** if (Curr_setup->LD1_EN) 1678:Src/main.c **** { 1679:Src/main.c **** HAL_GPIO_WritePin(LD1_EN_GPIO_Port, LD1_EN_Pin, GPIO_PIN_SET); 1680:Src/main.c **** //LL_SPI_Enable(SPI2);//Enable SPI for Laser1 DAC 1681:Src/main.c **** } 1682:Src/main.c **** else 1683:Src/main.c **** { 1684:Src/main.c **** HAL_GPIO_WritePin(LD1_EN_GPIO_Port, LD1_EN_Pin, GPIO_PIN_RESET); 1685:Src/main.c **** //LL_SPI_Disable(SPI2);//Disable SPI for Laser1 DAC 1686:Src/main.c **** } 1687:Src/main.c **** 1688:Src/main.c **** if (Curr_setup->LD2_EN) 1689:Src/main.c **** { 1690:Src/main.c **** HAL_GPIO_WritePin(LD2_EN_GPIO_Port, LD2_EN_Pin, GPIO_PIN_SET); 1691:Src/main.c **** //LL_SPI_Enable(SPI6);//Enable SPI for Laser2 DAC 1692:Src/main.c **** } 1693:Src/main.c **** else 1694:Src/main.c **** { 1695:Src/main.c **** HAL_GPIO_WritePin(LD2_EN_GPIO_Port, LD2_EN_Pin, GPIO_PIN_RESET); 1696:Src/main.c **** //LL_SPI_Disable(SPI6);//Disable SPI for Laser2 DAC 1697:Src/main.c **** } 1698:Src/main.c **** 1699:Src/main.c **** if (Curr_setup->REF1_EN) 1700:Src/main.c **** { 1701:Src/main.c **** HAL_GPIO_WritePin(REF0_EN_GPIO_Port, REF0_EN_Pin, GPIO_PIN_SET); 1702:Src/main.c **** } 1703:Src/main.c **** else 1704:Src/main.c **** { 1705:Src/main.c **** HAL_GPIO_WritePin(REF0_EN_GPIO_Port, REF0_EN_Pin, GPIO_PIN_RESET); 1706:Src/main.c **** } 1707:Src/main.c **** 1708:Src/main.c **** if (Curr_setup->REF2_EN) 1709:Src/main.c **** { 1710:Src/main.c **** HAL_GPIO_WritePin(REF2_ON_GPIO_Port, REF2_ON_Pin, GPIO_PIN_SET); 1711:Src/main.c **** } 1712:Src/main.c **** else 1713:Src/main.c **** { 1714:Src/main.c **** HAL_GPIO_WritePin(REF2_ON_GPIO_Port, REF2_ON_Pin, GPIO_PIN_RESET); 1715:Src/main.c **** } 1716:Src/main.c **** 1717:Src/main.c **** if ((Curr_setup->TS1_EN)&&(Curr_setup->TEC1_EN)) 1718:Src/main.c **** { 1719:Src/main.c **** Set_LTEC(3,32767); 1720:Src/main.c **** Set_LTEC(3,32767); 1721:Src/main.c **** HAL_GPIO_WritePin(TEC1_PD_GPIO_Port, TEC1_PD_Pin, GPIO_PIN_SET); 1722:Src/main.c **** HAL_GPIO_WritePin(TECEN1_GPIO_Port, TECEN1_Pin, GPIO_PIN_SET); 1723:Src/main.c **** } 1724:Src/main.c **** else 1725:Src/main.c **** { 1726:Src/main.c **** HAL_GPIO_WritePin(TECEN1_GPIO_Port, TECEN1_Pin, GPIO_PIN_RESET); 1727:Src/main.c **** HAL_GPIO_WritePin(TEC1_PD_GPIO_Port, TEC1_PD_Pin, GPIO_PIN_RESET); 1728:Src/main.c **** } 1729:Src/main.c **** ARM GAS /tmp/ccdsDELB.s page 78 1730:Src/main.c **** if ((Curr_setup->TS2_EN)&&(Curr_setup->TEC2_EN)) 1731:Src/main.c **** { 1732:Src/main.c **** Set_LTEC(4,32767); 1733:Src/main.c **** Set_LTEC(4,32767); 1734:Src/main.c **** HAL_GPIO_WritePin(TEC2_PD_GPIO_Port, TEC2_PD_Pin, GPIO_PIN_SET); 1735:Src/main.c **** HAL_GPIO_WritePin(TECEN2_GPIO_Port, TECEN2_Pin, GPIO_PIN_SET); 1736:Src/main.c **** } 1737:Src/main.c **** else 1738:Src/main.c **** { 1739:Src/main.c **** HAL_GPIO_WritePin(TECEN2_GPIO_Port, TECEN2_Pin, GPIO_PIN_RESET); 1740:Src/main.c **** HAL_GPIO_WritePin(TEC2_PD_GPIO_Port, TEC2_PD_Pin, GPIO_PIN_RESET); 1741:Src/main.c **** } 1742:Src/main.c **** 1743:Src/main.c **** if (Curr_setup->PI1_RD==0) 1744:Src/main.c **** { 1745:Src/main.c **** LD1_curr_setup->P_coef_temp = 10; 1746:Src/main.c **** LD1_curr_setup->I_coef_temp = 0.01; 1747:Src/main.c **** } 1748:Src/main.c **** 1749:Src/main.c **** if (Curr_setup->PI2_RD==0) 1750:Src/main.c **** { 1751:Src/main.c **** LD2_curr_setup->P_coef_temp = 10; 1752:Src/main.c **** LD2_curr_setup->I_coef_temp = 0.01; 1753:Src/main.c **** } 1754:Src/main.c **** } 1755:Src/main.c **** 1756:Src/main.c **** static void Decode_task(uint16_t *Command, LDx_SetupTypeDef *LD1_curr_setup, LDx_SetupTypeDef *LD2_ 1757:Src/main.c **** { 253 .loc 2 1757 1 is_stmt 1 view -0 254 .cfi_startproc 255 @ args = 0, pretend = 0, frame = 8 256 @ frame_needed = 0, uses_anonymous_args = 0 257 @ link register save eliminated. 258 .loc 2 1757 1 is_stmt 0 view .LVU66 259 0000 82B0 sub sp, sp, #8 260 .LCFI3: 261 .cfi_def_cfa_offset 8 1758:Src/main.c **** uint16_t *temp2; 262 .loc 2 1758 2 is_stmt 1 view .LVU67 1759:Src/main.c **** 1760:Src/main.c **** temp2 = (uint16_t *)Command; 263 .loc 2 1760 2 view .LVU68 264 .LVL15: 1761:Src/main.c **** Curr_setup->WORK_EN = ((uint8_t)((*temp2)>>0))&0x01; 265 .loc 2 1761 2 view .LVU69 266 .loc 2 1761 36 is_stmt 0 view .LVU70 267 0002 0288 ldrh r2, [r0] 268 .LVL16: 269 .loc 2 1761 48 view .LVU71 270 0004 02F00102 and r2, r2, #1 271 .loc 2 1761 22 view .LVU72 272 0008 1A70 strb r2, [r3] 1762:Src/main.c **** Curr_setup->U5V1_EN = ((uint8_t)((*temp2)>>1))&0x01; 273 .loc 2 1762 2 is_stmt 1 view .LVU73 274 .loc 2 1762 36 is_stmt 0 view .LVU74 275 000a 0288 ldrh r2, [r0] 276 .loc 2 1762 48 view .LVU75 ARM GAS /tmp/ccdsDELB.s page 79 277 000c C2F34002 ubfx r2, r2, #1, #1 278 .loc 2 1762 22 view .LVU76 279 0010 5A70 strb r2, [r3, #1] 1763:Src/main.c **** Curr_setup->U5V2_EN = ((uint8_t)((*temp2)>>2))&0x01; 280 .loc 2 1763 2 is_stmt 1 view .LVU77 281 .loc 2 1763 36 is_stmt 0 view .LVU78 282 0012 0288 ldrh r2, [r0] 283 .loc 2 1763 48 view .LVU79 284 0014 C2F38002 ubfx r2, r2, #2, #1 285 .loc 2 1763 22 view .LVU80 286 0018 9A70 strb r2, [r3, #2] 1764:Src/main.c **** Curr_setup->LD1_EN = ((uint8_t)((*temp2)>>3))&0x01; 287 .loc 2 1764 2 is_stmt 1 view .LVU81 288 .loc 2 1764 35 is_stmt 0 view .LVU82 289 001a 0288 ldrh r2, [r0] 290 .loc 2 1764 47 view .LVU83 291 001c C2F3C002 ubfx r2, r2, #3, #1 292 .loc 2 1764 21 view .LVU84 293 0020 DA70 strb r2, [r3, #3] 1765:Src/main.c **** Curr_setup->LD2_EN = ((uint8_t)((*temp2)>>4))&0x01; 294 .loc 2 1765 2 is_stmt 1 view .LVU85 295 .loc 2 1765 35 is_stmt 0 view .LVU86 296 0022 0288 ldrh r2, [r0] 297 .loc 2 1765 47 view .LVU87 298 0024 C2F30012 ubfx r2, r2, #4, #1 299 .loc 2 1765 21 view .LVU88 300 0028 1A71 strb r2, [r3, #4] 1766:Src/main.c **** Curr_setup->REF1_EN = ((uint8_t)((*temp2)>>5))&0x01; 301 .loc 2 1766 2 is_stmt 1 view .LVU89 302 .loc 2 1766 36 is_stmt 0 view .LVU90 303 002a 0288 ldrh r2, [r0] 304 .loc 2 1766 48 view .LVU91 305 002c C2F34012 ubfx r2, r2, #5, #1 306 .loc 2 1766 22 view .LVU92 307 0030 5A71 strb r2, [r3, #5] 1767:Src/main.c **** Curr_setup->REF2_EN = ((uint8_t)((*temp2)>>6))&0x01; 308 .loc 2 1767 2 is_stmt 1 view .LVU93 309 .loc 2 1767 36 is_stmt 0 view .LVU94 310 0032 0288 ldrh r2, [r0] 311 .loc 2 1767 48 view .LVU95 312 0034 C2F38012 ubfx r2, r2, #6, #1 313 .loc 2 1767 22 view .LVU96 314 0038 9A71 strb r2, [r3, #6] 1768:Src/main.c **** Curr_setup->TEC1_EN = ((uint8_t)((*temp2)>>7))&0x01; 315 .loc 2 1768 2 is_stmt 1 view .LVU97 316 .loc 2 1768 36 is_stmt 0 view .LVU98 317 003a 0288 ldrh r2, [r0] 318 .loc 2 1768 48 view .LVU99 319 003c C2F3C012 ubfx r2, r2, #7, #1 320 .loc 2 1768 22 view .LVU100 321 0040 DA71 strb r2, [r3, #7] 1769:Src/main.c **** Curr_setup->TEC2_EN = ((uint8_t)((*temp2)>>8))&0x01; 322 .loc 2 1769 2 is_stmt 1 view .LVU101 323 .loc 2 1769 36 is_stmt 0 view .LVU102 324 0042 0288 ldrh r2, [r0] 325 .loc 2 1769 48 view .LVU103 326 0044 C2F30022 ubfx r2, r2, #8, #1 ARM GAS /tmp/ccdsDELB.s page 80 327 .loc 2 1769 22 view .LVU104 328 0048 1A72 strb r2, [r3, #8] 1770:Src/main.c **** Curr_setup->TS1_EN = ((uint8_t)((*temp2)>>9))&0x01; 329 .loc 2 1770 2 is_stmt 1 view .LVU105 330 .loc 2 1770 35 is_stmt 0 view .LVU106 331 004a 0288 ldrh r2, [r0] 332 .loc 2 1770 47 view .LVU107 333 004c C2F34022 ubfx r2, r2, #9, #1 334 .loc 2 1770 21 view .LVU108 335 0050 5A72 strb r2, [r3, #9] 1771:Src/main.c **** Curr_setup->TS2_EN = ((uint8_t)((*temp2)>>10))&0x01; 336 .loc 2 1771 2 is_stmt 1 view .LVU109 337 .loc 2 1771 35 is_stmt 0 view .LVU110 338 0052 0288 ldrh r2, [r0] 339 .loc 2 1771 48 view .LVU111 340 0054 C2F38022 ubfx r2, r2, #10, #1 341 .loc 2 1771 21 view .LVU112 342 0058 9A72 strb r2, [r3, #10] 1772:Src/main.c **** Curr_setup->SD_EN = ((uint8_t)((*temp2)>>11))&0x01; 343 .loc 2 1772 2 is_stmt 1 view .LVU113 344 .loc 2 1772 34 is_stmt 0 view .LVU114 345 005a 0288 ldrh r2, [r0] 346 .loc 2 1772 47 view .LVU115 347 005c C2F3C022 ubfx r2, r2, #11, #1 348 .loc 2 1772 20 view .LVU116 349 0060 DA72 strb r2, [r3, #11] 1773:Src/main.c **** Curr_setup->PI1_RD = ((uint8_t)((*temp2)>>12))&0x01; 350 .loc 2 1773 2 is_stmt 1 view .LVU117 351 .loc 2 1773 35 is_stmt 0 view .LVU118 352 0062 0288 ldrh r2, [r0] 353 .loc 2 1773 48 view .LVU119 354 0064 C2F30032 ubfx r2, r2, #12, #1 355 .loc 2 1773 21 view .LVU120 356 0068 1A73 strb r2, [r3, #12] 1774:Src/main.c **** Curr_setup->PI2_RD = ((uint8_t)((*temp2)>>13))&0x01; 357 .loc 2 1774 2 is_stmt 1 view .LVU121 358 .loc 2 1774 35 is_stmt 0 view .LVU122 359 006a 0288 ldrh r2, [r0] 360 .loc 2 1774 48 view .LVU123 361 006c C2F34032 ubfx r2, r2, #13, #1 362 .loc 2 1774 21 view .LVU124 363 0070 5A73 strb r2, [r3, #13] 1775:Src/main.c **** 1776:Src/main.c **** temp2++; 364 .loc 2 1776 2 is_stmt 1 view .LVU125 365 .LVL17: 1777:Src/main.c **** task.task_type = (uint8_t)(*temp2); temp2++; 366 .loc 2 1777 2 view .LVU126 367 .loc 2 1777 21 is_stmt 0 view .LVU127 368 0072 8278 ldrb r2, [r0, #2] @ zero_extendqisi2 369 .loc 2 1777 19 view .LVU128 370 0074 384B ldr r3, .L13+8 371 .LVL18: 372 .loc 2 1777 19 view .LVU129 373 0076 1A70 strb r2, [r3] 374 .loc 2 1777 40 is_stmt 1 view .LVU130 375 .LVL19: ARM GAS /tmp/ccdsDELB.s page 81 1778:Src/main.c **** task.min_param = (float)(*temp2); temp2++; 376 .loc 2 1778 2 view .LVU131 377 .loc 2 1778 29 is_stmt 0 view .LVU132 378 0078 8288 ldrh r2, [r0, #4] 379 007a 07EE902A vmov s15, r2 @ int 380 .loc 2 1778 21 view .LVU133 381 007e F8EE677A vcvt.f32.u32 s15, s15 382 .loc 2 1778 19 view .LVU134 383 0082 C3ED017A vstr.32 s15, [r3, #4] 384 .loc 2 1778 38 is_stmt 1 view .LVU135 385 .LVL20: 1779:Src/main.c **** task.max_param = (float)(*temp2); temp2++; 386 .loc 2 1779 2 view .LVU136 387 .loc 2 1779 29 is_stmt 0 view .LVU137 388 0086 C288 ldrh r2, [r0, #6] 389 0088 07EE902A vmov s15, r2 @ int 390 .loc 2 1779 21 view .LVU138 391 008c F8EE677A vcvt.f32.u32 s15, s15 392 .loc 2 1779 19 view .LVU139 393 0090 C3ED027A vstr.32 s15, [r3, #8] 394 .loc 2 1779 38 is_stmt 1 view .LVU140 395 .LVL21: 1780:Src/main.c **** task.delta_param = (float)(*temp2); temp2++; 396 .loc 2 1780 2 view .LVU141 397 .loc 2 1780 29 is_stmt 0 view .LVU142 398 0094 0289 ldrh r2, [r0, #8] 399 0096 07EE902A vmov s15, r2 @ int 400 .loc 2 1780 21 view .LVU143 401 009a F8EE677A vcvt.f32.u32 s15, s15 402 .loc 2 1780 19 view .LVU144 403 009e C3ED037A vstr.32 s15, [r3, #12] 404 .loc 2 1780 38 is_stmt 1 view .LVU145 405 .LVL22: 1781:Src/main.c **** task.dt = (float)(*temp2) / 100.0; temp2++; 406 .loc 2 1781 2 view .LVU146 407 .loc 2 1781 29 is_stmt 0 view .LVU147 408 00a2 4289 ldrh r2, [r0, #10] 409 00a4 07EE102A vmov s14, r2 @ int 410 .loc 2 1781 21 view .LVU148 411 00a8 B8EE477B vcvt.f64.u32 d7, s14 412 .loc 2 1781 37 view .LVU149 413 00ac 9FED285B vldr.64 d5, .L13 414 00b0 87EE056B vdiv.f64 d6, d7, d5 415 .loc 2 1781 19 view .LVU150 416 00b4 FCEEC67B vcvt.u32.f64 s15, d6 417 00b8 CDED017A vstr.32 s15, [sp, #4] @ int 418 00bc 9DF80420 ldrb r2, [sp, #4] @ zero_extendqisi2 419 00c0 1A75 strb r2, [r3, #20] 420 .loc 2 1781 46 is_stmt 1 view .LVU151 421 .LVL23: 1782:Src/main.c **** task.sec_param = (float)(*temp2); temp2++; 422 .loc 2 1782 2 view .LVU152 423 .loc 2 1782 29 is_stmt 0 view .LVU153 424 00c2 8189 ldrh r1, [r0, #12] 425 .LVL24: 426 .loc 2 1782 29 view .LVU154 427 00c4 07EE901A vmov s15, r1 @ int ARM GAS /tmp/ccdsDELB.s page 82 428 .loc 2 1782 21 view .LVU155 429 00c8 F8EE677A vcvt.f32.u32 s15, s15 430 .loc 2 1782 19 view .LVU156 431 00cc C3ED067A vstr.32 s15, [r3, #24] 432 .loc 2 1782 38 is_stmt 1 view .LVU157 433 .LVL25: 1783:Src/main.c **** task.curr = (float)(*temp2); temp2++; 434 .loc 2 1783 2 view .LVU158 435 .loc 2 1783 29 is_stmt 0 view .LVU159 436 00d0 C189 ldrh r1, [r0, #14] 437 00d2 07EE901A vmov s15, r1 @ int 438 .loc 2 1783 21 view .LVU160 439 00d6 F8EE677A vcvt.f32.u32 s15, s15 440 .loc 2 1783 19 view .LVU161 441 00da C3ED077A vstr.32 s15, [r3, #28] 442 .loc 2 1783 38 is_stmt 1 view .LVU162 443 .LVL26: 1784:Src/main.c **** task.temp = (float)(*temp2); temp2++; 444 .loc 2 1784 2 view .LVU163 445 .loc 2 1784 29 is_stmt 0 view .LVU164 446 00de 018A ldrh r1, [r0, #16] 447 00e0 07EE901A vmov s15, r1 @ int 448 .loc 2 1784 21 view .LVU165 449 00e4 F8EE677A vcvt.f32.u32 s15, s15 450 .loc 2 1784 19 view .LVU166 451 00e8 C3ED087A vstr.32 s15, [r3, #32] 452 .loc 2 1784 38 is_stmt 1 view .LVU167 453 .LVL27: 1785:Src/main.c **** task.tau = (float)(*temp2); temp2++; 454 .loc 2 1785 2 view .LVU168 455 .loc 2 1785 29 is_stmt 0 view .LVU169 456 00ec 418A ldrh r1, [r0, #18] 457 .loc 2 1785 19 view .LVU170 458 00ee D982 strh r1, [r3, #22] @ movhi 459 .loc 2 1785 38 is_stmt 1 view .LVU171 460 .LVL28: 1786:Src/main.c **** task.p_coef_1 = (float)(*temp2) * 256.0; temp2++; 461 .loc 2 1786 2 view .LVU172 462 .loc 2 1786 29 is_stmt 0 view .LVU173 463 00f0 818A ldrh r1, [r0, #20] 464 00f2 07EE101A vmov s14, r1 @ int 465 .loc 2 1786 21 view .LVU174 466 00f6 B8EE477A vcvt.f32.u32 s14, s14 467 .loc 2 1786 37 view .LVU175 468 00fa DFED186A vldr.32 s13, .L13+12 469 00fe 27EE267A vmul.f32 s14, s14, s13 470 .loc 2 1786 19 view .LVU176 471 0102 83ED0A7A vstr.32 s14, [r3, #40] 472 .loc 2 1786 46 is_stmt 1 view .LVU177 473 .LVL29: 1787:Src/main.c **** task.i_coef_1 = (float)(*temp2) * 256.0; temp2++; 474 .loc 2 1787 2 view .LVU178 475 .loc 2 1787 29 is_stmt 0 view .LVU179 476 0106 C18A ldrh r1, [r0, #22] 477 0108 07EE101A vmov s14, r1 @ int 478 .loc 2 1787 21 view .LVU180 479 010c B8EE477A vcvt.f32.u32 s14, s14 ARM GAS /tmp/ccdsDELB.s page 83 480 .loc 2 1787 37 view .LVU181 481 0110 27EE267A vmul.f32 s14, s14, s13 482 .loc 2 1787 19 view .LVU182 483 0114 83ED097A vstr.32 s14, [r3, #36] 484 .loc 2 1787 46 is_stmt 1 view .LVU183 485 .LVL30: 1788:Src/main.c **** task.p_coef_2 = (float)(*temp2) * 256.0; temp2++; 486 .loc 2 1788 2 view .LVU184 487 .loc 2 1788 29 is_stmt 0 view .LVU185 488 0118 018B ldrh r1, [r0, #24] 489 011a 07EE101A vmov s14, r1 @ int 490 .loc 2 1788 21 view .LVU186 491 011e B8EE477A vcvt.f32.u32 s14, s14 492 .loc 2 1788 37 view .LVU187 493 0122 27EE267A vmul.f32 s14, s14, s13 494 .loc 2 1788 19 view .LVU188 495 0126 83ED0C7A vstr.32 s14, [r3, #48] 496 .loc 2 1788 46 is_stmt 1 view .LVU189 497 .LVL31: 1789:Src/main.c **** task.i_coef_2 = (float)(*temp2) * 256.0; temp2++; 498 .loc 2 1789 2 view .LVU190 499 .loc 2 1789 29 is_stmt 0 view .LVU191 500 012a 418B ldrh r1, [r0, #26] 501 012c 07EE901A vmov s15, r1 @ int 502 .loc 2 1789 21 view .LVU192 503 0130 F8EE677A vcvt.f32.u32 s15, s15 504 .loc 2 1789 37 view .LVU193 505 0134 67EEA67A vmul.f32 s15, s15, s13 506 .loc 2 1789 19 view .LVU194 507 0138 C3ED0B7A vstr.32 s15, [r3, #44] 508 .loc 2 1789 46 is_stmt 1 view .LVU195 509 .LVL32: 1790:Src/main.c **** 1791:Src/main.c **** TO10_counter = task.dt / 10 - 1; 510 .loc 2 1791 2 view .LVU196 511 .loc 2 1791 25 is_stmt 0 view .LVU197 512 013c 084B ldr r3, .L13+16 513 013e A3FB0232 umull r3, r2, r3, r2 514 0142 D208 lsrs r2, r2, #3 515 .loc 2 1791 30 view .LVU198 516 0144 013A subs r2, r2, #1 517 .loc 2 1791 15 view .LVU199 518 0146 074B ldr r3, .L13+20 519 0148 1A60 str r2, [r3] 1792:Src/main.c **** } 520 .loc 2 1792 1 view .LVU200 521 014a 02B0 add sp, sp, #8 522 .LCFI4: 523 .cfi_def_cfa_offset 0 524 @ sp needed 525 014c 7047 bx lr 526 .L14: 527 014e 00BF .align 3 528 .L13: 529 0150 00000000 .word 0 530 0154 00005940 .word 1079574528 531 0158 00000000 .word .LANCHOR1 ARM GAS /tmp/ccdsDELB.s page 84 532 015c 00008043 .word 1132462080 533 0160 CDCCCCCC .word -858993459 534 0164 00000000 .word .LANCHOR2 535 .cfi_endproc 536 .LFE1205: 538 .section .text.PID_Controller_Temp,"ax",%progbits 539 .align 1 540 .syntax unified 541 .thumb 542 .thumb_func 543 .fpu fpv5-d16 545 PID_Controller_Temp: 546 .LVL33: 547 .LFB1209: 1793:Src/main.c **** 1794:Src/main.c **** void Set_LTEC(uint8_t num, uint16_t DATA) 1795:Src/main.c **** { 1796:Src/main.c **** uint32_t tmp32; 1797:Src/main.c **** switch (num) 1798:Src/main.c **** { 1799:Src/main.c **** case 1: 1800:Src/main.c **** HAL_GPIO_WritePin(DAC_LD1_CS_GPIO_Port, DAC_LD1_CS_Pin, GPIO_PIN_RESET);//Start operation with L 1801:Src/main.c **** //tmp32=0; 1802:Src/main.c **** //while(tmp32<500){tmp32++;} 1803:Src/main.c **** tmp32 = 0; 1804:Src/main.c **** while((!LL_SPI_IsActiveFlag_TXE(SPI2))&&(tmp32<=500)) {tmp32++;}//When trans. last data cycle wi 1805:Src/main.c **** LL_SPI_TransmitData16(SPI2, DATA);//Transmit word to Laser1 DAC 1806:Src/main.c **** tmp32 = 0; 1807:Src/main.c **** while((!LL_SPI_IsActiveFlag_RXNE(SPI2))&&(tmp32<=500)) {tmp32++;}//When trans. last data cycle w 1808:Src/main.c **** (void) SPI2->DR; 1809:Src/main.c **** break; 1810:Src/main.c **** case 2: 1811:Src/main.c **** HAL_GPIO_WritePin(DAC_LD2_CS_GPIO_Port, DAC_LD2_CS_Pin, GPIO_PIN_RESET);//Start operation with L 1812:Src/main.c **** //tmp32=0; 1813:Src/main.c **** //while(tmp32<500){tmp32++;} 1814:Src/main.c **** tmp32 = 0; 1815:Src/main.c **** while((!LL_SPI_IsActiveFlag_TXE(SPI6))&&(tmp32<=500)) {tmp32++;}//When trans. last data cycle wi 1816:Src/main.c **** LL_SPI_TransmitData16(SPI6, DATA);//Transmit word to Laser1 DAC 1817:Src/main.c **** tmp32 = 0; 1818:Src/main.c **** while((!LL_SPI_IsActiveFlag_RXNE(SPI6))&&(tmp32<=500)) {tmp32++;}//When trans. last data cycle w 1819:Src/main.c **** (void) SPI6->DR; 1820:Src/main.c **** break; 1821:Src/main.c **** case 3: 1822:Src/main.c **** HAL_GPIO_WritePin(DAC_TEC1_CS_GPIO_Port, DAC_TEC1_CS_Pin, GPIO_PIN_RESET);//Start operation with 1823:Src/main.c **** //tmp32=0; 1824:Src/main.c **** //while(tmp32<500){tmp32++;} 1825:Src/main.c **** tmp32 = 0; 1826:Src/main.c **** while((!LL_SPI_IsActiveFlag_TXE(SPI2))&&(tmp32<=500)) {tmp32++;}//When trans. last data cycle wi 1827:Src/main.c **** LL_SPI_TransmitData16(SPI2, DATA);//Transmit word to Laser1 DAC 1828:Src/main.c **** tmp32 = 0; 1829:Src/main.c **** while((!LL_SPI_IsActiveFlag_RXNE(SPI2))&&(tmp32<=500)) {tmp32++;}//When trans. last data cycle w 1830:Src/main.c **** (void) SPI2->DR; 1831:Src/main.c **** break; 1832:Src/main.c **** case 4: 1833:Src/main.c **** HAL_GPIO_WritePin(DAC_TEC2_CS_GPIO_Port, DAC_TEC2_CS_Pin, GPIO_PIN_RESET);//Start operation with 1834:Src/main.c **** //tmp32=0; 1835:Src/main.c **** //while(tmp32<500){tmp32++;} ARM GAS /tmp/ccdsDELB.s page 85 1836:Src/main.c **** tmp32 = 0; 1837:Src/main.c **** while((!LL_SPI_IsActiveFlag_TXE(SPI6))&&(tmp32<=500)) {tmp32++;}//When trans. last data cycle wi 1838:Src/main.c **** LL_SPI_TransmitData16(SPI6, DATA);//Transmit word to Laser1 DAC 1839:Src/main.c **** tmp32 = 0; 1840:Src/main.c **** while((!LL_SPI_IsActiveFlag_RXNE(SPI6))&&(tmp32<=500)) {tmp32++;}//When trans. last data cycle w 1841:Src/main.c **** (void) SPI6->DR; 1842:Src/main.c **** break; 1843:Src/main.c **** } 1844:Src/main.c **** HAL_GPIO_WritePin(DAC_LD1_CS_GPIO_Port, DAC_LD1_CS_Pin, GPIO_PIN_SET);//End operation with LDAC1 1845:Src/main.c **** HAL_GPIO_WritePin(DAC_LD2_CS_GPIO_Port, DAC_LD2_CS_Pin, GPIO_PIN_SET);//End operation with LDAC2 1846:Src/main.c **** HAL_GPIO_WritePin(DAC_TEC1_CS_GPIO_Port, DAC_TEC1_CS_Pin, GPIO_PIN_SET);//End operation with TEC1 1847:Src/main.c **** HAL_GPIO_WritePin(DAC_TEC2_CS_GPIO_Port, DAC_TEC2_CS_Pin, GPIO_PIN_SET);//End operation with TEC2 1848:Src/main.c **** } 1849:Src/main.c **** static uint16_t MPhD_T(uint8_t num) 1850:Src/main.c **** { 1851:Src/main.c **** uint16_t P; 1852:Src/main.c **** uint32_t tmp32; 1853:Src/main.c **** HAL_GPIO_WritePin(SPI4_CNV_GPIO_Port, SPI4_CNV_Pin, GPIO_PIN_RESET);//Prepare conversion 1854:Src/main.c **** HAL_GPIO_WritePin(SPI5_CNV_GPIO_Port, SPI5_CNV_Pin, GPIO_PIN_RESET);//Prepare conversion 1855:Src/main.c **** tmp32=0; 1856:Src/main.c **** while(tmp32<500){tmp32++;} 1857:Src/main.c **** HAL_GPIO_WritePin(SPI4_CNV_GPIO_Port, SPI4_CNV_Pin, GPIO_PIN_SET);//Stop acqusition & start conver 1858:Src/main.c **** HAL_GPIO_WritePin(SPI5_CNV_GPIO_Port, SPI5_CNV_Pin, GPIO_PIN_SET);//Stop acqusition & start conver 1859:Src/main.c **** tmp32=0; 1860:Src/main.c **** while(tmp32<500){tmp32++;} 1861:Src/main.c **** if (num==1)//MPD1 1862:Src/main.c **** { 1863:Src/main.c **** HAL_GPIO_WritePin(ADC_ThrLD1_CS_GPIO_Port, ADC_ThrLD1_CS_Pin, GPIO_PIN_SET); 1864:Src/main.c **** HAL_GPIO_WritePin(ADC_MPD1_CS_GPIO_Port, ADC_MPD1_CS_Pin, GPIO_PIN_RESET); 1865:Src/main.c **** tmp32=0; 1866:Src/main.c **** while(tmp32<500){tmp32++;} 1867:Src/main.c **** //LL_SPI_TransmitData16(SPI4, 0xFFFF);//We must to clock the CLK output for collect RX data. We c 1868:Src/main.c **** LL_SPI_Enable(SPI4);//Enable SPI for MPhD1 ADC 1869:Src/main.c **** tmp32 = 0; 1870:Src/main.c **** while(((!LL_SPI_IsActiveFlag_RXNE(SPI4))&&(tmp32<=1000))) {tmp32++;}//When rec. last data cycle w 1871:Src/main.c **** LL_SPI_Disable(SPI4);//Enable SPI for MPhD1 ADC 1872:Src/main.c **** while(tmp32<500){tmp32++;} 1873:Src/main.c **** //HAL_SPI_Receive(&hspi4, &P[0], 1, 100); 1874:Src/main.c **** HAL_GPIO_WritePin(ADC_MPD1_CS_GPIO_Port, ADC_MPD1_CS_Pin, GPIO_PIN_SET); 1875:Src/main.c **** P = LL_SPI_ReceiveData16(SPI4); 1876:Src/main.c **** } 1877:Src/main.c **** else if (num==2)//MPD2 1878:Src/main.c **** { 1879:Src/main.c **** HAL_GPIO_WritePin(ADC_ThrLD2_CS_GPIO_Port, ADC_ThrLD2_CS_Pin, GPIO_PIN_SET); 1880:Src/main.c **** HAL_GPIO_WritePin(ADC_MPD2_CS_GPIO_Port, ADC_MPD2_CS_Pin, GPIO_PIN_RESET); 1881:Src/main.c **** tmp32=0; 1882:Src/main.c **** while(tmp32<500){tmp32++;} 1883:Src/main.c **** //LL_SPI_TransmitData16(SPI5, 0xFFFF);//We must to clock the CLK output for collect RX data. We c 1884:Src/main.c **** LL_SPI_Enable(SPI5);//Enable SPI for MPhD2 ADC 1885:Src/main.c **** tmp32 = 0; 1886:Src/main.c **** while(((!LL_SPI_IsActiveFlag_RXNE(SPI5))&&(tmp32<=1000))) {tmp32++;}//When rec. last data cycle w 1887:Src/main.c **** LL_SPI_Disable(SPI5);//Enable SPI for MPhD2 ADC 1888:Src/main.c **** while(tmp32<500){tmp32++;} 1889:Src/main.c **** //HAL_SPI_Receive(&hspi4, &P[0], 1, 100); 1890:Src/main.c **** HAL_GPIO_WritePin(ADC_MPD2_CS_GPIO_Port, ADC_MPD2_CS_Pin, GPIO_PIN_SET); 1891:Src/main.c **** P = LL_SPI_ReceiveData16(SPI5); 1892:Src/main.c **** } ARM GAS /tmp/ccdsDELB.s page 86 1893:Src/main.c **** else if (num==3)//ThrLD1 1894:Src/main.c **** { 1895:Src/main.c **** HAL_GPIO_WritePin(ADC_MPD1_CS_GPIO_Port, ADC_MPD1_CS_Pin, GPIO_PIN_SET); 1896:Src/main.c **** HAL_GPIO_WritePin(ADC_ThrLD1_CS_GPIO_Port, ADC_ThrLD1_CS_Pin, GPIO_PIN_RESET); 1897:Src/main.c **** tmp32=0; 1898:Src/main.c **** while(tmp32<500){tmp32++;} 1899:Src/main.c **** //LL_SPI_TransmitData16(SPI4, 0xFFFF);//We must to clock the CLK output for collect RX data. We c 1900:Src/main.c **** LL_SPI_Enable(SPI4);//Enable SPI for ThrLD1 ADC 1901:Src/main.c **** tmp32 = 0; 1902:Src/main.c **** while(((!LL_SPI_IsActiveFlag_RXNE(SPI4))&&(tmp32<=1000))) {tmp32++;}//When rec. last data cycle w 1903:Src/main.c **** LL_SPI_Disable(SPI4);//Enable SPI for ThrLD1 ADC 1904:Src/main.c **** while(tmp32<500){tmp32++;} 1905:Src/main.c **** //HAL_SPI_Receive(&hspi4, &P[0], 1, 100); 1906:Src/main.c **** HAL_GPIO_WritePin(ADC_ThrLD1_CS_GPIO_Port, ADC_ThrLD1_CS_Pin, GPIO_PIN_SET); 1907:Src/main.c **** P = LL_SPI_ReceiveData16(SPI4); 1908:Src/main.c **** } 1909:Src/main.c **** else if (num==4)//ThrLD2 1910:Src/main.c **** { 1911:Src/main.c **** HAL_GPIO_WritePin(ADC_MPD2_CS_GPIO_Port, ADC_MPD2_CS_Pin, GPIO_PIN_SET); 1912:Src/main.c **** HAL_GPIO_WritePin(ADC_ThrLD2_CS_GPIO_Port, ADC_ThrLD2_CS_Pin, GPIO_PIN_RESET); 1913:Src/main.c **** tmp32=0; 1914:Src/main.c **** while(tmp32<500){tmp32++;} 1915:Src/main.c **** //LL_SPI_TransmitData16(SPI5, 0xFFFF);//We must to clock the CLK output for collect RX data. We c 1916:Src/main.c **** LL_SPI_Enable(SPI5);//Enable SPI for ThrLD2 ADC 1917:Src/main.c **** tmp32 = 0; 1918:Src/main.c **** while(((!LL_SPI_IsActiveFlag_RXNE(SPI5))&&(tmp32<=1000))) {tmp32++;}//When rec. last data cycle w 1919:Src/main.c **** LL_SPI_Disable(SPI5);//Enable SPI for ThrLD2 ADC 1920:Src/main.c **** while(tmp32<500){tmp32++;} 1921:Src/main.c **** //HAL_SPI_Receive(&hspi4, &P[0], 1, 100); 1922:Src/main.c **** HAL_GPIO_WritePin(ADC_ThrLD2_CS_GPIO_Port, ADC_ThrLD2_CS_Pin, GPIO_PIN_SET); 1923:Src/main.c **** P = LL_SPI_ReceiveData16(SPI5); 1924:Src/main.c **** } 1925:Src/main.c **** /*float I_LD, Ith, I0m, T0m, Inorm, Tnorm1, Tnorm2, P, T_C, A, Pnorm; 1926:Src/main.c **** 1927:Src/main.c **** Inorm = (float) (65535) / (float) (100); 1928:Src/main.c **** Tnorm1 = (float) (65535) / (float) (50); 1929:Src/main.c **** Tnorm2 = 4; 1930:Src/main.c **** Pnorm = (float)(65535) / (float)(20); 1931:Src/main.c **** I0m = 8.1568;//@4 C - lowest temperature of system 1932:Src/main.c **** T0m = 48.6282; 1933:Src/main.c **** T_C = (float) (T_LD) / Tnorm1 + Tnorm2; 1934:Src/main.c **** 1935:Src/main.c **** Ith = I0m * expf(T_C/T0m); 1936:Src/main.c **** I_LD = (float) (C_LD) / Inorm; 1937:Src/main.c **** 1938:Src/main.c **** if (I_LD > Ith) 1939:Src/main.c **** { 1940:Src/main.c **** A = (float) (2.24276128270098e-07) * T_C * T_C * T_C - (float) (4.73392579025590e-05) * T_C * T_ 1941:Src/main.c **** P = A * (I_LD - Ith) * Pnorm; 1942:Src/main.c **** } 1943:Src/main.c **** else 1944:Src/main.c **** { 1945:Src/main.c **** P = 0; 1946:Src/main.c **** } */ 1947:Src/main.c **** return P; 1948:Src/main.c **** } 1949:Src/main.c **** /*static uint16_t Temp_LD(uint16_t T_LD_before, uint16_t T_LD, uint32_t Timer_before, uint32_t Time ARM GAS /tmp/ccdsDELB.s page 87 1950:Src/main.c **** { 1951:Src/main.c **** uint16_t Result; 1952:Src/main.c **** // uint8_t randf; 1953:Src/main.c **** 1954:Src/main.c **** randf = 0; 1955:Src/main.c **** for (uint8_t i = 0; i < 32; i++) 1956:Src/main.c **** { 1957:Src/main.c **** randf = ((Timer>>i)&0x0001)^randf; 1958:Src/main.c **** } 1959:Src/main.c **** 1960:Src/main.c **** Result = ((float)(T_LD - T_LD_before))*((float)(1-expf(((float)(Timer_before)-(float)(Timer))/((fl 1961:Src/main.c **** 1962:Src/main.c **** return (uint16_t)(Result); 1963:Src/main.c **** }*/ 1964:Src/main.c **** static uint16_t Get_ADC(uint8_t num) 1965:Src/main.c **** { 1966:Src/main.c **** uint16_t OUT; 1967:Src/main.c **** switch (num) 1968:Src/main.c **** { 1969:Src/main.c **** case 0: 1970:Src/main.c **** HAL_ADC_Start(&hadc1); // Power on 1971:Src/main.c **** break; 1972:Src/main.c **** case 1: 1973:Src/main.c **** HAL_ADC_PollForConversion(&hadc1, 100); // Waiting for conversion 1974:Src/main.c **** OUT = HAL_ADC_GetValue(&hadc1); // Get value adc 1975:Src/main.c **** break; 1976:Src/main.c **** case 2: 1977:Src/main.c **** HAL_ADC_Stop(&hadc1); // Power off 1978:Src/main.c **** break; 1979:Src/main.c **** case 3: 1980:Src/main.c **** HAL_ADC_Start(&hadc3); // Power on 1981:Src/main.c **** break; 1982:Src/main.c **** case 4: 1983:Src/main.c **** HAL_ADC_PollForConversion(&hadc3, 100); // Waiting for conversion 1984:Src/main.c **** OUT = HAL_ADC_GetValue(&hadc3); // Get value adc 1985:Src/main.c **** break; 1986:Src/main.c **** case 5: 1987:Src/main.c **** HAL_ADC_Stop(&hadc3); // Power off 1988:Src/main.c **** break; 1989:Src/main.c **** } 1990:Src/main.c **** return OUT; 1991:Src/main.c **** } 1992:Src/main.c **** uint16_t PID_Controller_Temp(LDx_SetupTypeDef * LDx_curr_setup, LDx_ParamTypeDef * LDx_results, uin 1993:Src/main.c **** { 548 .loc 2 1993 1 is_stmt 1 view -0 549 .cfi_startproc 550 @ args = 0, pretend = 0, frame = 0 551 @ frame_needed = 0, uses_anonymous_args = 0 552 @ link register save eliminated. 553 .loc 2 1993 1 is_stmt 0 view .LVU202 554 0000 30B4 push {r4, r5} 555 .LCFI5: 556 .cfi_def_cfa_offset 8 557 .cfi_offset 4, -8 558 .cfi_offset 5, -4 1994:Src/main.c **** int e_pid; 559 .loc 2 1994 2 is_stmt 1 view .LVU203 ARM GAS /tmp/ccdsDELB.s page 88 1995:Src/main.c **** float P_coef_current;//, I_coef_current; 560 .loc 2 1995 2 view .LVU204 1996:Src/main.c **** float e_integral; 561 .loc 2 1996 2 view .LVU205 1997:Src/main.c **** int x_output; 562 .loc 2 1997 2 view .LVU206 1998:Src/main.c **** 1999:Src/main.c **** e_pid = (int) LDx_results->LD_CURR_TEMP - (int) LDx_curr_setup->LD_TEMP; 563 .loc 2 1999 2 view .LVU207 564 .loc 2 1999 28 is_stmt 0 view .LVU208 565 0002 0B88 ldrh r3, [r1] 566 .loc 2 1999 65 view .LVU209 567 0004 0488 ldrh r4, [r0] 568 .loc 2 1999 8 view .LVU210 569 0006 1B1B subs r3, r3, r4 570 .LVL34: 2000:Src/main.c **** 2001:Src/main.c **** e_integral = LDx_results->e_integral; 571 .loc 2 2001 2 is_stmt 1 view .LVU211 572 .loc 2 2001 13 is_stmt 0 view .LVU212 573 0008 D1ED017A vldr.32 s15, [r1, #4] 574 .LVL35: 2002:Src/main.c **** 2003:Src/main.c **** if((e_pid < 3000) && (e_pid > - 3000)){ 575 .loc 2 2003 2 is_stmt 1 view .LVU213 576 .loc 2 2003 20 is_stmt 0 view .LVU214 577 000c 03F6B73C addw ip, r3, #2999 578 .loc 2 2003 4 view .LVU215 579 0010 41F26E74 movw r4, #5998 580 0014 A445 cmp ip, r4 581 0016 18D8 bhi .L16 2004:Src/main.c **** e_integral += LDx_curr_setup->I_coef_temp * (float)(e_pid) * (float)(TO7 - TO7_PID) / (float) 100 582 .loc 2 2004 3 is_stmt 1 view .LVU216 583 .loc 2 2004 31 is_stmt 0 view .LVU217 584 0018 90ED027A vldr.32 s14, [r0, #8] 585 .loc 2 2004 47 view .LVU218 586 001c 06EE903A vmov s13, r3 @ int 587 0020 F8EEE66A vcvt.f32.s32 s13, s13 588 .loc 2 2004 45 view .LVU219 589 0024 67EE266A vmul.f32 s13, s14, s13 590 .loc 2 2004 76 view .LVU220 591 0028 284C ldr r4, .L26 592 002a 2468 ldr r4, [r4] 593 002c 284D ldr r5, .L26+4 594 002e 2D68 ldr r5, [r5] 595 0030 641B subs r4, r4, r5 596 0032 07EE104A vmov s14, r4 @ int 597 .loc 2 2004 64 view .LVU221 598 0036 B8EE477A vcvt.f32.u32 s14, s14 599 .loc 2 2004 62 view .LVU222 600 003a 26EE877A vmul.f32 s14, s13, s14 601 .loc 2 2004 87 view .LVU223 602 003e 9FED256A vldr.32 s12, .L26+8 603 0042 C7EE066A vdiv.f32 s13, s14, s12 604 .loc 2 2004 14 view .LVU224 605 0046 77EEA67A vadd.f32 s15, s15, s13 606 .LVL36: ARM GAS /tmp/ccdsDELB.s page 89 607 .L16: 2005:Src/main.c **** } 2006:Src/main.c **** P_coef_current = LDx_curr_setup->P_coef_temp; 608 .loc 2 2006 2 is_stmt 1 view .LVU225 609 .loc 2 2006 17 is_stmt 0 view .LVU226 610 004a D0ED016A vldr.32 s13, [r0, #4] 611 .LVL37: 2007:Src/main.c **** 2008:Src/main.c **** if (e_integral > 32000){ 612 .loc 2 2008 2 is_stmt 1 view .LVU227 613 .loc 2 2008 5 is_stmt 0 view .LVU228 614 004e 9FED227A vldr.32 s14, .L26+12 615 0052 F4EEC77A vcmpe.f32 s15, s14 616 0056 F1EE10FA vmrs APSR_nzcv, FPSCR 617 005a 09DC bgt .L20 2009:Src/main.c **** e_integral = 32000; 2010:Src/main.c **** } 2011:Src/main.c **** else if (e_integral < - 32000){ 618 .loc 2 2011 7 is_stmt 1 view .LVU229 619 .loc 2 2011 10 is_stmt 0 view .LVU230 620 005c 9FED1F7A vldr.32 s14, .L26+16 621 0060 F4EEC77A vcmpe.f32 s15, s14 622 0064 F1EE10FA vmrs APSR_nzcv, FPSCR 623 0068 04D5 bpl .L17 2012:Src/main.c **** e_integral = -32000; 624 .loc 2 2012 15 view .LVU231 625 006a DFED1C7A vldr.32 s15, .L26+16 626 .LVL38: 627 .loc 2 2012 15 view .LVU232 628 006e 01E0 b .L17 629 .LVL39: 630 .L20: 2009:Src/main.c **** e_integral = 32000; 631 .loc 2 2009 15 view .LVU233 632 0070 DFED197A vldr.32 s15, .L26+12 633 .LVL40: 634 .L17: 2013:Src/main.c **** } 2014:Src/main.c **** LDx_results->e_integral = e_integral; 635 .loc 2 2014 2 is_stmt 1 view .LVU234 636 .loc 2 2014 26 is_stmt 0 view .LVU235 637 0074 C1ED017A vstr.32 s15, [r1, #4] 2015:Src/main.c **** 2016:Src/main.c **** x_output = 32768 + P_coef_current * e_pid + (int)e_integral;//32768 - P_coef_current * e_pid - (in 638 .loc 2 2016 2 is_stmt 1 view .LVU236 639 .loc 2 2016 36 is_stmt 0 view .LVU237 640 0078 07EE103A vmov s14, r3 @ int 641 007c B8EEC77A vcvt.f32.s32 s14, s14 642 0080 27EE267A vmul.f32 s14, s14, s13 643 .loc 2 2016 19 view .LVU238 644 0084 DFED166A vldr.32 s13, .L26+20 645 .LVL41: 646 .loc 2 2016 19 view .LVU239 647 0088 37EE267A vadd.f32 s14, s14, s13 648 .loc 2 2016 46 view .LVU240 649 008c FDEEE77A vcvt.s32.f32 s15, s15 650 .LVL42: ARM GAS /tmp/ccdsDELB.s page 90 651 .loc 2 2016 44 view .LVU241 652 0090 F8EEE77A vcvt.f32.s32 s15, s15 653 0094 77EE877A vadd.f32 s15, s15, s14 654 .loc 2 2016 11 view .LVU242 655 0098 FDEEE77A vcvt.s32.f32 s15, s15 656 009c 17EE900A vmov r0, s15 @ int 657 .LVL43: 2017:Src/main.c **** 2018:Src/main.c **** if(x_output < 1000){ 658 .loc 2 2018 2 is_stmt 1 view .LVU243 659 .loc 2 2018 4 is_stmt 0 view .LVU244 660 00a0 B0F57A7F cmp r0, #1000 661 00a4 06DB blt .L22 2019:Src/main.c **** x_output = 8800; 2020:Src/main.c **** } 2021:Src/main.c **** else if(x_output > 56800){ 662 .loc 2 2021 7 is_stmt 1 view .LVU245 663 .loc 2 2021 9 is_stmt 0 view .LVU246 664 00a6 4DF6E053 movw r3, #56800 665 .LVL44: 666 .loc 2 2021 9 view .LVU247 667 00aa 9842 cmp r0, r3 668 00ac 04DD ble .L18 2022:Src/main.c **** x_output = 56800; 669 .loc 2 2022 12 view .LVU248 670 00ae 4DF6E050 movw r0, #56800 671 .LVL45: 672 .loc 2 2022 12 view .LVU249 673 00b2 01E0 b .L18 674 .LVL46: 675 .L22: 2019:Src/main.c **** x_output = 8800; 676 .loc 2 2019 12 view .LVU250 677 00b4 42F26020 movw r0, #8800 678 .LVL47: 679 .L18: 2023:Src/main.c **** } 2024:Src/main.c **** 2025:Src/main.c **** if (num==2) 680 .loc 2 2025 2 is_stmt 1 view .LVU251 681 .loc 2 2025 5 is_stmt 0 view .LVU252 682 00b8 022A cmp r2, #2 683 00ba 02D0 beq .L25 684 .LVL48: 685 .L19: 2026:Src/main.c **** TO7_PID = TO7;//Save current time only on 2nd laser 2027:Src/main.c **** 2028:Src/main.c **** return (uint16_t)x_output; 686 .loc 2 2028 2 is_stmt 1 view .LVU253 2029:Src/main.c **** } 687 .loc 2 2029 1 is_stmt 0 view .LVU254 688 00bc 80B2 uxth r0, r0 689 .LVL49: 690 .loc 2 2029 1 view .LVU255 691 00be 30BC pop {r4, r5} 692 .LCFI6: 693 .cfi_remember_state ARM GAS /tmp/ccdsDELB.s page 91 694 .cfi_restore 5 695 .cfi_restore 4 696 .cfi_def_cfa_offset 0 697 00c0 7047 bx lr 698 .LVL50: 699 .L25: 700 .LCFI7: 701 .cfi_restore_state 2026:Src/main.c **** TO7_PID = TO7;//Save current time only on 2nd laser 702 .loc 2 2026 3 is_stmt 1 view .LVU256 2026:Src/main.c **** TO7_PID = TO7;//Save current time only on 2nd laser 703 .loc 2 2026 11 is_stmt 0 view .LVU257 704 00c2 024B ldr r3, .L26 705 00c4 1A68 ldr r2, [r3] 706 .LVL51: 2026:Src/main.c **** TO7_PID = TO7;//Save current time only on 2nd laser 707 .loc 2 2026 11 view .LVU258 708 00c6 024B ldr r3, .L26+4 709 00c8 1A60 str r2, [r3] 710 00ca F7E7 b .L19 711 .L27: 712 .align 2 713 .L26: 714 00cc 00000000 .word .LANCHOR3 715 00d0 00000000 .word .LANCHOR4 716 00d4 0000C842 .word 1120403456 717 00d8 0000FA46 .word 1190789120 718 00dc 0000FAC6 .word -956694528 719 00e0 00000047 .word 1191182336 720 .cfi_endproc 721 .LFE1209: 723 .section .text.Set_LTEC,"ax",%progbits 724 .align 1 725 .syntax unified 726 .thumb 727 .thumb_func 728 .fpu fpv5-d16 730 Set_LTEC: 731 .LVL52: 732 .LFB1206: 1795:Src/main.c **** uint32_t tmp32; 733 .loc 2 1795 1 is_stmt 1 view -0 734 .cfi_startproc 735 @ args = 0, pretend = 0, frame = 0 736 @ frame_needed = 0, uses_anonymous_args = 0 1795:Src/main.c **** uint32_t tmp32; 737 .loc 2 1795 1 is_stmt 0 view .LVU260 738 0000 38B5 push {r3, r4, r5, lr} 739 .LCFI8: 740 .cfi_def_cfa_offset 16 741 .cfi_offset 3, -16 742 .cfi_offset 4, -12 743 .cfi_offset 5, -8 744 .cfi_offset 14, -4 745 0002 0C46 mov r4, r1 1796:Src/main.c **** switch (num) 746 .loc 2 1796 2 is_stmt 1 view .LVU261 ARM GAS /tmp/ccdsDELB.s page 92 1797:Src/main.c **** { 747 .loc 2 1797 2 view .LVU262 748 0004 0138 subs r0, r0, #1 749 .LVL53: 1797:Src/main.c **** { 750 .loc 2 1797 2 is_stmt 0 view .LVU263 751 0006 0328 cmp r0, #3 752 0008 23D8 bhi .L29 753 000a DFE800F0 tbb [pc, r0] 754 .L31: 755 000e 02 .byte (.L34-.L31)/2 756 000f 3B .byte (.L33-.L31)/2 757 0010 5B .byte (.L32-.L31)/2 758 0011 7C .byte (.L30-.L31)/2 759 .p2align 1 760 .L34: 1800:Src/main.c **** //tmp32=0; 761 .loc 2 1800 4 is_stmt 1 view .LVU264 762 0012 0022 movs r2, #0 763 0014 4FF48041 mov r1, #16384 764 .LVL54: 1800:Src/main.c **** //tmp32=0; 765 .loc 2 1800 4 is_stmt 0 view .LVU265 766 0018 4B48 ldr r0, .L60 767 001a FFF7FEFF bl HAL_GPIO_WritePin 768 .LVL55: 1803:Src/main.c **** while((!LL_SPI_IsActiveFlag_TXE(SPI2))&&(tmp32<=500)) {tmp32++;}//When trans. last data cycle wi 769 .loc 2 1803 4 is_stmt 1 view .LVU266 1804:Src/main.c **** LL_SPI_TransmitData16(SPI2, DATA);//Transmit word to Laser1 DAC 770 .loc 2 1804 4 view .LVU267 1803:Src/main.c **** while((!LL_SPI_IsActiveFlag_TXE(SPI2))&&(tmp32<=500)) {tmp32++;}//When trans. last data cycle wi 771 .loc 2 1803 10 is_stmt 0 view .LVU268 772 001e 0022 movs r2, #0 773 .LVL56: 774 .L35: 1804:Src/main.c **** LL_SPI_TransmitData16(SPI2, DATA);//Transmit word to Laser1 DAC 775 .loc 2 1804 9 is_stmt 1 discriminator 1 view .LVU269 776 .LBB301: 777 .LBI301: 778 .file 4 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h" 1:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 2:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** ****************************************************************************** 3:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @file stm32f7xx_ll_spi.h 4:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @author MCD Application Team 5:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Header file of SPI LL module. 6:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** ****************************************************************************** 7:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @attention 8:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * 9:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * Copyright (c) 2017 STMicroelectronics. 10:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * All rights reserved. 11:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * 12:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * This software is licensed under terms that can be found in the LICENSE file 13:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * in the root directory of this software component. 14:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * If no LICENSE file comes with this software, it is provided AS-IS. 15:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * 16:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** ****************************************************************************** 17:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ ARM GAS /tmp/ccdsDELB.s page 93 18:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 19:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /* Define to prevent recursive inclusion -------------------------------------*/ 20:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #ifndef STM32F7xx_LL_SPI_H 21:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define STM32F7xx_LL_SPI_H 22:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 23:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #ifdef __cplusplus 24:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** extern "C" { 25:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #endif 26:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 27:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /* Includes ------------------------------------------------------------------*/ 28:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #include "stm32f7xx.h" 29:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 30:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @addtogroup STM32F7xx_LL_Driver 31:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @{ 32:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 33:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 34:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #if defined (SPI1) || defined (SPI2) || defined (SPI3) || defined (SPI4) || defined (SPI5) || defin 35:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 36:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL SPI 37:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @{ 38:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 39:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 40:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /* Private types -------------------------------------------------------------*/ 41:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /* Private variables ---------------------------------------------------------*/ 42:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /* Private macros ------------------------------------------------------------*/ 43:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 44:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /* Exported types ------------------------------------------------------------*/ 45:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #if defined(USE_FULL_LL_DRIVER) 46:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_ES_INIT SPI Exported Init structure 47:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @{ 48:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 49:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 50:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 51:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief SPI Init structures definition 52:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 53:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** typedef struct 54:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 55:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** uint32_t TransferDirection; /*!< Specifies the SPI unidirectional or bidirectional data mod 56:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** This parameter can be a value of @ref SPI_LL_EC_TRANSFER_M 57:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 58:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** This feature can be modified afterwards using unitary func 59:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 60:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** uint32_t Mode; /*!< Specifies the SPI mode (Master/Slave). 61:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** This parameter can be a value of @ref SPI_LL_EC_MODE. 62:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 63:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** This feature can be modified afterwards using unitary func 64:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 65:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** uint32_t DataWidth; /*!< Specifies the SPI data width. 66:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** This parameter can be a value of @ref SPI_LL_EC_DATAWIDTH. 67:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 68:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** This feature can be modified afterwards using unitary func 69:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 70:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** uint32_t ClockPolarity; /*!< Specifies the serial clock steady state. 71:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** This parameter can be a value of @ref SPI_LL_EC_POLARITY. 72:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 73:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** This feature can be modified afterwards using unitary func 74:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** ARM GAS /tmp/ccdsDELB.s page 94 75:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** uint32_t ClockPhase; /*!< Specifies the clock active edge for the bit capture. 76:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** This parameter can be a value of @ref SPI_LL_EC_PHASE. 77:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 78:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** This feature can be modified afterwards using unitary func 79:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 80:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** uint32_t NSS; /*!< Specifies whether the NSS signal is managed by hardware (N 81:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** This parameter can be a value of @ref SPI_LL_EC_NSS_MODE. 82:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 83:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** This feature can be modified afterwards using unitary func 84:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 85:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** uint32_t BaudRate; /*!< Specifies the BaudRate prescaler value which will be used 86:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** This parameter can be a value of @ref SPI_LL_EC_BAUDRATEPR 87:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** @note The communication clock is derived from the master c 88:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 89:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** This feature can be modified afterwards using unitary func 90:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 91:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** uint32_t BitOrder; /*!< Specifies whether data transfers start from MSB or LSB bit 92:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** This parameter can be a value of @ref SPI_LL_EC_BIT_ORDER. 93:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 94:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** This feature can be modified afterwards using unitary func 95:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 96:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** uint32_t CRCCalculation; /*!< Specifies if the CRC calculation is enabled or not. 97:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** This parameter can be a value of @ref SPI_LL_EC_CRC_CALCUL 98:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 99:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** This feature can be modified afterwards using unitary func 100:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 101:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** uint32_t CRCPoly; /*!< Specifies the polynomial used for the CRC calculation. 102:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** This parameter must be a number between Min_Data = 0x00 an 103:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 104:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** This feature can be modified afterwards using unitary func 105:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 106:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } LL_SPI_InitTypeDef; 107:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 108:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 109:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @} 110:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 111:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #endif /* USE_FULL_LL_DRIVER */ 112:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 113:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /* Exported constants --------------------------------------------------------*/ 114:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_Exported_Constants SPI Exported Constants 115:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @{ 116:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 117:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 118:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_EC_GET_FLAG Get Flags Defines 119:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Flags defines which can be used with LL_SPI_ReadReg function 120:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @{ 121:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 122:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_SR_RXNE SPI_SR_RXNE /*!< Rx buffer not empty flag 123:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_SR_TXE SPI_SR_TXE /*!< Tx buffer empty flag 124:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_SR_BSY SPI_SR_BSY /*!< Busy flag 125:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_SR_CRCERR SPI_SR_CRCERR /*!< CRC error flag 126:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_SR_MODF SPI_SR_MODF /*!< Mode fault flag 127:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_SR_OVR SPI_SR_OVR /*!< Overrun flag 128:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_SR_FRE SPI_SR_FRE /*!< TI mode frame format erro 129:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 130:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @} 131:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ ARM GAS /tmp/ccdsDELB.s page 95 132:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 133:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_EC_IT IT Defines 134:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief IT defines which can be used with LL_SPI_ReadReg and LL_SPI_WriteReg functions 135:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @{ 136:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 137:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_CR2_RXNEIE SPI_CR2_RXNEIE /*!< Rx buffer not empty inter 138:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_CR2_TXEIE SPI_CR2_TXEIE /*!< Tx buffer empty interrupt 139:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_CR2_ERRIE SPI_CR2_ERRIE /*!< Error interrupt enable 140:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 141:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @} 142:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 143:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 144:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_EC_MODE Operation Mode 145:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @{ 146:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 147:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_MODE_MASTER (SPI_CR1_MSTR | SPI_CR1_SSI) /*!< Master configuratio 148:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_MODE_SLAVE 0x00000000U /*!< Slave configuration 149:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 150:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @} 151:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 152:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 153:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_EC_PROTOCOL Serial Protocol 154:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @{ 155:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 156:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_PROTOCOL_MOTOROLA 0x00000000U /*!< Motorola mode. Used as de 157:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_PROTOCOL_TI (SPI_CR2_FRF) /*!< TI mode 158:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 159:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @} 160:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 161:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 162:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_EC_PHASE Clock Phase 163:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @{ 164:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 165:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_PHASE_1EDGE 0x00000000U /*!< First clock transition is 166:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_PHASE_2EDGE (SPI_CR1_CPHA) /*!< Second clock transition i 167:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 168:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @} 169:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 170:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 171:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_EC_POLARITY Clock Polarity 172:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @{ 173:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 174:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_POLARITY_LOW 0x00000000U /*!< Clock to 0 when idle */ 175:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_POLARITY_HIGH (SPI_CR1_CPOL) /*!< Clock to 1 when idle */ 176:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 177:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @} 178:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 179:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 180:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_EC_BAUDRATEPRESCALER Baud Rate Prescaler 181:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @{ 182:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 183:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_BAUDRATEPRESCALER_DIV2 0x00000000U /*!< Baud 184:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_BAUDRATEPRESCALER_DIV4 (SPI_CR1_BR_0) /*!< Baud 185:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_BAUDRATEPRESCALER_DIV8 (SPI_CR1_BR_1) /*!< Baud 186:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_BAUDRATEPRESCALER_DIV16 (SPI_CR1_BR_1 | SPI_CR1_BR_0) /*!< Baud 187:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_BAUDRATEPRESCALER_DIV32 (SPI_CR1_BR_2) /*!< Baud 188:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_BAUDRATEPRESCALER_DIV64 (SPI_CR1_BR_2 | SPI_CR1_BR_0) /*!< Baud ARM GAS /tmp/ccdsDELB.s page 96 189:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_BAUDRATEPRESCALER_DIV128 (SPI_CR1_BR_2 | SPI_CR1_BR_1) /*!< Baud 190:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_BAUDRATEPRESCALER_DIV256 (SPI_CR1_BR_2 | SPI_CR1_BR_1 | SPI_CR1_BR_0) /*!< Baud 191:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 192:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @} 193:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 194:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 195:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_EC_BIT_ORDER Transmission Bit Order 196:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @{ 197:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 198:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_LSB_FIRST (SPI_CR1_LSBFIRST) /*!< Data is transmitted/recei 199:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_MSB_FIRST 0x00000000U /*!< Data is transmitted/recei 200:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 201:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @} 202:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 203:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 204:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_EC_TRANSFER_MODE Transfer Mode 205:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @{ 206:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 207:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_FULL_DUPLEX 0x00000000U /*!< Full-Duplex mo 208:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_SIMPLEX_RX (SPI_CR1_RXONLY) /*!< Simplex Rx mod 209:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_HALF_DUPLEX_RX (SPI_CR1_BIDIMODE) /*!< Half-Duplex Rx 210:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_HALF_DUPLEX_TX (SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE) /*!< Half-Duplex Tx 211:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 212:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @} 213:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 214:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 215:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_EC_NSS_MODE Slave Select Pin Mode 216:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @{ 217:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 218:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_NSS_SOFT (SPI_CR1_SSM) /*!< NSS managed inter 219:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_NSS_HARD_INPUT 0x00000000U /*!< NSS pin used in I 220:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_NSS_HARD_OUTPUT (((uint32_t)SPI_CR2_SSOE << 16U)) /*!< NSS pin used in O 221:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 222:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @} 223:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 224:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 225:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_EC_DATAWIDTH Datawidth 226:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @{ 227:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 228:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_DATAWIDTH_4BIT (SPI_CR2_DS_0 | SPI_CR2_DS_1) 229:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_DATAWIDTH_5BIT (SPI_CR2_DS_2) 230:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_DATAWIDTH_6BIT (SPI_CR2_DS_2 | SPI_CR2_DS_0) 231:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_DATAWIDTH_7BIT (SPI_CR2_DS_2 | SPI_CR2_DS_1) 232:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_DATAWIDTH_8BIT (SPI_CR2_DS_2 | SPI_CR2_DS_1 | SPI_CR2_DS_0) 233:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_DATAWIDTH_9BIT (SPI_CR2_DS_3) 234:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_DATAWIDTH_10BIT (SPI_CR2_DS_3 | SPI_CR2_DS_0) 235:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_DATAWIDTH_11BIT (SPI_CR2_DS_3 | SPI_CR2_DS_1) 236:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_DATAWIDTH_12BIT (SPI_CR2_DS_3 | SPI_CR2_DS_1 | SPI_CR2_DS_0) 237:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_DATAWIDTH_13BIT (SPI_CR2_DS_3 | SPI_CR2_DS_2) 238:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_DATAWIDTH_14BIT (SPI_CR2_DS_3 | SPI_CR2_DS_2 | SPI_CR2_DS_0) 239:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_DATAWIDTH_15BIT (SPI_CR2_DS_3 | SPI_CR2_DS_2 | SPI_CR2_DS_1) 240:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_DATAWIDTH_16BIT (SPI_CR2_DS_3 | SPI_CR2_DS_2 | SPI_CR2_DS_1 | SPI_CR2_DS 241:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 242:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @} 243:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 244:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #if defined(USE_FULL_LL_DRIVER) 245:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** ARM GAS /tmp/ccdsDELB.s page 97 246:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_EC_CRC_CALCULATION CRC Calculation 247:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @{ 248:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 249:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_CRCCALCULATION_DISABLE 0x00000000U /*!< CRC calculation disabled 250:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_CRCCALCULATION_ENABLE (SPI_CR1_CRCEN) /*!< CRC calculation enabled 251:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 252:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @} 253:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 254:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #endif /* USE_FULL_LL_DRIVER */ 255:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 256:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_EC_CRC_LENGTH CRC Length 257:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @{ 258:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 259:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_CRC_8BIT 0x00000000U /*!< 8-bit CRC length */ 260:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_CRC_16BIT (SPI_CR1_CRCL) /*!< 16-bit CRC length */ 261:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 262:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @} 263:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 264:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 265:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_EC_RX_FIFO_TH RX FIFO Threshold 266:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @{ 267:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 268:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_RX_FIFO_TH_HALF 0x00000000U /*!< RXNE event is generated i 269:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_RX_FIFO_TH_QUARTER (SPI_CR2_FRXTH) /*!< RXNE event is generated i 270:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 271:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @} 272:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 273:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 274:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_EC_RX_FIFO RX FIFO Level 275:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @{ 276:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 277:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_RX_FIFO_EMPTY 0x00000000U /*!< FIFO reception em 278:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_RX_FIFO_QUARTER_FULL (SPI_SR_FRLVL_0) /*!< FIFO reception 1/ 279:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_RX_FIFO_HALF_FULL (SPI_SR_FRLVL_1) /*!< FIFO reception 1/ 280:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_RX_FIFO_FULL (SPI_SR_FRLVL_1 | SPI_SR_FRLVL_0) /*!< FIFO reception fu 281:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 282:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @} 283:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 284:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 285:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_EC_TX_FIFO TX FIFO Level 286:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @{ 287:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 288:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_TX_FIFO_EMPTY 0x00000000U /*!< FIFO transmission 289:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_TX_FIFO_QUARTER_FULL (SPI_SR_FTLVL_0) /*!< FIFO transmission 290:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_TX_FIFO_HALF_FULL (SPI_SR_FTLVL_1) /*!< FIFO transmission 291:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_TX_FIFO_FULL (SPI_SR_FTLVL_1 | SPI_SR_FTLVL_0) /*!< FIFO transmission 292:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 293:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @} 294:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 295:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 296:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_EC_DMA_PARITY DMA Parity 297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @{ 298:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 299:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_DMA_PARITY_EVEN 0x00000000U /*!< Select DMA parity Even */ 300:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_DMA_PARITY_ODD 0x00000001U /*!< Select DMA parity Odd */ 301:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 302:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** ARM GAS /tmp/ccdsDELB.s page 98 303:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @} 304:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 305:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 306:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 307:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @} 308:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 309:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 310:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /* Exported macro ------------------------------------------------------------*/ 311:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_Exported_Macros SPI Exported Macros 312:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @{ 313:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_EM_WRITE_READ Common Write and read registers Macros 316:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @{ 317:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 318:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 319:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 320:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Write a value in SPI register 321:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param __INSTANCE__ SPI Instance 322:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param __REG__ Register to be written 323:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param __VALUE__ Value to be written in the register 324:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None 325:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 326:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE 327:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 328:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 329:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Read a value in SPI register 330:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param __INSTANCE__ SPI Instance 331:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param __REG__ Register to be read 332:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval Register value 333:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 334:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) 335:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 336:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @} 337:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 338:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 339:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 340:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @} 341:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 342:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 343:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /* Exported functions --------------------------------------------------------*/ 344:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_Exported_Functions SPI Exported Functions 345:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @{ 346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 347:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 348:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_EF_Configuration Configuration 349:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @{ 350:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 351:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 352:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 353:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Enable SPI peripheral 354:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR1 SPE LL_SPI_Enable 355:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 356:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None 357:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 358:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_Enable(SPI_TypeDef *SPIx) 359:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { ARM GAS /tmp/ccdsDELB.s page 99 360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** SET_BIT(SPIx->CR1, SPI_CR1_SPE); 361:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 362:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 363:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 364:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Disable SPI peripheral 365:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @note When disabling the SPI, follow the procedure described in the Reference Manual. 366:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR1 SPE LL_SPI_Disable 367:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 368:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None 369:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_Disable(SPI_TypeDef *SPIx) 371:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE); 373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 374:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 375:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 376:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Check if SPI peripheral is enabled 377:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR1 SPE LL_SPI_IsEnabled 378:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 379:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval State of bit (1 or 0). 380:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 381:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_IsEnabled(SPI_TypeDef *SPIx) 382:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 383:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** return ((READ_BIT(SPIx->CR1, SPI_CR1_SPE) == (SPI_CR1_SPE)) ? 1UL : 0UL); 384:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 385:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 386:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 387:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Set SPI operation mode to Master or Slave 388:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @note This bit should not be changed when communication is ongoing. 389:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR1 MSTR LL_SPI_SetMode\n 390:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * CR1 SSI LL_SPI_SetMode 391:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 392:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param Mode This parameter can be one of the following values: 393:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_MODE_MASTER 394:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_MODE_SLAVE 395:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None 396:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 397:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_SetMode(SPI_TypeDef *SPIx, uint32_t Mode) 398:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 399:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** MODIFY_REG(SPIx->CR1, SPI_CR1_MSTR | SPI_CR1_SSI, Mode); 400:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 401:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 402:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 403:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Get SPI operation mode (Master or Slave) 404:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR1 MSTR LL_SPI_GetMode\n 405:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * CR1 SSI LL_SPI_GetMode 406:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 407:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval Returned value can be one of the following values: 408:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_MODE_MASTER 409:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_MODE_SLAVE 410:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 411:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_GetMode(SPI_TypeDef *SPIx) 412:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 413:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_MSTR | SPI_CR1_SSI)); 414:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 415:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 416:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** ARM GAS /tmp/ccdsDELB.s page 100 417:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Set serial protocol used 418:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation. 419:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR2 FRF LL_SPI_SetStandard 420:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 421:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param Standard This parameter can be one of the following values: 422:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_PROTOCOL_MOTOROLA 423:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_PROTOCOL_TI 424:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None 425:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 426:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_SetStandard(SPI_TypeDef *SPIx, uint32_t Standard) 427:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** MODIFY_REG(SPIx->CR2, SPI_CR2_FRF, Standard); 429:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 430:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 431:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 432:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Get serial protocol used 433:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR2 FRF LL_SPI_GetStandard 434:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 435:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval Returned value can be one of the following values: 436:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_PROTOCOL_MOTOROLA 437:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_PROTOCOL_TI 438:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 439:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_GetStandard(SPI_TypeDef *SPIx) 440:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 441:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_FRF)); 442:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 443:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 444:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 445:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Set clock phase 446:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @note This bit should not be changed when communication is ongoing. 447:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * This bit is not used in SPI TI mode. 448:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR1 CPHA LL_SPI_SetClockPhase 449:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 450:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param ClockPhase This parameter can be one of the following values: 451:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_PHASE_1EDGE 452:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_PHASE_2EDGE 453:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None 454:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 455:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_SetClockPhase(SPI_TypeDef *SPIx, uint32_t ClockPhase) 456:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 457:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** MODIFY_REG(SPIx->CR1, SPI_CR1_CPHA, ClockPhase); 458:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 459:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 460:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 461:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Get clock phase 462:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR1 CPHA LL_SPI_GetClockPhase 463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 464:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval Returned value can be one of the following values: 465:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_PHASE_1EDGE 466:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_PHASE_2EDGE 467:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 468:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_GetClockPhase(SPI_TypeDef *SPIx) 469:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 470:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPHA)); 471:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 472:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 473:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** ARM GAS /tmp/ccdsDELB.s page 101 474:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Set clock polarity 475:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @note This bit should not be changed when communication is ongoing. 476:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * This bit is not used in SPI TI mode. 477:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR1 CPOL LL_SPI_SetClockPolarity 478:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 479:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param ClockPolarity This parameter can be one of the following values: 480:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_POLARITY_LOW 481:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_POLARITY_HIGH 482:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None 483:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 484:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPolarity) 485:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 486:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** MODIFY_REG(SPIx->CR1, SPI_CR1_CPOL, ClockPolarity); 487:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 488:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 489:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 490:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Get clock polarity 491:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR1 CPOL LL_SPI_GetClockPolarity 492:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 493:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval Returned value can be one of the following values: 494:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_POLARITY_LOW 495:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_POLARITY_HIGH 496:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 497:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_GetClockPolarity(SPI_TypeDef *SPIx) 498:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 499:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPOL)); 500:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 501:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 502:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 503:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Set baud rate prescaler 504:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @note These bits should not be changed when communication is ongoing. SPI BaudRate = fPCLK/Pr 505:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR1 BR LL_SPI_SetBaudRatePrescaler 506:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 507:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param BaudRate This parameter can be one of the following values: 508:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2 509:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4 510:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8 511:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16 512:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32 513:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64 514:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128 515:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256 516:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None 517:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 518:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_SetBaudRatePrescaler(SPI_TypeDef *SPIx, uint32_t BaudRate) 519:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 520:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** MODIFY_REG(SPIx->CR1, SPI_CR1_BR, BaudRate); 521:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 522:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 523:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 524:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Get baud rate prescaler 525:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR1 BR LL_SPI_GetBaudRatePrescaler 526:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 527:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval Returned value can be one of the following values: 528:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2 529:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4 530:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8 ARM GAS /tmp/ccdsDELB.s page 102 531:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16 532:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32 533:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64 534:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128 535:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256 536:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 537:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_GetBaudRatePrescaler(SPI_TypeDef *SPIx) 538:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 539:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_BR)); 540:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 541:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 542:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 543:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Set transfer bit order 544:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @note This bit should not be changed when communication is ongoing. This bit is not used in S 545:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR1 LSBFIRST LL_SPI_SetTransferBitOrder 546:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 547:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param BitOrder This parameter can be one of the following values: 548:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_LSB_FIRST 549:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_MSB_FIRST 550:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None 551:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 552:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_SetTransferBitOrder(SPI_TypeDef *SPIx, uint32_t BitOrder) 553:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 554:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** MODIFY_REG(SPIx->CR1, SPI_CR1_LSBFIRST, BitOrder); 555:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 556:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 557:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 558:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Get transfer bit order 559:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR1 LSBFIRST LL_SPI_GetTransferBitOrder 560:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 561:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval Returned value can be one of the following values: 562:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_LSB_FIRST 563:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_MSB_FIRST 564:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 565:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_GetTransferBitOrder(SPI_TypeDef *SPIx) 566:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 567:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_LSBFIRST)); 568:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 569:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 570:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 571:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Set transfer direction mode 572:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @note For Half-Duplex mode, Rx Direction is set by default. 573:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * In master mode, the MOSI pin is used and in slave mode, the MISO pin is used for Half-D 574:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR1 RXONLY LL_SPI_SetTransferDirection\n 575:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * CR1 BIDIMODE LL_SPI_SetTransferDirection\n 576:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * CR1 BIDIOE LL_SPI_SetTransferDirection 577:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 578:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param TransferDirection This parameter can be one of the following values: 579:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_FULL_DUPLEX 580:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_SIMPLEX_RX 581:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_HALF_DUPLEX_RX 582:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_HALF_DUPLEX_TX 583:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None 584:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 585:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_SetTransferDirection(SPI_TypeDef *SPIx, uint32_t TransferDirection) 586:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 587:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** MODIFY_REG(SPIx->CR1, SPI_CR1_RXONLY | SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE, TransferDirection); ARM GAS /tmp/ccdsDELB.s page 103 588:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 589:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 590:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 591:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Get transfer direction mode 592:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR1 RXONLY LL_SPI_GetTransferDirection\n 593:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * CR1 BIDIMODE LL_SPI_GetTransferDirection\n 594:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * CR1 BIDIOE LL_SPI_GetTransferDirection 595:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 596:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval Returned value can be one of the following values: 597:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_FULL_DUPLEX 598:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_SIMPLEX_RX 599:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_HALF_DUPLEX_RX 600:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_HALF_DUPLEX_TX 601:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 602:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_GetTransferDirection(SPI_TypeDef *SPIx) 603:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 604:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_RXONLY | SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE)); 605:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 606:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 607:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 608:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Set frame data width 609:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR2 DS LL_SPI_SetDataWidth 610:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 611:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param DataWidth This parameter can be one of the following values: 612:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_DATAWIDTH_4BIT 613:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_DATAWIDTH_5BIT 614:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_DATAWIDTH_6BIT 615:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_DATAWIDTH_7BIT 616:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_DATAWIDTH_8BIT 617:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_DATAWIDTH_9BIT 618:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_DATAWIDTH_10BIT 619:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_DATAWIDTH_11BIT 620:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_DATAWIDTH_12BIT 621:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_DATAWIDTH_13BIT 622:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_DATAWIDTH_14BIT 623:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_DATAWIDTH_15BIT 624:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_DATAWIDTH_16BIT 625:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None 626:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 627:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_SetDataWidth(SPI_TypeDef *SPIx, uint32_t DataWidth) 628:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 629:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** MODIFY_REG(SPIx->CR2, SPI_CR2_DS, DataWidth); 630:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 631:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 632:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 633:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Get frame data width 634:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR2 DS LL_SPI_GetDataWidth 635:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 636:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval Returned value can be one of the following values: 637:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_DATAWIDTH_4BIT 638:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_DATAWIDTH_5BIT 639:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_DATAWIDTH_6BIT 640:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_DATAWIDTH_7BIT 641:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_DATAWIDTH_8BIT 642:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_DATAWIDTH_9BIT 643:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_DATAWIDTH_10BIT 644:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_DATAWIDTH_11BIT ARM GAS /tmp/ccdsDELB.s page 104 645:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_DATAWIDTH_12BIT 646:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_DATAWIDTH_13BIT 647:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_DATAWIDTH_14BIT 648:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_DATAWIDTH_15BIT 649:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_DATAWIDTH_16BIT 650:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 651:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_GetDataWidth(SPI_TypeDef *SPIx) 652:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 653:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_DS)); 654:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 655:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 656:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 657:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Set threshold of RXFIFO that triggers an RXNE event 658:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR2 FRXTH LL_SPI_SetRxFIFOThreshold 659:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 660:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param Threshold This parameter can be one of the following values: 661:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_RX_FIFO_TH_HALF 662:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_RX_FIFO_TH_QUARTER 663:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None 664:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 665:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_SetRxFIFOThreshold(SPI_TypeDef *SPIx, uint32_t Threshold) 666:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 667:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** MODIFY_REG(SPIx->CR2, SPI_CR2_FRXTH, Threshold); 668:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 669:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 670:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 671:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Get threshold of RXFIFO that triggers an RXNE event 672:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR2 FRXTH LL_SPI_GetRxFIFOThreshold 673:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 674:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval Returned value can be one of the following values: 675:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_RX_FIFO_TH_HALF 676:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_RX_FIFO_TH_QUARTER 677:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 678:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_GetRxFIFOThreshold(SPI_TypeDef *SPIx) 679:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 680:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_FRXTH)); 681:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 682:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 683:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 684:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @} 685:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 686:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 687:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_EF_CRC_Management CRC Management 688:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @{ 689:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 690:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 691:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 692:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Enable CRC 693:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation. 694:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR1 CRCEN LL_SPI_EnableCRC 695:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 696:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None 697:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 698:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_EnableCRC(SPI_TypeDef *SPIx) 699:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 700:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** SET_BIT(SPIx->CR1, SPI_CR1_CRCEN); 701:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } ARM GAS /tmp/ccdsDELB.s page 105 702:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 703:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 704:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Disable CRC 705:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation. 706:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR1 CRCEN LL_SPI_DisableCRC 707:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 708:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None 709:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 710:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_DisableCRC(SPI_TypeDef *SPIx) 711:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 712:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** CLEAR_BIT(SPIx->CR1, SPI_CR1_CRCEN); 713:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 714:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 715:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 716:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Check if CRC is enabled 717:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation. 718:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR1 CRCEN LL_SPI_IsEnabledCRC 719:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 720:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval State of bit (1 or 0). 721:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 722:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_IsEnabledCRC(SPI_TypeDef *SPIx) 723:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 724:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** return ((READ_BIT(SPIx->CR1, SPI_CR1_CRCEN) == (SPI_CR1_CRCEN)) ? 1UL : 0UL); 725:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 726:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 727:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 728:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Set CRC Length 729:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation. 730:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR1 CRCL LL_SPI_SetCRCWidth 731:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 732:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param CRCLength This parameter can be one of the following values: 733:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_CRC_8BIT 734:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_CRC_16BIT 735:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None 736:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 737:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_SetCRCWidth(SPI_TypeDef *SPIx, uint32_t CRCLength) 738:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 739:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** MODIFY_REG(SPIx->CR1, SPI_CR1_CRCL, CRCLength); 740:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 741:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 742:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 743:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Get CRC Length 744:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR1 CRCL LL_SPI_GetCRCWidth 745:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 746:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval Returned value can be one of the following values: 747:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_CRC_8BIT 748:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_CRC_16BIT 749:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 750:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_GetCRCWidth(SPI_TypeDef *SPIx) 751:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 752:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CRCL)); 753:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 754:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 755:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 756:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Set CRCNext to transfer CRC on the line 757:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @note This bit has to be written as soon as the last data is written in the SPIx_DR register. 758:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR1 CRCNEXT LL_SPI_SetCRCNext ARM GAS /tmp/ccdsDELB.s page 106 759:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 760:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None 761:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 762:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_SetCRCNext(SPI_TypeDef *SPIx) 763:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 764:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** SET_BIT(SPIx->CR1, SPI_CR1_CRCNEXT); 765:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 766:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 767:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 768:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Set polynomial for CRC calculation 769:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CRCPR CRCPOLY LL_SPI_SetCRCPolynomial 770:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 771:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param CRCPoly This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFF 772:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None 773:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 774:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_SetCRCPolynomial(SPI_TypeDef *SPIx, uint32_t CRCPoly) 775:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 776:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** WRITE_REG(SPIx->CRCPR, (uint16_t)CRCPoly); 777:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 778:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 779:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 780:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Get polynomial for CRC calculation 781:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CRCPR CRCPOLY LL_SPI_GetCRCPolynomial 782:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 783:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF 784:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 785:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_GetCRCPolynomial(SPI_TypeDef *SPIx) 786:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 787:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** return (uint32_t)(READ_REG(SPIx->CRCPR)); 788:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 789:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 790:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 791:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Get Rx CRC 792:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll RXCRCR RXCRC LL_SPI_GetRxCRC 793:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 794:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF 795:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 796:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_GetRxCRC(SPI_TypeDef *SPIx) 797:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 798:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** return (uint32_t)(READ_REG(SPIx->RXCRCR)); 799:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 800:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 801:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 802:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Get Tx CRC 803:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll TXCRCR TXCRC LL_SPI_GetTxCRC 804:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 805:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF 806:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 807:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_GetTxCRC(SPI_TypeDef *SPIx) 808:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 809:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** return (uint32_t)(READ_REG(SPIx->TXCRCR)); 810:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 811:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 812:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 813:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @} 814:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 815:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** ARM GAS /tmp/ccdsDELB.s page 107 816:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_EF_NSS_Management Slave Select Pin Management 817:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @{ 818:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 819:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 820:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 821:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Set NSS mode 822:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @note LL_SPI_NSS_SOFT Mode is not used in SPI TI mode. 823:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR1 SSM LL_SPI_SetNSSMode\n 824:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR2 SSOE LL_SPI_SetNSSMode 825:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 826:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param NSS This parameter can be one of the following values: 827:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_NSS_SOFT 828:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_NSS_HARD_INPUT 829:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_NSS_HARD_OUTPUT 830:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None 831:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 832:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_SetNSSMode(SPI_TypeDef *SPIx, uint32_t NSS) 833:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 834:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** MODIFY_REG(SPIx->CR1, SPI_CR1_SSM, NSS); 835:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** MODIFY_REG(SPIx->CR2, SPI_CR2_SSOE, ((uint32_t)(NSS >> 16U))); 836:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 837:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 838:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 839:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Get NSS mode 840:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR1 SSM LL_SPI_GetNSSMode\n 841:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR2 SSOE LL_SPI_GetNSSMode 842:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 843:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval Returned value can be one of the following values: 844:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_NSS_SOFT 845:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_NSS_HARD_INPUT 846:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_NSS_HARD_OUTPUT 847:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 848:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_GetNSSMode(SPI_TypeDef *SPIx) 849:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 850:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** uint32_t Ssm = (READ_BIT(SPIx->CR1, SPI_CR1_SSM)); 851:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** uint32_t Ssoe = (READ_BIT(SPIx->CR2, SPI_CR2_SSOE) << 16U); 852:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** return (Ssm | Ssoe); 853:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 854:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 855:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 856:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Enable NSS pulse management 857:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @note This bit should not be changed when communication is ongoing. This bit is not used in S 858:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR2 NSSP LL_SPI_EnableNSSPulseMgt 859:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 860:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None 861:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 862:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_EnableNSSPulseMgt(SPI_TypeDef *SPIx) 863:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 864:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** SET_BIT(SPIx->CR2, SPI_CR2_NSSP); 865:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 866:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 867:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 868:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Disable NSS pulse management 869:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @note This bit should not be changed when communication is ongoing. This bit is not used in S 870:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR2 NSSP LL_SPI_DisableNSSPulseMgt 871:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 872:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None ARM GAS /tmp/ccdsDELB.s page 108 873:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 874:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_DisableNSSPulseMgt(SPI_TypeDef *SPIx) 875:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 876:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** CLEAR_BIT(SPIx->CR2, SPI_CR2_NSSP); 877:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 878:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 879:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 880:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Check if NSS pulse is enabled 881:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @note This bit should not be changed when communication is ongoing. This bit is not used in S 882:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR2 NSSP LL_SPI_IsEnabledNSSPulse 883:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 884:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval State of bit (1 or 0). 885:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 886:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_IsEnabledNSSPulse(SPI_TypeDef *SPIx) 887:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 888:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** return ((READ_BIT(SPIx->CR2, SPI_CR2_NSSP) == (SPI_CR2_NSSP)) ? 1UL : 0UL); 889:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 890:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 891:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 892:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @} 893:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 894:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 895:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_EF_FLAG_Management FLAG Management 896:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @{ 897:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 898:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 899:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 900:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Check if Rx buffer is not empty 901:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll SR RXNE LL_SPI_IsActiveFlag_RXNE 902:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 903:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval State of bit (1 or 0). 904:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 905:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXNE(SPI_TypeDef *SPIx) 906:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** return ((READ_BIT(SPIx->SR, SPI_SR_RXNE) == (SPI_SR_RXNE)) ? 1UL : 0UL); 908:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 909:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 910:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 911:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Check if Tx buffer is empty 912:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll SR TXE LL_SPI_IsActiveFlag_TXE 913:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 914:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval State of bit (1 or 0). 915:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 916:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXE(SPI_TypeDef *SPIx) 779 .loc 4 916 26 discriminator 1 view .LVU270 780 .LBB302: 917:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** return ((READ_BIT(SPIx->SR, SPI_SR_TXE) == (SPI_SR_TXE)) ? 1UL : 0UL); 781 .loc 4 918 3 discriminator 1 view .LVU271 782 .loc 4 918 12 is_stmt 0 discriminator 1 view .LVU272 783 0020 4A4B ldr r3, .L60+4 784 0022 9B68 ldr r3, [r3, #8] 785 .loc 4 918 66 discriminator 1 view .LVU273 786 0024 13F0020F tst r3, #2 787 0028 04D1 bne .L36 788 .LVL57: 789 .loc 4 918 66 discriminator 1 view .LVU274 ARM GAS /tmp/ccdsDELB.s page 109 790 .LBE302: 791 .LBE301: 1804:Src/main.c **** LL_SPI_TransmitData16(SPI2, DATA);//Transmit word to Laser1 DAC 792 .loc 2 1804 42 view .LVU275 793 002a B2F5FA7F cmp r2, #500 794 002e 01D8 bhi .L36 1804:Src/main.c **** LL_SPI_TransmitData16(SPI2, DATA);//Transmit word to Laser1 DAC 795 .loc 2 1804 59 is_stmt 1 discriminator 3 view .LVU276 1804:Src/main.c **** LL_SPI_TransmitData16(SPI2, DATA);//Transmit word to Laser1 DAC 796 .loc 2 1804 64 is_stmt 0 discriminator 3 view .LVU277 797 0030 0132 adds r2, r2, #1 798 .LVL58: 1804:Src/main.c **** LL_SPI_TransmitData16(SPI2, DATA);//Transmit word to Laser1 DAC 799 .loc 2 1804 64 discriminator 3 view .LVU278 800 0032 F5E7 b .L35 801 .L36: 1805:Src/main.c **** tmp32 = 0; 802 .loc 2 1805 4 is_stmt 1 view .LVU279 803 .LVL59: 804 .LBB303: 805 .LBI303: 919:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 920:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 921:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 922:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Get CRC error flag 923:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll SR CRCERR LL_SPI_IsActiveFlag_CRCERR 924:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 925:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval State of bit (1 or 0). 926:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 927:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_CRCERR(SPI_TypeDef *SPIx) 928:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 929:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** return ((READ_BIT(SPIx->SR, SPI_SR_CRCERR) == (SPI_SR_CRCERR)) ? 1UL : 0UL); 930:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 931:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 932:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 933:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Get mode fault error flag 934:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll SR MODF LL_SPI_IsActiveFlag_MODF 935:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 936:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval State of bit (1 or 0). 937:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 938:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_MODF(SPI_TypeDef *SPIx) 939:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 940:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** return ((READ_BIT(SPIx->SR, SPI_SR_MODF) == (SPI_SR_MODF)) ? 1UL : 0UL); 941:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 942:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 943:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 944:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Get overrun error flag 945:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll SR OVR LL_SPI_IsActiveFlag_OVR 946:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 947:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval State of bit (1 or 0). 948:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 949:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_OVR(SPI_TypeDef *SPIx) 950:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 951:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** return ((READ_BIT(SPIx->SR, SPI_SR_OVR) == (SPI_SR_OVR)) ? 1UL : 0UL); 952:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 953:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 954:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** ARM GAS /tmp/ccdsDELB.s page 110 955:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Get busy flag 956:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @note The BSY flag is cleared under any one of the following conditions: 957:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * -When the SPI is correctly disabled 958:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * -When a fault is detected in Master mode (MODF bit set to 1) 959:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * -In Master mode, when it finishes a data transmission and no new data is ready to be 960:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * sent 961:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * -In Slave mode, when the BSY flag is set to '0' for at least one SPI clock cycle between 962:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * each data transfer. 963:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll SR BSY LL_SPI_IsActiveFlag_BSY 964:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 965:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval State of bit (1 or 0). 966:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 967:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_BSY(SPI_TypeDef *SPIx) 968:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 969:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** return ((READ_BIT(SPIx->SR, SPI_SR_BSY) == (SPI_SR_BSY)) ? 1UL : 0UL); 970:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 971:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 972:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 973:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Get frame format error flag 974:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll SR FRE LL_SPI_IsActiveFlag_FRE 975:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 976:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval State of bit (1 or 0). 977:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 978:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_FRE(SPI_TypeDef *SPIx) 979:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 980:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** return ((READ_BIT(SPIx->SR, SPI_SR_FRE) == (SPI_SR_FRE)) ? 1UL : 0UL); 981:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 982:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 983:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 984:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Get FIFO reception Level 985:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll SR FRLVL LL_SPI_GetRxFIFOLevel 986:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 987:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval Returned value can be one of the following values: 988:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_RX_FIFO_EMPTY 989:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_RX_FIFO_QUARTER_FULL 990:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_RX_FIFO_HALF_FULL 991:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_RX_FIFO_FULL 992:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 993:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_GetRxFIFOLevel(SPI_TypeDef *SPIx) 994:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 995:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** return (uint32_t)(READ_BIT(SPIx->SR, SPI_SR_FRLVL)); 996:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 997:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 998:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 999:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Get FIFO Transmission Level 1000:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll SR FTLVL LL_SPI_GetTxFIFOLevel 1001:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 1002:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval Returned value can be one of the following values: 1003:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_TX_FIFO_EMPTY 1004:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_TX_FIFO_QUARTER_FULL 1005:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_TX_FIFO_HALF_FULL 1006:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_TX_FIFO_FULL 1007:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 1008:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_GetTxFIFOLevel(SPI_TypeDef *SPIx) 1009:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 1010:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** return (uint32_t)(READ_BIT(SPIx->SR, SPI_SR_FTLVL)); 1011:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } ARM GAS /tmp/ccdsDELB.s page 111 1012:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 1013:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 1014:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Clear CRC error flag 1015:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll SR CRCERR LL_SPI_ClearFlag_CRCERR 1016:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 1017:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None 1018:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 1019:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_ClearFlag_CRCERR(SPI_TypeDef *SPIx) 1020:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 1021:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** CLEAR_BIT(SPIx->SR, SPI_SR_CRCERR); 1022:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1023:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 1024:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 1025:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Clear mode fault error flag 1026:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @note Clearing this flag is done by a read access to the SPIx_SR 1027:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * register followed by a write access to the SPIx_CR1 register 1028:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll SR MODF LL_SPI_ClearFlag_MODF 1029:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 1030:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None 1031:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 1032:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_ClearFlag_MODF(SPI_TypeDef *SPIx) 1033:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 1034:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __IO uint32_t tmpreg_sr; 1035:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** tmpreg_sr = SPIx->SR; 1036:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** (void) tmpreg_sr; 1037:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE); 1038:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1039:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 1040:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 1041:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Clear overrun error flag 1042:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @note Clearing this flag is done by a read access to the SPIx_DR 1043:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * register followed by a read access to the SPIx_SR register 1044:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll SR OVR LL_SPI_ClearFlag_OVR 1045:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 1046:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None 1047:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 1048:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_ClearFlag_OVR(SPI_TypeDef *SPIx) 1049:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 1050:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __IO uint32_t tmpreg; 1051:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** tmpreg = SPIx->DR; 1052:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** (void) tmpreg; 1053:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** tmpreg = SPIx->SR; 1054:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** (void) tmpreg; 1055:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1056:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 1057:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 1058:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Clear frame format error flag 1059:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @note Clearing this flag is done by reading SPIx_SR register 1060:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll SR FRE LL_SPI_ClearFlag_FRE 1061:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 1062:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None 1063:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 1064:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_ClearFlag_FRE(SPI_TypeDef *SPIx) 1065:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 1066:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __IO uint32_t tmpreg; 1067:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** tmpreg = SPIx->SR; 1068:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** (void) tmpreg; ARM GAS /tmp/ccdsDELB.s page 112 1069:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1070:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 1071:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 1072:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @} 1073:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 1074:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 1075:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_EF_IT_Management Interrupt Management 1076:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @{ 1077:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 1078:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 1079:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 1080:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Enable error interrupt 1081:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @note This bit controls the generation of an interrupt when an error condition occurs (CRCERR 1082:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR2 ERRIE LL_SPI_EnableIT_ERR 1083:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 1084:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None 1085:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 1086:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_EnableIT_ERR(SPI_TypeDef *SPIx) 1087:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 1088:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** SET_BIT(SPIx->CR2, SPI_CR2_ERRIE); 1089:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1090:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 1091:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 1092:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Enable Rx buffer not empty interrupt 1093:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR2 RXNEIE LL_SPI_EnableIT_RXNE 1094:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 1095:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None 1096:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 1097:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_EnableIT_RXNE(SPI_TypeDef *SPIx) 1098:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 1099:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** SET_BIT(SPIx->CR2, SPI_CR2_RXNEIE); 1100:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1101:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 1102:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 1103:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Enable Tx buffer empty interrupt 1104:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR2 TXEIE LL_SPI_EnableIT_TXE 1105:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 1106:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None 1107:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 1108:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_EnableIT_TXE(SPI_TypeDef *SPIx) 1109:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 1110:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** SET_BIT(SPIx->CR2, SPI_CR2_TXEIE); 1111:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1112:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 1113:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 1114:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Disable error interrupt 1115:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @note This bit controls the generation of an interrupt when an error condition occurs (CRCERR 1116:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR2 ERRIE LL_SPI_DisableIT_ERR 1117:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 1118:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None 1119:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 1120:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_DisableIT_ERR(SPI_TypeDef *SPIx) 1121:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 1122:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** CLEAR_BIT(SPIx->CR2, SPI_CR2_ERRIE); 1123:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1124:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 1125:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** ARM GAS /tmp/ccdsDELB.s page 113 1126:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Disable Rx buffer not empty interrupt 1127:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR2 RXNEIE LL_SPI_DisableIT_RXNE 1128:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 1129:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None 1130:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 1131:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_DisableIT_RXNE(SPI_TypeDef *SPIx) 1132:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 1133:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** CLEAR_BIT(SPIx->CR2, SPI_CR2_RXNEIE); 1134:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1135:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 1136:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 1137:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Disable Tx buffer empty interrupt 1138:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR2 TXEIE LL_SPI_DisableIT_TXE 1139:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 1140:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None 1141:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 1142:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_DisableIT_TXE(SPI_TypeDef *SPIx) 1143:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 1144:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** CLEAR_BIT(SPIx->CR2, SPI_CR2_TXEIE); 1145:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1146:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 1147:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 1148:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Check if error interrupt is enabled 1149:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR2 ERRIE LL_SPI_IsEnabledIT_ERR 1150:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 1151:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval State of bit (1 or 0). 1152:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 1153:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_ERR(SPI_TypeDef *SPIx) 1154:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 1155:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** return ((READ_BIT(SPIx->CR2, SPI_CR2_ERRIE) == (SPI_CR2_ERRIE)) ? 1UL : 0UL); 1156:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1157:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 1158:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 1159:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Check if Rx buffer not empty interrupt is enabled 1160:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR2 RXNEIE LL_SPI_IsEnabledIT_RXNE 1161:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 1162:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval State of bit (1 or 0). 1163:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 1164:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_RXNE(SPI_TypeDef *SPIx) 1165:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 1166:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** return ((READ_BIT(SPIx->CR2, SPI_CR2_RXNEIE) == (SPI_CR2_RXNEIE)) ? 1UL : 0UL); 1167:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1168:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 1169:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 1170:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Check if Tx buffer empty interrupt 1171:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR2 TXEIE LL_SPI_IsEnabledIT_TXE 1172:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 1173:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval State of bit (1 or 0). 1174:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 1175:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_TXE(SPI_TypeDef *SPIx) 1176:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 1177:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** return ((READ_BIT(SPIx->CR2, SPI_CR2_TXEIE) == (SPI_CR2_TXEIE)) ? 1UL : 0UL); 1178:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1179:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 1180:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 1181:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @} 1182:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ ARM GAS /tmp/ccdsDELB.s page 114 1183:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 1184:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_EF_DMA_Management DMA Management 1185:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @{ 1186:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 1187:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 1188:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 1189:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Enable DMA Rx 1190:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR2 RXDMAEN LL_SPI_EnableDMAReq_RX 1191:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 1192:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None 1193:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 1194:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_EnableDMAReq_RX(SPI_TypeDef *SPIx) 1195:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 1196:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** SET_BIT(SPIx->CR2, SPI_CR2_RXDMAEN); 1197:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1198:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 1199:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 1200:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Disable DMA Rx 1201:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR2 RXDMAEN LL_SPI_DisableDMAReq_RX 1202:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 1203:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None 1204:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 1205:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_DisableDMAReq_RX(SPI_TypeDef *SPIx) 1206:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 1207:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** CLEAR_BIT(SPIx->CR2, SPI_CR2_RXDMAEN); 1208:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1209:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 1210:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 1211:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Check if DMA Rx is enabled 1212:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR2 RXDMAEN LL_SPI_IsEnabledDMAReq_RX 1213:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 1214:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval State of bit (1 or 0). 1215:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 1216:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_RX(SPI_TypeDef *SPIx) 1217:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 1218:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** return ((READ_BIT(SPIx->CR2, SPI_CR2_RXDMAEN) == (SPI_CR2_RXDMAEN)) ? 1UL : 0UL); 1219:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1220:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 1221:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 1222:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Enable DMA Tx 1223:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR2 TXDMAEN LL_SPI_EnableDMAReq_TX 1224:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 1225:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None 1226:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 1227:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_EnableDMAReq_TX(SPI_TypeDef *SPIx) 1228:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 1229:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** SET_BIT(SPIx->CR2, SPI_CR2_TXDMAEN); 1230:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1231:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 1232:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 1233:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Disable DMA Tx 1234:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR2 TXDMAEN LL_SPI_DisableDMAReq_TX 1235:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 1236:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None 1237:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 1238:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_DisableDMAReq_TX(SPI_TypeDef *SPIx) 1239:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { ARM GAS /tmp/ccdsDELB.s page 115 1240:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** CLEAR_BIT(SPIx->CR2, SPI_CR2_TXDMAEN); 1241:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1242:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 1243:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 1244:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Check if DMA Tx is enabled 1245:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR2 TXDMAEN LL_SPI_IsEnabledDMAReq_TX 1246:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 1247:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval State of bit (1 or 0). 1248:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 1249:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx) 1250:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 1251:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** return ((READ_BIT(SPIx->CR2, SPI_CR2_TXDMAEN) == (SPI_CR2_TXDMAEN)) ? 1UL : 0UL); 1252:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1253:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 1254:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 1255:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Set parity of Last DMA reception 1256:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR2 LDMARX LL_SPI_SetDMAParity_RX 1257:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 1258:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param Parity This parameter can be one of the following values: 1259:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_DMA_PARITY_ODD 1260:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_DMA_PARITY_EVEN 1261:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None 1262:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 1263:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_SetDMAParity_RX(SPI_TypeDef *SPIx, uint32_t Parity) 1264:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 1265:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** MODIFY_REG(SPIx->CR2, SPI_CR2_LDMARX, (Parity << SPI_CR2_LDMARX_Pos)); 1266:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1267:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 1268:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 1269:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Get parity configuration for Last DMA reception 1270:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR2 LDMARX LL_SPI_GetDMAParity_RX 1271:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 1272:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval Returned value can be one of the following values: 1273:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_DMA_PARITY_ODD 1274:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_DMA_PARITY_EVEN 1275:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 1276:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_GetDMAParity_RX(SPI_TypeDef *SPIx) 1277:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 1278:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_LDMARX) >> SPI_CR2_LDMARX_Pos); 1279:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1280:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 1281:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 1282:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Set parity of Last DMA transmission 1283:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR2 LDMATX LL_SPI_SetDMAParity_TX 1284:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 1285:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param Parity This parameter can be one of the following values: 1286:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_DMA_PARITY_ODD 1287:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_DMA_PARITY_EVEN 1288:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None 1289:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 1290:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_SetDMAParity_TX(SPI_TypeDef *SPIx, uint32_t Parity) 1291:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 1292:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** MODIFY_REG(SPIx->CR2, SPI_CR2_LDMATX, (Parity << SPI_CR2_LDMATX_Pos)); 1293:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1294:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 1295:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 1296:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Get parity configuration for Last DMA transmission ARM GAS /tmp/ccdsDELB.s page 116 1297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR2 LDMATX LL_SPI_GetDMAParity_TX 1298:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 1299:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval Returned value can be one of the following values: 1300:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_DMA_PARITY_ODD 1301:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_DMA_PARITY_EVEN 1302:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 1303:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_GetDMAParity_TX(SPI_TypeDef *SPIx) 1304:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 1305:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_LDMATX) >> SPI_CR2_LDMATX_Pos); 1306:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1307:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 1308:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 1309:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Get the data register address used for DMA transfer 1310:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll DR DR LL_SPI_DMA_GetRegAddr 1311:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 1312:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval Address of data register 1313:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 1314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_DMA_GetRegAddr(SPI_TypeDef *SPIx) 1315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 1316:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** return (uint32_t) &(SPIx->DR); 1317:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1318:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 1319:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 1320:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @} 1321:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 1322:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 1323:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_EF_DATA_Management DATA Management 1324:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @{ 1325:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 1326:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 1327:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 1328:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Read 8-Bits in the data register 1329:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll DR DR LL_SPI_ReceiveData8 1330:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 1331:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval RxData Value between Min_Data=0x00 and Max_Data=0xFF 1332:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 1333:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint8_t LL_SPI_ReceiveData8(SPI_TypeDef *SPIx) 1334:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 1335:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** return (*((__IO uint8_t *)&SPIx->DR)); 1336:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1337:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 1338:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 1339:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Read 16-Bits in the data register 1340:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll DR DR LL_SPI_ReceiveData16 1341:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 1342:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval RxData Value between Min_Data=0x00 and Max_Data=0xFFFF 1343:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 1344:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint16_t LL_SPI_ReceiveData16(SPI_TypeDef *SPIx) 1345:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 1346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** return (uint16_t)(READ_REG(SPIx->DR)); 1347:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1348:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 1349:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 1350:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Write 8-Bits in the data register 1351:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll DR DR LL_SPI_TransmitData8 1352:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 1353:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param TxData Value between Min_Data=0x00 and Max_Data=0xFF ARM GAS /tmp/ccdsDELB.s page 117 1354:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None 1355:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 1356:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_TransmitData8(SPI_TypeDef *SPIx, uint8_t TxData) 1357:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 1358:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #if defined (__GNUC__) 1359:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __IO uint8_t *spidr = ((__IO uint8_t *)&SPIx->DR); 1360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** *spidr = TxData; 1361:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #else 1362:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** *((__IO uint8_t *)&SPIx->DR) = TxData; 1363:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #endif /* __GNUC__ */ 1364:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1365:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 1366:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 1367:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Write 16-Bits in the data register 1368:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll DR DR LL_SPI_TransmitData16 1369:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 1370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param TxData Value between Min_Data=0x00 and Max_Data=0xFFFF 1371:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None 1372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 1373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData) 806 .loc 4 1373 22 view .LVU280 807 .LBB304: 1374:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 1375:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #if defined (__GNUC__) 1376:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __IO uint16_t *spidr = ((__IO uint16_t *)&SPIx->DR); 808 .loc 4 1376 3 view .LVU281 1377:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** *spidr = TxData; 809 .loc 4 1377 3 view .LVU282 810 .loc 4 1377 10 is_stmt 0 view .LVU283 811 0034 454B ldr r3, .L60+4 812 0036 9C81 strh r4, [r3, #12] @ movhi 813 .LVL60: 814 .loc 4 1377 10 view .LVU284 815 .LBE304: 816 .LBE303: 1806:Src/main.c **** while((!LL_SPI_IsActiveFlag_RXNE(SPI2))&&(tmp32<=500)) {tmp32++;}//When trans. last data cycle w 817 .loc 2 1806 4 is_stmt 1 view .LVU285 1807:Src/main.c **** (void) SPI2->DR; 818 .loc 2 1807 4 view .LVU286 1806:Src/main.c **** while((!LL_SPI_IsActiveFlag_RXNE(SPI2))&&(tmp32<=500)) {tmp32++;}//When trans. last data cycle w 819 .loc 2 1806 10 is_stmt 0 view .LVU287 820 0038 0022 movs r2, #0 821 .LVL61: 822 .L38: 1807:Src/main.c **** (void) SPI2->DR; 823 .loc 2 1807 9 is_stmt 1 discriminator 1 view .LVU288 824 .LBB305: 825 .LBI305: 905:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 826 .loc 4 905 26 discriminator 1 view .LVU289 827 .LBB306: 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 828 .loc 4 907 3 discriminator 1 view .LVU290 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 829 .loc 4 907 12 is_stmt 0 discriminator 1 view .LVU291 830 003a 444B ldr r3, .L60+4 831 003c 9B68 ldr r3, [r3, #8] ARM GAS /tmp/ccdsDELB.s page 118 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 832 .loc 4 907 68 discriminator 1 view .LVU292 833 003e 13F0010F tst r3, #1 834 0042 04D1 bne .L39 835 .LVL62: 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 836 .loc 4 907 68 discriminator 1 view .LVU293 837 .LBE306: 838 .LBE305: 1807:Src/main.c **** (void) SPI2->DR; 839 .loc 2 1807 43 view .LVU294 840 0044 B2F5FA7F cmp r2, #500 841 0048 01D8 bhi .L39 1807:Src/main.c **** (void) SPI2->DR; 842 .loc 2 1807 60 is_stmt 1 discriminator 3 view .LVU295 1807:Src/main.c **** (void) SPI2->DR; 843 .loc 2 1807 65 is_stmt 0 discriminator 3 view .LVU296 844 004a 0132 adds r2, r2, #1 845 .LVL63: 1807:Src/main.c **** (void) SPI2->DR; 846 .loc 2 1807 65 discriminator 3 view .LVU297 847 004c F5E7 b .L38 848 .L39: 1808:Src/main.c **** break; 849 .loc 2 1808 4 is_stmt 1 view .LVU298 850 004e 3F4B ldr r3, .L60+4 851 0050 DB68 ldr r3, [r3, #12] 1809:Src/main.c **** case 2: 852 .loc 2 1809 3 view .LVU299 853 .LVL64: 854 .L29: 1844:Src/main.c **** HAL_GPIO_WritePin(DAC_LD2_CS_GPIO_Port, DAC_LD2_CS_Pin, GPIO_PIN_SET);//End operation with LDAC2 855 .loc 2 1844 2 view .LVU300 856 0052 3D4D ldr r5, .L60 857 0054 0122 movs r2, #1 858 0056 4FF48041 mov r1, #16384 859 005a 2846 mov r0, r5 860 005c FFF7FEFF bl HAL_GPIO_WritePin 861 .LVL65: 1845:Src/main.c **** HAL_GPIO_WritePin(DAC_TEC1_CS_GPIO_Port, DAC_TEC1_CS_Pin, GPIO_PIN_SET);//End operation with TEC1 862 .loc 2 1845 2 view .LVU301 863 0060 3B4C ldr r4, .L60+8 864 0062 0122 movs r2, #1 865 0064 4021 movs r1, #64 866 0066 2046 mov r0, r4 867 0068 FFF7FEFF bl HAL_GPIO_WritePin 868 .LVL66: 1846:Src/main.c **** HAL_GPIO_WritePin(DAC_TEC2_CS_GPIO_Port, DAC_TEC2_CS_Pin, GPIO_PIN_SET);//End operation with TEC2 869 .loc 2 1846 2 view .LVU302 870 006c 0122 movs r2, #1 871 006e 4FF48051 mov r1, #4096 872 0072 2846 mov r0, r5 873 0074 FFF7FEFF bl HAL_GPIO_WritePin 874 .LVL67: 1847:Src/main.c **** } 875 .loc 2 1847 2 view .LVU303 876 0078 0122 movs r2, #1 ARM GAS /tmp/ccdsDELB.s page 119 877 007a 1021 movs r1, #16 878 007c 2046 mov r0, r4 879 007e FFF7FEFF bl HAL_GPIO_WritePin 880 .LVL68: 1848:Src/main.c **** static uint16_t MPhD_T(uint8_t num) 881 .loc 2 1848 1 is_stmt 0 view .LVU304 882 0082 38BD pop {r3, r4, r5, pc} 883 .LVL69: 884 .L33: 1811:Src/main.c **** //tmp32=0; 885 .loc 2 1811 4 is_stmt 1 view .LVU305 886 0084 0022 movs r2, #0 887 0086 4021 movs r1, #64 888 .LVL70: 1811:Src/main.c **** //tmp32=0; 889 .loc 2 1811 4 is_stmt 0 view .LVU306 890 0088 3148 ldr r0, .L60+8 891 008a FFF7FEFF bl HAL_GPIO_WritePin 892 .LVL71: 1814:Src/main.c **** while((!LL_SPI_IsActiveFlag_TXE(SPI6))&&(tmp32<=500)) {tmp32++;}//When trans. last data cycle wi 893 .loc 2 1814 4 is_stmt 1 view .LVU307 1815:Src/main.c **** LL_SPI_TransmitData16(SPI6, DATA);//Transmit word to Laser1 DAC 894 .loc 2 1815 4 view .LVU308 1814:Src/main.c **** while((!LL_SPI_IsActiveFlag_TXE(SPI6))&&(tmp32<=500)) {tmp32++;}//When trans. last data cycle wi 895 .loc 2 1814 10 is_stmt 0 view .LVU309 896 008e 0022 movs r2, #0 897 .LVL72: 898 .L41: 1815:Src/main.c **** LL_SPI_TransmitData16(SPI6, DATA);//Transmit word to Laser1 DAC 899 .loc 2 1815 9 is_stmt 1 discriminator 1 view .LVU310 900 .LBB307: 901 .LBI307: 916:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 902 .loc 4 916 26 discriminator 1 view .LVU311 903 .LBB308: 918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 904 .loc 4 918 3 discriminator 1 view .LVU312 918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 905 .loc 4 918 12 is_stmt 0 discriminator 1 view .LVU313 906 0090 304B ldr r3, .L60+12 907 0092 9B68 ldr r3, [r3, #8] 918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 908 .loc 4 918 66 discriminator 1 view .LVU314 909 0094 13F0020F tst r3, #2 910 0098 04D1 bne .L42 911 .LVL73: 918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 912 .loc 4 918 66 discriminator 1 view .LVU315 913 .LBE308: 914 .LBE307: 1815:Src/main.c **** LL_SPI_TransmitData16(SPI6, DATA);//Transmit word to Laser1 DAC 915 .loc 2 1815 42 view .LVU316 916 009a B2F5FA7F cmp r2, #500 917 009e 01D8 bhi .L42 1815:Src/main.c **** LL_SPI_TransmitData16(SPI6, DATA);//Transmit word to Laser1 DAC 918 .loc 2 1815 59 is_stmt 1 discriminator 3 view .LVU317 1815:Src/main.c **** LL_SPI_TransmitData16(SPI6, DATA);//Transmit word to Laser1 DAC ARM GAS /tmp/ccdsDELB.s page 120 919 .loc 2 1815 64 is_stmt 0 discriminator 3 view .LVU318 920 00a0 0132 adds r2, r2, #1 921 .LVL74: 1815:Src/main.c **** LL_SPI_TransmitData16(SPI6, DATA);//Transmit word to Laser1 DAC 922 .loc 2 1815 64 discriminator 3 view .LVU319 923 00a2 F5E7 b .L41 924 .L42: 1816:Src/main.c **** tmp32 = 0; 925 .loc 2 1816 4 is_stmt 1 view .LVU320 926 .LVL75: 927 .LBB309: 928 .LBI309: 1373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 929 .loc 4 1373 22 view .LVU321 930 .LBB310: 1376:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** *spidr = TxData; 931 .loc 4 1376 3 view .LVU322 932 .loc 4 1377 3 view .LVU323 933 .loc 4 1377 10 is_stmt 0 view .LVU324 934 00a4 2B4B ldr r3, .L60+12 935 00a6 9C81 strh r4, [r3, #12] @ movhi 936 .LVL76: 937 .loc 4 1377 10 view .LVU325 938 .LBE310: 939 .LBE309: 1817:Src/main.c **** while((!LL_SPI_IsActiveFlag_RXNE(SPI6))&&(tmp32<=500)) {tmp32++;}//When trans. last data cycle w 940 .loc 2 1817 4 is_stmt 1 view .LVU326 1818:Src/main.c **** (void) SPI6->DR; 941 .loc 2 1818 4 view .LVU327 1817:Src/main.c **** while((!LL_SPI_IsActiveFlag_RXNE(SPI6))&&(tmp32<=500)) {tmp32++;}//When trans. last data cycle w 942 .loc 2 1817 10 is_stmt 0 view .LVU328 943 00a8 0022 movs r2, #0 944 .LVL77: 945 .L44: 1818:Src/main.c **** (void) SPI6->DR; 946 .loc 2 1818 9 is_stmt 1 discriminator 1 view .LVU329 947 .LBB311: 948 .LBI311: 905:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 949 .loc 4 905 26 discriminator 1 view .LVU330 950 .LBB312: 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 951 .loc 4 907 3 discriminator 1 view .LVU331 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 952 .loc 4 907 12 is_stmt 0 discriminator 1 view .LVU332 953 00aa 2A4B ldr r3, .L60+12 954 00ac 9B68 ldr r3, [r3, #8] 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 955 .loc 4 907 68 discriminator 1 view .LVU333 956 00ae 13F0010F tst r3, #1 957 00b2 04D1 bne .L45 958 .LVL78: 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 959 .loc 4 907 68 discriminator 1 view .LVU334 960 .LBE312: 961 .LBE311: 1818:Src/main.c **** (void) SPI6->DR; ARM GAS /tmp/ccdsDELB.s page 121 962 .loc 2 1818 43 view .LVU335 963 00b4 B2F5FA7F cmp r2, #500 964 00b8 01D8 bhi .L45 1818:Src/main.c **** (void) SPI6->DR; 965 .loc 2 1818 60 is_stmt 1 discriminator 3 view .LVU336 1818:Src/main.c **** (void) SPI6->DR; 966 .loc 2 1818 65 is_stmt 0 discriminator 3 view .LVU337 967 00ba 0132 adds r2, r2, #1 968 .LVL79: 1818:Src/main.c **** (void) SPI6->DR; 969 .loc 2 1818 65 discriminator 3 view .LVU338 970 00bc F5E7 b .L44 971 .L45: 1819:Src/main.c **** break; 972 .loc 2 1819 4 is_stmt 1 view .LVU339 973 00be 254B ldr r3, .L60+12 974 00c0 DB68 ldr r3, [r3, #12] 1820:Src/main.c **** case 3: 975 .loc 2 1820 3 view .LVU340 976 00c2 C6E7 b .L29 977 .LVL80: 978 .L32: 1822:Src/main.c **** //tmp32=0; 979 .loc 2 1822 4 view .LVU341 980 00c4 0022 movs r2, #0 981 00c6 4FF48051 mov r1, #4096 982 .LVL81: 1822:Src/main.c **** //tmp32=0; 983 .loc 2 1822 4 is_stmt 0 view .LVU342 984 00ca 1F48 ldr r0, .L60 985 00cc FFF7FEFF bl HAL_GPIO_WritePin 986 .LVL82: 1825:Src/main.c **** while((!LL_SPI_IsActiveFlag_TXE(SPI2))&&(tmp32<=500)) {tmp32++;}//When trans. last data cycle wi 987 .loc 2 1825 4 is_stmt 1 view .LVU343 1826:Src/main.c **** LL_SPI_TransmitData16(SPI2, DATA);//Transmit word to Laser1 DAC 988 .loc 2 1826 4 view .LVU344 1825:Src/main.c **** while((!LL_SPI_IsActiveFlag_TXE(SPI2))&&(tmp32<=500)) {tmp32++;}//When trans. last data cycle wi 989 .loc 2 1825 10 is_stmt 0 view .LVU345 990 00d0 0022 movs r2, #0 991 .LVL83: 992 .L47: 1826:Src/main.c **** LL_SPI_TransmitData16(SPI2, DATA);//Transmit word to Laser1 DAC 993 .loc 2 1826 9 is_stmt 1 discriminator 1 view .LVU346 994 .LBB313: 995 .LBI313: 916:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 996 .loc 4 916 26 discriminator 1 view .LVU347 997 .LBB314: 918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 998 .loc 4 918 3 discriminator 1 view .LVU348 918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 999 .loc 4 918 12 is_stmt 0 discriminator 1 view .LVU349 1000 00d2 1E4B ldr r3, .L60+4 1001 00d4 9B68 ldr r3, [r3, #8] 918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1002 .loc 4 918 66 discriminator 1 view .LVU350 1003 00d6 13F0020F tst r3, #2 ARM GAS /tmp/ccdsDELB.s page 122 1004 00da 04D1 bne .L48 1005 .LVL84: 918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1006 .loc 4 918 66 discriminator 1 view .LVU351 1007 .LBE314: 1008 .LBE313: 1826:Src/main.c **** LL_SPI_TransmitData16(SPI2, DATA);//Transmit word to Laser1 DAC 1009 .loc 2 1826 42 view .LVU352 1010 00dc B2F5FA7F cmp r2, #500 1011 00e0 01D8 bhi .L48 1826:Src/main.c **** LL_SPI_TransmitData16(SPI2, DATA);//Transmit word to Laser1 DAC 1012 .loc 2 1826 59 is_stmt 1 discriminator 3 view .LVU353 1826:Src/main.c **** LL_SPI_TransmitData16(SPI2, DATA);//Transmit word to Laser1 DAC 1013 .loc 2 1826 64 is_stmt 0 discriminator 3 view .LVU354 1014 00e2 0132 adds r2, r2, #1 1015 .LVL85: 1826:Src/main.c **** LL_SPI_TransmitData16(SPI2, DATA);//Transmit word to Laser1 DAC 1016 .loc 2 1826 64 discriminator 3 view .LVU355 1017 00e4 F5E7 b .L47 1018 .L48: 1827:Src/main.c **** tmp32 = 0; 1019 .loc 2 1827 4 is_stmt 1 view .LVU356 1020 .LVL86: 1021 .LBB315: 1022 .LBI315: 1373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 1023 .loc 4 1373 22 view .LVU357 1024 .LBB316: 1376:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** *spidr = TxData; 1025 .loc 4 1376 3 view .LVU358 1026 .loc 4 1377 3 view .LVU359 1027 .loc 4 1377 10 is_stmt 0 view .LVU360 1028 00e6 194B ldr r3, .L60+4 1029 00e8 9C81 strh r4, [r3, #12] @ movhi 1030 .LVL87: 1031 .loc 4 1377 10 view .LVU361 1032 .LBE316: 1033 .LBE315: 1828:Src/main.c **** while((!LL_SPI_IsActiveFlag_RXNE(SPI2))&&(tmp32<=500)) {tmp32++;}//When trans. last data cycle w 1034 .loc 2 1828 4 is_stmt 1 view .LVU362 1829:Src/main.c **** (void) SPI2->DR; 1035 .loc 2 1829 4 view .LVU363 1828:Src/main.c **** while((!LL_SPI_IsActiveFlag_RXNE(SPI2))&&(tmp32<=500)) {tmp32++;}//When trans. last data cycle w 1036 .loc 2 1828 10 is_stmt 0 view .LVU364 1037 00ea 0022 movs r2, #0 1038 .LVL88: 1039 .L50: 1829:Src/main.c **** (void) SPI2->DR; 1040 .loc 2 1829 9 is_stmt 1 discriminator 1 view .LVU365 1041 .LBB317: 1042 .LBI317: 905:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 1043 .loc 4 905 26 discriminator 1 view .LVU366 1044 .LBB318: 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1045 .loc 4 907 3 discriminator 1 view .LVU367 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } ARM GAS /tmp/ccdsDELB.s page 123 1046 .loc 4 907 12 is_stmt 0 discriminator 1 view .LVU368 1047 00ec 174B ldr r3, .L60+4 1048 00ee 9B68 ldr r3, [r3, #8] 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1049 .loc 4 907 68 discriminator 1 view .LVU369 1050 00f0 13F0010F tst r3, #1 1051 00f4 04D1 bne .L51 1052 .LVL89: 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1053 .loc 4 907 68 discriminator 1 view .LVU370 1054 .LBE318: 1055 .LBE317: 1829:Src/main.c **** (void) SPI2->DR; 1056 .loc 2 1829 43 view .LVU371 1057 00f6 B2F5FA7F cmp r2, #500 1058 00fa 01D8 bhi .L51 1829:Src/main.c **** (void) SPI2->DR; 1059 .loc 2 1829 60 is_stmt 1 discriminator 3 view .LVU372 1829:Src/main.c **** (void) SPI2->DR; 1060 .loc 2 1829 65 is_stmt 0 discriminator 3 view .LVU373 1061 00fc 0132 adds r2, r2, #1 1062 .LVL90: 1829:Src/main.c **** (void) SPI2->DR; 1063 .loc 2 1829 65 discriminator 3 view .LVU374 1064 00fe F5E7 b .L50 1065 .L51: 1830:Src/main.c **** break; 1066 .loc 2 1830 4 is_stmt 1 view .LVU375 1067 0100 124B ldr r3, .L60+4 1068 0102 DB68 ldr r3, [r3, #12] 1831:Src/main.c **** case 4: 1069 .loc 2 1831 3 view .LVU376 1070 0104 A5E7 b .L29 1071 .LVL91: 1072 .L30: 1833:Src/main.c **** //tmp32=0; 1073 .loc 2 1833 4 view .LVU377 1074 0106 0022 movs r2, #0 1075 0108 1021 movs r1, #16 1076 .LVL92: 1833:Src/main.c **** //tmp32=0; 1077 .loc 2 1833 4 is_stmt 0 view .LVU378 1078 010a 1148 ldr r0, .L60+8 1079 010c FFF7FEFF bl HAL_GPIO_WritePin 1080 .LVL93: 1836:Src/main.c **** while((!LL_SPI_IsActiveFlag_TXE(SPI6))&&(tmp32<=500)) {tmp32++;}//When trans. last data cycle wi 1081 .loc 2 1836 4 is_stmt 1 view .LVU379 1837:Src/main.c **** LL_SPI_TransmitData16(SPI6, DATA);//Transmit word to Laser1 DAC 1082 .loc 2 1837 4 view .LVU380 1836:Src/main.c **** while((!LL_SPI_IsActiveFlag_TXE(SPI6))&&(tmp32<=500)) {tmp32++;}//When trans. last data cycle wi 1083 .loc 2 1836 10 is_stmt 0 view .LVU381 1084 0110 0022 movs r2, #0 1085 .LVL94: 1086 .L53: 1837:Src/main.c **** LL_SPI_TransmitData16(SPI6, DATA);//Transmit word to Laser1 DAC 1087 .loc 2 1837 9 is_stmt 1 discriminator 1 view .LVU382 1088 .LBB319: ARM GAS /tmp/ccdsDELB.s page 124 1089 .LBI319: 916:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 1090 .loc 4 916 26 discriminator 1 view .LVU383 1091 .LBB320: 918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1092 .loc 4 918 3 discriminator 1 view .LVU384 918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1093 .loc 4 918 12 is_stmt 0 discriminator 1 view .LVU385 1094 0112 104B ldr r3, .L60+12 1095 0114 9B68 ldr r3, [r3, #8] 918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1096 .loc 4 918 66 discriminator 1 view .LVU386 1097 0116 13F0020F tst r3, #2 1098 011a 04D1 bne .L54 1099 .LVL95: 918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1100 .loc 4 918 66 discriminator 1 view .LVU387 1101 .LBE320: 1102 .LBE319: 1837:Src/main.c **** LL_SPI_TransmitData16(SPI6, DATA);//Transmit word to Laser1 DAC 1103 .loc 2 1837 42 view .LVU388 1104 011c B2F5FA7F cmp r2, #500 1105 0120 01D8 bhi .L54 1837:Src/main.c **** LL_SPI_TransmitData16(SPI6, DATA);//Transmit word to Laser1 DAC 1106 .loc 2 1837 59 is_stmt 1 discriminator 3 view .LVU389 1837:Src/main.c **** LL_SPI_TransmitData16(SPI6, DATA);//Transmit word to Laser1 DAC 1107 .loc 2 1837 64 is_stmt 0 discriminator 3 view .LVU390 1108 0122 0132 adds r2, r2, #1 1109 .LVL96: 1837:Src/main.c **** LL_SPI_TransmitData16(SPI6, DATA);//Transmit word to Laser1 DAC 1110 .loc 2 1837 64 discriminator 3 view .LVU391 1111 0124 F5E7 b .L53 1112 .L54: 1838:Src/main.c **** tmp32 = 0; 1113 .loc 2 1838 4 is_stmt 1 view .LVU392 1114 .LVL97: 1115 .LBB321: 1116 .LBI321: 1373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 1117 .loc 4 1373 22 view .LVU393 1118 .LBB322: 1376:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** *spidr = TxData; 1119 .loc 4 1376 3 view .LVU394 1120 .loc 4 1377 3 view .LVU395 1121 .loc 4 1377 10 is_stmt 0 view .LVU396 1122 0126 0B4B ldr r3, .L60+12 1123 0128 9C81 strh r4, [r3, #12] @ movhi 1124 .LVL98: 1125 .loc 4 1377 10 view .LVU397 1126 .LBE322: 1127 .LBE321: 1839:Src/main.c **** while((!LL_SPI_IsActiveFlag_RXNE(SPI6))&&(tmp32<=500)) {tmp32++;}//When trans. last data cycle w 1128 .loc 2 1839 4 is_stmt 1 view .LVU398 1840:Src/main.c **** (void) SPI6->DR; 1129 .loc 2 1840 4 view .LVU399 1839:Src/main.c **** while((!LL_SPI_IsActiveFlag_RXNE(SPI6))&&(tmp32<=500)) {tmp32++;}//When trans. last data cycle w 1130 .loc 2 1839 10 is_stmt 0 view .LVU400 ARM GAS /tmp/ccdsDELB.s page 125 1131 012a 0022 movs r2, #0 1132 .LVL99: 1133 .L56: 1840:Src/main.c **** (void) SPI6->DR; 1134 .loc 2 1840 9 is_stmt 1 discriminator 1 view .LVU401 1135 .LBB323: 1136 .LBI323: 905:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 1137 .loc 4 905 26 discriminator 1 view .LVU402 1138 .LBB324: 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1139 .loc 4 907 3 discriminator 1 view .LVU403 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1140 .loc 4 907 12 is_stmt 0 discriminator 1 view .LVU404 1141 012c 094B ldr r3, .L60+12 1142 012e 9B68 ldr r3, [r3, #8] 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1143 .loc 4 907 68 discriminator 1 view .LVU405 1144 0130 13F0010F tst r3, #1 1145 0134 04D1 bne .L57 1146 .LVL100: 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1147 .loc 4 907 68 discriminator 1 view .LVU406 1148 .LBE324: 1149 .LBE323: 1840:Src/main.c **** (void) SPI6->DR; 1150 .loc 2 1840 43 view .LVU407 1151 0136 B2F5FA7F cmp r2, #500 1152 013a 01D8 bhi .L57 1840:Src/main.c **** (void) SPI6->DR; 1153 .loc 2 1840 60 is_stmt 1 discriminator 3 view .LVU408 1840:Src/main.c **** (void) SPI6->DR; 1154 .loc 2 1840 65 is_stmt 0 discriminator 3 view .LVU409 1155 013c 0132 adds r2, r2, #1 1156 .LVL101: 1840:Src/main.c **** (void) SPI6->DR; 1157 .loc 2 1840 65 discriminator 3 view .LVU410 1158 013e F5E7 b .L56 1159 .L57: 1841:Src/main.c **** break; 1160 .loc 2 1841 4 is_stmt 1 view .LVU411 1161 0140 044B ldr r3, .L60+12 1162 0142 DB68 ldr r3, [r3, #12] 1842:Src/main.c **** } 1163 .loc 2 1842 3 view .LVU412 1164 0144 85E7 b .L29 1165 .L61: 1166 0146 00BF .align 2 1167 .L60: 1168 0148 00040240 .word 1073873920 1169 014c 00380040 .word 1073756160 1170 0150 00000240 .word 1073872896 1171 0154 00540140 .word 1073828864 1172 .cfi_endproc 1173 .LFE1206: 1175 .section .text.MPhD_T,"ax",%progbits 1176 .align 1 ARM GAS /tmp/ccdsDELB.s page 126 1177 .syntax unified 1178 .thumb 1179 .thumb_func 1180 .fpu fpv5-d16 1182 MPhD_T: 1183 .LVL102: 1184 .LFB1207: 1850:Src/main.c **** uint16_t P; 1185 .loc 2 1850 1 view -0 1186 .cfi_startproc 1187 @ args = 0, pretend = 0, frame = 0 1188 @ frame_needed = 0, uses_anonymous_args = 0 1850:Src/main.c **** uint16_t P; 1189 .loc 2 1850 1 is_stmt 0 view .LVU414 1190 0000 38B5 push {r3, r4, r5, lr} 1191 .LCFI9: 1192 .cfi_def_cfa_offset 16 1193 .cfi_offset 3, -16 1194 .cfi_offset 4, -12 1195 .cfi_offset 5, -8 1196 .cfi_offset 14, -4 1197 0002 0446 mov r4, r0 1851:Src/main.c **** uint32_t tmp32; 1198 .loc 2 1851 2 is_stmt 1 view .LVU415 1852:Src/main.c **** HAL_GPIO_WritePin(SPI4_CNV_GPIO_Port, SPI4_CNV_Pin, GPIO_PIN_RESET);//Prepare conversion 1199 .loc 2 1852 2 view .LVU416 1853:Src/main.c **** HAL_GPIO_WritePin(SPI5_CNV_GPIO_Port, SPI5_CNV_Pin, GPIO_PIN_RESET);//Prepare conversion 1200 .loc 2 1853 2 view .LVU417 1201 0004 0022 movs r2, #0 1202 0006 4FF48041 mov r1, #16384 1203 000a 8248 ldr r0, .L106 1204 .LVL103: 1853:Src/main.c **** HAL_GPIO_WritePin(SPI5_CNV_GPIO_Port, SPI5_CNV_Pin, GPIO_PIN_RESET);//Prepare conversion 1205 .loc 2 1853 2 is_stmt 0 view .LVU418 1206 000c FFF7FEFF bl HAL_GPIO_WritePin 1207 .LVL104: 1854:Src/main.c **** tmp32=0; 1208 .loc 2 1854 2 is_stmt 1 view .LVU419 1209 0010 0022 movs r2, #0 1210 0012 4FF40071 mov r1, #512 1211 0016 8048 ldr r0, .L106+4 1212 0018 FFF7FEFF bl HAL_GPIO_WritePin 1213 .LVL105: 1855:Src/main.c **** while(tmp32<500){tmp32++;} 1214 .loc 2 1855 2 view .LVU420 1856:Src/main.c **** HAL_GPIO_WritePin(SPI4_CNV_GPIO_Port, SPI4_CNV_Pin, GPIO_PIN_SET);//Stop acqusition & start conver 1215 .loc 2 1856 2 view .LVU421 1855:Src/main.c **** while(tmp32<500){tmp32++;} 1216 .loc 2 1855 7 is_stmt 0 view .LVU422 1217 001c 0023 movs r3, #0 1856:Src/main.c **** HAL_GPIO_WritePin(SPI4_CNV_GPIO_Port, SPI4_CNV_Pin, GPIO_PIN_SET);//Stop acqusition & start conver 1218 .loc 2 1856 7 view .LVU423 1219 001e 00E0 b .L63 1220 .LVL106: 1221 .L64: 1856:Src/main.c **** HAL_GPIO_WritePin(SPI4_CNV_GPIO_Port, SPI4_CNV_Pin, GPIO_PIN_SET);//Stop acqusition & start conver 1222 .loc 2 1856 19 is_stmt 1 discriminator 2 view .LVU424 ARM GAS /tmp/ccdsDELB.s page 127 1856:Src/main.c **** HAL_GPIO_WritePin(SPI4_CNV_GPIO_Port, SPI4_CNV_Pin, GPIO_PIN_SET);//Stop acqusition & start conver 1223 .loc 2 1856 24 is_stmt 0 discriminator 2 view .LVU425 1224 0020 0133 adds r3, r3, #1 1225 .LVL107: 1226 .L63: 1856:Src/main.c **** HAL_GPIO_WritePin(SPI4_CNV_GPIO_Port, SPI4_CNV_Pin, GPIO_PIN_SET);//Stop acqusition & start conver 1227 .loc 2 1856 7 is_stmt 1 discriminator 1 view .LVU426 1228 0022 B3F5FA7F cmp r3, #500 1229 0026 FBD3 bcc .L64 1857:Src/main.c **** HAL_GPIO_WritePin(SPI5_CNV_GPIO_Port, SPI5_CNV_Pin, GPIO_PIN_SET);//Stop acqusition & start conver 1230 .loc 2 1857 2 view .LVU427 1231 0028 0122 movs r2, #1 1232 002a 4FF48041 mov r1, #16384 1233 002e 7948 ldr r0, .L106 1234 0030 FFF7FEFF bl HAL_GPIO_WritePin 1235 .LVL108: 1858:Src/main.c **** tmp32=0; 1236 .loc 2 1858 2 view .LVU428 1237 0034 0122 movs r2, #1 1238 0036 4FF40071 mov r1, #512 1239 003a 7748 ldr r0, .L106+4 1240 003c FFF7FEFF bl HAL_GPIO_WritePin 1241 .LVL109: 1859:Src/main.c **** while(tmp32<500){tmp32++;} 1242 .loc 2 1859 2 view .LVU429 1860:Src/main.c **** if (num==1)//MPD1 1243 .loc 2 1860 2 view .LVU430 1859:Src/main.c **** while(tmp32<500){tmp32++;} 1244 .loc 2 1859 7 is_stmt 0 view .LVU431 1245 0040 0023 movs r3, #0 1860:Src/main.c **** if (num==1)//MPD1 1246 .loc 2 1860 7 view .LVU432 1247 0042 00E0 b .L65 1248 .LVL110: 1249 .L66: 1860:Src/main.c **** if (num==1)//MPD1 1250 .loc 2 1860 19 is_stmt 1 discriminator 2 view .LVU433 1860:Src/main.c **** if (num==1)//MPD1 1251 .loc 2 1860 24 is_stmt 0 discriminator 2 view .LVU434 1252 0044 0133 adds r3, r3, #1 1253 .LVL111: 1254 .L65: 1860:Src/main.c **** if (num==1)//MPD1 1255 .loc 2 1860 7 is_stmt 1 discriminator 1 view .LVU435 1256 0046 B3F5FA7F cmp r3, #500 1257 004a FBD3 bcc .L66 1861:Src/main.c **** { 1258 .loc 2 1861 2 view .LVU436 1861:Src/main.c **** { 1259 .loc 2 1861 5 is_stmt 0 view .LVU437 1260 004c 012C cmp r4, #1 1261 004e 08D0 beq .L100 1877:Src/main.c **** { 1262 .loc 2 1877 7 is_stmt 1 view .LVU438 1877:Src/main.c **** { 1263 .loc 2 1877 10 is_stmt 0 view .LVU439 1264 0050 022C cmp r4, #2 ARM GAS /tmp/ccdsDELB.s page 128 1265 0052 3DD0 beq .L101 1893:Src/main.c **** { 1266 .loc 2 1893 7 is_stmt 1 view .LVU440 1893:Src/main.c **** { 1267 .loc 2 1893 10 is_stmt 0 view .LVU441 1268 0054 032C cmp r4, #3 1269 0056 70D0 beq .L102 1909:Src/main.c **** { 1270 .loc 2 1909 7 is_stmt 1 view .LVU442 1909:Src/main.c **** { 1271 .loc 2 1909 10 is_stmt 0 view .LVU443 1272 0058 042C cmp r4, #4 1273 005a 00F0A580 beq .L103 1274 .LVL112: 1275 .L75: 1947:Src/main.c **** } 1276 .loc 2 1947 2 is_stmt 1 view .LVU444 1948:Src/main.c **** /*static uint16_t Temp_LD(uint16_t T_LD_before, uint16_t T_LD, uint32_t Timer_before, uint32_t Time 1277 .loc 2 1948 1 is_stmt 0 view .LVU445 1278 005e 2846 mov r0, r5 1279 0060 38BD pop {r3, r4, r5, pc} 1280 .LVL113: 1281 .L100: 1863:Src/main.c **** HAL_GPIO_WritePin(ADC_MPD1_CS_GPIO_Port, ADC_MPD1_CS_Pin, GPIO_PIN_RESET); 1282 .loc 2 1863 3 is_stmt 1 view .LVU446 1283 0062 6C4C ldr r4, .L106 1284 0064 0122 movs r2, #1 1285 0066 4FF40061 mov r1, #2048 1286 006a 2046 mov r0, r4 1287 006c FFF7FEFF bl HAL_GPIO_WritePin 1288 .LVL114: 1864:Src/main.c **** tmp32=0; 1289 .loc 2 1864 3 view .LVU447 1290 0070 0022 movs r2, #0 1291 0072 4FF48061 mov r1, #1024 1292 0076 2046 mov r0, r4 1293 0078 FFF7FEFF bl HAL_GPIO_WritePin 1294 .LVL115: 1865:Src/main.c **** while(tmp32<500){tmp32++;} 1295 .loc 2 1865 3 view .LVU448 1866:Src/main.c **** //LL_SPI_TransmitData16(SPI4, 0xFFFF);//We must to clock the CLK output for collect RX data. We c 1296 .loc 2 1866 3 view .LVU449 1865:Src/main.c **** while(tmp32<500){tmp32++;} 1297 .loc 2 1865 8 is_stmt 0 view .LVU450 1298 007c 0023 movs r3, #0 1866:Src/main.c **** //LL_SPI_TransmitData16(SPI4, 0xFFFF);//We must to clock the CLK output for collect RX data. We c 1299 .loc 2 1866 8 view .LVU451 1300 007e 00E0 b .L68 1301 .LVL116: 1302 .L69: 1866:Src/main.c **** //LL_SPI_TransmitData16(SPI4, 0xFFFF);//We must to clock the CLK output for collect RX data. We c 1303 .loc 2 1866 20 is_stmt 1 discriminator 2 view .LVU452 1866:Src/main.c **** //LL_SPI_TransmitData16(SPI4, 0xFFFF);//We must to clock the CLK output for collect RX data. We c 1304 .loc 2 1866 25 is_stmt 0 discriminator 2 view .LVU453 1305 0080 0133 adds r3, r3, #1 1306 .LVL117: 1307 .L68: ARM GAS /tmp/ccdsDELB.s page 129 1866:Src/main.c **** //LL_SPI_TransmitData16(SPI4, 0xFFFF);//We must to clock the CLK output for collect RX data. We c 1308 .loc 2 1866 8 is_stmt 1 discriminator 1 view .LVU454 1309 0082 B3F5FA7F cmp r3, #500 1310 0086 FBD3 bcc .L69 1868:Src/main.c **** tmp32 = 0; 1311 .loc 2 1868 3 view .LVU455 1312 .LVL118: 1313 .LBB325: 1314 .LBI325: 358:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 1315 .loc 4 358 22 view .LVU456 1316 .LBB326: 360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1317 .loc 4 360 3 view .LVU457 1318 0088 644A ldr r2, .L106+8 1319 008a 1368 ldr r3, [r2] 1320 .LVL119: 360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1321 .loc 4 360 3 is_stmt 0 view .LVU458 1322 008c 43F04003 orr r3, r3, #64 1323 0090 1360 str r3, [r2] 1324 .LVL120: 360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1325 .loc 4 360 3 view .LVU459 1326 .LBE326: 1327 .LBE325: 1869:Src/main.c **** while(((!LL_SPI_IsActiveFlag_RXNE(SPI4))&&(tmp32<=1000))) {tmp32++;}//When rec. last data cycle w 1328 .loc 2 1869 3 is_stmt 1 view .LVU460 1870:Src/main.c **** LL_SPI_Disable(SPI4);//Enable SPI for MPhD1 ADC 1329 .loc 2 1870 3 view .LVU461 1869:Src/main.c **** while(((!LL_SPI_IsActiveFlag_RXNE(SPI4))&&(tmp32<=1000))) {tmp32++;}//When rec. last data cycle w 1330 .loc 2 1869 9 is_stmt 0 view .LVU462 1331 0092 0023 movs r3, #0 1332 .LVL121: 1333 .L70: 1870:Src/main.c **** LL_SPI_Disable(SPI4);//Enable SPI for MPhD1 ADC 1334 .loc 2 1870 8 is_stmt 1 discriminator 1 view .LVU463 1335 .LBB327: 1336 .LBI327: 905:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 1337 .loc 4 905 26 discriminator 1 view .LVU464 1338 .LBB328: 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1339 .loc 4 907 3 discriminator 1 view .LVU465 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1340 .loc 4 907 12 is_stmt 0 discriminator 1 view .LVU466 1341 0094 614A ldr r2, .L106+8 1342 0096 9268 ldr r2, [r2, #8] 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1343 .loc 4 907 68 discriminator 1 view .LVU467 1344 0098 12F0010F tst r2, #1 1345 009c 04D1 bne .L71 1346 .LVL122: 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1347 .loc 4 907 68 discriminator 1 view .LVU468 1348 .LBE328: 1349 .LBE327: ARM GAS /tmp/ccdsDELB.s page 130 1870:Src/main.c **** LL_SPI_Disable(SPI4);//Enable SPI for MPhD1 ADC 1350 .loc 2 1870 43 view .LVU469 1351 009e B3F57A7F cmp r3, #1000 1352 00a2 01D8 bhi .L71 1870:Src/main.c **** LL_SPI_Disable(SPI4);//Enable SPI for MPhD1 ADC 1353 .loc 2 1870 62 is_stmt 1 discriminator 3 view .LVU470 1870:Src/main.c **** LL_SPI_Disable(SPI4);//Enable SPI for MPhD1 ADC 1354 .loc 2 1870 67 is_stmt 0 discriminator 3 view .LVU471 1355 00a4 0133 adds r3, r3, #1 1356 .LVL123: 1870:Src/main.c **** LL_SPI_Disable(SPI4);//Enable SPI for MPhD1 ADC 1357 .loc 2 1870 67 discriminator 3 view .LVU472 1358 00a6 F5E7 b .L70 1359 .L71: 1871:Src/main.c **** while(tmp32<500){tmp32++;} 1360 .loc 2 1871 3 is_stmt 1 view .LVU473 1361 .LVL124: 1362 .LBB329: 1363 .LBI329: 370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 1364 .loc 4 370 22 view .LVU474 1365 .LBB330: 372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1366 .loc 4 372 3 view .LVU475 1367 00a8 5C49 ldr r1, .L106+8 1368 00aa 0A68 ldr r2, [r1] 1369 00ac 22F04002 bic r2, r2, #64 1370 00b0 0A60 str r2, [r1] 373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 1371 .loc 4 373 1 is_stmt 0 view .LVU476 1372 00b2 00E0 b .L73 1373 .LVL125: 1374 .L74: 373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 1375 .loc 4 373 1 view .LVU477 1376 .LBE330: 1377 .LBE329: 1872:Src/main.c **** //HAL_SPI_Receive(&hspi4, &P[0], 1, 100); 1378 .loc 2 1872 20 is_stmt 1 discriminator 2 view .LVU478 1872:Src/main.c **** //HAL_SPI_Receive(&hspi4, &P[0], 1, 100); 1379 .loc 2 1872 25 is_stmt 0 discriminator 2 view .LVU479 1380 00b4 0133 adds r3, r3, #1 1381 .LVL126: 1382 .L73: 1872:Src/main.c **** //HAL_SPI_Receive(&hspi4, &P[0], 1, 100); 1383 .loc 2 1872 8 is_stmt 1 discriminator 1 view .LVU480 1384 00b6 B3F5FA7F cmp r3, #500 1385 00ba FBD3 bcc .L74 1874:Src/main.c **** P = LL_SPI_ReceiveData16(SPI4); 1386 .loc 2 1874 3 view .LVU481 1387 00bc 0122 movs r2, #1 1388 00be 4FF48061 mov r1, #1024 1389 00c2 5448 ldr r0, .L106 1390 00c4 FFF7FEFF bl HAL_GPIO_WritePin 1391 .LVL127: 1875:Src/main.c **** } 1392 .loc 2 1875 3 view .LVU482 ARM GAS /tmp/ccdsDELB.s page 131 1393 .LBB331: 1394 .LBI331: 1344:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 1395 .loc 4 1344 26 view .LVU483 1396 .LBB332: 1346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1397 .loc 4 1346 3 view .LVU484 1346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1398 .loc 4 1346 21 is_stmt 0 view .LVU485 1399 00c8 544B ldr r3, .L106+8 1400 00ca DD68 ldr r5, [r3, #12] 1346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1401 .loc 4 1346 10 view .LVU486 1402 00cc ADB2 uxth r5, r5 1403 .LVL128: 1346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1404 .loc 4 1346 10 view .LVU487 1405 .LBE332: 1406 .LBE331: 1407 00ce C6E7 b .L75 1408 .LVL129: 1409 .L101: 1879:Src/main.c **** HAL_GPIO_WritePin(ADC_MPD2_CS_GPIO_Port, ADC_MPD2_CS_Pin, GPIO_PIN_RESET); 1410 .loc 2 1879 3 is_stmt 1 view .LVU488 1411 00d0 514C ldr r4, .L106+4 1412 00d2 0122 movs r2, #1 1413 00d4 4FF48061 mov r1, #1024 1414 00d8 2046 mov r0, r4 1415 00da FFF7FEFF bl HAL_GPIO_WritePin 1416 .LVL130: 1880:Src/main.c **** tmp32=0; 1417 .loc 2 1880 3 view .LVU489 1418 00de 0022 movs r2, #0 1419 00e0 4021 movs r1, #64 1420 00e2 2046 mov r0, r4 1421 00e4 FFF7FEFF bl HAL_GPIO_WritePin 1422 .LVL131: 1881:Src/main.c **** while(tmp32<500){tmp32++;} 1423 .loc 2 1881 3 view .LVU490 1882:Src/main.c **** //LL_SPI_TransmitData16(SPI5, 0xFFFF);//We must to clock the CLK output for collect RX data. We c 1424 .loc 2 1882 3 view .LVU491 1881:Src/main.c **** while(tmp32<500){tmp32++;} 1425 .loc 2 1881 8 is_stmt 0 view .LVU492 1426 00e8 0023 movs r3, #0 1882:Src/main.c **** //LL_SPI_TransmitData16(SPI5, 0xFFFF);//We must to clock the CLK output for collect RX data. We c 1427 .loc 2 1882 8 view .LVU493 1428 00ea 00E0 b .L77 1429 .LVL132: 1430 .L78: 1882:Src/main.c **** //LL_SPI_TransmitData16(SPI5, 0xFFFF);//We must to clock the CLK output for collect RX data. We c 1431 .loc 2 1882 20 is_stmt 1 discriminator 2 view .LVU494 1882:Src/main.c **** //LL_SPI_TransmitData16(SPI5, 0xFFFF);//We must to clock the CLK output for collect RX data. We c 1432 .loc 2 1882 25 is_stmt 0 discriminator 2 view .LVU495 1433 00ec 0133 adds r3, r3, #1 1434 .LVL133: 1435 .L77: 1882:Src/main.c **** //LL_SPI_TransmitData16(SPI5, 0xFFFF);//We must to clock the CLK output for collect RX data. We c ARM GAS /tmp/ccdsDELB.s page 132 1436 .loc 2 1882 8 is_stmt 1 discriminator 1 view .LVU496 1437 00ee B3F5FA7F cmp r3, #500 1438 00f2 FBD3 bcc .L78 1884:Src/main.c **** tmp32 = 0; 1439 .loc 2 1884 3 view .LVU497 1440 .LVL134: 1441 .LBB333: 1442 .LBI333: 358:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 1443 .loc 4 358 22 view .LVU498 1444 .LBB334: 360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1445 .loc 4 360 3 view .LVU499 1446 00f4 4A4A ldr r2, .L106+12 1447 00f6 1368 ldr r3, [r2] 1448 .LVL135: 360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1449 .loc 4 360 3 is_stmt 0 view .LVU500 1450 00f8 43F04003 orr r3, r3, #64 1451 00fc 1360 str r3, [r2] 1452 .LVL136: 360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1453 .loc 4 360 3 view .LVU501 1454 .LBE334: 1455 .LBE333: 1885:Src/main.c **** while(((!LL_SPI_IsActiveFlag_RXNE(SPI5))&&(tmp32<=1000))) {tmp32++;}//When rec. last data cycle w 1456 .loc 2 1885 3 is_stmt 1 view .LVU502 1886:Src/main.c **** LL_SPI_Disable(SPI5);//Enable SPI for MPhD2 ADC 1457 .loc 2 1886 3 view .LVU503 1885:Src/main.c **** while(((!LL_SPI_IsActiveFlag_RXNE(SPI5))&&(tmp32<=1000))) {tmp32++;}//When rec. last data cycle w 1458 .loc 2 1885 9 is_stmt 0 view .LVU504 1459 00fe 0023 movs r3, #0 1460 .LVL137: 1461 .L79: 1886:Src/main.c **** LL_SPI_Disable(SPI5);//Enable SPI for MPhD2 ADC 1462 .loc 2 1886 8 is_stmt 1 discriminator 1 view .LVU505 1463 .LBB335: 1464 .LBI335: 905:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 1465 .loc 4 905 26 discriminator 1 view .LVU506 1466 .LBB336: 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1467 .loc 4 907 3 discriminator 1 view .LVU507 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1468 .loc 4 907 12 is_stmt 0 discriminator 1 view .LVU508 1469 0100 474A ldr r2, .L106+12 1470 0102 9268 ldr r2, [r2, #8] 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1471 .loc 4 907 68 discriminator 1 view .LVU509 1472 0104 12F0010F tst r2, #1 1473 0108 04D1 bne .L80 1474 .LVL138: 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1475 .loc 4 907 68 discriminator 1 view .LVU510 1476 .LBE336: 1477 .LBE335: 1886:Src/main.c **** LL_SPI_Disable(SPI5);//Enable SPI for MPhD2 ADC ARM GAS /tmp/ccdsDELB.s page 133 1478 .loc 2 1886 43 view .LVU511 1479 010a B3F57A7F cmp r3, #1000 1480 010e 01D8 bhi .L80 1886:Src/main.c **** LL_SPI_Disable(SPI5);//Enable SPI for MPhD2 ADC 1481 .loc 2 1886 62 is_stmt 1 discriminator 3 view .LVU512 1886:Src/main.c **** LL_SPI_Disable(SPI5);//Enable SPI for MPhD2 ADC 1482 .loc 2 1886 67 is_stmt 0 discriminator 3 view .LVU513 1483 0110 0133 adds r3, r3, #1 1484 .LVL139: 1886:Src/main.c **** LL_SPI_Disable(SPI5);//Enable SPI for MPhD2 ADC 1485 .loc 2 1886 67 discriminator 3 view .LVU514 1486 0112 F5E7 b .L79 1487 .L80: 1887:Src/main.c **** while(tmp32<500){tmp32++;} 1488 .loc 2 1887 3 is_stmt 1 view .LVU515 1489 .LVL140: 1490 .LBB337: 1491 .LBI337: 370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 1492 .loc 4 370 22 view .LVU516 1493 .LBB338: 372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1494 .loc 4 372 3 view .LVU517 1495 0114 4249 ldr r1, .L106+12 1496 0116 0A68 ldr r2, [r1] 1497 0118 22F04002 bic r2, r2, #64 1498 011c 0A60 str r2, [r1] 373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 1499 .loc 4 373 1 is_stmt 0 view .LVU518 1500 011e 00E0 b .L82 1501 .LVL141: 1502 .L83: 373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 1503 .loc 4 373 1 view .LVU519 1504 .LBE338: 1505 .LBE337: 1888:Src/main.c **** //HAL_SPI_Receive(&hspi4, &P[0], 1, 100); 1506 .loc 2 1888 20 is_stmt 1 discriminator 2 view .LVU520 1888:Src/main.c **** //HAL_SPI_Receive(&hspi4, &P[0], 1, 100); 1507 .loc 2 1888 25 is_stmt 0 discriminator 2 view .LVU521 1508 0120 0133 adds r3, r3, #1 1509 .LVL142: 1510 .L82: 1888:Src/main.c **** //HAL_SPI_Receive(&hspi4, &P[0], 1, 100); 1511 .loc 2 1888 8 is_stmt 1 discriminator 1 view .LVU522 1512 0122 B3F5FA7F cmp r3, #500 1513 0126 FBD3 bcc .L83 1890:Src/main.c **** P = LL_SPI_ReceiveData16(SPI5); 1514 .loc 2 1890 3 view .LVU523 1515 0128 0122 movs r2, #1 1516 012a 4021 movs r1, #64 1517 012c 3A48 ldr r0, .L106+4 1518 012e FFF7FEFF bl HAL_GPIO_WritePin 1519 .LVL143: 1891:Src/main.c **** } 1520 .loc 2 1891 3 view .LVU524 1521 .LBB339: ARM GAS /tmp/ccdsDELB.s page 134 1522 .LBI339: 1344:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 1523 .loc 4 1344 26 view .LVU525 1524 .LBB340: 1346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1525 .loc 4 1346 3 view .LVU526 1346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1526 .loc 4 1346 21 is_stmt 0 view .LVU527 1527 0132 3B4B ldr r3, .L106+12 1528 0134 DD68 ldr r5, [r3, #12] 1346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1529 .loc 4 1346 10 view .LVU528 1530 0136 ADB2 uxth r5, r5 1531 .LVL144: 1346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1532 .loc 4 1346 10 view .LVU529 1533 .LBE340: 1534 .LBE339: 1535 0138 91E7 b .L75 1536 .LVL145: 1537 .L102: 1895:Src/main.c **** HAL_GPIO_WritePin(ADC_ThrLD1_CS_GPIO_Port, ADC_ThrLD1_CS_Pin, GPIO_PIN_RESET); 1538 .loc 2 1895 3 is_stmt 1 view .LVU530 1539 013a 364C ldr r4, .L106 1540 013c 0122 movs r2, #1 1541 013e 4FF48061 mov r1, #1024 1542 0142 2046 mov r0, r4 1543 0144 FFF7FEFF bl HAL_GPIO_WritePin 1544 .LVL146: 1896:Src/main.c **** tmp32=0; 1545 .loc 2 1896 3 view .LVU531 1546 0148 0022 movs r2, #0 1547 014a 4FF40061 mov r1, #2048 1548 014e 2046 mov r0, r4 1549 0150 FFF7FEFF bl HAL_GPIO_WritePin 1550 .LVL147: 1897:Src/main.c **** while(tmp32<500){tmp32++;} 1551 .loc 2 1897 3 view .LVU532 1898:Src/main.c **** //LL_SPI_TransmitData16(SPI4, 0xFFFF);//We must to clock the CLK output for collect RX data. We c 1552 .loc 2 1898 3 view .LVU533 1897:Src/main.c **** while(tmp32<500){tmp32++;} 1553 .loc 2 1897 8 is_stmt 0 view .LVU534 1554 0154 0023 movs r3, #0 1898:Src/main.c **** //LL_SPI_TransmitData16(SPI4, 0xFFFF);//We must to clock the CLK output for collect RX data. We c 1555 .loc 2 1898 8 view .LVU535 1556 0156 00E0 b .L85 1557 .LVL148: 1558 .L86: 1898:Src/main.c **** //LL_SPI_TransmitData16(SPI4, 0xFFFF);//We must to clock the CLK output for collect RX data. We c 1559 .loc 2 1898 20 is_stmt 1 discriminator 2 view .LVU536 1898:Src/main.c **** //LL_SPI_TransmitData16(SPI4, 0xFFFF);//We must to clock the CLK output for collect RX data. We c 1560 .loc 2 1898 25 is_stmt 0 discriminator 2 view .LVU537 1561 0158 0133 adds r3, r3, #1 1562 .LVL149: 1563 .L85: 1898:Src/main.c **** //LL_SPI_TransmitData16(SPI4, 0xFFFF);//We must to clock the CLK output for collect RX data. We c 1564 .loc 2 1898 8 is_stmt 1 discriminator 1 view .LVU538 ARM GAS /tmp/ccdsDELB.s page 135 1565 015a B3F5FA7F cmp r3, #500 1566 015e FBD3 bcc .L86 1900:Src/main.c **** tmp32 = 0; 1567 .loc 2 1900 3 view .LVU539 1568 .LVL150: 1569 .LBB341: 1570 .LBI341: 358:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 1571 .loc 4 358 22 view .LVU540 1572 .LBB342: 360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1573 .loc 4 360 3 view .LVU541 1574 0160 2E4A ldr r2, .L106+8 1575 0162 1368 ldr r3, [r2] 1576 .LVL151: 360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1577 .loc 4 360 3 is_stmt 0 view .LVU542 1578 0164 43F04003 orr r3, r3, #64 1579 0168 1360 str r3, [r2] 1580 .LVL152: 360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1581 .loc 4 360 3 view .LVU543 1582 .LBE342: 1583 .LBE341: 1901:Src/main.c **** while(((!LL_SPI_IsActiveFlag_RXNE(SPI4))&&(tmp32<=1000))) {tmp32++;}//When rec. last data cycle w 1584 .loc 2 1901 3 is_stmt 1 view .LVU544 1902:Src/main.c **** LL_SPI_Disable(SPI4);//Enable SPI for ThrLD1 ADC 1585 .loc 2 1902 3 view .LVU545 1901:Src/main.c **** while(((!LL_SPI_IsActiveFlag_RXNE(SPI4))&&(tmp32<=1000))) {tmp32++;}//When rec. last data cycle w 1586 .loc 2 1901 9 is_stmt 0 view .LVU546 1587 016a 0023 movs r3, #0 1588 .LVL153: 1589 .L87: 1902:Src/main.c **** LL_SPI_Disable(SPI4);//Enable SPI for ThrLD1 ADC 1590 .loc 2 1902 8 is_stmt 1 discriminator 1 view .LVU547 1591 .LBB343: 1592 .LBI343: 905:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 1593 .loc 4 905 26 discriminator 1 view .LVU548 1594 .LBB344: 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1595 .loc 4 907 3 discriminator 1 view .LVU549 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1596 .loc 4 907 12 is_stmt 0 discriminator 1 view .LVU550 1597 016c 2B4A ldr r2, .L106+8 1598 016e 9268 ldr r2, [r2, #8] 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1599 .loc 4 907 68 discriminator 1 view .LVU551 1600 0170 12F0010F tst r2, #1 1601 0174 04D1 bne .L88 1602 .LVL154: 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1603 .loc 4 907 68 discriminator 1 view .LVU552 1604 .LBE344: 1605 .LBE343: 1902:Src/main.c **** LL_SPI_Disable(SPI4);//Enable SPI for ThrLD1 ADC 1606 .loc 2 1902 43 view .LVU553 ARM GAS /tmp/ccdsDELB.s page 136 1607 0176 B3F57A7F cmp r3, #1000 1608 017a 01D8 bhi .L88 1902:Src/main.c **** LL_SPI_Disable(SPI4);//Enable SPI for ThrLD1 ADC 1609 .loc 2 1902 62 is_stmt 1 discriminator 3 view .LVU554 1902:Src/main.c **** LL_SPI_Disable(SPI4);//Enable SPI for ThrLD1 ADC 1610 .loc 2 1902 67 is_stmt 0 discriminator 3 view .LVU555 1611 017c 0133 adds r3, r3, #1 1612 .LVL155: 1902:Src/main.c **** LL_SPI_Disable(SPI4);//Enable SPI for ThrLD1 ADC 1613 .loc 2 1902 67 discriminator 3 view .LVU556 1614 017e F5E7 b .L87 1615 .L88: 1903:Src/main.c **** while(tmp32<500){tmp32++;} 1616 .loc 2 1903 3 is_stmt 1 view .LVU557 1617 .LVL156: 1618 .LBB345: 1619 .LBI345: 370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 1620 .loc 4 370 22 view .LVU558 1621 .LBB346: 372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1622 .loc 4 372 3 view .LVU559 1623 0180 2649 ldr r1, .L106+8 1624 0182 0A68 ldr r2, [r1] 1625 0184 22F04002 bic r2, r2, #64 1626 0188 0A60 str r2, [r1] 1627 .LVL157: 1628 .L90: 372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1629 .loc 4 372 3 is_stmt 0 view .LVU560 1630 .LBE346: 1631 .LBE345: 1904:Src/main.c **** //HAL_SPI_Receive(&hspi4, &P[0], 1, 100); 1632 .loc 2 1904 8 is_stmt 1 discriminator 1 view .LVU561 1633 018a B3F5FA7F cmp r3, #500 1634 018e 01D2 bcs .L104 1904:Src/main.c **** //HAL_SPI_Receive(&hspi4, &P[0], 1, 100); 1635 .loc 2 1904 20 discriminator 2 view .LVU562 1904:Src/main.c **** //HAL_SPI_Receive(&hspi4, &P[0], 1, 100); 1636 .loc 2 1904 25 is_stmt 0 discriminator 2 view .LVU563 1637 0190 0133 adds r3, r3, #1 1638 .LVL158: 1904:Src/main.c **** //HAL_SPI_Receive(&hspi4, &P[0], 1, 100); 1639 .loc 2 1904 25 discriminator 2 view .LVU564 1640 0192 FAE7 b .L90 1641 .L104: 1906:Src/main.c **** P = LL_SPI_ReceiveData16(SPI4); 1642 .loc 2 1906 3 is_stmt 1 view .LVU565 1643 0194 0122 movs r2, #1 1644 0196 4FF40061 mov r1, #2048 1645 019a 1E48 ldr r0, .L106 1646 019c FFF7FEFF bl HAL_GPIO_WritePin 1647 .LVL159: 1907:Src/main.c **** } 1648 .loc 2 1907 3 view .LVU566 1649 .LBB347: 1650 .LBI347: ARM GAS /tmp/ccdsDELB.s page 137 1344:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 1651 .loc 4 1344 26 view .LVU567 1652 .LBB348: 1346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1653 .loc 4 1346 3 view .LVU568 1346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1654 .loc 4 1346 21 is_stmt 0 view .LVU569 1655 01a0 1E4B ldr r3, .L106+8 1656 01a2 DD68 ldr r5, [r3, #12] 1346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1657 .loc 4 1346 10 view .LVU570 1658 01a4 ADB2 uxth r5, r5 1659 .LVL160: 1346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1660 .loc 4 1346 10 view .LVU571 1661 .LBE348: 1662 .LBE347: 1663 01a6 5AE7 b .L75 1664 .LVL161: 1665 .L103: 1911:Src/main.c **** HAL_GPIO_WritePin(ADC_ThrLD2_CS_GPIO_Port, ADC_ThrLD2_CS_Pin, GPIO_PIN_RESET); 1666 .loc 2 1911 3 is_stmt 1 view .LVU572 1667 01a8 1B4C ldr r4, .L106+4 1668 01aa 0122 movs r2, #1 1669 01ac 4021 movs r1, #64 1670 01ae 2046 mov r0, r4 1671 01b0 FFF7FEFF bl HAL_GPIO_WritePin 1672 .LVL162: 1912:Src/main.c **** tmp32=0; 1673 .loc 2 1912 3 view .LVU573 1674 01b4 0022 movs r2, #0 1675 01b6 4FF48061 mov r1, #1024 1676 01ba 2046 mov r0, r4 1677 01bc FFF7FEFF bl HAL_GPIO_WritePin 1678 .LVL163: 1913:Src/main.c **** while(tmp32<500){tmp32++;} 1679 .loc 2 1913 3 view .LVU574 1914:Src/main.c **** //LL_SPI_TransmitData16(SPI5, 0xFFFF);//We must to clock the CLK output for collect RX data. We c 1680 .loc 2 1914 3 view .LVU575 1913:Src/main.c **** while(tmp32<500){tmp32++;} 1681 .loc 2 1913 8 is_stmt 0 view .LVU576 1682 01c0 0023 movs r3, #0 1683 .LVL164: 1684 .L92: 1914:Src/main.c **** //LL_SPI_TransmitData16(SPI5, 0xFFFF);//We must to clock the CLK output for collect RX data. We c 1685 .loc 2 1914 8 is_stmt 1 discriminator 1 view .LVU577 1686 01c2 B3F5FA7F cmp r3, #500 1687 01c6 01D2 bcs .L105 1914:Src/main.c **** //LL_SPI_TransmitData16(SPI5, 0xFFFF);//We must to clock the CLK output for collect RX data. We c 1688 .loc 2 1914 20 discriminator 2 view .LVU578 1914:Src/main.c **** //LL_SPI_TransmitData16(SPI5, 0xFFFF);//We must to clock the CLK output for collect RX data. We c 1689 .loc 2 1914 25 is_stmt 0 discriminator 2 view .LVU579 1690 01c8 0133 adds r3, r3, #1 1691 .LVL165: 1914:Src/main.c **** //LL_SPI_TransmitData16(SPI5, 0xFFFF);//We must to clock the CLK output for collect RX data. We c 1692 .loc 2 1914 25 discriminator 2 view .LVU580 1693 01ca FAE7 b .L92 ARM GAS /tmp/ccdsDELB.s page 138 1694 .L105: 1916:Src/main.c **** tmp32 = 0; 1695 .loc 2 1916 3 is_stmt 1 view .LVU581 1696 .LVL166: 1697 .LBB349: 1698 .LBI349: 358:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 1699 .loc 4 358 22 view .LVU582 1700 .LBB350: 360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1701 .loc 4 360 3 view .LVU583 1702 01cc 144A ldr r2, .L106+12 1703 01ce 1368 ldr r3, [r2] 1704 .LVL167: 360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1705 .loc 4 360 3 is_stmt 0 view .LVU584 1706 01d0 43F04003 orr r3, r3, #64 1707 01d4 1360 str r3, [r2] 1708 .LVL168: 360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1709 .loc 4 360 3 view .LVU585 1710 .LBE350: 1711 .LBE349: 1917:Src/main.c **** while(((!LL_SPI_IsActiveFlag_RXNE(SPI5))&&(tmp32<=1000))) {tmp32++;}//When rec. last data cycle w 1712 .loc 2 1917 3 is_stmt 1 view .LVU586 1918:Src/main.c **** LL_SPI_Disable(SPI5);//Enable SPI for ThrLD2 ADC 1713 .loc 2 1918 3 view .LVU587 1917:Src/main.c **** while(((!LL_SPI_IsActiveFlag_RXNE(SPI5))&&(tmp32<=1000))) {tmp32++;}//When rec. last data cycle w 1714 .loc 2 1917 9 is_stmt 0 view .LVU588 1715 01d6 0023 movs r3, #0 1716 .LVL169: 1717 .L94: 1918:Src/main.c **** LL_SPI_Disable(SPI5);//Enable SPI for ThrLD2 ADC 1718 .loc 2 1918 8 is_stmt 1 discriminator 1 view .LVU589 1719 .LBB351: 1720 .LBI351: 905:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 1721 .loc 4 905 26 discriminator 1 view .LVU590 1722 .LBB352: 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1723 .loc 4 907 3 discriminator 1 view .LVU591 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1724 .loc 4 907 12 is_stmt 0 discriminator 1 view .LVU592 1725 01d8 114A ldr r2, .L106+12 1726 01da 9268 ldr r2, [r2, #8] 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1727 .loc 4 907 68 discriminator 1 view .LVU593 1728 01dc 12F0010F tst r2, #1 1729 01e0 04D1 bne .L95 1730 .LVL170: 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1731 .loc 4 907 68 discriminator 1 view .LVU594 1732 .LBE352: 1733 .LBE351: 1918:Src/main.c **** LL_SPI_Disable(SPI5);//Enable SPI for ThrLD2 ADC 1734 .loc 2 1918 43 view .LVU595 1735 01e2 B3F57A7F cmp r3, #1000 ARM GAS /tmp/ccdsDELB.s page 139 1736 01e6 01D8 bhi .L95 1918:Src/main.c **** LL_SPI_Disable(SPI5);//Enable SPI for ThrLD2 ADC 1737 .loc 2 1918 62 is_stmt 1 discriminator 3 view .LVU596 1918:Src/main.c **** LL_SPI_Disable(SPI5);//Enable SPI for ThrLD2 ADC 1738 .loc 2 1918 67 is_stmt 0 discriminator 3 view .LVU597 1739 01e8 0133 adds r3, r3, #1 1740 .LVL171: 1918:Src/main.c **** LL_SPI_Disable(SPI5);//Enable SPI for ThrLD2 ADC 1741 .loc 2 1918 67 discriminator 3 view .LVU598 1742 01ea F5E7 b .L94 1743 .L95: 1919:Src/main.c **** while(tmp32<500){tmp32++;} 1744 .loc 2 1919 3 is_stmt 1 view .LVU599 1745 .LVL172: 1746 .LBB353: 1747 .LBI353: 370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 1748 .loc 4 370 22 view .LVU600 1749 .LBB354: 372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1750 .loc 4 372 3 view .LVU601 1751 01ec 0C49 ldr r1, .L106+12 1752 01ee 0A68 ldr r2, [r1] 1753 01f0 22F04002 bic r2, r2, #64 1754 01f4 0A60 str r2, [r1] 373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 1755 .loc 4 373 1 is_stmt 0 view .LVU602 1756 01f6 00E0 b .L97 1757 .LVL173: 1758 .L98: 373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 1759 .loc 4 373 1 view .LVU603 1760 .LBE354: 1761 .LBE353: 1920:Src/main.c **** //HAL_SPI_Receive(&hspi4, &P[0], 1, 100); 1762 .loc 2 1920 20 is_stmt 1 discriminator 2 view .LVU604 1920:Src/main.c **** //HAL_SPI_Receive(&hspi4, &P[0], 1, 100); 1763 .loc 2 1920 25 is_stmt 0 discriminator 2 view .LVU605 1764 01f8 0133 adds r3, r3, #1 1765 .LVL174: 1766 .L97: 1920:Src/main.c **** //HAL_SPI_Receive(&hspi4, &P[0], 1, 100); 1767 .loc 2 1920 8 is_stmt 1 discriminator 1 view .LVU606 1768 01fa B3F5FA7F cmp r3, #500 1769 01fe FBD3 bcc .L98 1922:Src/main.c **** P = LL_SPI_ReceiveData16(SPI5); 1770 .loc 2 1922 3 view .LVU607 1771 0200 0122 movs r2, #1 1772 0202 4FF48061 mov r1, #1024 1773 0206 0448 ldr r0, .L106+4 1774 0208 FFF7FEFF bl HAL_GPIO_WritePin 1775 .LVL175: 1923:Src/main.c **** } 1776 .loc 2 1923 3 view .LVU608 1777 .LBB355: 1778 .LBI355: 1344:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { ARM GAS /tmp/ccdsDELB.s page 140 1779 .loc 4 1344 26 view .LVU609 1780 .LBB356: 1346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1781 .loc 4 1346 3 view .LVU610 1346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1782 .loc 4 1346 21 is_stmt 0 view .LVU611 1783 020c 044B ldr r3, .L106+12 1784 020e DD68 ldr r5, [r3, #12] 1346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1785 .loc 4 1346 10 view .LVU612 1786 0210 ADB2 uxth r5, r5 1787 .LVL176: 1346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1788 .loc 4 1346 10 view .LVU613 1789 0212 24E7 b .L75 1790 .L107: 1791 .align 2 1792 .L106: 1793 0214 00100240 .word 1073876992 1794 0218 00140240 .word 1073878016 1795 021c 00340140 .word 1073820672 1796 0220 00500140 .word 1073827840 1797 .LBE356: 1798 .LBE355: 1799 .cfi_endproc 1800 .LFE1207: 1802 .section .text.MX_GPIO_Init,"ax",%progbits 1803 .align 1 1804 .syntax unified 1805 .thumb 1806 .thumb_func 1807 .fpu fpv5-d16 1809 MX_GPIO_Init: 1810 .LFB1202: 1319:Src/main.c **** GPIO_InitTypeDef GPIO_InitStruct = {0}; 1811 .loc 2 1319 1 is_stmt 1 view -0 1812 .cfi_startproc 1813 @ args = 0, pretend = 0, frame = 48 1814 @ frame_needed = 0, uses_anonymous_args = 0 1815 0000 2DE9F04F push {r4, r5, r6, r7, r8, r9, r10, fp, lr} 1816 .LCFI10: 1817 .cfi_def_cfa_offset 36 1818 .cfi_offset 4, -36 1819 .cfi_offset 5, -32 1820 .cfi_offset 6, -28 1821 .cfi_offset 7, -24 1822 .cfi_offset 8, -20 1823 .cfi_offset 9, -16 1824 .cfi_offset 10, -12 1825 .cfi_offset 11, -8 1826 .cfi_offset 14, -4 1827 0004 8DB0 sub sp, sp, #52 1828 .LCFI11: 1829 .cfi_def_cfa_offset 88 1320:Src/main.c **** /* USER CODE BEGIN MX_GPIO_Init_1 */ 1830 .loc 2 1320 3 view .LVU615 1320:Src/main.c **** /* USER CODE BEGIN MX_GPIO_Init_1 */ ARM GAS /tmp/ccdsDELB.s page 141 1831 .loc 2 1320 20 is_stmt 0 view .LVU616 1832 0006 0024 movs r4, #0 1833 0008 0794 str r4, [sp, #28] 1834 000a 0894 str r4, [sp, #32] 1835 000c 0994 str r4, [sp, #36] 1836 000e 0A94 str r4, [sp, #40] 1837 0010 0B94 str r4, [sp, #44] 1325:Src/main.c **** __HAL_RCC_GPIOH_CLK_ENABLE(); 1838 .loc 2 1325 3 is_stmt 1 view .LVU617 1839 .LBB357: 1325:Src/main.c **** __HAL_RCC_GPIOH_CLK_ENABLE(); 1840 .loc 2 1325 3 view .LVU618 1325:Src/main.c **** __HAL_RCC_GPIOH_CLK_ENABLE(); 1841 .loc 2 1325 3 view .LVU619 1842 0012 784B ldr r3, .L110 1843 0014 1A6B ldr r2, [r3, #48] 1844 0016 42F02002 orr r2, r2, #32 1845 001a 1A63 str r2, [r3, #48] 1325:Src/main.c **** __HAL_RCC_GPIOH_CLK_ENABLE(); 1846 .loc 2 1325 3 view .LVU620 1847 001c 1A6B ldr r2, [r3, #48] 1848 001e 02F02002 and r2, r2, #32 1849 0022 0092 str r2, [sp] 1325:Src/main.c **** __HAL_RCC_GPIOH_CLK_ENABLE(); 1850 .loc 2 1325 3 view .LVU621 1851 0024 009A ldr r2, [sp] 1852 .LBE357: 1325:Src/main.c **** __HAL_RCC_GPIOH_CLK_ENABLE(); 1853 .loc 2 1325 3 view .LVU622 1326:Src/main.c **** __HAL_RCC_GPIOC_CLK_ENABLE(); 1854 .loc 2 1326 3 view .LVU623 1855 .LBB358: 1326:Src/main.c **** __HAL_RCC_GPIOC_CLK_ENABLE(); 1856 .loc 2 1326 3 view .LVU624 1326:Src/main.c **** __HAL_RCC_GPIOC_CLK_ENABLE(); 1857 .loc 2 1326 3 view .LVU625 1858 0026 1A6B ldr r2, [r3, #48] 1859 0028 42F08002 orr r2, r2, #128 1860 002c 1A63 str r2, [r3, #48] 1326:Src/main.c **** __HAL_RCC_GPIOC_CLK_ENABLE(); 1861 .loc 2 1326 3 view .LVU626 1862 002e 1A6B ldr r2, [r3, #48] 1863 0030 02F08002 and r2, r2, #128 1864 0034 0192 str r2, [sp, #4] 1326:Src/main.c **** __HAL_RCC_GPIOC_CLK_ENABLE(); 1865 .loc 2 1326 3 view .LVU627 1866 0036 019A ldr r2, [sp, #4] 1867 .LBE358: 1326:Src/main.c **** __HAL_RCC_GPIOC_CLK_ENABLE(); 1868 .loc 2 1326 3 view .LVU628 1327:Src/main.c **** __HAL_RCC_GPIOA_CLK_ENABLE(); 1869 .loc 2 1327 3 view .LVU629 1870 .LBB359: 1327:Src/main.c **** __HAL_RCC_GPIOA_CLK_ENABLE(); 1871 .loc 2 1327 3 view .LVU630 1327:Src/main.c **** __HAL_RCC_GPIOA_CLK_ENABLE(); 1872 .loc 2 1327 3 view .LVU631 ARM GAS /tmp/ccdsDELB.s page 142 1873 0038 1A6B ldr r2, [r3, #48] 1874 003a 42F00402 orr r2, r2, #4 1875 003e 1A63 str r2, [r3, #48] 1327:Src/main.c **** __HAL_RCC_GPIOA_CLK_ENABLE(); 1876 .loc 2 1327 3 view .LVU632 1877 0040 1A6B ldr r2, [r3, #48] 1878 0042 02F00402 and r2, r2, #4 1879 0046 0292 str r2, [sp, #8] 1327:Src/main.c **** __HAL_RCC_GPIOA_CLK_ENABLE(); 1880 .loc 2 1327 3 view .LVU633 1881 0048 029A ldr r2, [sp, #8] 1882 .LBE359: 1327:Src/main.c **** __HAL_RCC_GPIOA_CLK_ENABLE(); 1883 .loc 2 1327 3 view .LVU634 1328:Src/main.c **** __HAL_RCC_GPIOB_CLK_ENABLE(); 1884 .loc 2 1328 3 view .LVU635 1885 .LBB360: 1328:Src/main.c **** __HAL_RCC_GPIOB_CLK_ENABLE(); 1886 .loc 2 1328 3 view .LVU636 1328:Src/main.c **** __HAL_RCC_GPIOB_CLK_ENABLE(); 1887 .loc 2 1328 3 view .LVU637 1888 004a 1A6B ldr r2, [r3, #48] 1889 004c 42F00102 orr r2, r2, #1 1890 0050 1A63 str r2, [r3, #48] 1328:Src/main.c **** __HAL_RCC_GPIOB_CLK_ENABLE(); 1891 .loc 2 1328 3 view .LVU638 1892 0052 1A6B ldr r2, [r3, #48] 1893 0054 02F00102 and r2, r2, #1 1894 0058 0392 str r2, [sp, #12] 1328:Src/main.c **** __HAL_RCC_GPIOB_CLK_ENABLE(); 1895 .loc 2 1328 3 view .LVU639 1896 005a 039A ldr r2, [sp, #12] 1897 .LBE360: 1328:Src/main.c **** __HAL_RCC_GPIOB_CLK_ENABLE(); 1898 .loc 2 1328 3 view .LVU640 1329:Src/main.c **** __HAL_RCC_GPIOE_CLK_ENABLE(); 1899 .loc 2 1329 3 view .LVU641 1900 .LBB361: 1329:Src/main.c **** __HAL_RCC_GPIOE_CLK_ENABLE(); 1901 .loc 2 1329 3 view .LVU642 1329:Src/main.c **** __HAL_RCC_GPIOE_CLK_ENABLE(); 1902 .loc 2 1329 3 view .LVU643 1903 005c 1A6B ldr r2, [r3, #48] 1904 005e 42F00202 orr r2, r2, #2 1905 0062 1A63 str r2, [r3, #48] 1329:Src/main.c **** __HAL_RCC_GPIOE_CLK_ENABLE(); 1906 .loc 2 1329 3 view .LVU644 1907 0064 1A6B ldr r2, [r3, #48] 1908 0066 02F00202 and r2, r2, #2 1909 006a 0492 str r2, [sp, #16] 1329:Src/main.c **** __HAL_RCC_GPIOE_CLK_ENABLE(); 1910 .loc 2 1329 3 view .LVU645 1911 006c 049A ldr r2, [sp, #16] 1912 .LBE361: 1329:Src/main.c **** __HAL_RCC_GPIOE_CLK_ENABLE(); 1913 .loc 2 1329 3 view .LVU646 1330:Src/main.c **** __HAL_RCC_GPIOD_CLK_ENABLE(); ARM GAS /tmp/ccdsDELB.s page 143 1914 .loc 2 1330 3 view .LVU647 1915 .LBB362: 1330:Src/main.c **** __HAL_RCC_GPIOD_CLK_ENABLE(); 1916 .loc 2 1330 3 view .LVU648 1330:Src/main.c **** __HAL_RCC_GPIOD_CLK_ENABLE(); 1917 .loc 2 1330 3 view .LVU649 1918 006e 1A6B ldr r2, [r3, #48] 1919 0070 42F01002 orr r2, r2, #16 1920 0074 1A63 str r2, [r3, #48] 1330:Src/main.c **** __HAL_RCC_GPIOD_CLK_ENABLE(); 1921 .loc 2 1330 3 view .LVU650 1922 0076 1A6B ldr r2, [r3, #48] 1923 0078 02F01002 and r2, r2, #16 1924 007c 0592 str r2, [sp, #20] 1330:Src/main.c **** __HAL_RCC_GPIOD_CLK_ENABLE(); 1925 .loc 2 1330 3 view .LVU651 1926 007e 059A ldr r2, [sp, #20] 1927 .LBE362: 1330:Src/main.c **** __HAL_RCC_GPIOD_CLK_ENABLE(); 1928 .loc 2 1330 3 view .LVU652 1331:Src/main.c **** 1929 .loc 2 1331 3 view .LVU653 1930 .LBB363: 1331:Src/main.c **** 1931 .loc 2 1331 3 view .LVU654 1331:Src/main.c **** 1932 .loc 2 1331 3 view .LVU655 1933 0080 1A6B ldr r2, [r3, #48] 1934 0082 42F00802 orr r2, r2, #8 1935 0086 1A63 str r2, [r3, #48] 1331:Src/main.c **** 1936 .loc 2 1331 3 view .LVU656 1937 0088 1B6B ldr r3, [r3, #48] 1938 008a 03F00803 and r3, r3, #8 1939 008e 0693 str r3, [sp, #24] 1331:Src/main.c **** 1940 .loc 2 1331 3 view .LVU657 1941 0090 069B ldr r3, [sp, #24] 1942 .LBE363: 1331:Src/main.c **** 1943 .loc 2 1331 3 view .LVU658 1334:Src/main.c **** 1944 .loc 2 1334 3 view .LVU659 1945 0092 DFF86CA1 ldr r10, .L110+12 1946 0096 2246 mov r2, r4 1947 0098 4FF4C861 mov r1, #1600 1948 009c 5046 mov r0, r10 1949 009e FFF7FEFF bl HAL_GPIO_WritePin 1950 .LVL177: 1337:Src/main.c **** 1951 .loc 2 1337 3 view .LVU660 1952 00a2 DFF860B1 ldr fp, .L110+16 1953 00a6 2246 mov r2, r4 1954 00a8 3C21 movs r1, #60 1955 00aa 5846 mov r0, fp 1956 00ac FFF7FEFF bl HAL_GPIO_WritePin 1957 .LVL178: ARM GAS /tmp/ccdsDELB.s page 144 1340:Src/main.c **** 1958 .loc 2 1340 3 view .LVU661 1959 00b0 514F ldr r7, .L110+4 1960 00b2 2246 mov r2, r4 1961 00b4 4B21 movs r1, #75 1962 00b6 3846 mov r0, r7 1963 00b8 FFF7FEFF bl HAL_GPIO_WritePin 1964 .LVL179: 1343:Src/main.c **** 1965 .loc 2 1343 3 view .LVU662 1966 00bc 0122 movs r2, #1 1967 00be 1021 movs r1, #16 1968 00c0 3846 mov r0, r7 1969 00c2 FFF7FEFF bl HAL_GPIO_WritePin 1970 .LVL180: 1346:Src/main.c **** 1971 .loc 2 1346 3 view .LVU663 1972 00c6 4D4E ldr r6, .L110+8 1973 00c8 2246 mov r2, r4 1974 00ca 4FF44061 mov r1, #3072 1975 00ce 3046 mov r0, r6 1976 00d0 FFF7FEFF bl HAL_GPIO_WritePin 1977 .LVL181: 1349:Src/main.c **** 1978 .loc 2 1349 3 view .LVU664 1979 00d4 0122 movs r2, #1 1980 00d6 4FF48041 mov r1, #16384 1981 00da 3046 mov r0, r6 1982 00dc FFF7FEFF bl HAL_GPIO_WritePin 1983 .LVL182: 1352:Src/main.c **** 1984 .loc 2 1352 3 view .LVU665 1985 00e0 DFF82491 ldr r9, .L110+20 1986 00e4 2246 mov r2, r4 1987 00e6 4FF49841 mov r1, #19456 1988 00ea 4846 mov r0, r9 1989 00ec FFF7FEFF bl HAL_GPIO_WritePin 1990 .LVL183: 1355:Src/main.c **** 1991 .loc 2 1355 3 view .LVU666 1992 00f0 0122 movs r2, #1 1993 00f2 4FF48051 mov r1, #4096 1994 00f6 4846 mov r0, r9 1995 00f8 FFF7FEFF bl HAL_GPIO_WritePin 1996 .LVL184: 1358:Src/main.c **** 1997 .loc 2 1358 3 view .LVU667 1998 00fc DFF80C81 ldr r8, .L110+24 1999 0100 2246 mov r2, r4 2000 0102 4FF4C171 mov r1, #386 2001 0106 4046 mov r0, r8 2002 0108 FFF7FEFF bl HAL_GPIO_WritePin 2003 .LVL185: 1361:Src/main.c **** GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 2004 .loc 2 1361 3 view .LVU668 1361:Src/main.c **** GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 2005 .loc 2 1361 23 is_stmt 0 view .LVU669 ARM GAS /tmp/ccdsDELB.s page 145 2006 010c 4FF4C863 mov r3, #1600 2007 0110 0793 str r3, [sp, #28] 1362:Src/main.c **** GPIO_InitStruct.Pull = GPIO_NOPULL; 2008 .loc 2 1362 3 is_stmt 1 view .LVU670 1362:Src/main.c **** GPIO_InitStruct.Pull = GPIO_NOPULL; 2009 .loc 2 1362 24 is_stmt 0 view .LVU671 2010 0112 0125 movs r5, #1 2011 0114 0895 str r5, [sp, #32] 1363:Src/main.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 2012 .loc 2 1363 3 is_stmt 1 view .LVU672 1363:Src/main.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 2013 .loc 2 1363 24 is_stmt 0 view .LVU673 2014 0116 0994 str r4, [sp, #36] 1364:Src/main.c **** HAL_GPIO_Init(GPIOF, &GPIO_InitStruct); 2015 .loc 2 1364 3 is_stmt 1 view .LVU674 1364:Src/main.c **** HAL_GPIO_Init(GPIOF, &GPIO_InitStruct); 2016 .loc 2 1364 25 is_stmt 0 view .LVU675 2017 0118 0A94 str r4, [sp, #40] 1365:Src/main.c **** 2018 .loc 2 1365 3 is_stmt 1 view .LVU676 2019 011a 07A9 add r1, sp, #28 2020 011c 5046 mov r0, r10 2021 011e FFF7FEFF bl HAL_GPIO_Init 2022 .LVL186: 1368:Src/main.c **** GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 2023 .loc 2 1368 3 view .LVU677 1368:Src/main.c **** GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 2024 .loc 2 1368 23 is_stmt 0 view .LVU678 2025 0122 3423 movs r3, #52 2026 0124 0793 str r3, [sp, #28] 1369:Src/main.c **** GPIO_InitStruct.Pull = GPIO_NOPULL; 2027 .loc 2 1369 3 is_stmt 1 view .LVU679 1369:Src/main.c **** GPIO_InitStruct.Pull = GPIO_NOPULL; 2028 .loc 2 1369 24 is_stmt 0 view .LVU680 2029 0126 0895 str r5, [sp, #32] 1370:Src/main.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 2030 .loc 2 1370 3 is_stmt 1 view .LVU681 1370:Src/main.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 2031 .loc 2 1370 24 is_stmt 0 view .LVU682 2032 0128 0994 str r4, [sp, #36] 1371:Src/main.c **** HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); 2033 .loc 2 1371 3 is_stmt 1 view .LVU683 1371:Src/main.c **** HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); 2034 .loc 2 1371 25 is_stmt 0 view .LVU684 2035 012a 0A94 str r4, [sp, #40] 1372:Src/main.c **** 2036 .loc 2 1372 3 is_stmt 1 view .LVU685 2037 012c 07A9 add r1, sp, #28 2038 012e 5846 mov r0, fp 2039 0130 FFF7FEFF bl HAL_GPIO_Init 2040 .LVL187: 1375:Src/main.c **** GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 2041 .loc 2 1375 3 view .LVU686 1375:Src/main.c **** GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 2042 .loc 2 1375 23 is_stmt 0 view .LVU687 2043 0134 0823 movs r3, #8 2044 0136 0793 str r3, [sp, #28] ARM GAS /tmp/ccdsDELB.s page 146 1376:Src/main.c **** GPIO_InitStruct.Pull = GPIO_NOPULL; 2045 .loc 2 1376 3 is_stmt 1 view .LVU688 1376:Src/main.c **** GPIO_InitStruct.Pull = GPIO_NOPULL; 2046 .loc 2 1376 24 is_stmt 0 view .LVU689 2047 0138 0895 str r5, [sp, #32] 1377:Src/main.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; 2048 .loc 2 1377 3 is_stmt 1 view .LVU690 1377:Src/main.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; 2049 .loc 2 1377 24 is_stmt 0 view .LVU691 2050 013a 0994 str r4, [sp, #36] 1378:Src/main.c **** HAL_GPIO_Init(EN_5V1_GPIO_Port, &GPIO_InitStruct); 2051 .loc 2 1378 3 is_stmt 1 view .LVU692 1378:Src/main.c **** HAL_GPIO_Init(EN_5V1_GPIO_Port, &GPIO_InitStruct); 2052 .loc 2 1378 25 is_stmt 0 view .LVU693 2053 013c 0323 movs r3, #3 2054 013e 0A93 str r3, [sp, #40] 1379:Src/main.c **** 2055 .loc 2 1379 3 is_stmt 1 view .LVU694 2056 0140 07A9 add r1, sp, #28 2057 0142 5846 mov r0, fp 2058 0144 FFF7FEFF bl HAL_GPIO_Init 2059 .LVL188: 1383:Src/main.c **** |DAC_LD2_CS_Pin; 2060 .loc 2 1383 3 view .LVU695 1383:Src/main.c **** |DAC_LD2_CS_Pin; 2061 .loc 2 1383 23 is_stmt 0 view .LVU696 2062 0148 5B23 movs r3, #91 2063 014a 0793 str r3, [sp, #28] 1385:Src/main.c **** GPIO_InitStruct.Pull = GPIO_NOPULL; 2064 .loc 2 1385 3 is_stmt 1 view .LVU697 1385:Src/main.c **** GPIO_InitStruct.Pull = GPIO_NOPULL; 2065 .loc 2 1385 24 is_stmt 0 view .LVU698 2066 014c 0895 str r5, [sp, #32] 1386:Src/main.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 2067 .loc 2 1386 3 is_stmt 1 view .LVU699 1386:Src/main.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 2068 .loc 2 1386 24 is_stmt 0 view .LVU700 2069 014e 0994 str r4, [sp, #36] 1387:Src/main.c **** HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 2070 .loc 2 1387 3 is_stmt 1 view .LVU701 1387:Src/main.c **** HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 2071 .loc 2 1387 25 is_stmt 0 view .LVU702 2072 0150 0A94 str r4, [sp, #40] 1388:Src/main.c **** 2073 .loc 2 1388 3 is_stmt 1 view .LVU703 2074 0152 07A9 add r1, sp, #28 2075 0154 3846 mov r0, r7 2076 0156 FFF7FEFF bl HAL_GPIO_Init 2077 .LVL189: 1391:Src/main.c **** GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 2078 .loc 2 1391 3 view .LVU704 1391:Src/main.c **** GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 2079 .loc 2 1391 23 is_stmt 0 view .LVU705 2080 015a 4FF4F043 mov r3, #30720 2081 015e 0793 str r3, [sp, #28] 1392:Src/main.c **** GPIO_InitStruct.Pull = GPIO_NOPULL; 2082 .loc 2 1392 3 is_stmt 1 view .LVU706 ARM GAS /tmp/ccdsDELB.s page 147 1392:Src/main.c **** GPIO_InitStruct.Pull = GPIO_NOPULL; 2083 .loc 2 1392 24 is_stmt 0 view .LVU707 2084 0160 0894 str r4, [sp, #32] 1393:Src/main.c **** HAL_GPIO_Init(GPIOF, &GPIO_InitStruct); 2085 .loc 2 1393 3 is_stmt 1 view .LVU708 1393:Src/main.c **** HAL_GPIO_Init(GPIOF, &GPIO_InitStruct); 2086 .loc 2 1393 24 is_stmt 0 view .LVU709 2087 0162 0994 str r4, [sp, #36] 1394:Src/main.c **** 2088 .loc 2 1394 3 is_stmt 1 view .LVU710 2089 0164 07A9 add r1, sp, #28 2090 0166 5046 mov r0, r10 2091 0168 FFF7FEFF bl HAL_GPIO_Init 2092 .LVL190: 1397:Src/main.c **** GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 2093 .loc 2 1397 3 view .LVU711 1397:Src/main.c **** GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 2094 .loc 2 1397 23 is_stmt 0 view .LVU712 2095 016c 4FF44063 mov r3, #3072 2096 0170 0793 str r3, [sp, #28] 1398:Src/main.c **** GPIO_InitStruct.Pull = GPIO_NOPULL; 2097 .loc 2 1398 3 is_stmt 1 view .LVU713 1398:Src/main.c **** GPIO_InitStruct.Pull = GPIO_NOPULL; 2098 .loc 2 1398 24 is_stmt 0 view .LVU714 2099 0172 0895 str r5, [sp, #32] 1399:Src/main.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 2100 .loc 2 1399 3 is_stmt 1 view .LVU715 1399:Src/main.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 2101 .loc 2 1399 24 is_stmt 0 view .LVU716 2102 0174 0994 str r4, [sp, #36] 1400:Src/main.c **** HAL_GPIO_Init(GPIOE, &GPIO_InitStruct); 2103 .loc 2 1400 3 is_stmt 1 view .LVU717 1400:Src/main.c **** HAL_GPIO_Init(GPIOE, &GPIO_InitStruct); 2104 .loc 2 1400 25 is_stmt 0 view .LVU718 2105 0176 0A94 str r4, [sp, #40] 1401:Src/main.c **** 2106 .loc 2 1401 3 is_stmt 1 view .LVU719 2107 0178 07A9 add r1, sp, #28 2108 017a 3046 mov r0, r6 2109 017c FFF7FEFF bl HAL_GPIO_Init 2110 .LVL191: 1404:Src/main.c **** GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 2111 .loc 2 1404 3 view .LVU720 1404:Src/main.c **** GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 2112 .loc 2 1404 23 is_stmt 0 view .LVU721 2113 0180 4FF48043 mov r3, #16384 2114 0184 0793 str r3, [sp, #28] 1405:Src/main.c **** GPIO_InitStruct.Pull = GPIO_NOPULL; 2115 .loc 2 1405 3 is_stmt 1 view .LVU722 1405:Src/main.c **** GPIO_InitStruct.Pull = GPIO_NOPULL; 2116 .loc 2 1405 24 is_stmt 0 view .LVU723 2117 0186 0895 str r5, [sp, #32] 1406:Src/main.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; 2118 .loc 2 1406 3 is_stmt 1 view .LVU724 1406:Src/main.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; 2119 .loc 2 1406 24 is_stmt 0 view .LVU725 2120 0188 0994 str r4, [sp, #36] ARM GAS /tmp/ccdsDELB.s page 148 1407:Src/main.c **** HAL_GPIO_Init(SPI4_CNV_GPIO_Port, &GPIO_InitStruct); 2121 .loc 2 1407 3 is_stmt 1 view .LVU726 1407:Src/main.c **** HAL_GPIO_Init(SPI4_CNV_GPIO_Port, &GPIO_InitStruct); 2122 .loc 2 1407 25 is_stmt 0 view .LVU727 2123 018a 0323 movs r3, #3 2124 018c 0A93 str r3, [sp, #40] 1408:Src/main.c **** 2125 .loc 2 1408 3 is_stmt 1 view .LVU728 2126 018e 07A9 add r1, sp, #28 2127 0190 3046 mov r0, r6 2128 0192 FFF7FEFF bl HAL_GPIO_Init 2129 .LVL192: 1411:Src/main.c **** GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 2130 .loc 2 1411 3 view .LVU729 1411:Src/main.c **** GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 2131 .loc 2 1411 23 is_stmt 0 view .LVU730 2132 0196 4FF4B843 mov r3, #23552 2133 019a 0793 str r3, [sp, #28] 1412:Src/main.c **** GPIO_InitStruct.Pull = GPIO_NOPULL; 2134 .loc 2 1412 3 is_stmt 1 view .LVU731 1412:Src/main.c **** GPIO_InitStruct.Pull = GPIO_NOPULL; 2135 .loc 2 1412 24 is_stmt 0 view .LVU732 2136 019c 0895 str r5, [sp, #32] 1413:Src/main.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 2137 .loc 2 1413 3 is_stmt 1 view .LVU733 1413:Src/main.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 2138 .loc 2 1413 24 is_stmt 0 view .LVU734 2139 019e 0994 str r4, [sp, #36] 1414:Src/main.c **** HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 2140 .loc 2 1414 3 is_stmt 1 view .LVU735 1414:Src/main.c **** HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 2141 .loc 2 1414 25 is_stmt 0 view .LVU736 2142 01a0 0A94 str r4, [sp, #40] 1415:Src/main.c **** 2143 .loc 2 1415 3 is_stmt 1 view .LVU737 2144 01a2 07A9 add r1, sp, #28 2145 01a4 4846 mov r0, r9 2146 01a6 FFF7FEFF bl HAL_GPIO_Init 2147 .LVL193: 1418:Src/main.c **** GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 2148 .loc 2 1418 3 view .LVU738 1418:Src/main.c **** GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 2149 .loc 2 1418 23 is_stmt 0 view .LVU739 2150 01aa 4FF4C173 mov r3, #386 2151 01ae 0793 str r3, [sp, #28] 1419:Src/main.c **** GPIO_InitStruct.Pull = GPIO_NOPULL; 2152 .loc 2 1419 3 is_stmt 1 view .LVU740 1419:Src/main.c **** GPIO_InitStruct.Pull = GPIO_NOPULL; 2153 .loc 2 1419 24 is_stmt 0 view .LVU741 2154 01b0 0895 str r5, [sp, #32] 1420:Src/main.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 2155 .loc 2 1420 3 is_stmt 1 view .LVU742 1420:Src/main.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 2156 .loc 2 1420 24 is_stmt 0 view .LVU743 2157 01b2 0994 str r4, [sp, #36] 1421:Src/main.c **** HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); 2158 .loc 2 1421 3 is_stmt 1 view .LVU744 ARM GAS /tmp/ccdsDELB.s page 149 1421:Src/main.c **** HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); 2159 .loc 2 1421 25 is_stmt 0 view .LVU745 2160 01b4 0A94 str r4, [sp, #40] 1422:Src/main.c **** 2161 .loc 2 1422 3 is_stmt 1 view .LVU746 2162 01b6 07A9 add r1, sp, #28 2163 01b8 4046 mov r0, r8 2164 01ba FFF7FEFF bl HAL_GPIO_Init 2165 .LVL194: 1425:Src/main.c **** GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 2166 .loc 2 1425 3 view .LVU747 1425:Src/main.c **** GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 2167 .loc 2 1425 23 is_stmt 0 view .LVU748 2168 01be 4FF48073 mov r3, #256 2169 01c2 0793 str r3, [sp, #28] 1426:Src/main.c **** GPIO_InitStruct.Pull = GPIO_NOPULL; 2170 .loc 2 1426 3 is_stmt 1 view .LVU749 1426:Src/main.c **** GPIO_InitStruct.Pull = GPIO_NOPULL; 2171 .loc 2 1426 24 is_stmt 0 view .LVU750 2172 01c4 0894 str r4, [sp, #32] 1427:Src/main.c **** HAL_GPIO_Init(USB_FLAG_GPIO_Port, &GPIO_InitStruct); 2173 .loc 2 1427 3 is_stmt 1 view .LVU751 1427:Src/main.c **** HAL_GPIO_Init(USB_FLAG_GPIO_Port, &GPIO_InitStruct); 2174 .loc 2 1427 24 is_stmt 0 view .LVU752 2175 01c6 0994 str r4, [sp, #36] 1428:Src/main.c **** 2176 .loc 2 1428 3 is_stmt 1 view .LVU753 2177 01c8 07A9 add r1, sp, #28 2178 01ca 3846 mov r0, r7 2179 01cc FFF7FEFF bl HAL_GPIO_Init 2180 .LVL195: 1431:Src/main.c **** GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 2181 .loc 2 1431 3 view .LVU754 1431:Src/main.c **** GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 2182 .loc 2 1431 23 is_stmt 0 view .LVU755 2183 01d0 0795 str r5, [sp, #28] 1432:Src/main.c **** GPIO_InitStruct.Pull = GPIO_NOPULL; 2184 .loc 2 1432 3 is_stmt 1 view .LVU756 1432:Src/main.c **** GPIO_InitStruct.Pull = GPIO_NOPULL; 2185 .loc 2 1432 24 is_stmt 0 view .LVU757 2186 01d2 0894 str r4, [sp, #32] 1433:Src/main.c **** HAL_GPIO_Init(SDMMC1_EN_GPIO_Port, &GPIO_InitStruct); 2187 .loc 2 1433 3 is_stmt 1 view .LVU758 1433:Src/main.c **** HAL_GPIO_Init(SDMMC1_EN_GPIO_Port, &GPIO_InitStruct); 2188 .loc 2 1433 24 is_stmt 0 view .LVU759 2189 01d4 0994 str r4, [sp, #36] 1434:Src/main.c **** 2190 .loc 2 1434 3 is_stmt 1 view .LVU760 2191 01d6 07A9 add r1, sp, #28 2192 01d8 4046 mov r0, r8 2193 01da FFF7FEFF bl HAL_GPIO_Init 2194 .LVL196: 1437:Src/main.c **** GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 2195 .loc 2 1437 3 view .LVU761 1437:Src/main.c **** GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 2196 .loc 2 1437 23 is_stmt 0 view .LVU762 2197 01de 0223 movs r3, #2 ARM GAS /tmp/ccdsDELB.s page 150 2198 01e0 0793 str r3, [sp, #28] 1438:Src/main.c **** GPIO_InitStruct.Pull = GPIO_NOPULL; 2199 .loc 2 1438 3 is_stmt 1 view .LVU763 1438:Src/main.c **** GPIO_InitStruct.Pull = GPIO_NOPULL; 2200 .loc 2 1438 24 is_stmt 0 view .LVU764 2201 01e2 0894 str r4, [sp, #32] 1439:Src/main.c **** HAL_GPIO_Init(FPGA_CONF_DONE_GPIO_Port, &GPIO_InitStruct); 2202 .loc 2 1439 3 is_stmt 1 view .LVU765 1439:Src/main.c **** HAL_GPIO_Init(FPGA_CONF_DONE_GPIO_Port, &GPIO_InitStruct); 2203 .loc 2 1439 24 is_stmt 0 view .LVU766 2204 01e4 0994 str r4, [sp, #36] 1440:Src/main.c **** 2205 .loc 2 1440 3 is_stmt 1 view .LVU767 2206 01e6 07A9 add r1, sp, #28 2207 01e8 3046 mov r0, r6 2208 01ea FFF7FEFF bl HAL_GPIO_Init 2209 .LVL197: 1444:Src/main.c **** 2210 .loc 2 1444 1 is_stmt 0 view .LVU768 2211 01ee 0DB0 add sp, sp, #52 2212 .LCFI12: 2213 .cfi_def_cfa_offset 36 2214 @ sp needed 2215 01f0 BDE8F08F pop {r4, r5, r6, r7, r8, r9, r10, fp, pc} 2216 .L111: 2217 .align 2 2218 .L110: 2219 01f4 00380240 .word 1073887232 2220 01f8 00000240 .word 1073872896 2221 01fc 00100240 .word 1073876992 2222 0200 00140240 .word 1073878016 2223 0204 00080240 .word 1073874944 2224 0208 00040240 .word 1073873920 2225 020c 000C0240 .word 1073875968 2226 .cfi_endproc 2227 .LFE1202: 2229 .section .text.MX_SPI4_Init,"ax",%progbits 2230 .align 1 2231 .syntax unified 2232 .thumb 2233 .thumb_func 2234 .fpu fpv5-d16 2236 MX_SPI4_Init: 2237 .LFB1192: 836:Src/main.c **** 2238 .loc 2 836 1 is_stmt 1 view -0 2239 .cfi_startproc 2240 @ args = 0, pretend = 0, frame = 72 2241 @ frame_needed = 0, uses_anonymous_args = 0 2242 0000 2DE9F041 push {r4, r5, r6, r7, r8, lr} 2243 .LCFI13: 2244 .cfi_def_cfa_offset 24 2245 .cfi_offset 4, -24 2246 .cfi_offset 5, -20 2247 .cfi_offset 6, -16 2248 .cfi_offset 7, -12 2249 .cfi_offset 8, -8 ARM GAS /tmp/ccdsDELB.s page 151 2250 .cfi_offset 14, -4 2251 0004 92B0 sub sp, sp, #72 2252 .LCFI14: 2253 .cfi_def_cfa_offset 96 842:Src/main.c **** 2254 .loc 2 842 3 view .LVU770 842:Src/main.c **** 2255 .loc 2 842 22 is_stmt 0 view .LVU771 2256 0006 2822 movs r2, #40 2257 0008 0021 movs r1, #0 2258 000a 08A8 add r0, sp, #32 2259 000c FFF7FEFF bl memset 2260 .LVL198: 844:Src/main.c **** 2261 .loc 2 844 3 is_stmt 1 view .LVU772 844:Src/main.c **** 2262 .loc 2 844 23 is_stmt 0 view .LVU773 2263 0010 0024 movs r4, #0 2264 0012 0294 str r4, [sp, #8] 2265 0014 0394 str r4, [sp, #12] 2266 0016 0494 str r4, [sp, #16] 2267 0018 0594 str r4, [sp, #20] 2268 001a 0694 str r4, [sp, #24] 2269 001c 0794 str r4, [sp, #28] 847:Src/main.c **** 2270 .loc 2 847 3 is_stmt 1 view .LVU774 2271 .LVL199: 2272 .LBB364: 2273 .LBI364: 316:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } 317:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 318:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** 319:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Check if AHB1 peripheral clock is enabled or not 320:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll AHB1ENR GPIOAEN LL_AHB1_GRP1_IsEnabledClock\n 321:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOBEN LL_AHB1_GRP1_IsEnabledClock\n 322:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOCEN LL_AHB1_GRP1_IsEnabledClock\n 323:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIODEN LL_AHB1_GRP1_IsEnabledClock\n 324:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOEEN LL_AHB1_GRP1_IsEnabledClock\n 325:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOFEN LL_AHB1_GRP1_IsEnabledClock\n 326:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOGEN LL_AHB1_GRP1_IsEnabledClock\n 327:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOHEN LL_AHB1_GRP1_IsEnabledClock\n 328:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOIEN LL_AHB1_GRP1_IsEnabledClock\n 329:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOJEN LL_AHB1_GRP1_IsEnabledClock\n 330:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOKEN LL_AHB1_GRP1_IsEnabledClock\n 331:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR CRCEN LL_AHB1_GRP1_IsEnabledClock\n 332:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR BKPSRAMEN LL_AHB1_GRP1_IsEnabledClock\n 333:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR DTCMRAMEN LL_AHB1_GRP1_IsEnabledClock\n 334:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR DMA1EN LL_AHB1_GRP1_IsEnabledClock\n 335:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR DMA2EN LL_AHB1_GRP1_IsEnabledClock\n 336:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR DMA2DEN LL_AHB1_GRP1_IsEnabledClock\n 337:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR ETHMACEN LL_AHB1_GRP1_IsEnabledClock\n 338:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR ETHMACTXEN LL_AHB1_GRP1_IsEnabledClock\n 339:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR ETHMACRXEN LL_AHB1_GRP1_IsEnabledClock\n 340:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR ETHMACPTPEN LL_AHB1_GRP1_IsEnabledClock\n 341:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR OTGHSEN LL_AHB1_GRP1_IsEnabledClock\n 342:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR OTGHSULPIENDEN LL_AHB1_GRP1_IsEnabledClock 343:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: ARM GAS /tmp/ccdsDELB.s page 152 344:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA 345:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB 346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC 347:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD 348:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE 349:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF 350:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG 351:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH 352:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI 353:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*) 354:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*) 355:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRC 356:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM 357:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DTCMRAM 358:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 359:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*) 361:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*) 362:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*) 363:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*) 364:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACPTP (*) 365:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS 366:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHSULPI 367:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * 368:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. 369:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval State of Periphs (1 or 0). 370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ 371:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs) 372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { 373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** return (READ_BIT(RCC->AHB1ENR, Periphs) == Periphs); 374:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } 375:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 376:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** 377:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Disable AHB1 peripherals clock. 378:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll AHB1ENR GPIOAEN LL_AHB1_GRP1_DisableClock\n 379:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOBEN LL_AHB1_GRP1_DisableClock\n 380:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOCEN LL_AHB1_GRP1_DisableClock\n 381:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIODEN LL_AHB1_GRP1_DisableClock\n 382:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOEEN LL_AHB1_GRP1_DisableClock\n 383:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOFEN LL_AHB1_GRP1_DisableClock\n 384:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOGEN LL_AHB1_GRP1_DisableClock\n 385:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOHEN LL_AHB1_GRP1_DisableClock\n 386:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOIEN LL_AHB1_GRP1_DisableClock\n 387:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOJEN LL_AHB1_GRP1_DisableClock\n 388:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOKEN LL_AHB1_GRP1_DisableClock\n 389:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR CRCEN LL_AHB1_GRP1_DisableClock\n 390:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR BKPSRAMEN LL_AHB1_GRP1_DisableClock\n 391:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR DTCMRAMEN LL_AHB1_GRP1_DisableClock\n 392:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR DMA1EN LL_AHB1_GRP1_DisableClock\n 393:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR DMA2EN LL_AHB1_GRP1_DisableClock\n 394:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR DMA2DEN LL_AHB1_GRP1_DisableClock\n 395:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR ETHMACEN LL_AHB1_GRP1_DisableClock\n 396:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR ETHMACTXEN LL_AHB1_GRP1_DisableClock\n 397:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR ETHMACRXEN LL_AHB1_GRP1_DisableClock\n 398:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR ETHMACPTPEN LL_AHB1_GRP1_DisableClock\n 399:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR OTGHSEN LL_AHB1_GRP1_DisableClock\n 400:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR OTGHSULPIENDEN LL_AHB1_GRP1_DisableClock ARM GAS /tmp/ccdsDELB.s page 153 401:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: 402:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA 403:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB 404:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC 405:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD 406:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE 407:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF 408:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG 409:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH 410:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI 411:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*) 412:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*) 413:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRC 414:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM 415:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DTCMRAM 416:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 417:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 418:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*) 419:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*) 420:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*) 421:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*) 422:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACPTP (*) 423:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS 424:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHSULPI 425:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * 426:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. 427:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval None 428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ 429:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs) 430:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { 431:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** CLEAR_BIT(RCC->AHB1ENR, Periphs); 432:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } 433:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 434:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** 435:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Force AHB1 peripherals reset. 436:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll AHB1RSTR GPIOARST LL_AHB1_GRP1_ForceReset\n 437:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR GPIOBRST LL_AHB1_GRP1_ForceReset\n 438:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR GPIOCRST LL_AHB1_GRP1_ForceReset\n 439:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR GPIODRST LL_AHB1_GRP1_ForceReset\n 440:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR GPIOERST LL_AHB1_GRP1_ForceReset\n 441:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR GPIOFRST LL_AHB1_GRP1_ForceReset\n 442:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR GPIOGRST LL_AHB1_GRP1_ForceReset\n 443:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR GPIOHRST LL_AHB1_GRP1_ForceReset\n 444:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR GPIOIRST LL_AHB1_GRP1_ForceReset\n 445:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR GPIOJRST LL_AHB1_GRP1_ForceReset\n 446:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR GPIOKRST LL_AHB1_GRP1_ForceReset\n 447:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR CRCRST LL_AHB1_GRP1_ForceReset\n 448:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR DMA1RST LL_AHB1_GRP1_ForceReset\n 449:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR DMA2RST LL_AHB1_GRP1_ForceReset\n 450:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR DMA2DRST LL_AHB1_GRP1_ForceReset\n 451:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR ETHMACRST LL_AHB1_GRP1_ForceReset\n 452:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR OTGHSRST LL_AHB1_GRP1_ForceReset 453:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: 454:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ALL 455:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA 456:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB 457:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC ARM GAS /tmp/ccdsDELB.s page 154 458:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD 459:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE 460:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF 461:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG 462:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH 463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI 464:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*) 465:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*) 466:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRC 467:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 468:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 469:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*) 470:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*) 471:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS 472:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * 473:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. 474:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval None 475:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ 476:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs) 477:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { 478:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** SET_BIT(RCC->AHB1RSTR, Periphs); 479:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } 480:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 481:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** 482:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Release AHB1 peripherals reset. 483:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll AHB1RSTR GPIOARST LL_AHB1_GRP1_ReleaseReset\n 484:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR GPIOBRST LL_AHB1_GRP1_ReleaseReset\n 485:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR GPIOCRST LL_AHB1_GRP1_ReleaseReset\n 486:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR GPIODRST LL_AHB1_GRP1_ReleaseReset\n 487:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR GPIOERST LL_AHB1_GRP1_ReleaseReset\n 488:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR GPIOFRST LL_AHB1_GRP1_ReleaseReset\n 489:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR GPIOGRST LL_AHB1_GRP1_ReleaseReset\n 490:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR GPIOHRST LL_AHB1_GRP1_ReleaseReset\n 491:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR GPIOIRST LL_AHB1_GRP1_ReleaseReset\n 492:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR GPIOJRST LL_AHB1_GRP1_ReleaseReset\n 493:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR GPIOKRST LL_AHB1_GRP1_ReleaseReset\n 494:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR CRCRST LL_AHB1_GRP1_ReleaseReset\n 495:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR DMA1RST LL_AHB1_GRP1_ReleaseReset\n 496:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR DMA2RST LL_AHB1_GRP1_ReleaseReset\n 497:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR DMA2DRST LL_AHB1_GRP1_ReleaseReset\n 498:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR ETHMACRST LL_AHB1_GRP1_ReleaseReset\n 499:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR OTGHSRST LL_AHB1_GRP1_ReleaseReset 500:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: 501:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ALL 502:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA 503:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB 504:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC 505:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD 506:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE 507:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF 508:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG 509:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH 510:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI 511:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*) 512:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*) 513:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRC 514:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 ARM GAS /tmp/ccdsDELB.s page 155 515:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 516:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*) 517:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*) 518:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS 519:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * 520:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. 521:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval None 522:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ 523:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs) 524:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { 525:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** CLEAR_BIT(RCC->AHB1RSTR, Periphs); 526:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } 527:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 528:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** 529:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Enable AHB1 peripheral clocks in low-power mode 530:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll AHB1LPENR GPIOALPEN LL_AHB1_GRP1_EnableClockLowPower\n 531:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR GPIOBLPEN LL_AHB1_GRP1_EnableClockLowPower\n 532:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR GPIOCLPEN LL_AHB1_GRP1_EnableClockLowPower\n 533:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR GPIODLPEN LL_AHB1_GRP1_EnableClockLowPower\n 534:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR GPIOELPEN LL_AHB1_GRP1_EnableClockLowPower\n 535:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR GPIOFLPEN LL_AHB1_GRP1_EnableClockLowPower\n 536:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR GPIOGLPEN LL_AHB1_GRP1_EnableClockLowPower\n 537:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR GPIOHLPEN LL_AHB1_GRP1_EnableClockLowPower\n 538:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR GPIOILPEN LL_AHB1_GRP1_EnableClockLowPower\n 539:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR GPIOJLPEN LL_AHB1_GRP1_EnableClockLowPower\n 540:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR GPIOKLPEN LL_AHB1_GRP1_EnableClockLowPower\n 541:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR CRCLPEN LL_AHB1_GRP1_EnableClockLowPower\n 542:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR AXILPEN LL_AHB1_GRP1_EnableClockLowPower\n 543:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR FLITFLPEN LL_AHB1_GRP1_EnableClockLowPower\n 544:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR SRAM1LPEN LL_AHB1_GRP1_EnableClockLowPower\n 545:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR SRAM2LPEN LL_AHB1_GRP1_EnableClockLowPower\n 546:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR BKPSRAMLPEN LL_AHB1_GRP1_EnableClockLowPower\n 547:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR DTCMRAMLPEN LL_AHB1_GRP1_EnableClockLowPower\n 548:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR DMA1LPEN LL_AHB1_GRP1_EnableClockLowPower\n 549:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR DMA2LPEN LL_AHB1_GRP1_EnableClockLowPower\n 550:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR DMA2DLPEN LL_AHB1_GRP1_EnableClockLowPower\n 551:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR ETHMACLPEN LL_AHB1_GRP1_EnableClockLowPower\n 552:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR ETHMACTXLPEN LL_AHB1_GRP1_EnableClockLowPower\n 553:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR ETHMACRXLPEN LL_AHB1_GRP1_EnableClockLowPower\n 554:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR ETHMACPTPLPEN LL_AHB1_GRP1_EnableClockLowPower\n 555:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR OTGHSLPEN LL_AHB1_GRP1_EnableClockLowPower\n 556:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR OTGHSULPILPEN LL_AHB1_GRP1_EnableClockLowPower 557:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: 558:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA 559:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB 560:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC 561:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD 562:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE 563:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF 564:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG 565:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH 566:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI 567:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*) 568:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*) 569:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRC 570:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_AXI 571:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_FLITF ARM GAS /tmp/ccdsDELB.s page 156 572:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1 573:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM2 574:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM 575:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DTCMRAM 576:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 577:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 578:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*) 579:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*) 580:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*) 581:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*) 582:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACPTP (*) 583:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS 584:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHSULPI 585:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * 586:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. 587:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval None 588:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ 589:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB1_GRP1_EnableClockLowPower(uint32_t Periphs) 590:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { 591:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __IO uint32_t tmpreg; 592:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** SET_BIT(RCC->AHB1LPENR, Periphs); 593:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Delay after an RCC peripheral clock enabling */ 594:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** tmpreg = READ_BIT(RCC->AHB1LPENR, Periphs); 595:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; 596:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } 597:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 598:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** 599:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Disable AHB1 peripheral clocks in low-power mode 600:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll AHB1LPENR GPIOALPEN LL_AHB1_GRP1_DisableClockLowPower\n 601:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR GPIOBLPEN LL_AHB1_GRP1_DisableClockLowPower\n 602:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR GPIOCLPEN LL_AHB1_GRP1_DisableClockLowPower\n 603:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR GPIODLPEN LL_AHB1_GRP1_DisableClockLowPower\n 604:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR GPIOELPEN LL_AHB1_GRP1_DisableClockLowPower\n 605:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR GPIOFLPEN LL_AHB1_GRP1_DisableClockLowPower\n 606:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR GPIOGLPEN LL_AHB1_GRP1_DisableClockLowPower\n 607:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR GPIOHLPEN LL_AHB1_GRP1_DisableClockLowPower\n 608:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR GPIOILPEN LL_AHB1_GRP1_DisableClockLowPower\n 609:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR GPIOJLPEN LL_AHB1_GRP1_DisableClockLowPower\n 610:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR GPIOKLPEN LL_AHB1_GRP1_DisableClockLowPower\n 611:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR CRCLPEN LL_AHB1_GRP1_DisableClockLowPower\n 612:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR AXILPEN LL_AHB1_GRP1_DisableClockLowPower\n 613:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR FLITFLPEN LL_AHB1_GRP1_DisableClockLowPower\n 614:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR SRAM1LPEN LL_AHB1_GRP1_DisableClockLowPower\n 615:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR SRAM2LPEN LL_AHB1_GRP1_DisableClockLowPower\n 616:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR BKPSRAMLPEN LL_AHB1_GRP1_DisableClockLowPower\n 617:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR DTCMRAMLPEN LL_AHB1_GRP1_DisableClockLowPower\n 618:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR DMA1LPEN LL_AHB1_GRP1_DisableClockLowPower\n 619:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR DMA2LPEN LL_AHB1_GRP1_DisableClockLowPower\n 620:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR DMA2DLPEN LL_AHB1_GRP1_DisableClockLowPower\n 621:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR ETHMACLPEN LL_AHB1_GRP1_DisableClockLowPower\n 622:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR ETHMACTXLPEN LL_AHB1_GRP1_DisableClockLowPower\n 623:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR ETHMACRXLPEN LL_AHB1_GRP1_DisableClockLowPower\n 624:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR ETHMACPTPLPEN LL_AHB1_GRP1_DisableClockLowPower\n 625:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR OTGHSLPEN LL_AHB1_GRP1_DisableClockLowPower\n 626:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR OTGHSULPILPEN LL_AHB1_GRP1_DisableClockLowPower 627:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: 628:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA ARM GAS /tmp/ccdsDELB.s page 157 629:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB 630:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC 631:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD 632:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE 633:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF 634:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG 635:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH 636:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI 637:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*) 638:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*) 639:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRC 640:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_AXI 641:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_FLITF 642:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1 643:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM2 644:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM 645:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DTCMRAM 646:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 647:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 648:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*) 649:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*) 650:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*) 651:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*) 652:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACPTP (*) 653:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS 654:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHSULPI 655:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * 656:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. 657:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval None 658:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ 659:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB1_GRP1_DisableClockLowPower(uint32_t Periphs) 660:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { 661:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** CLEAR_BIT(RCC->AHB1LPENR, Periphs); 662:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } 663:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 664:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** 665:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @} 666:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ 667:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 668:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** @defgroup BUS_LL_EF_AHB2 AHB2 669:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @{ 670:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ 671:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 672:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** 673:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Enable AHB2 peripherals clock. 674:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll AHB2ENR DCMIEN LL_AHB2_GRP1_EnableClock\n 675:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2ENR JPEGEN LL_AHB2_GRP1_EnableClock\n 676:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2ENR CRYPEN LL_AHB2_GRP1_EnableClock\n 677:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2ENR AESEN LL_AHB2_GRP1_EnableClock\n 678:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2ENR HASHEN LL_AHB2_GRP1_EnableClock\n 679:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2ENR RNGEN LL_AHB2_GRP1_EnableClock\n 680:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2ENR OTGFSEN LL_AHB2_GRP1_EnableClock 681:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: 682:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*) 683:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_JPEG (*) 684:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) 685:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*) ARM GAS /tmp/ccdsDELB.s page 158 686:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) 687:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_RNG 688:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS 689:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * 690:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. 691:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval None 692:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ 693:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB2_GRP1_EnableClock(uint32_t Periphs) 694:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { 695:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __IO uint32_t tmpreg; 696:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** SET_BIT(RCC->AHB2ENR, Periphs); 697:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Delay after an RCC peripheral clock enabling */ 698:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** tmpreg = READ_BIT(RCC->AHB2ENR, Periphs); 699:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; 700:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } 701:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 702:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** 703:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Check if AHB2 peripheral clock is enabled or not 704:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll AHB2ENR DCMIEN LL_AHB2_GRP1_IsEnabledClock\n 705:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2ENR JPEGEN LL_AHB2_GRP1_IsEnabledClock\n 706:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2ENR CRYPEN LL_AHB2_GRP1_IsEnabledClock\n 707:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2ENR AESEN LL_AHB2_GRP1_IsEnabledClock\n 708:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2ENR HASHEN LL_AHB2_GRP1_IsEnabledClock\n 709:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2ENR RNGEN LL_AHB2_GRP1_IsEnabledClock\n 710:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2ENR OTGFSEN LL_AHB2_GRP1_IsEnabledClock 711:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: 712:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*) 713:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_JPEG (*) 714:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) 715:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*) 716:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) 717:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_RNG 718:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS 719:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * 720:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. 721:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval State of Periphs (1 or 0). 722:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ 723:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE uint32_t LL_AHB2_GRP1_IsEnabledClock(uint32_t Periphs) 724:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { 725:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** return (READ_BIT(RCC->AHB2ENR, Periphs) == Periphs); 726:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } 727:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 728:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** 729:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Disable AHB2 peripherals clock. 730:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll AHB2ENR DCMIEN LL_AHB2_GRP1_DisableClock\n 731:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2ENR JPEGEN LL_AHB2_GRP1_DisableClock\n 732:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2ENR CRYPEN LL_AHB2_GRP1_DisableClock\n 733:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2ENR AESEN LL_AHB2_GRP1_DisableClock\n 734:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2ENR HASHEN LL_AHB2_GRP1_DisableClock\n 735:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2ENR RNGEN LL_AHB2_GRP1_DisableClock\n 736:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2ENR OTGFSEN LL_AHB2_GRP1_DisableClock 737:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: 738:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*) 739:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_JPEG (*) 740:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) 741:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*) 742:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) ARM GAS /tmp/ccdsDELB.s page 159 743:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_RNG 744:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS 745:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * 746:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. 747:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval None 748:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ 749:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB2_GRP1_DisableClock(uint32_t Periphs) 750:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { 751:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** CLEAR_BIT(RCC->AHB2ENR, Periphs); 752:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } 753:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 754:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** 755:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Force AHB2 peripherals reset. 756:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll AHB2RSTR DCMIRST LL_AHB2_GRP1_ForceReset\n 757:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2RSTR JPEGRST LL_AHB2_GRP1_ForceReset\n 758:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2RSTR CRYPRST LL_AHB2_GRP1_ForceReset\n 759:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2RSTR AESRST LL_AHB2_GRP1_ForceReset\n 760:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2RSTR HASHRST LL_AHB2_GRP1_ForceReset\n 761:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2RSTR RNGRST LL_AHB2_GRP1_ForceReset\n 762:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2RSTR OTGFSRST LL_AHB2_GRP1_ForceReset 763:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: 764:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_ALL 765:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*) 766:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_JPEG (*) 767:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) 768:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*) 769:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) 770:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_RNG 771:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS 772:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * 773:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. 774:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval None 775:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ 776:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB2_GRP1_ForceReset(uint32_t Periphs) 777:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { 778:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** SET_BIT(RCC->AHB2RSTR, Periphs); 779:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } 780:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 781:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** 782:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Release AHB2 peripherals reset. 783:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll AHB2RSTR DCMIRST LL_AHB2_GRP1_ReleaseReset\n 784:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2RSTR JPEGRST LL_AHB2_GRP1_ReleaseReset\n 785:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2RSTR CRYPRST LL_AHB2_GRP1_ReleaseReset\n 786:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2RSTR AESRST LL_AHB2_GRP1_ReleaseReset\n 787:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2RSTR HASHRST LL_AHB2_GRP1_ReleaseReset\n 788:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2RSTR RNGRST LL_AHB2_GRP1_ReleaseReset\n 789:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2RSTR OTGFSRST LL_AHB2_GRP1_ReleaseReset 790:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: 791:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_ALL 792:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*) 793:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_JPEG (*) 794:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) 795:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*) 796:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) 797:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_RNG 798:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS 799:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * ARM GAS /tmp/ccdsDELB.s page 160 800:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. 801:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval None 802:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ 803:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB2_GRP1_ReleaseReset(uint32_t Periphs) 804:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { 805:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** CLEAR_BIT(RCC->AHB2RSTR, Periphs); 806:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } 807:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 808:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** 809:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Enable AHB2 peripheral clocks in low-power mode 810:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll AHB2LPENR DCMILPEN LL_AHB2_GRP1_EnableClockLowPower\n 811:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2LPENR JPEGLPEN LL_AHB2_GRP1_EnableClockLowPower\n 812:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2LPENR CRYPLPEN LL_AHB2_GRP1_EnableClockLowPower\n 813:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2LPENR AESLPEN LL_AHB2_GRP1_EnableClockLowPower\n 814:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2LPENR HASHLPEN LL_AHB2_GRP1_EnableClockLowPower\n 815:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2LPENR RNGLPEN LL_AHB2_GRP1_EnableClockLowPower\n 816:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2LPENR OTGFSLPEN LL_AHB2_GRP1_EnableClockLowPower 817:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: 818:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*) 819:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_JPEG (*) 820:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) 821:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*) 822:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) 823:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_RNG 824:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS 825:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * 826:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. 827:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval None 828:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ 829:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB2_GRP1_EnableClockLowPower(uint32_t Periphs) 830:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { 831:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __IO uint32_t tmpreg; 832:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** SET_BIT(RCC->AHB2LPENR, Periphs); 833:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Delay after an RCC peripheral clock enabling */ 834:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** tmpreg = READ_BIT(RCC->AHB2LPENR, Periphs); 835:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; 836:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } 837:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 838:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** 839:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Disable AHB2 peripheral clocks in low-power mode 840:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll AHB2LPENR DCMILPEN LL_AHB2_GRP1_DisableClockLowPower\n 841:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2LPENR JPEGLPEN LL_AHB2_GRP1_DisableClockLowPower\n 842:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2LPENR CRYPLPEN LL_AHB2_GRP1_DisableClockLowPower\n 843:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2LPENR AESLPEN LL_AHB2_GRP1_DisableClockLowPower\n 844:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2LPENR HASHLPEN LL_AHB2_GRP1_DisableClockLowPower\n 845:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2LPENR RNGLPEN LL_AHB2_GRP1_DisableClockLowPower\n 846:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2LPENR OTGFSLPEN LL_AHB2_GRP1_DisableClockLowPower 847:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: 848:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*) 849:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_JPEG (*) 850:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) 851:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*) 852:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) 853:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_RNG 854:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS 855:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * 856:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. ARM GAS /tmp/ccdsDELB.s page 161 857:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval None 858:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ 859:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB2_GRP1_DisableClockLowPower(uint32_t Periphs) 860:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { 861:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** CLEAR_BIT(RCC->AHB2LPENR, Periphs); 862:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } 863:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 864:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** 865:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @} 866:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ 867:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 868:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** @defgroup BUS_LL_EF_AHB3 AHB3 869:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @{ 870:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ 871:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 872:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** 873:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Enable AHB3 peripherals clock. 874:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll AHB3ENR FMCEN LL_AHB3_GRP1_EnableClock\n 875:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB3ENR QSPIEN LL_AHB3_GRP1_EnableClock 876:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: 877:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*) 878:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI 879:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * 880:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. 881:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval None 882:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ 883:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB3_GRP1_EnableClock(uint32_t Periphs) 884:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { 885:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __IO uint32_t tmpreg; 886:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** SET_BIT(RCC->AHB3ENR, Periphs); 887:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Delay after an RCC peripheral clock enabling */ 888:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** tmpreg = READ_BIT(RCC->AHB3ENR, Periphs); 889:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; 890:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } 891:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 892:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** 893:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Check if AHB3 peripheral clock is enabled or not 894:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll AHB3ENR FMCEN LL_AHB3_GRP1_IsEnabledClock\n 895:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB3ENR QSPIEN LL_AHB3_GRP1_IsEnabledClock 896:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: 897:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*) 898:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI 899:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * 900:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. 901:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval State of Periphs (1 or 0). 902:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ 903:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE uint32_t LL_AHB3_GRP1_IsEnabledClock(uint32_t Periphs) 904:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { 905:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** return (READ_BIT(RCC->AHB3ENR, Periphs) == Periphs); 906:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 908:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** 909:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Disable AHB3 peripherals clock. 910:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll AHB3ENR FMCEN LL_AHB3_GRP1_DisableClock\n 911:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB3ENR QSPIEN LL_AHB3_GRP1_DisableClock 912:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: 913:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*) ARM GAS /tmp/ccdsDELB.s page 162 914:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI 915:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * 916:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. 917:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval None 918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ 919:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB3_GRP1_DisableClock(uint32_t Periphs) 920:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { 921:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** CLEAR_BIT(RCC->AHB3ENR, Periphs); 922:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } 923:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 924:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** 925:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Force AHB3 peripherals reset. 926:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll AHB3RSTR FMCRST LL_AHB3_GRP1_ForceReset\n 927:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB3RSTR QSPIRST LL_AHB3_GRP1_ForceReset 928:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: 929:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB3_GRP1_PERIPH_ALL 930:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*) 931:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI 932:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * 933:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. 934:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval None 935:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ 936:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB3_GRP1_ForceReset(uint32_t Periphs) 937:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { 938:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** SET_BIT(RCC->AHB3RSTR, Periphs); 939:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } 940:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 941:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** 942:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Release AHB3 peripherals reset. 943:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll AHB3RSTR FMCRST LL_AHB3_GRP1_ReleaseReset\n 944:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB3RSTR QSPIRST LL_AHB3_GRP1_ReleaseReset 945:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: 946:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_ALL 947:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*) 948:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI 949:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * 950:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. 951:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval None 952:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ 953:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB3_GRP1_ReleaseReset(uint32_t Periphs) 954:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { 955:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** CLEAR_BIT(RCC->AHB3RSTR, Periphs); 956:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } 957:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 958:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** 959:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Enable AHB3 peripheral clocks in low-power mode 960:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll AHB3LPENR FMCLPEN LL_AHB3_GRP1_EnableClockLowPower\n 961:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB3LPENR QSPILPEN LL_AHB3_GRP1_EnableClockLowPower 962:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: 963:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*) 964:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI 965:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * 966:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. 967:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval None 968:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ 969:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB3_GRP1_EnableClockLowPower(uint32_t Periphs) 970:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { ARM GAS /tmp/ccdsDELB.s page 163 971:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __IO uint32_t tmpreg; 972:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** SET_BIT(RCC->AHB3LPENR, Periphs); 973:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Delay after an RCC peripheral clock enabling */ 974:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** tmpreg = READ_BIT(RCC->AHB3LPENR, Periphs); 975:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; 976:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } 977:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 978:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** 979:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Disable AHB3 peripheral clocks in low-power mode 980:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll AHB3LPENR FMCLPEN LL_AHB3_GRP1_DisableClockLowPower\n 981:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB3LPENR QSPILPEN LL_AHB3_GRP1_DisableClockLowPower 982:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: 983:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*) 984:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI 985:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * 986:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. 987:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval None 988:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ 989:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB3_GRP1_DisableClockLowPower(uint32_t Periphs) 990:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { 991:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** CLEAR_BIT(RCC->AHB3LPENR, Periphs); 992:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } 993:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 994:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** 995:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @} 996:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ 997:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 998:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** @defgroup BUS_LL_EF_APB1 APB1 999:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @{ 1000:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ 1001:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 1002:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** 1003:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Enable APB1 peripherals clock. 1004:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_EnableClock\n 1005:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR TIM3EN LL_APB1_GRP1_EnableClock\n 1006:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR TIM4EN LL_APB1_GRP1_EnableClock\n 1007:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR TIM5EN LL_APB1_GRP1_EnableClock\n 1008:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR TIM6EN LL_APB1_GRP1_EnableClock\n 1009:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR TIM7EN LL_APB1_GRP1_EnableClock\n 1010:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR TIM12EN LL_APB1_GRP1_EnableClock\n 1011:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR TIM13EN LL_APB1_GRP1_EnableClock\n 1012:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR TIM14EN LL_APB1_GRP1_EnableClock\n 1013:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR LPTIM1EN LL_APB1_GRP1_EnableClock\n 1014:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR WWDGEN LL_APB1_GRP1_EnableClock\n 1015:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR SPI2EN LL_APB1_GRP1_EnableClock\n 1016:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR SPI3EN LL_APB1_GRP1_EnableClock\n 1017:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR SPDIFRXEN LL_APB1_GRP1_EnableClock\n 1018:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR USART2EN LL_APB1_GRP1_EnableClock\n 1019:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR USART3EN LL_APB1_GRP1_EnableClock\n 1020:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR UART4EN LL_APB1_GRP1_EnableClock\n 1021:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR UART5EN LL_APB1_GRP1_EnableClock\n 1022:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR I2C1EN LL_APB1_GRP1_EnableClock\n 1023:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR I2C2EN LL_APB1_GRP1_EnableClock\n 1024:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR I2C3EN LL_APB1_GRP1_EnableClock\n 1025:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR I2C4EN LL_APB1_GRP1_EnableClock\n 1026:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR CAN1EN LL_APB1_GRP1_EnableClock\n 1027:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR CAN2EN LL_APB1_GRP1_EnableClock\n ARM GAS /tmp/ccdsDELB.s page 164 1028:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR CAN3EN LL_APB1_GRP1_EnableClock\n 1029:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR CECEN LL_APB1_GRP1_EnableClock\n 1030:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR PWREN LL_APB1_GRP1_EnableClock\n 1031:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR DACEN LL_APB1_GRP1_EnableClock\n 1032:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR UART7EN LL_APB1_GRP1_EnableClock\n 1033:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR UART8EN LL_APB1_GRP1_EnableClock\n 1034:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR RTCEN LL_APB1_GRP1_EnableClock 1035:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: 1036:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 1037:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 1038:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 1039:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 1040:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 1041:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 1042:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 1043:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 1044:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 1045:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 1046:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_WWDG 1047:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 1048:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 1049:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*) 1050:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART2 1051:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART3 1052:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART4 1053:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART5 1054:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 1055:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 1056:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 1057:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C4 (*) 1058:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 1059:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*) 1060:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*) 1061:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) 1062:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_PWR 1063:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 1064:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART7 1065:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART8 1066:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*) 1067:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * 1068:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. 1069:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval None 1070:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ 1071:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs) 1072:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { 1073:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __IO uint32_t tmpreg; 1074:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** SET_BIT(RCC->APB1ENR, Periphs); 1075:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Delay after an RCC peripheral clock enabling */ 1076:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** tmpreg = READ_BIT(RCC->APB1ENR, Periphs); 1077:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; 1078:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } 1079:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 1080:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** 1081:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Check if APB1 peripheral clock is enabled or not 1082:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_IsEnabledClock\n 1083:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR TIM3EN LL_APB1_GRP1_IsEnabledClock\n 1084:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR TIM4EN LL_APB1_GRP1_IsEnabledClock\n ARM GAS /tmp/ccdsDELB.s page 165 1085:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR TIM5EN LL_APB1_GRP1_IsEnabledClock\n 1086:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR TIM6EN LL_APB1_GRP1_IsEnabledClock\n 1087:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR TIM7EN LL_APB1_GRP1_IsEnabledClock\n 1088:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR TIM12EN LL_APB1_GRP1_IsEnabledClock\n 1089:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR TIM13EN LL_APB1_GRP1_IsEnabledClock\n 1090:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR TIM14EN LL_APB1_GRP1_IsEnabledClock\n 1091:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR LPTIM1EN LL_APB1_GRP1_IsEnabledClock\n 1092:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR WWDGEN LL_APB1_GRP1_IsEnabledClock\n 1093:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR SPI2EN LL_APB1_GRP1_IsEnabledClock\n 1094:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR SPI3EN LL_APB1_GRP1_IsEnabledClock\n 1095:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR SPDIFRXEN LL_APB1_GRP1_IsEnabledClock\n 1096:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR USART2EN LL_APB1_GRP1_IsEnabledClock\n 1097:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR USART3EN LL_APB1_GRP1_IsEnabledClock\n 1098:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR UART4EN LL_APB1_GRP1_IsEnabledClock\n 1099:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR UART5EN LL_APB1_GRP1_IsEnabledClock\n 1100:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR I2C1EN LL_APB1_GRP1_IsEnabledClock\n 1101:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR I2C2EN LL_APB1_GRP1_IsEnabledClock\n 1102:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR I2C3EN LL_APB1_GRP1_IsEnabledClock\n 1103:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR I2C4EN LL_APB1_GRP1_IsEnabledClock\n 1104:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR CAN1EN LL_APB1_GRP1_IsEnabledClock\n 1105:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR CAN2EN LL_APB1_GRP1_IsEnabledClock\n 1106:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR CAN3EN LL_APB1_GRP1_IsEnabledClock\n 1107:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR CECEN LL_APB1_GRP1_IsEnabledClock\n 1108:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR PWREN LL_APB1_GRP1_IsEnabledClock\n 1109:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR DACEN LL_APB1_GRP1_IsEnabledClock\n 1110:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR UART7EN LL_APB1_GRP1_IsEnabledClock\n 1111:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR UART8EN LL_APB1_GRP1_IsEnabledClock\n 1112:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR RTCEN LL_APB1_GRP1_IsEnabledClock 1113:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: 1114:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 1115:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 1116:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 1117:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 1118:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 1119:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 1120:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 1121:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 1122:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 1123:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 1124:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_WWDG 1125:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 1126:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 1127:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*) 1128:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART2 1129:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART3 1130:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART4 1131:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART5 1132:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 1133:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 1134:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 1135:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C4 (*) 1136:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 1137:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*) 1138:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*) 1139:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) 1140:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_PWR 1141:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 ARM GAS /tmp/ccdsDELB.s page 166 1142:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART7 1143:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART8 1144:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*) 1145:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * 1146:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. 1147:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval State of Periphs (1 or 0). 1148:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ 1149:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs) 1150:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { 1151:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** return (READ_BIT(RCC->APB1ENR, Periphs) == Periphs); 1152:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } 1153:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 1154:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** 1155:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Disable APB1 peripherals clock. 1156:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_DisableClock\n 1157:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR TIM3EN LL_APB1_GRP1_DisableClock\n 1158:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR TIM4EN LL_APB1_GRP1_DisableClock\n 1159:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR TIM5EN LL_APB1_GRP1_DisableClock\n 1160:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR TIM6EN LL_APB1_GRP1_DisableClock\n 1161:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR TIM7EN LL_APB1_GRP1_DisableClock\n 1162:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR TIM12EN LL_APB1_GRP1_DisableClock\n 1163:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR TIM13EN LL_APB1_GRP1_DisableClock\n 1164:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR TIM14EN LL_APB1_GRP1_DisableClock\n 1165:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR LPTIM1EN LL_APB1_GRP1_DisableClock\n 1166:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR WWDGEN LL_APB1_GRP1_DisableClock\n 1167:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR SPI2EN LL_APB1_GRP1_DisableClock\n 1168:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR SPI3EN LL_APB1_GRP1_DisableClock\n 1169:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR SPDIFRXEN LL_APB1_GRP1_DisableClock\n 1170:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR USART2EN LL_APB1_GRP1_DisableClock\n 1171:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR USART3EN LL_APB1_GRP1_DisableClock\n 1172:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR UART4EN LL_APB1_GRP1_DisableClock\n 1173:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR UART5EN LL_APB1_GRP1_DisableClock\n 1174:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR I2C1EN LL_APB1_GRP1_DisableClock\n 1175:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR I2C2EN LL_APB1_GRP1_DisableClock\n 1176:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR I2C3EN LL_APB1_GRP1_DisableClock\n 1177:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR I2C4EN LL_APB1_GRP1_DisableClock\n 1178:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR CAN1EN LL_APB1_GRP1_DisableClock\n 1179:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR CAN2EN LL_APB1_GRP1_DisableClock\n 1180:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR CAN3EN LL_APB1_GRP1_DisableClock\n 1181:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR CECEN LL_APB1_GRP1_DisableClock\n 1182:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR PWREN LL_APB1_GRP1_DisableClock\n 1183:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR DACEN LL_APB1_GRP1_DisableClock\n 1184:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR UART7EN LL_APB1_GRP1_DisableClock\n 1185:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR UART8EN LL_APB1_GRP1_DisableClock\n 1186:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR RTCEN LL_APB1_GRP1_DisableClock 1187:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: 1188:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 1189:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 1190:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 1191:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 1192:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 1193:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 1194:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 1195:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 1196:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 1197:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 1198:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_WWDG ARM GAS /tmp/ccdsDELB.s page 167 1199:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 1200:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 1201:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*) 1202:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART2 1203:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART3 1204:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART4 1205:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART5 1206:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 1207:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 1208:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 1209:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C4 (*) 1210:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 1211:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*) 1212:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*) 1213:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) 1214:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_PWR 1215:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 1216:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART7 1217:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART8 1218:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*) 1219:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * 1220:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. 1221:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval None 1222:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ 1223:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_APB1_GRP1_DisableClock(uint32_t Periphs) 1224:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { 1225:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** CLEAR_BIT(RCC->APB1ENR, Periphs); 1226:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } 1227:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 1228:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** 1229:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Force APB1 peripherals reset. 1230:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll APB1RSTR TIM2RST LL_APB1_GRP1_ForceReset\n 1231:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR TIM3RST LL_APB1_GRP1_ForceReset\n 1232:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR TIM4RST LL_APB1_GRP1_ForceReset\n 1233:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR TIM5RST LL_APB1_GRP1_ForceReset\n 1234:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR TIM6RST LL_APB1_GRP1_ForceReset\n 1235:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR TIM7RST LL_APB1_GRP1_ForceReset\n 1236:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR TIM12RST LL_APB1_GRP1_ForceReset\n 1237:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR TIM13RST LL_APB1_GRP1_ForceReset\n 1238:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR TIM14RST LL_APB1_GRP1_ForceReset\n 1239:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR LPTIM1RST LL_APB1_GRP1_ForceReset\n 1240:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR WWDGRST LL_APB1_GRP1_ForceReset\n 1241:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR SPI2RST LL_APB1_GRP1_ForceReset\n 1242:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR SPI3RST LL_APB1_GRP1_ForceReset\n 1243:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR SPDIFRXRST LL_APB1_GRP1_ForceReset\n 1244:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR USART2RST LL_APB1_GRP1_ForceReset\n 1245:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR USART3RST LL_APB1_GRP1_ForceReset\n 1246:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR UART4RST LL_APB1_GRP1_ForceReset\n 1247:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR UART5RST LL_APB1_GRP1_ForceReset\n 1248:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR I2C1RST LL_APB1_GRP1_ForceReset\n 1249:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR I2C2RST LL_APB1_GRP1_ForceReset\n 1250:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR I2C3RST LL_APB1_GRP1_ForceReset\n 1251:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR I2C4RST LL_APB1_GRP1_ForceReset\n 1252:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR CAN1RST LL_APB1_GRP1_ForceReset\n 1253:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR CAN2RST LL_APB1_GRP1_ForceReset\n 1254:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR CAN3RST LL_APB1_GRP1_ForceReset\n 1255:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR CECRST LL_APB1_GRP1_ForceReset\n ARM GAS /tmp/ccdsDELB.s page 168 1256:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR PWRRST LL_APB1_GRP1_ForceReset\n 1257:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR DACRST LL_APB1_GRP1_ForceReset\n 1258:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR UART7RST LL_APB1_GRP1_ForceReset\n 1259:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR UART8RST LL_APB1_GRP1_ForceReset 1260:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: 1261:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 1262:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 1263:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 1264:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 1265:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 1266:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 1267:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 1268:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 1269:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 1270:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 1271:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_WWDG 1272:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 1273:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 1274:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*) 1275:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART2 1276:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART3 1277:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART4 1278:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART5 1279:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 1280:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 1281:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 1282:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C4 (*) 1283:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 1284:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*) 1285:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*) 1286:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) 1287:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_PWR 1288:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 1289:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART7 1290:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART8 1291:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * 1292:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. 1293:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval None 1294:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ 1295:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_APB1_GRP1_ForceReset(uint32_t Periphs) 1296:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { 1297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** SET_BIT(RCC->APB1RSTR, Periphs); 1298:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } 1299:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 1300:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** 1301:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Release APB1 peripherals reset. 1302:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll APB1RSTR TIM2RST LL_APB1_GRP1_ReleaseReset\n 1303:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR TIM3RST LL_APB1_GRP1_ReleaseReset\n 1304:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR TIM4RST LL_APB1_GRP1_ReleaseReset\n 1305:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR TIM5RST LL_APB1_GRP1_ReleaseReset\n 1306:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR TIM6RST LL_APB1_GRP1_ReleaseReset\n 1307:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR TIM7RST LL_APB1_GRP1_ReleaseReset\n 1308:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR TIM12RST LL_APB1_GRP1_ReleaseReset\n 1309:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR TIM13RST LL_APB1_GRP1_ReleaseReset\n 1310:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR TIM14RST LL_APB1_GRP1_ReleaseReset\n 1311:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR LPTIM1RST LL_APB1_GRP1_ReleaseReset\n 1312:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR WWDGRST LL_APB1_GRP1_ReleaseReset\n ARM GAS /tmp/ccdsDELB.s page 169 1313:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR SPI2RST LL_APB1_GRP1_ReleaseReset\n 1314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR SPI3RST LL_APB1_GRP1_ReleaseReset\n 1315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR SPDIFRXRST LL_APB1_GRP1_ReleaseReset\n 1316:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR USART2RST LL_APB1_GRP1_ReleaseReset\n 1317:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR USART3RST LL_APB1_GRP1_ReleaseReset\n 1318:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR UART4RST LL_APB1_GRP1_ReleaseReset\n 1319:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR UART5RST LL_APB1_GRP1_ReleaseReset\n 1320:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR I2C1RST LL_APB1_GRP1_ReleaseReset\n 1321:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR I2C2RST LL_APB1_GRP1_ReleaseReset\n 1322:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR I2C3RST LL_APB1_GRP1_ReleaseReset\n 1323:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR I2C4RST LL_APB1_GRP1_ReleaseReset\n 1324:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR CAN1RST LL_APB1_GRP1_ReleaseReset\n 1325:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR CAN2RST LL_APB1_GRP1_ReleaseReset\n 1326:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR CAN3RST LL_APB1_GRP1_ReleaseReset\n 1327:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR CECRST LL_APB1_GRP1_ReleaseReset\n 1328:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR PWRRST LL_APB1_GRP1_ReleaseReset\n 1329:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR DACRST LL_APB1_GRP1_ReleaseReset\n 1330:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR UART7RST LL_APB1_GRP1_ReleaseReset\n 1331:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR UART8RST LL_APB1_GRP1_ReleaseReset 1332:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: 1333:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 1334:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 1335:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 1336:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 1337:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 1338:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 1339:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 1340:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 1341:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 1342:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 1343:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_WWDG 1344:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 1345:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 1346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*) 1347:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART2 1348:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART3 1349:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART4 1350:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART5 1351:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 1352:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 1353:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 1354:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C4 (*) 1355:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 1356:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*) 1357:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*) 1358:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) 1359:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_PWR 1360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 1361:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART7 1362:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART8 1363:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * 1364:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. 1365:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval None 1366:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ 1367:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_APB1_GRP1_ReleaseReset(uint32_t Periphs) 1368:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { 1369:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** CLEAR_BIT(RCC->APB1RSTR, Periphs); ARM GAS /tmp/ccdsDELB.s page 170 1370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } 1371:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 1372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** 1373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Enable APB1 peripheral clocks in low-power mode 1374:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll APB1LPENR TIM2LPEN LL_APB1_GRP1_EnableClockLowPower\n 1375:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR TIM3LPEN LL_APB1_GRP1_EnableClockLowPower\n 1376:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR TIM4LPEN LL_APB1_GRP1_EnableClockLowPower\n 1377:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR TIM5LPEN LL_APB1_GRP1_EnableClockLowPower\n 1378:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR TIM6LPEN LL_APB1_GRP1_EnableClockLowPower\n 1379:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR TIM7LPEN LL_APB1_GRP1_EnableClockLowPower\n 1380:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR TIM12LPEN LL_APB1_GRP1_EnableClockLowPower\n 1381:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR TIM13LPEN LL_APB1_GRP1_EnableClockLowPower\n 1382:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR TIM14LPEN LL_APB1_GRP1_EnableClockLowPower\n 1383:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR LPTIM1LPEN LL_APB1_GRP1_EnableClockLowPower\n 1384:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR WWDGLPEN LL_APB1_GRP1_EnableClockLowPower\n 1385:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR SPI2LPEN LL_APB1_GRP1_EnableClockLowPower\n 1386:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR SPI3LPEN LL_APB1_GRP1_EnableClockLowPower\n 1387:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR SPDIFRXLPEN LL_APB1_GRP1_EnableClockLowPower\n 1388:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR USART2LPEN LL_APB1_GRP1_EnableClockLowPower\n 1389:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR USART3LPEN LL_APB1_GRP1_EnableClockLowPower\n 1390:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR UART4LPEN LL_APB1_GRP1_EnableClockLowPower\n 1391:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR UART5LPEN LL_APB1_GRP1_EnableClockLowPower\n 1392:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR I2C1LPEN LL_APB1_GRP1_EnableClockLowPower\n 1393:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR I2C2LPEN LL_APB1_GRP1_EnableClockLowPower\n 1394:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR I2C3LPEN LL_APB1_GRP1_EnableClockLowPower\n 1395:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR I2C4LPEN LL_APB1_GRP1_EnableClockLowPower\n 1396:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR CAN1LPEN LL_APB1_GRP1_EnableClockLowPower\n 1397:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR CAN2LPEN LL_APB1_GRP1_EnableClockLowPower\n 1398:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR CAN3LPEN LL_APB1_GRP1_EnableClockLowPower\n 1399:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR CECLPEN LL_APB1_GRP1_EnableClockLowPower\n 1400:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR PWRLPEN LL_APB1_GRP1_EnableClockLowPower\n 1401:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR DACLPEN LL_APB1_GRP1_EnableClockLowPower\n 1402:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR UART7LPEN LL_APB1_GRP1_EnableClockLowPower\n 1403:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR UART8LPEN LL_APB1_GRP1_EnableClockLowPower\n 1404:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR RTCLPEN LL_APB1_GRP1_EnableClockLowPower 1405:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: 1406:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 1407:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 1408:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 1409:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 1410:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 1411:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 1412:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 1413:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 1414:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 1415:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 1416:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_WWDG 1417:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 1418:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 1419:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*) 1420:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART2 1421:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART3 1422:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART4 1423:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART5 1424:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 1425:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 1426:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 ARM GAS /tmp/ccdsDELB.s page 171 1427:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C4 (*) 1428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 1429:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*) 1430:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*) 1431:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) 1432:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_PWR 1433:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 1434:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART7 1435:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART8 1436:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*) 1437:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * 1438:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. 1439:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval None 1440:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ 1441:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_APB1_GRP1_EnableClockLowPower(uint32_t Periphs) 1442:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { 1443:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __IO uint32_t tmpreg; 1444:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** SET_BIT(RCC->APB1LPENR, Periphs); 1445:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Delay after an RCC peripheral clock enabling */ 1446:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** tmpreg = READ_BIT(RCC->APB1LPENR, Periphs); 1447:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; 1448:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } 1449:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 1450:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** 1451:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Disable APB1 peripheral clocks in low-power mode 1452:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll APB1LPENR TIM2LPEN LL_APB1_GRP1_DisableClockLowPower\n 1453:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR TIM3LPEN LL_APB1_GRP1_DisableClockLowPower\n 1454:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR TIM4LPEN LL_APB1_GRP1_DisableClockLowPower\n 1455:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR TIM5LPEN LL_APB1_GRP1_DisableClockLowPower\n 1456:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR TIM6LPEN LL_APB1_GRP1_DisableClockLowPower\n 1457:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR TIM7LPEN LL_APB1_GRP1_DisableClockLowPower\n 1458:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR TIM12LPEN LL_APB1_GRP1_DisableClockLowPower\n 1459:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR TIM13LPEN LL_APB1_GRP1_DisableClockLowPower\n 1460:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR TIM14LPEN LL_APB1_GRP1_DisableClockLowPower\n 1461:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR LPTIM1LPEN LL_APB1_GRP1_DisableClockLowPower\n 1462:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR WWDGLPEN LL_APB1_GRP1_DisableClockLowPower\n 1463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR SPI2LPEN LL_APB1_GRP1_DisableClockLowPower\n 1464:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR SPI3LPEN LL_APB1_GRP1_DisableClockLowPower\n 1465:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR SPDIFRXLPEN LL_APB1_GRP1_DisableClockLowPower\n 1466:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR USART2LPEN LL_APB1_GRP1_DisableClockLowPower\n 1467:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR USART3LPEN LL_APB1_GRP1_DisableClockLowPower\n 1468:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR UART4LPEN LL_APB1_GRP1_DisableClockLowPower\n 1469:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR UART5LPEN LL_APB1_GRP1_DisableClockLowPower\n 1470:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR I2C1LPEN LL_APB1_GRP1_DisableClockLowPower\n 1471:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR I2C2LPEN LL_APB1_GRP1_DisableClockLowPower\n 1472:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR I2C3LPEN LL_APB1_GRP1_DisableClockLowPower\n 1473:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR I2C4LPEN LL_APB1_GRP1_DisableClockLowPower\n 1474:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR CAN1LPEN LL_APB1_GRP1_DisableClockLowPower\n 1475:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR CAN2LPEN LL_APB1_GRP1_DisableClockLowPower\n 1476:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR CAN3LPEN LL_APB1_GRP1_DisableClockLowPower\n 1477:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR CECLPEN LL_APB1_GRP1_DisableClockLowPower\n 1478:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR PWRLPEN LL_APB1_GRP1_DisableClockLowPower\n 1479:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR DACLPEN LL_APB1_GRP1_DisableClockLowPower\n 1480:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR UART7LPEN LL_APB1_GRP1_DisableClockLowPower\n 1481:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR UART8LPEN LL_APB1_GRP1_DisableClockLowPower\n 1482:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR RTCLPEN LL_APB1_GRP1_DisableClockLowPower 1483:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: ARM GAS /tmp/ccdsDELB.s page 172 1484:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 1485:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 1486:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 1487:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 1488:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 1489:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 1490:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 1491:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 1492:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 1493:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 1494:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_WWDG 1495:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 1496:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 1497:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*) 1498:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART2 1499:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART3 1500:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART4 1501:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART5 1502:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 1503:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 1504:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 1505:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C4 (*) 1506:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 1507:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*) 1508:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*) 1509:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) 1510:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_PWR 1511:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 1512:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART7 1513:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART8 1514:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*) 1515:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * 1516:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. 1517:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval None 1518:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ 1519:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_APB1_GRP1_DisableClockLowPower(uint32_t Periphs) 1520:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { 1521:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** CLEAR_BIT(RCC->APB1LPENR, Periphs); 1522:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } 1523:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 1524:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** 1525:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @} 1526:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ 1527:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 1528:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** @defgroup BUS_LL_EF_APB2 APB2 1529:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @{ 1530:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ 1531:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 1532:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** 1533:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Enable APB2 peripherals clock. 1534:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll APB2ENR TIM1EN LL_APB2_GRP1_EnableClock\n 1535:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR TIM8EN LL_APB2_GRP1_EnableClock\n 1536:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR USART1EN LL_APB2_GRP1_EnableClock\n 1537:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR USART6EN LL_APB2_GRP1_EnableClock\n 1538:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR ADC1EN LL_APB2_GRP1_EnableClock\n 1539:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR ADC2EN LL_APB2_GRP1_EnableClock\n 1540:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR ADC3EN LL_APB2_GRP1_EnableClock\n ARM GAS /tmp/ccdsDELB.s page 173 1541:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR SDMMC1EN LL_APB2_GRP1_EnableClock\n 1542:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR SDMMC2EN LL_APB2_GRP1_EnableClock\n 1543:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR SPI1EN LL_APB2_GRP1_EnableClock\n 1544:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR SPI4EN LL_APB2_GRP1_EnableClock\n 1545:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR SYSCFGEN LL_APB2_GRP1_EnableClock\n 1546:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR TIM9EN LL_APB2_GRP1_EnableClock\n 1547:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR TIM10EN LL_APB2_GRP1_EnableClock\n 1548:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR TIM11EN LL_APB2_GRP1_EnableClock\n 1549:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR SPI5EN LL_APB2_GRP1_EnableClock\n 1550:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR SPI6EN LL_APB2_GRP1_EnableClock\n 1551:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR SAI1EN LL_APB2_GRP1_EnableClock\n 1552:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR SAI2EN LL_APB2_GRP1_EnableClock\n 1553:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR LTDCEN LL_APB2_GRP1_EnableClock\n 1554:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR DSIEN LL_APB2_GRP1_EnableClock\n 1555:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR DFSDM1EN LL_APB2_GRP1_EnableClock\n 1556:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR MDIOEN LL_APB2_GRP1_EnableClock\n 1557:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR OTGPHYCEN LL_APB2_GRP1_EnableClock 1558:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: 1559:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 1560:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 1561:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_USART1 1562:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_USART6 1563:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_ADC1 1564:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_ADC2 1565:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_ADC3 1566:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1 1567:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC2 (*) 1568:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 1569:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 1570:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG 1571:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_TIM9 1572:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_TIM10 1573:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_TIM11 1574:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 1575:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*) 1576:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 1577:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 1578:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*) 1579:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*) 1580:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*) 1581:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_MDIO (*) 1582:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_OTGPHYC (*) 1583:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * 1584:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. 1585:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval None 1586:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ 1587:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_APB2_GRP1_EnableClock(uint32_t Periphs) 2274 .loc 3 1587 22 view .LVU775 2275 .LBB365: 1588:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { 1589:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __IO uint32_t tmpreg; 2276 .loc 3 1589 3 view .LVU776 1590:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** SET_BIT(RCC->APB2ENR, Periphs); 2277 .loc 3 1590 3 view .LVU777 2278 001e 2A4B ldr r3, .L114 2279 0020 5A6C ldr r2, [r3, #68] 2280 0022 42F40052 orr r2, r2, #8192 ARM GAS /tmp/ccdsDELB.s page 174 2281 0026 5A64 str r2, [r3, #68] 1591:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Delay after an RCC peripheral clock enabling */ 1592:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** tmpreg = READ_BIT(RCC->APB2ENR, Periphs); 2282 .loc 3 1592 3 view .LVU778 2283 .loc 3 1592 12 is_stmt 0 view .LVU779 2284 0028 5A6C ldr r2, [r3, #68] 2285 002a 02F40052 and r2, r2, #8192 2286 .loc 3 1592 10 view .LVU780 2287 002e 0192 str r2, [sp, #4] 1593:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; 2288 .loc 3 1593 3 is_stmt 1 view .LVU781 2289 0030 019A ldr r2, [sp, #4] 2290 .LVL200: 2291 .loc 3 1593 3 is_stmt 0 view .LVU782 2292 .LBE365: 2293 .LBE364: 849:Src/main.c **** /**SPI4 GPIO Configuration 2294 .loc 2 849 3 is_stmt 1 view .LVU783 2295 .LBB366: 2296 .LBI366: 309:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { 2297 .loc 3 309 22 view .LVU784 2298 .LBB367: 311:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** SET_BIT(RCC->AHB1ENR, Periphs); 2299 .loc 3 311 3 view .LVU785 312:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Delay after an RCC peripheral clock enabling */ 2300 .loc 3 312 3 view .LVU786 2301 0032 1A6B ldr r2, [r3, #48] 2302 0034 42F01002 orr r2, r2, #16 2303 0038 1A63 str r2, [r3, #48] 314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; 2304 .loc 3 314 3 view .LVU787 314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; 2305 .loc 3 314 12 is_stmt 0 view .LVU788 2306 003a 1B6B ldr r3, [r3, #48] 2307 003c 03F01003 and r3, r3, #16 314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; 2308 .loc 3 314 10 view .LVU789 2309 0040 0093 str r3, [sp] 315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } 2310 .loc 3 315 3 is_stmt 1 view .LVU790 2311 0042 009B ldr r3, [sp] 2312 .LVL201: 315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } 2313 .loc 3 315 3 is_stmt 0 view .LVU791 2314 .LBE367: 2315 .LBE366: 854:Src/main.c **** GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE; 2316 .loc 2 854 3 is_stmt 1 view .LVU792 854:Src/main.c **** GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE; 2317 .loc 2 854 23 is_stmt 0 view .LVU793 2318 0044 4FF48053 mov r3, #4096 2319 0048 0293 str r3, [sp, #8] 855:Src/main.c **** GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH; 2320 .loc 2 855 3 is_stmt 1 view .LVU794 855:Src/main.c **** GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH; 2321 .loc 2 855 24 is_stmt 0 view .LVU795 ARM GAS /tmp/ccdsDELB.s page 175 2322 004a 0225 movs r5, #2 2323 004c 0395 str r5, [sp, #12] 856:Src/main.c **** GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; 2324 .loc 2 856 3 is_stmt 1 view .LVU796 856:Src/main.c **** GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; 2325 .loc 2 856 25 is_stmt 0 view .LVU797 2326 004e 4FF00308 mov r8, #3 2327 0052 CDF81080 str r8, [sp, #16] 857:Src/main.c **** GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; 2328 .loc 2 857 3 is_stmt 1 view .LVU798 858:Src/main.c **** GPIO_InitStruct.Alternate = LL_GPIO_AF_5; 2329 .loc 2 858 3 view .LVU799 859:Src/main.c **** LL_GPIO_Init(GPIOE, &GPIO_InitStruct); 2330 .loc 2 859 3 view .LVU800 859:Src/main.c **** LL_GPIO_Init(GPIOE, &GPIO_InitStruct); 2331 .loc 2 859 29 is_stmt 0 view .LVU801 2332 0056 0527 movs r7, #5 2333 0058 0797 str r7, [sp, #28] 860:Src/main.c **** 2334 .loc 2 860 3 is_stmt 1 view .LVU802 2335 005a 1C4E ldr r6, .L114+4 2336 005c 02A9 add r1, sp, #8 2337 005e 3046 mov r0, r6 2338 0060 FFF7FEFF bl LL_GPIO_Init 2339 .LVL202: 862:Src/main.c **** GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE; 2340 .loc 2 862 3 view .LVU803 862:Src/main.c **** GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE; 2341 .loc 2 862 23 is_stmt 0 view .LVU804 2342 0064 4FF40053 mov r3, #8192 2343 0068 0293 str r3, [sp, #8] 863:Src/main.c **** GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH; 2344 .loc 2 863 3 is_stmt 1 view .LVU805 863:Src/main.c **** GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH; 2345 .loc 2 863 24 is_stmt 0 view .LVU806 2346 006a 0395 str r5, [sp, #12] 864:Src/main.c **** GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; 2347 .loc 2 864 3 is_stmt 1 view .LVU807 864:Src/main.c **** GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; 2348 .loc 2 864 25 is_stmt 0 view .LVU808 2349 006c CDF81080 str r8, [sp, #16] 865:Src/main.c **** GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; 2350 .loc 2 865 3 is_stmt 1 view .LVU809 865:Src/main.c **** GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; 2351 .loc 2 865 30 is_stmt 0 view .LVU810 2352 0070 0594 str r4, [sp, #20] 866:Src/main.c **** GPIO_InitStruct.Alternate = LL_GPIO_AF_5; 2353 .loc 2 866 3 is_stmt 1 view .LVU811 866:Src/main.c **** GPIO_InitStruct.Alternate = LL_GPIO_AF_5; 2354 .loc 2 866 24 is_stmt 0 view .LVU812 2355 0072 0694 str r4, [sp, #24] 867:Src/main.c **** LL_GPIO_Init(GPIOE, &GPIO_InitStruct); 2356 .loc 2 867 3 is_stmt 1 view .LVU813 867:Src/main.c **** LL_GPIO_Init(GPIOE, &GPIO_InitStruct); 2357 .loc 2 867 29 is_stmt 0 view .LVU814 2358 0074 0797 str r7, [sp, #28] 868:Src/main.c **** ARM GAS /tmp/ccdsDELB.s page 176 2359 .loc 2 868 3 is_stmt 1 view .LVU815 2360 0076 02A9 add r1, sp, #8 2361 0078 3046 mov r0, r6 2362 007a FFF7FEFF bl LL_GPIO_Init 2363 .LVL203: 874:Src/main.c **** SPI_InitStruct.Mode = LL_SPI_MODE_MASTER; 2364 .loc 2 874 3 view .LVU816 874:Src/main.c **** SPI_InitStruct.Mode = LL_SPI_MODE_MASTER; 2365 .loc 2 874 36 is_stmt 0 view .LVU817 2366 007e 4FF48063 mov r3, #1024 2367 0082 0893 str r3, [sp, #32] 875:Src/main.c **** SPI_InitStruct.DataWidth = LL_SPI_DATAWIDTH_16BIT; 2368 .loc 2 875 3 is_stmt 1 view .LVU818 875:Src/main.c **** SPI_InitStruct.DataWidth = LL_SPI_DATAWIDTH_16BIT; 2369 .loc 2 875 23 is_stmt 0 view .LVU819 2370 0084 4FF48273 mov r3, #260 2371 0088 0993 str r3, [sp, #36] 876:Src/main.c **** SPI_InitStruct.ClockPolarity = LL_SPI_POLARITY_HIGH; 2372 .loc 2 876 3 is_stmt 1 view .LVU820 876:Src/main.c **** SPI_InitStruct.ClockPolarity = LL_SPI_POLARITY_HIGH; 2373 .loc 2 876 28 is_stmt 0 view .LVU821 2374 008a 4FF47063 mov r3, #3840 2375 008e 0A93 str r3, [sp, #40] 877:Src/main.c **** SPI_InitStruct.ClockPhase = LL_SPI_PHASE_1EDGE; 2376 .loc 2 877 3 is_stmt 1 view .LVU822 877:Src/main.c **** SPI_InitStruct.ClockPhase = LL_SPI_PHASE_1EDGE; 2377 .loc 2 877 32 is_stmt 0 view .LVU823 2378 0090 0B95 str r5, [sp, #44] 878:Src/main.c **** SPI_InitStruct.NSS = LL_SPI_NSS_SOFT; 2379 .loc 2 878 3 is_stmt 1 view .LVU824 878:Src/main.c **** SPI_InitStruct.NSS = LL_SPI_NSS_SOFT; 2380 .loc 2 878 29 is_stmt 0 view .LVU825 2381 0092 0C94 str r4, [sp, #48] 879:Src/main.c **** SPI_InitStruct.BaudRate = LL_SPI_BAUDRATEPRESCALER_DIV16; 2382 .loc 2 879 3 is_stmt 1 view .LVU826 879:Src/main.c **** SPI_InitStruct.BaudRate = LL_SPI_BAUDRATEPRESCALER_DIV16; 2383 .loc 2 879 22 is_stmt 0 view .LVU827 2384 0094 4FF40073 mov r3, #512 2385 0098 0D93 str r3, [sp, #52] 880:Src/main.c **** SPI_InitStruct.BitOrder = LL_SPI_MSB_FIRST; 2386 .loc 2 880 3 is_stmt 1 view .LVU828 880:Src/main.c **** SPI_InitStruct.BitOrder = LL_SPI_MSB_FIRST; 2387 .loc 2 880 27 is_stmt 0 view .LVU829 2388 009a 1823 movs r3, #24 2389 009c 0E93 str r3, [sp, #56] 881:Src/main.c **** SPI_InitStruct.CRCCalculation = LL_SPI_CRCCALCULATION_DISABLE; 2390 .loc 2 881 3 is_stmt 1 view .LVU830 881:Src/main.c **** SPI_InitStruct.CRCCalculation = LL_SPI_CRCCALCULATION_DISABLE; 2391 .loc 2 881 27 is_stmt 0 view .LVU831 2392 009e 0F94 str r4, [sp, #60] 882:Src/main.c **** SPI_InitStruct.CRCPoly = 7; 2393 .loc 2 882 3 is_stmt 1 view .LVU832 882:Src/main.c **** SPI_InitStruct.CRCPoly = 7; 2394 .loc 2 882 33 is_stmt 0 view .LVU833 2395 00a0 1094 str r4, [sp, #64] 883:Src/main.c **** LL_SPI_Init(SPI4, &SPI_InitStruct); 2396 .loc 2 883 3 is_stmt 1 view .LVU834 ARM GAS /tmp/ccdsDELB.s page 177 883:Src/main.c **** LL_SPI_Init(SPI4, &SPI_InitStruct); 2397 .loc 2 883 26 is_stmt 0 view .LVU835 2398 00a2 0723 movs r3, #7 2399 00a4 1193 str r3, [sp, #68] 884:Src/main.c **** LL_SPI_SetStandard(SPI4, LL_SPI_PROTOCOL_MOTOROLA); 2400 .loc 2 884 3 is_stmt 1 view .LVU836 2401 00a6 0A4C ldr r4, .L114+8 2402 00a8 08A9 add r1, sp, #32 2403 00aa 2046 mov r0, r4 2404 00ac FFF7FEFF bl LL_SPI_Init 2405 .LVL204: 885:Src/main.c **** LL_SPI_DisableNSSPulseMgt(SPI4); 2406 .loc 2 885 3 view .LVU837 2407 .LBB368: 2408 .LBI368: 426:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 2409 .loc 4 426 22 view .LVU838 2410 .LBB369: 428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 2411 .loc 4 428 3 view .LVU839 2412 00b0 6368 ldr r3, [r4, #4] 2413 00b2 23F01003 bic r3, r3, #16 2414 00b6 6360 str r3, [r4, #4] 2415 .LVL205: 428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 2416 .loc 4 428 3 is_stmt 0 view .LVU840 2417 .LBE369: 2418 .LBE368: 886:Src/main.c **** /* USER CODE BEGIN SPI4_Init 2 */ 2419 .loc 2 886 3 is_stmt 1 view .LVU841 2420 .LBB370: 2421 .LBI370: 874:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 2422 .loc 4 874 22 view .LVU842 2423 .LBB371: 876:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 2424 .loc 4 876 3 view .LVU843 2425 00b8 6368 ldr r3, [r4, #4] 2426 00ba 23F00803 bic r3, r3, #8 2427 00be 6360 str r3, [r4, #4] 2428 .LVL206: 876:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 2429 .loc 4 876 3 is_stmt 0 view .LVU844 2430 .LBE371: 2431 .LBE370: 891:Src/main.c **** 2432 .loc 2 891 1 view .LVU845 2433 00c0 12B0 add sp, sp, #72 2434 .LCFI15: 2435 .cfi_def_cfa_offset 24 2436 @ sp needed 2437 00c2 BDE8F081 pop {r4, r5, r6, r7, r8, pc} 2438 .L115: 2439 00c6 00BF .align 2 2440 .L114: 2441 00c8 00380240 .word 1073887232 2442 00cc 00100240 .word 1073876992 ARM GAS /tmp/ccdsDELB.s page 178 2443 00d0 00340140 .word 1073820672 2444 .cfi_endproc 2445 .LFE1192: 2447 .section .text.MX_SPI2_Init,"ax",%progbits 2448 .align 1 2449 .syntax unified 2450 .thumb 2451 .thumb_func 2452 .fpu fpv5-d16 2454 MX_SPI2_Init: 2455 .LFB1191: 773:Src/main.c **** 2456 .loc 2 773 1 is_stmt 1 view -0 2457 .cfi_startproc 2458 @ args = 0, pretend = 0, frame = 72 2459 @ frame_needed = 0, uses_anonymous_args = 0 2460 0000 2DE9F041 push {r4, r5, r6, r7, r8, lr} 2461 .LCFI16: 2462 .cfi_def_cfa_offset 24 2463 .cfi_offset 4, -24 2464 .cfi_offset 5, -20 2465 .cfi_offset 6, -16 2466 .cfi_offset 7, -12 2467 .cfi_offset 8, -8 2468 .cfi_offset 14, -4 2469 0004 92B0 sub sp, sp, #72 2470 .LCFI17: 2471 .cfi_def_cfa_offset 96 779:Src/main.c **** 2472 .loc 2 779 3 view .LVU847 779:Src/main.c **** 2473 .loc 2 779 22 is_stmt 0 view .LVU848 2474 0006 2822 movs r2, #40 2475 0008 0021 movs r1, #0 2476 000a 08A8 add r0, sp, #32 2477 000c FFF7FEFF bl memset 2478 .LVL207: 781:Src/main.c **** 2479 .loc 2 781 3 is_stmt 1 view .LVU849 781:Src/main.c **** 2480 .loc 2 781 23 is_stmt 0 view .LVU850 2481 0010 0024 movs r4, #0 2482 0012 0294 str r4, [sp, #8] 2483 0014 0394 str r4, [sp, #12] 2484 0016 0494 str r4, [sp, #16] 2485 0018 0594 str r4, [sp, #20] 2486 001a 0694 str r4, [sp, #24] 2487 001c 0794 str r4, [sp, #28] 784:Src/main.c **** 2488 .loc 2 784 3 is_stmt 1 view .LVU851 2489 .LVL208: 2490 .LBB372: 2491 .LBI372: 1071:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { 2492 .loc 3 1071 22 view .LVU852 2493 .LBB373: 1073:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** SET_BIT(RCC->APB1ENR, Periphs); ARM GAS /tmp/ccdsDELB.s page 179 2494 .loc 3 1073 3 view .LVU853 1074:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Delay after an RCC peripheral clock enabling */ 2495 .loc 3 1074 3 view .LVU854 2496 001e 294B ldr r3, .L118 2497 0020 1A6C ldr r2, [r3, #64] 2498 0022 42F48042 orr r2, r2, #16384 2499 0026 1A64 str r2, [r3, #64] 1076:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; 2500 .loc 3 1076 3 view .LVU855 1076:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; 2501 .loc 3 1076 12 is_stmt 0 view .LVU856 2502 0028 1A6C ldr r2, [r3, #64] 2503 002a 02F48042 and r2, r2, #16384 1076:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; 2504 .loc 3 1076 10 view .LVU857 2505 002e 0192 str r2, [sp, #4] 1077:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } 2506 .loc 3 1077 3 is_stmt 1 view .LVU858 2507 0030 019A ldr r2, [sp, #4] 2508 .LVL209: 1077:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } 2509 .loc 3 1077 3 is_stmt 0 view .LVU859 2510 .LBE373: 2511 .LBE372: 786:Src/main.c **** /**SPI2 GPIO Configuration 2512 .loc 2 786 3 is_stmt 1 view .LVU860 2513 .LBB374: 2514 .LBI374: 309:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { 2515 .loc 3 309 22 view .LVU861 2516 .LBB375: 311:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** SET_BIT(RCC->AHB1ENR, Periphs); 2517 .loc 3 311 3 view .LVU862 312:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Delay after an RCC peripheral clock enabling */ 2518 .loc 3 312 3 view .LVU863 2519 0032 1A6B ldr r2, [r3, #48] 2520 0034 42F00202 orr r2, r2, #2 2521 0038 1A63 str r2, [r3, #48] 314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; 2522 .loc 3 314 3 view .LVU864 314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; 2523 .loc 3 314 12 is_stmt 0 view .LVU865 2524 003a 1B6B ldr r3, [r3, #48] 2525 003c 03F00203 and r3, r3, #2 314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; 2526 .loc 3 314 10 view .LVU866 2527 0040 0093 str r3, [sp] 315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } 2528 .loc 3 315 3 is_stmt 1 view .LVU867 2529 0042 009B ldr r3, [sp] 2530 .LVL210: 315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } 2531 .loc 3 315 3 is_stmt 0 view .LVU868 2532 .LBE375: 2533 .LBE374: 791:Src/main.c **** GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE; 2534 .loc 2 791 3 is_stmt 1 view .LVU869 ARM GAS /tmp/ccdsDELB.s page 180 791:Src/main.c **** GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE; 2535 .loc 2 791 23 is_stmt 0 view .LVU870 2536 0044 4FF40053 mov r3, #8192 2537 0048 0293 str r3, [sp, #8] 792:Src/main.c **** GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH; 2538 .loc 2 792 3 is_stmt 1 view .LVU871 792:Src/main.c **** GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH; 2539 .loc 2 792 24 is_stmt 0 view .LVU872 2540 004a 0225 movs r5, #2 2541 004c 0395 str r5, [sp, #12] 793:Src/main.c **** GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; 2542 .loc 2 793 3 is_stmt 1 view .LVU873 793:Src/main.c **** GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; 2543 .loc 2 793 25 is_stmt 0 view .LVU874 2544 004e 4FF00308 mov r8, #3 2545 0052 CDF81080 str r8, [sp, #16] 794:Src/main.c **** GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; 2546 .loc 2 794 3 is_stmt 1 view .LVU875 795:Src/main.c **** GPIO_InitStruct.Alternate = LL_GPIO_AF_5; 2547 .loc 2 795 3 view .LVU876 796:Src/main.c **** LL_GPIO_Init(GPIOB, &GPIO_InitStruct); 2548 .loc 2 796 3 view .LVU877 796:Src/main.c **** LL_GPIO_Init(GPIOB, &GPIO_InitStruct); 2549 .loc 2 796 29 is_stmt 0 view .LVU878 2550 0056 0527 movs r7, #5 2551 0058 0797 str r7, [sp, #28] 797:Src/main.c **** 2552 .loc 2 797 3 is_stmt 1 view .LVU879 2553 005a 1B4E ldr r6, .L118+4 2554 005c 02A9 add r1, sp, #8 2555 005e 3046 mov r0, r6 2556 0060 FFF7FEFF bl LL_GPIO_Init 2557 .LVL211: 799:Src/main.c **** GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE; 2558 .loc 2 799 3 view .LVU880 799:Src/main.c **** GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE; 2559 .loc 2 799 23 is_stmt 0 view .LVU881 2560 0064 4FF40043 mov r3, #32768 2561 0068 0293 str r3, [sp, #8] 800:Src/main.c **** GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH; 2562 .loc 2 800 3 is_stmt 1 view .LVU882 800:Src/main.c **** GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH; 2563 .loc 2 800 24 is_stmt 0 view .LVU883 2564 006a 0395 str r5, [sp, #12] 801:Src/main.c **** GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; 2565 .loc 2 801 3 is_stmt 1 view .LVU884 801:Src/main.c **** GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; 2566 .loc 2 801 25 is_stmt 0 view .LVU885 2567 006c CDF81080 str r8, [sp, #16] 802:Src/main.c **** GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; 2568 .loc 2 802 3 is_stmt 1 view .LVU886 802:Src/main.c **** GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; 2569 .loc 2 802 30 is_stmt 0 view .LVU887 2570 0070 0594 str r4, [sp, #20] 803:Src/main.c **** GPIO_InitStruct.Alternate = LL_GPIO_AF_5; 2571 .loc 2 803 3 is_stmt 1 view .LVU888 803:Src/main.c **** GPIO_InitStruct.Alternate = LL_GPIO_AF_5; ARM GAS /tmp/ccdsDELB.s page 181 2572 .loc 2 803 24 is_stmt 0 view .LVU889 2573 0072 0694 str r4, [sp, #24] 804:Src/main.c **** LL_GPIO_Init(GPIOB, &GPIO_InitStruct); 2574 .loc 2 804 3 is_stmt 1 view .LVU890 804:Src/main.c **** LL_GPIO_Init(GPIOB, &GPIO_InitStruct); 2575 .loc 2 804 29 is_stmt 0 view .LVU891 2576 0074 0797 str r7, [sp, #28] 805:Src/main.c **** 2577 .loc 2 805 3 is_stmt 1 view .LVU892 2578 0076 02A9 add r1, sp, #8 2579 0078 3046 mov r0, r6 2580 007a FFF7FEFF bl LL_GPIO_Init 2581 .LVL212: 811:Src/main.c **** SPI_InitStruct.Mode = LL_SPI_MODE_MASTER; 2582 .loc 2 811 3 view .LVU893 811:Src/main.c **** SPI_InitStruct.Mode = LL_SPI_MODE_MASTER; 2583 .loc 2 811 36 is_stmt 0 view .LVU894 2584 007e 0894 str r4, [sp, #32] 812:Src/main.c **** SPI_InitStruct.DataWidth = LL_SPI_DATAWIDTH_16BIT; 2585 .loc 2 812 3 is_stmt 1 view .LVU895 812:Src/main.c **** SPI_InitStruct.DataWidth = LL_SPI_DATAWIDTH_16BIT; 2586 .loc 2 812 23 is_stmt 0 view .LVU896 2587 0080 4FF48273 mov r3, #260 2588 0084 0993 str r3, [sp, #36] 813:Src/main.c **** SPI_InitStruct.ClockPolarity = LL_SPI_POLARITY_HIGH; 2589 .loc 2 813 3 is_stmt 1 view .LVU897 813:Src/main.c **** SPI_InitStruct.ClockPolarity = LL_SPI_POLARITY_HIGH; 2590 .loc 2 813 28 is_stmt 0 view .LVU898 2591 0086 4FF47063 mov r3, #3840 2592 008a 0A93 str r3, [sp, #40] 814:Src/main.c **** SPI_InitStruct.ClockPhase = LL_SPI_PHASE_2EDGE; 2593 .loc 2 814 3 is_stmt 1 view .LVU899 814:Src/main.c **** SPI_InitStruct.ClockPhase = LL_SPI_PHASE_2EDGE; 2594 .loc 2 814 32 is_stmt 0 view .LVU900 2595 008c 0B95 str r5, [sp, #44] 815:Src/main.c **** SPI_InitStruct.NSS = LL_SPI_NSS_SOFT; 2596 .loc 2 815 3 is_stmt 1 view .LVU901 815:Src/main.c **** SPI_InitStruct.NSS = LL_SPI_NSS_SOFT; 2597 .loc 2 815 29 is_stmt 0 view .LVU902 2598 008e 0123 movs r3, #1 2599 0090 0C93 str r3, [sp, #48] 816:Src/main.c **** SPI_InitStruct.BaudRate = LL_SPI_BAUDRATEPRESCALER_DIV8; 2600 .loc 2 816 3 is_stmt 1 view .LVU903 816:Src/main.c **** SPI_InitStruct.BaudRate = LL_SPI_BAUDRATEPRESCALER_DIV8; 2601 .loc 2 816 22 is_stmt 0 view .LVU904 2602 0092 4FF40073 mov r3, #512 2603 0096 0D93 str r3, [sp, #52] 817:Src/main.c **** SPI_InitStruct.BitOrder = LL_SPI_MSB_FIRST; 2604 .loc 2 817 3 is_stmt 1 view .LVU905 817:Src/main.c **** SPI_InitStruct.BitOrder = LL_SPI_MSB_FIRST; 2605 .loc 2 817 27 is_stmt 0 view .LVU906 2606 0098 1023 movs r3, #16 2607 009a 0E93 str r3, [sp, #56] 818:Src/main.c **** SPI_InitStruct.CRCCalculation = LL_SPI_CRCCALCULATION_DISABLE; 2608 .loc 2 818 3 is_stmt 1 view .LVU907 818:Src/main.c **** SPI_InitStruct.CRCCalculation = LL_SPI_CRCCALCULATION_DISABLE; 2609 .loc 2 818 27 is_stmt 0 view .LVU908 ARM GAS /tmp/ccdsDELB.s page 182 2610 009c 0F94 str r4, [sp, #60] 819:Src/main.c **** SPI_InitStruct.CRCPoly = 7; 2611 .loc 2 819 3 is_stmt 1 view .LVU909 819:Src/main.c **** SPI_InitStruct.CRCPoly = 7; 2612 .loc 2 819 33 is_stmt 0 view .LVU910 2613 009e 1094 str r4, [sp, #64] 820:Src/main.c **** LL_SPI_Init(SPI2, &SPI_InitStruct); 2614 .loc 2 820 3 is_stmt 1 view .LVU911 820:Src/main.c **** LL_SPI_Init(SPI2, &SPI_InitStruct); 2615 .loc 2 820 26 is_stmt 0 view .LVU912 2616 00a0 0723 movs r3, #7 2617 00a2 1193 str r3, [sp, #68] 821:Src/main.c **** LL_SPI_SetStandard(SPI2, LL_SPI_PROTOCOL_MOTOROLA); 2618 .loc 2 821 3 is_stmt 1 view .LVU913 2619 00a4 094C ldr r4, .L118+8 2620 00a6 08A9 add r1, sp, #32 2621 00a8 2046 mov r0, r4 2622 00aa FFF7FEFF bl LL_SPI_Init 2623 .LVL213: 822:Src/main.c **** LL_SPI_DisableNSSPulseMgt(SPI2); 2624 .loc 2 822 3 view .LVU914 2625 .LBB376: 2626 .LBI376: 426:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 2627 .loc 4 426 22 view .LVU915 2628 .LBB377: 428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 2629 .loc 4 428 3 view .LVU916 2630 00ae 6368 ldr r3, [r4, #4] 2631 00b0 23F01003 bic r3, r3, #16 2632 00b4 6360 str r3, [r4, #4] 2633 .LVL214: 428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 2634 .loc 4 428 3 is_stmt 0 view .LVU917 2635 .LBE377: 2636 .LBE376: 823:Src/main.c **** /* USER CODE BEGIN SPI2_Init 2 */ 2637 .loc 2 823 3 is_stmt 1 view .LVU918 2638 .LBB378: 2639 .LBI378: 874:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 2640 .loc 4 874 22 view .LVU919 2641 .LBB379: 876:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 2642 .loc 4 876 3 view .LVU920 2643 00b6 6368 ldr r3, [r4, #4] 2644 00b8 23F00803 bic r3, r3, #8 2645 00bc 6360 str r3, [r4, #4] 2646 .LVL215: 876:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 2647 .loc 4 876 3 is_stmt 0 view .LVU921 2648 .LBE379: 2649 .LBE378: 828:Src/main.c **** 2650 .loc 2 828 1 view .LVU922 2651 00be 12B0 add sp, sp, #72 2652 .LCFI18: ARM GAS /tmp/ccdsDELB.s page 183 2653 .cfi_def_cfa_offset 24 2654 @ sp needed 2655 00c0 BDE8F081 pop {r4, r5, r6, r7, r8, pc} 2656 .L119: 2657 .align 2 2658 .L118: 2659 00c4 00380240 .word 1073887232 2660 00c8 00040240 .word 1073873920 2661 00cc 00380040 .word 1073756160 2662 .cfi_endproc 2663 .LFE1191: 2665 .section .text.MX_SPI5_Init,"ax",%progbits 2666 .align 1 2667 .syntax unified 2668 .thumb 2669 .thumb_func 2670 .fpu fpv5-d16 2672 MX_SPI5_Init: 2673 .LFB1193: 899:Src/main.c **** 2674 .loc 2 899 1 is_stmt 1 view -0 2675 .cfi_startproc 2676 @ args = 0, pretend = 0, frame = 72 2677 @ frame_needed = 0, uses_anonymous_args = 0 2678 0000 2DE9F041 push {r4, r5, r6, r7, r8, lr} 2679 .LCFI19: 2680 .cfi_def_cfa_offset 24 2681 .cfi_offset 4, -24 2682 .cfi_offset 5, -20 2683 .cfi_offset 6, -16 2684 .cfi_offset 7, -12 2685 .cfi_offset 8, -8 2686 .cfi_offset 14, -4 2687 0004 92B0 sub sp, sp, #72 2688 .LCFI20: 2689 .cfi_def_cfa_offset 96 905:Src/main.c **** 2690 .loc 2 905 3 view .LVU924 905:Src/main.c **** 2691 .loc 2 905 22 is_stmt 0 view .LVU925 2692 0006 2822 movs r2, #40 2693 0008 0021 movs r1, #0 2694 000a 08A8 add r0, sp, #32 2695 000c FFF7FEFF bl memset 2696 .LVL216: 907:Src/main.c **** 2697 .loc 2 907 3 is_stmt 1 view .LVU926 907:Src/main.c **** 2698 .loc 2 907 23 is_stmt 0 view .LVU927 2699 0010 0024 movs r4, #0 2700 0012 0294 str r4, [sp, #8] 2701 0014 0394 str r4, [sp, #12] 2702 0016 0494 str r4, [sp, #16] 2703 0018 0594 str r4, [sp, #20] 2704 001a 0694 str r4, [sp, #24] 2705 001c 0794 str r4, [sp, #28] 910:Src/main.c **** ARM GAS /tmp/ccdsDELB.s page 184 2706 .loc 2 910 3 is_stmt 1 view .LVU928 2707 .LVL217: 2708 .LBB380: 2709 .LBI380: 1587:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { 2710 .loc 3 1587 22 view .LVU929 2711 .LBB381: 1589:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** SET_BIT(RCC->APB2ENR, Periphs); 2712 .loc 3 1589 3 view .LVU930 1590:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Delay after an RCC peripheral clock enabling */ 2713 .loc 3 1590 3 view .LVU931 2714 001e 294B ldr r3, .L122 2715 0020 5A6C ldr r2, [r3, #68] 2716 0022 42F48012 orr r2, r2, #1048576 2717 0026 5A64 str r2, [r3, #68] 1592:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; 2718 .loc 3 1592 3 view .LVU932 1592:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; 2719 .loc 3 1592 12 is_stmt 0 view .LVU933 2720 0028 5A6C ldr r2, [r3, #68] 2721 002a 02F48012 and r2, r2, #1048576 1592:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; 2722 .loc 3 1592 10 view .LVU934 2723 002e 0192 str r2, [sp, #4] 2724 .loc 3 1593 3 is_stmt 1 view .LVU935 2725 0030 019A ldr r2, [sp, #4] 2726 .LVL218: 2727 .loc 3 1593 3 is_stmt 0 view .LVU936 2728 .LBE381: 2729 .LBE380: 912:Src/main.c **** /**SPI5 GPIO Configuration 2730 .loc 2 912 3 is_stmt 1 view .LVU937 2731 .LBB382: 2732 .LBI382: 309:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { 2733 .loc 3 309 22 view .LVU938 2734 .LBB383: 311:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** SET_BIT(RCC->AHB1ENR, Periphs); 2735 .loc 3 311 3 view .LVU939 312:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Delay after an RCC peripheral clock enabling */ 2736 .loc 3 312 3 view .LVU940 2737 0032 1A6B ldr r2, [r3, #48] 2738 0034 42F02002 orr r2, r2, #32 2739 0038 1A63 str r2, [r3, #48] 314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; 2740 .loc 3 314 3 view .LVU941 314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; 2741 .loc 3 314 12 is_stmt 0 view .LVU942 2742 003a 1B6B ldr r3, [r3, #48] 2743 003c 03F02003 and r3, r3, #32 314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; 2744 .loc 3 314 10 view .LVU943 2745 0040 0093 str r3, [sp] 315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } 2746 .loc 3 315 3 is_stmt 1 view .LVU944 2747 0042 009B ldr r3, [sp] 2748 .LVL219: ARM GAS /tmp/ccdsDELB.s page 185 315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } 2749 .loc 3 315 3 is_stmt 0 view .LVU945 2750 .LBE383: 2751 .LBE382: 917:Src/main.c **** GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE; 2752 .loc 2 917 3 is_stmt 1 view .LVU946 917:Src/main.c **** GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE; 2753 .loc 2 917 23 is_stmt 0 view .LVU947 2754 0044 8023 movs r3, #128 2755 0046 0293 str r3, [sp, #8] 918:Src/main.c **** GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH; 2756 .loc 2 918 3 is_stmt 1 view .LVU948 918:Src/main.c **** GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH; 2757 .loc 2 918 24 is_stmt 0 view .LVU949 2758 0048 0225 movs r5, #2 2759 004a 0395 str r5, [sp, #12] 919:Src/main.c **** GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; 2760 .loc 2 919 3 is_stmt 1 view .LVU950 919:Src/main.c **** GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; 2761 .loc 2 919 25 is_stmt 0 view .LVU951 2762 004c 4FF00308 mov r8, #3 2763 0050 CDF81080 str r8, [sp, #16] 920:Src/main.c **** GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; 2764 .loc 2 920 3 is_stmt 1 view .LVU952 921:Src/main.c **** GPIO_InitStruct.Alternate = LL_GPIO_AF_5; 2765 .loc 2 921 3 view .LVU953 922:Src/main.c **** LL_GPIO_Init(GPIOF, &GPIO_InitStruct); 2766 .loc 2 922 3 view .LVU954 922:Src/main.c **** LL_GPIO_Init(GPIOF, &GPIO_InitStruct); 2767 .loc 2 922 29 is_stmt 0 view .LVU955 2768 0054 0527 movs r7, #5 2769 0056 0797 str r7, [sp, #28] 923:Src/main.c **** 2770 .loc 2 923 3 is_stmt 1 view .LVU956 2771 0058 1B4E ldr r6, .L122+4 2772 005a 02A9 add r1, sp, #8 2773 005c 3046 mov r0, r6 2774 005e FFF7FEFF bl LL_GPIO_Init 2775 .LVL220: 925:Src/main.c **** GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE; 2776 .loc 2 925 3 view .LVU957 925:Src/main.c **** GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE; 2777 .loc 2 925 23 is_stmt 0 view .LVU958 2778 0062 4FF48073 mov r3, #256 2779 0066 0293 str r3, [sp, #8] 926:Src/main.c **** GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH; 2780 .loc 2 926 3 is_stmt 1 view .LVU959 926:Src/main.c **** GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH; 2781 .loc 2 926 24 is_stmt 0 view .LVU960 2782 0068 0395 str r5, [sp, #12] 927:Src/main.c **** GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; 2783 .loc 2 927 3 is_stmt 1 view .LVU961 927:Src/main.c **** GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; 2784 .loc 2 927 25 is_stmt 0 view .LVU962 2785 006a CDF81080 str r8, [sp, #16] 928:Src/main.c **** GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; 2786 .loc 2 928 3 is_stmt 1 view .LVU963 ARM GAS /tmp/ccdsDELB.s page 186 928:Src/main.c **** GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; 2787 .loc 2 928 30 is_stmt 0 view .LVU964 2788 006e 0594 str r4, [sp, #20] 929:Src/main.c **** GPIO_InitStruct.Alternate = LL_GPIO_AF_5; 2789 .loc 2 929 3 is_stmt 1 view .LVU965 929:Src/main.c **** GPIO_InitStruct.Alternate = LL_GPIO_AF_5; 2790 .loc 2 929 24 is_stmt 0 view .LVU966 2791 0070 0694 str r4, [sp, #24] 930:Src/main.c **** LL_GPIO_Init(GPIOF, &GPIO_InitStruct); 2792 .loc 2 930 3 is_stmt 1 view .LVU967 930:Src/main.c **** LL_GPIO_Init(GPIOF, &GPIO_InitStruct); 2793 .loc 2 930 29 is_stmt 0 view .LVU968 2794 0072 0797 str r7, [sp, #28] 931:Src/main.c **** 2795 .loc 2 931 3 is_stmt 1 view .LVU969 2796 0074 02A9 add r1, sp, #8 2797 0076 3046 mov r0, r6 2798 0078 FFF7FEFF bl LL_GPIO_Init 2799 .LVL221: 937:Src/main.c **** SPI_InitStruct.Mode = LL_SPI_MODE_MASTER; 2800 .loc 2 937 3 view .LVU970 937:Src/main.c **** SPI_InitStruct.Mode = LL_SPI_MODE_MASTER; 2801 .loc 2 937 36 is_stmt 0 view .LVU971 2802 007c 4FF48063 mov r3, #1024 2803 0080 0893 str r3, [sp, #32] 938:Src/main.c **** SPI_InitStruct.DataWidth = LL_SPI_DATAWIDTH_16BIT; 2804 .loc 2 938 3 is_stmt 1 view .LVU972 938:Src/main.c **** SPI_InitStruct.DataWidth = LL_SPI_DATAWIDTH_16BIT; 2805 .loc 2 938 23 is_stmt 0 view .LVU973 2806 0082 4FF48273 mov r3, #260 2807 0086 0993 str r3, [sp, #36] 939:Src/main.c **** SPI_InitStruct.ClockPolarity = LL_SPI_POLARITY_HIGH; 2808 .loc 2 939 3 is_stmt 1 view .LVU974 939:Src/main.c **** SPI_InitStruct.ClockPolarity = LL_SPI_POLARITY_HIGH; 2809 .loc 2 939 28 is_stmt 0 view .LVU975 2810 0088 4FF47063 mov r3, #3840 2811 008c 0A93 str r3, [sp, #40] 940:Src/main.c **** SPI_InitStruct.ClockPhase = LL_SPI_PHASE_1EDGE; 2812 .loc 2 940 3 is_stmt 1 view .LVU976 940:Src/main.c **** SPI_InitStruct.ClockPhase = LL_SPI_PHASE_1EDGE; 2813 .loc 2 940 32 is_stmt 0 view .LVU977 2814 008e 0B95 str r5, [sp, #44] 941:Src/main.c **** SPI_InitStruct.NSS = LL_SPI_NSS_SOFT; 2815 .loc 2 941 3 is_stmt 1 view .LVU978 941:Src/main.c **** SPI_InitStruct.NSS = LL_SPI_NSS_SOFT; 2816 .loc 2 941 29 is_stmt 0 view .LVU979 2817 0090 0C94 str r4, [sp, #48] 942:Src/main.c **** SPI_InitStruct.BaudRate = LL_SPI_BAUDRATEPRESCALER_DIV16; 2818 .loc 2 942 3 is_stmt 1 view .LVU980 942:Src/main.c **** SPI_InitStruct.BaudRate = LL_SPI_BAUDRATEPRESCALER_DIV16; 2819 .loc 2 942 22 is_stmt 0 view .LVU981 2820 0092 4FF40073 mov r3, #512 2821 0096 0D93 str r3, [sp, #52] 943:Src/main.c **** SPI_InitStruct.BitOrder = LL_SPI_MSB_FIRST; 2822 .loc 2 943 3 is_stmt 1 view .LVU982 943:Src/main.c **** SPI_InitStruct.BitOrder = LL_SPI_MSB_FIRST; 2823 .loc 2 943 27 is_stmt 0 view .LVU983 ARM GAS /tmp/ccdsDELB.s page 187 2824 0098 1823 movs r3, #24 2825 009a 0E93 str r3, [sp, #56] 944:Src/main.c **** SPI_InitStruct.CRCCalculation = LL_SPI_CRCCALCULATION_DISABLE; 2826 .loc 2 944 3 is_stmt 1 view .LVU984 944:Src/main.c **** SPI_InitStruct.CRCCalculation = LL_SPI_CRCCALCULATION_DISABLE; 2827 .loc 2 944 27 is_stmt 0 view .LVU985 2828 009c 0F94 str r4, [sp, #60] 945:Src/main.c **** SPI_InitStruct.CRCPoly = 7; 2829 .loc 2 945 3 is_stmt 1 view .LVU986 945:Src/main.c **** SPI_InitStruct.CRCPoly = 7; 2830 .loc 2 945 33 is_stmt 0 view .LVU987 2831 009e 1094 str r4, [sp, #64] 946:Src/main.c **** LL_SPI_Init(SPI5, &SPI_InitStruct); 2832 .loc 2 946 3 is_stmt 1 view .LVU988 946:Src/main.c **** LL_SPI_Init(SPI5, &SPI_InitStruct); 2833 .loc 2 946 26 is_stmt 0 view .LVU989 2834 00a0 0723 movs r3, #7 2835 00a2 1193 str r3, [sp, #68] 947:Src/main.c **** LL_SPI_SetStandard(SPI5, LL_SPI_PROTOCOL_MOTOROLA); 2836 .loc 2 947 3 is_stmt 1 view .LVU990 2837 00a4 094C ldr r4, .L122+8 2838 00a6 08A9 add r1, sp, #32 2839 00a8 2046 mov r0, r4 2840 00aa FFF7FEFF bl LL_SPI_Init 2841 .LVL222: 948:Src/main.c **** LL_SPI_DisableNSSPulseMgt(SPI5); 2842 .loc 2 948 3 view .LVU991 2843 .LBB384: 2844 .LBI384: 426:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 2845 .loc 4 426 22 view .LVU992 2846 .LBB385: 428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 2847 .loc 4 428 3 view .LVU993 2848 00ae 6368 ldr r3, [r4, #4] 2849 00b0 23F01003 bic r3, r3, #16 2850 00b4 6360 str r3, [r4, #4] 2851 .LVL223: 428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 2852 .loc 4 428 3 is_stmt 0 view .LVU994 2853 .LBE385: 2854 .LBE384: 949:Src/main.c **** /* USER CODE BEGIN SPI5_Init 2 */ 2855 .loc 2 949 3 is_stmt 1 view .LVU995 2856 .LBB386: 2857 .LBI386: 874:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 2858 .loc 4 874 22 view .LVU996 2859 .LBB387: 876:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 2860 .loc 4 876 3 view .LVU997 2861 00b6 6368 ldr r3, [r4, #4] 2862 00b8 23F00803 bic r3, r3, #8 2863 00bc 6360 str r3, [r4, #4] 2864 .LVL224: 876:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 2865 .loc 4 876 3 is_stmt 0 view .LVU998 ARM GAS /tmp/ccdsDELB.s page 188 2866 .LBE387: 2867 .LBE386: 954:Src/main.c **** 2868 .loc 2 954 1 view .LVU999 2869 00be 12B0 add sp, sp, #72 2870 .LCFI21: 2871 .cfi_def_cfa_offset 24 2872 @ sp needed 2873 00c0 BDE8F081 pop {r4, r5, r6, r7, r8, pc} 2874 .L123: 2875 .align 2 2876 .L122: 2877 00c4 00380240 .word 1073887232 2878 00c8 00140240 .word 1073878016 2879 00cc 00500140 .word 1073827840 2880 .cfi_endproc 2881 .LFE1193: 2883 .section .text.MX_SPI6_Init,"ax",%progbits 2884 .align 1 2885 .syntax unified 2886 .thumb 2887 .thumb_func 2888 .fpu fpv5-d16 2890 MX_SPI6_Init: 2891 .LFB1194: 962:Src/main.c **** 2892 .loc 2 962 1 is_stmt 1 view -0 2893 .cfi_startproc 2894 @ args = 0, pretend = 0, frame = 72 2895 @ frame_needed = 0, uses_anonymous_args = 0 2896 0000 2DE9F041 push {r4, r5, r6, r7, r8, lr} 2897 .LCFI22: 2898 .cfi_def_cfa_offset 24 2899 .cfi_offset 4, -24 2900 .cfi_offset 5, -20 2901 .cfi_offset 6, -16 2902 .cfi_offset 7, -12 2903 .cfi_offset 8, -8 2904 .cfi_offset 14, -4 2905 0004 92B0 sub sp, sp, #72 2906 .LCFI23: 2907 .cfi_def_cfa_offset 96 968:Src/main.c **** 2908 .loc 2 968 3 view .LVU1001 968:Src/main.c **** 2909 .loc 2 968 22 is_stmt 0 view .LVU1002 2910 0006 2822 movs r2, #40 2911 0008 0021 movs r1, #0 2912 000a 08A8 add r0, sp, #32 2913 000c FFF7FEFF bl memset 2914 .LVL225: 970:Src/main.c **** 2915 .loc 2 970 3 is_stmt 1 view .LVU1003 970:Src/main.c **** 2916 .loc 2 970 23 is_stmt 0 view .LVU1004 2917 0010 0024 movs r4, #0 2918 0012 0294 str r4, [sp, #8] ARM GAS /tmp/ccdsDELB.s page 189 2919 0014 0394 str r4, [sp, #12] 2920 0016 0494 str r4, [sp, #16] 2921 0018 0594 str r4, [sp, #20] 2922 001a 0694 str r4, [sp, #24] 2923 001c 0794 str r4, [sp, #28] 973:Src/main.c **** 2924 .loc 2 973 3 is_stmt 1 view .LVU1005 2925 .LVL226: 2926 .LBB388: 2927 .LBI388: 1587:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { 2928 .loc 3 1587 22 view .LVU1006 2929 .LBB389: 1589:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** SET_BIT(RCC->APB2ENR, Periphs); 2930 .loc 3 1589 3 view .LVU1007 1590:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Delay after an RCC peripheral clock enabling */ 2931 .loc 3 1590 3 view .LVU1008 2932 001e 294B ldr r3, .L126 2933 0020 5A6C ldr r2, [r3, #68] 2934 0022 42F40012 orr r2, r2, #2097152 2935 0026 5A64 str r2, [r3, #68] 1592:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; 2936 .loc 3 1592 3 view .LVU1009 1592:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; 2937 .loc 3 1592 12 is_stmt 0 view .LVU1010 2938 0028 5A6C ldr r2, [r3, #68] 2939 002a 02F40012 and r2, r2, #2097152 1592:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; 2940 .loc 3 1592 10 view .LVU1011 2941 002e 0192 str r2, [sp, #4] 2942 .loc 3 1593 3 is_stmt 1 view .LVU1012 2943 0030 019A ldr r2, [sp, #4] 2944 .LVL227: 2945 .loc 3 1593 3 is_stmt 0 view .LVU1013 2946 .LBE389: 2947 .LBE388: 975:Src/main.c **** /**SPI6 GPIO Configuration 2948 .loc 2 975 3 is_stmt 1 view .LVU1014 2949 .LBB390: 2950 .LBI390: 309:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { 2951 .loc 3 309 22 view .LVU1015 2952 .LBB391: 311:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** SET_BIT(RCC->AHB1ENR, Periphs); 2953 .loc 3 311 3 view .LVU1016 312:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Delay after an RCC peripheral clock enabling */ 2954 .loc 3 312 3 view .LVU1017 2955 0032 1A6B ldr r2, [r3, #48] 2956 0034 42F00102 orr r2, r2, #1 2957 0038 1A63 str r2, [r3, #48] 314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; 2958 .loc 3 314 3 view .LVU1018 314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; 2959 .loc 3 314 12 is_stmt 0 view .LVU1019 2960 003a 1B6B ldr r3, [r3, #48] 2961 003c 03F00103 and r3, r3, #1 314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; ARM GAS /tmp/ccdsDELB.s page 190 2962 .loc 3 314 10 view .LVU1020 2963 0040 0093 str r3, [sp] 315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } 2964 .loc 3 315 3 is_stmt 1 view .LVU1021 2965 0042 009B ldr r3, [sp] 2966 .LVL228: 315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } 2967 .loc 3 315 3 is_stmt 0 view .LVU1022 2968 .LBE391: 2969 .LBE390: 980:Src/main.c **** GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE; 2970 .loc 2 980 3 is_stmt 1 view .LVU1023 980:Src/main.c **** GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE; 2971 .loc 2 980 23 is_stmt 0 view .LVU1024 2972 0044 2023 movs r3, #32 2973 0046 0293 str r3, [sp, #8] 981:Src/main.c **** GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH; 2974 .loc 2 981 3 is_stmt 1 view .LVU1025 981:Src/main.c **** GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH; 2975 .loc 2 981 24 is_stmt 0 view .LVU1026 2976 0048 0225 movs r5, #2 2977 004a 0395 str r5, [sp, #12] 982:Src/main.c **** GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; 2978 .loc 2 982 3 is_stmt 1 view .LVU1027 982:Src/main.c **** GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; 2979 .loc 2 982 25 is_stmt 0 view .LVU1028 2980 004c 4FF00308 mov r8, #3 2981 0050 CDF81080 str r8, [sp, #16] 983:Src/main.c **** GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; 2982 .loc 2 983 3 is_stmt 1 view .LVU1029 984:Src/main.c **** GPIO_InitStruct.Alternate = LL_GPIO_AF_8; 2983 .loc 2 984 3 view .LVU1030 985:Src/main.c **** LL_GPIO_Init(GPIOA, &GPIO_InitStruct); 2984 .loc 2 985 3 view .LVU1031 985:Src/main.c **** LL_GPIO_Init(GPIOA, &GPIO_InitStruct); 2985 .loc 2 985 29 is_stmt 0 view .LVU1032 2986 0054 0827 movs r7, #8 2987 0056 0797 str r7, [sp, #28] 986:Src/main.c **** 2988 .loc 2 986 3 is_stmt 1 view .LVU1033 2989 0058 1B4E ldr r6, .L126+4 2990 005a 0DEB0701 add r1, sp, r7 2991 005e 3046 mov r0, r6 2992 0060 FFF7FEFF bl LL_GPIO_Init 2993 .LVL229: 988:Src/main.c **** GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE; 2994 .loc 2 988 3 view .LVU1034 988:Src/main.c **** GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE; 2995 .loc 2 988 23 is_stmt 0 view .LVU1035 2996 0064 8023 movs r3, #128 2997 0066 0293 str r3, [sp, #8] 989:Src/main.c **** GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH; 2998 .loc 2 989 3 is_stmt 1 view .LVU1036 989:Src/main.c **** GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH; 2999 .loc 2 989 24 is_stmt 0 view .LVU1037 3000 0068 0395 str r5, [sp, #12] 990:Src/main.c **** GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; ARM GAS /tmp/ccdsDELB.s page 191 3001 .loc 2 990 3 is_stmt 1 view .LVU1038 990:Src/main.c **** GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; 3002 .loc 2 990 25 is_stmt 0 view .LVU1039 3003 006a CDF81080 str r8, [sp, #16] 991:Src/main.c **** GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; 3004 .loc 2 991 3 is_stmt 1 view .LVU1040 991:Src/main.c **** GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; 3005 .loc 2 991 30 is_stmt 0 view .LVU1041 3006 006e 0594 str r4, [sp, #20] 992:Src/main.c **** GPIO_InitStruct.Alternate = LL_GPIO_AF_8; 3007 .loc 2 992 3 is_stmt 1 view .LVU1042 992:Src/main.c **** GPIO_InitStruct.Alternate = LL_GPIO_AF_8; 3008 .loc 2 992 24 is_stmt 0 view .LVU1043 3009 0070 0694 str r4, [sp, #24] 993:Src/main.c **** LL_GPIO_Init(GPIOA, &GPIO_InitStruct); 3010 .loc 2 993 3 is_stmt 1 view .LVU1044 993:Src/main.c **** LL_GPIO_Init(GPIOA, &GPIO_InitStruct); 3011 .loc 2 993 29 is_stmt 0 view .LVU1045 3012 0072 0797 str r7, [sp, #28] 994:Src/main.c **** 3013 .loc 2 994 3 is_stmt 1 view .LVU1046 3014 0074 0DEB0701 add r1, sp, r7 3015 0078 3046 mov r0, r6 3016 007a FFF7FEFF bl LL_GPIO_Init 3017 .LVL230: 1000:Src/main.c **** SPI_InitStruct.Mode = LL_SPI_MODE_MASTER; 3018 .loc 2 1000 3 view .LVU1047 1000:Src/main.c **** SPI_InitStruct.Mode = LL_SPI_MODE_MASTER; 3019 .loc 2 1000 36 is_stmt 0 view .LVU1048 3020 007e 0894 str r4, [sp, #32] 1001:Src/main.c **** SPI_InitStruct.DataWidth = LL_SPI_DATAWIDTH_16BIT; 3021 .loc 2 1001 3 is_stmt 1 view .LVU1049 1001:Src/main.c **** SPI_InitStruct.DataWidth = LL_SPI_DATAWIDTH_16BIT; 3022 .loc 2 1001 23 is_stmt 0 view .LVU1050 3023 0080 4FF48273 mov r3, #260 3024 0084 0993 str r3, [sp, #36] 1002:Src/main.c **** SPI_InitStruct.ClockPolarity = LL_SPI_POLARITY_HIGH; 3025 .loc 2 1002 3 is_stmt 1 view .LVU1051 1002:Src/main.c **** SPI_InitStruct.ClockPolarity = LL_SPI_POLARITY_HIGH; 3026 .loc 2 1002 28 is_stmt 0 view .LVU1052 3027 0086 4FF47063 mov r3, #3840 3028 008a 0A93 str r3, [sp, #40] 1003:Src/main.c **** SPI_InitStruct.ClockPhase = LL_SPI_PHASE_2EDGE; 3029 .loc 2 1003 3 is_stmt 1 view .LVU1053 1003:Src/main.c **** SPI_InitStruct.ClockPhase = LL_SPI_PHASE_2EDGE; 3030 .loc 2 1003 32 is_stmt 0 view .LVU1054 3031 008c 0B95 str r5, [sp, #44] 1004:Src/main.c **** SPI_InitStruct.NSS = LL_SPI_NSS_SOFT; 3032 .loc 2 1004 3 is_stmt 1 view .LVU1055 1004:Src/main.c **** SPI_InitStruct.NSS = LL_SPI_NSS_SOFT; 3033 .loc 2 1004 29 is_stmt 0 view .LVU1056 3034 008e 0123 movs r3, #1 3035 0090 0C93 str r3, [sp, #48] 1005:Src/main.c **** SPI_InitStruct.BaudRate = LL_SPI_BAUDRATEPRESCALER_DIV16; 3036 .loc 2 1005 3 is_stmt 1 view .LVU1057 1005:Src/main.c **** SPI_InitStruct.BaudRate = LL_SPI_BAUDRATEPRESCALER_DIV16; 3037 .loc 2 1005 22 is_stmt 0 view .LVU1058 ARM GAS /tmp/ccdsDELB.s page 192 3038 0092 4FF40073 mov r3, #512 3039 0096 0D93 str r3, [sp, #52] 1006:Src/main.c **** SPI_InitStruct.BitOrder = LL_SPI_MSB_FIRST; 3040 .loc 2 1006 3 is_stmt 1 view .LVU1059 1006:Src/main.c **** SPI_InitStruct.BitOrder = LL_SPI_MSB_FIRST; 3041 .loc 2 1006 27 is_stmt 0 view .LVU1060 3042 0098 1823 movs r3, #24 3043 009a 0E93 str r3, [sp, #56] 1007:Src/main.c **** SPI_InitStruct.CRCCalculation = LL_SPI_CRCCALCULATION_DISABLE; 3044 .loc 2 1007 3 is_stmt 1 view .LVU1061 1007:Src/main.c **** SPI_InitStruct.CRCCalculation = LL_SPI_CRCCALCULATION_DISABLE; 3045 .loc 2 1007 27 is_stmt 0 view .LVU1062 3046 009c 0F94 str r4, [sp, #60] 1008:Src/main.c **** SPI_InitStruct.CRCPoly = 7; 3047 .loc 2 1008 3 is_stmt 1 view .LVU1063 1008:Src/main.c **** SPI_InitStruct.CRCPoly = 7; 3048 .loc 2 1008 33 is_stmt 0 view .LVU1064 3049 009e 1094 str r4, [sp, #64] 1009:Src/main.c **** LL_SPI_Init(SPI6, &SPI_InitStruct); 3050 .loc 2 1009 3 is_stmt 1 view .LVU1065 1009:Src/main.c **** LL_SPI_Init(SPI6, &SPI_InitStruct); 3051 .loc 2 1009 26 is_stmt 0 view .LVU1066 3052 00a0 0723 movs r3, #7 3053 00a2 1193 str r3, [sp, #68] 1010:Src/main.c **** LL_SPI_SetStandard(SPI6, LL_SPI_PROTOCOL_MOTOROLA); 3054 .loc 2 1010 3 is_stmt 1 view .LVU1067 3055 00a4 094C ldr r4, .L126+8 3056 00a6 08A9 add r1, sp, #32 3057 00a8 2046 mov r0, r4 3058 00aa FFF7FEFF bl LL_SPI_Init 3059 .LVL231: 1011:Src/main.c **** LL_SPI_DisableNSSPulseMgt(SPI6); 3060 .loc 2 1011 3 view .LVU1068 3061 .LBB392: 3062 .LBI392: 426:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 3063 .loc 4 426 22 view .LVU1069 3064 .LBB393: 428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 3065 .loc 4 428 3 view .LVU1070 3066 00ae 6368 ldr r3, [r4, #4] 3067 00b0 23F01003 bic r3, r3, #16 3068 00b4 6360 str r3, [r4, #4] 3069 .LVL232: 428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 3070 .loc 4 428 3 is_stmt 0 view .LVU1071 3071 .LBE393: 3072 .LBE392: 1012:Src/main.c **** /* USER CODE BEGIN SPI6_Init 2 */ 3073 .loc 2 1012 3 is_stmt 1 view .LVU1072 3074 .LBB394: 3075 .LBI394: 874:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 3076 .loc 4 874 22 view .LVU1073 3077 .LBB395: 876:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 3078 .loc 4 876 3 view .LVU1074 ARM GAS /tmp/ccdsDELB.s page 193 3079 00b6 6368 ldr r3, [r4, #4] 3080 00b8 23F00803 bic r3, r3, #8 3081 00bc 6360 str r3, [r4, #4] 3082 .LVL233: 876:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 3083 .loc 4 876 3 is_stmt 0 view .LVU1075 3084 .LBE395: 3085 .LBE394: 1017:Src/main.c **** 3086 .loc 2 1017 1 view .LVU1076 3087 00be 12B0 add sp, sp, #72 3088 .LCFI24: 3089 .cfi_def_cfa_offset 24 3090 @ sp needed 3091 00c0 BDE8F081 pop {r4, r5, r6, r7, r8, pc} 3092 .L127: 3093 .align 2 3094 .L126: 3095 00c4 00380240 .word 1073887232 3096 00c8 00000240 .word 1073872896 3097 00cc 00540140 .word 1073828864 3098 .cfi_endproc 3099 .LFE1194: 3101 .section .text.MX_TIM2_Init,"ax",%progbits 3102 .align 1 3103 .syntax unified 3104 .thumb 3105 .thumb_func 3106 .fpu fpv5-d16 3108 MX_TIM2_Init: 3109 .LFB1195: 1025:Src/main.c **** 3110 .loc 2 1025 1 is_stmt 1 view -0 3111 .cfi_startproc 3112 @ args = 0, pretend = 0, frame = 24 3113 @ frame_needed = 0, uses_anonymous_args = 0 3114 0000 10B5 push {r4, lr} 3115 .LCFI25: 3116 .cfi_def_cfa_offset 8 3117 .cfi_offset 4, -8 3118 .cfi_offset 14, -4 3119 0002 86B0 sub sp, sp, #24 3120 .LCFI26: 3121 .cfi_def_cfa_offset 32 1031:Src/main.c **** 3122 .loc 2 1031 3 view .LVU1078 1031:Src/main.c **** 3123 .loc 2 1031 22 is_stmt 0 view .LVU1079 3124 0004 0024 movs r4, #0 3125 0006 0194 str r4, [sp, #4] 3126 0008 0294 str r4, [sp, #8] 3127 000a 0394 str r4, [sp, #12] 3128 000c 0494 str r4, [sp, #16] 3129 000e 0594 str r4, [sp, #20] 1034:Src/main.c **** 3130 .loc 2 1034 3 is_stmt 1 view .LVU1080 3131 .LVL234: ARM GAS /tmp/ccdsDELB.s page 194 3132 .LBB396: 3133 .LBI396: 1071:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { 3134 .loc 3 1071 22 view .LVU1081 3135 .LBB397: 1073:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** SET_BIT(RCC->APB1ENR, Periphs); 3136 .loc 3 1073 3 view .LVU1082 1074:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Delay after an RCC peripheral clock enabling */ 3137 .loc 3 1074 3 view .LVU1083 3138 0010 1D4B ldr r3, .L130 3139 0012 1A6C ldr r2, [r3, #64] 3140 0014 42F00102 orr r2, r2, #1 3141 0018 1A64 str r2, [r3, #64] 1076:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; 3142 .loc 3 1076 3 view .LVU1084 1076:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; 3143 .loc 3 1076 12 is_stmt 0 view .LVU1085 3144 001a 1B6C ldr r3, [r3, #64] 3145 001c 03F00103 and r3, r3, #1 1076:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; 3146 .loc 3 1076 10 view .LVU1086 3147 0020 0093 str r3, [sp] 1077:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } 3148 .loc 3 1077 3 is_stmt 1 view .LVU1087 3149 0022 009B ldr r3, [sp] 3150 .LVL235: 1077:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } 3151 .loc 3 1077 3 is_stmt 0 view .LVU1088 3152 .LBE397: 3153 .LBE396: 1037:Src/main.c **** NVIC_EnableIRQ(TIM2_IRQn); 3154 .loc 2 1037 3 is_stmt 1 view .LVU1089 3155 .LBB398: 3156 .LBI398: 1884:Drivers/CMSIS/Include/core_cm7.h **** { 3157 .loc 1 1884 26 view .LVU1090 3158 .LBB399: 1886:Drivers/CMSIS/Include/core_cm7.h **** } 3159 .loc 1 1886 3 view .LVU1091 1886:Drivers/CMSIS/Include/core_cm7.h **** } 3160 .loc 1 1886 26 is_stmt 0 view .LVU1092 3161 0024 194B ldr r3, .L130+4 3162 0026 D868 ldr r0, [r3, #12] 3163 .LBE399: 3164 .LBE398: 1037:Src/main.c **** NVIC_EnableIRQ(TIM2_IRQn); 3165 .loc 2 1037 3 view .LVU1093 3166 0028 2246 mov r2, r4 3167 002a 2146 mov r1, r4 3168 002c C0F30220 ubfx r0, r0, #8, #3 3169 0030 FFF7FEFF bl NVIC_EncodePriority 3170 .LVL236: 3171 .LBB400: 3172 .LBI400: 2024:Drivers/CMSIS/Include/core_cm7.h **** { 3173 .loc 1 2024 22 is_stmt 1 view .LVU1094 3174 .LBB401: ARM GAS /tmp/ccdsDELB.s page 195 2026:Drivers/CMSIS/Include/core_cm7.h **** { 3175 .loc 1 2026 3 view .LVU1095 2028:Drivers/CMSIS/Include/core_cm7.h **** } 3176 .loc 1 2028 5 view .LVU1096 2028:Drivers/CMSIS/Include/core_cm7.h **** } 3177 .loc 1 2028 49 is_stmt 0 view .LVU1097 3178 0034 0001 lsls r0, r0, #4 3179 .LVL237: 2028:Drivers/CMSIS/Include/core_cm7.h **** } 3180 .loc 1 2028 49 view .LVU1098 3181 0036 C0B2 uxtb r0, r0 2028:Drivers/CMSIS/Include/core_cm7.h **** } 3182 .loc 1 2028 47 view .LVU1099 3183 0038 154B ldr r3, .L130+8 3184 003a 83F81C03 strb r0, [r3, #796] 3185 .LVL238: 2028:Drivers/CMSIS/Include/core_cm7.h **** } 3186 .loc 1 2028 47 view .LVU1100 3187 .LBE401: 3188 .LBE400: 1038:Src/main.c **** 3189 .loc 2 1038 3 is_stmt 1 view .LVU1101 3190 .LBB402: 3191 .LBI402: 1896:Drivers/CMSIS/Include/core_cm7.h **** { 3192 .loc 1 1896 22 view .LVU1102 3193 .LBB403: 1898:Drivers/CMSIS/Include/core_cm7.h **** { 3194 .loc 1 1898 3 view .LVU1103 1900:Drivers/CMSIS/Include/core_cm7.h **** } 3195 .loc 1 1900 5 view .LVU1104 1900:Drivers/CMSIS/Include/core_cm7.h **** } 3196 .loc 1 1900 43 is_stmt 0 view .LVU1105 3197 003e 4FF08052 mov r2, #268435456 3198 0042 1A60 str r2, [r3] 3199 .LVL239: 1900:Drivers/CMSIS/Include/core_cm7.h **** } 3200 .loc 1 1900 43 view .LVU1106 3201 .LBE403: 3202 .LBE402: 1043:Src/main.c **** TIM_InitStruct.CounterMode = LL_TIM_COUNTERMODE_UP; 3203 .loc 2 1043 3 is_stmt 1 view .LVU1107 1043:Src/main.c **** TIM_InitStruct.CounterMode = LL_TIM_COUNTERMODE_UP; 3204 .loc 2 1043 28 is_stmt 0 view .LVU1108 3205 0044 4FF47A73 mov r3, #1000 3206 0048 ADF80430 strh r3, [sp, #4] @ movhi 1044:Src/main.c **** TIM_InitStruct.Autoreload = 840000; 3207 .loc 2 1044 3 is_stmt 1 view .LVU1109 1044:Src/main.c **** TIM_InitStruct.Autoreload = 840000; 3208 .loc 2 1044 30 is_stmt 0 view .LVU1110 3209 004c 0294 str r4, [sp, #8] 1045:Src/main.c **** TIM_InitStruct.ClockDivision = LL_TIM_CLOCKDIVISION_DIV1; 3210 .loc 2 1045 3 is_stmt 1 view .LVU1111 1045:Src/main.c **** TIM_InitStruct.ClockDivision = LL_TIM_CLOCKDIVISION_DIV1; 3211 .loc 2 1045 29 is_stmt 0 view .LVU1112 3212 004e 114B ldr r3, .L130+12 3213 0050 0393 str r3, [sp, #12] ARM GAS /tmp/ccdsDELB.s page 196 1046:Src/main.c **** LL_TIM_Init(TIM2, &TIM_InitStruct); 3214 .loc 2 1046 3 is_stmt 1 view .LVU1113 1046:Src/main.c **** LL_TIM_Init(TIM2, &TIM_InitStruct); 3215 .loc 2 1046 32 is_stmt 0 view .LVU1114 3216 0052 0494 str r4, [sp, #16] 1047:Src/main.c **** LL_TIM_DisableARRPreload(TIM2); 3217 .loc 2 1047 3 is_stmt 1 view .LVU1115 3218 0054 01A9 add r1, sp, #4 3219 0056 4FF08040 mov r0, #1073741824 3220 005a FFF7FEFF bl LL_TIM_Init 3221 .LVL240: 1048:Src/main.c **** LL_TIM_SetClockSource(TIM2, LL_TIM_CLOCKSOURCE_INTERNAL); 3222 .loc 2 1048 3 view .LVU1116 3223 .LBB404: 3224 .LBI404: 3225 .file 5 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h" 1:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 2:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** ****************************************************************************** 3:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @file stm32f7xx_ll_tim.h 4:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @author MCD Application Team 5:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Header file of TIM LL module. 6:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** ****************************************************************************** 7:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @attention 8:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * 9:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * Copyright (c) 2017 STMicroelectronics. 10:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * All rights reserved. 11:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * 12:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * This software is licensed under terms that can be found in the LICENSE file 13:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * in the root directory of this software component. 14:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * If no LICENSE file comes with this software, it is provided AS-IS. 15:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * 16:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** ****************************************************************************** 17:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 18:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 19:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /* Define to prevent recursive inclusion -------------------------------------*/ 20:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #ifndef __STM32F7xx_LL_TIM_H 21:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define __STM32F7xx_LL_TIM_H 22:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 23:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #ifdef __cplusplus 24:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** extern "C" { 25:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #endif 26:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 27:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /* Includes ------------------------------------------------------------------*/ 28:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #include "stm32f7xx.h" 29:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 30:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @addtogroup STM32F7xx_LL_Driver 31:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ 32:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 33:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 34:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #if defined (TIM1) || defined (TIM8) || defined (TIM2) || defined (TIM3) || defined (TIM4) || defi 35:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 36:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL TIM 37:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ 38:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 39:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 40:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /* Private types -------------------------------------------------------------*/ 41:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /* Private variables ---------------------------------------------------------*/ ARM GAS /tmp/ccdsDELB.s page 197 42:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_Private_Variables TIM Private Variables 43:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ 44:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 45:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** static const uint8_t OFFSET_TAB_CCMRx[] = 46:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 47:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 0x00U, /* 0: TIMx_CH1 */ 48:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 0x00U, /* 1: TIMx_CH1N */ 49:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 0x00U, /* 2: TIMx_CH2 */ 50:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 0x00U, /* 3: TIMx_CH2N */ 51:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 0x04U, /* 4: TIMx_CH3 */ 52:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 0x04U, /* 5: TIMx_CH3N */ 53:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 0x04U, /* 6: TIMx_CH4 */ 54:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 0x3CU, /* 7: TIMx_CH5 */ 55:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 0x3CU /* 8: TIMx_CH6 */ 56:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }; 57:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 58:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** static const uint8_t SHIFT_TAB_OCxx[] = 59:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 60:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 0U, /* 0: OC1M, OC1FE, OC1PE */ 61:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 0U, /* 1: - NA */ 62:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 8U, /* 2: OC2M, OC2FE, OC2PE */ 63:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 0U, /* 3: - NA */ 64:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 0U, /* 4: OC3M, OC3FE, OC3PE */ 65:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 0U, /* 5: - NA */ 66:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 8U, /* 6: OC4M, OC4FE, OC4PE */ 67:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 0U, /* 7: OC5M, OC5FE, OC5PE */ 68:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 8U /* 8: OC6M, OC6FE, OC6PE */ 69:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }; 70:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 71:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** static const uint8_t SHIFT_TAB_ICxx[] = 72:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 73:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 0U, /* 0: CC1S, IC1PSC, IC1F */ 74:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 0U, /* 1: - NA */ 75:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 8U, /* 2: CC2S, IC2PSC, IC2F */ 76:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 0U, /* 3: - NA */ 77:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 0U, /* 4: CC3S, IC3PSC, IC3F */ 78:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 0U, /* 5: - NA */ 79:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 8U, /* 6: CC4S, IC4PSC, IC4F */ 80:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 0U, /* 7: - NA */ 81:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 0U /* 8: - NA */ 82:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }; 83:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 84:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** static const uint8_t SHIFT_TAB_CCxP[] = 85:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 86:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 0U, /* 0: CC1P */ 87:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 2U, /* 1: CC1NP */ 88:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 4U, /* 2: CC2P */ 89:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 6U, /* 3: CC2NP */ 90:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 8U, /* 4: CC3P */ 91:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 10U, /* 5: CC3NP */ 92:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 12U, /* 6: CC4P */ 93:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 16U, /* 7: CC5P */ 94:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 20U /* 8: CC6P */ 95:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }; 96:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 97:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** static const uint8_t SHIFT_TAB_OISx[] = 98:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { ARM GAS /tmp/ccdsDELB.s page 198 99:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 0U, /* 0: OIS1 */ 100:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1U, /* 1: OIS1N */ 101:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 2U, /* 2: OIS2 */ 102:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3U, /* 3: OIS2N */ 103:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 4U, /* 4: OIS3 */ 104:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 5U, /* 5: OIS3N */ 105:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 6U, /* 6: OIS4 */ 106:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 8U, /* 7: OIS5 */ 107:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 10U /* 8: OIS6 */ 108:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }; 109:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 110:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} 111:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 112:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 113:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /* Private constants ---------------------------------------------------------*/ 114:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_Private_Constants TIM Private Constants 115:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ 116:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 117:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 118:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #if defined(TIM_BREAK_INPUT_SUPPORT) 119:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /* Defines used for the bit position in the register and perform offsets */ 120:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define TIM_POSITION_BRK_SOURCE (POSITION_VAL(Source) & 0x1FUL) 121:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 122:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /* Generic bit definitions for TIMx_AF1 register */ 123:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define TIMx_AF1_BKINP TIM1_AF1_BKINP /*!< BRK BKIN input polarity */ 124:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #endif /* TIM_BREAK_INPUT_SUPPORT */ 125:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 126:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /* Remap mask definitions */ 127:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define TIMx_OR_RMP_SHIFT 16U 128:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define TIMx_OR_RMP_MASK 0x0000FFFFU 129:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define TIM2_OR_RMP_MASK (TIM2_OR_ITR1_RMP << TIMx_OR_RMP_SHIFT) 130:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define TIM5_OR_RMP_MASK (TIM5_OR_TI4_RMP << TIMx_OR_RMP_SHIFT) 131:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define TIM11_OR_RMP_MASK (TIM11_OR_TI1_RMP << TIMx_OR_RMP_SHIFT) 132:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 133:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /* Mask used to set the TDG[x:0] of the DTG bits of the TIMx_BDTR register */ 134:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define DT_DELAY_1 ((uint8_t)0x7F) 135:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define DT_DELAY_2 ((uint8_t)0x3F) 136:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define DT_DELAY_3 ((uint8_t)0x1F) 137:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define DT_DELAY_4 ((uint8_t)0x1F) 138:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 139:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /* Mask used to set the DTG[7:5] bits of the DTG bits of the TIMx_BDTR register */ 140:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define DT_RANGE_1 ((uint8_t)0x00) 141:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define DT_RANGE_2 ((uint8_t)0x80) 142:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define DT_RANGE_3 ((uint8_t)0xC0) 143:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define DT_RANGE_4 ((uint8_t)0xE0) 144:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 145:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 146:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 147:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} 148:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 149:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 150:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /* Private macros ------------------------------------------------------------*/ 151:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_Private_Macros TIM Private Macros 152:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ 153:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 154:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @brief Convert channel id into channel index. 155:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param __CHANNEL__ This parameter can be one of the following values: ARM GAS /tmp/ccdsDELB.s page 199 156:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 157:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1N 158:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 159:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2N 160:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 161:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3N 162:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 163:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH5 164:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH6 165:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval none 166:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 167:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define TIM_GET_CHANNEL_INDEX( __CHANNEL__) \ 168:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** (((__CHANNEL__) == LL_TIM_CHANNEL_CH1) ? 0U :\ 169:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** ((__CHANNEL__) == LL_TIM_CHANNEL_CH1N) ? 1U :\ 170:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** ((__CHANNEL__) == LL_TIM_CHANNEL_CH2) ? 2U :\ 171:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** ((__CHANNEL__) == LL_TIM_CHANNEL_CH2N) ? 3U :\ 172:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** ((__CHANNEL__) == LL_TIM_CHANNEL_CH3) ? 4U :\ 173:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** ((__CHANNEL__) == LL_TIM_CHANNEL_CH3N) ? 5U :\ 174:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** ((__CHANNEL__) == LL_TIM_CHANNEL_CH4) ? 6U :\ 175:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** ((__CHANNEL__) == LL_TIM_CHANNEL_CH5) ? 7U : 8U) 176:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 177:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @brief Calculate the deadtime sampling period(in ps). 178:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param __TIMCLK__ timer input clock frequency (in Hz). 179:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param __CKD__ This parameter can be one of the following values: 180:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CLOCKDIVISION_DIV1 181:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CLOCKDIVISION_DIV2 182:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CLOCKDIVISION_DIV4 183:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval none 184:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 185:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define TIM_CALC_DTS(__TIMCLK__, __CKD__) \ 186:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** (((__CKD__) == LL_TIM_CLOCKDIVISION_DIV1) ? ((uint64_t)1000000000000U/(__TIMCLK__)) : \ 187:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** ((__CKD__) == LL_TIM_CLOCKDIVISION_DIV2) ? ((uint64_t)1000000000000U/((__TIMCLK__) >> 1U)) : \ 188:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** ((uint64_t)1000000000000U/((__TIMCLK__) >> 2U))) 189:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 190:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} 191:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 192:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 193:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 194:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /* Exported types ------------------------------------------------------------*/ 195:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #if defined(USE_FULL_LL_DRIVER) 196:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_ES_INIT TIM Exported Init structure 197:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ 198:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 199:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 200:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 201:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief TIM Time Base configuration structure definition. 202:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 203:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** typedef struct 204:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 205:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint16_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock. 206:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a number between Min_Data=0x0000 and Max_D 207:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 208:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary function 209:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_SetPrescaler().*/ 210:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 211:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t CounterMode; /*!< Specifies the counter mode. 212:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_COUNTERMODE. ARM GAS /tmp/ccdsDELB.s page 200 213:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 214:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary function 215:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_SetCounterMode().*/ 216:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 217:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t Autoreload; /*!< Specifies the auto reload value to be loaded into the active 218:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** Auto-Reload Register at the next update event. 219:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter must be a number between Min_Data=0x0000 and Max_ 220:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** Some timer instances may support 32 bits counters. In that case 221:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** be a number between 0x0000 and 0xFFFFFFFF. 222:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 223:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary function 224:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_SetAutoReload().*/ 225:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 226:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t ClockDivision; /*!< Specifies the clock division. 227:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_CLOCKDIVISION. 228:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 229:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary function 230:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_SetClockDivision().*/ 231:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 232:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downc 233:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** reaches zero, an update event is generated and counting restarts 234:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** from the RCR value (N). 235:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This means in PWM mode that (N+1) corresponds to: 236:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** - the number of PWM periods in edge-aligned mode 237:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** - the number of half PWM period in center-aligned mode 238:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** GP timers: this parameter must be a number between Min_Data = 0x 239:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** Max_Data = 0xFF. 240:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** Advanced timers: this parameter must be a number between Min_Dat 241:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** Max_Data = 0xFFFF. 242:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 243:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary function 244:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_SetRepetitionCounter().*/ 245:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } LL_TIM_InitTypeDef; 246:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 247:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 248:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief TIM Output Compare configuration structure definition. 249:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 250:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** typedef struct 251:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 252:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t OCMode; /*!< Specifies the output mode. 253:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_OCMODE. 254:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 255:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary function 256:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_OC_SetMode().*/ 257:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 258:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t OCState; /*!< Specifies the TIM Output Compare state. 259:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_OCSTATE. 260:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 261:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary functions 262:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/ 263:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 264:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t OCNState; /*!< Specifies the TIM complementary Output Compare state. 265:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_OCSTATE. 266:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 267:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary functions 268:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/ 269:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** ARM GAS /tmp/ccdsDELB.s page 201 270:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t CompareValue; /*!< Specifies the Compare value to be loaded into the Capture Compare Re 271:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a number between Min_Data=0x0000 and Max_Data= 272:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 273:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary function 274:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** LL_TIM_OC_SetCompareCHx (x=1..6).*/ 275:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 276:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t OCPolarity; /*!< Specifies the output polarity. 277:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY. 278:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 279:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary function 280:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_OC_SetPolarity().*/ 281:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 282:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t OCNPolarity; /*!< Specifies the complementary output polarity. 283:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY. 284:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 285:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary function 286:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_OC_SetPolarity().*/ 287:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 288:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 289:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. 290:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE. 291:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 292:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary function 293:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_OC_SetIdleState().*/ 294:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 295:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. 296:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE. 297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 298:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary function 299:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_OC_SetIdleState().*/ 300:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } LL_TIM_OC_InitTypeDef; 301:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 302:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 303:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief TIM Input Capture configuration structure definition. 304:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 305:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 306:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** typedef struct 307:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 308:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 309:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t ICPolarity; /*!< Specifies the active edge of the input signal. 310:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY. 311:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 312:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary function 313:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_IC_SetPolarity().*/ 314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t ICActiveInput; /*!< Specifies the input. 316:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT. 317:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 318:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary function 319:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_IC_SetActiveInput().*/ 320:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 321:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler. 322:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_ICPSC. 323:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 324:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary function 325:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_IC_SetPrescaler().*/ 326:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** ARM GAS /tmp/ccdsDELB.s page 202 327:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t ICFilter; /*!< Specifies the input capture filter. 328:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_IC_FILTER. 329:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 330:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary function 331:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_IC_SetFilter().*/ 332:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } LL_TIM_IC_InitTypeDef; 333:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 334:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 335:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 336:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief TIM Encoder interface configuration structure definition. 337:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 338:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** typedef struct 339:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 340:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t EncoderMode; /*!< Specifies the encoder resolution (x2 or x4). 341:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_ENCODERMODE. 342:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 343:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary function 344:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_SetEncoderMode().*/ 345:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input. 347:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY. 348:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 349:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary function 350:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_IC_SetPolarity().*/ 351:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 352:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t IC1ActiveInput; /*!< Specifies the TI1 input source 353:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT. 354:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 355:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary function 356:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_IC_SetActiveInput().*/ 357:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 358:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value. 359:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_ICPSC. 360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 361:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary function 362:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_IC_SetPrescaler().*/ 363:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 364:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t IC1Filter; /*!< Specifies the TI1 input filter. 365:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_IC_FILTER. 366:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 367:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary function 368:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_IC_SetFilter().*/ 369:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t IC2Polarity; /*!< Specifies the active edge of TI2 input. 371:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY. 372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary function 374:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_IC_SetPolarity().*/ 375:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 376:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t IC2ActiveInput; /*!< Specifies the TI2 input source 377:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT. 378:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 379:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary function 380:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_IC_SetActiveInput().*/ 381:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 382:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t IC2Prescaler; /*!< Specifies the TI2 input prescaler value. 383:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_ICPSC. ARM GAS /tmp/ccdsDELB.s page 203 384:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 385:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary function 386:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_IC_SetPrescaler().*/ 387:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 388:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t IC2Filter; /*!< Specifies the TI2 input filter. 389:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_IC_FILTER. 390:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 391:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary function 392:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_IC_SetFilter().*/ 393:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 394:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } LL_TIM_ENCODER_InitTypeDef; 395:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 396:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 397:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief TIM Hall sensor interface configuration structure definition. 398:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 399:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** typedef struct 400:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 401:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 402:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input. 403:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY. 404:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 405:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary function 406:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_IC_SetPolarity().*/ 407:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 408:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value. 409:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** Prescaler must be set to get a maximum counter period longer th 410:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** time interval between 2 consecutive changes on the Hall inputs. 411:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_ICPSC. 412:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 413:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary function 414:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_IC_SetPrescaler().*/ 415:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 416:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t IC1Filter; /*!< Specifies the TI1 input filter. 417:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of 418:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref TIM_LL_EC_IC_FILTER. 419:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 420:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary function 421:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_IC_SetFilter().*/ 422:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 423:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t CommutationDelay; /*!< Specifies the compare value to be loaded into the Capture Compa 424:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** A positive pulse (TRGO event) is generated with a programmable 425:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** a change occurs on the Hall inputs. 426:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a number between Min_Data = 0x0000 and Ma 427:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary function 429:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_OC_SetCompareCH2().*/ 430:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } LL_TIM_HALLSENSOR_InitTypeDef; 431:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 432:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 433:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief BDTR (Break and Dead Time) structure definition 434:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 435:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** typedef struct 436:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 437:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t OSSRState; /*!< Specifies the Off-State selection used in Run mode. 438:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_OSSR 439:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 440:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary functio ARM GAS /tmp/ccdsDELB.s page 204 441:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_SetOffStates() 442:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 443:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @note This bit-field cannot be modified as long as LOCK level 444:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** programmed. */ 445:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 446:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t OSSIState; /*!< Specifies the Off-State used in Idle state. 447:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_OSSI 448:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 449:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary functio 450:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_SetOffStates() 451:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 452:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @note This bit-field cannot be modified as long as LOCK level 453:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** programmed. */ 454:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 455:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t LockLevel; /*!< Specifies the LOCK level parameters. 456:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_LOCKLEVEL 457:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 458:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @note The LOCK bits can be written only once after the reset. 459:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** register has been written, their content is frozen until the 460:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 461:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint8_t DeadTime; /*!< Specifies the delay time between the switching-off and the 462:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** switching-on of the outputs. 463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a number between Min_Data = 0x00 and Ma 464:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 465:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary functio 466:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_OC_SetDeadTime() 467:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 468:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @note This bit-field can not be modified as long as LOCK leve 469:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** programmed. */ 470:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 471:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint16_t BreakState; /*!< Specifies whether the TIM Break input is enabled or not. 472:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_BREAK_ENABLE 473:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 474:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary functio 475:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_EnableBRK() or @ref LL_TIM_DisableBRK() 476:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 477:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @note This bit-field can not be modified as long as LOCK leve 478:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** programmed. */ 479:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 480:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t BreakPolarity; /*!< Specifies the TIM Break Input pin polarity. 481:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_BREAK_POLARIT 482:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 483:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary functio 484:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_ConfigBRK() 485:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 486:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @note This bit-field can not be modified as long as LOCK leve 487:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** programmed. */ 488:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 489:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t BreakFilter; /*!< Specifies the TIM Break Filter. 490:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_BREAK_FILTER 491:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 492:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary functio 493:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_ConfigBRK() 494:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 495:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @note This bit-field can not be modified as long as LOCK leve 496:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** programmed. */ 497:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** ARM GAS /tmp/ccdsDELB.s page 205 498:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t Break2State; /*!< Specifies whether the TIM Break2 input is enabled or not. 499:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_BREAK2_ENABLE 500:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 501:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary functio 502:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_EnableBRK2() or @ref LL_TIM_DisableBRK2() 503:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 504:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @note This bit-field can not be modified as long as LOCK leve 505:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** programmed. */ 506:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 507:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t Break2Polarity; /*!< Specifies the TIM Break2 Input pin polarity. 508:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_BREAK2_POLARI 509:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 510:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary functio 511:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_ConfigBRK2() 512:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 513:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @note This bit-field can not be modified as long as LOCK leve 514:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** programmed. */ 515:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 516:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t Break2Filter; /*!< Specifies the TIM Break2 Filter. 517:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_BREAK2_FILTER 518:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 519:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary functio 520:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_ConfigBRK2() 521:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 522:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @note This bit-field can not be modified as long as LOCK leve 523:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** programmed. */ 524:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 525:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t AutomaticOutput; /*!< Specifies whether the TIM Automatic Output feature is enabled 526:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_AUTOMATICOUTP 527:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 528:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary functio 529:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_EnableAutomaticOutput() or @ref LL_TIM_DisableAut 530:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 531:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @note This bit-field can not be modified as long as LOCK leve 532:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** programmed. */ 533:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } LL_TIM_BDTR_InitTypeDef; 534:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 535:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 536:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} 537:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 538:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #endif /* USE_FULL_LL_DRIVER */ 539:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 540:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /* Exported constants --------------------------------------------------------*/ 541:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_Exported_Constants TIM Exported Constants 542:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ 543:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 544:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 545:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EC_GET_FLAG Get Flags Defines 546:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Flags defines which can be used with LL_TIM_ReadReg function. 547:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ 548:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 549:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_SR_UIF TIM_SR_UIF /*!< Update interrupt flag */ 550:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_SR_CC1IF TIM_SR_CC1IF /*!< Capture/compare 1 interrup 551:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_SR_CC2IF TIM_SR_CC2IF /*!< Capture/compare 2 interrup 552:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_SR_CC3IF TIM_SR_CC3IF /*!< Capture/compare 3 interrup 553:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_SR_CC4IF TIM_SR_CC4IF /*!< Capture/compare 4 interrup 554:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_SR_CC5IF TIM_SR_CC5IF /*!< Capture/compare 5 interrup ARM GAS /tmp/ccdsDELB.s page 206 555:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_SR_CC6IF TIM_SR_CC6IF /*!< Capture/compare 6 interrup 556:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_SR_COMIF TIM_SR_COMIF /*!< COM interrupt flag */ 557:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_SR_TIF TIM_SR_TIF /*!< Trigger interrupt flag */ 558:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_SR_BIF TIM_SR_BIF /*!< Break interrupt flag */ 559:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_SR_B2IF TIM_SR_B2IF /*!< Second break interrupt fla 560:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_SR_CC1OF TIM_SR_CC1OF /*!< Capture/Compare 1 overcapt 561:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_SR_CC2OF TIM_SR_CC2OF /*!< Capture/Compare 2 overcapt 562:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_SR_CC3OF TIM_SR_CC3OF /*!< Capture/Compare 3 overcapt 563:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_SR_CC4OF TIM_SR_CC4OF /*!< Capture/Compare 4 overcapt 564:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_SR_SBIF TIM_SR_SBIF /*!< System Break interrupt fla 565:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 566:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} 567:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 568:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 569:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #if defined(USE_FULL_LL_DRIVER) 570:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EC_BREAK_ENABLE Break Enable 571:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ 572:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 573:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_BREAK_DISABLE 0x00000000U /*!< Break function disabled */ 574:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_BREAK_ENABLE TIM_BDTR_BKE /*!< Break function enabled */ 575:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 576:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} 577:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 578:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 579:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EC_BREAK2_ENABLE Break2 Enable 580:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ 581:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 582:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_BREAK2_DISABLE 0x00000000U /*!< Break2 function disabled */ 583:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_BREAK2_ENABLE TIM_BDTR_BK2E /*!< Break2 function enabled */ 584:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 585:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} 586:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 587:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 588:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EC_AUTOMATICOUTPUT_ENABLE Automatic output enable 589:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ 590:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 591:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U /*!< MOE can be set only by 592:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /*!< MOE can be set by softw 593:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 594:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} 595:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 596:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #endif /* USE_FULL_LL_DRIVER */ 597:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 598:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EC_IT IT Defines 599:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief IT defines which can be used with LL_TIM_ReadReg and LL_TIM_WriteReg functions. 600:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ 601:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 602:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_DIER_UIE TIM_DIER_UIE /*!< Update interrupt enable */ 603:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_DIER_CC1IE TIM_DIER_CC1IE /*!< Capture/compare 1 interrup 604:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_DIER_CC2IE TIM_DIER_CC2IE /*!< Capture/compare 2 interrup 605:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_DIER_CC3IE TIM_DIER_CC3IE /*!< Capture/compare 3 interrup 606:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_DIER_CC4IE TIM_DIER_CC4IE /*!< Capture/compare 4 interrup 607:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_DIER_COMIE TIM_DIER_COMIE /*!< COM interrupt enable */ 608:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_DIER_TIE TIM_DIER_TIE /*!< Trigger interrupt enable * 609:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_DIER_BIE TIM_DIER_BIE /*!< Break interrupt enable */ 610:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 611:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} ARM GAS /tmp/ccdsDELB.s page 207 612:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 613:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 614:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EC_UPDATESOURCE Update Source 615:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ 616:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 617:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_UPDATESOURCE_REGULAR 0x00000000U /*!< Counter overflow/underflow 618:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_UPDATESOURCE_COUNTER TIM_CR1_URS /*!< Only counter overflow/unde 619:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 620:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} 621:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 622:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 623:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EC_ONEPULSEMODE One Pulse Mode 624:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ 625:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 626:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_ONEPULSEMODE_SINGLE TIM_CR1_OPM /*!< Counter stops counting at 627:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_ONEPULSEMODE_REPETITIVE 0x00000000U /*!< Counter is not stopped at 628:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 629:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} 630:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 631:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 632:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EC_COUNTERMODE Counter Mode 633:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ 634:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 635:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_COUNTERMODE_UP 0x00000000U /*!< Counter used as upcounter 636:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_COUNTERMODE_DOWN TIM_CR1_DIR /*!< Counter used as downcounte 637:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_COUNTERMODE_CENTER_DOWN TIM_CR1_CMS_0 /*!< The counter counts up and 638:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_COUNTERMODE_CENTER_UP TIM_CR1_CMS_1 /*!< The counter counts up and 639:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_COUNTERMODE_CENTER_UP_DOWN TIM_CR1_CMS /*!< The counter counts up and 640:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 641:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} 642:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 643:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 644:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EC_CLOCKDIVISION Clock Division 645:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ 646:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 647:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_CLOCKDIVISION_DIV1 0x00000000U /*!< tDTS=tCK_INT */ 648:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0 /*!< tDTS=2*tCK_INT */ 649:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1 /*!< tDTS=4*tCK_INT */ 650:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 651:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} 652:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 653:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 654:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EC_COUNTERDIRECTION Counter Direction 655:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ 656:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 657:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_COUNTERDIRECTION_UP 0x00000000U /*!< Timer counter counts up */ 658:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_COUNTERDIRECTION_DOWN TIM_CR1_DIR /*!< Timer counter counts down 659:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 660:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} 661:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 662:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 663:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EC_CCUPDATESOURCE Capture Compare Update Source 664:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ 665:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 666:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_CCUPDATESOURCE_COMG_ONLY 0x00000000U /*!< Capture/compare control bi 667:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI TIM_CR2_CCUS /*!< Capture/compare control bi 668:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** ARM GAS /tmp/ccdsDELB.s page 208 669:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} 670:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 671:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 672:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EC_CCDMAREQUEST Capture Compare DMA Request 673:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ 674:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 675:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_CCDMAREQUEST_CC 0x00000000U /*!< CCx DMA request sent when 676:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_CCDMAREQUEST_UPDATE TIM_CR2_CCDS /*!< CCx DMA requests sent when 677:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 678:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} 679:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 680:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 681:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EC_LOCKLEVEL Lock Level 682:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ 683:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 684:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_LOCKLEVEL_OFF 0x00000000U /*!< LOCK OFF - No bit is write 685:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0 /*!< LOCK Level 1 */ 686:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1 /*!< LOCK Level 2 */ 687:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_LOCKLEVEL_3 TIM_BDTR_LOCK /*!< LOCK Level 3 */ 688:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 689:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} 690:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 691:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 692:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EC_CHANNEL Channel 693:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ 694:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 695:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_CHANNEL_CH1 TIM_CCER_CC1E /*!< Timer input/output channel 1 696:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_CHANNEL_CH1N TIM_CCER_CC1NE /*!< Timer complementary output ch 697:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_CHANNEL_CH2 TIM_CCER_CC2E /*!< Timer input/output channel 2 698:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_CHANNEL_CH2N TIM_CCER_CC2NE /*!< Timer complementary output ch 699:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_CHANNEL_CH3 TIM_CCER_CC3E /*!< Timer input/output channel 3 700:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_CHANNEL_CH3N TIM_CCER_CC3NE /*!< Timer complementary output ch 701:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_CHANNEL_CH4 TIM_CCER_CC4E /*!< Timer input/output channel 4 702:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_CHANNEL_CH5 TIM_CCER_CC5E /*!< Timer output channel 5 */ 703:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_CHANNEL_CH6 TIM_CCER_CC6E /*!< Timer output channel 6 */ 704:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 705:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} 706:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 707:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 708:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #if defined(USE_FULL_LL_DRIVER) 709:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EC_OCSTATE Output Configuration State 710:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ 711:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 712:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_OCSTATE_DISABLE 0x00000000U /*!< OCx is not active */ 713:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_OCSTATE_ENABLE TIM_CCER_CC1E /*!< OCx signal is output on 714:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 715:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} 716:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 717:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #endif /* USE_FULL_LL_DRIVER */ 718:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 719:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** Legacy definitions for compatibility purpose 720:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @cond 0 721:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 722:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_OCMODE_ASSYMETRIC_PWM1 LL_TIM_OCMODE_ASYMMETRIC_PWM1 723:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_OCMODE_ASSYMETRIC_PWM2 LL_TIM_OCMODE_ASYMMETRIC_PWM2 724:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 725:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @endcond ARM GAS /tmp/ccdsDELB.s page 209 726:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 727:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 728:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EC_OCMODE Output Configuration Mode 729:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ 730:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 731:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_OCMODE_FROZEN 0x00000000U 732:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0 733:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1 734:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) 735:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_OCMODE_FORCED_INACTIVE TIM_CCMR1_OC1M_2 736:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0) 737:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1) 738:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1 739:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_OCMODE_RETRIG_OPM1 TIM_CCMR1_OC1M_3 740:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_OCMODE_RETRIG_OPM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0) 741:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_OCMODE_COMBINED_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2) 742:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_OCMODE_COMBINED_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1 743:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_OCMODE_ASYMMETRIC_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1 744:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_OCMODE_ASYMMETRIC_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M) 745:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 746:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} 747:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 748:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 749:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EC_OCPOLARITY Output Configuration Polarity 750:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ 751:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 752:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_OCPOLARITY_HIGH 0x00000000U /*!< OCxactive high*/ 753:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_OCPOLARITY_LOW TIM_CCER_CC1P /*!< OCxactive low*/ 754:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 755:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} 756:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 757:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 758:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EC_OCIDLESTATE Output Configuration Idle State 759:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ 760:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 761:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_OCIDLESTATE_LOW 0x00000000U /*!__REG__, (__VAL 1185:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1186:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 1187:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Read a value in TIM register. 1188:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param __INSTANCE__ TIM Instance 1189:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param __REG__ Register to be read 1190:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval Register value 1191:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1192:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__) 1193:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 1194:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} 1195:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1196:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1197:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 1198:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief HELPER macro retrieving the UIFCPY flag from the counter value. 1199:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note ex: @ref __LL_TIM_GETFLAG_UIFCPY (@ref LL_TIM_GetCounter ()); 1200:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Relevant only if UIF flag remapping has been enabled (UIF status bit is copied 1201:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * to TIMx_CNT register bit 31) 1202:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param __CNT__ Counter value 1203:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval UIF status bit 1204:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1205:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define __LL_TIM_GETFLAG_UIFCPY(__CNT__) \ 1206:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** (READ_BIT((__CNT__), TIM_CNT_UIFCPY) >> TIM_CNT_UIFCPY_Pos) 1207:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1208:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 1209:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief HELPER macro calculating DTG[0:7] in the TIMx_BDTR register to achieve the requested de 1210:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note ex: @ref __LL_TIM_CALC_DEADTIME (80000000, @ref LL_TIM_GetClockDivision (), 120); 1211:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param __TIMCLK__ timer input clock frequency (in Hz) 1212:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param __CKD__ This parameter can be one of the following values: 1213:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CLOCKDIVISION_DIV1 1214:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CLOCKDIVISION_DIV2 1215:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CLOCKDIVISION_DIV4 1216:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param __DT__ deadtime duration (in ns) 1217:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval DTG[0:7] 1218:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1219:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define __LL_TIM_CALC_DEADTIME(__TIMCLK__, __CKD__, __DT__) \ 1220:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** ( (((uint64_t)((__DT__)*1000U)) < ((DT_DELAY_1+1U) * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? 1221:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** (uint8_t)(((uint64_t)((__DT__)*1000U) / TIM_CALC_DTS((__TIMCLK__), (__CKD__))) & DT_DELAY_1) : 1222:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** (((uint64_t)((__DT__)*1000U)) < ((64U + (DT_DELAY_2+1U)) * 2U * TIM_CALC_DTS((__TIMCLK__), (__C 1223:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** (uint8_t)(DT_RANGE_2 | ((uint8_t)((uint8_t)((((uint64_t)((__DT__)*1000U))/ TIM_CALC_DTS((__TIMC 1224:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** (__CKD__))) >> 1U) - (uint8_t) 64) & DT_DELAY_2)) 1225:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_3+1U)) * 8U * TIM_CALC_DTS((__TIMCLK__), (__C 1226:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** (uint8_t)(DT_RANGE_3 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMC 1227:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** (__CKD__))) >> 3U) - (uint8_t) 32) & DT_DELAY_3)) 1228:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_4+1U)) * 16U * TIM_CALC_DTS((__TIMCLK__), (__ 1229:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** (uint8_t)(DT_RANGE_4 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMC 1230:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** (__CKD__))) >> 4U) - (uint8_t) 32) & DT_DELAY_4)) 1231:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 0U) 1232:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1233:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 1234:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief HELPER macro calculating the prescaler value to achieve the required counter clock freq 1235:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note ex: @ref __LL_TIM_CALC_PSC (80000000, 1000000); 1236:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param __TIMCLK__ timer input clock frequency (in Hz) 1237:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param __CNTCLK__ counter clock frequency (in Hz) 1238:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval Prescaler value (between Min_Data=0 and Max_Data=65535) ARM GAS /tmp/ccdsDELB.s page 218 1239:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1240:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define __LL_TIM_CALC_PSC(__TIMCLK__, __CNTCLK__) \ 1241:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** (((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)((((__TIMCLK__) + (__CNTCLK__)/2U)/(__CNTCLK__)) - 1U 1242:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1243:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 1244:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief HELPER macro calculating the auto-reload value to achieve the required output signal fr 1245:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note ex: @ref __LL_TIM_CALC_ARR (1000000, @ref LL_TIM_GetPrescaler (), 10000); 1246:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param __TIMCLK__ timer input clock frequency (in Hz) 1247:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param __PSC__ prescaler 1248:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param __FREQ__ output signal frequency (in Hz) 1249:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535) 1250:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1251:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define __LL_TIM_CALC_ARR(__TIMCLK__, __PSC__, __FREQ__) \ 1252:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** ((((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? (((__TIMCLK__)/((__FREQ__) * ((__PSC__) + 1U)) 1253:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1254:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 1255:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief HELPER macro calculating the compare value required to achieve the required timer outpu 1256:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * active/inactive delay. 1257:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note ex: @ref __LL_TIM_CALC_DELAY (1000000, @ref LL_TIM_GetPrescaler (), 10); 1258:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param __TIMCLK__ timer input clock frequency (in Hz) 1259:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param __PSC__ prescaler 1260:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param __DELAY__ timer output compare active/inactive delay (in us) 1261:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval Compare value (between Min_Data=0 and Max_Data=65535) 1262:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1263:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define __LL_TIM_CALC_DELAY(__TIMCLK__, __PSC__, __DELAY__) \ 1264:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** ((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__)) \ 1265:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** / ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U)))) 1266:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1267:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 1268:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief HELPER macro calculating the auto-reload value to achieve the required pulse duration 1269:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * (when the timer operates in one pulse mode). 1270:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note ex: @ref __LL_TIM_CALC_PULSE (1000000, @ref LL_TIM_GetPrescaler (), 10, 20); 1271:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param __TIMCLK__ timer input clock frequency (in Hz) 1272:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param __PSC__ prescaler 1273:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param __DELAY__ timer output compare active/inactive delay (in us) 1274:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param __PULSE__ pulse duration (in us) 1275:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535) 1276:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1277:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define __LL_TIM_CALC_PULSE(__TIMCLK__, __PSC__, __DELAY__, __PULSE__) \ 1278:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** ((uint32_t)(__LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__PULSE__)) \ 1279:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + __LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__DELAY__)))) 1280:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1281:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 1282:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief HELPER macro retrieving the ratio of the input capture prescaler 1283:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note ex: @ref __LL_TIM_GET_ICPSC_RATIO (@ref LL_TIM_IC_GetPrescaler ()); 1284:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param __ICPSC__ This parameter can be one of the following values: 1285:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ICPSC_DIV1 1286:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ICPSC_DIV2 1287:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ICPSC_DIV4 1288:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ICPSC_DIV8 1289:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval Input capture prescaler ratio (1, 2, 4 or 8) 1290:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1291:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define __LL_TIM_GET_ICPSC_RATIO(__ICPSC__) \ 1292:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** ((uint32_t)(0x01U << (((__ICPSC__) >> 16U) >> TIM_CCMR1_IC1PSC_Pos))) 1293:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1294:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1295:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** ARM GAS /tmp/ccdsDELB.s page 219 1296:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} 1297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1298:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1299:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /* Exported functions --------------------------------------------------------*/ 1300:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_Exported_Functions TIM Exported Functions 1301:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ 1302:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1303:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1304:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EF_Time_Base Time Base configuration 1305:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ 1306:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1307:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 1308:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Enable timer counter. 1309:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR1 CEN LL_TIM_EnableCounter 1310:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 1311:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 1312:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1313:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_EnableCounter(TIM_TypeDef *TIMx) 1314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 1315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** SET_BIT(TIMx->CR1, TIM_CR1_CEN); 1316:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 1317:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1318:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 1319:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Disable timer counter. 1320:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR1 CEN LL_TIM_DisableCounter 1321:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 1322:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 1323:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1324:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_DisableCounter(TIM_TypeDef *TIMx) 1325:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 1326:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** CLEAR_BIT(TIMx->CR1, TIM_CR1_CEN); 1327:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 1328:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1329:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 1330:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Indicates whether the timer counter is enabled. 1331:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR1 CEN LL_TIM_IsEnabledCounter 1332:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 1333:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval State of bit (1 or 0). 1334:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1335:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsEnabledCounter(const TIM_TypeDef *TIMx) 1336:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 1337:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return ((READ_BIT(TIMx->CR1, TIM_CR1_CEN) == (TIM_CR1_CEN)) ? 1UL : 0UL); 1338:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 1339:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1340:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 1341:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Enable update event generation. 1342:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR1 UDIS LL_TIM_EnableUpdateEvent 1343:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 1344:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 1345:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_EnableUpdateEvent(TIM_TypeDef *TIMx) 1347:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 1348:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** CLEAR_BIT(TIMx->CR1, TIM_CR1_UDIS); 1349:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 1350:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1351:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 1352:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Disable update event generation. ARM GAS /tmp/ccdsDELB.s page 220 1353:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR1 UDIS LL_TIM_DisableUpdateEvent 1354:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 1355:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 1356:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1357:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_DisableUpdateEvent(TIM_TypeDef *TIMx) 1358:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 1359:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** SET_BIT(TIMx->CR1, TIM_CR1_UDIS); 1360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 1361:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1362:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 1363:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Indicates whether update event generation is enabled. 1364:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR1 UDIS LL_TIM_IsEnabledUpdateEvent 1365:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 1366:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval Inverted state of bit (0 or 1). 1367:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1368:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsEnabledUpdateEvent(const TIM_TypeDef *TIMx) 1369:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 1370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return ((READ_BIT(TIMx->CR1, TIM_CR1_UDIS) == (uint32_t)RESET) ? 1UL : 0UL); 1371:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 1372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 1374:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Set update event source 1375:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Update event source set to LL_TIM_UPDATESOURCE_REGULAR: any of the following events 1376:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * generate an update interrupt or DMA request if enabled: 1377:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * - Counter overflow/underflow 1378:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * - Setting the UG bit 1379:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * - Update generation through the slave mode controller 1380:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Update event source set to LL_TIM_UPDATESOURCE_COUNTER: only counter 1381:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * overflow/underflow generates an update interrupt or DMA request if enabled. 1382:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR1 URS LL_TIM_SetUpdateSource 1383:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 1384:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param UpdateSource This parameter can be one of the following values: 1385:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_UPDATESOURCE_REGULAR 1386:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_UPDATESOURCE_COUNTER 1387:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 1388:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1389:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_SetUpdateSource(TIM_TypeDef *TIMx, uint32_t UpdateSource) 1390:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 1391:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(TIMx->CR1, TIM_CR1_URS, UpdateSource); 1392:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 1393:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1394:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 1395:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Get actual event update source 1396:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR1 URS LL_TIM_GetUpdateSource 1397:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 1398:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval Returned value can be one of the following values: 1399:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_UPDATESOURCE_REGULAR 1400:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_UPDATESOURCE_COUNTER 1401:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1402:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_GetUpdateSource(const TIM_TypeDef *TIMx) 1403:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 1404:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_URS)); 1405:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 1406:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1407:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 1408:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Set one pulse mode (one shot v.s. repetitive). 1409:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR1 OPM LL_TIM_SetOnePulseMode ARM GAS /tmp/ccdsDELB.s page 221 1410:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 1411:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param OnePulseMode This parameter can be one of the following values: 1412:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ONEPULSEMODE_SINGLE 1413:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE 1414:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 1415:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1416:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_SetOnePulseMode(TIM_TypeDef *TIMx, uint32_t OnePulseMode) 1417:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 1418:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(TIMx->CR1, TIM_CR1_OPM, OnePulseMode); 1419:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 1420:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1421:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 1422:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Get actual one pulse mode. 1423:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR1 OPM LL_TIM_GetOnePulseMode 1424:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 1425:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval Returned value can be one of the following values: 1426:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ONEPULSEMODE_SINGLE 1427:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE 1428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1429:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_GetOnePulseMode(const TIM_TypeDef *TIMx) 1430:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 1431:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_OPM)); 1432:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 1433:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1434:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 1435:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Set the timer counter counting mode. 1436:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to 1437:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * check whether or not the counter mode selection feature is supported 1438:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * by a timer instance. 1439:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) 1440:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * requires a timer reset to avoid unexpected direction 1441:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * due to DIR bit readonly in center aligned mode. 1442:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR1 DIR LL_TIM_SetCounterMode\n 1443:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CR1 CMS LL_TIM_SetCounterMode 1444:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 1445:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param CounterMode This parameter can be one of the following values: 1446:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_COUNTERMODE_UP 1447:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_COUNTERMODE_DOWN 1448:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP 1449:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN 1450:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN 1451:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 1452:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1453:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_SetCounterMode(TIM_TypeDef *TIMx, uint32_t CounterMode) 1454:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 1455:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(TIMx->CR1, (TIM_CR1_DIR | TIM_CR1_CMS), CounterMode); 1456:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 1457:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1458:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 1459:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Get actual counter mode. 1460:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to 1461:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * check whether or not the counter mode selection feature is supported 1462:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * by a timer instance. 1463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR1 DIR LL_TIM_GetCounterMode\n 1464:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CR1 CMS LL_TIM_GetCounterMode 1465:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 1466:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval Returned value can be one of the following values: ARM GAS /tmp/ccdsDELB.s page 222 1467:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_COUNTERMODE_UP 1468:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_COUNTERMODE_DOWN 1469:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP 1470:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN 1471:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN 1472:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1473:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_GetCounterMode(const TIM_TypeDef *TIMx) 1474:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 1475:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t counter_mode; 1476:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1477:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** counter_mode = (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CMS)); 1478:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1479:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** if (counter_mode == 0U) 1480:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 1481:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** counter_mode = (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR)); 1482:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 1483:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1484:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return counter_mode; 1485:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 1486:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1487:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 1488:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Enable auto-reload (ARR) preload. 1489:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR1 ARPE LL_TIM_EnableARRPreload 1490:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 1491:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 1492:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1493:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_EnableARRPreload(TIM_TypeDef *TIMx) 1494:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 1495:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** SET_BIT(TIMx->CR1, TIM_CR1_ARPE); 1496:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 1497:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1498:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 1499:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Disable auto-reload (ARR) preload. 1500:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR1 ARPE LL_TIM_DisableARRPreload 1501:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 1502:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 1503:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1504:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_DisableARRPreload(TIM_TypeDef *TIMx) 3226 .loc 5 1504 22 view .LVU1117 3227 .LBB405: 1505:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 1506:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** CLEAR_BIT(TIMx->CR1, TIM_CR1_ARPE); 3228 .loc 5 1506 3 view .LVU1118 3229 005e 4FF08043 mov r3, #1073741824 3230 0062 1A68 ldr r2, [r3] 3231 0064 22F08002 bic r2, r2, #128 3232 0068 1A60 str r2, [r3] 3233 .LVL241: 3234 .loc 5 1506 3 is_stmt 0 view .LVU1119 3235 .LBE405: 3236 .LBE404: 1049:Src/main.c **** LL_TIM_SetTriggerOutput(TIM2, LL_TIM_TRGO_RESET); 3237 .loc 2 1049 3 is_stmt 1 view .LVU1120 3238 .LBB406: 3239 .LBI406: 1507:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 1508:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** ARM GAS /tmp/ccdsDELB.s page 223 1509:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 1510:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Indicates whether auto-reload (ARR) preload is enabled. 1511:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR1 ARPE LL_TIM_IsEnabledARRPreload 1512:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 1513:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval State of bit (1 or 0). 1514:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1515:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsEnabledARRPreload(const TIM_TypeDef *TIMx) 1516:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 1517:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return ((READ_BIT(TIMx->CR1, TIM_CR1_ARPE) == (TIM_CR1_ARPE)) ? 1UL : 0UL); 1518:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 1519:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1520:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 1521:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Set the division ratio between the timer clock and the sampling clock used by the dead 1522:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * (when supported) and the digital filters. 1523:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check 1524:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * whether or not the clock division feature is supported by the timer 1525:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * instance. 1526:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR1 CKD LL_TIM_SetClockDivision 1527:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 1528:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param ClockDivision This parameter can be one of the following values: 1529:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CLOCKDIVISION_DIV1 1530:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CLOCKDIVISION_DIV2 1531:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CLOCKDIVISION_DIV4 1532:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 1533:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1534:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_SetClockDivision(TIM_TypeDef *TIMx, uint32_t ClockDivision) 1535:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 1536:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(TIMx->CR1, TIM_CR1_CKD, ClockDivision); 1537:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 1538:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1539:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 1540:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Get the actual division ratio between the timer clock and the sampling clock used by t 1541:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * generators (when supported) and the digital filters. 1542:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check 1543:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * whether or not the clock division feature is supported by the timer 1544:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * instance. 1545:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR1 CKD LL_TIM_GetClockDivision 1546:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 1547:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval Returned value can be one of the following values: 1548:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CLOCKDIVISION_DIV1 1549:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CLOCKDIVISION_DIV2 1550:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CLOCKDIVISION_DIV4 1551:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1552:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_GetClockDivision(const TIM_TypeDef *TIMx) 1553:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 1554:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CKD)); 1555:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 1556:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1557:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 1558:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Set the counter value. 1559:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check 1560:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * whether or not a timer instance supports a 32 bits counter. 1561:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CNT CNT LL_TIM_SetCounter 1562:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 1563:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Counter Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF) 1564:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 1565:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ ARM GAS /tmp/ccdsDELB.s page 224 1566:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_SetCounter(TIM_TypeDef *TIMx, uint32_t Counter) 1567:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 1568:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** WRITE_REG(TIMx->CNT, Counter); 1569:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 1570:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1571:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 1572:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Get the counter value. 1573:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check 1574:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * whether or not a timer instance supports a 32 bits counter. 1575:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CNT CNT LL_TIM_GetCounter 1576:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 1577:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF) 1578:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1579:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_GetCounter(const TIM_TypeDef *TIMx) 1580:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 1581:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return (uint32_t)(READ_REG(TIMx->CNT)); 1582:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 1583:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1584:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 1585:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Get the current direction of the counter 1586:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR1 DIR LL_TIM_GetDirection 1587:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 1588:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval Returned value can be one of the following values: 1589:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_COUNTERDIRECTION_UP 1590:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_COUNTERDIRECTION_DOWN 1591:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1592:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_GetDirection(const TIM_TypeDef *TIMx) 1593:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 1594:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR)); 1595:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 1596:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1597:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 1598:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Set the prescaler value. 1599:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note The counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1). 1600:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note The prescaler can be changed on the fly as this control register is buffered. The new 1601:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * prescaler ratio is taken into account at the next update event. 1602:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Helper macro @ref __LL_TIM_CALC_PSC can be used to calculate the Prescaler parameter 1603:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll PSC PSC LL_TIM_SetPrescaler 1604:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 1605:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Prescaler between Min_Data=0 and Max_Data=65535 1606:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 1607:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1608:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Prescaler) 1609:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 1610:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** WRITE_REG(TIMx->PSC, Prescaler); 1611:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 1612:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1613:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 1614:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Get the prescaler value. 1615:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll PSC PSC LL_TIM_GetPrescaler 1616:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 1617:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval Prescaler value between Min_Data=0 and Max_Data=65535 1618:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1619:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_GetPrescaler(const TIM_TypeDef *TIMx) 1620:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 1621:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return (uint32_t)(READ_REG(TIMx->PSC)); 1622:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } ARM GAS /tmp/ccdsDELB.s page 225 1623:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1624:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 1625:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Set the auto-reload value. 1626:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note The counter is blocked while the auto-reload value is null. 1627:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check 1628:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * whether or not a timer instance supports a 32 bits counter. 1629:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Helper macro @ref __LL_TIM_CALC_ARR can be used to calculate the AutoReload parameter 1630:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll ARR ARR LL_TIM_SetAutoReload 1631:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 1632:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param AutoReload between Min_Data=0 and Max_Data=65535 1633:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 1634:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1635:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_SetAutoReload(TIM_TypeDef *TIMx, uint32_t AutoReload) 1636:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 1637:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** WRITE_REG(TIMx->ARR, AutoReload); 1638:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 1639:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1640:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 1641:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Get the auto-reload value. 1642:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll ARR ARR LL_TIM_GetAutoReload 1643:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check 1644:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * whether or not a timer instance supports a 32 bits counter. 1645:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 1646:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval Auto-reload value 1647:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1648:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_GetAutoReload(const TIM_TypeDef *TIMx) 1649:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 1650:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return (uint32_t)(READ_REG(TIMx->ARR)); 1651:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 1652:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1653:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 1654:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Set the repetition counter value. 1655:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note For advanced timer instances RepetitionCounter can be up to 65535. 1656:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check 1657:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * whether or not a timer instance supports a repetition counter. 1658:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll RCR REP LL_TIM_SetRepetitionCounter 1659:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 1660:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param RepetitionCounter between Min_Data=0 and Max_Data=255 or 65535 for advanced timer. 1661:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 1662:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1663:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_SetRepetitionCounter(TIM_TypeDef *TIMx, uint32_t RepetitionCounter) 1664:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 1665:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** WRITE_REG(TIMx->RCR, RepetitionCounter); 1666:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 1667:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1668:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 1669:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Get the repetition counter value. 1670:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check 1671:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * whether or not a timer instance supports a repetition counter. 1672:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll RCR REP LL_TIM_GetRepetitionCounter 1673:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 1674:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval Repetition counter value 1675:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1676:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_GetRepetitionCounter(const TIM_TypeDef *TIMx) 1677:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 1678:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return (uint32_t)(READ_REG(TIMx->RCR)); 1679:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } ARM GAS /tmp/ccdsDELB.s page 226 1680:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1681:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 1682:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Force a continuous copy of the update interrupt flag (UIF) into the timer counter regis 1683:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note This allows both the counter value and a potential roll-over condition signalled by the U 1684:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * in an atomic way. 1685:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR1 UIFREMAP LL_TIM_EnableUIFRemap 1686:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 1687:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 1688:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1689:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_EnableUIFRemap(TIM_TypeDef *TIMx) 1690:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 1691:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** SET_BIT(TIMx->CR1, TIM_CR1_UIFREMAP); 1692:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 1693:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1694:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 1695:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Disable update interrupt flag (UIF) remapping. 1696:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR1 UIFREMAP LL_TIM_DisableUIFRemap 1697:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 1698:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 1699:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1700:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_DisableUIFRemap(TIM_TypeDef *TIMx) 1701:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 1702:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** CLEAR_BIT(TIMx->CR1, TIM_CR1_UIFREMAP); 1703:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 1704:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1705:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 1706:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Indicate whether update interrupt flag (UIF) copy is set. 1707:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Counter Counter value 1708:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval State of bit (1 or 0). 1709:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1710:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsActiveUIFCPY(const uint32_t Counter) 1711:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 1712:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return (((Counter & TIM_CNT_UIFCPY) == (TIM_CNT_UIFCPY)) ? 1UL : 0UL); 1713:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 1714:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1715:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 1716:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} 1717:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1718:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1719:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EF_Capture_Compare Capture Compare configuration 1720:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ 1721:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1722:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 1723:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Enable the capture/compare control bits (CCxE, CCxNE and OCxM) preload. 1724:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note CCxE, CCxNE and OCxM bits are preloaded, after having been written, 1725:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * they are updated only when a commutation event (COM) occurs. 1726:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Only on channels that have a complementary output. 1727:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check 1728:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * whether or not a timer instance is able to generate a commutation event. 1729:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR2 CCPC LL_TIM_CC_EnablePreload 1730:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 1731:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 1732:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1733:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_CC_EnablePreload(TIM_TypeDef *TIMx) 1734:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 1735:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** SET_BIT(TIMx->CR2, TIM_CR2_CCPC); 1736:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } ARM GAS /tmp/ccdsDELB.s page 227 1737:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1738:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 1739:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Disable the capture/compare control bits (CCxE, CCxNE and OCxM) preload. 1740:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check 1741:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * whether or not a timer instance is able to generate a commutation event. 1742:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR2 CCPC LL_TIM_CC_DisablePreload 1743:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 1744:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 1745:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1746:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_CC_DisablePreload(TIM_TypeDef *TIMx) 1747:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 1748:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** CLEAR_BIT(TIMx->CR2, TIM_CR2_CCPC); 1749:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 1750:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1751:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 1752:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Indicates whether the capture/compare control bits (CCxE, CCxNE and OCxM) preload is en 1753:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR2 CCPC LL_TIM_CC_IsEnabledPreload 1754:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 1755:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval State of bit (1 or 0). 1756:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1757:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledPreload(const TIM_TypeDef *TIMx) 1758:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 1759:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return ((READ_BIT(TIMx->CR2, TIM_CR2_CCPC) == (TIM_CR2_CCPC)) ? 1UL : 0UL); 1760:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 1761:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1762:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 1763:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Set the updated source of the capture/compare control bits (CCxE, CCxNE and OCxM). 1764:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check 1765:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * whether or not a timer instance is able to generate a commutation event. 1766:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR2 CCUS LL_TIM_CC_SetUpdate 1767:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 1768:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param CCUpdateSource This parameter can be one of the following values: 1769:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CCUPDATESOURCE_COMG_ONLY 1770:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI 1771:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 1772:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1773:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_CC_SetUpdate(TIM_TypeDef *TIMx, uint32_t CCUpdateSource) 1774:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 1775:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(TIMx->CR2, TIM_CR2_CCUS, CCUpdateSource); 1776:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 1777:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1778:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 1779:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Set the trigger of the capture/compare DMA request. 1780:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR2 CCDS LL_TIM_CC_SetDMAReqTrigger 1781:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 1782:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param DMAReqTrigger This parameter can be one of the following values: 1783:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CCDMAREQUEST_CC 1784:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CCDMAREQUEST_UPDATE 1785:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 1786:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1787:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_CC_SetDMAReqTrigger(TIM_TypeDef *TIMx, uint32_t DMAReqTrigger) 1788:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 1789:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(TIMx->CR2, TIM_CR2_CCDS, DMAReqTrigger); 1790:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 1791:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1792:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 1793:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Get actual trigger of the capture/compare DMA request. ARM GAS /tmp/ccdsDELB.s page 228 1794:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR2 CCDS LL_TIM_CC_GetDMAReqTrigger 1795:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 1796:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval Returned value can be one of the following values: 1797:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CCDMAREQUEST_CC 1798:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CCDMAREQUEST_UPDATE 1799:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1800:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_CC_GetDMAReqTrigger(const TIM_TypeDef *TIMx) 1801:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 1802:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return (uint32_t)(READ_BIT(TIMx->CR2, TIM_CR2_CCDS)); 1803:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 1804:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1805:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 1806:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Set the lock level to freeze the 1807:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * configuration of several capture/compare parameters. 1808:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not 1809:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * the lock mechanism is supported by a timer instance. 1810:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll BDTR LOCK LL_TIM_CC_SetLockLevel 1811:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 1812:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param LockLevel This parameter can be one of the following values: 1813:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_LOCKLEVEL_OFF 1814:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_LOCKLEVEL_1 1815:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_LOCKLEVEL_2 1816:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_LOCKLEVEL_3 1817:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 1818:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1819:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_CC_SetLockLevel(TIM_TypeDef *TIMx, uint32_t LockLevel) 1820:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 1821:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(TIMx->BDTR, TIM_BDTR_LOCK, LockLevel); 1822:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 1823:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1824:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 1825:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Enable capture/compare channels. 1826:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCER CC1E LL_TIM_CC_EnableChannel\n 1827:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC1NE LL_TIM_CC_EnableChannel\n 1828:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC2E LL_TIM_CC_EnableChannel\n 1829:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC2NE LL_TIM_CC_EnableChannel\n 1830:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC3E LL_TIM_CC_EnableChannel\n 1831:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC3NE LL_TIM_CC_EnableChannel\n 1832:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC4E LL_TIM_CC_EnableChannel\n 1833:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC5E LL_TIM_CC_EnableChannel\n 1834:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC6E LL_TIM_CC_EnableChannel 1835:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 1836:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Channels This parameter can be a combination of the following values: 1837:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 1838:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1N 1839:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 1840:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2N 1841:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 1842:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3N 1843:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 1844:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH5 1845:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH6 1846:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 1847:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1848:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_CC_EnableChannel(TIM_TypeDef *TIMx, uint32_t Channels) 1849:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 1850:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** SET_BIT(TIMx->CCER, Channels); ARM GAS /tmp/ccdsDELB.s page 229 1851:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 1852:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1853:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 1854:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Disable capture/compare channels. 1855:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCER CC1E LL_TIM_CC_DisableChannel\n 1856:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC1NE LL_TIM_CC_DisableChannel\n 1857:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC2E LL_TIM_CC_DisableChannel\n 1858:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC2NE LL_TIM_CC_DisableChannel\n 1859:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC3E LL_TIM_CC_DisableChannel\n 1860:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC3NE LL_TIM_CC_DisableChannel\n 1861:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC4E LL_TIM_CC_DisableChannel\n 1862:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC5E LL_TIM_CC_DisableChannel\n 1863:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC6E LL_TIM_CC_DisableChannel 1864:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 1865:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Channels This parameter can be a combination of the following values: 1866:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 1867:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1N 1868:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 1869:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2N 1870:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 1871:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3N 1872:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 1873:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH5 1874:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH6 1875:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 1876:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1877:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_CC_DisableChannel(TIM_TypeDef *TIMx, uint32_t Channels) 1878:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 1879:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** CLEAR_BIT(TIMx->CCER, Channels); 1880:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 1881:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1882:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 1883:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Indicate whether channel(s) is(are) enabled. 1884:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCER CC1E LL_TIM_CC_IsEnabledChannel\n 1885:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC1NE LL_TIM_CC_IsEnabledChannel\n 1886:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC2E LL_TIM_CC_IsEnabledChannel\n 1887:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC2NE LL_TIM_CC_IsEnabledChannel\n 1888:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC3E LL_TIM_CC_IsEnabledChannel\n 1889:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC3NE LL_TIM_CC_IsEnabledChannel\n 1890:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC4E LL_TIM_CC_IsEnabledChannel\n 1891:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC5E LL_TIM_CC_IsEnabledChannel\n 1892:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC6E LL_TIM_CC_IsEnabledChannel 1893:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 1894:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Channels This parameter can be a combination of the following values: 1895:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 1896:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1N 1897:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 1898:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2N 1899:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 1900:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3N 1901:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 1902:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH5 1903:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH6 1904:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval State of bit (1 or 0). 1905:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1906:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledChannel(const TIM_TypeDef *TIMx, uint32_t Channels) 1907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { ARM GAS /tmp/ccdsDELB.s page 230 1908:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return ((READ_BIT(TIMx->CCER, Channels) == (Channels)) ? 1UL : 0UL); 1909:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 1910:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1911:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 1912:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} 1913:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1914:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1915:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EF_Output_Channel Output channel configuration 1916:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ 1917:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 1919:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Configure an output channel. 1920:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCMR1 CC1S LL_TIM_OC_ConfigOutput\n 1921:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR1 CC2S LL_TIM_OC_ConfigOutput\n 1922:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 CC3S LL_TIM_OC_ConfigOutput\n 1923:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 CC4S LL_TIM_OC_ConfigOutput\n 1924:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR3 CC5S LL_TIM_OC_ConfigOutput\n 1925:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR3 CC6S LL_TIM_OC_ConfigOutput\n 1926:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC1P LL_TIM_OC_ConfigOutput\n 1927:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC2P LL_TIM_OC_ConfigOutput\n 1928:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC3P LL_TIM_OC_ConfigOutput\n 1929:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC4P LL_TIM_OC_ConfigOutput\n 1930:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC5P LL_TIM_OC_ConfigOutput\n 1931:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC6P LL_TIM_OC_ConfigOutput\n 1932:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CR2 OIS1 LL_TIM_OC_ConfigOutput\n 1933:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CR2 OIS2 LL_TIM_OC_ConfigOutput\n 1934:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CR2 OIS3 LL_TIM_OC_ConfigOutput\n 1935:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CR2 OIS4 LL_TIM_OC_ConfigOutput\n 1936:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CR2 OIS5 LL_TIM_OC_ConfigOutput\n 1937:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CR2 OIS6 LL_TIM_OC_ConfigOutput 1938:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 1939:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Channel This parameter can be one of the following values: 1940:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 1941:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 1942:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 1943:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 1944:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH5 1945:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH6 1946:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Configuration This parameter must be a combination of all the following values: 1947:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCPOLARITY_HIGH or @ref LL_TIM_OCPOLARITY_LOW 1948:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCIDLESTATE_LOW or @ref LL_TIM_OCIDLESTATE_HIGH 1949:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 1950:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1951:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configura 1952:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 1953:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 1954:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iC 1955:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** CLEAR_BIT(*pReg, (TIM_CCMR1_CC1S << SHIFT_TAB_OCxx[iChannel])); 1956:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]), 1957:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** (Configuration & TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]); 1958:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]), 1959:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** (Configuration & TIM_CR2_OIS1) << SHIFT_TAB_OISx[iChannel]); 1960:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 1961:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1962:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 1963:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Define the behavior of the output reference signal OCxREF from which 1964:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * OCx and OCxN (when relevant) are derived. ARM GAS /tmp/ccdsDELB.s page 231 1965:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCMR1 OC1M LL_TIM_OC_SetMode\n 1966:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR1 OC2M LL_TIM_OC_SetMode\n 1967:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 OC3M LL_TIM_OC_SetMode\n 1968:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 OC4M LL_TIM_OC_SetMode\n 1969:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR3 OC5M LL_TIM_OC_SetMode\n 1970:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR3 OC6M LL_TIM_OC_SetMode 1971:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 1972:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Channel This parameter can be one of the following values: 1973:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 1974:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 1975:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 1976:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 1977:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH5 1978:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH6 1979:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Mode This parameter can be one of the following values: 1980:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_FROZEN 1981:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_ACTIVE 1982:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_INACTIVE 1983:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_TOGGLE 1984:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE 1985:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE 1986:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_PWM1 1987:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_PWM2 1988:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_RETRIG_OPM1 1989:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_RETRIG_OPM2 1990:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_COMBINED_PWM1 1991:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_COMBINED_PWM2 1992:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_ASYMMETRIC_PWM1 1993:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_ASYMMETRIC_PWM2 1994:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 1995:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1996:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Mode) 1997:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 1998:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 1999:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iC 2000:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel]), Mode << SHIFT 2001:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 2002:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 2003:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 2004:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Get the output compare mode of an output channel. 2005:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCMR1 OC1M LL_TIM_OC_GetMode\n 2006:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR1 OC2M LL_TIM_OC_GetMode\n 2007:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 OC3M LL_TIM_OC_GetMode\n 2008:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 OC4M LL_TIM_OC_GetMode\n 2009:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR3 OC5M LL_TIM_OC_GetMode\n 2010:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR3 OC6M LL_TIM_OC_GetMode 2011:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 2012:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Channel This parameter can be one of the following values: 2013:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 2014:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 2015:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 2016:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 2017:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH5 2018:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH6 2019:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval Returned value can be one of the following values: 2020:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_FROZEN 2021:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_ACTIVE ARM GAS /tmp/ccdsDELB.s page 232 2022:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_INACTIVE 2023:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_TOGGLE 2024:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE 2025:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE 2026:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_PWM1 2027:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_PWM2 2028:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_RETRIG_OPM1 2029:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_RETRIG_OPM2 2030:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_COMBINED_PWM1 2031:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_COMBINED_PWM2 2032:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_ASYMMETRIC_PWM1 2033:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_ASYMMETRIC_PWM2 2034:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 2035:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_OC_GetMode(const TIM_TypeDef *TIMx, uint32_t Channel) 2036:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 2037:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 2038:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CC 2039:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return (READ_BIT(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel])) >> SHIFT 2040:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 2041:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 2042:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 2043:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Set the polarity of an output channel. 2044:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCER CC1P LL_TIM_OC_SetPolarity\n 2045:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC1NP LL_TIM_OC_SetPolarity\n 2046:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC2P LL_TIM_OC_SetPolarity\n 2047:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC2NP LL_TIM_OC_SetPolarity\n 2048:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC3P LL_TIM_OC_SetPolarity\n 2049:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC3NP LL_TIM_OC_SetPolarity\n 2050:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC4P LL_TIM_OC_SetPolarity\n 2051:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC5P LL_TIM_OC_SetPolarity\n 2052:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC6P LL_TIM_OC_SetPolarity 2053:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 2054:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Channel This parameter can be one of the following values: 2055:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 2056:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1N 2057:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 2058:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2N 2059:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 2060:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3N 2061:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 2062:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH5 2063:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH6 2064:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Polarity This parameter can be one of the following values: 2065:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCPOLARITY_HIGH 2066:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCPOLARITY_LOW 2067:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 2068:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 2069:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_OC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Polarity) 2070:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 2071:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 2072:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]), Polarity << SHIFT_TAB_CCxP[i 2073:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 2074:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 2075:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 2076:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Get the polarity of an output channel. 2077:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCER CC1P LL_TIM_OC_GetPolarity\n 2078:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC1NP LL_TIM_OC_GetPolarity\n ARM GAS /tmp/ccdsDELB.s page 233 2079:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC2P LL_TIM_OC_GetPolarity\n 2080:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC2NP LL_TIM_OC_GetPolarity\n 2081:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC3P LL_TIM_OC_GetPolarity\n 2082:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC3NP LL_TIM_OC_GetPolarity\n 2083:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC4P LL_TIM_OC_GetPolarity\n 2084:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC5P LL_TIM_OC_GetPolarity\n 2085:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC6P LL_TIM_OC_GetPolarity 2086:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 2087:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Channel This parameter can be one of the following values: 2088:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 2089:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1N 2090:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 2091:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2N 2092:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 2093:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3N 2094:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 2095:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH5 2096:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH6 2097:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval Returned value can be one of the following values: 2098:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCPOLARITY_HIGH 2099:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCPOLARITY_LOW 2100:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 2101:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity(const TIM_TypeDef *TIMx, uint32_t Channel) 2102:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 2103:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 2104:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return (READ_BIT(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel])) >> SHIFT_TAB_CCxP[iChan 2105:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 2106:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 2107:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 2108:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Set the IDLE state of an output channel 2109:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note This function is significant only for the timer instances 2110:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * supporting the break feature. Macro IS_TIM_BREAK_INSTANCE(TIMx) 2111:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * can be used to check whether or not a timer instance provides 2112:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * a break input. 2113:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR2 OIS1 LL_TIM_OC_SetIdleState\n 2114:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CR2 OIS2N LL_TIM_OC_SetIdleState\n 2115:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CR2 OIS2 LL_TIM_OC_SetIdleState\n 2116:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CR2 OIS2N LL_TIM_OC_SetIdleState\n 2117:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CR2 OIS3 LL_TIM_OC_SetIdleState\n 2118:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CR2 OIS3N LL_TIM_OC_SetIdleState\n 2119:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CR2 OIS4 LL_TIM_OC_SetIdleState\n 2120:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CR2 OIS5 LL_TIM_OC_SetIdleState\n 2121:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CR2 OIS6 LL_TIM_OC_SetIdleState 2122:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 2123:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Channel This parameter can be one of the following values: 2124:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 2125:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1N 2126:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 2127:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2N 2128:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 2129:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3N 2130:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 2131:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH5 2132:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH6 2133:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param IdleState This parameter can be one of the following values: 2134:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCIDLESTATE_LOW 2135:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCIDLESTATE_HIGH ARM GAS /tmp/ccdsDELB.s page 234 2136:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 2137:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 2138:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_OC_SetIdleState(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t IdleState 2139:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 2140:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 2141:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]), IdleState << SHIFT_TAB_OISx[iC 2142:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 2143:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 2144:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 2145:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Get the IDLE state of an output channel 2146:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR2 OIS1 LL_TIM_OC_GetIdleState\n 2147:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CR2 OIS2N LL_TIM_OC_GetIdleState\n 2148:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CR2 OIS2 LL_TIM_OC_GetIdleState\n 2149:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CR2 OIS2N LL_TIM_OC_GetIdleState\n 2150:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CR2 OIS3 LL_TIM_OC_GetIdleState\n 2151:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CR2 OIS3N LL_TIM_OC_GetIdleState\n 2152:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CR2 OIS4 LL_TIM_OC_GetIdleState\n 2153:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CR2 OIS5 LL_TIM_OC_GetIdleState\n 2154:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CR2 OIS6 LL_TIM_OC_GetIdleState 2155:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 2156:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Channel This parameter can be one of the following values: 2157:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 2158:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1N 2159:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 2160:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2N 2161:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 2162:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3N 2163:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 2164:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH5 2165:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH6 2166:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval Returned value can be one of the following values: 2167:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCIDLESTATE_LOW 2168:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCIDLESTATE_HIGH 2169:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 2170:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_OC_GetIdleState(const TIM_TypeDef *TIMx, uint32_t Channel) 2171:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 2172:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 2173:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return (READ_BIT(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel])) >> SHIFT_TAB_OISx[iChanne 2174:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 2175:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 2176:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 2177:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Enable fast mode for the output channel. 2178:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Acts only if the channel is configured in PWM1 or PWM2 mode. 2179:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCMR1 OC1FE LL_TIM_OC_EnableFast\n 2180:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR1 OC2FE LL_TIM_OC_EnableFast\n 2181:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 OC3FE LL_TIM_OC_EnableFast\n 2182:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 OC4FE LL_TIM_OC_EnableFast\n 2183:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR3 OC5FE LL_TIM_OC_EnableFast\n 2184:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR3 OC6FE LL_TIM_OC_EnableFast 2185:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 2186:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Channel This parameter can be one of the following values: 2187:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 2188:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 2189:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 2190:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 2191:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH5 2192:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH6 ARM GAS /tmp/ccdsDELB.s page 235 2193:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 2194:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 2195:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_OC_EnableFast(TIM_TypeDef *TIMx, uint32_t Channel) 2196:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 2197:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 2198:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iC 2199:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** SET_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel])); 2200:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 2201:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 2202:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 2203:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 2204:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Disable fast mode for the output channel. 2205:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCMR1 OC1FE LL_TIM_OC_DisableFast\n 2206:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR1 OC2FE LL_TIM_OC_DisableFast\n 2207:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 OC3FE LL_TIM_OC_DisableFast\n 2208:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 OC4FE LL_TIM_OC_DisableFast\n 2209:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR3 OC5FE LL_TIM_OC_DisableFast\n 2210:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR3 OC6FE LL_TIM_OC_DisableFast 2211:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 2212:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Channel This parameter can be one of the following values: 2213:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 2214:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 2215:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 2216:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 2217:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH5 2218:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH6 2219:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 2220:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 2221:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_OC_DisableFast(TIM_TypeDef *TIMx, uint32_t Channel) 2222:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 2223:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 2224:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iC 2225:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** CLEAR_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel])); 2226:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 2227:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 2228:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 2229:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 2230:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Indicates whether fast mode is enabled for the output channel. 2231:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCMR1 OC1FE LL_TIM_OC_IsEnabledFast\n 2232:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR1 OC2FE LL_TIM_OC_IsEnabledFast\n 2233:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 OC3FE LL_TIM_OC_IsEnabledFast\n 2234:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 OC4FE LL_TIM_OC_IsEnabledFast\n 2235:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR3 OC5FE LL_TIM_OC_IsEnabledFast\n 2236:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR3 OC6FE LL_TIM_OC_IsEnabledFast 2237:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 2238:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Channel This parameter can be one of the following values: 2239:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 2240:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 2241:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 2242:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 2243:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH5 2244:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH6 2245:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval State of bit (1 or 0). 2246:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 2247:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(const TIM_TypeDef *TIMx, uint32_t Channel) 2248:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 2249:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); ARM GAS /tmp/ccdsDELB.s page 236 2250:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CC 2251:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t bitfield = TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]; 2252:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL); 2253:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 2254:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 2255:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 2256:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Enable compare register (TIMx_CCRx) preload for the output channel. 2257:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCMR1 OC1PE LL_TIM_OC_EnablePreload\n 2258:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR1 OC2PE LL_TIM_OC_EnablePreload\n 2259:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 OC3PE LL_TIM_OC_EnablePreload\n 2260:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 OC4PE LL_TIM_OC_EnablePreload\n 2261:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR3 OC5PE LL_TIM_OC_EnablePreload\n 2262:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR3 OC6PE LL_TIM_OC_EnablePreload 2263:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 2264:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Channel This parameter can be one of the following values: 2265:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 2266:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 2267:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 2268:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 2269:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH5 2270:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH6 2271:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 2272:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 2273:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_OC_EnablePreload(TIM_TypeDef *TIMx, uint32_t Channel) 2274:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 2275:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 2276:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iC 2277:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** SET_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel])); 2278:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 2279:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 2280:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 2281:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Disable compare register (TIMx_CCRx) preload for the output channel. 2282:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCMR1 OC1PE LL_TIM_OC_DisablePreload\n 2283:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR1 OC2PE LL_TIM_OC_DisablePreload\n 2284:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 OC3PE LL_TIM_OC_DisablePreload\n 2285:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 OC4PE LL_TIM_OC_DisablePreload\n 2286:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR3 OC5PE LL_TIM_OC_DisablePreload\n 2287:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR3 OC6PE LL_TIM_OC_DisablePreload 2288:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 2289:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Channel This parameter can be one of the following values: 2290:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 2291:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 2292:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 2293:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 2294:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH5 2295:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH6 2296:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 2297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 2298:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_OC_DisablePreload(TIM_TypeDef *TIMx, uint32_t Channel) 2299:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 2300:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 2301:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iC 2302:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** CLEAR_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel])); 2303:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 2304:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 2305:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 2306:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Indicates whether compare register (TIMx_CCRx) preload is enabled for the output channe ARM GAS /tmp/ccdsDELB.s page 237 2307:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCMR1 OC1PE LL_TIM_OC_IsEnabledPreload\n 2308:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR1 OC2PE LL_TIM_OC_IsEnabledPreload\n 2309:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 OC3PE LL_TIM_OC_IsEnabledPreload\n 2310:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 OC4PE LL_TIM_OC_IsEnabledPreload\n 2311:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR3 OC5PE LL_TIM_OC_IsEnabledPreload\n 2312:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR3 OC6PE LL_TIM_OC_IsEnabledPreload 2313:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 2314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Channel This parameter can be one of the following values: 2315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 2316:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 2317:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 2318:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 2319:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH5 2320:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH6 2321:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval State of bit (1 or 0). 2322:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 2323:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(const TIM_TypeDef *TIMx, uint32_t Channel) 2324:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 2325:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 2326:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CC 2327:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t bitfield = TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]; 2328:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL); 2329:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 2330:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 2331:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 2332:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Enable clearing the output channel on an external event. 2333:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note This function can only be used in Output compare and PWM modes. It does not work in Force 2334:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether 2335:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * or not a timer instance can clear the OCxREF signal on an external event. 2336:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCMR1 OC1CE LL_TIM_OC_EnableClear\n 2337:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR1 OC2CE LL_TIM_OC_EnableClear\n 2338:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 OC3CE LL_TIM_OC_EnableClear\n 2339:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 OC4CE LL_TIM_OC_EnableClear\n 2340:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR3 OC5CE LL_TIM_OC_EnableClear\n 2341:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR3 OC6CE LL_TIM_OC_EnableClear 2342:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 2343:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Channel This parameter can be one of the following values: 2344:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 2345:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 2346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 2347:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 2348:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH5 2349:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH6 2350:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 2351:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 2352:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_OC_EnableClear(TIM_TypeDef *TIMx, uint32_t Channel) 2353:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 2354:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 2355:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iC 2356:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** SET_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel])); 2357:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 2358:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 2359:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 2360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Disable clearing the output channel on an external event. 2361:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether 2362:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * or not a timer instance can clear the OCxREF signal on an external event. 2363:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCMR1 OC1CE LL_TIM_OC_DisableClear\n ARM GAS /tmp/ccdsDELB.s page 238 2364:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR1 OC2CE LL_TIM_OC_DisableClear\n 2365:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 OC3CE LL_TIM_OC_DisableClear\n 2366:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 OC4CE LL_TIM_OC_DisableClear\n 2367:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR3 OC5CE LL_TIM_OC_DisableClear\n 2368:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR3 OC6CE LL_TIM_OC_DisableClear 2369:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 2370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Channel This parameter can be one of the following values: 2371:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 2372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 2373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 2374:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 2375:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH5 2376:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH6 2377:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 2378:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 2379:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_OC_DisableClear(TIM_TypeDef *TIMx, uint32_t Channel) 2380:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 2381:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 2382:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iC 2383:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** CLEAR_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel])); 2384:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 2385:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 2386:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 2387:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Indicates clearing the output channel on an external event is enabled for the output ch 2388:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note This function enables clearing the output channel on an external event. 2389:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note This function can only be used in Output compare and PWM modes. It does not work in Force 2390:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether 2391:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * or not a timer instance can clear the OCxREF signal on an external event. 2392:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCMR1 OC1CE LL_TIM_OC_IsEnabledClear\n 2393:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR1 OC2CE LL_TIM_OC_IsEnabledClear\n 2394:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 OC3CE LL_TIM_OC_IsEnabledClear\n 2395:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 OC4CE LL_TIM_OC_IsEnabledClear\n 2396:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR3 OC5CE LL_TIM_OC_IsEnabledClear\n 2397:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR3 OC6CE LL_TIM_OC_IsEnabledClear 2398:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 2399:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Channel This parameter can be one of the following values: 2400:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 2401:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 2402:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 2403:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 2404:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH5 2405:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH6 2406:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval State of bit (1 or 0). 2407:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 2408:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(const TIM_TypeDef *TIMx, uint32_t Channel) 2409:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 2410:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 2411:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CC 2412:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t bitfield = TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]; 2413:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL); 2414:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 2415:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 2416:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 2417:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Set the dead-time delay (delay inserted between the rising edge of the OCxREF signal an 2418:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * the Ocx and OCxN signals). 2419:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not 2420:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * dead-time insertion feature is supported by a timer instance. ARM GAS /tmp/ccdsDELB.s page 239 2421:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Helper macro @ref __LL_TIM_CALC_DEADTIME can be used to calculate the DeadTime parameter 2422:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll BDTR DTG LL_TIM_OC_SetDeadTime 2423:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 2424:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param DeadTime between Min_Data=0 and Max_Data=255 2425:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 2426:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 2427:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_OC_SetDeadTime(TIM_TypeDef *TIMx, uint32_t DeadTime) 2428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 2429:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(TIMx->BDTR, TIM_BDTR_DTG, DeadTime); 2430:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 2431:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 2432:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 2433:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Set compare value for output channel 1 (TIMx_CCR1). 2434:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF. 2435:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check 2436:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * whether or not a timer instance supports a 32 bits counter. 2437:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not 2438:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * output channel 1 is supported by a timer instance. 2439:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCR1 CCR1 LL_TIM_OC_SetCompareCH1 2440:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 2441:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param CompareValue between Min_Data=0 and Max_Data=65535 2442:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 2443:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 2444:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_OC_SetCompareCH1(TIM_TypeDef *TIMx, uint32_t CompareValue) 2445:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 2446:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** WRITE_REG(TIMx->CCR1, CompareValue); 2447:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 2448:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 2449:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 2450:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Set compare value for output channel 2 (TIMx_CCR2). 2451:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF. 2452:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check 2453:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * whether or not a timer instance supports a 32 bits counter. 2454:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not 2455:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * output channel 2 is supported by a timer instance. 2456:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCR2 CCR2 LL_TIM_OC_SetCompareCH2 2457:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 2458:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param CompareValue between Min_Data=0 and Max_Data=65535 2459:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 2460:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 2461:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_OC_SetCompareCH2(TIM_TypeDef *TIMx, uint32_t CompareValue) 2462:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 2463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** WRITE_REG(TIMx->CCR2, CompareValue); 2464:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 2465:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 2466:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 2467:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Set compare value for output channel 3 (TIMx_CCR3). 2468:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF. 2469:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check 2470:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * whether or not a timer instance supports a 32 bits counter. 2471:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not 2472:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * output channel is supported by a timer instance. 2473:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCR3 CCR3 LL_TIM_OC_SetCompareCH3 2474:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 2475:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param CompareValue between Min_Data=0 and Max_Data=65535 2476:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 2477:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ ARM GAS /tmp/ccdsDELB.s page 240 2478:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_OC_SetCompareCH3(TIM_TypeDef *TIMx, uint32_t CompareValue) 2479:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 2480:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** WRITE_REG(TIMx->CCR3, CompareValue); 2481:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 2482:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 2483:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 2484:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Set compare value for output channel 4 (TIMx_CCR4). 2485:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF. 2486:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check 2487:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * whether or not a timer instance supports a 32 bits counter. 2488:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not 2489:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * output channel 4 is supported by a timer instance. 2490:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCR4 CCR4 LL_TIM_OC_SetCompareCH4 2491:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 2492:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param CompareValue between Min_Data=0 and Max_Data=65535 2493:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 2494:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 2495:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_OC_SetCompareCH4(TIM_TypeDef *TIMx, uint32_t CompareValue) 2496:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 2497:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** WRITE_REG(TIMx->CCR4, CompareValue); 2498:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 2499:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 2500:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 2501:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Set compare value for output channel 5 (TIMx_CCR5). 2502:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not 2503:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * output channel 5 is supported by a timer instance. 2504:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCR5 CCR5 LL_TIM_OC_SetCompareCH5 2505:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 2506:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param CompareValue between Min_Data=0 and Max_Data=65535 2507:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 2508:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 2509:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_OC_SetCompareCH5(TIM_TypeDef *TIMx, uint32_t CompareValue) 2510:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 2511:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(TIMx->CCR5, TIM_CCR5_CCR5, CompareValue); 2512:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 2513:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 2514:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 2515:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Set compare value for output channel 6 (TIMx_CCR6). 2516:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not 2517:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * output channel 6 is supported by a timer instance. 2518:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCR6 CCR6 LL_TIM_OC_SetCompareCH6 2519:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 2520:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param CompareValue between Min_Data=0 and Max_Data=65535 2521:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 2522:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 2523:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_OC_SetCompareCH6(TIM_TypeDef *TIMx, uint32_t CompareValue) 2524:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 2525:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** WRITE_REG(TIMx->CCR6, CompareValue); 2526:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 2527:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 2528:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 2529:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Get compare value (TIMx_CCR1) set for output channel 1. 2530:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFF 2531:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check 2532:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * whether or not a timer instance supports a 32 bits counter. 2533:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not 2534:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * output channel 1 is supported by a timer instance. ARM GAS /tmp/ccdsDELB.s page 241 2535:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCR1 CCR1 LL_TIM_OC_GetCompareCH1 2536:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 2537:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval CompareValue (between Min_Data=0 and Max_Data=65535) 2538:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 2539:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH1(const TIM_TypeDef *TIMx) 2540:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 2541:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return (uint32_t)(READ_REG(TIMx->CCR1)); 2542:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 2543:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 2544:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 2545:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Get compare value (TIMx_CCR2) set for output channel 2. 2546:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFF 2547:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check 2548:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * whether or not a timer instance supports a 32 bits counter. 2549:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not 2550:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * output channel 2 is supported by a timer instance. 2551:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCR2 CCR2 LL_TIM_OC_GetCompareCH2 2552:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 2553:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval CompareValue (between Min_Data=0 and Max_Data=65535) 2554:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 2555:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH2(const TIM_TypeDef *TIMx) 2556:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 2557:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return (uint32_t)(READ_REG(TIMx->CCR2)); 2558:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 2559:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 2560:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 2561:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Get compare value (TIMx_CCR3) set for output channel 3. 2562:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFF 2563:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check 2564:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * whether or not a timer instance supports a 32 bits counter. 2565:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not 2566:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * output channel 3 is supported by a timer instance. 2567:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCR3 CCR3 LL_TIM_OC_GetCompareCH3 2568:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 2569:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval CompareValue (between Min_Data=0 and Max_Data=65535) 2570:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 2571:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH3(const TIM_TypeDef *TIMx) 2572:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 2573:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return (uint32_t)(READ_REG(TIMx->CCR3)); 2574:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 2575:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 2576:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 2577:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Get compare value (TIMx_CCR4) set for output channel 4. 2578:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFF 2579:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check 2580:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * whether or not a timer instance supports a 32 bits counter. 2581:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not 2582:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * output channel 4 is supported by a timer instance. 2583:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCR4 CCR4 LL_TIM_OC_GetCompareCH4 2584:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 2585:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval CompareValue (between Min_Data=0 and Max_Data=65535) 2586:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 2587:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH4(const TIM_TypeDef *TIMx) 2588:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 2589:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return (uint32_t)(READ_REG(TIMx->CCR4)); 2590:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 2591:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** ARM GAS /tmp/ccdsDELB.s page 242 2592:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 2593:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Get compare value (TIMx_CCR5) set for output channel 5. 2594:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not 2595:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * output channel 5 is supported by a timer instance. 2596:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCR5 CCR5 LL_TIM_OC_GetCompareCH5 2597:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 2598:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval CompareValue (between Min_Data=0 and Max_Data=65535) 2599:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 2600:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH5(const TIM_TypeDef *TIMx) 2601:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 2602:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return (uint32_t)(READ_BIT(TIMx->CCR5, TIM_CCR5_CCR5)); 2603:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 2604:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 2605:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 2606:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Get compare value (TIMx_CCR6) set for output channel 6. 2607:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not 2608:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * output channel 6 is supported by a timer instance. 2609:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCR6 CCR6 LL_TIM_OC_GetCompareCH6 2610:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 2611:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval CompareValue (between Min_Data=0 and Max_Data=65535) 2612:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 2613:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH6(const TIM_TypeDef *TIMx) 2614:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 2615:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return (uint32_t)(READ_REG(TIMx->CCR6)); 2616:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 2617:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 2618:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 2619:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Select on which reference signal the OC5REF is combined to. 2620:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_COMBINED3PHASEPWM_INSTANCE(TIMx) can be used to check 2621:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * whether or not a timer instance supports the combined 3-phase PWM mode. 2622:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCR5 GC5C3 LL_TIM_SetCH5CombinedChannels\n 2623:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCR5 GC5C2 LL_TIM_SetCH5CombinedChannels\n 2624:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCR5 GC5C1 LL_TIM_SetCH5CombinedChannels 2625:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 2626:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param GroupCH5 This parameter can be a combination of the following values: 2627:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_GROUPCH5_NONE 2628:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_GROUPCH5_OC1REFC 2629:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_GROUPCH5_OC2REFC 2630:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_GROUPCH5_OC3REFC 2631:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 2632:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 2633:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_SetCH5CombinedChannels(TIM_TypeDef *TIMx, uint32_t GroupCH5) 2634:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 2635:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(TIMx->CCR5, (TIM_CCR5_GC5C3 | TIM_CCR5_GC5C2 | TIM_CCR5_GC5C1), GroupCH5); 2636:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 2637:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 2638:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 2639:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} 2640:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 2641:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 2642:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EF_Input_Channel Input channel configuration 2643:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ 2644:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 2645:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 2646:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Configure input channel. 2647:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCMR1 CC1S LL_TIM_IC_Config\n 2648:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR1 IC1PSC LL_TIM_IC_Config\n ARM GAS /tmp/ccdsDELB.s page 243 2649:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR1 IC1F LL_TIM_IC_Config\n 2650:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR1 CC2S LL_TIM_IC_Config\n 2651:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR1 IC2PSC LL_TIM_IC_Config\n 2652:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR1 IC2F LL_TIM_IC_Config\n 2653:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 CC3S LL_TIM_IC_Config\n 2654:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 IC3PSC LL_TIM_IC_Config\n 2655:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 IC3F LL_TIM_IC_Config\n 2656:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 CC4S LL_TIM_IC_Config\n 2657:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 IC4PSC LL_TIM_IC_Config\n 2658:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 IC4F LL_TIM_IC_Config\n 2659:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC1P LL_TIM_IC_Config\n 2660:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC1NP LL_TIM_IC_Config\n 2661:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC2P LL_TIM_IC_Config\n 2662:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC2NP LL_TIM_IC_Config\n 2663:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC3P LL_TIM_IC_Config\n 2664:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC3NP LL_TIM_IC_Config\n 2665:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC4P LL_TIM_IC_Config\n 2666:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC4NP LL_TIM_IC_Config 2667:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 2668:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Channel This parameter can be one of the following values: 2669:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 2670:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 2671:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 2672:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 2673:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Configuration This parameter must be a combination of all the following values: 2674:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI or @ref LL_TIM_ACTIVEINPUT_INDIRECTTI or @ref LL_ 2675:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ICPSC_DIV1 or ... or @ref LL_TIM_ICPSC_DIV8 2676:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV1 or ... or @ref LL_TIM_IC_FILTER_FDIV32_N8 2677:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_POLARITY_RISING or @ref LL_TIM_IC_POLARITY_FALLING or @ref LL_TIM_I 2678:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 2679:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 2680:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration) 2681:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 2682:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 2683:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iC 2684:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChanne 2685:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** ((Configuration >> 16U) & (TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S)) 2686:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** << SHIFT_TAB_ICxx[iChannel]); 2687:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]), 2688:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** (Configuration & (TIM_CCER_CC1NP | TIM_CCER_CC1P)) << SHIFT_TAB_CCxP[iChannel]); 2689:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 2690:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 2691:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 2692:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Set the active input. 2693:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCMR1 CC1S LL_TIM_IC_SetActiveInput\n 2694:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR1 CC2S LL_TIM_IC_SetActiveInput\n 2695:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 CC3S LL_TIM_IC_SetActiveInput\n 2696:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 CC4S LL_TIM_IC_SetActiveInput 2697:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 2698:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Channel This parameter can be one of the following values: 2699:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 2700:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 2701:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 2702:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 2703:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param ICActiveInput This parameter can be one of the following values: 2704:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI 2705:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI ARM GAS /tmp/ccdsDELB.s page 244 2706:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ACTIVEINPUT_TRC 2707:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 2708:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 2709:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_IC_SetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICActiv 2710:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 2711:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 2712:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iC 2713:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), (ICActiveInput >> 16U) << SHIFT 2714:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 2715:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 2716:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 2717:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Get the current active input. 2718:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCMR1 CC1S LL_TIM_IC_GetActiveInput\n 2719:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR1 CC2S LL_TIM_IC_GetActiveInput\n 2720:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 CC3S LL_TIM_IC_GetActiveInput\n 2721:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 CC4S LL_TIM_IC_GetActiveInput 2722:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 2723:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Channel This parameter can be one of the following values: 2724:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 2725:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 2726:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 2727:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 2728:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval Returned value can be one of the following values: 2729:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI 2730:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI 2731:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ACTIVEINPUT_TRC 2732:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 2733:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(const TIM_TypeDef *TIMx, uint32_t Channel) 2734:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 2735:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 2736:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CC 2737:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return ((READ_BIT(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChann 2738:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 2739:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 2740:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 2741:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Set the prescaler of input channel. 2742:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCMR1 IC1PSC LL_TIM_IC_SetPrescaler\n 2743:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR1 IC2PSC LL_TIM_IC_SetPrescaler\n 2744:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 IC3PSC LL_TIM_IC_SetPrescaler\n 2745:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 IC4PSC LL_TIM_IC_SetPrescaler 2746:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 2747:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Channel This parameter can be one of the following values: 2748:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 2749:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 2750:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 2751:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 2752:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param ICPrescaler This parameter can be one of the following values: 2753:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ICPSC_DIV1 2754:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ICPSC_DIV2 2755:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ICPSC_DIV4 2756:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ICPSC_DIV8 2757:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 2758:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 2759:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_IC_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPrescal 2760:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 2761:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 2762:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iC ARM GAS /tmp/ccdsDELB.s page 245 2763:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel]), (ICPrescaler >> 16U) << SHIFT 2764:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 2765:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 2766:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 2767:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Get the current prescaler value acting on an input channel. 2768:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCMR1 IC1PSC LL_TIM_IC_GetPrescaler\n 2769:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR1 IC2PSC LL_TIM_IC_GetPrescaler\n 2770:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 IC3PSC LL_TIM_IC_GetPrescaler\n 2771:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 IC4PSC LL_TIM_IC_GetPrescaler 2772:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 2773:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Channel This parameter can be one of the following values: 2774:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 2775:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 2776:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 2777:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 2778:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval Returned value can be one of the following values: 2779:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ICPSC_DIV1 2780:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ICPSC_DIV2 2781:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ICPSC_DIV4 2782:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ICPSC_DIV8 2783:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 2784:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(const TIM_TypeDef *TIMx, uint32_t Channel) 2785:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 2786:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 2787:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CC 2788:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iCha 2789:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 2790:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 2791:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 2792:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Set the input filter duration. 2793:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCMR1 IC1F LL_TIM_IC_SetFilter\n 2794:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR1 IC2F LL_TIM_IC_SetFilter\n 2795:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 IC3F LL_TIM_IC_SetFilter\n 2796:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 IC4F LL_TIM_IC_SetFilter 2797:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 2798:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Channel This parameter can be one of the following values: 2799:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 2800:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 2801:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 2802:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 2803:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param ICFilter This parameter can be one of the following values: 2804:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV1 2805:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV1_N2 2806:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV1_N4 2807:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV1_N8 2808:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV2_N6 2809:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV2_N8 2810:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV4_N6 2811:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV4_N8 2812:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV8_N6 2813:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV8_N8 2814:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV16_N5 2815:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV16_N6 2816:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV16_N8 2817:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV32_N5 2818:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV32_N6 2819:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV32_N8 ARM GAS /tmp/ccdsDELB.s page 246 2820:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 2821:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 2822:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_IC_SetFilter(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICFilter) 2823:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 2824:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 2825:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iC 2826:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel]), (ICFilter >> 16U) << SHIFT_TAB_ 2827:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 2828:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 2829:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 2830:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Get the input filter duration. 2831:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCMR1 IC1F LL_TIM_IC_GetFilter\n 2832:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR1 IC2F LL_TIM_IC_GetFilter\n 2833:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 IC3F LL_TIM_IC_GetFilter\n 2834:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 IC4F LL_TIM_IC_GetFilter 2835:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 2836:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Channel This parameter can be one of the following values: 2837:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 2838:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 2839:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 2840:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 2841:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval Returned value can be one of the following values: 2842:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV1 2843:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV1_N2 2844:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV1_N4 2845:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV1_N8 2846:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV2_N6 2847:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV2_N8 2848:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV4_N6 2849:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV4_N8 2850:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV8_N6 2851:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV8_N8 2852:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV16_N5 2853:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV16_N6 2854:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV16_N8 2855:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV32_N5 2856:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV32_N6 2857:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV32_N8 2858:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 2859:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IC_GetFilter(const TIM_TypeDef *TIMx, uint32_t Channel) 2860:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 2861:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 2862:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CC 2863:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChann 2864:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 2865:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 2866:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 2867:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Set the input channel polarity. 2868:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCER CC1P LL_TIM_IC_SetPolarity\n 2869:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC1NP LL_TIM_IC_SetPolarity\n 2870:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC2P LL_TIM_IC_SetPolarity\n 2871:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC2NP LL_TIM_IC_SetPolarity\n 2872:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC3P LL_TIM_IC_SetPolarity\n 2873:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC3NP LL_TIM_IC_SetPolarity\n 2874:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC4P LL_TIM_IC_SetPolarity\n 2875:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC4NP LL_TIM_IC_SetPolarity 2876:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance ARM GAS /tmp/ccdsDELB.s page 247 2877:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Channel This parameter can be one of the following values: 2878:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 2879:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 2880:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 2881:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 2882:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param ICPolarity This parameter can be one of the following values: 2883:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_POLARITY_RISING 2884:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_POLARITY_FALLING 2885:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE 2886:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 2887:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 2888:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_IC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPolarity 2889:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 2890:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 2891:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]), 2892:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** ICPolarity << SHIFT_TAB_CCxP[iChannel]); 2893:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 2894:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 2895:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 2896:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Get the current input channel polarity. 2897:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCER CC1P LL_TIM_IC_GetPolarity\n 2898:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC1NP LL_TIM_IC_GetPolarity\n 2899:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC2P LL_TIM_IC_GetPolarity\n 2900:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC2NP LL_TIM_IC_GetPolarity\n 2901:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC3P LL_TIM_IC_GetPolarity\n 2902:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC3NP LL_TIM_IC_GetPolarity\n 2903:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC4P LL_TIM_IC_GetPolarity\n 2904:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC4NP LL_TIM_IC_GetPolarity 2905:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 2906:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Channel This parameter can be one of the following values: 2907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 2908:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 2909:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 2910:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 2911:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval Returned value can be one of the following values: 2912:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_POLARITY_RISING 2913:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_POLARITY_FALLING 2914:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE 2915:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 2916:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IC_GetPolarity(const TIM_TypeDef *TIMx, uint32_t Channel) 2917:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 2918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 2919:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return (READ_BIT(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel])) >> 2920:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** SHIFT_TAB_CCxP[iChannel]); 2921:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 2922:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 2923:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 2924:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Connect the TIMx_CH1, CH2 and CH3 pins to the TI1 input (XOR combination). 2925:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not 2926:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * a timer instance provides an XOR input. 2927:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR2 TI1S LL_TIM_IC_EnableXORCombination 2928:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 2929:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 2930:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 2931:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_IC_EnableXORCombination(TIM_TypeDef *TIMx) 2932:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 2933:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** SET_BIT(TIMx->CR2, TIM_CR2_TI1S); ARM GAS /tmp/ccdsDELB.s page 248 2934:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 2935:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 2936:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 2937:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Disconnect the TIMx_CH1, CH2 and CH3 pins from the TI1 input. 2938:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not 2939:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * a timer instance provides an XOR input. 2940:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR2 TI1S LL_TIM_IC_DisableXORCombination 2941:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 2942:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 2943:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 2944:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_IC_DisableXORCombination(TIM_TypeDef *TIMx) 2945:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 2946:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** CLEAR_BIT(TIMx->CR2, TIM_CR2_TI1S); 2947:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 2948:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 2949:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 2950:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Indicates whether the TIMx_CH1, CH2 and CH3 pins are connectected to the TI1 input. 2951:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not 2952:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * a timer instance provides an XOR input. 2953:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR2 TI1S LL_TIM_IC_IsEnabledXORCombination 2954:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 2955:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval State of bit (1 or 0). 2956:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 2957:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IC_IsEnabledXORCombination(const TIM_TypeDef *TIMx) 2958:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 2959:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return ((READ_BIT(TIMx->CR2, TIM_CR2_TI1S) == (TIM_CR2_TI1S)) ? 1UL : 0UL); 2960:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 2961:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 2962:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 2963:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Get captured value for input channel 1. 2964:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xF 2965:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check 2966:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * whether or not a timer instance supports a 32 bits counter. 2967:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not 2968:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * input channel 1 is supported by a timer instance. 2969:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCR1 CCR1 LL_TIM_IC_GetCaptureCH1 2970:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 2971:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval CapturedValue (between Min_Data=0 and Max_Data=65535) 2972:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 2973:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH1(const TIM_TypeDef *TIMx) 2974:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 2975:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return (uint32_t)(READ_REG(TIMx->CCR1)); 2976:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 2977:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 2978:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 2979:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Get captured value for input channel 2. 2980:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xF 2981:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check 2982:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * whether or not a timer instance supports a 32 bits counter. 2983:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not 2984:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * input channel 2 is supported by a timer instance. 2985:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCR2 CCR2 LL_TIM_IC_GetCaptureCH2 2986:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 2987:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval CapturedValue (between Min_Data=0 and Max_Data=65535) 2988:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 2989:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH2(const TIM_TypeDef *TIMx) 2990:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { ARM GAS /tmp/ccdsDELB.s page 249 2991:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return (uint32_t)(READ_REG(TIMx->CCR2)); 2992:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 2993:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 2994:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 2995:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Get captured value for input channel 3. 2996:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xF 2997:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check 2998:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * whether or not a timer instance supports a 32 bits counter. 2999:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not 3000:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * input channel 3 is supported by a timer instance. 3001:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCR3 CCR3 LL_TIM_IC_GetCaptureCH3 3002:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3003:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval CapturedValue (between Min_Data=0 and Max_Data=65535) 3004:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3005:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH3(const TIM_TypeDef *TIMx) 3006:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3007:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return (uint32_t)(READ_REG(TIMx->CCR3)); 3008:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3009:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3010:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3011:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Get captured value for input channel 4. 3012:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xF 3013:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check 3014:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * whether or not a timer instance supports a 32 bits counter. 3015:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not 3016:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * input channel 4 is supported by a timer instance. 3017:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCR4 CCR4 LL_TIM_IC_GetCaptureCH4 3018:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3019:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval CapturedValue (between Min_Data=0 and Max_Data=65535) 3020:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3021:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH4(const TIM_TypeDef *TIMx) 3022:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3023:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return (uint32_t)(READ_REG(TIMx->CCR4)); 3024:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3025:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3026:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3027:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} 3028:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3029:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3030:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EF_Clock_Selection Counter clock selection 3031:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ 3032:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3033:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3034:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Enable external clock mode 2. 3035:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note When external clock mode 2 is enabled the counter is clocked by any active edge on the ET 3036:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check 3037:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * whether or not a timer instance supports external clock mode2. 3038:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SMCR ECE LL_TIM_EnableExternalClock 3039:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3040:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 3041:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3042:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_EnableExternalClock(TIM_TypeDef *TIMx) 3043:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3044:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** SET_BIT(TIMx->SMCR, TIM_SMCR_ECE); 3045:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3046:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3047:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** ARM GAS /tmp/ccdsDELB.s page 250 3048:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Disable external clock mode 2. 3049:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check 3050:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * whether or not a timer instance supports external clock mode2. 3051:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SMCR ECE LL_TIM_DisableExternalClock 3052:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3053:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 3054:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3055:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_DisableExternalClock(TIM_TypeDef *TIMx) 3056:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3057:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** CLEAR_BIT(TIMx->SMCR, TIM_SMCR_ECE); 3058:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3059:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3060:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3061:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Indicate whether external clock mode 2 is enabled. 3062:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check 3063:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * whether or not a timer instance supports external clock mode2. 3064:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SMCR ECE LL_TIM_IsEnabledExternalClock 3065:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3066:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval State of bit (1 or 0). 3067:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3068:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsEnabledExternalClock(const TIM_TypeDef *TIMx) 3069:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3070:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return ((READ_BIT(TIMx->SMCR, TIM_SMCR_ECE) == (TIM_SMCR_ECE)) ? 1UL : 0UL); 3071:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3072:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3073:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3074:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Set the clock source of the counter clock. 3075:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note when selected clock source is external clock mode 1, the timer input 3076:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * the external clock is applied is selected by calling the @ref LL_TIM_SetTriggerInput() 3077:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * function. This timer input must be configured by calling 3078:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * the @ref LL_TIM_IC_Config() function. 3079:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(TIMx) can be used to check 3080:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * whether or not a timer instance supports external clock mode1. 3081:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check 3082:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * whether or not a timer instance supports external clock mode2. 3083:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SMCR SMS LL_TIM_SetClockSource\n 3084:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * SMCR ECE LL_TIM_SetClockSource 3085:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3086:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param ClockSource This parameter can be one of the following values: 3087:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CLOCKSOURCE_INTERNAL 3088:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE1 3089:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE2 3090:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 3091:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3092:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_SetClockSource(TIM_TypeDef *TIMx, uint32_t ClockSource) 3240 .loc 5 3092 22 view .LVU1121 3241 .LBB407: 3093:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3094:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS | TIM_SMCR_ECE, ClockSource); 3242 .loc 5 3094 3 view .LVU1122 3243 006a 9968 ldr r1, [r3, #8] 3244 006c 0A4A ldr r2, .L130+16 3245 006e 0A40 ands r2, r2, r1 3246 0070 9A60 str r2, [r3, #8] 3247 .LVL242: 3248 .loc 5 3094 3 is_stmt 0 view .LVU1123 3249 .LBE407: ARM GAS /tmp/ccdsDELB.s page 251 3250 .LBE406: 1050:Src/main.c **** LL_TIM_DisableMasterSlaveMode(TIM2); 3251 .loc 2 1050 3 is_stmt 1 view .LVU1124 3252 .LBB408: 3253 .LBI408: 3095:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3096:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3097:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3098:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Set the encoder interface mode. 3099:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx) can be used to check 3100:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * whether or not a timer instance supports the encoder mode. 3101:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SMCR SMS LL_TIM_SetEncoderMode 3102:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3103:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param EncoderMode This parameter can be one of the following values: 3104:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ENCODERMODE_X2_TI1 3105:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ENCODERMODE_X2_TI2 3106:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ENCODERMODE_X4_TI12 3107:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 3108:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3109:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_SetEncoderMode(TIM_TypeDef *TIMx, uint32_t EncoderMode) 3110:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3111:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, EncoderMode); 3112:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3113:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3114:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3115:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} 3116:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3117:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3118:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EF_Timer_Synchronization Timer synchronisation configuration 3119:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ 3120:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3121:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3122:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Set the trigger output (TRGO) used for timer synchronization . 3123:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_MASTER_INSTANCE(TIMx) can be used to check 3124:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * whether or not a timer instance can operate as a master timer. 3125:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR2 MMS LL_TIM_SetTriggerOutput 3126:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3127:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TimerSynchronization This parameter can be one of the following values: 3128:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TRGO_RESET 3129:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TRGO_ENABLE 3130:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TRGO_UPDATE 3131:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TRGO_CC1IF 3132:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TRGO_OC1REF 3133:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TRGO_OC2REF 3134:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TRGO_OC3REF 3135:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TRGO_OC4REF 3136:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 3137:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3138:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_SetTriggerOutput(TIM_TypeDef *TIMx, uint32_t TimerSynchronization) 3254 .loc 5 3138 22 view .LVU1125 3255 .LBB409: 3139:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3140:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(TIMx->CR2, TIM_CR2_MMS, TimerSynchronization); 3256 .loc 5 3140 3 view .LVU1126 3257 0072 5A68 ldr r2, [r3, #4] 3258 0074 22F07002 bic r2, r2, #112 3259 0078 5A60 str r2, [r3, #4] ARM GAS /tmp/ccdsDELB.s page 252 3260 .LVL243: 3261 .loc 5 3140 3 is_stmt 0 view .LVU1127 3262 .LBE409: 3263 .LBE408: 1051:Src/main.c **** /* USER CODE BEGIN TIM2_Init 2 */ 3264 .loc 2 1051 3 is_stmt 1 view .LVU1128 3265 .LBB410: 3266 .LBI410: 3141:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3142:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3143:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3144:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Set the trigger output 2 (TRGO2) used for ADC synchronization . 3145:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_TRGO2_INSTANCE(TIMx) can be used to check 3146:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * whether or not a timer instance can be used for ADC synchronization. 3147:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR2 MMS2 LL_TIM_SetTriggerOutput2 3148:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer Instance 3149:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param ADCSynchronization This parameter can be one of the following values: 3150:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TRGO2_RESET 3151:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TRGO2_ENABLE 3152:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TRGO2_UPDATE 3153:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TRGO2_CC1F 3154:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TRGO2_OC1 3155:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TRGO2_OC2 3156:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TRGO2_OC3 3157:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TRGO2_OC4 3158:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TRGO2_OC5 3159:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TRGO2_OC6 3160:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TRGO2_OC4_RISINGFALLING 3161:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TRGO2_OC6_RISINGFALLING 3162:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TRGO2_OC4_RISING_OC6_RISING 3163:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TRGO2_OC4_RISING_OC6_FALLING 3164:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TRGO2_OC5_RISING_OC6_RISING 3165:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TRGO2_OC5_RISING_OC6_FALLING 3166:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 3167:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3168:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_SetTriggerOutput2(TIM_TypeDef *TIMx, uint32_t ADCSynchronization) 3169:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3170:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(TIMx->CR2, TIM_CR2_MMS2, ADCSynchronization); 3171:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3172:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3173:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3174:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Set the synchronization mode of a slave timer. 3175:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not 3176:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * a timer instance can operate as a slave timer. 3177:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SMCR SMS LL_TIM_SetSlaveMode 3178:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3179:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param SlaveMode This parameter can be one of the following values: 3180:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_SLAVEMODE_DISABLED 3181:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_SLAVEMODE_RESET 3182:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_SLAVEMODE_GATED 3183:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_SLAVEMODE_TRIGGER 3184:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_SLAVEMODE_COMBINED_RESETTRIGGER 3185:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 3186:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3187:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_SetSlaveMode(TIM_TypeDef *TIMx, uint32_t SlaveMode) 3188:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3189:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, SlaveMode); ARM GAS /tmp/ccdsDELB.s page 253 3190:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3191:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3192:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3193:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Set the selects the trigger input to be used to synchronize the counter. 3194:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not 3195:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * a timer instance can operate as a slave timer. 3196:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SMCR TS LL_TIM_SetTriggerInput 3197:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3198:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TriggerInput This parameter can be one of the following values: 3199:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TS_ITR0 3200:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TS_ITR1 3201:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TS_ITR2 3202:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TS_ITR3 3203:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TS_TI1F_ED 3204:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TS_TI1FP1 3205:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TS_TI2FP2 3206:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TS_ETRF 3207:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 3208:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3209:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_SetTriggerInput(TIM_TypeDef *TIMx, uint32_t TriggerInput) 3210:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3211:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(TIMx->SMCR, TIM_SMCR_TS, TriggerInput); 3212:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3213:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3214:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3215:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Enable the Master/Slave mode. 3216:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not 3217:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * a timer instance can operate as a slave timer. 3218:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SMCR MSM LL_TIM_EnableMasterSlaveMode 3219:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3220:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 3221:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3222:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_EnableMasterSlaveMode(TIM_TypeDef *TIMx) 3223:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3224:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** SET_BIT(TIMx->SMCR, TIM_SMCR_MSM); 3225:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3226:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3227:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3228:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Disable the Master/Slave mode. 3229:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not 3230:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * a timer instance can operate as a slave timer. 3231:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SMCR MSM LL_TIM_DisableMasterSlaveMode 3232:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3233:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 3234:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3235:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_DisableMasterSlaveMode(TIM_TypeDef *TIMx) 3267 .loc 5 3235 22 view .LVU1129 3268 .LBB411: 3236:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3237:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** CLEAR_BIT(TIMx->SMCR, TIM_SMCR_MSM); 3269 .loc 5 3237 3 view .LVU1130 3270 007a 9A68 ldr r2, [r3, #8] 3271 007c 22F08002 bic r2, r2, #128 3272 0080 9A60 str r2, [r3, #8] 3273 .LVL244: 3274 .loc 5 3237 3 is_stmt 0 view .LVU1131 3275 .LBE411: ARM GAS /tmp/ccdsDELB.s page 254 3276 .LBE410: 1056:Src/main.c **** 3277 .loc 2 1056 1 view .LVU1132 3278 0082 06B0 add sp, sp, #24 3279 .LCFI27: 3280 .cfi_def_cfa_offset 8 3281 @ sp needed 3282 0084 10BD pop {r4, pc} 3283 .L131: 3284 0086 00BF .align 2 3285 .L130: 3286 0088 00380240 .word 1073887232 3287 008c 00ED00E0 .word -536810240 3288 0090 00E100E0 .word -536813312 3289 0094 40D10C00 .word 840000 3290 0098 F8BFFEFF .word -81928 3291 .cfi_endproc 3292 .LFE1195: 3294 .section .text.MX_TIM5_Init,"ax",%progbits 3295 .align 1 3296 .syntax unified 3297 .thumb 3298 .thumb_func 3299 .fpu fpv5-d16 3301 MX_TIM5_Init: 3302 .LFB1196: 1064:Src/main.c **** 3303 .loc 2 1064 1 is_stmt 1 view -0 3304 .cfi_startproc 3305 @ args = 0, pretend = 0, frame = 24 3306 @ frame_needed = 0, uses_anonymous_args = 0 3307 0000 10B5 push {r4, lr} 3308 .LCFI28: 3309 .cfi_def_cfa_offset 8 3310 .cfi_offset 4, -8 3311 .cfi_offset 14, -4 3312 0002 86B0 sub sp, sp, #24 3313 .LCFI29: 3314 .cfi_def_cfa_offset 32 1070:Src/main.c **** 3315 .loc 2 1070 3 view .LVU1134 1070:Src/main.c **** 3316 .loc 2 1070 22 is_stmt 0 view .LVU1135 3317 0004 0024 movs r4, #0 3318 0006 0194 str r4, [sp, #4] 3319 0008 0294 str r4, [sp, #8] 3320 000a 0394 str r4, [sp, #12] 3321 000c 0494 str r4, [sp, #16] 3322 000e 0594 str r4, [sp, #20] 1073:Src/main.c **** 3323 .loc 2 1073 3 is_stmt 1 view .LVU1136 3324 .LVL245: 3325 .LBB412: 3326 .LBI412: 1071:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { 3327 .loc 3 1071 22 view .LVU1137 3328 .LBB413: ARM GAS /tmp/ccdsDELB.s page 255 1073:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** SET_BIT(RCC->APB1ENR, Periphs); 3329 .loc 3 1073 3 view .LVU1138 1074:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Delay after an RCC peripheral clock enabling */ 3330 .loc 3 1074 3 view .LVU1139 3331 0010 1C4B ldr r3, .L134 3332 0012 1A6C ldr r2, [r3, #64] 3333 0014 42F00802 orr r2, r2, #8 3334 0018 1A64 str r2, [r3, #64] 1076:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; 3335 .loc 3 1076 3 view .LVU1140 1076:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; 3336 .loc 3 1076 12 is_stmt 0 view .LVU1141 3337 001a 1B6C ldr r3, [r3, #64] 3338 001c 03F00803 and r3, r3, #8 1076:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; 3339 .loc 3 1076 10 view .LVU1142 3340 0020 0093 str r3, [sp] 1077:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } 3341 .loc 3 1077 3 is_stmt 1 view .LVU1143 3342 0022 009B ldr r3, [sp] 3343 .LVL246: 1077:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } 3344 .loc 3 1077 3 is_stmt 0 view .LVU1144 3345 .LBE413: 3346 .LBE412: 1076:Src/main.c **** NVIC_EnableIRQ(TIM5_IRQn); 3347 .loc 2 1076 3 is_stmt 1 view .LVU1145 3348 .LBB414: 3349 .LBI414: 1884:Drivers/CMSIS/Include/core_cm7.h **** { 3350 .loc 1 1884 26 view .LVU1146 3351 .LBB415: 1886:Drivers/CMSIS/Include/core_cm7.h **** } 3352 .loc 1 1886 3 view .LVU1147 1886:Drivers/CMSIS/Include/core_cm7.h **** } 3353 .loc 1 1886 26 is_stmt 0 view .LVU1148 3354 0024 184B ldr r3, .L134+4 3355 0026 D868 ldr r0, [r3, #12] 3356 .LBE415: 3357 .LBE414: 1076:Src/main.c **** NVIC_EnableIRQ(TIM5_IRQn); 3358 .loc 2 1076 3 view .LVU1149 3359 0028 2246 mov r2, r4 3360 002a 2146 mov r1, r4 3361 002c C0F30220 ubfx r0, r0, #8, #3 3362 0030 FFF7FEFF bl NVIC_EncodePriority 3363 .LVL247: 3364 .LBB416: 3365 .LBI416: 2024:Drivers/CMSIS/Include/core_cm7.h **** { 3366 .loc 1 2024 22 is_stmt 1 view .LVU1150 3367 .LBB417: 2026:Drivers/CMSIS/Include/core_cm7.h **** { 3368 .loc 1 2026 3 view .LVU1151 2028:Drivers/CMSIS/Include/core_cm7.h **** } 3369 .loc 1 2028 5 view .LVU1152 2028:Drivers/CMSIS/Include/core_cm7.h **** } ARM GAS /tmp/ccdsDELB.s page 256 3370 .loc 1 2028 49 is_stmt 0 view .LVU1153 3371 0034 0001 lsls r0, r0, #4 3372 .LVL248: 2028:Drivers/CMSIS/Include/core_cm7.h **** } 3373 .loc 1 2028 49 view .LVU1154 3374 0036 C0B2 uxtb r0, r0 2028:Drivers/CMSIS/Include/core_cm7.h **** } 3375 .loc 1 2028 47 view .LVU1155 3376 0038 144B ldr r3, .L134+8 3377 003a 83F83203 strb r0, [r3, #818] 3378 .LVL249: 2028:Drivers/CMSIS/Include/core_cm7.h **** } 3379 .loc 1 2028 47 view .LVU1156 3380 .LBE417: 3381 .LBE416: 1077:Src/main.c **** 3382 .loc 2 1077 3 is_stmt 1 view .LVU1157 3383 .LBB418: 3384 .LBI418: 1896:Drivers/CMSIS/Include/core_cm7.h **** { 3385 .loc 1 1896 22 view .LVU1158 3386 .LBB419: 1898:Drivers/CMSIS/Include/core_cm7.h **** { 3387 .loc 1 1898 3 view .LVU1159 1900:Drivers/CMSIS/Include/core_cm7.h **** } 3388 .loc 1 1900 5 view .LVU1160 1900:Drivers/CMSIS/Include/core_cm7.h **** } 3389 .loc 1 1900 43 is_stmt 0 view .LVU1161 3390 003e 4FF48022 mov r2, #262144 3391 0042 5A60 str r2, [r3, #4] 3392 .LVL250: 1900:Drivers/CMSIS/Include/core_cm7.h **** } 3393 .loc 1 1900 43 view .LVU1162 3394 .LBE419: 3395 .LBE418: 1082:Src/main.c **** TIM_InitStruct.CounterMode = LL_TIM_COUNTERMODE_UP; 3396 .loc 2 1082 3 is_stmt 1 view .LVU1163 1082:Src/main.c **** TIM_InitStruct.CounterMode = LL_TIM_COUNTERMODE_UP; 3397 .loc 2 1082 28 is_stmt 0 view .LVU1164 3398 0044 42F21073 movw r3, #10000 3399 0048 ADF80430 strh r3, [sp, #4] @ movhi 1083:Src/main.c **** TIM_InitStruct.Autoreload = 560; 3400 .loc 2 1083 3 is_stmt 1 view .LVU1165 1083:Src/main.c **** TIM_InitStruct.Autoreload = 560; 3401 .loc 2 1083 30 is_stmt 0 view .LVU1166 3402 004c 0294 str r4, [sp, #8] 1084:Src/main.c **** TIM_InitStruct.ClockDivision = LL_TIM_CLOCKDIVISION_DIV1; 3403 .loc 2 1084 3 is_stmt 1 view .LVU1167 1084:Src/main.c **** TIM_InitStruct.ClockDivision = LL_TIM_CLOCKDIVISION_DIV1; 3404 .loc 2 1084 29 is_stmt 0 view .LVU1168 3405 004e 4FF40C73 mov r3, #560 3406 0052 0393 str r3, [sp, #12] 1085:Src/main.c **** LL_TIM_Init(TIM5, &TIM_InitStruct); 3407 .loc 2 1085 3 is_stmt 1 view .LVU1169 1085:Src/main.c **** LL_TIM_Init(TIM5, &TIM_InitStruct); 3408 .loc 2 1085 32 is_stmt 0 view .LVU1170 3409 0054 0494 str r4, [sp, #16] ARM GAS /tmp/ccdsDELB.s page 257 1086:Src/main.c **** LL_TIM_DisableARRPreload(TIM5); 3410 .loc 2 1086 3 is_stmt 1 view .LVU1171 3411 0056 0E4C ldr r4, .L134+12 3412 0058 01A9 add r1, sp, #4 3413 005a 2046 mov r0, r4 3414 005c FFF7FEFF bl LL_TIM_Init 3415 .LVL251: 1087:Src/main.c **** LL_TIM_SetClockSource(TIM5, LL_TIM_CLOCKSOURCE_INTERNAL); 3416 .loc 2 1087 3 view .LVU1172 3417 .LBB420: 3418 .LBI420: 1504:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3419 .loc 5 1504 22 view .LVU1173 3420 .LBB421: 1506:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3421 .loc 5 1506 3 view .LVU1174 3422 0060 2368 ldr r3, [r4] 3423 0062 23F08003 bic r3, r3, #128 3424 0066 2360 str r3, [r4] 3425 .LVL252: 1506:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3426 .loc 5 1506 3 is_stmt 0 view .LVU1175 3427 .LBE421: 3428 .LBE420: 1088:Src/main.c **** LL_TIM_SetTriggerOutput(TIM5, LL_TIM_TRGO_RESET); 3429 .loc 2 1088 3 is_stmt 1 view .LVU1176 3430 .LBB422: 3431 .LBI422: 3092:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3432 .loc 5 3092 22 view .LVU1177 3433 .LBB423: 3094:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3434 .loc 5 3094 3 view .LVU1178 3435 0068 A268 ldr r2, [r4, #8] 3436 006a 0A4B ldr r3, .L134+16 3437 006c 1340 ands r3, r3, r2 3438 006e A360 str r3, [r4, #8] 3439 .LVL253: 3094:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3440 .loc 5 3094 3 is_stmt 0 view .LVU1179 3441 .LBE423: 3442 .LBE422: 1089:Src/main.c **** LL_TIM_DisableMasterSlaveMode(TIM5); 3443 .loc 2 1089 3 is_stmt 1 view .LVU1180 3444 .LBB424: 3445 .LBI424: 3138:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3446 .loc 5 3138 22 view .LVU1181 3447 .LBB425: 3140:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3448 .loc 5 3140 3 view .LVU1182 3449 0070 6368 ldr r3, [r4, #4] 3450 0072 23F07003 bic r3, r3, #112 3451 0076 6360 str r3, [r4, #4] 3452 .LVL254: 3140:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3453 .loc 5 3140 3 is_stmt 0 view .LVU1183 ARM GAS /tmp/ccdsDELB.s page 258 3454 .LBE425: 3455 .LBE424: 1090:Src/main.c **** /* USER CODE BEGIN TIM5_Init 2 */ 3456 .loc 2 1090 3 is_stmt 1 view .LVU1184 3457 .LBB426: 3458 .LBI426: 3235:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3459 .loc 5 3235 22 view .LVU1185 3460 .LBB427: 3461 .loc 5 3237 3 view .LVU1186 3462 0078 A368 ldr r3, [r4, #8] 3463 007a 23F08003 bic r3, r3, #128 3464 007e A360 str r3, [r4, #8] 3465 .LVL255: 3466 .loc 5 3237 3 is_stmt 0 view .LVU1187 3467 .LBE427: 3468 .LBE426: 1095:Src/main.c **** 3469 .loc 2 1095 1 view .LVU1188 3470 0080 06B0 add sp, sp, #24 3471 .LCFI30: 3472 .cfi_def_cfa_offset 8 3473 @ sp needed 3474 0082 10BD pop {r4, pc} 3475 .L135: 3476 .align 2 3477 .L134: 3478 0084 00380240 .word 1073887232 3479 0088 00ED00E0 .word -536810240 3480 008c 00E100E0 .word -536813312 3481 0090 000C0040 .word 1073744896 3482 0094 F8BFFEFF .word -81928 3483 .cfi_endproc 3484 .LFE1196: 3486 .section .text.MX_TIM7_Init,"ax",%progbits 3487 .align 1 3488 .syntax unified 3489 .thumb 3490 .thumb_func 3491 .fpu fpv5-d16 3493 MX_TIM7_Init: 3494 .LFB1198: 1140:Src/main.c **** 3495 .loc 2 1140 1 is_stmt 1 view -0 3496 .cfi_startproc 3497 @ args = 0, pretend = 0, frame = 24 3498 @ frame_needed = 0, uses_anonymous_args = 0 3499 0000 10B5 push {r4, lr} 3500 .LCFI31: 3501 .cfi_def_cfa_offset 8 3502 .cfi_offset 4, -8 3503 .cfi_offset 14, -4 3504 0002 86B0 sub sp, sp, #24 3505 .LCFI32: 3506 .cfi_def_cfa_offset 32 1146:Src/main.c **** 3507 .loc 2 1146 3 view .LVU1190 ARM GAS /tmp/ccdsDELB.s page 259 1146:Src/main.c **** 3508 .loc 2 1146 22 is_stmt 0 view .LVU1191 3509 0004 0024 movs r4, #0 3510 0006 0194 str r4, [sp, #4] 3511 0008 0294 str r4, [sp, #8] 3512 000a 0394 str r4, [sp, #12] 3513 000c 0494 str r4, [sp, #16] 3514 000e 0594 str r4, [sp, #20] 1149:Src/main.c **** 3515 .loc 2 1149 3 is_stmt 1 view .LVU1192 3516 .LVL256: 3517 .LBB428: 3518 .LBI428: 1071:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { 3519 .loc 3 1071 22 view .LVU1193 3520 .LBB429: 1073:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** SET_BIT(RCC->APB1ENR, Periphs); 3521 .loc 3 1073 3 view .LVU1194 1074:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Delay after an RCC peripheral clock enabling */ 3522 .loc 3 1074 3 view .LVU1195 3523 0010 1A4B ldr r3, .L138 3524 0012 1A6C ldr r2, [r3, #64] 3525 0014 42F02002 orr r2, r2, #32 3526 0018 1A64 str r2, [r3, #64] 1076:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; 3527 .loc 3 1076 3 view .LVU1196 1076:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; 3528 .loc 3 1076 12 is_stmt 0 view .LVU1197 3529 001a 1B6C ldr r3, [r3, #64] 3530 001c 03F02003 and r3, r3, #32 1076:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; 3531 .loc 3 1076 10 view .LVU1198 3532 0020 0093 str r3, [sp] 1077:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } 3533 .loc 3 1077 3 is_stmt 1 view .LVU1199 3534 0022 009B ldr r3, [sp] 3535 .LVL257: 1077:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } 3536 .loc 3 1077 3 is_stmt 0 view .LVU1200 3537 .LBE429: 3538 .LBE428: 1152:Src/main.c **** NVIC_EnableIRQ(TIM7_IRQn); 3539 .loc 2 1152 3 is_stmt 1 view .LVU1201 3540 .LBB430: 3541 .LBI430: 1884:Drivers/CMSIS/Include/core_cm7.h **** { 3542 .loc 1 1884 26 view .LVU1202 3543 .LBB431: 1886:Drivers/CMSIS/Include/core_cm7.h **** } 3544 .loc 1 1886 3 view .LVU1203 1886:Drivers/CMSIS/Include/core_cm7.h **** } 3545 .loc 1 1886 26 is_stmt 0 view .LVU1204 3546 0024 164B ldr r3, .L138+4 3547 0026 D868 ldr r0, [r3, #12] 3548 .LBE431: 3549 .LBE430: 1152:Src/main.c **** NVIC_EnableIRQ(TIM7_IRQn); ARM GAS /tmp/ccdsDELB.s page 260 3550 .loc 2 1152 3 view .LVU1205 3551 0028 2246 mov r2, r4 3552 002a 2146 mov r1, r4 3553 002c C0F30220 ubfx r0, r0, #8, #3 3554 0030 FFF7FEFF bl NVIC_EncodePriority 3555 .LVL258: 3556 .LBB432: 3557 .LBI432: 2024:Drivers/CMSIS/Include/core_cm7.h **** { 3558 .loc 1 2024 22 is_stmt 1 view .LVU1206 3559 .LBB433: 2026:Drivers/CMSIS/Include/core_cm7.h **** { 3560 .loc 1 2026 3 view .LVU1207 2028:Drivers/CMSIS/Include/core_cm7.h **** } 3561 .loc 1 2028 5 view .LVU1208 2028:Drivers/CMSIS/Include/core_cm7.h **** } 3562 .loc 1 2028 49 is_stmt 0 view .LVU1209 3563 0034 0001 lsls r0, r0, #4 3564 .LVL259: 2028:Drivers/CMSIS/Include/core_cm7.h **** } 3565 .loc 1 2028 49 view .LVU1210 3566 0036 C0B2 uxtb r0, r0 2028:Drivers/CMSIS/Include/core_cm7.h **** } 3567 .loc 1 2028 47 view .LVU1211 3568 0038 124B ldr r3, .L138+8 3569 003a 83F83703 strb r0, [r3, #823] 3570 .LVL260: 2028:Drivers/CMSIS/Include/core_cm7.h **** } 3571 .loc 1 2028 47 view .LVU1212 3572 .LBE433: 3573 .LBE432: 1153:Src/main.c **** 3574 .loc 2 1153 3 is_stmt 1 view .LVU1213 3575 .LBB434: 3576 .LBI434: 1896:Drivers/CMSIS/Include/core_cm7.h **** { 3577 .loc 1 1896 22 view .LVU1214 3578 .LBB435: 1898:Drivers/CMSIS/Include/core_cm7.h **** { 3579 .loc 1 1898 3 view .LVU1215 1900:Drivers/CMSIS/Include/core_cm7.h **** } 3580 .loc 1 1900 5 view .LVU1216 1900:Drivers/CMSIS/Include/core_cm7.h **** } 3581 .loc 1 1900 43 is_stmt 0 view .LVU1217 3582 003e 4FF40002 mov r2, #8388608 3583 0042 5A60 str r2, [r3, #4] 3584 .LVL261: 1900:Drivers/CMSIS/Include/core_cm7.h **** } 3585 .loc 1 1900 43 view .LVU1218 3586 .LBE435: 3587 .LBE434: 1158:Src/main.c **** TIM_InitStruct.CounterMode = LL_TIM_COUNTERMODE_UP; 3588 .loc 2 1158 3 is_stmt 1 view .LVU1219 1158:Src/main.c **** TIM_InitStruct.CounterMode = LL_TIM_COUNTERMODE_UP; 3589 .loc 2 1158 28 is_stmt 0 view .LVU1220 3590 0044 40F29733 movw r3, #919 3591 0048 ADF80430 strh r3, [sp, #4] @ movhi ARM GAS /tmp/ccdsDELB.s page 261 1159:Src/main.c **** TIM_InitStruct.Autoreload = 99; 3592 .loc 2 1159 3 is_stmt 1 view .LVU1221 1159:Src/main.c **** TIM_InitStruct.Autoreload = 99; 3593 .loc 2 1159 30 is_stmt 0 view .LVU1222 3594 004c 0294 str r4, [sp, #8] 1160:Src/main.c **** LL_TIM_Init(TIM7, &TIM_InitStruct); 3595 .loc 2 1160 3 is_stmt 1 view .LVU1223 1160:Src/main.c **** LL_TIM_Init(TIM7, &TIM_InitStruct); 3596 .loc 2 1160 29 is_stmt 0 view .LVU1224 3597 004e 6323 movs r3, #99 3598 0050 0393 str r3, [sp, #12] 1161:Src/main.c **** LL_TIM_DisableARRPreload(TIM7); 3599 .loc 2 1161 3 is_stmt 1 view .LVU1225 3600 0052 0D4C ldr r4, .L138+12 3601 0054 01A9 add r1, sp, #4 3602 0056 2046 mov r0, r4 3603 0058 FFF7FEFF bl LL_TIM_Init 3604 .LVL262: 1162:Src/main.c **** LL_TIM_SetTriggerOutput(TIM7, LL_TIM_TRGO_ENABLE); 3605 .loc 2 1162 3 view .LVU1226 3606 .LBB436: 3607 .LBI436: 1504:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3608 .loc 5 1504 22 view .LVU1227 3609 .LBB437: 1506:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3610 .loc 5 1506 3 view .LVU1228 3611 005c 2368 ldr r3, [r4] 3612 005e 23F08003 bic r3, r3, #128 3613 0062 2360 str r3, [r4] 3614 .LVL263: 1506:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3615 .loc 5 1506 3 is_stmt 0 view .LVU1229 3616 .LBE437: 3617 .LBE436: 1163:Src/main.c **** LL_TIM_DisableMasterSlaveMode(TIM7); 3618 .loc 2 1163 3 is_stmt 1 view .LVU1230 3619 .LBB438: 3620 .LBI438: 3138:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3621 .loc 5 3138 22 view .LVU1231 3622 .LBB439: 3140:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3623 .loc 5 3140 3 view .LVU1232 3624 0064 6368 ldr r3, [r4, #4] 3625 0066 23F07003 bic r3, r3, #112 3626 006a 43F01003 orr r3, r3, #16 3627 006e 6360 str r3, [r4, #4] 3628 .LVL264: 3140:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3629 .loc 5 3140 3 is_stmt 0 view .LVU1233 3630 .LBE439: 3631 .LBE438: 1164:Src/main.c **** /* USER CODE BEGIN TIM7_Init 2 */ 3632 .loc 2 1164 3 is_stmt 1 view .LVU1234 3633 .LBB440: 3634 .LBI440: ARM GAS /tmp/ccdsDELB.s page 262 3235:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3635 .loc 5 3235 22 view .LVU1235 3636 .LBB441: 3637 .loc 5 3237 3 view .LVU1236 3638 0070 A368 ldr r3, [r4, #8] 3639 0072 23F08003 bic r3, r3, #128 3640 0076 A360 str r3, [r4, #8] 3641 .LVL265: 3642 .loc 5 3237 3 is_stmt 0 view .LVU1237 3643 .LBE441: 3644 .LBE440: 1169:Src/main.c **** 3645 .loc 2 1169 1 view .LVU1238 3646 0078 06B0 add sp, sp, #24 3647 .LCFI33: 3648 .cfi_def_cfa_offset 8 3649 @ sp needed 3650 007a 10BD pop {r4, pc} 3651 .L139: 3652 .align 2 3653 .L138: 3654 007c 00380240 .word 1073887232 3655 0080 00ED00E0 .word -536810240 3656 0084 00E100E0 .word -536813312 3657 0088 00140040 .word 1073746944 3658 .cfi_endproc 3659 .LFE1198: 3661 .section .text.MX_TIM6_Init,"ax",%progbits 3662 .align 1 3663 .syntax unified 3664 .thumb 3665 .thumb_func 3666 .fpu fpv5-d16 3668 MX_TIM6_Init: 3669 .LFB1197: 1103:Src/main.c **** 3670 .loc 2 1103 1 is_stmt 1 view -0 3671 .cfi_startproc 3672 @ args = 0, pretend = 0, frame = 24 3673 @ frame_needed = 0, uses_anonymous_args = 0 3674 0000 10B5 push {r4, lr} 3675 .LCFI34: 3676 .cfi_def_cfa_offset 8 3677 .cfi_offset 4, -8 3678 .cfi_offset 14, -4 3679 0002 86B0 sub sp, sp, #24 3680 .LCFI35: 3681 .cfi_def_cfa_offset 32 1109:Src/main.c **** 3682 .loc 2 1109 3 view .LVU1240 1109:Src/main.c **** 3683 .loc 2 1109 22 is_stmt 0 view .LVU1241 3684 0004 0024 movs r4, #0 3685 0006 0194 str r4, [sp, #4] 3686 0008 0294 str r4, [sp, #8] 3687 000a 0394 str r4, [sp, #12] 3688 000c 0494 str r4, [sp, #16] ARM GAS /tmp/ccdsDELB.s page 263 3689 000e 0594 str r4, [sp, #20] 1112:Src/main.c **** 3690 .loc 2 1112 3 is_stmt 1 view .LVU1242 3691 .LVL266: 3692 .LBB442: 3693 .LBI442: 1071:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { 3694 .loc 3 1071 22 view .LVU1243 3695 .LBB443: 1073:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** SET_BIT(RCC->APB1ENR, Periphs); 3696 .loc 3 1073 3 view .LVU1244 1074:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Delay after an RCC peripheral clock enabling */ 3697 .loc 3 1074 3 view .LVU1245 3698 0010 1A4B ldr r3, .L142 3699 0012 1A6C ldr r2, [r3, #64] 3700 0014 42F01002 orr r2, r2, #16 3701 0018 1A64 str r2, [r3, #64] 1076:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; 3702 .loc 3 1076 3 view .LVU1246 1076:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; 3703 .loc 3 1076 12 is_stmt 0 view .LVU1247 3704 001a 1B6C ldr r3, [r3, #64] 3705 001c 03F01003 and r3, r3, #16 1076:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; 3706 .loc 3 1076 10 view .LVU1248 3707 0020 0093 str r3, [sp] 1077:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } 3708 .loc 3 1077 3 is_stmt 1 view .LVU1249 3709 0022 009B ldr r3, [sp] 3710 .LVL267: 1077:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } 3711 .loc 3 1077 3 is_stmt 0 view .LVU1250 3712 .LBE443: 3713 .LBE442: 1115:Src/main.c **** NVIC_EnableIRQ(TIM6_DAC_IRQn); 3714 .loc 2 1115 3 is_stmt 1 view .LVU1251 3715 .LBB444: 3716 .LBI444: 1884:Drivers/CMSIS/Include/core_cm7.h **** { 3717 .loc 1 1884 26 view .LVU1252 3718 .LBB445: 1886:Drivers/CMSIS/Include/core_cm7.h **** } 3719 .loc 1 1886 3 view .LVU1253 1886:Drivers/CMSIS/Include/core_cm7.h **** } 3720 .loc 1 1886 26 is_stmt 0 view .LVU1254 3721 0024 164B ldr r3, .L142+4 3722 0026 D868 ldr r0, [r3, #12] 3723 .LBE445: 3724 .LBE444: 1115:Src/main.c **** NVIC_EnableIRQ(TIM6_DAC_IRQn); 3725 .loc 2 1115 3 view .LVU1255 3726 0028 2246 mov r2, r4 3727 002a 2146 mov r1, r4 3728 002c C0F30220 ubfx r0, r0, #8, #3 3729 0030 FFF7FEFF bl NVIC_EncodePriority 3730 .LVL268: 3731 .LBB446: ARM GAS /tmp/ccdsDELB.s page 264 3732 .LBI446: 2024:Drivers/CMSIS/Include/core_cm7.h **** { 3733 .loc 1 2024 22 is_stmt 1 view .LVU1256 3734 .LBB447: 2026:Drivers/CMSIS/Include/core_cm7.h **** { 3735 .loc 1 2026 3 view .LVU1257 2028:Drivers/CMSIS/Include/core_cm7.h **** } 3736 .loc 1 2028 5 view .LVU1258 2028:Drivers/CMSIS/Include/core_cm7.h **** } 3737 .loc 1 2028 49 is_stmt 0 view .LVU1259 3738 0034 0001 lsls r0, r0, #4 3739 .LVL269: 2028:Drivers/CMSIS/Include/core_cm7.h **** } 3740 .loc 1 2028 49 view .LVU1260 3741 0036 C0B2 uxtb r0, r0 2028:Drivers/CMSIS/Include/core_cm7.h **** } 3742 .loc 1 2028 47 view .LVU1261 3743 0038 124B ldr r3, .L142+8 3744 003a 83F83603 strb r0, [r3, #822] 3745 .LVL270: 2028:Drivers/CMSIS/Include/core_cm7.h **** } 3746 .loc 1 2028 47 view .LVU1262 3747 .LBE447: 3748 .LBE446: 1116:Src/main.c **** 3749 .loc 2 1116 3 is_stmt 1 view .LVU1263 3750 .LBB448: 3751 .LBI448: 1896:Drivers/CMSIS/Include/core_cm7.h **** { 3752 .loc 1 1896 22 view .LVU1264 3753 .LBB449: 1898:Drivers/CMSIS/Include/core_cm7.h **** { 3754 .loc 1 1898 3 view .LVU1265 1900:Drivers/CMSIS/Include/core_cm7.h **** } 3755 .loc 1 1900 5 view .LVU1266 1900:Drivers/CMSIS/Include/core_cm7.h **** } 3756 .loc 1 1900 43 is_stmt 0 view .LVU1267 3757 003e 4FF48002 mov r2, #4194304 3758 0042 5A60 str r2, [r3, #4] 3759 .LVL271: 1900:Drivers/CMSIS/Include/core_cm7.h **** } 3760 .loc 1 1900 43 view .LVU1268 3761 .LBE449: 3762 .LBE448: 1121:Src/main.c **** TIM_InitStruct.CounterMode = LL_TIM_COUNTERMODE_UP; 3763 .loc 2 1121 3 is_stmt 1 view .LVU1269 1121:Src/main.c **** TIM_InitStruct.CounterMode = LL_TIM_COUNTERMODE_UP; 3764 .loc 2 1121 28 is_stmt 0 view .LVU1270 3765 0044 4BF2AF33 movw r3, #45999 3766 0048 ADF80430 strh r3, [sp, #4] @ movhi 1122:Src/main.c **** TIM_InitStruct.Autoreload = 19; 3767 .loc 2 1122 3 is_stmt 1 view .LVU1271 1122:Src/main.c **** TIM_InitStruct.Autoreload = 19; 3768 .loc 2 1122 30 is_stmt 0 view .LVU1272 3769 004c 0294 str r4, [sp, #8] 1123:Src/main.c **** LL_TIM_Init(TIM6, &TIM_InitStruct); 3770 .loc 2 1123 3 is_stmt 1 view .LVU1273 ARM GAS /tmp/ccdsDELB.s page 265 1123:Src/main.c **** LL_TIM_Init(TIM6, &TIM_InitStruct); 3771 .loc 2 1123 29 is_stmt 0 view .LVU1274 3772 004e 1323 movs r3, #19 3773 0050 0393 str r3, [sp, #12] 1124:Src/main.c **** LL_TIM_DisableARRPreload(TIM6); 3774 .loc 2 1124 3 is_stmt 1 view .LVU1275 3775 0052 0D4C ldr r4, .L142+12 3776 0054 01A9 add r1, sp, #4 3777 0056 2046 mov r0, r4 3778 0058 FFF7FEFF bl LL_TIM_Init 3779 .LVL272: 1125:Src/main.c **** LL_TIM_SetTriggerOutput(TIM6, LL_TIM_TRGO_ENABLE); 3780 .loc 2 1125 3 view .LVU1276 3781 .LBB450: 3782 .LBI450: 1504:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3783 .loc 5 1504 22 view .LVU1277 3784 .LBB451: 1506:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3785 .loc 5 1506 3 view .LVU1278 3786 005c 2368 ldr r3, [r4] 3787 005e 23F08003 bic r3, r3, #128 3788 0062 2360 str r3, [r4] 3789 .LVL273: 1506:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3790 .loc 5 1506 3 is_stmt 0 view .LVU1279 3791 .LBE451: 3792 .LBE450: 1126:Src/main.c **** LL_TIM_DisableMasterSlaveMode(TIM6); 3793 .loc 2 1126 3 is_stmt 1 view .LVU1280 3794 .LBB452: 3795 .LBI452: 3138:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3796 .loc 5 3138 22 view .LVU1281 3797 .LBB453: 3140:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3798 .loc 5 3140 3 view .LVU1282 3799 0064 6368 ldr r3, [r4, #4] 3800 0066 23F07003 bic r3, r3, #112 3801 006a 43F01003 orr r3, r3, #16 3802 006e 6360 str r3, [r4, #4] 3803 .LVL274: 3140:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3804 .loc 5 3140 3 is_stmt 0 view .LVU1283 3805 .LBE453: 3806 .LBE452: 1127:Src/main.c **** /* USER CODE BEGIN TIM6_Init 2 */ 3807 .loc 2 1127 3 is_stmt 1 view .LVU1284 3808 .LBB454: 3809 .LBI454: 3235:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3810 .loc 5 3235 22 view .LVU1285 3811 .LBB455: 3812 .loc 5 3237 3 view .LVU1286 3813 0070 A368 ldr r3, [r4, #8] 3814 0072 23F08003 bic r3, r3, #128 3815 0076 A360 str r3, [r4, #8] ARM GAS /tmp/ccdsDELB.s page 266 3816 .LVL275: 3817 .loc 5 3237 3 is_stmt 0 view .LVU1287 3818 .LBE455: 3819 .LBE454: 1132:Src/main.c **** 3820 .loc 2 1132 1 view .LVU1288 3821 0078 06B0 add sp, sp, #24 3822 .LCFI36: 3823 .cfi_def_cfa_offset 8 3824 @ sp needed 3825 007a 10BD pop {r4, pc} 3826 .L143: 3827 .align 2 3828 .L142: 3829 007c 00380240 .word 1073887232 3830 0080 00ED00E0 .word -536810240 3831 0084 00E100E0 .word -536813312 3832 0088 00100040 .word 1073745920 3833 .cfi_endproc 3834 .LFE1197: 3836 .section .rodata.Decode_uart.str1.4,"aMS",%progbits,1 3837 .align 2 3838 .LC0: 3839 0000 2F00 .ascii "/\000" 3840 0002 0000 .align 2 3841 .LC1: 3842 0004 434F4D4D .ascii "COMMAND.TXT\000" 3842 414E442E 3842 54585400 3843 .section .text.Decode_uart,"ax",%progbits 3844 .align 1 3845 .syntax unified 3846 .thumb 3847 .thumb_func 3848 .fpu fpv5-d16 3850 Decode_uart: 3851 .LVL276: 3852 .LFB1204: 1596:Src/main.c **** // uint8_t *temp1; 3853 .loc 2 1596 1 is_stmt 1 view -0 3854 .cfi_startproc 3855 @ args = 0, pretend = 0, frame = 0 3856 @ frame_needed = 0, uses_anonymous_args = 0 1596:Src/main.c **** // uint8_t *temp1; 3857 .loc 2 1596 1 is_stmt 0 view .LVU1290 3858 0000 2DE9F843 push {r3, r4, r5, r6, r7, r8, r9, lr} 3859 .LCFI37: 3860 .cfi_def_cfa_offset 32 3861 .cfi_offset 3, -32 3862 .cfi_offset 4, -28 3863 .cfi_offset 5, -24 3864 .cfi_offset 6, -20 3865 .cfi_offset 7, -16 3866 .cfi_offset 8, -12 3867 .cfi_offset 9, -8 3868 .cfi_offset 14, -4 3869 0004 0546 mov r5, r0 ARM GAS /tmp/ccdsDELB.s page 267 3870 0006 0F46 mov r7, r1 3871 0008 1646 mov r6, r2 3872 000a 1C46 mov r4, r3 1598:Src/main.c **** 3873 .loc 2 1598 2 is_stmt 1 view .LVU1291 1603:Src/main.c **** if ((HAL_GPIO_ReadPin(SDMMC1_EN_GPIO_Port, SDMMC1_EN_Pin) == GPIO_PIN_RESET)&& 3874 .loc 2 1603 2 view .LVU1292 1603:Src/main.c **** if ((HAL_GPIO_ReadPin(SDMMC1_EN_GPIO_Port, SDMMC1_EN_Pin) == GPIO_PIN_RESET)&& 3875 .loc 2 1603 6 is_stmt 0 view .LVU1293 3876 000c AF4B ldr r3, .L168 3877 .LVL277: 1603:Src/main.c **** if ((HAL_GPIO_ReadPin(SDMMC1_EN_GPIO_Port, SDMMC1_EN_Pin) == GPIO_PIN_RESET)&& 3878 .loc 2 1603 6 view .LVU1294 3879 000e 0022 movs r2, #0 3880 .LVL278: 1603:Src/main.c **** if ((HAL_GPIO_ReadPin(SDMMC1_EN_GPIO_Port, SDMMC1_EN_Pin) == GPIO_PIN_RESET)&& 3881 .loc 2 1603 6 view .LVU1295 3882 0010 1A60 str r2, [r3] 1604:Src/main.c **** (HAL_GPIO_ReadPin(USB_FLAG_GPIO_Port, USB_FLAG_Pin) == GPIO_PIN_SET))//if exist sd && connect u 3883 .loc 2 1604 2 is_stmt 1 view .LVU1296 1604:Src/main.c **** (HAL_GPIO_ReadPin(USB_FLAG_GPIO_Port, USB_FLAG_Pin) == GPIO_PIN_SET))//if exist sd && connect u 3884 .loc 2 1604 7 is_stmt 0 view .LVU1297 3885 0012 0121 movs r1, #1 3886 .LVL279: 1604:Src/main.c **** (HAL_GPIO_ReadPin(USB_FLAG_GPIO_Port, USB_FLAG_Pin) == GPIO_PIN_SET))//if exist sd && connect u 3887 .loc 2 1604 7 view .LVU1298 3888 0014 AE48 ldr r0, .L168+4 3889 .LVL280: 1604:Src/main.c **** (HAL_GPIO_ReadPin(USB_FLAG_GPIO_Port, USB_FLAG_Pin) == GPIO_PIN_SET))//if exist sd && connect u 3890 .loc 2 1604 7 view .LVU1299 3891 0016 FFF7FEFF bl HAL_GPIO_ReadPin 3892 .LVL281: 1604:Src/main.c **** (HAL_GPIO_ReadPin(USB_FLAG_GPIO_Port, USB_FLAG_Pin) == GPIO_PIN_SET))//if exist sd && connect u 3893 .loc 2 1604 5 view .LVU1300 3894 001a 0028 cmp r0, #0 3895 001c 00F0D280 beq .L165 3896 .L145: 1619:Src/main.c **** Curr_setup->WORK_EN = ((uint8_t)((*temp2)>>0))&0x01; 3897 .loc 2 1619 2 is_stmt 1 view .LVU1301 3898 .LVL282: 1620:Src/main.c **** Curr_setup->U5V1_EN = ((uint8_t)((*temp2)>>1))&0x01; 3899 .loc 2 1620 2 view .LVU1302 1620:Src/main.c **** Curr_setup->U5V1_EN = ((uint8_t)((*temp2)>>1))&0x01; 3900 .loc 2 1620 36 is_stmt 0 view .LVU1303 3901 0020 2B88 ldrh r3, [r5] 1620:Src/main.c **** Curr_setup->U5V1_EN = ((uint8_t)((*temp2)>>1))&0x01; 3902 .loc 2 1620 48 view .LVU1304 3903 0022 03F00103 and r3, r3, #1 1620:Src/main.c **** Curr_setup->U5V1_EN = ((uint8_t)((*temp2)>>1))&0x01; 3904 .loc 2 1620 22 view .LVU1305 3905 0026 2370 strb r3, [r4] 1621:Src/main.c **** Curr_setup->U5V2_EN = ((uint8_t)((*temp2)>>2))&0x01; 3906 .loc 2 1621 2 is_stmt 1 view .LVU1306 1621:Src/main.c **** Curr_setup->U5V2_EN = ((uint8_t)((*temp2)>>2))&0x01; 3907 .loc 2 1621 36 is_stmt 0 view .LVU1307 3908 0028 2B88 ldrh r3, [r5] 1621:Src/main.c **** Curr_setup->U5V2_EN = ((uint8_t)((*temp2)>>2))&0x01; ARM GAS /tmp/ccdsDELB.s page 268 3909 .loc 2 1621 48 view .LVU1308 3910 002a C3F34003 ubfx r3, r3, #1, #1 1621:Src/main.c **** Curr_setup->U5V2_EN = ((uint8_t)((*temp2)>>2))&0x01; 3911 .loc 2 1621 22 view .LVU1309 3912 002e 6370 strb r3, [r4, #1] 1622:Src/main.c **** Curr_setup->LD1_EN = ((uint8_t)((*temp2)>>3))&0x01; 3913 .loc 2 1622 2 is_stmt 1 view .LVU1310 1622:Src/main.c **** Curr_setup->LD1_EN = ((uint8_t)((*temp2)>>3))&0x01; 3914 .loc 2 1622 36 is_stmt 0 view .LVU1311 3915 0030 2B88 ldrh r3, [r5] 1622:Src/main.c **** Curr_setup->LD1_EN = ((uint8_t)((*temp2)>>3))&0x01; 3916 .loc 2 1622 48 view .LVU1312 3917 0032 C3F38003 ubfx r3, r3, #2, #1 1622:Src/main.c **** Curr_setup->LD1_EN = ((uint8_t)((*temp2)>>3))&0x01; 3918 .loc 2 1622 22 view .LVU1313 3919 0036 A370 strb r3, [r4, #2] 1623:Src/main.c **** Curr_setup->LD2_EN = ((uint8_t)((*temp2)>>4))&0x01; 3920 .loc 2 1623 2 is_stmt 1 view .LVU1314 1623:Src/main.c **** Curr_setup->LD2_EN = ((uint8_t)((*temp2)>>4))&0x01; 3921 .loc 2 1623 35 is_stmt 0 view .LVU1315 3922 0038 2B88 ldrh r3, [r5] 1623:Src/main.c **** Curr_setup->LD2_EN = ((uint8_t)((*temp2)>>4))&0x01; 3923 .loc 2 1623 47 view .LVU1316 3924 003a C3F3C003 ubfx r3, r3, #3, #1 1623:Src/main.c **** Curr_setup->LD2_EN = ((uint8_t)((*temp2)>>4))&0x01; 3925 .loc 2 1623 21 view .LVU1317 3926 003e E370 strb r3, [r4, #3] 1624:Src/main.c **** Curr_setup->REF1_EN = ((uint8_t)((*temp2)>>5))&0x01; 3927 .loc 2 1624 2 is_stmt 1 view .LVU1318 1624:Src/main.c **** Curr_setup->REF1_EN = ((uint8_t)((*temp2)>>5))&0x01; 3928 .loc 2 1624 35 is_stmt 0 view .LVU1319 3929 0040 2B88 ldrh r3, [r5] 1624:Src/main.c **** Curr_setup->REF1_EN = ((uint8_t)((*temp2)>>5))&0x01; 3930 .loc 2 1624 47 view .LVU1320 3931 0042 C3F30013 ubfx r3, r3, #4, #1 1624:Src/main.c **** Curr_setup->REF1_EN = ((uint8_t)((*temp2)>>5))&0x01; 3932 .loc 2 1624 21 view .LVU1321 3933 0046 2371 strb r3, [r4, #4] 1625:Src/main.c **** Curr_setup->REF2_EN = ((uint8_t)((*temp2)>>6))&0x01; 3934 .loc 2 1625 2 is_stmt 1 view .LVU1322 1625:Src/main.c **** Curr_setup->REF2_EN = ((uint8_t)((*temp2)>>6))&0x01; 3935 .loc 2 1625 36 is_stmt 0 view .LVU1323 3936 0048 2B88 ldrh r3, [r5] 1625:Src/main.c **** Curr_setup->REF2_EN = ((uint8_t)((*temp2)>>6))&0x01; 3937 .loc 2 1625 48 view .LVU1324 3938 004a C3F34013 ubfx r3, r3, #5, #1 1625:Src/main.c **** Curr_setup->REF2_EN = ((uint8_t)((*temp2)>>6))&0x01; 3939 .loc 2 1625 22 view .LVU1325 3940 004e 6371 strb r3, [r4, #5] 1626:Src/main.c **** Curr_setup->TEC1_EN = ((uint8_t)((*temp2)>>7))&0x01; 3941 .loc 2 1626 2 is_stmt 1 view .LVU1326 1626:Src/main.c **** Curr_setup->TEC1_EN = ((uint8_t)((*temp2)>>7))&0x01; 3942 .loc 2 1626 36 is_stmt 0 view .LVU1327 3943 0050 2B88 ldrh r3, [r5] 1626:Src/main.c **** Curr_setup->TEC1_EN = ((uint8_t)((*temp2)>>7))&0x01; 3944 .loc 2 1626 48 view .LVU1328 3945 0052 C3F38013 ubfx r3, r3, #6, #1 ARM GAS /tmp/ccdsDELB.s page 269 1626:Src/main.c **** Curr_setup->TEC1_EN = ((uint8_t)((*temp2)>>7))&0x01; 3946 .loc 2 1626 22 view .LVU1329 3947 0056 A371 strb r3, [r4, #6] 1627:Src/main.c **** Curr_setup->TEC2_EN = ((uint8_t)((*temp2)>>8))&0x01; 3948 .loc 2 1627 2 is_stmt 1 view .LVU1330 1627:Src/main.c **** Curr_setup->TEC2_EN = ((uint8_t)((*temp2)>>8))&0x01; 3949 .loc 2 1627 36 is_stmt 0 view .LVU1331 3950 0058 2B88 ldrh r3, [r5] 1627:Src/main.c **** Curr_setup->TEC2_EN = ((uint8_t)((*temp2)>>8))&0x01; 3951 .loc 2 1627 48 view .LVU1332 3952 005a C3F3C013 ubfx r3, r3, #7, #1 1627:Src/main.c **** Curr_setup->TEC2_EN = ((uint8_t)((*temp2)>>8))&0x01; 3953 .loc 2 1627 22 view .LVU1333 3954 005e E371 strb r3, [r4, #7] 1628:Src/main.c **** Curr_setup->TS1_EN = ((uint8_t)((*temp2)>>9))&0x01; 3955 .loc 2 1628 2 is_stmt 1 view .LVU1334 1628:Src/main.c **** Curr_setup->TS1_EN = ((uint8_t)((*temp2)>>9))&0x01; 3956 .loc 2 1628 36 is_stmt 0 view .LVU1335 3957 0060 2B88 ldrh r3, [r5] 1628:Src/main.c **** Curr_setup->TS1_EN = ((uint8_t)((*temp2)>>9))&0x01; 3958 .loc 2 1628 48 view .LVU1336 3959 0062 C3F30023 ubfx r3, r3, #8, #1 1628:Src/main.c **** Curr_setup->TS1_EN = ((uint8_t)((*temp2)>>9))&0x01; 3960 .loc 2 1628 22 view .LVU1337 3961 0066 2372 strb r3, [r4, #8] 1629:Src/main.c **** Curr_setup->TS2_EN = ((uint8_t)((*temp2)>>10))&0x01; 3962 .loc 2 1629 2 is_stmt 1 view .LVU1338 1629:Src/main.c **** Curr_setup->TS2_EN = ((uint8_t)((*temp2)>>10))&0x01; 3963 .loc 2 1629 35 is_stmt 0 view .LVU1339 3964 0068 2B88 ldrh r3, [r5] 1629:Src/main.c **** Curr_setup->TS2_EN = ((uint8_t)((*temp2)>>10))&0x01; 3965 .loc 2 1629 47 view .LVU1340 3966 006a C3F34023 ubfx r3, r3, #9, #1 1629:Src/main.c **** Curr_setup->TS2_EN = ((uint8_t)((*temp2)>>10))&0x01; 3967 .loc 2 1629 21 view .LVU1341 3968 006e 6372 strb r3, [r4, #9] 1630:Src/main.c **** Curr_setup->SD_EN = ((uint8_t)((*temp2)>>11))&0x01; 3969 .loc 2 1630 2 is_stmt 1 view .LVU1342 1630:Src/main.c **** Curr_setup->SD_EN = ((uint8_t)((*temp2)>>11))&0x01; 3970 .loc 2 1630 35 is_stmt 0 view .LVU1343 3971 0070 2B88 ldrh r3, [r5] 1630:Src/main.c **** Curr_setup->SD_EN = ((uint8_t)((*temp2)>>11))&0x01; 3972 .loc 2 1630 48 view .LVU1344 3973 0072 C3F38023 ubfx r3, r3, #10, #1 1630:Src/main.c **** Curr_setup->SD_EN = ((uint8_t)((*temp2)>>11))&0x01; 3974 .loc 2 1630 21 view .LVU1345 3975 0076 A372 strb r3, [r4, #10] 1631:Src/main.c **** Curr_setup->PI1_RD = ((uint8_t)((*temp2)>>12))&0x01; 3976 .loc 2 1631 2 is_stmt 1 view .LVU1346 1631:Src/main.c **** Curr_setup->PI1_RD = ((uint8_t)((*temp2)>>12))&0x01; 3977 .loc 2 1631 34 is_stmt 0 view .LVU1347 3978 0078 2B88 ldrh r3, [r5] 1631:Src/main.c **** Curr_setup->PI1_RD = ((uint8_t)((*temp2)>>12))&0x01; 3979 .loc 2 1631 47 view .LVU1348 3980 007a C3F3C023 ubfx r3, r3, #11, #1 1631:Src/main.c **** Curr_setup->PI1_RD = ((uint8_t)((*temp2)>>12))&0x01; 3981 .loc 2 1631 20 view .LVU1349 ARM GAS /tmp/ccdsDELB.s page 270 3982 007e E372 strb r3, [r4, #11] 1632:Src/main.c **** Curr_setup->PI2_RD = ((uint8_t)((*temp2)>>13))&0x01; 3983 .loc 2 1632 2 is_stmt 1 view .LVU1350 1632:Src/main.c **** Curr_setup->PI2_RD = ((uint8_t)((*temp2)>>13))&0x01; 3984 .loc 2 1632 35 is_stmt 0 view .LVU1351 3985 0080 2B88 ldrh r3, [r5] 1632:Src/main.c **** Curr_setup->PI2_RD = ((uint8_t)((*temp2)>>13))&0x01; 3986 .loc 2 1632 48 view .LVU1352 3987 0082 C3F30033 ubfx r3, r3, #12, #1 1632:Src/main.c **** Curr_setup->PI2_RD = ((uint8_t)((*temp2)>>13))&0x01; 3988 .loc 2 1632 21 view .LVU1353 3989 0086 2373 strb r3, [r4, #12] 1633:Src/main.c **** 3990 .loc 2 1633 2 is_stmt 1 view .LVU1354 1633:Src/main.c **** 3991 .loc 2 1633 35 is_stmt 0 view .LVU1355 3992 0088 2B88 ldrh r3, [r5] 1633:Src/main.c **** 3993 .loc 2 1633 48 view .LVU1356 3994 008a C3F34033 ubfx r3, r3, #13, #1 1633:Src/main.c **** 3995 .loc 2 1633 21 view .LVU1357 3996 008e 6373 strb r3, [r4, #13] 1635:Src/main.c **** LD1_curr_setup->LD_TEMP = (uint16_t)(*temp2); 3997 .loc 2 1635 2 is_stmt 1 view .LVU1358 3998 .LVL283: 1636:Src/main.c **** temp2++; 3999 .loc 2 1636 2 view .LVU1359 1636:Src/main.c **** temp2++; 4000 .loc 2 1636 28 is_stmt 0 view .LVU1360 4001 0090 6B88 ldrh r3, [r5, #2] 1636:Src/main.c **** temp2++; 4002 .loc 2 1636 26 view .LVU1361 4003 0092 3B80 strh r3, [r7] @ movhi 1637:Src/main.c **** LD2_curr_setup->LD_TEMP = (uint16_t)(*temp2); 4004 .loc 2 1637 2 is_stmt 1 view .LVU1362 4005 .LVL284: 1638:Src/main.c **** temp2++; 4006 .loc 2 1638 2 view .LVU1363 1638:Src/main.c **** temp2++; 4007 .loc 2 1638 28 is_stmt 0 view .LVU1364 4008 0094 AB88 ldrh r3, [r5, #4] 1638:Src/main.c **** temp2++; 4009 .loc 2 1638 26 view .LVU1365 4010 0096 3380 strh r3, [r6] @ movhi 1639:Src/main.c **** temp2++; 4011 .loc 2 1639 2 is_stmt 1 view .LVU1366 4012 .LVL285: 1640:Src/main.c **** temp2++; 4013 .loc 2 1640 2 view .LVU1367 1641:Src/main.c **** Curr_setup->AVERAGES = (uint16_t)(*temp2); 4014 .loc 2 1641 2 view .LVU1368 1642:Src/main.c **** temp2++; 4015 .loc 2 1642 2 view .LVU1369 1642:Src/main.c **** temp2++; 4016 .loc 2 1642 25 is_stmt 0 view .LVU1370 4017 0098 6B89 ldrh r3, [r5, #10] ARM GAS /tmp/ccdsDELB.s page 271 1642:Src/main.c **** temp2++; 4018 .loc 2 1642 23 view .LVU1371 4019 009a E381 strh r3, [r4, #14] @ movhi 1643:Src/main.c **** LD1_curr_setup->P_coef_temp = (float)((uint16_t)(*temp2))/((float)(256));//(float)(1/(float)((uint 4020 .loc 2 1643 2 is_stmt 1 view .LVU1372 4021 .LVL286: 1644:Src/main.c **** temp2++; 4022 .loc 2 1644 2 view .LVU1373 1644:Src/main.c **** temp2++; 4023 .loc 2 1644 51 is_stmt 0 view .LVU1374 4024 009c AB89 ldrh r3, [r5, #12] 4025 009e 07EE103A vmov s14, r3 @ int 1644:Src/main.c **** temp2++; 4026 .loc 2 1644 32 view .LVU1375 4027 00a2 B8EE477A vcvt.f32.u32 s14, s14 1644:Src/main.c **** temp2++; 4028 .loc 2 1644 59 view .LVU1376 4029 00a6 DFED8B6A vldr.32 s13, .L168+8 4030 00aa 27EE267A vmul.f32 s14, s14, s13 1644:Src/main.c **** temp2++; 4031 .loc 2 1644 30 view .LVU1377 4032 00ae 87ED017A vstr.32 s14, [r7, #4] 1645:Src/main.c **** LD1_curr_setup->I_coef_temp = (float)((uint16_t)(*temp2))/((float)(256));//(float)(1/(float)((uint 4033 .loc 2 1645 2 is_stmt 1 view .LVU1378 4034 .LVL287: 1646:Src/main.c **** temp2++; 4035 .loc 2 1646 2 view .LVU1379 1646:Src/main.c **** temp2++; 4036 .loc 2 1646 51 is_stmt 0 view .LVU1380 4037 00b2 EB89 ldrh r3, [r5, #14] 4038 00b4 07EE103A vmov s14, r3 @ int 1646:Src/main.c **** temp2++; 4039 .loc 2 1646 32 view .LVU1381 4040 00b8 B8EE477A vcvt.f32.u32 s14, s14 1646:Src/main.c **** temp2++; 4041 .loc 2 1646 59 view .LVU1382 4042 00bc 27EE267A vmul.f32 s14, s14, s13 1646:Src/main.c **** temp2++; 4043 .loc 2 1646 30 view .LVU1383 4044 00c0 87ED027A vstr.32 s14, [r7, #8] 1647:Src/main.c **** LD2_curr_setup->P_coef_temp = (float)((uint16_t)(*temp2))/((float)(256));//(float)(1/(float)((uint 4045 .loc 2 1647 2 is_stmt 1 view .LVU1384 4046 .LVL288: 1648:Src/main.c **** temp2++; 4047 .loc 2 1648 2 view .LVU1385 1648:Src/main.c **** temp2++; 4048 .loc 2 1648 51 is_stmt 0 view .LVU1386 4049 00c4 2B8A ldrh r3, [r5, #16] 4050 00c6 07EE103A vmov s14, r3 @ int 1648:Src/main.c **** temp2++; 4051 .loc 2 1648 32 view .LVU1387 4052 00ca B8EE477A vcvt.f32.u32 s14, s14 1648:Src/main.c **** temp2++; 4053 .loc 2 1648 59 view .LVU1388 4054 00ce 27EE267A vmul.f32 s14, s14, s13 1648:Src/main.c **** temp2++; 4055 .loc 2 1648 30 view .LVU1389 ARM GAS /tmp/ccdsDELB.s page 272 4056 00d2 86ED017A vstr.32 s14, [r6, #4] 1649:Src/main.c **** LD2_curr_setup->I_coef_temp = (float)((uint16_t)(*temp2))/((float)(256));//(float)(1/(float)((uint 4057 .loc 2 1649 2 is_stmt 1 view .LVU1390 4058 .LVL289: 1650:Src/main.c **** temp2++; 4059 .loc 2 1650 2 view .LVU1391 1650:Src/main.c **** temp2++; 4060 .loc 2 1650 51 is_stmt 0 view .LVU1392 4061 00d6 6B8A ldrh r3, [r5, #18] 4062 00d8 07EE903A vmov s15, r3 @ int 1650:Src/main.c **** temp2++; 4063 .loc 2 1650 32 view .LVU1393 4064 00dc F8EE677A vcvt.f32.u32 s15, s15 1650:Src/main.c **** temp2++; 4065 .loc 2 1650 59 view .LVU1394 4066 00e0 67EEA67A vmul.f32 s15, s15, s13 1650:Src/main.c **** temp2++; 4067 .loc 2 1650 30 view .LVU1395 4068 00e4 C6ED027A vstr.32 s15, [r6, #8] 1651:Src/main.c **** Long_Data[13] = (uint16_t)(*temp2);//Message ID 4069 .loc 2 1651 2 is_stmt 1 view .LVU1396 4070 .LVL290: 1652:Src/main.c **** temp2++; 4071 .loc 2 1652 2 view .LVU1397 1652:Src/main.c **** temp2++; 4072 .loc 2 1652 18 is_stmt 0 view .LVU1398 4073 00e8 AA8A ldrh r2, [r5, #20] 1652:Src/main.c **** temp2++; 4074 .loc 2 1652 16 view .LVU1399 4075 00ea 7B4B ldr r3, .L168+12 4076 00ec 5A83 strh r2, [r3, #26] @ movhi 1653:Src/main.c **** LD1_curr_setup->CURRENT = (uint16_t)(*temp2); 4077 .loc 2 1653 2 is_stmt 1 view .LVU1400 4078 .LVL291: 1654:Src/main.c **** temp2++; 4079 .loc 2 1654 2 view .LVU1401 1654:Src/main.c **** temp2++; 4080 .loc 2 1654 28 is_stmt 0 view .LVU1402 4081 00ee EB8A ldrh r3, [r5, #22] 1654:Src/main.c **** temp2++; 4082 .loc 2 1654 26 view .LVU1403 4083 00f0 BB81 strh r3, [r7, #12] @ movhi 1655:Src/main.c **** LD2_curr_setup->CURRENT = (uint16_t)(*temp2); 4084 .loc 2 1655 2 is_stmt 1 view .LVU1404 4085 .LVL292: 1656:Src/main.c **** temp2++; 4086 .loc 2 1656 2 view .LVU1405 1656:Src/main.c **** temp2++; 4087 .loc 2 1656 28 is_stmt 0 view .LVU1406 4088 00f2 2B8B ldrh r3, [r5, #24] 1656:Src/main.c **** temp2++; 4089 .loc 2 1656 26 view .LVU1407 4090 00f4 B381 strh r3, [r6, #12] @ movhi 1657:Src/main.c **** 4091 .loc 2 1657 2 is_stmt 1 view .LVU1408 4092 .LVL293: 1659:Src/main.c **** { ARM GAS /tmp/ccdsDELB.s page 273 4093 .loc 2 1659 2 view .LVU1409 1659:Src/main.c **** { 4094 .loc 2 1659 16 is_stmt 0 view .LVU1410 4095 00f6 6378 ldrb r3, [r4, #1] @ zero_extendqisi2 1659:Src/main.c **** { 4096 .loc 2 1659 5 view .LVU1411 4097 00f8 002B cmp r3, #0 4098 00fa 00F09580 beq .L146 1661:Src/main.c **** } 4099 .loc 2 1661 3 is_stmt 1 view .LVU1412 4100 00fe 0122 movs r2, #1 4101 0100 0821 movs r1, #8 4102 0102 7648 ldr r0, .L168+16 4103 0104 FFF7FEFF bl HAL_GPIO_WritePin 4104 .LVL294: 4105 .L147: 1668:Src/main.c **** { 4106 .loc 2 1668 2 view .LVU1413 1668:Src/main.c **** { 4107 .loc 2 1668 16 is_stmt 0 view .LVU1414 4108 0108 A378 ldrb r3, [r4, #2] @ zero_extendqisi2 1668:Src/main.c **** { 4109 .loc 2 1668 5 view .LVU1415 4110 010a 002B cmp r3, #0 4111 010c 00F09280 beq .L148 1670:Src/main.c **** } 4112 .loc 2 1670 3 is_stmt 1 view .LVU1416 4113 0110 0122 movs r2, #1 4114 0112 0421 movs r1, #4 4115 0114 7148 ldr r0, .L168+16 4116 0116 FFF7FEFF bl HAL_GPIO_WritePin 4117 .LVL295: 4118 .L149: 1677:Src/main.c **** { 4119 .loc 2 1677 2 view .LVU1417 1677:Src/main.c **** { 4120 .loc 2 1677 16 is_stmt 0 view .LVU1418 4121 011a E378 ldrb r3, [r4, #3] @ zero_extendqisi2 1677:Src/main.c **** { 4122 .loc 2 1677 5 view .LVU1419 4123 011c 002B cmp r3, #0 4124 011e 00F08F80 beq .L150 1679:Src/main.c **** //LL_SPI_Enable(SPI2);//Enable SPI for Laser1 DAC 4125 .loc 2 1679 3 is_stmt 1 view .LVU1420 4126 0122 0122 movs r2, #1 4127 0124 4FF48071 mov r1, #256 4128 0128 6948 ldr r0, .L168+4 4129 012a FFF7FEFF bl HAL_GPIO_WritePin 4130 .LVL296: 4131 .L151: 1688:Src/main.c **** { 4132 .loc 2 1688 2 view .LVU1421 1688:Src/main.c **** { 4133 .loc 2 1688 16 is_stmt 0 view .LVU1422 4134 012e 2379 ldrb r3, [r4, #4] @ zero_extendqisi2 1688:Src/main.c **** { 4135 .loc 2 1688 5 view .LVU1423 ARM GAS /tmp/ccdsDELB.s page 274 4136 0130 002B cmp r3, #0 4137 0132 00F08C80 beq .L152 1690:Src/main.c **** //LL_SPI_Enable(SPI6);//Enable SPI for Laser2 DAC 4138 .loc 2 1690 3 is_stmt 1 view .LVU1424 4139 0136 0122 movs r2, #1 4140 0138 1021 movs r1, #16 4141 013a 6848 ldr r0, .L168+16 4142 013c FFF7FEFF bl HAL_GPIO_WritePin 4143 .LVL297: 4144 .L153: 1699:Src/main.c **** { 4145 .loc 2 1699 2 view .LVU1425 1699:Src/main.c **** { 4146 .loc 2 1699 16 is_stmt 0 view .LVU1426 4147 0140 6379 ldrb r3, [r4, #5] @ zero_extendqisi2 1699:Src/main.c **** { 4148 .loc 2 1699 5 view .LVU1427 4149 0142 002B cmp r3, #0 4150 0144 00F08980 beq .L154 1701:Src/main.c **** } 4151 .loc 2 1701 3 is_stmt 1 view .LVU1428 4152 0148 0122 movs r2, #1 4153 014a 4FF48061 mov r1, #1024 4154 014e 6448 ldr r0, .L168+20 4155 0150 FFF7FEFF bl HAL_GPIO_WritePin 4156 .LVL298: 4157 .L155: 1708:Src/main.c **** { 4158 .loc 2 1708 2 view .LVU1429 1708:Src/main.c **** { 4159 .loc 2 1708 16 is_stmt 0 view .LVU1430 4160 0154 A379 ldrb r3, [r4, #6] @ zero_extendqisi2 1708:Src/main.c **** { 4161 .loc 2 1708 5 view .LVU1431 4162 0156 002B cmp r3, #0 4163 0158 00F08680 beq .L156 1710:Src/main.c **** } 4164 .loc 2 1710 3 is_stmt 1 view .LVU1432 4165 015c 0122 movs r2, #1 4166 015e 0821 movs r1, #8 4167 0160 6048 ldr r0, .L168+24 4168 0162 FFF7FEFF bl HAL_GPIO_WritePin 4169 .LVL299: 4170 .L157: 1717:Src/main.c **** { 4171 .loc 2 1717 2 view .LVU1433 1717:Src/main.c **** { 4172 .loc 2 1717 17 is_stmt 0 view .LVU1434 4173 0166 637A ldrb r3, [r4, #9] @ zero_extendqisi2 1717:Src/main.c **** { 4174 .loc 2 1717 5 view .LVU1435 4175 0168 1BB1 cbz r3, .L158 1717:Src/main.c **** { 4176 .loc 2 1717 39 discriminator 1 view .LVU1436 4177 016a E379 ldrb r3, [r4, #7] @ zero_extendqisi2 1717:Src/main.c **** { 4178 .loc 2 1717 26 discriminator 1 view .LVU1437 ARM GAS /tmp/ccdsDELB.s page 275 4179 016c 002B cmp r3, #0 4180 016e 40F08180 bne .L166 4181 .L158: 1726:Src/main.c **** HAL_GPIO_WritePin(TEC1_PD_GPIO_Port, TEC1_PD_Pin, GPIO_PIN_RESET); 4182 .loc 2 1726 3 is_stmt 1 view .LVU1438 4183 0172 0022 movs r2, #0 4184 0174 0121 movs r1, #1 4185 0176 5B48 ldr r0, .L168+24 4186 0178 FFF7FEFF bl HAL_GPIO_WritePin 4187 .LVL300: 1727:Src/main.c **** } 4188 .loc 2 1727 3 view .LVU1439 4189 017c 0022 movs r2, #0 4190 017e 4FF40061 mov r1, #2048 4191 0182 5748 ldr r0, .L168+20 4192 0184 FFF7FEFF bl HAL_GPIO_WritePin 4193 .LVL301: 4194 .L159: 1730:Src/main.c **** { 4195 .loc 2 1730 2 view .LVU1440 1730:Src/main.c **** { 4196 .loc 2 1730 17 is_stmt 0 view .LVU1441 4197 0188 A37A ldrb r3, [r4, #10] @ zero_extendqisi2 1730:Src/main.c **** { 4198 .loc 2 1730 5 view .LVU1442 4199 018a 1BB1 cbz r3, .L160 1730:Src/main.c **** { 4200 .loc 2 1730 39 discriminator 1 view .LVU1443 4201 018c 237A ldrb r3, [r4, #8] @ zero_extendqisi2 1730:Src/main.c **** { 4202 .loc 2 1730 26 discriminator 1 view .LVU1444 4203 018e 002B cmp r3, #0 4204 0190 40F08680 bne .L167 4205 .L160: 1739:Src/main.c **** HAL_GPIO_WritePin(TEC2_PD_GPIO_Port, TEC2_PD_Pin, GPIO_PIN_RESET); 4206 .loc 2 1739 3 is_stmt 1 view .LVU1445 4207 0194 0022 movs r2, #0 4208 0196 0221 movs r1, #2 4209 0198 5248 ldr r0, .L168+24 4210 019a FFF7FEFF bl HAL_GPIO_WritePin 4211 .LVL302: 1740:Src/main.c **** } 4212 .loc 2 1740 3 view .LVU1446 4213 019e 0022 movs r2, #0 4214 01a0 2021 movs r1, #32 4215 01a2 4E48 ldr r0, .L168+16 4216 01a4 FFF7FEFF bl HAL_GPIO_WritePin 4217 .LVL303: 4218 .L161: 1743:Src/main.c **** { 4219 .loc 2 1743 2 view .LVU1447 1743:Src/main.c **** { 4220 .loc 2 1743 16 is_stmt 0 view .LVU1448 4221 01a8 237B ldrb r3, [r4, #12] @ zero_extendqisi2 1743:Src/main.c **** { 4222 .loc 2 1743 5 view .LVU1449 4223 01aa 1BB9 cbnz r3, .L162 ARM GAS /tmp/ccdsDELB.s page 276 1745:Src/main.c **** LD1_curr_setup->I_coef_temp = 0.01; 4224 .loc 2 1745 3 is_stmt 1 view .LVU1450 1745:Src/main.c **** LD1_curr_setup->I_coef_temp = 0.01; 4225 .loc 2 1745 31 is_stmt 0 view .LVU1451 4226 01ac 4E4B ldr r3, .L168+28 4227 01ae 7B60 str r3, [r7, #4] @ float 1746:Src/main.c **** } 4228 .loc 2 1746 3 is_stmt 1 view .LVU1452 1746:Src/main.c **** } 4229 .loc 2 1746 31 is_stmt 0 view .LVU1453 4230 01b0 4E4B ldr r3, .L168+32 4231 01b2 BB60 str r3, [r7, #8] @ float 4232 .L162: 1749:Src/main.c **** { 4233 .loc 2 1749 2 is_stmt 1 view .LVU1454 1749:Src/main.c **** { 4234 .loc 2 1749 16 is_stmt 0 view .LVU1455 4235 01b4 637B ldrb r3, [r4, #13] @ zero_extendqisi2 1749:Src/main.c **** { 4236 .loc 2 1749 5 view .LVU1456 4237 01b6 1BB9 cbnz r3, .L144 1751:Src/main.c **** LD2_curr_setup->I_coef_temp = 0.01; 4238 .loc 2 1751 3 is_stmt 1 view .LVU1457 1751:Src/main.c **** LD2_curr_setup->I_coef_temp = 0.01; 4239 .loc 2 1751 31 is_stmt 0 view .LVU1458 4240 01b8 4B4B ldr r3, .L168+28 4241 01ba 7360 str r3, [r6, #4] @ float 1752:Src/main.c **** } 4242 .loc 2 1752 3 is_stmt 1 view .LVU1459 1752:Src/main.c **** } 4243 .loc 2 1752 31 is_stmt 0 view .LVU1460 4244 01bc 4B4B ldr r3, .L168+32 4245 01be B360 str r3, [r6, #8] @ float 4246 .L144: 1754:Src/main.c **** 4247 .loc 2 1754 1 view .LVU1461 4248 01c0 BDE8F883 pop {r3, r4, r5, r6, r7, r8, r9, pc} 4249 .LVL304: 4250 .L165: 1605:Src/main.c **** { 4251 .loc 2 1605 6 discriminator 1 view .LVU1462 4252 01c4 4FF48071 mov r1, #256 4253 01c8 4648 ldr r0, .L168+24 4254 01ca FFF7FEFF bl HAL_GPIO_ReadPin 4255 .LVL305: 1604:Src/main.c **** (HAL_GPIO_ReadPin(USB_FLAG_GPIO_Port, USB_FLAG_Pin) == GPIO_PIN_SET))//if exist sd && connect u 4256 .loc 2 1604 78 discriminator 1 view .LVU1463 4257 01ce 0128 cmp r0, #1 4258 01d0 7FF426AF bne .L145 1607:Src/main.c **** if (test == 0) //0 - suc 4259 .loc 2 1607 3 is_stmt 1 view .LVU1464 1607:Src/main.c **** if (test == 0) //0 - suc 4260 .loc 2 1607 10 is_stmt 0 view .LVU1465 4261 01d4 4648 ldr r0, .L168+36 4262 01d6 FFF7FEFF bl Mount_SD 4263 .LVL306: 1607:Src/main.c **** if (test == 0) //0 - suc ARM GAS /tmp/ccdsDELB.s page 277 4264 .loc 2 1607 8 view .LVU1466 4265 01da 3C4B ldr r3, .L168 4266 01dc 1860 str r0, [r3] 1608:Src/main.c **** { 4267 .loc 2 1608 3 is_stmt 1 view .LVU1467 1608:Src/main.c **** { 4268 .loc 2 1608 6 is_stmt 0 view .LVU1468 4269 01de 0028 cmp r0, #0 4270 01e0 7FF41EAF bne .L145 1611:Src/main.c **** test = Create_File("COMMAND.TXT"); // 0 -succ 4271 .loc 2 1611 4 is_stmt 1 view .LVU1469 1611:Src/main.c **** test = Create_File("COMMAND.TXT"); // 0 -succ 4272 .loc 2 1611 11 is_stmt 0 view .LVU1470 4273 01e4 DFF80C91 ldr r9, .L168+40 4274 01e8 4846 mov r0, r9 4275 01ea FFF7FEFF bl Remove_File 4276 .LVL307: 1611:Src/main.c **** test = Create_File("COMMAND.TXT"); // 0 -succ 4277 .loc 2 1611 9 view .LVU1471 4278 01ee DFF8DC80 ldr r8, .L168 4279 01f2 C8F80000 str r0, [r8] 1612:Src/main.c **** test = Write_File_byte("COMMAND.TXT", (uint8_t *)Command, CL_8); 4280 .loc 2 1612 4 is_stmt 1 view .LVU1472 1612:Src/main.c **** test = Write_File_byte("COMMAND.TXT", (uint8_t *)Command, CL_8); 4281 .loc 2 1612 11 is_stmt 0 view .LVU1473 4282 01f6 4846 mov r0, r9 4283 01f8 FFF7FEFF bl Create_File 4284 .LVL308: 1612:Src/main.c **** test = Write_File_byte("COMMAND.TXT", (uint8_t *)Command, CL_8); 4285 .loc 2 1612 9 view .LVU1474 4286 01fc C8F80000 str r0, [r8] 1613:Src/main.c **** test = Update_File_byte("COMMAND.TXT", (uint8_t *)Command, CL_8); 4287 .loc 2 1613 4 is_stmt 1 view .LVU1475 1613:Src/main.c **** test = Update_File_byte("COMMAND.TXT", (uint8_t *)Command, CL_8); 4288 .loc 2 1613 11 is_stmt 0 view .LVU1476 4289 0200 1E22 movs r2, #30 4290 0202 2946 mov r1, r5 4291 0204 4846 mov r0, r9 4292 0206 FFF7FEFF bl Write_File_byte 4293 .LVL309: 1613:Src/main.c **** test = Update_File_byte("COMMAND.TXT", (uint8_t *)Command, CL_8); 4294 .loc 2 1613 9 view .LVU1477 4295 020a C8F80000 str r0, [r8] 1614:Src/main.c **** test = Unmount_SD("/"); // 0 - succ 4296 .loc 2 1614 4 is_stmt 1 view .LVU1478 1614:Src/main.c **** test = Unmount_SD("/"); // 0 - succ 4297 .loc 2 1614 11 is_stmt 0 view .LVU1479 4298 020e 1E22 movs r2, #30 4299 0210 2946 mov r1, r5 4300 0212 4846 mov r0, r9 4301 0214 FFF7FEFF bl Update_File_byte 4302 .LVL310: 1614:Src/main.c **** test = Unmount_SD("/"); // 0 - succ 4303 .loc 2 1614 9 view .LVU1480 4304 0218 C8F80000 str r0, [r8] 1615:Src/main.c **** } 4305 .loc 2 1615 4 is_stmt 1 view .LVU1481 ARM GAS /tmp/ccdsDELB.s page 278 1615:Src/main.c **** } 4306 .loc 2 1615 11 is_stmt 0 view .LVU1482 4307 021c 3448 ldr r0, .L168+36 4308 021e FFF7FEFF bl Unmount_SD 4309 .LVL311: 1615:Src/main.c **** } 4310 .loc 2 1615 9 view .LVU1483 4311 0222 C8F80000 str r0, [r8] 4312 0226 FBE6 b .L145 4313 .LVL312: 4314 .L146: 1665:Src/main.c **** } 4315 .loc 2 1665 3 is_stmt 1 view .LVU1484 4316 0228 0022 movs r2, #0 4317 022a 0821 movs r1, #8 4318 022c 2B48 ldr r0, .L168+16 4319 022e FFF7FEFF bl HAL_GPIO_WritePin 4320 .LVL313: 4321 0232 69E7 b .L147 4322 .L148: 1674:Src/main.c **** } 4323 .loc 2 1674 3 view .LVU1485 4324 0234 0022 movs r2, #0 4325 0236 0421 movs r1, #4 4326 0238 2848 ldr r0, .L168+16 4327 023a FFF7FEFF bl HAL_GPIO_WritePin 4328 .LVL314: 4329 023e 6CE7 b .L149 4330 .L150: 1684:Src/main.c **** //LL_SPI_Disable(SPI2);//Disable SPI for Laser1 DAC 4331 .loc 2 1684 3 view .LVU1486 4332 0240 0022 movs r2, #0 4333 0242 4FF48071 mov r1, #256 4334 0246 2248 ldr r0, .L168+4 4335 0248 FFF7FEFF bl HAL_GPIO_WritePin 4336 .LVL315: 4337 024c 6FE7 b .L151 4338 .L152: 1695:Src/main.c **** //LL_SPI_Disable(SPI6);//Disable SPI for Laser2 DAC 4339 .loc 2 1695 3 view .LVU1487 4340 024e 0022 movs r2, #0 4341 0250 1021 movs r1, #16 4342 0252 2248 ldr r0, .L168+16 4343 0254 FFF7FEFF bl HAL_GPIO_WritePin 4344 .LVL316: 4345 0258 72E7 b .L153 4346 .L154: 1705:Src/main.c **** } 4347 .loc 2 1705 3 view .LVU1488 4348 025a 0022 movs r2, #0 4349 025c 4FF48061 mov r1, #1024 4350 0260 1F48 ldr r0, .L168+20 4351 0262 FFF7FEFF bl HAL_GPIO_WritePin 4352 .LVL317: 4353 0266 75E7 b .L155 4354 .L156: 1714:Src/main.c **** } ARM GAS /tmp/ccdsDELB.s page 279 4355 .loc 2 1714 3 view .LVU1489 4356 0268 0022 movs r2, #0 4357 026a 0821 movs r1, #8 4358 026c 1D48 ldr r0, .L168+24 4359 026e FFF7FEFF bl HAL_GPIO_WritePin 4360 .LVL318: 4361 0272 78E7 b .L157 4362 .L166: 1719:Src/main.c **** Set_LTEC(3,32767); 4363 .loc 2 1719 3 view .LVU1490 4364 0274 47F6FF71 movw r1, #32767 4365 0278 0320 movs r0, #3 4366 027a FFF7FEFF bl Set_LTEC 4367 .LVL319: 1720:Src/main.c **** HAL_GPIO_WritePin(TEC1_PD_GPIO_Port, TEC1_PD_Pin, GPIO_PIN_SET); 4368 .loc 2 1720 3 view .LVU1491 4369 027e 47F6FF71 movw r1, #32767 4370 0282 0320 movs r0, #3 4371 0284 FFF7FEFF bl Set_LTEC 4372 .LVL320: 1721:Src/main.c **** HAL_GPIO_WritePin(TECEN1_GPIO_Port, TECEN1_Pin, GPIO_PIN_SET); 4373 .loc 2 1721 3 view .LVU1492 4374 0288 0122 movs r2, #1 4375 028a 4FF40061 mov r1, #2048 4376 028e 1448 ldr r0, .L168+20 4377 0290 FFF7FEFF bl HAL_GPIO_WritePin 4378 .LVL321: 1722:Src/main.c **** } 4379 .loc 2 1722 3 view .LVU1493 4380 0294 0122 movs r2, #1 4381 0296 1146 mov r1, r2 4382 0298 1248 ldr r0, .L168+24 4383 029a FFF7FEFF bl HAL_GPIO_WritePin 4384 .LVL322: 4385 029e 73E7 b .L159 4386 .L167: 1732:Src/main.c **** Set_LTEC(4,32767); 4387 .loc 2 1732 3 view .LVU1494 4388 02a0 47F6FF71 movw r1, #32767 4389 02a4 0420 movs r0, #4 4390 02a6 FFF7FEFF bl Set_LTEC 4391 .LVL323: 1733:Src/main.c **** HAL_GPIO_WritePin(TEC2_PD_GPIO_Port, TEC2_PD_Pin, GPIO_PIN_SET); 4392 .loc 2 1733 3 view .LVU1495 4393 02aa 47F6FF71 movw r1, #32767 4394 02ae 0420 movs r0, #4 4395 02b0 FFF7FEFF bl Set_LTEC 4396 .LVL324: 1734:Src/main.c **** HAL_GPIO_WritePin(TECEN2_GPIO_Port, TECEN2_Pin, GPIO_PIN_SET); 4397 .loc 2 1734 3 view .LVU1496 4398 02b4 0122 movs r2, #1 4399 02b6 2021 movs r1, #32 4400 02b8 0848 ldr r0, .L168+16 4401 02ba FFF7FEFF bl HAL_GPIO_WritePin 4402 .LVL325: 1735:Src/main.c **** } 4403 .loc 2 1735 3 view .LVU1497 ARM GAS /tmp/ccdsDELB.s page 280 4404 02be 0122 movs r2, #1 4405 02c0 0221 movs r1, #2 4406 02c2 0848 ldr r0, .L168+24 4407 02c4 FFF7FEFF bl HAL_GPIO_WritePin 4408 .LVL326: 4409 02c8 6EE7 b .L161 4410 .L169: 4411 02ca 00BF .align 2 4412 .L168: 4413 02cc 00000000 .word .LANCHOR5 4414 02d0 000C0240 .word 1073875968 4415 02d4 0000803B .word 998244352 4416 02d8 00000000 .word .LANCHOR6 4417 02dc 00080240 .word 1073874944 4418 02e0 00040240 .word 1073873920 4419 02e4 00000240 .word 1073872896 4420 02e8 00002041 .word 1092616192 4421 02ec 0AD7233C .word 1008981770 4422 02f0 00000000 .word .LC0 4423 02f4 04000000 .word .LC1 4424 .cfi_endproc 4425 .LFE1204: 4427 .section .text.Init_params,"ax",%progbits 4428 .align 1 4429 .syntax unified 4430 .thumb 4431 .thumb_func 4432 .fpu fpv5-d16 4434 Init_params: 4435 .LFB1203: 1455:Src/main.c **** TO6 = 0; 4436 .loc 2 1455 1 view -0 4437 .cfi_startproc 4438 @ args = 0, pretend = 0, frame = 0 4439 @ frame_needed = 0, uses_anonymous_args = 0 4440 0000 2DE9F041 push {r4, r5, r6, r7, r8, lr} 4441 .LCFI38: 4442 .cfi_def_cfa_offset 24 4443 .cfi_offset 4, -24 4444 .cfi_offset 5, -20 4445 .cfi_offset 6, -16 4446 .cfi_offset 7, -12 4447 .cfi_offset 8, -8 4448 .cfi_offset 14, -4 1456:Src/main.c **** TO7 = 0; 4449 .loc 2 1456 2 view .LVU1499 1456:Src/main.c **** TO7 = 0; 4450 .loc 2 1456 6 is_stmt 0 view .LVU1500 4451 0004 0023 movs r3, #0 4452 0006 9C4A ldr r2, .L182 4453 0008 1360 str r3, [r2] 1457:Src/main.c **** TO7_before = 0; 4454 .loc 2 1457 2 is_stmt 1 view .LVU1501 1457:Src/main.c **** TO7_before = 0; 4455 .loc 2 1457 6 is_stmt 0 view .LVU1502 4456 000a 9C4A ldr r2, .L182+4 4457 000c 1360 str r3, [r2] ARM GAS /tmp/ccdsDELB.s page 281 1458:Src/main.c **** TO6_before = 0; 4458 .loc 2 1458 2 is_stmt 1 view .LVU1503 1458:Src/main.c **** TO6_before = 0; 4459 .loc 2 1458 13 is_stmt 0 view .LVU1504 4460 000e 9C4A ldr r2, .L182+8 4461 0010 1360 str r3, [r2] 1459:Src/main.c **** TO6_uart = 0; 4462 .loc 2 1459 2 is_stmt 1 view .LVU1505 1459:Src/main.c **** TO6_uart = 0; 4463 .loc 2 1459 13 is_stmt 0 view .LVU1506 4464 0012 9C4A ldr r2, .L182+12 4465 0014 1360 str r3, [r2] 1460:Src/main.c **** flg_tmt = 0; 4466 .loc 2 1460 2 is_stmt 1 view .LVU1507 1460:Src/main.c **** flg_tmt = 0; 4467 .loc 2 1460 11 is_stmt 0 view .LVU1508 4468 0016 9C4A ldr r2, .L182+16 4469 0018 1360 str r3, [r2] 1461:Src/main.c **** UART_rec_incr = 0; 4470 .loc 2 1461 2 is_stmt 1 view .LVU1509 1461:Src/main.c **** UART_rec_incr = 0; 4471 .loc 2 1461 10 is_stmt 0 view .LVU1510 4472 001a 9C4A ldr r2, .L182+20 4473 001c 1370 strb r3, [r2] 1462:Src/main.c **** fgoto = 0; 4474 .loc 2 1462 2 is_stmt 1 view .LVU1511 1462:Src/main.c **** fgoto = 0; 4475 .loc 2 1462 16 is_stmt 0 view .LVU1512 4476 001e 9C4A ldr r2, .L182+24 4477 0020 1380 strh r3, [r2] @ movhi 1463:Src/main.c **** sizeoffile = 0; 4478 .loc 2 1463 2 is_stmt 1 view .LVU1513 1463:Src/main.c **** sizeoffile = 0; 4479 .loc 2 1463 8 is_stmt 0 view .LVU1514 4480 0022 9C4A ldr r2, .L182+28 4481 0024 1360 str r3, [r2] 1464:Src/main.c **** u_tx_flg = 0; 4482 .loc 2 1464 2 is_stmt 1 view .LVU1515 1464:Src/main.c **** u_tx_flg = 0; 4483 .loc 2 1464 13 is_stmt 0 view .LVU1516 4484 0026 9C4A ldr r2, .L182+32 4485 0028 1360 str r3, [r2] 1465:Src/main.c **** u_rx_flg = 0; 4486 .loc 2 1465 2 is_stmt 1 view .LVU1517 1465:Src/main.c **** u_rx_flg = 0; 4487 .loc 2 1465 11 is_stmt 0 view .LVU1518 4488 002a 9C4A ldr r2, .L182+36 4489 002c 1370 strb r3, [r2] 1466:Src/main.c **** //State_Data[0]=0; 4490 .loc 2 1466 2 is_stmt 1 view .LVU1519 1466:Src/main.c **** //State_Data[0]=0; 4491 .loc 2 1466 11 is_stmt 0 view .LVU1520 4492 002e 9C4A ldr r2, .L182+40 4493 0030 1370 strb r3, [r2] 1469:Src/main.c **** { 4494 .loc 2 1469 2 is_stmt 1 view .LVU1521 4495 .LBB456: ARM GAS /tmp/ccdsDELB.s page 282 1469:Src/main.c **** { 4496 .loc 2 1469 7 view .LVU1522 4497 .LVL327: 1469:Src/main.c **** { 4498 .loc 2 1469 2 is_stmt 0 view .LVU1523 4499 0032 05E0 b .L171 4500 .LVL328: 4501 .L172: 1471:Src/main.c **** } 4502 .loc 2 1471 3 is_stmt 1 discriminator 3 view .LVU1524 1471:Src/main.c **** } 4503 .loc 2 1471 16 is_stmt 0 discriminator 3 view .LVU1525 4504 0034 9B4A ldr r2, .L182+44 4505 0036 0021 movs r1, #0 4506 0038 22F81310 strh r1, [r2, r3, lsl #1] @ movhi 1469:Src/main.c **** { 4507 .loc 2 1469 30 is_stmt 1 discriminator 3 view .LVU1526 1469:Src/main.c **** { 4508 .loc 2 1469 31 is_stmt 0 discriminator 3 view .LVU1527 4509 003c 0133 adds r3, r3, #1 4510 .LVL329: 1469:Src/main.c **** { 4511 .loc 2 1469 31 discriminator 3 view .LVU1528 4512 003e 9BB2 uxth r3, r3 4513 .LVL330: 4514 .L171: 1469:Src/main.c **** { 4515 .loc 2 1469 21 is_stmt 1 discriminator 1 view .LVU1529 1469:Src/main.c **** { 4516 .loc 2 1469 2 is_stmt 0 discriminator 1 view .LVU1530 4517 0040 0E2B cmp r3, #14 4518 0042 F7D9 bls .L172 4519 .LBE456: 1473:Src/main.c **** 4520 .loc 2 1473 2 is_stmt 1 view .LVU1531 1473:Src/main.c **** 4521 .loc 2 1473 14 is_stmt 0 view .LVU1532 4522 0044 974B ldr r3, .L182+44 4523 .LVL331: 1473:Src/main.c **** 4524 .loc 2 1473 14 view .LVU1533 4525 0046 41F21112 movw r2, #4369 4526 004a 1A80 strh r2, [r3] @ movhi 1476:Src/main.c **** Def_setup.LD1_EN = 0; 4527 .loc 2 1476 2 is_stmt 1 view .LVU1534 1476:Src/main.c **** Def_setup.LD1_EN = 0; 4528 .loc 2 1476 21 is_stmt 0 view .LVU1535 4529 004c 964B ldr r3, .L182+48 4530 004e 0022 movs r2, #0 4531 0050 DA81 strh r2, [r3, #14] @ movhi 1477:Src/main.c **** Def_setup.LD2_EN = 0; 4532 .loc 2 1477 2 is_stmt 1 view .LVU1536 1477:Src/main.c **** Def_setup.LD2_EN = 0; 4533 .loc 2 1477 19 is_stmt 0 view .LVU1537 4534 0052 DA70 strb r2, [r3, #3] 1478:Src/main.c **** Def_setup.MES_ID = 0; 4535 .loc 2 1478 2 is_stmt 1 view .LVU1538 ARM GAS /tmp/ccdsDELB.s page 283 1478:Src/main.c **** Def_setup.MES_ID = 0; 4536 .loc 2 1478 19 is_stmt 0 view .LVU1539 4537 0054 1A71 strb r2, [r3, #4] 1479:Src/main.c **** Def_setup.PI1_RD = 0; 4538 .loc 2 1479 2 is_stmt 1 view .LVU1540 1479:Src/main.c **** Def_setup.PI1_RD = 0; 4539 .loc 2 1479 19 is_stmt 0 view .LVU1541 4540 0056 1A82 strh r2, [r3, #16] @ movhi 1480:Src/main.c **** Def_setup.PI2_RD = 0; 4541 .loc 2 1480 2 is_stmt 1 view .LVU1542 1480:Src/main.c **** Def_setup.PI2_RD = 0; 4542 .loc 2 1480 19 is_stmt 0 view .LVU1543 4543 0058 1A73 strb r2, [r3, #12] 1481:Src/main.c **** Def_setup.REF1_EN = 0; 4544 .loc 2 1481 2 is_stmt 1 view .LVU1544 1481:Src/main.c **** Def_setup.REF1_EN = 0; 4545 .loc 2 1481 19 is_stmt 0 view .LVU1545 4546 005a 5A73 strb r2, [r3, #13] 1482:Src/main.c **** Def_setup.REF2_EN = 0; 4547 .loc 2 1482 2 is_stmt 1 view .LVU1546 1482:Src/main.c **** Def_setup.REF2_EN = 0; 4548 .loc 2 1482 20 is_stmt 0 view .LVU1547 4549 005c 5A71 strb r2, [r3, #5] 1483:Src/main.c **** Def_setup.SD_EN = 0; 4550 .loc 2 1483 2 is_stmt 1 view .LVU1548 1483:Src/main.c **** Def_setup.SD_EN = 0; 4551 .loc 2 1483 20 is_stmt 0 view .LVU1549 4552 005e 9A71 strb r2, [r3, #6] 1484:Src/main.c **** Def_setup.TEC1_EN = 0; 4553 .loc 2 1484 2 is_stmt 1 view .LVU1550 1484:Src/main.c **** Def_setup.TEC1_EN = 0; 4554 .loc 2 1484 18 is_stmt 0 view .LVU1551 4555 0060 DA72 strb r2, [r3, #11] 1485:Src/main.c **** Def_setup.TEC2_EN = 0; 4556 .loc 2 1485 2 is_stmt 1 view .LVU1552 1485:Src/main.c **** Def_setup.TEC2_EN = 0; 4557 .loc 2 1485 20 is_stmt 0 view .LVU1553 4558 0062 DA71 strb r2, [r3, #7] 1486:Src/main.c **** Def_setup.TS1_EN = 0; 4559 .loc 2 1486 2 is_stmt 1 view .LVU1554 1486:Src/main.c **** Def_setup.TS1_EN = 0; 4560 .loc 2 1486 20 is_stmt 0 view .LVU1555 4561 0064 1A72 strb r2, [r3, #8] 1487:Src/main.c **** Def_setup.TS2_EN = 0; 4562 .loc 2 1487 2 is_stmt 1 view .LVU1556 1487:Src/main.c **** Def_setup.TS2_EN = 0; 4563 .loc 2 1487 19 is_stmt 0 view .LVU1557 4564 0066 5A72 strb r2, [r3, #9] 1488:Src/main.c **** Def_setup.U5V1_EN = 0; 4565 .loc 2 1488 2 is_stmt 1 view .LVU1558 1488:Src/main.c **** Def_setup.U5V1_EN = 0; 4566 .loc 2 1488 19 is_stmt 0 view .LVU1559 4567 0068 9A72 strb r2, [r3, #10] 1489:Src/main.c **** Def_setup.U5V2_EN = 0; 4568 .loc 2 1489 2 is_stmt 1 view .LVU1560 1489:Src/main.c **** Def_setup.U5V2_EN = 0; 4569 .loc 2 1489 20 is_stmt 0 view .LVU1561 ARM GAS /tmp/ccdsDELB.s page 284 4570 006a 5A70 strb r2, [r3, #1] 1490:Src/main.c **** Def_setup.WORK_EN = 0; 4571 .loc 2 1490 2 is_stmt 1 view .LVU1562 1490:Src/main.c **** Def_setup.WORK_EN = 0; 4572 .loc 2 1490 20 is_stmt 0 view .LVU1563 4573 006c 9A70 strb r2, [r3, #2] 1491:Src/main.c **** 4574 .loc 2 1491 2 is_stmt 1 view .LVU1564 1491:Src/main.c **** 4575 .loc 2 1491 20 is_stmt 0 view .LVU1565 4576 006e 1A70 strb r2, [r3] 1493:Src/main.c **** LD2_def_setup.LD_TEMP = 0; 4577 .loc 2 1493 2 is_stmt 1 view .LVU1566 1493:Src/main.c **** LD2_def_setup.LD_TEMP = 0; 4578 .loc 2 1493 24 is_stmt 0 view .LVU1567 4579 0070 8E4D ldr r5, .L182+52 4580 0072 2A80 strh r2, [r5] @ movhi 1494:Src/main.c **** LD1_def_setup.P_coef_temp = 0; 4581 .loc 2 1494 2 is_stmt 1 view .LVU1568 1494:Src/main.c **** LD1_def_setup.P_coef_temp = 0; 4582 .loc 2 1494 24 is_stmt 0 view .LVU1569 4583 0074 8E4C ldr r4, .L182+56 4584 0076 2280 strh r2, [r4] @ movhi 1495:Src/main.c **** LD2_def_setup.P_coef_temp = 0; 4585 .loc 2 1495 2 is_stmt 1 view .LVU1570 1495:Src/main.c **** LD2_def_setup.P_coef_temp = 0; 4586 .loc 2 1495 28 is_stmt 0 view .LVU1571 4587 0078 0022 movs r2, #0 4588 007a 6A60 str r2, [r5, #4] @ float 1496:Src/main.c **** LD1_def_setup.I_coef_temp = 0; 4589 .loc 2 1496 2 is_stmt 1 view .LVU1572 1496:Src/main.c **** LD1_def_setup.I_coef_temp = 0; 4590 .loc 2 1496 28 is_stmt 0 view .LVU1573 4591 007c 6260 str r2, [r4, #4] @ float 1497:Src/main.c **** LD2_def_setup.I_coef_temp = 0; 4592 .loc 2 1497 2 is_stmt 1 view .LVU1574 1497:Src/main.c **** LD2_def_setup.I_coef_temp = 0; 4593 .loc 2 1497 28 is_stmt 0 view .LVU1575 4594 007e AA60 str r2, [r5, #8] @ float 1498:Src/main.c **** 4595 .loc 2 1498 2 is_stmt 1 view .LVU1576 1498:Src/main.c **** 4596 .loc 2 1498 28 is_stmt 0 view .LVU1577 4597 0080 A260 str r2, [r4, #8] @ float 1501:Src/main.c **** LD1_curr_setup = LD1_def_setup; 4598 .loc 2 1501 2 is_stmt 1 view .LVU1578 1501:Src/main.c **** LD1_curr_setup = LD1_def_setup; 4599 .loc 2 1501 13 is_stmt 0 view .LVU1579 4600 0082 8C4E ldr r6, .L182+60 4601 0084 9C46 mov ip, r3 4602 0086 BCE80F00 ldmia ip!, {r0, r1, r2, r3} 4603 008a 0FC6 stmia r6!, {r0, r1, r2, r3} 4604 008c DCF80030 ldr r3, [ip] 4605 0090 3380 strh r3, [r6] @ movhi 1502:Src/main.c **** LD2_curr_setup = LD2_def_setup; 4606 .loc 2 1502 2 is_stmt 1 view .LVU1580 1502:Src/main.c **** LD2_curr_setup = LD2_def_setup; ARM GAS /tmp/ccdsDELB.s page 285 4607 .loc 2 1502 17 is_stmt 0 view .LVU1581 4608 0092 894E ldr r6, .L182+64 4609 0094 95E80F00 ldm r5, {r0, r1, r2, r3} 4610 0098 86E80F00 stm r6, {r0, r1, r2, r3} 1503:Src/main.c **** 4611 .loc 2 1503 2 is_stmt 1 view .LVU1582 1503:Src/main.c **** 4612 .loc 2 1503 17 is_stmt 0 view .LVU1583 4613 009c 874D ldr r5, .L182+68 4614 009e 94E80F00 ldm r4, {r0, r1, r2, r3} 4615 00a2 85E80F00 stm r5, {r0, r1, r2, r3} 1508:Src/main.c **** LL_TIM_EnableCounter(TIM6); 4616 .loc 2 1508 2 is_stmt 1 view .LVU1584 4617 .LVL332: 4618 .LBB457: 4619 .LBI457: 3238:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3239:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3240:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3241:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Indicates whether the Master/Slave mode is enabled. 3242:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not 3243:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * a timer instance can operate as a slave timer. 3244:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SMCR MSM LL_TIM_IsEnabledMasterSlaveMode 3245:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3246:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval State of bit (1 or 0). 3247:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3248:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsEnabledMasterSlaveMode(const TIM_TypeDef *TIMx) 3249:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3250:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return ((READ_BIT(TIMx->SMCR, TIM_SMCR_MSM) == (TIM_SMCR_MSM)) ? 1UL : 0UL); 3251:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3252:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3253:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3254:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Configure the external trigger (ETR) input. 3255:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_ETR_INSTANCE(TIMx) can be used to check whether or not 3256:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * a timer instance provides an external trigger input. 3257:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SMCR ETP LL_TIM_ConfigETR\n 3258:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * SMCR ETPS LL_TIM_ConfigETR\n 3259:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * SMCR ETF LL_TIM_ConfigETR 3260:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3261:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param ETRPolarity This parameter can be one of the following values: 3262:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ETR_POLARITY_NONINVERTED 3263:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ETR_POLARITY_INVERTED 3264:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param ETRPrescaler This parameter can be one of the following values: 3265:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ETR_PRESCALER_DIV1 3266:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ETR_PRESCALER_DIV2 3267:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ETR_PRESCALER_DIV4 3268:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ETR_PRESCALER_DIV8 3269:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param ETRFilter This parameter can be one of the following values: 3270:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ETR_FILTER_FDIV1 3271:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N2 3272:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N4 3273:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N8 3274:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ETR_FILTER_FDIV2_N6 3275:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ETR_FILTER_FDIV2_N8 3276:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ETR_FILTER_FDIV4_N6 3277:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ETR_FILTER_FDIV4_N8 3278:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ETR_FILTER_FDIV8_N6 ARM GAS /tmp/ccdsDELB.s page 286 3279:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ETR_FILTER_FDIV8_N8 3280:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N5 3281:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N6 3282:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N8 3283:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N5 3284:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N6 3285:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N8 3286:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 3287:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3288:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_ConfigETR(TIM_TypeDef *TIMx, uint32_t ETRPolarity, uint32_t ETRPrescale 3289:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t ETRFilter) 3290:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3291:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(TIMx->SMCR, TIM_SMCR_ETP | TIM_SMCR_ETPS | TIM_SMCR_ETF, ETRPolarity | ETRPrescaler | 3292:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3293:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3294:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3295:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} 3296:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3298:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EF_Break_Function Break function configuration 3299:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ 3300:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3301:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3302:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Enable the break function. 3303:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not 3304:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * a timer instance provides a break input. 3305:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll BDTR BKE LL_TIM_EnableBRK 3306:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3307:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 3308:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3309:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_EnableBRK(TIM_TypeDef *TIMx) 3310:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3311:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** SET_BIT(TIMx->BDTR, TIM_BDTR_BKE); 3312:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3313:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Disable the break function. 3316:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll BDTR BKE LL_TIM_DisableBRK 3317:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3318:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not 3319:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * a timer instance provides a break input. 3320:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 3321:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3322:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_DisableBRK(TIM_TypeDef *TIMx) 3323:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3324:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BKE); 3325:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3326:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3327:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3328:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Configure the break input. 3329:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not 3330:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * a timer instance provides a break input. 3331:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll BDTR BKP LL_TIM_ConfigBRK\n 3332:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * BDTR BKF LL_TIM_ConfigBRK 3333:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3334:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param BreakPolarity This parameter can be one of the following values: 3335:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK_POLARITY_LOW ARM GAS /tmp/ccdsDELB.s page 287 3336:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK_POLARITY_HIGH 3337:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param BreakFilter This parameter can be one of the following values: 3338:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK_FILTER_FDIV1 3339:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N2 3340:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N4 3341:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N8 3342:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N6 3343:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N8 3344:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N6 3345:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N8 3346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N6 3347:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N8 3348:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N5 3349:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N6 3350:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N8 3351:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N5 3352:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N6 3353:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N8 3354:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 3355:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3356:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_ConfigBRK(TIM_TypeDef *TIMx, uint32_t BreakPolarity, 3357:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t BreakFilter) 3358:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3359:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(TIMx->BDTR, TIM_BDTR_BKP | TIM_BDTR_BKF, BreakPolarity | BreakFilter); 3360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3361:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3362:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3363:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Enable the break 2 function. 3364:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not 3365:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * a timer instance provides a second break input. 3366:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll BDTR BK2E LL_TIM_EnableBRK2 3367:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3368:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 3369:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_EnableBRK2(TIM_TypeDef *TIMx) 3371:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** SET_BIT(TIMx->BDTR, TIM_BDTR_BK2E); 3373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3374:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3375:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3376:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Disable the break 2 function. 3377:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not 3378:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * a timer instance provides a second break input. 3379:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll BDTR BK2E LL_TIM_DisableBRK2 3380:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3381:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 3382:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3383:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_DisableBRK2(TIM_TypeDef *TIMx) 3384:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3385:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BK2E); 3386:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3387:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3388:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3389:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Configure the break 2 input. 3390:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not 3391:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * a timer instance provides a second break input. 3392:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll BDTR BK2P LL_TIM_ConfigBRK2\n ARM GAS /tmp/ccdsDELB.s page 288 3393:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * BDTR BK2F LL_TIM_ConfigBRK2 3394:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3395:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Break2Polarity This parameter can be one of the following values: 3396:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK2_POLARITY_LOW 3397:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK2_POLARITY_HIGH 3398:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Break2Filter This parameter can be one of the following values: 3399:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1 3400:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N2 3401:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N4 3402:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N8 3403:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N6 3404:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N8 3405:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N6 3406:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N8 3407:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N6 3408:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N8 3409:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N5 3410:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N6 3411:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N8 3412:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N5 3413:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N6 3414:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N8 3415:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 3416:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3417:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_ConfigBRK2(TIM_TypeDef *TIMx, uint32_t Break2Polarity, uint32_t Break2F 3418:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3419:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(TIMx->BDTR, TIM_BDTR_BK2P | TIM_BDTR_BK2F, Break2Polarity | Break2Filter); 3420:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3421:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3422:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3423:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Select the outputs off state (enabled v.s. disabled) in Idle and Run modes. 3424:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not 3425:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * a timer instance provides a break input. 3426:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll BDTR OSSI LL_TIM_SetOffStates\n 3427:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * BDTR OSSR LL_TIM_SetOffStates 3428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3429:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param OffStateIdle This parameter can be one of the following values: 3430:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OSSI_DISABLE 3431:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OSSI_ENABLE 3432:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param OffStateRun This parameter can be one of the following values: 3433:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OSSR_DISABLE 3434:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OSSR_ENABLE 3435:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 3436:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3437:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_SetOffStates(TIM_TypeDef *TIMx, uint32_t OffStateIdle, uint32_t OffStat 3438:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3439:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(TIMx->BDTR, TIM_BDTR_OSSI | TIM_BDTR_OSSR, OffStateIdle | OffStateRun); 3440:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3441:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3442:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3443:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Enable automatic output (MOE can be set by software or automatically when a break input 3444:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not 3445:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * a timer instance provides a break input. 3446:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll BDTR AOE LL_TIM_EnableAutomaticOutput 3447:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3448:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 3449:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ ARM GAS /tmp/ccdsDELB.s page 289 3450:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_EnableAutomaticOutput(TIM_TypeDef *TIMx) 3451:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3452:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** SET_BIT(TIMx->BDTR, TIM_BDTR_AOE); 3453:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3454:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3455:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3456:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Disable automatic output (MOE can be set only by software). 3457:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not 3458:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * a timer instance provides a break input. 3459:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll BDTR AOE LL_TIM_DisableAutomaticOutput 3460:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3461:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 3462:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_DisableAutomaticOutput(TIM_TypeDef *TIMx) 3464:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3465:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** CLEAR_BIT(TIMx->BDTR, TIM_BDTR_AOE); 3466:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3467:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3468:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3469:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Indicate whether automatic output is enabled. 3470:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not 3471:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * a timer instance provides a break input. 3472:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll BDTR AOE LL_TIM_IsEnabledAutomaticOutput 3473:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3474:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval State of bit (1 or 0). 3475:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3476:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsEnabledAutomaticOutput(const TIM_TypeDef *TIMx) 3477:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3478:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return ((READ_BIT(TIMx->BDTR, TIM_BDTR_AOE) == (TIM_BDTR_AOE)) ? 1UL : 0UL); 3479:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3480:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3481:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3482:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Enable the outputs (set the MOE bit in TIMx_BDTR register). 3483:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by 3484:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * software and is reset in case of break or break2 event 3485:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not 3486:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * a timer instance provides a break input. 3487:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll BDTR MOE LL_TIM_EnableAllOutputs 3488:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3489:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 3490:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3491:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_EnableAllOutputs(TIM_TypeDef *TIMx) 3492:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3493:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** SET_BIT(TIMx->BDTR, TIM_BDTR_MOE); 3494:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3495:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3496:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3497:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Disable the outputs (reset the MOE bit in TIMx_BDTR register). 3498:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by 3499:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * software and is reset in case of break or break2 event. 3500:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not 3501:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * a timer instance provides a break input. 3502:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll BDTR MOE LL_TIM_DisableAllOutputs 3503:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3504:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 3505:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3506:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_DisableAllOutputs(TIM_TypeDef *TIMx) ARM GAS /tmp/ccdsDELB.s page 290 3507:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3508:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** CLEAR_BIT(TIMx->BDTR, TIM_BDTR_MOE); 3509:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3510:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3511:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3512:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Indicates whether outputs are enabled. 3513:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not 3514:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * a timer instance provides a break input. 3515:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll BDTR MOE LL_TIM_IsEnabledAllOutputs 3516:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3517:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval State of bit (1 or 0). 3518:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3519:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsEnabledAllOutputs(const TIM_TypeDef *TIMx) 3520:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3521:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return ((READ_BIT(TIMx->BDTR, TIM_BDTR_MOE) == (TIM_BDTR_MOE)) ? 1UL : 0UL); 3522:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3523:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3524:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #if defined(TIM_BREAK_INPUT_SUPPORT) 3525:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3526:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Enable the signals connected to the designated timer break input. 3527:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether 3528:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * or not a timer instance allows for break input selection. 3529:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll AF1 BKINE LL_TIM_EnableBreakInputSource\n 3530:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * AF1 BKDFBKE LL_TIM_EnableBreakInputSource\n 3531:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * AF2 BK2INE LL_TIM_EnableBreakInputSource\n 3532:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * AF2 BK2DFBKE LL_TIM_EnableBreakInputSource 3533:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3534:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param BreakInput This parameter can be one of the following values: 3535:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK_INPUT_BKIN 3536:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK_INPUT_BKIN2 3537:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Source This parameter can be one of the following values: 3538:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BKIN_SOURCE_BKIN 3539:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BKIN_SOURCE_DF1BK 3540:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 3541:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3542:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_EnableBreakInputSource(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t 3543:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3544:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput)); 3545:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** SET_BIT(*pReg, Source); 3546:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3547:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3548:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3549:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Disable the signals connected to the designated timer break input. 3550:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether 3551:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * or not a timer instance allows for break input selection. 3552:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll AF1 BKINE LL_TIM_DisableBreakInputSource\n 3553:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * AF1 BKDFBKE LL_TIM_DisableBreakInputSource\n 3554:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * AF2 BK2INE LL_TIM_DisableBreakInputSource\n 3555:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * AF2 BK2DFBKE LL_TIM_DisableBreakInputSource 3556:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3557:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param BreakInput This parameter can be one of the following values: 3558:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK_INPUT_BKIN 3559:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK_INPUT_BKIN2 3560:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Source This parameter can be one of the following values: 3561:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BKIN_SOURCE_BKIN 3562:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BKIN_SOURCE_DF1BK 3563:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None ARM GAS /tmp/ccdsDELB.s page 291 3564:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3565:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_DisableBreakInputSource(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_ 3566:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3567:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput)); 3568:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** CLEAR_BIT(*pReg, Source); 3569:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3570:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3571:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3572:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Set the polarity of the break signal for the timer break input. 3573:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether 3574:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * or not a timer instance allows for break input selection. 3575:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll AF1 BKINP LL_TIM_SetBreakInputSourcePolarity\n 3576:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * AF1 BKDFBKP LL_TIM_SetBreakInputSourcePolarity\n 3577:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * AF2 BK2INP LL_TIM_SetBreakInputSourcePolarity\n 3578:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * AF2 BK2DFBKP LL_TIM_SetBreakInputSourcePolarity 3579:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3580:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param BreakInput This parameter can be one of the following values: 3581:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK_INPUT_BKIN 3582:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK_INPUT_BKIN2 3583:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Source This parameter can be one of the following values: 3584:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BKIN_SOURCE_BKIN 3585:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BKIN_SOURCE_DF1BK 3586:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Polarity This parameter can be one of the following values: 3587:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BKIN_POLARITY_LOW 3588:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BKIN_POLARITY_HIGH 3589:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 3590:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3591:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_SetBreakInputSourcePolarity(TIM_TypeDef *TIMx, uint32_t BreakInput, uin 3592:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t Polarity) 3593:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3594:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput)); 3595:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(*pReg, (TIMx_AF1_BKINP << TIM_POSITION_BRK_SOURCE), (Polarity << TIM_POSITION_BRK_SOUR 3596:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3597:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #endif /* TIM_BREAK_INPUT_SUPPORT */ 3598:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3599:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} 3600:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3601:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3602:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EF_DMA_Burst_Mode DMA burst mode configuration 3603:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ 3604:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3605:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3606:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Configures the timer DMA burst feature. 3607:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_DMABURST_INSTANCE(TIMx) can be used to check whether or 3608:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * not a timer instance supports the DMA burst mode. 3609:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll DCR DBL LL_TIM_ConfigDMABurst\n 3610:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * DCR DBA LL_TIM_ConfigDMABurst 3611:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3612:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param DMABurstBaseAddress This parameter can be one of the following values: 3613:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_BASEADDR_CR1 3614:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_BASEADDR_CR2 3615:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_BASEADDR_SMCR 3616:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_BASEADDR_DIER 3617:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_BASEADDR_SR 3618:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_BASEADDR_EGR 3619:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR1 3620:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR2 ARM GAS /tmp/ccdsDELB.s page 292 3621:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_BASEADDR_CCER 3622:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_BASEADDR_CNT 3623:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_BASEADDR_PSC 3624:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_BASEADDR_ARR 3625:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_BASEADDR_RCR 3626:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR1 3627:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR2 3628:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR3 3629:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR4 3630:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_BASEADDR_BDTR 3631:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_BASEADDR_OR 3632:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR3 3633:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR5 3634:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR6 3635:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_BASEADDR_AF1 (*) 3636:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_BASEADDR_AF2 (*) 3637:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * (*) value not defined in all devices 3638:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param DMABurstLength This parameter can be one of the following values: 3639:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_LENGTH_1TRANSFER 3640:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_LENGTH_2TRANSFERS 3641:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_LENGTH_3TRANSFERS 3642:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_LENGTH_4TRANSFERS 3643:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_LENGTH_5TRANSFERS 3644:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_LENGTH_6TRANSFERS 3645:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_LENGTH_7TRANSFERS 3646:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_LENGTH_8TRANSFERS 3647:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_LENGTH_9TRANSFERS 3648:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_LENGTH_10TRANSFERS 3649:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_LENGTH_11TRANSFERS 3650:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_LENGTH_12TRANSFERS 3651:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_LENGTH_13TRANSFERS 3652:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_LENGTH_14TRANSFERS 3653:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_LENGTH_15TRANSFERS 3654:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_LENGTH_16TRANSFERS 3655:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_LENGTH_17TRANSFERS 3656:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_LENGTH_18TRANSFERS 3657:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 3658:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3659:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_ConfigDMABurst(TIM_TypeDef *TIMx, uint32_t DMABurstBaseAddress, uint32_ 3660:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3661:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(TIMx->DCR, (TIM_DCR_DBL | TIM_DCR_DBA), (DMABurstBaseAddress | DMABurstLength)); 3662:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3663:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3664:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3665:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} 3666:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3667:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3668:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EF_Timer_Inputs_Remapping Timer input remapping 3669:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ 3670:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3671:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3672:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Remap TIM inputs (input channel, internal/external triggers). 3673:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_REMAP_INSTANCE(TIMx) can be used to check whether or not 3674:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * a some timer inputs can be remapped. 3675:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll TIM2_OR ITR1_RMP LL_TIM_SetRemap\n 3676:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * TIM5_OR TI4_RMP LL_TIM_SetRemap\n 3677:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * TIM11_OR TI1_RMP LL_TIM_SetRemap ARM GAS /tmp/ccdsDELB.s page 293 3678:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3679:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Remap Remap param depends on the TIMx. Description available only 3680:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * in CHM version of the User Manual (not in .pdf). 3681:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * Otherwise see Reference Manual description of OR registers. 3682:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * 3683:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * Below description summarizes "Timer Instance" and "Remap" param combinations: 3684:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * 3685:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * TIM2: one of the following values 3686:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * 3687:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * ITR1_RMP can be one of the following values 3688:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TIM2_ITR1_RMP_TIM8_TRGO 3689:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TIM2_ITR1_RMP_ETH_PTP 3690:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TIM2_ITR1_RMP_OTG_FS_SOF 3691:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TIM2_ITR1_RMP_OTG_HS_SOF 3692:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * 3693:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * TIM5: one of the following values 3694:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * 3695:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TIM5_TI4_RMP_GPIO 3696:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TIM5_TI4_RMP_LSI 3697:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TIM5_TI4_RMP_LSE 3698:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TIM5_TI4_RMP_RTC 3699:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * 3700:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * TIM11: one of the following values 3701:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * 3702:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TIM11_TI1_RMP_GPIO 3703:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TIM11_TI1_RMP_SPDIFRX 3704:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TIM11_TI1_RMP_HSE 3705:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TIM11_TI1_RMP_MCO1 3706:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * 3707:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 3708:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3709:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_SetRemap(TIM_TypeDef *TIMx, uint32_t Remap) 3710:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3711:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(TIMx->OR, (Remap >> TIMx_OR_RMP_SHIFT), (Remap & TIMx_OR_RMP_MASK)); 3712:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3713:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3714:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3715:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} 3716:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3717:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3718:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EF_FLAG_Management FLAG-Management 3719:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ 3720:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3721:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3722:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Clear the update interrupt flag (UIF). 3723:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SR UIF LL_TIM_ClearFlag_UPDATE 3724:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3725:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 3726:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3727:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_ClearFlag_UPDATE(TIM_TypeDef *TIMx) 3728:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3729:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** WRITE_REG(TIMx->SR, ~(TIM_SR_UIF)); 3730:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3731:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3732:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3733:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Indicate whether update interrupt flag (UIF) is set (update interrupt is pending). 3734:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SR UIF LL_TIM_IsActiveFlag_UPDATE ARM GAS /tmp/ccdsDELB.s page 294 3735:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3736:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval State of bit (1 or 0). 3737:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3738:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_UPDATE(const TIM_TypeDef *TIMx) 3739:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3740:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return ((READ_BIT(TIMx->SR, TIM_SR_UIF) == (TIM_SR_UIF)) ? 1UL : 0UL); 3741:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3742:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3743:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3744:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Clear the Capture/Compare 1 interrupt flag (CC1F). 3745:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SR CC1IF LL_TIM_ClearFlag_CC1 3746:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3747:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 3748:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3749:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_ClearFlag_CC1(TIM_TypeDef *TIMx) 3750:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3751:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** WRITE_REG(TIMx->SR, ~(TIM_SR_CC1IF)); 3752:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3753:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3754:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3755:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Indicate whether Capture/Compare 1 interrupt flag (CC1F) is set (Capture/Compare 1 inte 3756:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SR CC1IF LL_TIM_IsActiveFlag_CC1 3757:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3758:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval State of bit (1 or 0). 3759:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3760:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1(const TIM_TypeDef *TIMx) 3761:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3762:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return ((READ_BIT(TIMx->SR, TIM_SR_CC1IF) == (TIM_SR_CC1IF)) ? 1UL : 0UL); 3763:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3764:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3765:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3766:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Clear the Capture/Compare 2 interrupt flag (CC2F). 3767:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SR CC2IF LL_TIM_ClearFlag_CC2 3768:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3769:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 3770:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3771:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_ClearFlag_CC2(TIM_TypeDef *TIMx) 3772:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3773:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** WRITE_REG(TIMx->SR, ~(TIM_SR_CC2IF)); 3774:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3775:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3776:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3777:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Indicate whether Capture/Compare 2 interrupt flag (CC2F) is set (Capture/Compare 2 inte 3778:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SR CC2IF LL_TIM_IsActiveFlag_CC2 3779:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3780:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval State of bit (1 or 0). 3781:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3782:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2(const TIM_TypeDef *TIMx) 3783:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3784:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return ((READ_BIT(TIMx->SR, TIM_SR_CC2IF) == (TIM_SR_CC2IF)) ? 1UL : 0UL); 3785:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3786:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3787:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3788:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Clear the Capture/Compare 3 interrupt flag (CC3F). 3789:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SR CC3IF LL_TIM_ClearFlag_CC3 3790:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3791:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None ARM GAS /tmp/ccdsDELB.s page 295 3792:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3793:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_ClearFlag_CC3(TIM_TypeDef *TIMx) 3794:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3795:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** WRITE_REG(TIMx->SR, ~(TIM_SR_CC3IF)); 3796:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3797:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3798:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3799:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Indicate whether Capture/Compare 3 interrupt flag (CC3F) is set (Capture/Compare 3 inte 3800:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SR CC3IF LL_TIM_IsActiveFlag_CC3 3801:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3802:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval State of bit (1 or 0). 3803:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3804:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3(const TIM_TypeDef *TIMx) 3805:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3806:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return ((READ_BIT(TIMx->SR, TIM_SR_CC3IF) == (TIM_SR_CC3IF)) ? 1UL : 0UL); 3807:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3808:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3809:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3810:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Clear the Capture/Compare 4 interrupt flag (CC4F). 3811:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SR CC4IF LL_TIM_ClearFlag_CC4 3812:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3813:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 3814:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3815:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_ClearFlag_CC4(TIM_TypeDef *TIMx) 3816:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3817:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** WRITE_REG(TIMx->SR, ~(TIM_SR_CC4IF)); 3818:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3819:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3820:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3821:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Indicate whether Capture/Compare 4 interrupt flag (CC4F) is set (Capture/Compare 4 inte 3822:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SR CC4IF LL_TIM_IsActiveFlag_CC4 3823:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3824:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval State of bit (1 or 0). 3825:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3826:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4(const TIM_TypeDef *TIMx) 3827:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3828:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return ((READ_BIT(TIMx->SR, TIM_SR_CC4IF) == (TIM_SR_CC4IF)) ? 1UL : 0UL); 3829:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3830:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3831:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3832:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Clear the Capture/Compare 5 interrupt flag (CC5F). 3833:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SR CC5IF LL_TIM_ClearFlag_CC5 3834:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3835:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 3836:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3837:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_ClearFlag_CC5(TIM_TypeDef *TIMx) 3838:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3839:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** WRITE_REG(TIMx->SR, ~(TIM_SR_CC5IF)); 3840:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3841:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3842:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3843:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Indicate whether Capture/Compare 5 interrupt flag (CC5F) is set (Capture/Compare 5 inte 3844:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SR CC5IF LL_TIM_IsActiveFlag_CC5 3845:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3846:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval State of bit (1 or 0). 3847:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3848:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC5(const TIM_TypeDef *TIMx) ARM GAS /tmp/ccdsDELB.s page 296 3849:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3850:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return ((READ_BIT(TIMx->SR, TIM_SR_CC5IF) == (TIM_SR_CC5IF)) ? 1UL : 0UL); 3851:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3852:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3853:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3854:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Clear the Capture/Compare 6 interrupt flag (CC6F). 3855:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SR CC6IF LL_TIM_ClearFlag_CC6 3856:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3857:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 3858:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3859:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_ClearFlag_CC6(TIM_TypeDef *TIMx) 3860:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3861:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** WRITE_REG(TIMx->SR, ~(TIM_SR_CC6IF)); 3862:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3863:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3864:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3865:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Indicate whether Capture/Compare 6 interrupt flag (CC6F) is set (Capture/Compare 6 inte 3866:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SR CC6IF LL_TIM_IsActiveFlag_CC6 3867:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3868:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval State of bit (1 or 0). 3869:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3870:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC6(const TIM_TypeDef *TIMx) 3871:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3872:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return ((READ_BIT(TIMx->SR, TIM_SR_CC6IF) == (TIM_SR_CC6IF)) ? 1UL : 0UL); 3873:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3874:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3875:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3876:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Clear the commutation interrupt flag (COMIF). 3877:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SR COMIF LL_TIM_ClearFlag_COM 3878:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3879:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 3880:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3881:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_ClearFlag_COM(TIM_TypeDef *TIMx) 3882:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3883:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** WRITE_REG(TIMx->SR, ~(TIM_SR_COMIF)); 3884:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3885:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3886:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3887:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Indicate whether commutation interrupt flag (COMIF) is set (commutation interrupt is pe 3888:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SR COMIF LL_TIM_IsActiveFlag_COM 3889:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3890:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval State of bit (1 or 0). 3891:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3892:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_COM(const TIM_TypeDef *TIMx) 3893:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3894:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return ((READ_BIT(TIMx->SR, TIM_SR_COMIF) == (TIM_SR_COMIF)) ? 1UL : 0UL); 3895:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3896:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3897:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3898:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Clear the trigger interrupt flag (TIF). 3899:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SR TIF LL_TIM_ClearFlag_TRIG 3900:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3901:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 3902:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3903:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_ClearFlag_TRIG(TIM_TypeDef *TIMx) 3904:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3905:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** WRITE_REG(TIMx->SR, ~(TIM_SR_TIF)); ARM GAS /tmp/ccdsDELB.s page 297 3906:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3908:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3909:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Indicate whether trigger interrupt flag (TIF) is set (trigger interrupt is pending). 3910:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SR TIF LL_TIM_IsActiveFlag_TRIG 3911:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3912:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval State of bit (1 or 0). 3913:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3914:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_TRIG(const TIM_TypeDef *TIMx) 3915:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3916:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return ((READ_BIT(TIMx->SR, TIM_SR_TIF) == (TIM_SR_TIF)) ? 1UL : 0UL); 3917:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3919:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3920:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Clear the break interrupt flag (BIF). 3921:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SR BIF LL_TIM_ClearFlag_BRK 3922:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3923:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 3924:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3925:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_ClearFlag_BRK(TIM_TypeDef *TIMx) 3926:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3927:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** WRITE_REG(TIMx->SR, ~(TIM_SR_BIF)); 3928:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3929:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3930:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3931:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Indicate whether break interrupt flag (BIF) is set (break interrupt is pending). 3932:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SR BIF LL_TIM_IsActiveFlag_BRK 3933:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3934:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval State of bit (1 or 0). 3935:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3936:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK(const TIM_TypeDef *TIMx) 3937:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3938:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return ((READ_BIT(TIMx->SR, TIM_SR_BIF) == (TIM_SR_BIF)) ? 1UL : 0UL); 3939:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3940:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3941:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3942:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Clear the break 2 interrupt flag (B2IF). 3943:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SR B2IF LL_TIM_ClearFlag_BRK2 3944:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3945:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 3946:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3947:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_ClearFlag_BRK2(TIM_TypeDef *TIMx) 3948:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3949:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** WRITE_REG(TIMx->SR, ~(TIM_SR_B2IF)); 3950:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3951:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3952:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3953:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Indicate whether break 2 interrupt flag (B2IF) is set (break 2 interrupt is pending). 3954:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SR B2IF LL_TIM_IsActiveFlag_BRK2 3955:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3956:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval State of bit (1 or 0). 3957:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3958:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK2(const TIM_TypeDef *TIMx) 3959:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3960:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return ((READ_BIT(TIMx->SR, TIM_SR_B2IF) == (TIM_SR_B2IF)) ? 1UL : 0UL); 3961:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3962:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** ARM GAS /tmp/ccdsDELB.s page 298 3963:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3964:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Clear the Capture/Compare 1 over-capture interrupt flag (CC1OF). 3965:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SR CC1OF LL_TIM_ClearFlag_CC1OVR 3966:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3967:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 3968:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3969:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_ClearFlag_CC1OVR(TIM_TypeDef *TIMx) 3970:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3971:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** WRITE_REG(TIMx->SR, ~(TIM_SR_CC1OF)); 3972:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3973:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3974:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3975:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Indicate whether Capture/Compare 1 over-capture interrupt flag (CC1OF) is set 3976:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * (Capture/Compare 1 interrupt is pending). 3977:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SR CC1OF LL_TIM_IsActiveFlag_CC1OVR 3978:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3979:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval State of bit (1 or 0). 3980:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3981:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1OVR(const TIM_TypeDef *TIMx) 3982:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3983:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return ((READ_BIT(TIMx->SR, TIM_SR_CC1OF) == (TIM_SR_CC1OF)) ? 1UL : 0UL); 3984:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3985:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3986:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3987:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Clear the Capture/Compare 2 over-capture interrupt flag (CC2OF). 3988:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SR CC2OF LL_TIM_ClearFlag_CC2OVR 3989:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3990:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 3991:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3992:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_ClearFlag_CC2OVR(TIM_TypeDef *TIMx) 3993:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3994:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** WRITE_REG(TIMx->SR, ~(TIM_SR_CC2OF)); 3995:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3996:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3997:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3998:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Indicate whether Capture/Compare 2 over-capture interrupt flag (CC2OF) is set 3999:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * (Capture/Compare 2 over-capture interrupt is pending). 4000:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SR CC2OF LL_TIM_IsActiveFlag_CC2OVR 4001:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 4002:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval State of bit (1 or 0). 4003:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 4004:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2OVR(const TIM_TypeDef *TIMx) 4005:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 4006:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return ((READ_BIT(TIMx->SR, TIM_SR_CC2OF) == (TIM_SR_CC2OF)) ? 1UL : 0UL); 4007:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 4008:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 4009:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 4010:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Clear the Capture/Compare 3 over-capture interrupt flag (CC3OF). 4011:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SR CC3OF LL_TIM_ClearFlag_CC3OVR 4012:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 4013:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 4014:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 4015:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_ClearFlag_CC3OVR(TIM_TypeDef *TIMx) 4016:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 4017:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** WRITE_REG(TIMx->SR, ~(TIM_SR_CC3OF)); 4018:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 4019:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** ARM GAS /tmp/ccdsDELB.s page 299 4020:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 4021:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Indicate whether Capture/Compare 3 over-capture interrupt flag (CC3OF) is set 4022:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * (Capture/Compare 3 over-capture interrupt is pending). 4023:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SR CC3OF LL_TIM_IsActiveFlag_CC3OVR 4024:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 4025:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval State of bit (1 or 0). 4026:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 4027:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3OVR(const TIM_TypeDef *TIMx) 4028:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 4029:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return ((READ_BIT(TIMx->SR, TIM_SR_CC3OF) == (TIM_SR_CC3OF)) ? 1UL : 0UL); 4030:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 4031:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 4032:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 4033:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Clear the Capture/Compare 4 over-capture interrupt flag (CC4OF). 4034:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SR CC4OF LL_TIM_ClearFlag_CC4OVR 4035:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 4036:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 4037:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 4038:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_ClearFlag_CC4OVR(TIM_TypeDef *TIMx) 4039:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 4040:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** WRITE_REG(TIMx->SR, ~(TIM_SR_CC4OF)); 4041:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 4042:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 4043:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 4044:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Indicate whether Capture/Compare 4 over-capture interrupt flag (CC4OF) is set 4045:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * (Capture/Compare 4 over-capture interrupt is pending). 4046:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SR CC4OF LL_TIM_IsActiveFlag_CC4OVR 4047:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 4048:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval State of bit (1 or 0). 4049:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 4050:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4OVR(const TIM_TypeDef *TIMx) 4051:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 4052:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return ((READ_BIT(TIMx->SR, TIM_SR_CC4OF) == (TIM_SR_CC4OF)) ? 1UL : 0UL); 4053:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 4054:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 4055:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 4056:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Clear the system break interrupt flag (SBIF). 4057:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SR SBIF LL_TIM_ClearFlag_SYSBRK 4058:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 4059:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 4060:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 4061:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_ClearFlag_SYSBRK(TIM_TypeDef *TIMx) 4062:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 4063:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** WRITE_REG(TIMx->SR, ~(TIM_SR_SBIF)); 4064:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 4065:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 4066:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 4067:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Indicate whether system break interrupt flag (SBIF) is set (system break interrupt is p 4068:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SR SBIF LL_TIM_IsActiveFlag_SYSBRK 4069:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 4070:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval State of bit (1 or 0). 4071:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 4072:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_SYSBRK(const TIM_TypeDef *TIMx) 4073:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 4074:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return ((READ_BIT(TIMx->SR, TIM_SR_SBIF) == (TIM_SR_SBIF)) ? 1UL : 0UL); 4075:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 4076:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** ARM GAS /tmp/ccdsDELB.s page 300 4077:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 4078:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} 4079:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 4080:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 4081:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EF_IT_Management IT-Management 4082:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ 4083:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 4084:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 4085:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Enable update interrupt (UIE). 4086:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll DIER UIE LL_TIM_EnableIT_UPDATE 4087:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 4088:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 4089:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 4090:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_EnableIT_UPDATE(TIM_TypeDef *TIMx) 4620 .loc 5 4090 22 view .LVU1585 4621 .LBB458: 4091:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 4092:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** SET_BIT(TIMx->DIER, TIM_DIER_UIE); 4622 .loc 5 4092 3 view .LVU1586 4623 00a6 864B ldr r3, .L182+72 4624 00a8 DA68 ldr r2, [r3, #12] 4625 00aa 42F00102 orr r2, r2, #1 4626 00ae DA60 str r2, [r3, #12] 4627 .LVL333: 4628 .loc 5 4092 3 is_stmt 0 view .LVU1587 4629 .LBE458: 4630 .LBE457: 1509:Src/main.c **** LL_TIM_EnableIT_UPDATE(TIM7); 4631 .loc 2 1509 2 is_stmt 1 view .LVU1588 4632 .LBB459: 4633 .LBI459: 1313:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 4634 .loc 5 1313 22 view .LVU1589 4635 .LBB460: 1315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 4636 .loc 5 1315 3 view .LVU1590 4637 00b0 1A68 ldr r2, [r3] 4638 00b2 42F00102 orr r2, r2, #1 4639 00b6 1A60 str r2, [r3] 4640 .LVL334: 1315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 4641 .loc 5 1315 3 is_stmt 0 view .LVU1591 4642 .LBE460: 4643 .LBE459: 1510:Src/main.c **** LL_TIM_EnableCounter(TIM7); 4644 .loc 2 1510 2 is_stmt 1 view .LVU1592 4645 .LBB461: 4646 .LBI461: 4090:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 4647 .loc 5 4090 22 view .LVU1593 4648 .LBB462: 4649 .loc 5 4092 3 view .LVU1594 4650 00b8 03F58063 add r3, r3, #1024 4651 00bc DA68 ldr r2, [r3, #12] 4652 00be 42F00102 orr r2, r2, #1 4653 00c2 DA60 str r2, [r3, #12] 4654 .LVL335: ARM GAS /tmp/ccdsDELB.s page 301 4655 .loc 5 4092 3 is_stmt 0 view .LVU1595 4656 .LBE462: 4657 .LBE461: 1511:Src/main.c **** //HAL_TIM_Base_Start_IT(&htim6); 4658 .loc 2 1511 2 is_stmt 1 view .LVU1596 4659 .LBB463: 4660 .LBI463: 1313:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 4661 .loc 5 1313 22 view .LVU1597 4662 .LBB464: 1315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 4663 .loc 5 1315 3 view .LVU1598 4664 00c4 1A68 ldr r2, [r3] 4665 00c6 42F00102 orr r2, r2, #1 4666 00ca 1A60 str r2, [r3] 4667 .LVL336: 1315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 4668 .loc 5 1315 3 is_stmt 0 view .LVU1599 4669 .LBE464: 4670 .LBE463: 1518:Src/main.c **** LL_DMA_ClearFlag_TC7(DMA2); 4671 .loc 2 1518 3 is_stmt 1 view .LVU1600 4672 .LBB465: 4673 .LBI465: 4674 .file 6 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h" 1:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 2:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** ****************************************************************************** 3:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @file stm32f7xx_ll_dma.h 4:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @author MCD Application Team 5:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Header file of DMA LL module. 6:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** ****************************************************************************** 7:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @attention 8:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * 9:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * Copyright (c) 2017 STMicroelectronics. 10:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * All rights reserved. 11:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * 12:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * This software is licensed under terms that can be found in the LICENSE file in 13:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * the root directory of this software component. 14:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * If no LICENSE file comes with this software, it is provided AS-IS. 15:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * 16:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** ****************************************************************************** 17:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 18:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 19:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /* Define to prevent recursive inclusion -------------------------------------*/ 20:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #ifndef __STM32F7xx_LL_DMA_H 21:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define __STM32F7xx_LL_DMA_H 22:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 23:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #ifdef __cplusplus 24:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** extern "C" { 25:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #endif 26:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 27:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /* Includes ------------------------------------------------------------------*/ 28:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #include "stm32f7xx.h" 29:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 30:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @addtogroup STM32F7xx_LL_Driver 31:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @{ 32:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ ARM GAS /tmp/ccdsDELB.s page 302 33:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 34:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #if defined (DMA1) || defined (DMA2) 35:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 36:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL DMA 37:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @{ 38:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 39:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 40:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /* Private types -------------------------------------------------------------*/ 41:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /* Private variables ---------------------------------------------------------*/ 42:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_Private_Variables DMA Private Variables 43:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @{ 44:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 45:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /* Array used to get the DMA stream register offset versus stream index LL_DMA_STREAM_x */ 46:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** static const uint8_t STREAM_OFFSET_TAB[] = 47:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 48:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** (uint8_t)(DMA1_Stream0_BASE - DMA1_BASE), 49:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** (uint8_t)(DMA1_Stream1_BASE - DMA1_BASE), 50:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** (uint8_t)(DMA1_Stream2_BASE - DMA1_BASE), 51:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** (uint8_t)(DMA1_Stream3_BASE - DMA1_BASE), 52:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** (uint8_t)(DMA1_Stream4_BASE - DMA1_BASE), 53:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** (uint8_t)(DMA1_Stream5_BASE - DMA1_BASE), 54:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** (uint8_t)(DMA1_Stream6_BASE - DMA1_BASE), 55:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** (uint8_t)(DMA1_Stream7_BASE - DMA1_BASE) 56:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }; 57:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 58:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 59:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @} 60:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 61:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 62:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /* Private constants ---------------------------------------------------------*/ 63:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_Private_Constants DMA Private Constants 64:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @{ 65:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 66:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #if defined(DMA_SxCR_CHSEL_3) 67:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define DMA_CHANNEL_SELECTION_8_15 68:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #endif /* DMA_SxCR_CHSEL_3 */ 69:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 70:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @} 71:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 72:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 73:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 74:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /* Private macros ------------------------------------------------------------*/ 75:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /* Exported types ------------------------------------------------------------*/ 76:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #if defined(USE_FULL_LL_DRIVER) 77:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_ES_INIT DMA Exported Init structure 78:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @{ 79:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 80:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** typedef struct 81:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 82:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** uint32_t PeriphOrM2MSrcAddress; /*!< Specifies the peripheral base address for DMA transfer 83:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** or as Source base address in case of memory to memory trans 84:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 85:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** This parameter must be a value between Min_Data = 0 and Max 86:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 87:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** uint32_t MemoryOrM2MDstAddress; /*!< Specifies the memory base address for DMA transfer 88:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** or as Destination base address in case of memory to memory 89:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** ARM GAS /tmp/ccdsDELB.s page 303 90:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** This parameter must be a value between Min_Data = 0 and Max 91:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 92:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** uint32_t Direction; /*!< Specifies if the data will be transferred from memory to pe 93:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** from memory to memory or from peripheral to memory. 94:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** This parameter can be a value of @ref DMA_LL_EC_DIRECTION 95:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 96:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** This feature can be modified afterwards using unitary funct 97:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 98:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** uint32_t Mode; /*!< Specifies the normal or circular operation mode. 99:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** This parameter can be a value of @ref DMA_LL_EC_MODE 100:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** @note The circular buffer mode cannot be used if the memory 101:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** data transfer direction is configured on the selected 102:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 103:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** This feature can be modified afterwards using unitary funct 104:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 105:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** uint32_t PeriphOrM2MSrcIncMode; /*!< Specifies whether the Peripheral address or Source address 106:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** is incremented or not. 107:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** This parameter can be a value of @ref DMA_LL_EC_PERIPH 108:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 109:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** This feature can be modified afterwards using unitary funct 110:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 111:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** uint32_t MemoryOrM2MDstIncMode; /*!< Specifies whether the Memory address or Destination address 112:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** is incremented or not. 113:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** This parameter can be a value of @ref DMA_LL_EC_MEMORY 114:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 115:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** This feature can be modified afterwards using unitary funct 116:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 117:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** uint32_t PeriphOrM2MSrcDataSize; /*!< Specifies the Peripheral data size alignment or Source data 118:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** in case of memory to memory transfer direction. 119:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** This parameter can be a value of @ref DMA_LL_EC_PDATAALIGN 120:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 121:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** This feature can be modified afterwards using unitary funct 122:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 123:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** uint32_t MemoryOrM2MDstDataSize; /*!< Specifies the Memory data size alignment or Destination dat 124:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** in case of memory to memory transfer direction. 125:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** This parameter can be a value of @ref DMA_LL_EC_MDATAALIGN 126:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 127:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** This feature can be modified afterwards using unitary funct 128:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 129:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** uint32_t NbData; /*!< Specifies the number of data to transfer, in data unit. 130:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** The data unit is equal to the source buffer configuration s 131:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** or MemorySize parameters depending in the transfer directio 132:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** This parameter must be a value between Min_Data = 0 and Max 133:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 134:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** This feature can be modified afterwards using unitary funct 135:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 136:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** uint32_t Channel; /*!< Specifies the peripheral channel. 137:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** This parameter can be a value of @ref DMA_LL_EC_CHANNEL 138:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 139:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** This feature can be modified afterwards using unitary funct 140:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 141:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** uint32_t Priority; /*!< Specifies the channel priority level. 142:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** This parameter can be a value of @ref DMA_LL_EC_PRIORITY 143:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 144:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** This feature can be modified afterwards using unitary funct 145:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 146:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** uint32_t FIFOMode; /*!< Specifies if the FIFO mode or Direct mode will be used for ARM GAS /tmp/ccdsDELB.s page 304 147:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** This parameter can be a value of @ref DMA_LL_FIFOMODE 148:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** @note The Direct mode (FIFO mode disabled) cannot be used i 149:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** memory-to-memory data transfer is configured on the selecte 150:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 151:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** This feature can be modified afterwards using unitary funct 152:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 153:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** uint32_t FIFOThreshold; /*!< Specifies the FIFO threshold level. 154:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** This parameter can be a value of @ref DMA_LL_EC_FIFOTHRESHO 155:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 156:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** This feature can be modified afterwards using unitary funct 157:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 158:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** uint32_t MemBurst; /*!< Specifies the Burst transfer configuration for the memory t 159:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** It specifies the amount of data to be transferred in a sing 160:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** transaction. 161:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** This parameter can be a value of @ref DMA_LL_EC_MBURST 162:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** @note The burst mode is possible only if the address Increm 163:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 164:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** This feature can be modified afterwards using unitary funct 165:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 166:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** uint32_t PeriphBurst; /*!< Specifies the Burst transfer configuration for the peripher 167:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** It specifies the amount of data to be transferred in a sing 168:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** transaction. 169:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** This parameter can be a value of @ref DMA_LL_EC_PBURST 170:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** @note The burst mode is possible only if the address Increm 171:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 172:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** This feature can be modified afterwards using unitary funct 173:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 174:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } LL_DMA_InitTypeDef; 175:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 176:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @} 177:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 178:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #endif /*USE_FULL_LL_DRIVER*/ 179:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /* Exported constants --------------------------------------------------------*/ 180:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_Exported_Constants DMA Exported Constants 181:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @{ 182:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 183:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 184:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_EC_STREAM STREAM 185:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @{ 186:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 187:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_STREAM_0 0x00000000U 188:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_STREAM_1 0x00000001U 189:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_STREAM_2 0x00000002U 190:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_STREAM_3 0x00000003U 191:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_STREAM_4 0x00000004U 192:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_STREAM_5 0x00000005U 193:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_STREAM_6 0x00000006U 194:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_STREAM_7 0x00000007U 195:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_STREAM_ALL 0xFFFF0000U 196:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 197:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @} 198:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 199:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 200:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_EC_DIRECTION DIRECTION 201:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @{ 202:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 203:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_DIRECTION_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direc ARM GAS /tmp/ccdsDELB.s page 305 204:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_DIRECTION_MEMORY_TO_PERIPH DMA_SxCR_DIR_0 /*!< Memory to peripheral direc 205:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_DIRECTION_MEMORY_TO_MEMORY DMA_SxCR_DIR_1 /*!< Memory to memory direction 206:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 207:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @} 208:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 209:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 210:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_EC_MODE MODE 211:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @{ 212:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 213:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_MODE_NORMAL 0x00000000U /*!< Normal Mode 214:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_MODE_CIRCULAR DMA_SxCR_CIRC /*!< Circular Mode 215:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_MODE_PFCTRL DMA_SxCR_PFCTRL /*!< Peripheral flow control mo 216:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 217:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @} 218:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 219:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 220:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_EC_DOUBLEBUFFER_MODE DOUBLE BUFFER MODE 221:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @{ 222:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 223:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_DOUBLEBUFFER_MODE_DISABLE 0x00000000U /*!< Disable double buffering m 224:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_DOUBLEBUFFER_MODE_ENABLE DMA_SxCR_DBM /*!< Enable double buffering mo 225:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 226:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @} 227:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 228:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 229:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_EC_PERIPH PERIPH 230:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @{ 231:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 232:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_PERIPH_NOINCREMENT 0x00000000U /*!< Peripheral increment mode 233:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_PERIPH_INCREMENT DMA_SxCR_PINC /*!< Peripheral increment mode 234:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 235:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @} 236:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 237:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 238:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_EC_MEMORY MEMORY 239:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @{ 240:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 241:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_MEMORY_NOINCREMENT 0x00000000U /*!< Memory increment mode Disa 242:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_MEMORY_INCREMENT DMA_SxCR_MINC /*!< Memory increment mode Enab 243:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 244:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @} 245:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 246:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 247:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_EC_PDATAALIGN PDATAALIGN 248:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @{ 249:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 250:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_PDATAALIGN_BYTE 0x00000000U /*!< Peripheral data alignment 251:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_PDATAALIGN_HALFWORD DMA_SxCR_PSIZE_0 /*!< Peripheral data alignment 252:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_PDATAALIGN_WORD DMA_SxCR_PSIZE_1 /*!< Peripheral data alignment 253:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 254:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @} 255:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 256:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 257:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_EC_MDATAALIGN MDATAALIGN 258:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @{ 259:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 260:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_MDATAALIGN_BYTE 0x00000000U /*!< Memory data alignment : By ARM GAS /tmp/ccdsDELB.s page 306 261:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_MDATAALIGN_HALFWORD DMA_SxCR_MSIZE_0 /*!< Memory data alignment : Ha 262:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_MDATAALIGN_WORD DMA_SxCR_MSIZE_1 /*!< Memory data alignment : Wo 263:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 264:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @} 265:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 266:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 267:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_EC_OFFSETSIZE OFFSETSIZE 268:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @{ 269:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 270:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_OFFSETSIZE_PSIZE 0x00000000U /*!< Peripheral increment offse 271:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_OFFSETSIZE_FIXEDTO4 DMA_SxCR_PINCOS /*!< Peripheral increment offse 272:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 273:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @} 274:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 275:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 276:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_EC_PRIORITY PRIORITY 277:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @{ 278:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 279:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_PRIORITY_LOW 0x00000000U /*!< Priority level : Low 280:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_PRIORITY_MEDIUM DMA_SxCR_PL_0 /*!< Priority level : Medium 281:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_PRIORITY_HIGH DMA_SxCR_PL_1 /*!< Priority level : High 282:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_PRIORITY_VERYHIGH DMA_SxCR_PL /*!< Priority level : Very_High 283:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 284:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @} 285:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 286:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 287:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_EC_CHANNEL CHANNEL 288:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @{ 289:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 290:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_CHANNEL_0 0x00000000U 291:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_CHANNEL_1 DMA_SxCR_CHSEL_0 292:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_CHANNEL_2 DMA_SxCR_CHSEL_1 293:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_CHANNEL_3 (DMA_SxCR_CHSEL_0 | DMA_SxCR_CHSEL_1) 294:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_CHANNEL_4 DMA_SxCR_CHSEL_2 295:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_CHANNEL_5 (DMA_SxCR_CHSEL_2 | DMA_SxCR_CHSEL_0) 296:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_CHANNEL_6 (DMA_SxCR_CHSEL_2 | DMA_SxCR_CHSEL_1) 297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_CHANNEL_7 (DMA_SxCR_CHSEL_2 | DMA_SxCR_CHSEL_1 | DMA_SxCR_CHSEL_0) 298:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #if defined(DMA_CHANNEL_SELECTION_8_15) 299:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_CHANNEL_8 DMA_SxCR_CHSEL_3 300:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_CHANNEL_9 (DMA_SxCR_CHSEL_3 | DMA_SxCR_CHSEL_0) 301:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_CHANNEL_10 (DMA_SxCR_CHSEL_3 | DMA_SxCR_CHSEL_1) 302:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_CHANNEL_11 (DMA_SxCR_CHSEL_3 | DMA_SxCR_CHSEL_1 | DMA_SxCR_CHSEL_0) 303:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_CHANNEL_12 (DMA_SxCR_CHSEL_3 | DMA_SxCR_CHSEL_2) 304:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_CHANNEL_13 (DMA_SxCR_CHSEL_3 | DMA_SxCR_CHSEL_2 | DMA_SxCR_CHSEL_0) 305:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_CHANNEL_14 (DMA_SxCR_CHSEL_3 | DMA_SxCR_CHSEL_2 | DMA_SxCR_CHSEL_1) 306:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_CHANNEL_15 DMA_SxCR_CHSEL 307:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #endif /* DMA_CHANNEL_SELECTION_8_15 */ 308:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 309:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @} 310:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 311:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 312:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_EC_MBURST MBURST 313:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @{ 314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_MBURST_SINGLE 0x00000000U /*!< Memory burst 316:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_MBURST_INC4 DMA_SxCR_MBURST_0 /*!< Memory burst 317:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_MBURST_INC8 DMA_SxCR_MBURST_1 /*!< Memory burst ARM GAS /tmp/ccdsDELB.s page 307 318:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_MBURST_INC16 (DMA_SxCR_MBURST_0 | DMA_SxCR_MBURST_1) /*!< Memory burst 319:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 320:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @} 321:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 322:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 323:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_EC_PBURST PBURST 324:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @{ 325:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 326:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_PBURST_SINGLE 0x00000000U /*!< Peripheral b 327:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_PBURST_INC4 DMA_SxCR_PBURST_0 /*!< Peripheral b 328:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_PBURST_INC8 DMA_SxCR_PBURST_1 /*!< Peripheral b 329:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_PBURST_INC16 (DMA_SxCR_PBURST_0 | DMA_SxCR_PBURST_1) /*!< Peripheral b 330:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 331:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @} 332:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 333:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 334:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_FIFOMODE DMA_LL_FIFOMODE 335:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @{ 336:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 337:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_FIFOMODE_DISABLE 0x00000000U /*!< FIFO mode di 338:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_FIFOMODE_ENABLE DMA_SxFCR_DMDIS /*!< FIFO mode en 339:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 340:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @} 341:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 342:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 343:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_EC_FIFOSTATUS_0 FIFOSTATUS 0 344:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @{ 345:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_FIFOSTATUS_0_25 0x00000000U /*!< 0 < fifo_lev 347:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_FIFOSTATUS_25_50 DMA_SxFCR_FS_0 /*!< 1/4 < fifo_l 348:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_FIFOSTATUS_50_75 DMA_SxFCR_FS_1 /*!< 1/2 < fifo_l 349:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_FIFOSTATUS_75_100 (DMA_SxFCR_FS_1 | DMA_SxFCR_FS_0) /*!< 3/4 < fifo_l 350:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_FIFOSTATUS_EMPTY DMA_SxFCR_FS_2 /*!< FIFO is empt 351:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_FIFOSTATUS_FULL (DMA_SxFCR_FS_2 | DMA_SxFCR_FS_0) /*!< FIFO is full 352:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 353:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @} 354:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 355:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 356:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_EC_FIFOTHRESHOLD FIFOTHRESHOLD 357:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @{ 358:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 359:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_FIFOTHRESHOLD_1_4 0x00000000U /*!< FIFO thresho 360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_FIFOTHRESHOLD_1_2 DMA_SxFCR_FTH_0 /*!< FIFO thresho 361:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_FIFOTHRESHOLD_3_4 DMA_SxFCR_FTH_1 /*!< FIFO thresho 362:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_FIFOTHRESHOLD_FULL DMA_SxFCR_FTH /*!< FIFO thresho 363:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 364:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @} 365:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 366:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 367:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_EC_CURRENTTARGETMEM CURRENTTARGETMEM 368:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @{ 369:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_CURRENTTARGETMEM0 0x00000000U /*!< Set CurrentT 371:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_CURRENTTARGETMEM1 DMA_SxCR_CT /*!< Set CurrentT 372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @} 374:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ ARM GAS /tmp/ccdsDELB.s page 308 375:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 376:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 377:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @} 378:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 379:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 380:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /* Exported macro ------------------------------------------------------------*/ 381:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_Exported_Macros DMA Exported Macros 382:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @{ 383:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 384:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 385:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_EM_WRITE_READ Common Write and read registers macros 386:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @{ 387:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 388:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 389:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Write a value in DMA register 390:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param __INSTANCE__ DMA Instance 391:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param __REG__ Register to be written 392:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param __VALUE__ Value to be written in the register 393:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 394:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 395:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE 396:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 397:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 398:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Read a value in DMA register 399:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param __INSTANCE__ DMA Instance 400:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param __REG__ Register to be read 401:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval Register value 402:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 403:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) 404:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 405:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @} 406:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 407:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 408:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_EM_CONVERT_DMAxCHANNELy Convert DMAxStreamy 409:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @{ 410:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 411:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 412:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Convert DMAx_Streamy into DMAx 413:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param __STREAM_INSTANCE__ DMAx_Streamy 414:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval DMAx 415:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 416:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define __LL_DMA_GET_INSTANCE(__STREAM_INSTANCE__) \ 417:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** (((uint32_t)(__STREAM_INSTANCE__) > ((uint32_t)DMA1_Stream7)) ? DMA2 : DMA1) 418:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 419:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 420:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Convert DMAx_Streamy into LL_DMA_STREAM_y 421:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param __STREAM_INSTANCE__ DMAx_Streamy 422:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval LL_DMA_CHANNEL_y 423:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 424:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define __LL_DMA_GET_STREAM(__STREAM_INSTANCE__) \ 425:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** (((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream0)) ? LL_DMA_STREAM_0 : \ 426:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream0)) ? LL_DMA_STREAM_0 : \ 427:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream1)) ? LL_DMA_STREAM_1 : \ 428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream1)) ? LL_DMA_STREAM_1 : \ 429:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream2)) ? LL_DMA_STREAM_2 : \ 430:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream2)) ? LL_DMA_STREAM_2 : \ 431:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream3)) ? LL_DMA_STREAM_3 : \ ARM GAS /tmp/ccdsDELB.s page 309 432:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream3)) ? LL_DMA_STREAM_3 : \ 433:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream4)) ? LL_DMA_STREAM_4 : \ 434:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream4)) ? LL_DMA_STREAM_4 : \ 435:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream5)) ? LL_DMA_STREAM_5 : \ 436:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream5)) ? LL_DMA_STREAM_5 : \ 437:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream6)) ? LL_DMA_STREAM_6 : \ 438:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream6)) ? LL_DMA_STREAM_6 : \ 439:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** LL_DMA_STREAM_7) 440:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 441:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 442:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Convert DMA Instance DMAx and LL_DMA_STREAM_y into DMAx_Streamy 443:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param __DMA_INSTANCE__ DMAx 444:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param __STREAM__ LL_DMA_STREAM_y 445:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval DMAx_Streamy 446:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 447:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define __LL_DMA_GET_STREAM_INSTANCE(__DMA_INSTANCE__, __STREAM__) \ 448:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** ((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DM 449:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DM 450:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DM 451:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DM 452:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DM 453:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DM 454:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DM 455:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DM 456:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DM 457:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DM 458:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DM 459:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DM 460:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DM 461:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DM 462:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DM 463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** DMA2_Stream7) 464:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 465:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 466:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @} 467:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 468:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 469:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 470:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @} 471:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 472:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 473:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 474:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /* Exported functions --------------------------------------------------------*/ 475:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_Exported_Functions DMA Exported Functions 476:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @{ 477:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 478:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 479:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_EF_Configuration Configuration 480:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @{ 481:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 482:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 483:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Enable DMA stream. 484:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR EN LL_DMA_EnableStream 485:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 486:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: 487:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 488:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 ARM GAS /tmp/ccdsDELB.s page 310 489:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 490:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 491:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 492:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 493:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 494:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 495:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 496:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 497:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_EnableStream(DMA_TypeDef *DMAx, uint32_t Stream) 498:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 499:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA 500:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 501:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 502:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 503:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Disable DMA stream. 504:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR EN LL_DMA_DisableStream 505:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 506:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: 507:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 508:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 509:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 510:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 511:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 512:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 513:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 514:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 515:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 516:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 517:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_DisableStream(DMA_TypeDef *DMAx, uint32_t Stream) 4675 .loc 6 517 22 view .LVU1601 4676 .LBB466: 518:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 519:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, D 4677 .loc 6 519 3 view .LVU1602 4678 00cc 03F51433 add r3, r3, #151552 4679 00d0 D3F8B820 ldr r2, [r3, #184] 4680 00d4 22F00102 bic r2, r2, #1 4681 00d8 C3F8B820 str r2, [r3, #184] 4682 .LVL337: 4683 .loc 6 519 3 is_stmt 0 view .LVU1603 4684 .LBE466: 4685 .LBE465: 1519:Src/main.c **** LL_DMA_ClearFlag_TE7(DMA2); 4686 .loc 2 1519 3 is_stmt 1 view .LVU1604 4687 .LBB467: 4688 .LBI467: 520:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 521:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 522:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 523:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Check if DMA stream is enabled or disabled. 524:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR EN LL_DMA_IsEnabledStream 525:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 526:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: 527:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 528:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 529:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 530:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 ARM GAS /tmp/ccdsDELB.s page 311 531:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 532:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 533:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 534:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 535:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). 536:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 537:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsEnabledStream(DMA_TypeDef *DMAx, uint32_t Stream) 538:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 539:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))- 540:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 541:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 542:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 543:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Configure all parameters linked to DMA transfer. 544:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR DIR LL_DMA_ConfigTransfer\n 545:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * CR CIRC LL_DMA_ConfigTransfer\n 546:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * CR PINC LL_DMA_ConfigTransfer\n 547:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * CR MINC LL_DMA_ConfigTransfer\n 548:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * CR PSIZE LL_DMA_ConfigTransfer\n 549:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * CR MSIZE LL_DMA_ConfigTransfer\n 550:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * CR PL LL_DMA_ConfigTransfer\n 551:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * CR PFCTRL LL_DMA_ConfigTransfer 552:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 553:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: 554:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 555:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 556:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 557:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 558:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 559:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 560:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 561:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 562:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Configuration This parameter must be a combination of all the following values: 563:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY or @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH o 564:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_MODE_NORMAL or @ref LL_DMA_MODE_CIRCULAR or @ref LL_DMA_MODE_PFCTRL 565:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_PERIPH_INCREMENT or @ref LL_DMA_PERIPH_NOINCREMENT 566:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_MEMORY_INCREMENT or @ref LL_DMA_MEMORY_NOINCREMENT 567:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_PDATAALIGN_BYTE or @ref LL_DMA_PDATAALIGN_HALFWORD or @ref LL_DMA_PDAT 568:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_MDATAALIGN_BYTE or @ref LL_DMA_MDATAALIGN_HALFWORD or @ref LL_DMA_MDAT 569:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_PRIORITY_LOW or @ref LL_DMA_PRIORITY_MEDIUM or @ref LL_DMA_PRIORITY_HI 570:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** *@retval None 571:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 572:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ConfigTransfer(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Configurati 573:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 574:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** MODIFY_REG(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, 575:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** DMA_SxCR_DIR | DMA_SxCR_CIRC | DMA_SxCR_PINC | DMA_SxCR_MINC | DMA_SxCR_PSIZE | DMA_Sx 576:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** Configuration); 577:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 578:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 579:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 580:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Set Data transfer direction (read from peripheral or from memory). 581:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR DIR LL_DMA_SetDataTransferDirection 582:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 583:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: 584:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 585:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 586:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 587:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 ARM GAS /tmp/ccdsDELB.s page 312 588:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 589:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 590:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 591:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 592:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Direction This parameter can be one of the following values: 593:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY 594:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH 595:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY 596:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 597:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 598:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_SetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t 599:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 600:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, D 601:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 602:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 603:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 604:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Data transfer direction (read from peripheral or from memory). 605:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR DIR LL_DMA_GetDataTransferDirection 606:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 607:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: 608:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 609:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 610:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 611:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 612:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 613:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 614:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 615:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 616:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval Returned value can be one of the following values: 617:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY 618:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH 619:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY 620:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 621:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Stream) 622:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 623:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))- 624:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 625:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 626:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 627:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Set DMA mode normal, circular or peripheral flow control. 628:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR CIRC LL_DMA_SetMode\n 629:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * CR PFCTRL LL_DMA_SetMode 630:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 631:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: 632:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 633:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 634:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 635:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 636:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 637:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 638:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 639:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 640:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Mode This parameter can be one of the following values: 641:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_MODE_NORMAL 642:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_MODE_CIRCULAR 643:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_MODE_PFCTRL 644:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None ARM GAS /tmp/ccdsDELB.s page 313 645:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 646:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_SetMode(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Mode) 647:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 648:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, D 649:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 650:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 651:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 652:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get DMA mode normal, circular or peripheral flow control. 653:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR CIRC LL_DMA_GetMode\n 654:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * CR PFCTRL LL_DMA_GetMode 655:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 656:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: 657:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 658:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 659:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 660:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 661:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 662:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 663:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 664:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 665:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval Returned value can be one of the following values: 666:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_MODE_NORMAL 667:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_MODE_CIRCULAR 668:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_MODE_PFCTRL 669:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 670:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_GetMode(DMA_TypeDef *DMAx, uint32_t Stream) 671:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 672:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))- 673:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 674:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 675:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 676:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Set Peripheral increment mode. 677:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR PINC LL_DMA_SetPeriphIncMode 678:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 679:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: 680:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 681:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 682:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 683:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 684:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 685:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 686:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 687:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 688:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param IncrementMode This parameter can be one of the following values: 689:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_PERIPH_NOINCREMENT 690:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_PERIPH_INCREMENT 691:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 692:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 693:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_SetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Increment 694:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 695:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, D 696:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 697:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 698:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 699:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Peripheral increment mode. 700:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR PINC LL_DMA_GetPeriphIncMode 701:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance ARM GAS /tmp/ccdsDELB.s page 314 702:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: 703:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 704:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 705:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 706:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 707:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 708:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 709:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 710:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 711:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval Returned value can be one of the following values: 712:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_PERIPH_NOINCREMENT 713:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_PERIPH_INCREMENT 714:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 715:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_GetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Stream) 716:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 717:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))- 718:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 719:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 720:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 721:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Set Memory increment mode. 722:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR MINC LL_DMA_SetMemoryIncMode 723:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 724:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: 725:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 726:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 727:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 728:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 729:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 730:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 731:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 732:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 733:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param IncrementMode This parameter can be one of the following values: 734:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_MEMORY_NOINCREMENT 735:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_MEMORY_INCREMENT 736:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 737:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 738:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_SetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Increment 739:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 740:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, D 741:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 742:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 743:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 744:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Memory increment mode. 745:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR MINC LL_DMA_GetMemoryIncMode 746:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 747:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: 748:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 749:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 750:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 751:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 752:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 753:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 754:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 755:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 756:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval Returned value can be one of the following values: 757:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_MEMORY_NOINCREMENT 758:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_MEMORY_INCREMENT ARM GAS /tmp/ccdsDELB.s page 315 759:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 760:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Stream) 761:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 762:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))- 763:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 764:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 765:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 766:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Set Peripheral size. 767:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR PSIZE LL_DMA_SetPeriphSize 768:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 769:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: 770:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 771:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 772:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 773:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 774:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 775:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 776:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 777:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 778:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Size This parameter can be one of the following values: 779:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_PDATAALIGN_BYTE 780:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_PDATAALIGN_HALFWORD 781:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_PDATAALIGN_WORD 782:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 783:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 784:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_SetPeriphSize(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Size) 785:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 786:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, D 787:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 788:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 789:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 790:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Peripheral size. 791:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR PSIZE LL_DMA_GetPeriphSize 792:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 793:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: 794:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 795:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 796:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 797:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 798:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 799:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 800:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 801:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 802:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval Returned value can be one of the following values: 803:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_PDATAALIGN_BYTE 804:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_PDATAALIGN_HALFWORD 805:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_PDATAALIGN_WORD 806:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 807:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_GetPeriphSize(DMA_TypeDef *DMAx, uint32_t Stream) 808:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 809:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))- 810:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 811:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 812:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 813:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Set Memory size. 814:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR MSIZE LL_DMA_SetMemorySize 815:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance ARM GAS /tmp/ccdsDELB.s page 316 816:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: 817:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 818:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 819:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 820:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 821:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 822:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 823:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 824:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 825:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Size This parameter can be one of the following values: 826:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_MDATAALIGN_BYTE 827:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_MDATAALIGN_HALFWORD 828:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_MDATAALIGN_WORD 829:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 830:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 831:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_SetMemorySize(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Size) 832:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 833:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, D 834:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 835:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 836:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 837:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Memory size. 838:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR MSIZE LL_DMA_GetMemorySize 839:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 840:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: 841:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 842:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 843:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 844:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 845:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 846:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 847:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 848:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 849:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval Returned value can be one of the following values: 850:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_MDATAALIGN_BYTE 851:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_MDATAALIGN_HALFWORD 852:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_MDATAALIGN_WORD 853:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 854:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_GetMemorySize(DMA_TypeDef *DMAx, uint32_t Stream) 855:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 856:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))- 857:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 858:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 859:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 860:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Set Peripheral increment offset size. 861:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR PINCOS LL_DMA_SetIncOffsetSize 862:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 863:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: 864:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 865:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 866:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 867:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 868:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 869:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 870:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 871:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 872:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param OffsetSize This parameter can be one of the following values: ARM GAS /tmp/ccdsDELB.s page 317 873:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_OFFSETSIZE_PSIZE 874:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_OFFSETSIZE_FIXEDTO4 875:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 876:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 877:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_SetIncOffsetSize(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t OffsetSiz 878:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 879:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, D 880:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 881:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 882:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 883:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Peripheral increment offset size. 884:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR PINCOS LL_DMA_GetIncOffsetSize 885:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 886:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: 887:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 888:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 889:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 890:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 891:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 892:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 893:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 894:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 895:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval Returned value can be one of the following values: 896:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_OFFSETSIZE_PSIZE 897:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_OFFSETSIZE_FIXEDTO4 898:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 899:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_GetIncOffsetSize(DMA_TypeDef *DMAx, uint32_t Stream) 900:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 901:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))- 902:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 903:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 904:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 905:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Set Stream priority level. 906:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR PL LL_DMA_SetStreamPriorityLevel 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 908:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: 909:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 910:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 911:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 912:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 913:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 914:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 915:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 916:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 917:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Priority This parameter can be one of the following values: 918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_PRIORITY_LOW 919:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_PRIORITY_MEDIUM 920:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_PRIORITY_HIGH 921:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_PRIORITY_VERYHIGH 922:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 923:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 924:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_SetStreamPriorityLevel(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Pr 925:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 926:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, D 927:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 928:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 929:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** ARM GAS /tmp/ccdsDELB.s page 318 930:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream priority level. 931:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR PL LL_DMA_GetStreamPriorityLevel 932:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 933:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: 934:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 935:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 936:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 937:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 938:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 939:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 940:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 941:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 942:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval Returned value can be one of the following values: 943:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_PRIORITY_LOW 944:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_PRIORITY_MEDIUM 945:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_PRIORITY_HIGH 946:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_PRIORITY_VERYHIGH 947:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 948:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_GetStreamPriorityLevel(DMA_TypeDef *DMAx, uint32_t Stream) 949:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 950:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))- 951:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 952:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 953:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 954:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Set Number of data to transfer. 955:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll NDTR NDT LL_DMA_SetDataLength 956:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @note This action has no effect if 957:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * stream is enabled. 958:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 959:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: 960:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 961:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 962:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 963:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 964:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 965:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 966:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 967:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 968:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param NbData Between 0 to 0xFFFFFFFF 969:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 970:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 971:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_SetDataLength(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t NbData) 972:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 973:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->NDTR, 974:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 975:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 976:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 977:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Number of data to transfer. 978:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll NDTR NDT LL_DMA_GetDataLength 979:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @note Once the stream is enabled, the return value indicate the 980:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * remaining bytes to be transmitted. 981:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 982:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: 983:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 984:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 985:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 986:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 ARM GAS /tmp/ccdsDELB.s page 319 987:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 988:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 989:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 990:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 991:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval Between 0 to 0xFFFFFFFF 992:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 993:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_GetDataLength(DMA_TypeDef* DMAx, uint32_t Stream) 994:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 995:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))- 996:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 997:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 998:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 999:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Select Channel number associated to the Stream. 1000:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR CHSEL LL_DMA_SetChannelSelection 1001:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 1002:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: 1003:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 1004:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 1005:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 1006:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 1007:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 1008:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 1009:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 1010:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 1011:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Channel This parameter can be one of the following values: 1012:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_0 1013:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_1 1014:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_2 1015:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_3 1016:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_4 1017:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_5 1018:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_6 1019:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_7 1020:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_8 (*) 1021:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_9 (*) 1022:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_10 (*) 1023:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_11 (*) 1024:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_12 (*) 1025:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_13 (*) 1026:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_14 (*) 1027:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_15 (*) 1028:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * 1029:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * (*) value not defined in all devices. 1030:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 1031:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1032:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_SetChannelSelection(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Channe 1033:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1034:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, D 1035:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1036:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1037:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1038:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get the Channel number associated to the Stream. 1039:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR CHSEL LL_DMA_GetChannelSelection 1040:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 1041:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: 1042:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 1043:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 ARM GAS /tmp/ccdsDELB.s page 320 1044:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 1045:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 1046:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 1047:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 1048:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 1049:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 1050:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval Returned value can be one of the following values: 1051:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_0 1052:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_1 1053:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_2 1054:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_3 1055:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_4 1056:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_5 1057:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_6 1058:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_7 1059:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_8 (*) 1060:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_9 (*) 1061:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_10 (*) 1062:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_11 (*) 1063:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_12 (*) 1064:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_13 (*) 1065:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_14 (*) 1066:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_15 (*) 1067:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * 1068:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * (*) value not defined in all devices. 1069:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1070:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_GetChannelSelection(DMA_TypeDef *DMAx, uint32_t Stream) 1071:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1072:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))- 1073:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1074:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1075:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1076:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Set Memory burst transfer configuration. 1077:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR MBURST LL_DMA_SetMemoryBurstxfer 1078:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 1079:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: 1080:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 1081:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 1082:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 1083:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 1084:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 1085:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 1086:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 1087:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 1088:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Mburst This parameter can be one of the following values: 1089:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_MBURST_SINGLE 1090:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_MBURST_INC4 1091:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_MBURST_INC8 1092:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_MBURST_INC16 1093:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 1094:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1095:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_SetMemoryBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Mburst) 1096:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1097:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, D 1098:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1099:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1100:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** ARM GAS /tmp/ccdsDELB.s page 321 1101:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Memory burst transfer configuration. 1102:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR MBURST LL_DMA_GetMemoryBurstxfer 1103:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 1104:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: 1105:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 1106:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 1107:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 1108:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 1109:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 1110:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 1111:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 1112:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 1113:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval Returned value can be one of the following values: 1114:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_MBURST_SINGLE 1115:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_MBURST_INC4 1116:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_MBURST_INC8 1117:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_MBURST_INC16 1118:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1119:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_GetMemoryBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream) 1120:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1121:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))- 1122:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1123:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1124:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1125:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Set Peripheral burst transfer configuration. 1126:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR PBURST LL_DMA_SetPeriphBurstxfer 1127:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 1128:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: 1129:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 1130:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 1131:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 1132:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 1133:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 1134:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 1135:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 1136:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 1137:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Pburst This parameter can be one of the following values: 1138:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_PBURST_SINGLE 1139:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_PBURST_INC4 1140:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_PBURST_INC8 1141:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_PBURST_INC16 1142:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 1143:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1144:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_SetPeriphBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Pburst) 1145:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1146:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, D 1147:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1148:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1149:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1150:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Peripheral burst transfer configuration. 1151:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR PBURST LL_DMA_GetPeriphBurstxfer 1152:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 1153:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: 1154:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 1155:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 1156:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 1157:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 ARM GAS /tmp/ccdsDELB.s page 322 1158:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 1159:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 1160:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 1161:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 1162:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval Returned value can be one of the following values: 1163:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_PBURST_SINGLE 1164:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_PBURST_INC4 1165:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_PBURST_INC8 1166:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_PBURST_INC16 1167:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1168:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_GetPeriphBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream) 1169:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1170:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))- 1171:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1172:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1173:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1174:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Set Current target (only in double buffer mode) to Memory 1 or Memory 0. 1175:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR CT LL_DMA_SetCurrentTargetMem 1176:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 1177:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: 1178:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 1179:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 1180:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 1181:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 1182:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 1183:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 1184:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 1185:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 1186:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param CurrentMemory This parameter can be one of the following values: 1187:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CURRENTTARGETMEM0 1188:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CURRENTTARGETMEM1 1189:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 1190:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1191:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_SetCurrentTargetMem(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Curren 1192:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1193:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, 1194:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1195:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1196:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1197:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Set Current target (only in double buffer mode) to Memory 1 or Memory 0. 1198:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR CT LL_DMA_GetCurrentTargetMem 1199:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 1200:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: 1201:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 1202:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 1203:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 1204:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 1205:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 1206:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 1207:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 1208:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 1209:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval Returned value can be one of the following values: 1210:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CURRENTTARGETMEM0 1211:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CURRENTTARGETMEM1 1212:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1213:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_GetCurrentTargetMem(DMA_TypeDef *DMAx, uint32_t Stream) 1214:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { ARM GAS /tmp/ccdsDELB.s page 323 1215:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))- 1216:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1217:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1218:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1219:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Enable the double buffer mode. 1220:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR DBM LL_DMA_EnableDoubleBufferMode 1221:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 1222:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: 1223:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 1224:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 1225:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 1226:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 1227:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 1228:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 1229:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 1230:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 1231:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 1232:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1233:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_EnableDoubleBufferMode(DMA_TypeDef *DMAx, uint32_t Stream) 1234:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1235:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA 1236:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1237:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1238:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1239:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Disable the double buffer mode. 1240:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR DBM LL_DMA_DisableDoubleBufferMode 1241:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 1242:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: 1243:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 1244:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 1245:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 1246:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 1247:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 1248:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 1249:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 1250:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 1251:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 1252:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1253:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_DisableDoubleBufferMode(DMA_TypeDef *DMAx, uint32_t Stream) 1254:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1255:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, D 1256:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1257:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1258:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1259:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get FIFO status. 1260:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll FCR FS LL_DMA_GetFIFOStatus 1261:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 1262:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: 1263:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 1264:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 1265:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 1266:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 1267:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 1268:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 1269:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 1270:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 1271:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval Returned value can be one of the following values: ARM GAS /tmp/ccdsDELB.s page 324 1272:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_FIFOSTATUS_0_25 1273:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_FIFOSTATUS_25_50 1274:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_FIFOSTATUS_50_75 1275:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_FIFOSTATUS_75_100 1276:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_FIFOSTATUS_EMPTY 1277:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_FIFOSTATUS_FULL 1278:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1279:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_GetFIFOStatus(DMA_TypeDef *DMAx, uint32_t Stream) 1280:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1281:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))- 1282:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1283:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1284:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1285:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Disable Fifo mode. 1286:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll FCR DMDIS LL_DMA_DisableFifoMode 1287:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 1288:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: 1289:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 1290:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 1291:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 1292:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 1293:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 1294:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 1295:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 1296:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 1297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 1298:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1299:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_DisableFifoMode(DMA_TypeDef *DMAx, uint32_t Stream) 1300:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1301:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, 1302:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1303:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1304:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1305:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Enable Fifo mode. 1306:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll FCR DMDIS LL_DMA_EnableFifoMode 1307:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 1308:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: 1309:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 1310:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 1311:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 1312:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 1313:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 1314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 1315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 1316:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 1317:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 1318:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1319:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_EnableFifoMode(DMA_TypeDef *DMAx, uint32_t Stream) 1320:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1321:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DM 1322:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1323:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1324:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1325:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Select FIFO threshold. 1326:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll FCR FTH LL_DMA_SetFIFOThreshold 1327:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 1328:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: ARM GAS /tmp/ccdsDELB.s page 325 1329:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 1330:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 1331:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 1332:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 1333:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 1334:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 1335:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 1336:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 1337:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Threshold This parameter can be one of the following values: 1338:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_FIFOTHRESHOLD_1_4 1339:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_FIFOTHRESHOLD_1_2 1340:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_FIFOTHRESHOLD_3_4 1341:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_FIFOTHRESHOLD_FULL 1342:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 1343:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1344:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_SetFIFOThreshold(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Threshold 1345:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, 1347:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1348:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1349:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1350:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get FIFO threshold. 1351:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll FCR FTH LL_DMA_GetFIFOThreshold 1352:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 1353:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: 1354:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 1355:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 1356:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 1357:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 1358:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 1359:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 1360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 1361:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 1362:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval Returned value can be one of the following values: 1363:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_FIFOTHRESHOLD_1_4 1364:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_FIFOTHRESHOLD_1_2 1365:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_FIFOTHRESHOLD_3_4 1366:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_FIFOTHRESHOLD_FULL 1367:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1368:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_GetFIFOThreshold(DMA_TypeDef *DMAx, uint32_t Stream) 1369:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))- 1371:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1374:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Configure the FIFO . 1375:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll FCR FTH LL_DMA_ConfigFifo\n 1376:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * FCR DMDIS LL_DMA_ConfigFifo 1377:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 1378:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: 1379:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 1380:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 1381:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 1382:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 1383:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 1384:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 1385:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 ARM GAS /tmp/ccdsDELB.s page 326 1386:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 1387:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param FifoMode This parameter can be one of the following values: 1388:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_FIFOMODE_ENABLE 1389:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_FIFOMODE_DISABLE 1390:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param FifoThreshold This parameter can be one of the following values: 1391:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_FIFOTHRESHOLD_1_4 1392:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_FIFOTHRESHOLD_1_2 1393:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_FIFOTHRESHOLD_3_4 1394:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_FIFOTHRESHOLD_FULL 1395:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 1396:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1397:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ConfigFifo(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t FifoMode, uint3 1398:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1399:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, 1400:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1401:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1402:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1403:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Configure the Source and Destination addresses. 1404:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @note This API must not be called when the DMA stream is enabled. 1405:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll M0AR M0A LL_DMA_ConfigAddresses\n 1406:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * PAR PA LL_DMA_ConfigAddresses 1407:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 1408:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: 1409:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 1410:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 1411:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 1412:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 1413:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 1414:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 1415:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 1416:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 1417:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param SrcAddress Between 0 to 0xFFFFFFFF 1418:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DstAddress Between 0 to 0xFFFFFFFF 1419:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Direction This parameter can be one of the following values: 1420:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY 1421:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH 1422:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY 1423:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 1424:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1425:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ConfigAddresses(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t SrcAddress 1426:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1427:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /* Direction Memory to Periph */ 1428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** if (Direction == LL_DMA_DIRECTION_MEMORY_TO_PERIPH) 1429:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1430:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR 1431:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR, 1432:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1433:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /* Direction Periph to Memory and Memory to Memory */ 1434:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** else 1435:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1436:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR, 1437:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR 1438:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1439:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1440:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1441:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1442:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Set the Memory address. ARM GAS /tmp/ccdsDELB.s page 327 1443:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll M0AR M0A LL_DMA_SetMemoryAddress 1444:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMO 1445:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @note This API must not be called when the DMA channel is enabled. 1446:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 1447:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: 1448:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 1449:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 1450:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 1451:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 1452:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 1453:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 1454:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 1455:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 1456:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param MemoryAddress Between 0 to 0xFFFFFFFF 1457:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 1458:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1459:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_SetMemoryAddress(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t MemoryAdd 1460:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1461:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR, 1462:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1464:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1465:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Set the Peripheral address. 1466:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll PAR PA LL_DMA_SetPeriphAddress 1467:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMO 1468:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @note This API must not be called when the DMA channel is enabled. 1469:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 1470:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: 1471:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 1472:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 1473:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 1474:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 1475:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 1476:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 1477:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 1478:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 1479:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param PeriphAddress Between 0 to 0xFFFFFFFF 1480:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 1481:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1482:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_SetPeriphAddress(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t PeriphAdd 1483:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1484:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR, P 1485:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1486:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1487:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1488:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get the Memory address. 1489:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll M0AR M0A LL_DMA_GetMemoryAddress 1490:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMO 1491:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 1492:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: 1493:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 1494:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 1495:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 1496:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 1497:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 1498:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 1499:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 ARM GAS /tmp/ccdsDELB.s page 328 1500:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 1501:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval Between 0 to 0xFFFFFFFF 1502:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1503:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress(DMA_TypeDef* DMAx, uint32_t Stream) 1504:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1505:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))- 1506:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1507:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1508:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1509:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get the Peripheral address. 1510:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll PAR PA LL_DMA_GetPeriphAddress 1511:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMO 1512:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 1513:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: 1514:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 1515:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 1516:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 1517:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 1518:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 1519:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 1520:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 1521:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 1522:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval Between 0 to 0xFFFFFFFF 1523:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1524:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress(DMA_TypeDef* DMAx, uint32_t Stream) 1525:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1526:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_REG(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream]))) 1527:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1528:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1529:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1530:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Set the Memory to Memory Source address. 1531:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll PAR PA LL_DMA_SetM2MSrcAddress 1532:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only. 1533:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @note This API must not be called when the DMA channel is enabled. 1534:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 1535:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: 1536:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 1537:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 1538:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 1539:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 1540:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 1541:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 1542:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 1543:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 1544:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param MemoryAddress Between 0 to 0xFFFFFFFF 1545:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 1546:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1547:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_SetM2MSrcAddress(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t MemoryAdd 1548:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1549:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR, M 1550:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1551:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1552:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1553:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Set the Memory to Memory Destination address. 1554:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll M0AR M0A LL_DMA_SetM2MDstAddress 1555:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only. 1556:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @note This API must not be called when the DMA channel is enabled. ARM GAS /tmp/ccdsDELB.s page 329 1557:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 1558:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: 1559:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 1560:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 1561:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 1562:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 1563:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 1564:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 1565:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 1566:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 1567:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param MemoryAddress Between 0 to 0xFFFFFFFF 1568:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 1569:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1570:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_SetM2MDstAddress(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t MemoryAdd 1571:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1572:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR 1573:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1574:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1575:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1576:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get the Memory to Memory Source address. 1577:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll PAR PA LL_DMA_GetM2MSrcAddress 1578:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only. 1579:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 1580:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: 1581:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 1582:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 1583:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 1584:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 1585:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 1586:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 1587:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 1588:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 1589:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval Between 0 to 0xFFFFFFFF 1590:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1591:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress(DMA_TypeDef* DMAx, uint32_t Stream) 1592:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1593:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_REG(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])) 1594:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1595:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1596:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1597:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get the Memory to Memory Destination address. 1598:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll M0AR M0A LL_DMA_GetM2MDstAddress 1599:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only. 1600:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 1601:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: 1602:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 1603:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 1604:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 1605:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 1606:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 1607:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 1608:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 1609:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 1610:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval Between 0 to 0xFFFFFFFF 1611:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1612:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(DMA_TypeDef* DMAx, uint32_t Stream) 1613:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { ARM GAS /tmp/ccdsDELB.s page 330 1614:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))-> 1615:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1616:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1617:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1618:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Set Memory 1 address (used in case of Double buffer mode). 1619:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll M1AR M1A LL_DMA_SetMemory1Address 1620:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 1621:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: 1622:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 1623:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 1624:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 1625:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 1626:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 1627:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 1628:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 1629:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 1630:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Address Between 0 to 0xFFFFFFFF 1631:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 1632:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1633:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_SetMemory1Address(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Address) 1634:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1635:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M1AR, 1636:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1637:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1638:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1639:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Memory 1 address (used in case of Double buffer mode). 1640:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll M1AR M1A LL_DMA_GetMemory1Address 1641:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 1642:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: 1643:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 1644:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 1645:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 1646:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 1647:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 1648:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 1649:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 1650:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 1651:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval Between 0 to 0xFFFFFFFF 1652:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1653:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_GetMemory1Address(DMA_TypeDef *DMAx, uint32_t Stream) 1654:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1655:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M1AR); 1656:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1657:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1658:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1659:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @} 1660:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1661:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1662:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_EF_FLAG_Management FLAG_Management 1663:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @{ 1664:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1665:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1666:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1667:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 0 half transfer flag. 1668:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LISR HTIF0 LL_DMA_IsActiveFlag_HT0 1669:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 1670:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). ARM GAS /tmp/ccdsDELB.s page 331 1671:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1672:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT0(DMA_TypeDef *DMAx) 1673:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1674:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->LISR ,DMA_LISR_HTIF0)==(DMA_LISR_HTIF0)); 1675:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1676:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1677:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1678:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 1 half transfer flag. 1679:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LISR HTIF1 LL_DMA_IsActiveFlag_HT1 1680:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 1681:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). 1682:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1683:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT1(DMA_TypeDef *DMAx) 1684:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1685:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->LISR ,DMA_LISR_HTIF1)==(DMA_LISR_HTIF1)); 1686:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1687:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1688:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1689:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 2 half transfer flag. 1690:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LISR HTIF2 LL_DMA_IsActiveFlag_HT2 1691:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 1692:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). 1693:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1694:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT2(DMA_TypeDef *DMAx) 1695:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1696:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->LISR ,DMA_LISR_HTIF2)==(DMA_LISR_HTIF2)); 1697:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1698:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1699:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1700:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 3 half transfer flag. 1701:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LISR HTIF3 LL_DMA_IsActiveFlag_HT3 1702:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 1703:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). 1704:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1705:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT3(DMA_TypeDef *DMAx) 1706:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1707:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->LISR ,DMA_LISR_HTIF3)==(DMA_LISR_HTIF3)); 1708:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1709:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1710:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1711:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 4 half transfer flag. 1712:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HISR HTIF4 LL_DMA_IsActiveFlag_HT4 1713:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 1714:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). 1715:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1716:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT4(DMA_TypeDef *DMAx) 1717:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1718:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->HISR ,DMA_HISR_HTIF4)==(DMA_HISR_HTIF4)); 1719:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1720:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1721:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1722:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 5 half transfer flag. 1723:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HISR HTIF0 LL_DMA_IsActiveFlag_HT5 1724:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 1725:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). 1726:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1727:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT5(DMA_TypeDef *DMAx) ARM GAS /tmp/ccdsDELB.s page 332 1728:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1729:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->HISR ,DMA_HISR_HTIF5)==(DMA_HISR_HTIF5)); 1730:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1731:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1732:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1733:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 6 half transfer flag. 1734:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HISR HTIF6 LL_DMA_IsActiveFlag_HT6 1735:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 1736:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). 1737:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1738:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT6(DMA_TypeDef *DMAx) 1739:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1740:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->HISR ,DMA_HISR_HTIF6)==(DMA_HISR_HTIF6)); 1741:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1742:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1743:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1744:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 7 half transfer flag. 1745:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HISR HTIF7 LL_DMA_IsActiveFlag_HT7 1746:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 1747:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). 1748:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1749:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT7(DMA_TypeDef *DMAx) 1750:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1751:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->HISR ,DMA_HISR_HTIF7)==(DMA_HISR_HTIF7)); 1752:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1753:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1754:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1755:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 0 transfer complete flag. 1756:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LISR TCIF0 LL_DMA_IsActiveFlag_TC0 1757:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 1758:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). 1759:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1760:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC0(DMA_TypeDef *DMAx) 1761:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1762:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->LISR ,DMA_LISR_TCIF0)==(DMA_LISR_TCIF0)); 1763:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1764:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1765:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1766:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 1 transfer complete flag. 1767:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LISR TCIF1 LL_DMA_IsActiveFlag_TC1 1768:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 1769:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). 1770:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1771:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC1(DMA_TypeDef *DMAx) 1772:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1773:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->LISR ,DMA_LISR_TCIF1)==(DMA_LISR_TCIF1)); 1774:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1775:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1776:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1777:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 2 transfer complete flag. 1778:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LISR TCIF2 LL_DMA_IsActiveFlag_TC2 1779:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 1780:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). 1781:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1782:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC2(DMA_TypeDef *DMAx) 1783:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1784:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->LISR ,DMA_LISR_TCIF2)==(DMA_LISR_TCIF2)); ARM GAS /tmp/ccdsDELB.s page 333 1785:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1786:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1787:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1788:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 3 transfer complete flag. 1789:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LISR TCIF3 LL_DMA_IsActiveFlag_TC3 1790:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 1791:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). 1792:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1793:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC3(DMA_TypeDef *DMAx) 1794:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1795:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->LISR ,DMA_LISR_TCIF3)==(DMA_LISR_TCIF3)); 1796:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1797:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1798:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1799:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 4 transfer complete flag. 1800:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HISR TCIF4 LL_DMA_IsActiveFlag_TC4 1801:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 1802:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). 1803:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1804:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC4(DMA_TypeDef *DMAx) 1805:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1806:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->HISR ,DMA_HISR_TCIF4)==(DMA_HISR_TCIF4)); 1807:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1808:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1809:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1810:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 5 transfer complete flag. 1811:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HISR TCIF0 LL_DMA_IsActiveFlag_TC5 1812:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 1813:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). 1814:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1815:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC5(DMA_TypeDef *DMAx) 1816:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1817:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->HISR ,DMA_HISR_TCIF5)==(DMA_HISR_TCIF5)); 1818:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1819:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1820:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1821:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 6 transfer complete flag. 1822:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HISR TCIF6 LL_DMA_IsActiveFlag_TC6 1823:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 1824:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). 1825:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1826:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC6(DMA_TypeDef *DMAx) 1827:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1828:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->HISR ,DMA_HISR_TCIF6)==(DMA_HISR_TCIF6)); 1829:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1830:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1831:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1832:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 7 transfer complete flag. 1833:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HISR TCIF7 LL_DMA_IsActiveFlag_TC7 1834:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 1835:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). 1836:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1837:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC7(DMA_TypeDef *DMAx) 1838:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1839:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->HISR ,DMA_HISR_TCIF7)==(DMA_HISR_TCIF7)); 1840:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1841:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** ARM GAS /tmp/ccdsDELB.s page 334 1842:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1843:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 0 transfer error flag. 1844:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LISR TEIF0 LL_DMA_IsActiveFlag_TE0 1845:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 1846:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). 1847:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1848:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE0(DMA_TypeDef *DMAx) 1849:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1850:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->LISR ,DMA_LISR_TEIF0)==(DMA_LISR_TEIF0)); 1851:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1852:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1853:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1854:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 1 transfer error flag. 1855:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LISR TEIF1 LL_DMA_IsActiveFlag_TE1 1856:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 1857:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). 1858:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1859:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE1(DMA_TypeDef *DMAx) 1860:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1861:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->LISR ,DMA_LISR_TEIF1)==(DMA_LISR_TEIF1)); 1862:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1863:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1864:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1865:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 2 transfer error flag. 1866:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LISR TEIF2 LL_DMA_IsActiveFlag_TE2 1867:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 1868:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). 1869:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1870:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE2(DMA_TypeDef *DMAx) 1871:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1872:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->LISR ,DMA_LISR_TEIF2)==(DMA_LISR_TEIF2)); 1873:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1874:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1875:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1876:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 3 transfer error flag. 1877:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LISR TEIF3 LL_DMA_IsActiveFlag_TE3 1878:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 1879:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). 1880:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1881:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE3(DMA_TypeDef *DMAx) 1882:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1883:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->LISR ,DMA_LISR_TEIF3)==(DMA_LISR_TEIF3)); 1884:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1885:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1886:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1887:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 4 transfer error flag. 1888:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HISR TEIF4 LL_DMA_IsActiveFlag_TE4 1889:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 1890:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). 1891:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1892:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE4(DMA_TypeDef *DMAx) 1893:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1894:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->HISR ,DMA_HISR_TEIF4)==(DMA_HISR_TEIF4)); 1895:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1896:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1897:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1898:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 5 transfer error flag. ARM GAS /tmp/ccdsDELB.s page 335 1899:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HISR TEIF0 LL_DMA_IsActiveFlag_TE5 1900:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 1901:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). 1902:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1903:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE5(DMA_TypeDef *DMAx) 1904:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1905:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->HISR ,DMA_HISR_TEIF5)==(DMA_HISR_TEIF5)); 1906:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1908:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1909:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 6 transfer error flag. 1910:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HISR TEIF6 LL_DMA_IsActiveFlag_TE6 1911:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 1912:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). 1913:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1914:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE6(DMA_TypeDef *DMAx) 1915:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1916:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->HISR ,DMA_HISR_TEIF6)==(DMA_HISR_TEIF6)); 1917:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1919:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1920:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 7 transfer error flag. 1921:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HISR TEIF7 LL_DMA_IsActiveFlag_TE7 1922:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 1923:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). 1924:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1925:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE7(DMA_TypeDef *DMAx) 1926:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1927:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->HISR ,DMA_HISR_TEIF7)==(DMA_HISR_TEIF7)); 1928:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1929:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1930:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1931:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 0 direct mode error flag. 1932:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LISR DMEIF0 LL_DMA_IsActiveFlag_DME0 1933:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 1934:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). 1935:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1936:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME0(DMA_TypeDef *DMAx) 1937:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1938:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->LISR ,DMA_LISR_DMEIF0)==(DMA_LISR_DMEIF0)); 1939:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1940:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1941:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1942:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 1 direct mode error flag. 1943:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LISR DMEIF1 LL_DMA_IsActiveFlag_DME1 1944:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 1945:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). 1946:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1947:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME1(DMA_TypeDef *DMAx) 1948:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1949:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->LISR ,DMA_LISR_DMEIF1)==(DMA_LISR_DMEIF1)); 1950:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1951:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1952:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1953:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 2 direct mode error flag. 1954:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LISR DMEIF2 LL_DMA_IsActiveFlag_DME2 1955:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance ARM GAS /tmp/ccdsDELB.s page 336 1956:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). 1957:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1958:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME2(DMA_TypeDef *DMAx) 1959:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1960:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->LISR ,DMA_LISR_DMEIF2)==(DMA_LISR_DMEIF2)); 1961:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1962:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1963:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1964:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 3 direct mode error flag. 1965:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LISR DMEIF3 LL_DMA_IsActiveFlag_DME3 1966:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 1967:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). 1968:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1969:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME3(DMA_TypeDef *DMAx) 1970:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1971:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->LISR ,DMA_LISR_DMEIF3)==(DMA_LISR_DMEIF3)); 1972:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1973:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1974:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1975:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 4 direct mode error flag. 1976:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HISR DMEIF4 LL_DMA_IsActiveFlag_DME4 1977:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 1978:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). 1979:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1980:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME4(DMA_TypeDef *DMAx) 1981:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1982:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->HISR ,DMA_HISR_DMEIF4)==(DMA_HISR_DMEIF4)); 1983:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1984:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1985:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1986:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 5 direct mode error flag. 1987:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HISR DMEIF0 LL_DMA_IsActiveFlag_DME5 1988:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 1989:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). 1990:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1991:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME5(DMA_TypeDef *DMAx) 1992:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1993:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->HISR ,DMA_HISR_DMEIF5)==(DMA_HISR_DMEIF5)); 1994:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1995:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1996:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1997:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 6 direct mode error flag. 1998:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HISR DMEIF6 LL_DMA_IsActiveFlag_DME6 1999:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 2000:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). 2001:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 2002:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME6(DMA_TypeDef *DMAx) 2003:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 2004:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->HISR ,DMA_HISR_DMEIF6)==(DMA_HISR_DMEIF6)); 2005:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 2006:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 2007:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 2008:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 7 direct mode error flag. 2009:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HISR DMEIF7 LL_DMA_IsActiveFlag_DME7 2010:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 2011:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). 2012:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ ARM GAS /tmp/ccdsDELB.s page 337 2013:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME7(DMA_TypeDef *DMAx) 2014:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 2015:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->HISR ,DMA_HISR_DMEIF7)==(DMA_HISR_DMEIF7)); 2016:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 2017:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 2018:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 2019:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 0 FIFO error flag. 2020:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LISR FEIF0 LL_DMA_IsActiveFlag_FE0 2021:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 2022:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). 2023:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 2024:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE0(DMA_TypeDef *DMAx) 2025:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 2026:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->LISR ,DMA_LISR_FEIF0)==(DMA_LISR_FEIF0)); 2027:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 2028:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 2029:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 2030:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 1 FIFO error flag. 2031:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LISR FEIF1 LL_DMA_IsActiveFlag_FE1 2032:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 2033:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). 2034:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 2035:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE1(DMA_TypeDef *DMAx) 2036:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 2037:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->LISR ,DMA_LISR_FEIF1)==(DMA_LISR_FEIF1)); 2038:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 2039:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 2040:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 2041:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 2 FIFO error flag. 2042:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LISR FEIF2 LL_DMA_IsActiveFlag_FE2 2043:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 2044:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). 2045:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 2046:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE2(DMA_TypeDef *DMAx) 2047:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 2048:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->LISR ,DMA_LISR_FEIF2)==(DMA_LISR_FEIF2)); 2049:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 2050:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 2051:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 2052:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 3 FIFO error flag. 2053:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LISR FEIF3 LL_DMA_IsActiveFlag_FE3 2054:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 2055:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). 2056:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 2057:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE3(DMA_TypeDef *DMAx) 2058:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 2059:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->LISR ,DMA_LISR_FEIF3)==(DMA_LISR_FEIF3)); 2060:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 2061:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 2062:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 2063:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 4 FIFO error flag. 2064:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HISR FEIF4 LL_DMA_IsActiveFlag_FE4 2065:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 2066:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). 2067:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 2068:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE4(DMA_TypeDef *DMAx) 2069:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { ARM GAS /tmp/ccdsDELB.s page 338 2070:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->HISR ,DMA_HISR_FEIF4)==(DMA_HISR_FEIF4)); 2071:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 2072:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 2073:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 2074:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 5 FIFO error flag. 2075:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HISR FEIF0 LL_DMA_IsActiveFlag_FE5 2076:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 2077:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). 2078:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 2079:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE5(DMA_TypeDef *DMAx) 2080:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 2081:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->HISR ,DMA_HISR_FEIF5)==(DMA_HISR_FEIF5)); 2082:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 2083:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 2084:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 2085:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 6 FIFO error flag. 2086:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HISR FEIF6 LL_DMA_IsActiveFlag_FE6 2087:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 2088:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). 2089:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 2090:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE6(DMA_TypeDef *DMAx) 2091:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 2092:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->HISR ,DMA_HISR_FEIF6)==(DMA_HISR_FEIF6)); 2093:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 2094:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 2095:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 2096:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 7 FIFO error flag. 2097:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HISR FEIF7 LL_DMA_IsActiveFlag_FE7 2098:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 2099:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). 2100:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 2101:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE7(DMA_TypeDef *DMAx) 2102:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 2103:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->HISR ,DMA_HISR_FEIF7)==(DMA_HISR_FEIF7)); 2104:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 2105:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 2106:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 2107:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Clear Stream 0 half transfer flag. 2108:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LIFCR CHTIF0 LL_DMA_ClearFlag_HT0 2109:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 2110:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 2111:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 2112:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_HT0(DMA_TypeDef *DMAx) 2113:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 2114:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CHTIF0); 2115:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 2116:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 2117:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 2118:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Clear Stream 1 half transfer flag. 2119:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LIFCR CHTIF1 LL_DMA_ClearFlag_HT1 2120:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 2121:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 2122:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 2123:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_HT1(DMA_TypeDef *DMAx) 2124:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 2125:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CHTIF1); 2126:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } ARM GAS /tmp/ccdsDELB.s page 339 2127:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 2128:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 2129:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Clear Stream 2 half transfer flag. 2130:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LIFCR CHTIF2 LL_DMA_ClearFlag_HT2 2131:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 2132:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 2133:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 2134:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_HT2(DMA_TypeDef *DMAx) 2135:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 2136:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CHTIF2); 2137:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 2138:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 2139:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 2140:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Clear Stream 3 half transfer flag. 2141:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LIFCR CHTIF3 LL_DMA_ClearFlag_HT3 2142:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 2143:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 2144:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 2145:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_HT3(DMA_TypeDef *DMAx) 2146:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 2147:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CHTIF3); 2148:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 2149:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 2150:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 2151:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Clear Stream 4 half transfer flag. 2152:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HIFCR CHTIF4 LL_DMA_ClearFlag_HT4 2153:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 2154:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 2155:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 2156:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_HT4(DMA_TypeDef *DMAx) 2157:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 2158:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CHTIF4); 2159:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 2160:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 2161:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 2162:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Clear Stream 5 half transfer flag. 2163:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HIFCR CHTIF5 LL_DMA_ClearFlag_HT5 2164:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 2165:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 2166:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 2167:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_HT5(DMA_TypeDef *DMAx) 2168:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 2169:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CHTIF5); 2170:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 2171:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 2172:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 2173:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Clear Stream 6 half transfer flag. 2174:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HIFCR CHTIF6 LL_DMA_ClearFlag_HT6 2175:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 2176:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 2177:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 2178:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_HT6(DMA_TypeDef *DMAx) 2179:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 2180:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CHTIF6); 2181:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 2182:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 2183:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** ARM GAS /tmp/ccdsDELB.s page 340 2184:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Clear Stream 7 half transfer flag. 2185:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HIFCR CHTIF7 LL_DMA_ClearFlag_HT7 2186:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 2187:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 2188:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 2189:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_HT7(DMA_TypeDef *DMAx) 2190:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 2191:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CHTIF7); 2192:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 2193:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 2194:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 2195:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Clear Stream 0 transfer complete flag. 2196:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LIFCR CTCIF0 LL_DMA_ClearFlag_TC0 2197:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 2198:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 2199:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 2200:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_TC0(DMA_TypeDef *DMAx) 2201:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 2202:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTCIF0); 2203:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 2204:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 2205:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 2206:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Clear Stream 1 transfer complete flag. 2207:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LIFCR CTCIF1 LL_DMA_ClearFlag_TC1 2208:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 2209:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 2210:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 2211:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_TC1(DMA_TypeDef *DMAx) 2212:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 2213:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTCIF1); 2214:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 2215:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 2216:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 2217:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Clear Stream 2 transfer complete flag. 2218:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LIFCR CTCIF2 LL_DMA_ClearFlag_TC2 2219:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 2220:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 2221:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 2222:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_TC2(DMA_TypeDef *DMAx) 2223:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 2224:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTCIF2); 2225:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 2226:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 2227:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 2228:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Clear Stream 3 transfer complete flag. 2229:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LIFCR CTCIF3 LL_DMA_ClearFlag_TC3 2230:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 2231:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 2232:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 2233:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_TC3(DMA_TypeDef *DMAx) 2234:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 2235:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTCIF3); 2236:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 2237:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 2238:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 2239:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Clear Stream 4 transfer complete flag. 2240:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HIFCR CTCIF4 LL_DMA_ClearFlag_TC4 ARM GAS /tmp/ccdsDELB.s page 341 2241:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 2242:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 2243:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 2244:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_TC4(DMA_TypeDef *DMAx) 2245:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 2246:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTCIF4); 2247:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 2248:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 2249:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 2250:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Clear Stream 5 transfer complete flag. 2251:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HIFCR CTCIF5 LL_DMA_ClearFlag_TC5 2252:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 2253:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 2254:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 2255:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_TC5(DMA_TypeDef *DMAx) 2256:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 2257:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTCIF5); 2258:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 2259:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 2260:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 2261:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Clear Stream 6 transfer complete flag. 2262:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HIFCR CTCIF6 LL_DMA_ClearFlag_TC6 2263:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 2264:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 2265:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 2266:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_TC6(DMA_TypeDef *DMAx) 2267:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 2268:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTCIF6); 2269:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 2270:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 2271:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 2272:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Clear Stream 7 transfer complete flag. 2273:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HIFCR CTCIF7 LL_DMA_ClearFlag_TC7 2274:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 2275:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 2276:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 2277:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_TC7(DMA_TypeDef *DMAx) 4689 .loc 6 2277 22 view .LVU1605 4690 .LBB468: 2278:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 2279:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTCIF7); 4691 .loc 6 2279 3 view .LVU1606 4692 00dc 4FF00062 mov r2, #134217728 4693 00e0 DA60 str r2, [r3, #12] 4694 .LVL338: 4695 .loc 6 2279 3 is_stmt 0 view .LVU1607 4696 .LBE468: 4697 .LBE467: 1520:Src/main.c **** LL_USART_EnableDMAReq_TX(USART1); 4698 .loc 2 1520 3 is_stmt 1 view .LVU1608 4699 .LBB469: 4700 .LBI469: 2280:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 2281:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 2282:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 2283:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Clear Stream 0 transfer error flag. 2284:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LIFCR CTEIF0 LL_DMA_ClearFlag_TE0 ARM GAS /tmp/ccdsDELB.s page 342 2285:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 2286:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 2287:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 2288:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_TE0(DMA_TypeDef *DMAx) 2289:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 2290:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTEIF0); 2291:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 2292:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 2293:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 2294:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Clear Stream 1 transfer error flag. 2295:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LIFCR CTEIF1 LL_DMA_ClearFlag_TE1 2296:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 2297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 2298:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 2299:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_TE1(DMA_TypeDef *DMAx) 2300:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 2301:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTEIF1); 2302:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 2303:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 2304:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 2305:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Clear Stream 2 transfer error flag. 2306:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LIFCR CTEIF2 LL_DMA_ClearFlag_TE2 2307:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 2308:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 2309:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 2310:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_TE2(DMA_TypeDef *DMAx) 2311:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 2312:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTEIF2); 2313:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 2314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 2315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 2316:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Clear Stream 3 transfer error flag. 2317:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LIFCR CTEIF3 LL_DMA_ClearFlag_TE3 2318:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 2319:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 2320:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 2321:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_TE3(DMA_TypeDef *DMAx) 2322:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 2323:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTEIF3); 2324:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 2325:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 2326:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 2327:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Clear Stream 4 transfer error flag. 2328:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HIFCR CTEIF4 LL_DMA_ClearFlag_TE4 2329:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 2330:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 2331:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 2332:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_TE4(DMA_TypeDef *DMAx) 2333:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 2334:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTEIF4); 2335:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 2336:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 2337:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 2338:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Clear Stream 5 transfer error flag. 2339:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HIFCR CTEIF5 LL_DMA_ClearFlag_TE5 2340:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 2341:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None ARM GAS /tmp/ccdsDELB.s page 343 2342:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 2343:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_TE5(DMA_TypeDef *DMAx) 2344:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 2345:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTEIF5); 2346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 2347:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 2348:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 2349:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Clear Stream 6 transfer error flag. 2350:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HIFCR CTEIF6 LL_DMA_ClearFlag_TE6 2351:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 2352:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 2353:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 2354:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_TE6(DMA_TypeDef *DMAx) 2355:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 2356:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTEIF6); 2357:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 2358:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 2359:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 2360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Clear Stream 7 transfer error flag. 2361:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HIFCR CTEIF7 LL_DMA_ClearFlag_TE7 2362:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 2363:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 2364:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 2365:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_TE7(DMA_TypeDef *DMAx) 4701 .loc 6 2365 22 view .LVU1609 4702 .LBB470: 2366:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 2367:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTEIF7); 4703 .loc 6 2367 3 view .LVU1610 4704 00e2 4FF00072 mov r2, #33554432 4705 00e6 DA60 str r2, [r3, #12] 4706 .LVL339: 4707 .L173: 4708 .loc 6 2367 3 is_stmt 0 view .LVU1611 4709 .LBE470: 4710 .LBE469: 4711 .file 7 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h" 1:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ****************************************************************************** 3:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @file stm32f7xx_ll_usart.h 4:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @author MCD Application Team 5:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Header file of USART LL module. 6:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ****************************************************************************** 7:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @attention 8:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * 9:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Copyright (c) 2017 STMicroelectronics. 10:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * All rights reserved. 11:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * 12:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * This software is licensed under terms that can be found in the LICENSE file 13:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * in the root directory of this software component. 14:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * If no LICENSE file comes with this software, it is provided AS-IS. 15:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * 16:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ****************************************************************************** 17:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 18:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 19:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* Define to prevent recursive inclusion -------------------------------------*/ 20:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #ifndef STM32F7xx_LL_USART_H ARM GAS /tmp/ccdsDELB.s page 344 21:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define STM32F7xx_LL_USART_H 22:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 23:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #ifdef __cplusplus 24:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** extern "C" { 25:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif 26:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 27:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* Includes ------------------------------------------------------------------*/ 28:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #include "stm32f7xx.h" 29:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 30:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @addtogroup STM32F7xx_LL_Driver 31:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ 32:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 33:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 34:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART1) || defined(USART2) || defined(USART3) || defined(USART6) \ 35:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** || defined(UART4) || defined(UART5) || defined(UART7) || defined(UART8) 36:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 37:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL USART 38:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ 39:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 40:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 41:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* Private types -------------------------------------------------------------*/ 42:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* Private variables ---------------------------------------------------------*/ 43:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 44:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* Private constants ---------------------------------------------------------*/ 45:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_Private_Constants USART Private Constants 46:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ 47:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 48:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 49:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} 50:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 51:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* Private macros ------------------------------------------------------------*/ 52:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USE_FULL_LL_DRIVER) 53:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_Private_Macros USART Private Macros 54:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ 55:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 56:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 57:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} 58:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 59:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /*USE_FULL_LL_DRIVER*/ 60:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 61:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* Exported types ------------------------------------------------------------*/ 62:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USE_FULL_LL_DRIVER) 63:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_ES_INIT USART Exported Init structures 64:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ 65:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 66:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 67:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 68:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief LL USART Init Structure definition 69:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 70:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** typedef struct 71:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 72:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 73:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** uint32_t BaudRate; /*!< This field defines expected Usart communication baud rat 74:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 75:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** This feature can be modified afterwards using unitary 76:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** function @ref LL_USART_SetBaudRate().*/ 77:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ARM GAS /tmp/ccdsDELB.s page 345 78:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** uint32_t DataWidth; /*!< Specifies the number of data bits transmitted or receive 79:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** This parameter can be a value of @ref USART_LL_EC_DATAWI 80:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 81:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** This feature can be modified afterwards using unitary 82:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** function @ref LL_USART_SetDataWidth().*/ 83:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 84:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** uint32_t StopBits; /*!< Specifies the number of stop bits transmitted. 85:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** This parameter can be a value of @ref USART_LL_EC_STOPBI 86:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 87:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** This feature can be modified afterwards using unitary 88:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** function @ref LL_USART_SetStopBitsLength().*/ 89:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 90:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** uint32_t Parity; /*!< Specifies the parity mode. 91:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** This parameter can be a value of @ref USART_LL_EC_PARITY 92:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 93:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** This feature can be modified afterwards using unitary 94:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** function @ref LL_USART_SetParity().*/ 95:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 96:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** uint32_t TransferDirection; /*!< Specifies whether the Receive and/or Transmit mode is en 97:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** This parameter can be a value of @ref USART_LL_EC_DIRECT 98:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 99:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** This feature can be modified afterwards using unitary 100:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** function @ref LL_USART_SetTransferDirection().*/ 101:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 102:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** uint32_t HardwareFlowControl; /*!< Specifies whether the hardware flow control mode is enab 103:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** This parameter can be a value of @ref USART_LL_EC_HWCONT 104:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 105:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** This feature can be modified afterwards using unitary 106:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** function @ref LL_USART_SetHWFlowCtrl().*/ 107:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 108:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** uint32_t OverSampling; /*!< Specifies whether USART oversampling mode is 16 or 8. 109:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** This parameter can be a value of @ref USART_LL_EC_OVERSA 110:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 111:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** This feature can be modified afterwards using unitary 112:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** function @ref LL_USART_SetOverSampling().*/ 113:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 114:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } LL_USART_InitTypeDef; 115:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 116:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 117:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief LL USART Clock Init Structure definition 118:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 119:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** typedef struct 120:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 121:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** uint32_t ClockOutput; /*!< Specifies whether the USART clock is enabled or disabled 122:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** This parameter can be a value of @ref USART_LL_EC_CLOCK. 123:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 124:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** USART HW configuration can be modified afterwards using 125:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** @ref LL_USART_EnableSCLKOutput() or @ref LL_USART_Disabl 126:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** For more details, refer to description of this function. 127:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 128:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** uint32_t ClockPolarity; /*!< Specifies the steady state of the serial clock. 129:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** This parameter can be a value of @ref USART_LL_EC_POLARI 130:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 131:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** USART HW configuration can be modified afterwards using 132:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** functions @ref LL_USART_SetClockPolarity(). 133:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** For more details, refer to description of this function. 134:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ARM GAS /tmp/ccdsDELB.s page 346 135:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** uint32_t ClockPhase; /*!< Specifies the clock transition on which the bit capture 136:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** This parameter can be a value of @ref USART_LL_EC_PHASE. 137:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 138:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** USART HW configuration can be modified afterwards using 139:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** functions @ref LL_USART_SetClockPhase(). 140:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** For more details, refer to description of this function. 141:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 142:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** uint32_t LastBitClockPulse; /*!< Specifies whether the clock pulse corresponding to the l 143:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** data bit (MSB) has to be output on the SCLK pin in synch 144:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** This parameter can be a value of @ref USART_LL_EC_LASTCL 145:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 146:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** USART HW configuration can be modified afterwards using 147:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** functions @ref LL_USART_SetLastClkPulseOutput(). 148:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** For more details, refer to description of this function. 149:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 150:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } LL_USART_ClockInitTypeDef; 151:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 152:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 153:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} 154:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 155:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USE_FULL_LL_DRIVER */ 156:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 157:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* Exported constants --------------------------------------------------------*/ 158:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_Exported_Constants USART Exported Constants 159:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ 160:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 161:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 162:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_CLEAR_FLAG Clear Flags Defines 163:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Flags defines which can be used with LL_USART_WriteReg function 164:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ 165:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 166:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ICR_PECF USART_ICR_PECF /*!< Parity error cle 167:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ICR_FECF USART_ICR_FECF /*!< Framing error cl 168:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ICR_NCF USART_ICR_NCF /*!< Noise error dete 169:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ICR_ORECF USART_ICR_ORECF /*!< Overrun error cl 170:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ICR_IDLECF USART_ICR_IDLECF /*!< Idle line detect 171:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ICR_TCCF USART_ICR_TCCF /*!< Transmission com 172:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_TCBGT_SUPPORT) 173:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ICR_TCBGTCF USART_ICR_TCBGTCF /*!< Transmission com 174:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_TCBGT_SUPPORT */ 175:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ICR_LBDCF USART_ICR_LBDCF /*!< LIN break detect 176:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ICR_CTSCF USART_ICR_CTSCF /*!< CTS clear flag * 177:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ICR_RTOCF USART_ICR_RTOCF /*!< Receiver timeout 178:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ICR_EOBCF USART_ICR_EOBCF /*!< End of block cle 179:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ICR_CMCF USART_ICR_CMCF /*!< Character match 180:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_CR1_UESM) 181:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_CR3_WUFIE) 182:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ICR_WUCF USART_ICR_WUCF /*!< Wakeup from Stop 183:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_CR3_WUFIE */ 184:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_CR1_UESM */ 185:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 186:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} 187:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 188:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 189:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_GET_FLAG Get Flags Defines 190:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Flags defines which can be used with LL_USART_ReadReg function 191:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ ARM GAS /tmp/ccdsDELB.s page 347 192:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 193:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_PE USART_ISR_PE /*!< Parity error fla 194:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_FE USART_ISR_FE /*!< Framing error fl 195:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_NE USART_ISR_NE /*!< Noise detected f 196:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_ORE USART_ISR_ORE /*!< Overrun error fl 197:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_IDLE USART_ISR_IDLE /*!< Idle line detect 198:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_RXNE USART_ISR_RXNE /*!< Read data regist 199:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_TC USART_ISR_TC /*!< Transmission com 200:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_TXE USART_ISR_TXE /*!< Transmit data re 201:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_LBDF USART_ISR_LBDF /*!< LIN break detect 202:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_CTSIF USART_ISR_CTSIF /*!< CTS interrupt fl 203:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_CTS USART_ISR_CTS /*!< CTS flag */ 204:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_RTOF USART_ISR_RTOF /*!< Receiver timeout 205:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_EOBF USART_ISR_EOBF /*!< End of block fla 206:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_ABRE USART_ISR_ABRE /*!< Auto baud rate e 207:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_ABRF USART_ISR_ABRF /*!< Auto baud rate f 208:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_BUSY USART_ISR_BUSY /*!< Busy flag */ 209:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_CMF USART_ISR_CMF /*!< Character match 210:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_SBKF USART_ISR_SBKF /*!< Send break flag 211:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_RWU USART_ISR_RWU /*!< Receiver wakeup 212:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_CR1_UESM) 213:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_CR3_WUFIE) 214:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_WUF USART_ISR_WUF /*!< Wakeup from Stop 215:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_CR3_WUFIE */ 216:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_CR1_UESM */ 217:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_TEACK USART_ISR_TEACK /*!< Transmit enable 218:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_ISR_REACK) 219:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_REACK USART_ISR_REACK /*!< Receive enable a 220:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_ISR_REACK */ 221:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_TCBGT_SUPPORT) 222:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_TCBGT USART_ISR_TCBGT /*!< Transmission com 223:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_TCBGT_SUPPORT */ 224:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 225:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} 226:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 227:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 228:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_IT IT Defines 229:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief IT defines which can be used with LL_USART_ReadReg and LL_USART_WriteReg functions 230:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ 231:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 232:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_CR1_IDLEIE USART_CR1_IDLEIE /*!< IDLE interrupt e 233:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_CR1_RXNEIE USART_CR1_RXNEIE /*!< Read data regist 234:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_CR1_TCIE USART_CR1_TCIE /*!< Transmission com 235:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_CR1_TXEIE USART_CR1_TXEIE /*!< Transmit data re 236:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_CR1_PEIE USART_CR1_PEIE /*!< Parity error */ 237:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_CR1_CMIE USART_CR1_CMIE /*!< Character match 238:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_CR1_RTOIE USART_CR1_RTOIE /*!< Receiver timeout 239:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_CR1_EOBIE USART_CR1_EOBIE /*!< End of Block int 240:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_CR2_LBDIE USART_CR2_LBDIE /*!< LIN break detect 241:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_CR3_EIE USART_CR3_EIE /*!< Error interrupt 242:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_CR3_CTSIE USART_CR3_CTSIE /*!< CTS interrupt en 243:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_CR1_UESM) 244:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_CR3_WUFIE) 245:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_CR3_WUFIE USART_CR3_WUFIE /*!< Wakeup from Stop 246:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_CR3_WUFIE */ 247:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_CR1_UESM */ 248:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_TCBGT_SUPPORT) ARM GAS /tmp/ccdsDELB.s page 348 249:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_CR3_TCBGTIE USART_CR3_TCBGTIE /*!< Transmission com 250:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_TCBGT_SUPPORT */ 251:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 252:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} 253:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 254:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 255:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_DIRECTION Communication Direction 256:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ 257:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 258:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_DIRECTION_NONE 0x00000000U /*!< Transmitter 259:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_DIRECTION_RX USART_CR1_RE /*!< Transmitter 260:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_DIRECTION_TX USART_CR1_TE /*!< Transmitter 261:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_DIRECTION_TX_RX (USART_CR1_TE |USART_CR1_RE) /*!< Transmitter 262:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 263:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} 264:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 265:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 266:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_PARITY Parity Control 267:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ 268:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 269:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_PARITY_NONE 0x00000000U /*!< Parity co 270:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_PARITY_EVEN USART_CR1_PCE /*!< Parity co 271:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS) /*!< Parity co 272:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 273:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} 274:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 275:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 276:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_WAKEUP Wakeup 277:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ 278:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 279:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_WAKEUP_IDLELINE 0x00000000U /*!< USART wake up from Mute 280:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_WAKEUP_ADDRESSMARK USART_CR1_WAKE /*!< USART wake up from Mute 281:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 282:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} 283:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 284:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 285:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_DATAWIDTH Datawidth 286:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ 287:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 288:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_DATAWIDTH_7B USART_CR1_M1 /*!< 7 bits word length : S 289:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_DATAWIDTH_8B 0x00000000U /*!< 8 bits word length : S 290:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_DATAWIDTH_9B USART_CR1_M0 /*!< 9 bits word length : S 291:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 292:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} 293:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 294:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 295:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_OVERSAMPLING Oversampling 296:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ 297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 298:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_OVERSAMPLING_16 0x00000000U /*!< Oversampling by 16 */ 299:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_OVERSAMPLING_8 USART_CR1_OVER8 /*!< Oversampling by 8 */ 300:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 301:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} 302:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 303:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 304:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USE_FULL_LL_DRIVER) 305:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_CLOCK Clock Signal ARM GAS /tmp/ccdsDELB.s page 349 306:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ 307:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 308:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 309:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_CLOCK_DISABLE 0x00000000U /*!< Clock signal not provid 310:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_CLOCK_ENABLE USART_CR2_CLKEN /*!< Clock signal provided * 311:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 312:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} 313:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /*USE_FULL_LL_DRIVER*/ 315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 316:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_LASTCLKPULSE Last Clock Pulse 317:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ 318:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 319:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_LASTCLKPULSE_NO_OUTPUT 0x00000000U /*!< The clock pulse of the l 320:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_LASTCLKPULSE_OUTPUT USART_CR2_LBCL /*!< The clock pulse of the l 321:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 322:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} 323:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 324:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 325:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_PHASE Clock Phase 326:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ 327:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 328:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_PHASE_1EDGE 0x00000000U /*!< The first clock transiti 329:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_PHASE_2EDGE USART_CR2_CPHA /*!< The second clock transit 330:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 331:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} 332:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 333:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 334:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_POLARITY Clock Polarity 335:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ 336:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 337:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_POLARITY_LOW 0x00000000U /*!< Steady low value on SCLK 338:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_POLARITY_HIGH USART_CR2_CPOL /*!< Steady high value on SCL 339:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 340:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} 341:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 342:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 343:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_STOPBITS Stop Bits 344:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ 345:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_STOPBITS_0_5 USART_CR2_STOP_0 /*!< 0.5 347:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_STOPBITS_1 0x00000000U /*!< 1 s 348:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_STOPBITS_1_5 (USART_CR2_STOP_0 | USART_CR2_STOP_1) /*!< 1.5 349:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_STOPBITS_2 USART_CR2_STOP_1 /*!< 2 s 350:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 351:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} 352:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 353:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 354:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_TXRX TX RX Pins Swap 355:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ 356:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 357:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_TXRX_STANDARD 0x00000000U /*!< TX/RX pins are used as d 358:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_TXRX_SWAPPED (USART_CR2_SWAP) /*!< TX and RX pins functions 359:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} 361:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 362:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ARM GAS /tmp/ccdsDELB.s page 350 363:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_RXPIN_LEVEL RX Pin Active Level Inversion 364:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ 365:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 366:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_RXPIN_LEVEL_STANDARD 0x00000000U /*!< RX pin signal works usin 367:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_RXPIN_LEVEL_INVERTED (USART_CR2_RXINV) /*!< RX pin signal values are 368:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 369:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} 370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 371:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_TXPIN_LEVEL TX Pin Active Level Inversion 373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ 374:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 375:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_TXPIN_LEVEL_STANDARD 0x00000000U /*!< TX pin signal works usin 376:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_TXPIN_LEVEL_INVERTED (USART_CR2_TXINV) /*!< TX pin signal values are 377:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 378:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} 379:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 380:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 381:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_BINARY_LOGIC Binary Data Inversion 382:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ 383:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 384:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_BINARY_LOGIC_POSITIVE 0x00000000U /*!< Logical data from the da 385:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_BINARY_LOGIC_NEGATIVE USART_CR2_DATAINV /*!< Logical data from the da 386:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 387:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} 388:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 389:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 390:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_BITORDER Bit Order 391:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ 392:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 393:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_BITORDER_LSBFIRST 0x00000000U /*!< data is transmitted/rece 394:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_BITORDER_MSBFIRST USART_CR2_MSBFIRST /*!< data is transmitted/rece 395:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 396:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} 397:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 398:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 399:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_AUTOBAUD_DETECT_ON Autobaud Detection 400:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ 401:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 402:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_AUTOBAUD_DETECT_ON_STARTBIT 0x00000000U /*!< Me 403:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_AUTOBAUD_DETECT_ON_FALLINGEDGE USART_CR2_ABRMODE_0 /*!< Fa 404:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME USART_CR2_ABRMODE_1 /*!< 0x 405:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_AUTOBAUD_DETECT_ON_55_FRAME (USART_CR2_ABRMODE_1 | USART_CR2_ABRMODE_0) /*!< 0x 406:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 407:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} 408:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 409:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 410:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_ADDRESS_DETECT Address Length Detection 411:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ 412:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 413:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ADDRESS_DETECT_4B 0x00000000U /*!< 4-bit address detection 414:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ADDRESS_DETECT_7B USART_CR2_ADDM7 /*!< 7-bit address detection 415:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 416:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} 417:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 418:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 419:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_HWCONTROL Hardware Control ARM GAS /tmp/ccdsDELB.s page 351 420:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ 421:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 422:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_HWCONTROL_NONE 0x00000000U /*!< CTS and R 423:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_HWCONTROL_RTS USART_CR3_RTSE /*!< RTS outpu 424:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_HWCONTROL_CTS USART_CR3_CTSE /*!< CTS mode 425:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_HWCONTROL_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE) /*!< CTS and R 426:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 427:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} 428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 429:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 430:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_CR1_UESM) 431:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_CR3_WUS) 432:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_WAKEUP_ON Wakeup Activation 433:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ 434:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 435:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_WAKEUP_ON_ADDRESS 0x00000000U /*!< Wake u 436:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_WAKEUP_ON_STARTBIT USART_CR3_WUS_1 /*!< Wake u 437:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_WAKEUP_ON_RXNE (USART_CR3_WUS_0 | USART_CR3_WUS_1) /*!< Wake u 438:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 439:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} 440:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 441:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 442:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_CR3_WUS */ 443:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_CR1_UESM */ 444:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_IRDA_POWER IrDA Power 445:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ 446:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 447:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_IRDA_POWER_NORMAL 0x00000000U /*!< IrDA normal power mode * 448:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_IRDA_POWER_LOW USART_CR3_IRLP /*!< IrDA low power mode */ 449:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 450:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} 451:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 452:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 453:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_LINBREAK_DETECT LIN Break Detection Length 454:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ 455:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 456:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_LINBREAK_DETECT_10B 0x00000000U /*!< 10-bit break detection m 457:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_LINBREAK_DETECT_11B USART_CR2_LBDL /*!< 11-bit break detection m 458:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 459:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} 460:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 461:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 462:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_DE_POLARITY Driver Enable Polarity 463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ 464:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 465:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_DE_POLARITY_HIGH 0x00000000U /*!< DE signal is active high 466:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_DE_POLARITY_LOW USART_CR3_DEP /*!< DE signal is active low 467:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 468:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} 469:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 470:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 471:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_DMA_REG_DATA DMA Register Data 472:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ 473:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 474:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_DMA_REG_DATA_TRANSMIT 0x00000000U /*!< Get address of data regis 475:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_DMA_REG_DATA_RECEIVE 0x00000001U /*!< Get address of data regis 476:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** ARM GAS /tmp/ccdsDELB.s page 352 477:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} 478:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 479:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 480:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 481:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} 482:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 483:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 484:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* Exported macro ------------------------------------------------------------*/ 485:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_Exported_Macros USART Exported Macros 486:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ 487:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 488:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 489:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EM_WRITE_READ Common Write and read registers Macros 490:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ 491:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 492:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 493:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 494:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Write a value in USART register 495:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param __INSTANCE__ USART Instance 496:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param __REG__ Register to be written 497:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param __VALUE__ Value to be written in the register 498:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 499:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 500:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VAL 501:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 502:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 503:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Read a value in USART register 504:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param __INSTANCE__ USART Instance 505:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param __REG__ Register to be read 506:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Register value 507:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 508:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) 509:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 510:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} 511:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 512:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 513:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EM_Exported_Macros_Helper Exported_Macros_Helper 514:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ 515:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 516:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 517:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 518:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Compute USARTDIV value according to Peripheral Clock and 519:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * expected Baud Rate in 8 bits sampling mode (32 bits value of USARTDIV is returned) 520:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param __PERIPHCLK__ Peripheral Clock frequency used for USART instance 521:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param __BAUDRATE__ Baud rate value to achieve 522:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval USARTDIV value to be used for BRR register filling in OverSampling_8 case 523:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 524:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define __LL_USART_DIV_SAMPLING8(__PERIPHCLK__, __BAUDRATE__) ((((__PERIPHCLK__)*2U)\ 525:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + ((__BAUDRATE__)/2U))/(__BAUDRATE_ 526:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 527:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 528:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Compute USARTDIV value according to Peripheral Clock and 529:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * expected Baud Rate in 16 bits sampling mode (32 bits value of USARTDIV is returned) 530:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param __PERIPHCLK__ Peripheral Clock frequency used for USART instance 531:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param __BAUDRATE__ Baud rate value to achieve 532:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval USARTDIV value to be used for BRR register filling in OverSampling_16 case 533:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ ARM GAS /tmp/ccdsDELB.s page 353 534:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define __LL_USART_DIV_SAMPLING16(__PERIPHCLK__, __BAUDRATE__) (((__PERIPHCLK__) + ((__BAUDRATE__)/ 535:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 536:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 537:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} 538:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 539:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 540:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 541:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} 542:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 543:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 544:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* Exported functions --------------------------------------------------------*/ 545:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 546:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_Exported_Functions USART Exported Functions 547:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ 548:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 549:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 550:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EF_Configuration Configuration functions 551:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ 552:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 553:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 554:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 555:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief USART Enable 556:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 UE LL_USART_Enable 557:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 558:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 559:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 560:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_Enable(USART_TypeDef *USARTx) 561:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 562:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** SET_BIT(USARTx->CR1, USART_CR1_UE); 563:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 564:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 565:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 566:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief USART Disable (all USART prescalers and outputs are disabled) 567:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note When USART is disabled, USART prescalers and outputs are stopped immediately, 568:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * and current operations are discarded. The configuration of the USART is kept, but all t 569:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * flags, in the USARTx_ISR are set to their default values. 570:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 UE LL_USART_Disable 571:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 572:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 573:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 574:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_Disable(USART_TypeDef *USARTx) 575:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 576:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** CLEAR_BIT(USARTx->CR1, USART_CR1_UE); 577:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 578:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 579:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 580:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Indicate if USART is enabled 581:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 UE LL_USART_IsEnabled 582:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 583:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). 584:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 585:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabled(const USART_TypeDef *USARTx) 586:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 587:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->CR1, USART_CR1_UE) == (USART_CR1_UE)) ? 1UL : 0UL); 588:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 589:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 590:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_CR1_UESM) ARM GAS /tmp/ccdsDELB.s page 354 591:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 592:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief USART enabled in STOP Mode. 593:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note When this function is enabled, USART is able to wake up the MCU from Stop mode, provide 594:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * USART clock selection is HSI or LSE in RCC. 595:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not 596:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Wake-up from Stop mode feature is supported by the USARTx instance. 597:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 UESM LL_USART_EnableInStopMode 598:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 599:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 600:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 601:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableInStopMode(USART_TypeDef *USARTx) 602:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 603:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_UESM); 604:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 605:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 606:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 607:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief USART disabled in STOP Mode. 608:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note When this function is disabled, USART is not able to wake up the MCU from Stop mode 609:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not 610:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Wake-up from Stop mode feature is supported by the USARTx instance. 611:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 UESM LL_USART_DisableInStopMode 612:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 613:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 614:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 615:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableInStopMode(USART_TypeDef *USARTx) 616:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 617:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_UESM); 618:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 619:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 620:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 621:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Indicate if USART is enabled in STOP Mode (able to wake up MCU from Stop mode or not) 622:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not 623:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Wake-up from Stop mode feature is supported by the USARTx instance. 624:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 UESM LL_USART_IsEnabledInStopMode 625:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 626:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). 627:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 628:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledInStopMode(const USART_TypeDef *USARTx) 629:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 630:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->CR1, USART_CR1_UESM) == (USART_CR1_UESM)) ? 1UL : 0UL); 631:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 632:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 633:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_CR3_UCESM) 634:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 635:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief USART Clock enabled in STOP Mode 636:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note When this function is called, USART Clock is enabled while in STOP mode 637:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 UCESM LL_USART_EnableClockInStopMode 638:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 639:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 640:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 641:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableClockInStopMode(USART_TypeDef *USARTx) 642:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 643:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_UCESM); 644:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 645:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 646:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 647:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief USART clock disabled in STOP Mode ARM GAS /tmp/ccdsDELB.s page 355 648:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note When this function is called, USART Clock is disabled while in STOP mode 649:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 UCESM LL_USART_DisableClockInStopMode 650:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 651:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 652:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 653:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableClockInStopMode(USART_TypeDef *USARTx) 654:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 655:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_UCESM); 656:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 657:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 658:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 659:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Indicate if USART clock is enabled in STOP Mode 660:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 UCESM LL_USART_IsClockEnabledInStopMode 661:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 662:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). 663:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 664:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsClockEnabledInStopMode(const USART_TypeDef *USARTx) 665:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 666:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return (READ_BIT(USARTx->CR3, USART_CR3_UCESM) == (USART_CR3_UCESM)); 667:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 668:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 669:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_CR3_UCESM */ 670:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_CR1_UESM*/ 671:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 672:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Receiver Enable (Receiver is enabled and begins searching for a start bit) 673:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 RE LL_USART_EnableDirectionRx 674:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 675:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 676:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 677:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableDirectionRx(USART_TypeDef *USARTx) 678:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 679:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_RE); 680:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 681:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 682:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 683:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Receiver Disable 684:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 RE LL_USART_DisableDirectionRx 685:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 686:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 687:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 688:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableDirectionRx(USART_TypeDef *USARTx) 689:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 690:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_RE); 691:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 692:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 693:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 694:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Transmitter Enable 695:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 TE LL_USART_EnableDirectionTx 696:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 697:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 698:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 699:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableDirectionTx(USART_TypeDef *USARTx) 700:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 701:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_TE); 702:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 703:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 704:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** ARM GAS /tmp/ccdsDELB.s page 356 705:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Transmitter Disable 706:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 TE LL_USART_DisableDirectionTx 707:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 708:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 709:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 710:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableDirectionTx(USART_TypeDef *USARTx) 711:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 712:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_TE); 713:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 714:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 715:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 716:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Configure simultaneously enabled/disabled states 717:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * of Transmitter and Receiver 718:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 RE LL_USART_SetTransferDirection\n 719:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR1 TE LL_USART_SetTransferDirection 720:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 721:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param TransferDirection This parameter can be one of the following values: 722:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_DIRECTION_NONE 723:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_DIRECTION_RX 724:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_DIRECTION_TX 725:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_DIRECTION_TX_RX 726:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 727:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 728:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetTransferDirection(USART_TypeDef *USARTx, uint32_t TransferDirectio 729:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 730:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_MODIFY_REG(USARTx->CR1, USART_CR1_RE | USART_CR1_TE, TransferDirection); 731:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 732:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 733:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 734:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Return enabled/disabled states of Transmitter and Receiver 735:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 RE LL_USART_GetTransferDirection\n 736:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR1 TE LL_USART_GetTransferDirection 737:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 738:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Returned value can be one of the following values: 739:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_DIRECTION_NONE 740:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_DIRECTION_RX 741:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_DIRECTION_TX 742:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_DIRECTION_TX_RX 743:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 744:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetTransferDirection(const USART_TypeDef *USARTx) 745:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 746:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_RE | USART_CR1_TE)); 747:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 748:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 749:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 750:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Configure Parity (enabled/disabled and parity mode if enabled). 751:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note This function selects if hardware parity control (generation and detection) is enabled 752:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * When the parity control is enabled (Odd or Even), computed parity bit is inserted at th 753:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * (9th or 8th bit depending on data width) and parity is checked on the received data. 754:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 PS LL_USART_SetParity\n 755:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR1 PCE LL_USART_SetParity 756:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 757:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param Parity This parameter can be one of the following values: 758:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_PARITY_NONE 759:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_PARITY_EVEN 760:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_PARITY_ODD 761:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None ARM GAS /tmp/ccdsDELB.s page 357 762:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 763:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetParity(USART_TypeDef *USARTx, uint32_t Parity) 764:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 765:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** MODIFY_REG(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE, Parity); 766:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 767:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 768:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 769:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Return Parity configuration (enabled/disabled and parity mode if enabled) 770:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 PS LL_USART_GetParity\n 771:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR1 PCE LL_USART_GetParity 772:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 773:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Returned value can be one of the following values: 774:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_PARITY_NONE 775:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_PARITY_EVEN 776:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_PARITY_ODD 777:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 778:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetParity(const USART_TypeDef *USARTx) 779:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 780:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE)); 781:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 782:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 783:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 784:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Set Receiver Wake Up method from Mute mode. 785:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 WAKE LL_USART_SetWakeUpMethod 786:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 787:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param Method This parameter can be one of the following values: 788:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_WAKEUP_IDLELINE 789:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_WAKEUP_ADDRESSMARK 790:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 791:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 792:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetWakeUpMethod(USART_TypeDef *USARTx, uint32_t Method) 793:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 794:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** MODIFY_REG(USARTx->CR1, USART_CR1_WAKE, Method); 795:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 796:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 797:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 798:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Return Receiver Wake Up method from Mute mode 799:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 WAKE LL_USART_GetWakeUpMethod 800:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 801:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Returned value can be one of the following values: 802:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_WAKEUP_IDLELINE 803:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_WAKEUP_ADDRESSMARK 804:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 805:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetWakeUpMethod(const USART_TypeDef *USARTx) 806:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 807:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_WAKE)); 808:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 809:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 810:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 811:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Set Word length (i.e. nb of data bits, excluding start and stop bits) 812:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 M0 LL_USART_SetDataWidth\n 813:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR1 M1 LL_USART_SetDataWidth 814:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 815:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param DataWidth This parameter can be one of the following values: 816:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_DATAWIDTH_7B 817:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_DATAWIDTH_8B 818:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_DATAWIDTH_9B ARM GAS /tmp/ccdsDELB.s page 358 819:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 820:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 821:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetDataWidth(USART_TypeDef *USARTx, uint32_t DataWidth) 822:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 823:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** MODIFY_REG(USARTx->CR1, USART_CR1_M, DataWidth); 824:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 825:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 826:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 827:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Return Word length (i.e. nb of data bits, excluding start and stop bits) 828:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 M0 LL_USART_GetDataWidth\n 829:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR1 M1 LL_USART_GetDataWidth 830:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 831:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Returned value can be one of the following values: 832:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_DATAWIDTH_7B 833:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_DATAWIDTH_8B 834:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_DATAWIDTH_9B 835:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 836:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetDataWidth(const USART_TypeDef *USARTx) 837:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 838:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_M)); 839:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 840:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 841:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 842:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Allow switch between Mute Mode and Active mode 843:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 MME LL_USART_EnableMuteMode 844:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 845:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 846:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 847:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableMuteMode(USART_TypeDef *USARTx) 848:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 849:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_MME); 850:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 851:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 852:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 853:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Prevent Mute Mode use. Set Receiver in active mode permanently. 854:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 MME LL_USART_DisableMuteMode 855:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 856:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 857:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 858:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableMuteMode(USART_TypeDef *USARTx) 859:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 860:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_MME); 861:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 862:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 863:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 864:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Indicate if switch between Mute Mode and Active mode is allowed 865:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 MME LL_USART_IsEnabledMuteMode 866:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 867:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). 868:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 869:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledMuteMode(const USART_TypeDef *USARTx) 870:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 871:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->CR1, USART_CR1_MME) == (USART_CR1_MME)) ? 1UL : 0UL); 872:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 873:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 874:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 875:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Set Oversampling to 8-bit or 16-bit mode ARM GAS /tmp/ccdsDELB.s page 359 876:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 OVER8 LL_USART_SetOverSampling 877:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 878:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param OverSampling This parameter can be one of the following values: 879:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_OVERSAMPLING_16 880:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_OVERSAMPLING_8 881:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 882:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 883:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetOverSampling(USART_TypeDef *USARTx, uint32_t OverSampling) 884:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 885:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** MODIFY_REG(USARTx->CR1, USART_CR1_OVER8, OverSampling); 886:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 887:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 888:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 889:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Return Oversampling mode 890:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 OVER8 LL_USART_GetOverSampling 891:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 892:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Returned value can be one of the following values: 893:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_OVERSAMPLING_16 894:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_OVERSAMPLING_8 895:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 896:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetOverSampling(const USART_TypeDef *USARTx) 897:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 898:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_OVER8)); 899:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 900:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 901:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 902:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Configure if Clock pulse of the last data bit is output to the SCLK pin or not 903:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not 904:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Synchronous mode is supported by the USARTx instance. 905:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 LBCL LL_USART_SetLastClkPulseOutput 906:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param LastBitClockPulse This parameter can be one of the following values: 908:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT 909:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_LASTCLKPULSE_OUTPUT 910:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 911:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 912:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetLastClkPulseOutput(USART_TypeDef *USARTx, uint32_t LastBitClockPul 913:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 914:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** MODIFY_REG(USARTx->CR2, USART_CR2_LBCL, LastBitClockPulse); 915:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 916:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 917:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Retrieve Clock pulse of the last data bit output configuration 919:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * (Last bit Clock pulse output to the SCLK pin or not) 920:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not 921:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Synchronous mode is supported by the USARTx instance. 922:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 LBCL LL_USART_GetLastClkPulseOutput 923:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 924:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Returned value can be one of the following values: 925:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT 926:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_LASTCLKPULSE_OUTPUT 927:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 928:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetLastClkPulseOutput(const USART_TypeDef *USARTx) 929:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 930:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_LBCL)); 931:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 932:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ARM GAS /tmp/ccdsDELB.s page 360 933:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 934:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Select the phase of the clock output on the SCLK pin in synchronous mode 935:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not 936:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Synchronous mode is supported by the USARTx instance. 937:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 CPHA LL_USART_SetClockPhase 938:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 939:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param ClockPhase This parameter can be one of the following values: 940:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_PHASE_1EDGE 941:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_PHASE_2EDGE 942:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 943:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 944:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetClockPhase(USART_TypeDef *USARTx, uint32_t ClockPhase) 945:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 946:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** MODIFY_REG(USARTx->CR2, USART_CR2_CPHA, ClockPhase); 947:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 948:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 949:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 950:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Return phase of the clock output on the SCLK pin in synchronous mode 951:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not 952:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Synchronous mode is supported by the USARTx instance. 953:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 CPHA LL_USART_GetClockPhase 954:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 955:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Returned value can be one of the following values: 956:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_PHASE_1EDGE 957:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_PHASE_2EDGE 958:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 959:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetClockPhase(const USART_TypeDef *USARTx) 960:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 961:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_CPHA)); 962:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 963:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 964:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 965:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Select the polarity of the clock output on the SCLK pin in synchronous mode 966:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not 967:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Synchronous mode is supported by the USARTx instance. 968:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 CPOL LL_USART_SetClockPolarity 969:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 970:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param ClockPolarity This parameter can be one of the following values: 971:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_POLARITY_LOW 972:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_POLARITY_HIGH 973:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 974:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 975:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetClockPolarity(USART_TypeDef *USARTx, uint32_t ClockPolarity) 976:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 977:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** MODIFY_REG(USARTx->CR2, USART_CR2_CPOL, ClockPolarity); 978:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 979:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 980:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 981:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Return polarity of the clock output on the SCLK pin in synchronous mode 982:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not 983:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Synchronous mode is supported by the USARTx instance. 984:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 CPOL LL_USART_GetClockPolarity 985:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 986:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Returned value can be one of the following values: 987:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_POLARITY_LOW 988:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_POLARITY_HIGH 989:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ ARM GAS /tmp/ccdsDELB.s page 361 990:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetClockPolarity(const USART_TypeDef *USARTx) 991:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 992:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_CPOL)); 993:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 994:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 995:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 996:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Configure Clock signal format (Phase Polarity and choice about output of last bit clock 997:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not 998:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Synchronous mode is supported by the USARTx instance. 999:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Call of this function is equivalent to following function call sequence : 1000:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Clock Phase configuration using @ref LL_USART_SetClockPhase() function 1001:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Clock Polarity configuration using @ref LL_USART_SetClockPolarity() function 1002:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Output of Last bit Clock pulse configuration using @ref LL_USART_SetLastClkPulseOutpu 1003:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 CPHA LL_USART_ConfigClock\n 1004:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR2 CPOL LL_USART_ConfigClock\n 1005:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR2 LBCL LL_USART_ConfigClock 1006:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1007:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param Phase This parameter can be one of the following values: 1008:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_PHASE_1EDGE 1009:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_PHASE_2EDGE 1010:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param Polarity This parameter can be one of the following values: 1011:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_POLARITY_LOW 1012:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_POLARITY_HIGH 1013:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param LBCPOutput This parameter can be one of the following values: 1014:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT 1015:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_LASTCLKPULSE_OUTPUT 1016:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 1017:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1018:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_ConfigClock(USART_TypeDef *USARTx, uint32_t Phase, uint32_t Polarity, 1019:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1020:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** MODIFY_REG(USARTx->CR2, USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_LBCL, Phase | Polarity | LBCP 1021:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1022:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1023:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1024:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Enable Clock output on SCLK pin 1025:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not 1026:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Synchronous mode is supported by the USARTx instance. 1027:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 CLKEN LL_USART_EnableSCLKOutput 1028:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1029:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 1030:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1031:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableSCLKOutput(USART_TypeDef *USARTx) 1032:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1033:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** SET_BIT(USARTx->CR2, USART_CR2_CLKEN); 1034:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1035:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1036:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1037:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Disable Clock output on SCLK pin 1038:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not 1039:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Synchronous mode is supported by the USARTx instance. 1040:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 CLKEN LL_USART_DisableSCLKOutput 1041:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1042:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 1043:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1044:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableSCLKOutput(USART_TypeDef *USARTx) 1045:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1046:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** CLEAR_BIT(USARTx->CR2, USART_CR2_CLKEN); ARM GAS /tmp/ccdsDELB.s page 362 1047:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1048:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1049:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1050:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Indicate if Clock output on SCLK pin is enabled 1051:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not 1052:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Synchronous mode is supported by the USARTx instance. 1053:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 CLKEN LL_USART_IsEnabledSCLKOutput 1054:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1055:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). 1056:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1057:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledSCLKOutput(const USART_TypeDef *USARTx) 1058:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1059:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->CR2, USART_CR2_CLKEN) == (USART_CR2_CLKEN)) ? 1UL : 0UL); 1060:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1061:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1062:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1063:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Set the length of the stop bits 1064:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 STOP LL_USART_SetStopBitsLength 1065:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1066:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param StopBits This parameter can be one of the following values: 1067:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_STOPBITS_0_5 1068:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_STOPBITS_1 1069:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_STOPBITS_1_5 1070:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_STOPBITS_2 1071:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 1072:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1073:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetStopBitsLength(USART_TypeDef *USARTx, uint32_t StopBits) 1074:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1075:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** MODIFY_REG(USARTx->CR2, USART_CR2_STOP, StopBits); 1076:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1077:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1078:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1079:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Retrieve the length of the stop bits 1080:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 STOP LL_USART_GetStopBitsLength 1081:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1082:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Returned value can be one of the following values: 1083:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_STOPBITS_0_5 1084:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_STOPBITS_1 1085:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_STOPBITS_1_5 1086:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_STOPBITS_2 1087:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1088:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetStopBitsLength(const USART_TypeDef *USARTx) 1089:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1090:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_STOP)); 1091:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1092:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1093:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1094:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Configure Character frame format (Datawidth, Parity control, Stop Bits) 1095:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Call of this function is equivalent to following function call sequence : 1096:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Data Width configuration using @ref LL_USART_SetDataWidth() function 1097:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Parity Control and mode configuration using @ref LL_USART_SetParity() function 1098:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Stop bits configuration using @ref LL_USART_SetStopBitsLength() function 1099:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 PS LL_USART_ConfigCharacter\n 1100:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR1 PCE LL_USART_ConfigCharacter\n 1101:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR1 M0 LL_USART_ConfigCharacter\n 1102:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR1 M1 LL_USART_ConfigCharacter\n 1103:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR2 STOP LL_USART_ConfigCharacter ARM GAS /tmp/ccdsDELB.s page 363 1104:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1105:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param DataWidth This parameter can be one of the following values: 1106:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_DATAWIDTH_7B 1107:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_DATAWIDTH_8B 1108:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_DATAWIDTH_9B 1109:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param Parity This parameter can be one of the following values: 1110:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_PARITY_NONE 1111:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_PARITY_EVEN 1112:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_PARITY_ODD 1113:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param StopBits This parameter can be one of the following values: 1114:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_STOPBITS_0_5 1115:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_STOPBITS_1 1116:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_STOPBITS_1_5 1117:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_STOPBITS_2 1118:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 1119:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1120:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_ConfigCharacter(USART_TypeDef *USARTx, uint32_t DataWidth, uint32_t P 1121:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** uint32_t StopBits) 1122:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1123:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** MODIFY_REG(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE | USART_CR1_M, Parity | DataWidth); 1124:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** MODIFY_REG(USARTx->CR2, USART_CR2_STOP, StopBits); 1125:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1126:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1127:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1128:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Configure TX/RX pins swapping setting. 1129:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 SWAP LL_USART_SetTXRXSwap 1130:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1131:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param SwapConfig This parameter can be one of the following values: 1132:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_TXRX_STANDARD 1133:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_TXRX_SWAPPED 1134:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 1135:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1136:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetTXRXSwap(USART_TypeDef *USARTx, uint32_t SwapConfig) 1137:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1138:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** MODIFY_REG(USARTx->CR2, USART_CR2_SWAP, SwapConfig); 1139:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1140:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1141:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1142:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Retrieve TX/RX pins swapping configuration. 1143:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 SWAP LL_USART_GetTXRXSwap 1144:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1145:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Returned value can be one of the following values: 1146:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_TXRX_STANDARD 1147:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_TXRX_SWAPPED 1148:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1149:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetTXRXSwap(const USART_TypeDef *USARTx) 1150:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1151:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_SWAP)); 1152:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1153:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1154:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1155:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Configure RX pin active level logic 1156:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 RXINV LL_USART_SetRXPinLevel 1157:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1158:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param PinInvMethod This parameter can be one of the following values: 1159:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_RXPIN_LEVEL_STANDARD 1160:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_RXPIN_LEVEL_INVERTED ARM GAS /tmp/ccdsDELB.s page 364 1161:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 1162:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1163:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetRXPinLevel(USART_TypeDef *USARTx, uint32_t PinInvMethod) 1164:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1165:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** MODIFY_REG(USARTx->CR2, USART_CR2_RXINV, PinInvMethod); 1166:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1167:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1168:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1169:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Retrieve RX pin active level logic configuration 1170:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 RXINV LL_USART_GetRXPinLevel 1171:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1172:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Returned value can be one of the following values: 1173:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_RXPIN_LEVEL_STANDARD 1174:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_RXPIN_LEVEL_INVERTED 1175:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1176:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetRXPinLevel(const USART_TypeDef *USARTx) 1177:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1178:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_RXINV)); 1179:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1180:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1181:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1182:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Configure TX pin active level logic 1183:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 TXINV LL_USART_SetTXPinLevel 1184:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1185:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param PinInvMethod This parameter can be one of the following values: 1186:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_TXPIN_LEVEL_STANDARD 1187:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_TXPIN_LEVEL_INVERTED 1188:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 1189:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1190:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetTXPinLevel(USART_TypeDef *USARTx, uint32_t PinInvMethod) 1191:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1192:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** MODIFY_REG(USARTx->CR2, USART_CR2_TXINV, PinInvMethod); 1193:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1194:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1195:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1196:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Retrieve TX pin active level logic configuration 1197:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 TXINV LL_USART_GetTXPinLevel 1198:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1199:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Returned value can be one of the following values: 1200:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_TXPIN_LEVEL_STANDARD 1201:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_TXPIN_LEVEL_INVERTED 1202:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1203:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetTXPinLevel(const USART_TypeDef *USARTx) 1204:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1205:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_TXINV)); 1206:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1207:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1208:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1209:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Configure Binary data logic. 1210:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Allow to define how Logical data from the data register are send/received : 1211:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * either in positive/direct logic (1=H, 0=L) or in negative/inverse logic (1=L, 0=H) 1212:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 DATAINV LL_USART_SetBinaryDataLogic 1213:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1214:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param DataLogic This parameter can be one of the following values: 1215:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_BINARY_LOGIC_POSITIVE 1216:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_BINARY_LOGIC_NEGATIVE 1217:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None ARM GAS /tmp/ccdsDELB.s page 365 1218:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1219:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetBinaryDataLogic(USART_TypeDef *USARTx, uint32_t DataLogic) 1220:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1221:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** MODIFY_REG(USARTx->CR2, USART_CR2_DATAINV, DataLogic); 1222:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1223:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1224:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1225:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Retrieve Binary data configuration 1226:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 DATAINV LL_USART_GetBinaryDataLogic 1227:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1228:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Returned value can be one of the following values: 1229:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_BINARY_LOGIC_POSITIVE 1230:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_BINARY_LOGIC_NEGATIVE 1231:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1232:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetBinaryDataLogic(const USART_TypeDef *USARTx) 1233:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1234:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_DATAINV)); 1235:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1236:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1237:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1238:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Configure transfer bit order (either Less or Most Significant Bit First) 1239:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note MSB First means data is transmitted/received with the MSB first, following the start bi 1240:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * LSB First means data is transmitted/received with data bit 0 first, following the start 1241:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 MSBFIRST LL_USART_SetTransferBitOrder 1242:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1243:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param BitOrder This parameter can be one of the following values: 1244:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_BITORDER_LSBFIRST 1245:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_BITORDER_MSBFIRST 1246:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 1247:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1248:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetTransferBitOrder(USART_TypeDef *USARTx, uint32_t BitOrder) 1249:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1250:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** MODIFY_REG(USARTx->CR2, USART_CR2_MSBFIRST, BitOrder); 1251:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1252:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1253:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1254:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Return transfer bit order (either Less or Most Significant Bit First) 1255:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note MSB First means data is transmitted/received with the MSB first, following the start bi 1256:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * LSB First means data is transmitted/received with data bit 0 first, following the start 1257:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 MSBFIRST LL_USART_GetTransferBitOrder 1258:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1259:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Returned value can be one of the following values: 1260:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_BITORDER_LSBFIRST 1261:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_BITORDER_MSBFIRST 1262:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1263:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetTransferBitOrder(const USART_TypeDef *USARTx) 1264:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1265:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_MSBFIRST)); 1266:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1267:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1268:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1269:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Enable Auto Baud-Rate Detection 1270:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or 1271:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Auto Baud Rate detection feature is supported by the USARTx instance. 1272:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 ABREN LL_USART_EnableAutoBaudRate 1273:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1274:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None ARM GAS /tmp/ccdsDELB.s page 366 1275:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1276:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableAutoBaudRate(USART_TypeDef *USARTx) 1277:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1278:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** SET_BIT(USARTx->CR2, USART_CR2_ABREN); 1279:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1280:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1281:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1282:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Disable Auto Baud-Rate Detection 1283:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or 1284:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Auto Baud Rate detection feature is supported by the USARTx instance. 1285:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 ABREN LL_USART_DisableAutoBaudRate 1286:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1287:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 1288:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1289:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableAutoBaudRate(USART_TypeDef *USARTx) 1290:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1291:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** CLEAR_BIT(USARTx->CR2, USART_CR2_ABREN); 1292:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1293:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1294:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1295:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Indicate if Auto Baud-Rate Detection mechanism is enabled 1296:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or 1297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Auto Baud Rate detection feature is supported by the USARTx instance. 1298:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 ABREN LL_USART_IsEnabledAutoBaud 1299:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1300:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). 1301:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1302:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledAutoBaud(const USART_TypeDef *USARTx) 1303:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1304:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->CR2, USART_CR2_ABREN) == (USART_CR2_ABREN)) ? 1UL : 0UL); 1305:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1306:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1307:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1308:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Set Auto Baud-Rate mode bits 1309:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or 1310:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Auto Baud Rate detection feature is supported by the USARTx instance. 1311:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 ABRMODE LL_USART_SetAutoBaudRateMode 1312:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1313:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param AutoBaudRateMode This parameter can be one of the following values: 1314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_STARTBIT 1315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_FALLINGEDGE 1316:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME 1317:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_55_FRAME 1318:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 1319:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1320:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetAutoBaudRateMode(USART_TypeDef *USARTx, uint32_t AutoBaudRateMode) 1321:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1322:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** MODIFY_REG(USARTx->CR2, USART_CR2_ABRMODE, AutoBaudRateMode); 1323:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1324:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1325:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1326:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Return Auto Baud-Rate mode 1327:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or 1328:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Auto Baud Rate detection feature is supported by the USARTx instance. 1329:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 ABRMODE LL_USART_GetAutoBaudRateMode 1330:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1331:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Returned value can be one of the following values: ARM GAS /tmp/ccdsDELB.s page 367 1332:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_STARTBIT 1333:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_FALLINGEDGE 1334:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME 1335:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_55_FRAME 1336:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1337:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetAutoBaudRateMode(const USART_TypeDef *USARTx) 1338:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1339:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_ABRMODE)); 1340:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1341:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1342:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1343:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Enable Receiver Timeout 1344:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 RTOEN LL_USART_EnableRxTimeout 1345:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 1347:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1348:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableRxTimeout(USART_TypeDef *USARTx) 1349:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1350:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** SET_BIT(USARTx->CR2, USART_CR2_RTOEN); 1351:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1352:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1353:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1354:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Disable Receiver Timeout 1355:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 RTOEN LL_USART_DisableRxTimeout 1356:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1357:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 1358:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1359:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableRxTimeout(USART_TypeDef *USARTx) 1360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1361:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** CLEAR_BIT(USARTx->CR2, USART_CR2_RTOEN); 1362:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1363:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1364:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1365:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Indicate if Receiver Timeout feature is enabled 1366:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 RTOEN LL_USART_IsEnabledRxTimeout 1367:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1368:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). 1369:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledRxTimeout(const USART_TypeDef *USARTx) 1371:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->CR2, USART_CR2_RTOEN) == (USART_CR2_RTOEN)) ? 1UL : 0UL); 1373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1374:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1375:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1376:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Set Address of the USART node. 1377:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note This is used in multiprocessor communication during Mute mode or Stop mode, 1378:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * for wake up with address mark detection. 1379:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note 4bits address node is used when 4-bit Address Detection is selected in ADDM7. 1380:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * (b7-b4 should be set to 0) 1381:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * 8bits address node is used when 7-bit Address Detection is selected in ADDM7. 1382:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * (This is used in multiprocessor communication during Mute mode or Stop mode, 1383:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * for wake up with 7-bit address mark detection. 1384:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * The MSB of the character sent by the transmitter should be equal to 1. 1385:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * It may also be used for character detection during normal reception, 1386:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Mute mode inactive (for example, end of block detection in ModBus protocol). 1387:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * In this case, the whole received character (8-bit) is compared to the ADD[7:0] 1388:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * value and CMF flag is set on match) ARM GAS /tmp/ccdsDELB.s page 368 1389:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 ADD LL_USART_ConfigNodeAddress\n 1390:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR2 ADDM7 LL_USART_ConfigNodeAddress 1391:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1392:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param AddressLen This parameter can be one of the following values: 1393:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_ADDRESS_DETECT_4B 1394:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_ADDRESS_DETECT_7B 1395:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param NodeAddress 4 or 7 bit Address of the USART node. 1396:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 1397:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1398:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_ConfigNodeAddress(USART_TypeDef *USARTx, uint32_t AddressLen, uint32_ 1399:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1400:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** MODIFY_REG(USARTx->CR2, USART_CR2_ADD | USART_CR2_ADDM7, 1401:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** (uint32_t)(AddressLen | (NodeAddress << USART_CR2_ADD_Pos))); 1402:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1403:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1404:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1405:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Return 8 bit Address of the USART node as set in ADD field of CR2. 1406:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note If 4-bit Address Detection is selected in ADDM7, 1407:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * only 4bits (b3-b0) of returned value are relevant (b31-b4 are not relevant) 1408:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * If 7-bit Address Detection is selected in ADDM7, 1409:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * only 8bits (b7-b0) of returned value are relevant (b31-b8 are not relevant) 1410:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 ADD LL_USART_GetNodeAddress 1411:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1412:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Address of the USART node (Value between Min_Data=0 and Max_Data=255) 1413:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1414:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetNodeAddress(const USART_TypeDef *USARTx) 1415:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1416:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_ADD) >> USART_CR2_ADD_Pos); 1417:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1418:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1419:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1420:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Return Length of Node Address used in Address Detection mode (7-bit or 4-bit) 1421:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 ADDM7 LL_USART_GetNodeAddressLen 1422:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1423:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Returned value can be one of the following values: 1424:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_ADDRESS_DETECT_4B 1425:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_ADDRESS_DETECT_7B 1426:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1427:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetNodeAddressLen(const USART_TypeDef *USARTx) 1428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1429:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_ADDM7)); 1430:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1431:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1432:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1433:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Enable RTS HW Flow Control 1434:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not 1435:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Hardware Flow control feature is supported by the USARTx instance. 1436:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 RTSE LL_USART_EnableRTSHWFlowCtrl 1437:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1438:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 1439:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1440:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableRTSHWFlowCtrl(USART_TypeDef *USARTx) 1441:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1442:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** SET_BIT(USARTx->CR3, USART_CR3_RTSE); 1443:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1444:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1445:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** ARM GAS /tmp/ccdsDELB.s page 369 1446:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Disable RTS HW Flow Control 1447:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not 1448:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Hardware Flow control feature is supported by the USARTx instance. 1449:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 RTSE LL_USART_DisableRTSHWFlowCtrl 1450:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1451:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 1452:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1453:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableRTSHWFlowCtrl(USART_TypeDef *USARTx) 1454:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1455:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** CLEAR_BIT(USARTx->CR3, USART_CR3_RTSE); 1456:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1457:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1458:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1459:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Enable CTS HW Flow Control 1460:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not 1461:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Hardware Flow control feature is supported by the USARTx instance. 1462:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 CTSE LL_USART_EnableCTSHWFlowCtrl 1463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1464:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 1465:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1466:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableCTSHWFlowCtrl(USART_TypeDef *USARTx) 1467:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1468:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** SET_BIT(USARTx->CR3, USART_CR3_CTSE); 1469:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1470:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1471:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1472:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Disable CTS HW Flow Control 1473:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not 1474:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Hardware Flow control feature is supported by the USARTx instance. 1475:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 CTSE LL_USART_DisableCTSHWFlowCtrl 1476:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1477:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 1478:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1479:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableCTSHWFlowCtrl(USART_TypeDef *USARTx) 1480:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1481:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** CLEAR_BIT(USARTx->CR3, USART_CR3_CTSE); 1482:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1483:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1484:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1485:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Configure HW Flow Control mode (both CTS and RTS) 1486:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not 1487:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Hardware Flow control feature is supported by the USARTx instance. 1488:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 RTSE LL_USART_SetHWFlowCtrl\n 1489:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR3 CTSE LL_USART_SetHWFlowCtrl 1490:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1491:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param HardwareFlowControl This parameter can be one of the following values: 1492:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_HWCONTROL_NONE 1493:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_HWCONTROL_RTS 1494:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_HWCONTROL_CTS 1495:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_HWCONTROL_RTS_CTS 1496:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 1497:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1498:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetHWFlowCtrl(USART_TypeDef *USARTx, uint32_t HardwareFlowControl) 1499:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1500:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** MODIFY_REG(USARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE, HardwareFlowControl); 1501:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1502:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ARM GAS /tmp/ccdsDELB.s page 370 1503:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1504:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Return HW Flow Control configuration (both CTS and RTS) 1505:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not 1506:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Hardware Flow control feature is supported by the USARTx instance. 1507:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 RTSE LL_USART_GetHWFlowCtrl\n 1508:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR3 CTSE LL_USART_GetHWFlowCtrl 1509:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1510:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Returned value can be one of the following values: 1511:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_HWCONTROL_NONE 1512:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_HWCONTROL_RTS 1513:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_HWCONTROL_CTS 1514:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_HWCONTROL_RTS_CTS 1515:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1516:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetHWFlowCtrl(const USART_TypeDef *USARTx) 1517:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1518:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE)); 1519:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1520:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1521:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1522:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Enable One bit sampling method 1523:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 ONEBIT LL_USART_EnableOneBitSamp 1524:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1525:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 1526:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1527:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableOneBitSamp(USART_TypeDef *USARTx) 1528:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1529:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** SET_BIT(USARTx->CR3, USART_CR3_ONEBIT); 1530:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1531:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1532:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1533:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Disable One bit sampling method 1534:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 ONEBIT LL_USART_DisableOneBitSamp 1535:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1536:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 1537:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1538:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableOneBitSamp(USART_TypeDef *USARTx) 1539:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1540:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** CLEAR_BIT(USARTx->CR3, USART_CR3_ONEBIT); 1541:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1542:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1543:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1544:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Indicate if One bit sampling method is enabled 1545:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 ONEBIT LL_USART_IsEnabledOneBitSamp 1546:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1547:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). 1548:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1549:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledOneBitSamp(const USART_TypeDef *USARTx) 1550:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1551:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->CR3, USART_CR3_ONEBIT) == (USART_CR3_ONEBIT)) ? 1UL : 0UL); 1552:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1553:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1554:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1555:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Enable Overrun detection 1556:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 OVRDIS LL_USART_EnableOverrunDetect 1557:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1558:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 1559:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ ARM GAS /tmp/ccdsDELB.s page 371 1560:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableOverrunDetect(USART_TypeDef *USARTx) 1561:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1562:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** CLEAR_BIT(USARTx->CR3, USART_CR3_OVRDIS); 1563:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1564:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1565:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1566:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Disable Overrun detection 1567:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 OVRDIS LL_USART_DisableOverrunDetect 1568:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1569:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 1570:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1571:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableOverrunDetect(USART_TypeDef *USARTx) 1572:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1573:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** SET_BIT(USARTx->CR3, USART_CR3_OVRDIS); 1574:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1575:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1576:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1577:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Indicate if Overrun detection is enabled 1578:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 OVRDIS LL_USART_IsEnabledOverrunDetect 1579:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1580:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). 1581:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1582:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledOverrunDetect(const USART_TypeDef *USARTx) 1583:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1584:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->CR3, USART_CR3_OVRDIS) != USART_CR3_OVRDIS) ? 1UL : 0UL); 1585:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1586:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1587:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_CR1_UESM) 1588:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_CR3_WUS) 1589:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1590:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Select event type for Wake UP Interrupt Flag (WUS[1:0] bits) 1591:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not 1592:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Wake-up from Stop mode feature is supported by the USARTx instance. 1593:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 WUS LL_USART_SetWKUPType 1594:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1595:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param Type This parameter can be one of the following values: 1596:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_WAKEUP_ON_ADDRESS 1597:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_WAKEUP_ON_STARTBIT 1598:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_WAKEUP_ON_RXNE 1599:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 1600:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1601:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetWKUPType(USART_TypeDef *USARTx, uint32_t Type) 1602:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1603:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** MODIFY_REG(USARTx->CR3, USART_CR3_WUS, Type); 1604:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1605:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1606:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1607:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Return event type for Wake UP Interrupt Flag (WUS[1:0] bits) 1608:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not 1609:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Wake-up from Stop mode feature is supported by the USARTx instance. 1610:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 WUS LL_USART_GetWKUPType 1611:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1612:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Returned value can be one of the following values: 1613:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_WAKEUP_ON_ADDRESS 1614:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_WAKEUP_ON_STARTBIT 1615:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_WAKEUP_ON_RXNE 1616:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ ARM GAS /tmp/ccdsDELB.s page 372 1617:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetWKUPType(const USART_TypeDef *USARTx) 1618:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1619:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_WUS)); 1620:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1621:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1622:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_CR3_WUS */ 1623:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_CR1_UESM */ 1624:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1625:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Configure USART BRR register for achieving expected Baud Rate value. 1626:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Compute and set USARTDIV value in BRR Register (full BRR content) 1627:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * according to used Peripheral Clock, Oversampling mode, and expected Baud Rate values 1628:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Peripheral clock and Baud rate values provided as function parameters should be valid 1629:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * (Baud rate value != 0) 1630:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note In case of oversampling by 16 and 8, BRR content must be greater than or equal to 16d. 1631:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll BRR BRR LL_USART_SetBaudRate 1632:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1633:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param PeriphClk Peripheral Clock 1634:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param OverSampling This parameter can be one of the following values: 1635:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_OVERSAMPLING_16 1636:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_OVERSAMPLING_8 1637:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param BaudRate Baud Rate 1638:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 1639:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1640:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetBaudRate(USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t OverS 1641:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** uint32_t BaudRate) 1642:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1643:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** uint32_t usartdiv; 1644:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** uint32_t brrtemp; 1645:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1646:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** if (OverSampling == LL_USART_OVERSAMPLING_8) 1647:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1648:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** usartdiv = (uint16_t)(__LL_USART_DIV_SAMPLING8(PeriphClk, BaudRate)); 1649:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** brrtemp = usartdiv & 0xFFF0U; 1650:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U); 1651:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** USARTx->BRR = brrtemp; 1652:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1653:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** else 1654:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1655:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** USARTx->BRR = (uint16_t)(__LL_USART_DIV_SAMPLING16(PeriphClk, BaudRate)); 1656:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1657:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1658:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1659:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1660:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Return current Baud Rate value, according to USARTDIV present in BRR register 1661:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * (full BRR content), and to used Peripheral Clock and Oversampling mode values 1662:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note In case of non-initialized or invalid value stored in BRR register, value 0 will be ret 1663:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note In case of oversampling by 16 and 8, BRR content must be greater than or equal to 16d. 1664:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll BRR BRR LL_USART_GetBaudRate 1665:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1666:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param PeriphClk Peripheral Clock 1667:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param OverSampling This parameter can be one of the following values: 1668:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_OVERSAMPLING_16 1669:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_OVERSAMPLING_8 1670:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Baud Rate 1671:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1672:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetBaudRate(const USART_TypeDef *USARTx, uint32_t PeriphClk, uint 1673:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { ARM GAS /tmp/ccdsDELB.s page 373 1674:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** uint32_t usartdiv; 1675:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** uint32_t brrresult = 0x0U; 1676:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1677:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** usartdiv = USARTx->BRR; 1678:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1679:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** if (usartdiv == 0U) 1680:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1681:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* Do not perform a division by 0 */ 1682:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1683:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** else if (OverSampling == LL_USART_OVERSAMPLING_8) 1684:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1685:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** usartdiv = (uint16_t)((usartdiv & 0xFFF0U) | ((usartdiv & 0x0007U) << 1U)) ; 1686:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** if (usartdiv != 0U) 1687:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1688:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** brrresult = (PeriphClk * 2U) / usartdiv; 1689:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1690:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1691:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** else 1692:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1693:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** if ((usartdiv & 0xFFFFU) != 0U) 1694:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1695:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** brrresult = PeriphClk / usartdiv; 1696:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1697:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1698:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return (brrresult); 1699:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1700:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1701:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1702:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Set Receiver Time Out Value (expressed in nb of bits duration) 1703:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll RTOR RTO LL_USART_SetRxTimeout 1704:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1705:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param Timeout Value between Min_Data=0x00 and Max_Data=0x00FFFFFF 1706:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 1707:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1708:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetRxTimeout(USART_TypeDef *USARTx, uint32_t Timeout) 1709:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1710:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** MODIFY_REG(USARTx->RTOR, USART_RTOR_RTO, Timeout); 1711:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1712:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1713:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1714:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Get Receiver Time Out Value (expressed in nb of bits duration) 1715:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll RTOR RTO LL_USART_GetRxTimeout 1716:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1717:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Value between Min_Data=0x00 and Max_Data=0x00FFFFFF 1718:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1719:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetRxTimeout(const USART_TypeDef *USARTx) 1720:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1721:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return (uint32_t)(READ_BIT(USARTx->RTOR, USART_RTOR_RTO)); 1722:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1723:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1724:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1725:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Set Block Length value in reception 1726:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll RTOR BLEN LL_USART_SetBlockLength 1727:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1728:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param BlockLength Value between Min_Data=0x00 and Max_Data=0xFF 1729:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 1730:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ ARM GAS /tmp/ccdsDELB.s page 374 1731:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetBlockLength(USART_TypeDef *USARTx, uint32_t BlockLength) 1732:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1733:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** MODIFY_REG(USARTx->RTOR, USART_RTOR_BLEN, BlockLength << USART_RTOR_BLEN_Pos); 1734:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1735:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1736:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1737:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Get Block Length value in reception 1738:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll RTOR BLEN LL_USART_GetBlockLength 1739:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1740:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Value between Min_Data=0x00 and Max_Data=0xFF 1741:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1742:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetBlockLength(const USART_TypeDef *USARTx) 1743:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1744:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return (uint32_t)(READ_BIT(USARTx->RTOR, USART_RTOR_BLEN) >> USART_RTOR_BLEN_Pos); 1745:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1746:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1747:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1748:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} 1749:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1750:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1751:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EF_Configuration_IRDA Configuration functions related to Irda feature 1752:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ 1753:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1754:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1755:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1756:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Enable IrDA mode 1757:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not 1758:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * IrDA feature is supported by the USARTx instance. 1759:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 IREN LL_USART_EnableIrda 1760:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1761:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 1762:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1763:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableIrda(USART_TypeDef *USARTx) 1764:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1765:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** SET_BIT(USARTx->CR3, USART_CR3_IREN); 1766:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1767:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1768:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1769:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Disable IrDA mode 1770:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not 1771:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * IrDA feature is supported by the USARTx instance. 1772:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 IREN LL_USART_DisableIrda 1773:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1774:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 1775:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1776:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableIrda(USART_TypeDef *USARTx) 1777:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1778:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** CLEAR_BIT(USARTx->CR3, USART_CR3_IREN); 1779:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1780:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1781:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1782:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Indicate if IrDA mode is enabled 1783:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not 1784:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * IrDA feature is supported by the USARTx instance. 1785:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 IREN LL_USART_IsEnabledIrda 1786:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1787:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). ARM GAS /tmp/ccdsDELB.s page 375 1788:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1789:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledIrda(const USART_TypeDef *USARTx) 1790:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1791:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->CR3, USART_CR3_IREN) == (USART_CR3_IREN)) ? 1UL : 0UL); 1792:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1793:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1794:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1795:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Configure IrDA Power Mode (Normal or Low Power) 1796:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not 1797:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * IrDA feature is supported by the USARTx instance. 1798:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 IRLP LL_USART_SetIrdaPowerMode 1799:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1800:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param PowerMode This parameter can be one of the following values: 1801:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_IRDA_POWER_NORMAL 1802:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_IRDA_POWER_LOW 1803:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 1804:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1805:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetIrdaPowerMode(USART_TypeDef *USARTx, uint32_t PowerMode) 1806:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1807:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** MODIFY_REG(USARTx->CR3, USART_CR3_IRLP, PowerMode); 1808:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1809:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1810:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1811:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Retrieve IrDA Power Mode configuration (Normal or Low Power) 1812:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not 1813:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * IrDA feature is supported by the USARTx instance. 1814:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 IRLP LL_USART_GetIrdaPowerMode 1815:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1816:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Returned value can be one of the following values: 1817:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_IRDA_POWER_NORMAL 1818:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_PHASE_2EDGE 1819:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1820:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetIrdaPowerMode(const USART_TypeDef *USARTx) 1821:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1822:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_IRLP)); 1823:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1824:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1825:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1826:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Set Irda prescaler value, used for dividing the USART clock source 1827:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * to achieve the Irda Low Power frequency (8 bits value) 1828:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not 1829:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * IrDA feature is supported by the USARTx instance. 1830:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll GTPR PSC LL_USART_SetIrdaPrescaler 1831:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1832:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param PrescalerValue Value between Min_Data=0x00 and Max_Data=0xFF 1833:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 1834:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1835:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetIrdaPrescaler(USART_TypeDef *USARTx, uint32_t PrescalerValue) 1836:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1837:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** MODIFY_REG(USARTx->GTPR, USART_GTPR_PSC, (uint16_t)PrescalerValue); 1838:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1839:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1840:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1841:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Return Irda prescaler value, used for dividing the USART clock source 1842:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * to achieve the Irda Low Power frequency (8 bits value) 1843:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not 1844:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * IrDA feature is supported by the USARTx instance. ARM GAS /tmp/ccdsDELB.s page 376 1845:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll GTPR PSC LL_USART_GetIrdaPrescaler 1846:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1847:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Irda prescaler value (Value between Min_Data=0x00 and Max_Data=0xFF) 1848:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1849:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetIrdaPrescaler(const USART_TypeDef *USARTx) 1850:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1851:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_PSC)); 1852:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1853:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1854:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1855:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} 1856:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1857:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1858:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EF_Configuration_Smartcard Configuration functions related to Smartcard feat 1859:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ 1860:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1861:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1862:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1863:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Enable Smartcard NACK transmission 1864:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not 1865:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Smartcard feature is supported by the USARTx instance. 1866:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 NACK LL_USART_EnableSmartcardNACK 1867:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1868:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 1869:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1870:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableSmartcardNACK(USART_TypeDef *USARTx) 1871:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1872:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** SET_BIT(USARTx->CR3, USART_CR3_NACK); 1873:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1874:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1875:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1876:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Disable Smartcard NACK transmission 1877:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not 1878:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Smartcard feature is supported by the USARTx instance. 1879:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 NACK LL_USART_DisableSmartcardNACK 1880:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1881:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 1882:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1883:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableSmartcardNACK(USART_TypeDef *USARTx) 1884:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1885:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** CLEAR_BIT(USARTx->CR3, USART_CR3_NACK); 1886:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1887:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1888:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1889:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Indicate if Smartcard NACK transmission is enabled 1890:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not 1891:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Smartcard feature is supported by the USARTx instance. 1892:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 NACK LL_USART_IsEnabledSmartcardNACK 1893:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1894:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). 1895:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1896:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcardNACK(const USART_TypeDef *USARTx) 1897:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1898:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->CR3, USART_CR3_NACK) == (USART_CR3_NACK)) ? 1UL : 0UL); 1899:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1900:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1901:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** ARM GAS /tmp/ccdsDELB.s page 377 1902:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Enable Smartcard mode 1903:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not 1904:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Smartcard feature is supported by the USARTx instance. 1905:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 SCEN LL_USART_EnableSmartcard 1906:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 1908:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1909:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableSmartcard(USART_TypeDef *USARTx) 1910:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1911:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** SET_BIT(USARTx->CR3, USART_CR3_SCEN); 1912:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1913:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1914:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1915:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Disable Smartcard mode 1916:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not 1917:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Smartcard feature is supported by the USARTx instance. 1918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 SCEN LL_USART_DisableSmartcard 1919:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1920:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 1921:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1922:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableSmartcard(USART_TypeDef *USARTx) 1923:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1924:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** CLEAR_BIT(USARTx->CR3, USART_CR3_SCEN); 1925:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1926:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1927:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1928:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Indicate if Smartcard mode is enabled 1929:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not 1930:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Smartcard feature is supported by the USARTx instance. 1931:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 SCEN LL_USART_IsEnabledSmartcard 1932:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1933:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). 1934:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1935:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcard(const USART_TypeDef *USARTx) 1936:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1937:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->CR3, USART_CR3_SCEN) == (USART_CR3_SCEN)) ? 1UL : 0UL); 1938:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1939:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1940:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1941:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Set Smartcard Auto-Retry Count value (SCARCNT[2:0] bits) 1942:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not 1943:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Smartcard feature is supported by the USARTx instance. 1944:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note This bit-field specifies the number of retries in transmit and receive, in Smartcard mo 1945:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * In transmission mode, it specifies the number of automatic retransmission retries, befo 1946:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * generating a transmission error (FE bit set). 1947:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * In reception mode, it specifies the number or erroneous reception trials, before genera 1948:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * reception error (RXNE and PE bits set) 1949:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 SCARCNT LL_USART_SetSmartcardAutoRetryCount 1950:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1951:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param AutoRetryCount Value between Min_Data=0 and Max_Data=7 1952:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 1953:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1954:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetSmartcardAutoRetryCount(USART_TypeDef *USARTx, uint32_t AutoRetryC 1955:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1956:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** MODIFY_REG(USARTx->CR3, USART_CR3_SCARCNT, AutoRetryCount << USART_CR3_SCARCNT_Pos); 1957:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1958:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ARM GAS /tmp/ccdsDELB.s page 378 1959:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1960:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Return Smartcard Auto-Retry Count value (SCARCNT[2:0] bits) 1961:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not 1962:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Smartcard feature is supported by the USARTx instance. 1963:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 SCARCNT LL_USART_GetSmartcardAutoRetryCount 1964:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1965:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Smartcard Auto-Retry Count value (Value between Min_Data=0 and Max_Data=7) 1966:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1967:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetSmartcardAutoRetryCount(const USART_TypeDef *USARTx) 1968:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1969:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_SCARCNT) >> USART_CR3_SCARCNT_Pos); 1970:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1971:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1972:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1973:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Set Smartcard prescaler value, used for dividing the USART clock 1974:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * source to provide the SMARTCARD Clock (5 bits value) 1975:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not 1976:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Smartcard feature is supported by the USARTx instance. 1977:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll GTPR PSC LL_USART_SetSmartcardPrescaler 1978:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1979:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param PrescalerValue Value between Min_Data=0 and Max_Data=31 1980:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 1981:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1982:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetSmartcardPrescaler(USART_TypeDef *USARTx, uint32_t PrescalerValue) 1983:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1984:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** MODIFY_REG(USARTx->GTPR, USART_GTPR_PSC, (uint16_t)PrescalerValue); 1985:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1986:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1987:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1988:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Return Smartcard prescaler value, used for dividing the USART clock 1989:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * source to provide the SMARTCARD Clock (5 bits value) 1990:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not 1991:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Smartcard feature is supported by the USARTx instance. 1992:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll GTPR PSC LL_USART_GetSmartcardPrescaler 1993:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1994:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Smartcard prescaler value (Value between Min_Data=0 and Max_Data=31) 1995:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1996:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetSmartcardPrescaler(const USART_TypeDef *USARTx) 1997:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1998:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_PSC)); 1999:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2000:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2001:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2002:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Set Smartcard Guard time value, expressed in nb of baud clocks periods 2003:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * (GT[7:0] bits : Guard time value) 2004:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not 2005:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Smartcard feature is supported by the USARTx instance. 2006:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll GTPR GT LL_USART_SetSmartcardGuardTime 2007:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2008:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param GuardTime Value between Min_Data=0x00 and Max_Data=0xFF 2009:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 2010:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2011:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetSmartcardGuardTime(USART_TypeDef *USARTx, uint32_t GuardTime) 2012:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2013:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** MODIFY_REG(USARTx->GTPR, USART_GTPR_GT, (uint16_t)(GuardTime << USART_GTPR_GT_Pos)); 2014:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2015:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ARM GAS /tmp/ccdsDELB.s page 379 2016:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2017:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Return Smartcard Guard time value, expressed in nb of baud clocks periods 2018:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * (GT[7:0] bits : Guard time value) 2019:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not 2020:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Smartcard feature is supported by the USARTx instance. 2021:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll GTPR GT LL_USART_GetSmartcardGuardTime 2022:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2023:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Smartcard Guard time value (Value between Min_Data=0x00 and Max_Data=0xFF) 2024:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2025:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetSmartcardGuardTime(const USART_TypeDef *USARTx) 2026:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2027:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_GT) >> USART_GTPR_GT_Pos); 2028:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2029:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2030:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2031:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} 2032:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2033:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2034:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EF_Configuration_HalfDuplex Configuration functions related to Half Duplex f 2035:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ 2036:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2037:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2038:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2039:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Enable Single Wire Half-Duplex mode 2040:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not 2041:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Half-Duplex mode is supported by the USARTx instance. 2042:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 HDSEL LL_USART_EnableHalfDuplex 2043:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2044:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 2045:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2046:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableHalfDuplex(USART_TypeDef *USARTx) 2047:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2048:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** SET_BIT(USARTx->CR3, USART_CR3_HDSEL); 2049:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2050:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2051:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2052:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Disable Single Wire Half-Duplex mode 2053:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not 2054:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Half-Duplex mode is supported by the USARTx instance. 2055:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 HDSEL LL_USART_DisableHalfDuplex 2056:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2057:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 2058:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2059:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableHalfDuplex(USART_TypeDef *USARTx) 2060:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2061:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** CLEAR_BIT(USARTx->CR3, USART_CR3_HDSEL); 2062:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2063:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2064:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2065:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Indicate if Single Wire Half-Duplex mode is enabled 2066:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not 2067:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Half-Duplex mode is supported by the USARTx instance. 2068:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 HDSEL LL_USART_IsEnabledHalfDuplex 2069:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2070:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). 2071:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2072:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledHalfDuplex(const USART_TypeDef *USARTx) ARM GAS /tmp/ccdsDELB.s page 380 2073:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2074:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->CR3, USART_CR3_HDSEL) == (USART_CR3_HDSEL)) ? 1UL : 0UL); 2075:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2076:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2077:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2078:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} 2079:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2080:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2081:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EF_Configuration_LIN Configuration functions related to LIN feature 2082:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ 2083:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2084:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2085:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2086:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Set LIN Break Detection Length 2087:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not 2088:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * LIN feature is supported by the USARTx instance. 2089:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 LBDL LL_USART_SetLINBrkDetectionLen 2090:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2091:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param LINBDLength This parameter can be one of the following values: 2092:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_LINBREAK_DETECT_10B 2093:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_LINBREAK_DETECT_11B 2094:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 2095:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2096:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetLINBrkDetectionLen(USART_TypeDef *USARTx, uint32_t LINBDLength) 2097:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2098:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** MODIFY_REG(USARTx->CR2, USART_CR2_LBDL, LINBDLength); 2099:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2100:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2101:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2102:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Return LIN Break Detection Length 2103:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not 2104:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * LIN feature is supported by the USARTx instance. 2105:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 LBDL LL_USART_GetLINBrkDetectionLen 2106:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2107:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Returned value can be one of the following values: 2108:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_LINBREAK_DETECT_10B 2109:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_LINBREAK_DETECT_11B 2110:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2111:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetLINBrkDetectionLen(const USART_TypeDef *USARTx) 2112:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2113:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_LBDL)); 2114:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2115:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2116:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2117:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Enable LIN mode 2118:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not 2119:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * LIN feature is supported by the USARTx instance. 2120:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 LINEN LL_USART_EnableLIN 2121:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2122:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 2123:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2124:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableLIN(USART_TypeDef *USARTx) 2125:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2126:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** SET_BIT(USARTx->CR2, USART_CR2_LINEN); 2127:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2128:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2129:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** ARM GAS /tmp/ccdsDELB.s page 381 2130:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Disable LIN mode 2131:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not 2132:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * LIN feature is supported by the USARTx instance. 2133:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 LINEN LL_USART_DisableLIN 2134:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2135:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 2136:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2137:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableLIN(USART_TypeDef *USARTx) 2138:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2139:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** CLEAR_BIT(USARTx->CR2, USART_CR2_LINEN); 2140:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2141:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2142:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2143:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Indicate if LIN mode is enabled 2144:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not 2145:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * LIN feature is supported by the USARTx instance. 2146:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 LINEN LL_USART_IsEnabledLIN 2147:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2148:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). 2149:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2150:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledLIN(const USART_TypeDef *USARTx) 2151:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2152:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->CR2, USART_CR2_LINEN) == (USART_CR2_LINEN)) ? 1UL : 0UL); 2153:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2154:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2155:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2156:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} 2157:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2158:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2159:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EF_Configuration_DE Configuration functions related to Driver Enable feature 2160:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ 2161:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2162:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2163:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2164:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Set DEDT (Driver Enable De-Assertion Time), Time value expressed on 5 bits ([4:0] bits) 2165:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not 2166:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Driver Enable feature is supported by the USARTx instance. 2167:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 DEDT LL_USART_SetDEDeassertionTime 2168:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2169:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param Time Value between Min_Data=0 and Max_Data=31 2170:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 2171:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2172:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetDEDeassertionTime(USART_TypeDef *USARTx, uint32_t Time) 2173:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2174:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** MODIFY_REG(USARTx->CR1, USART_CR1_DEDT, Time << USART_CR1_DEDT_Pos); 2175:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2176:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2177:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2178:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Return DEDT (Driver Enable De-Assertion Time) 2179:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not 2180:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Driver Enable feature is supported by the USARTx instance. 2181:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 DEDT LL_USART_GetDEDeassertionTime 2182:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2183:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Time value expressed on 5 bits ([4:0] bits) : Value between Min_Data=0 and Max_Data=31 2184:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2185:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetDEDeassertionTime(const USART_TypeDef *USARTx) 2186:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { ARM GAS /tmp/ccdsDELB.s page 382 2187:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_DEDT) >> USART_CR1_DEDT_Pos); 2188:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2189:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2190:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2191:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Set DEAT (Driver Enable Assertion Time), Time value expressed on 5 bits ([4:0] bits). 2192:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not 2193:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Driver Enable feature is supported by the USARTx instance. 2194:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 DEAT LL_USART_SetDEAssertionTime 2195:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2196:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param Time Value between Min_Data=0 and Max_Data=31 2197:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 2198:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2199:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetDEAssertionTime(USART_TypeDef *USARTx, uint32_t Time) 2200:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2201:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** MODIFY_REG(USARTx->CR1, USART_CR1_DEAT, Time << USART_CR1_DEAT_Pos); 2202:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2203:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2204:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2205:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Return DEAT (Driver Enable Assertion Time) 2206:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not 2207:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Driver Enable feature is supported by the USARTx instance. 2208:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 DEAT LL_USART_GetDEAssertionTime 2209:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2210:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Time value expressed on 5 bits ([4:0] bits) : Value between Min_Data=0 and Max_Data=31 2211:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2212:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetDEAssertionTime(const USART_TypeDef *USARTx) 2213:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2214:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_DEAT) >> USART_CR1_DEAT_Pos); 2215:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2216:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2217:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2218:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Enable Driver Enable (DE) Mode 2219:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not 2220:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Driver Enable feature is supported by the USARTx instance. 2221:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 DEM LL_USART_EnableDEMode 2222:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2223:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 2224:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2225:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableDEMode(USART_TypeDef *USARTx) 2226:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2227:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** SET_BIT(USARTx->CR3, USART_CR3_DEM); 2228:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2229:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2230:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2231:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Disable Driver Enable (DE) Mode 2232:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not 2233:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Driver Enable feature is supported by the USARTx instance. 2234:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 DEM LL_USART_DisableDEMode 2235:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2236:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 2237:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2238:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableDEMode(USART_TypeDef *USARTx) 2239:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2240:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** CLEAR_BIT(USARTx->CR3, USART_CR3_DEM); 2241:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2242:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2243:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** ARM GAS /tmp/ccdsDELB.s page 383 2244:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Indicate if Driver Enable (DE) Mode is enabled 2245:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not 2246:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Driver Enable feature is supported by the USARTx instance. 2247:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 DEM LL_USART_IsEnabledDEMode 2248:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2249:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). 2250:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2251:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledDEMode(const USART_TypeDef *USARTx) 2252:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2253:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->CR3, USART_CR3_DEM) == (USART_CR3_DEM)) ? 1UL : 0UL); 2254:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2255:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2256:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2257:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Select Driver Enable Polarity 2258:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not 2259:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Driver Enable feature is supported by the USARTx instance. 2260:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 DEP LL_USART_SetDESignalPolarity 2261:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2262:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param Polarity This parameter can be one of the following values: 2263:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_DE_POLARITY_HIGH 2264:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_DE_POLARITY_LOW 2265:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 2266:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2267:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetDESignalPolarity(USART_TypeDef *USARTx, uint32_t Polarity) 2268:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2269:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** MODIFY_REG(USARTx->CR3, USART_CR3_DEP, Polarity); 2270:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2271:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2272:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2273:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Return Driver Enable Polarity 2274:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not 2275:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Driver Enable feature is supported by the USARTx instance. 2276:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 DEP LL_USART_GetDESignalPolarity 2277:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2278:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Returned value can be one of the following values: 2279:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_DE_POLARITY_HIGH 2280:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_DE_POLARITY_LOW 2281:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2282:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetDESignalPolarity(const USART_TypeDef *USARTx) 2283:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2284:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_DEP)); 2285:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2286:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2287:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2288:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} 2289:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2290:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2291:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EF_AdvancedConfiguration Advanced Configurations services 2292:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ 2293:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2294:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2295:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2296:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Perform basic configuration of USART for enabling use in Asynchronous Mode (UART) 2297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note In UART mode, the following bits must be kept cleared: 2298:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - LINEN bit in the USART_CR2 register, 2299:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - CLKEN bit in the USART_CR2 register, 2300:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - SCEN bit in the USART_CR3 register, ARM GAS /tmp/ccdsDELB.s page 384 2301:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - IREN bit in the USART_CR3 register, 2302:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - HDSEL bit in the USART_CR3 register. 2303:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Call of this function is equivalent to following function call sequence : 2304:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function 2305:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function 2306:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function 2307:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function 2308:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function 2309:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Other remaining configurations items related to Asynchronous Mode 2310:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * (as Baud Rate, Word length, Parity, ...) should be set using 2311:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * dedicated functions 2312:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 LINEN LL_USART_ConfigAsyncMode\n 2313:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR2 CLKEN LL_USART_ConfigAsyncMode\n 2314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR3 SCEN LL_USART_ConfigAsyncMode\n 2315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR3 IREN LL_USART_ConfigAsyncMode\n 2316:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR3 HDSEL LL_USART_ConfigAsyncMode 2317:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2318:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 2319:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2320:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_ConfigAsyncMode(USART_TypeDef *USARTx) 2321:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2322:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* In Asynchronous mode, the following bits must be kept cleared: 2323:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** - LINEN, CLKEN bits in the USART_CR2 register, 2324:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** - SCEN, IREN and HDSEL bits in the USART_CR3 register. 2325:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2326:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); 2327:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN | USART_CR3_HDSEL)); 2328:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2329:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2330:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2331:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Perform basic configuration of USART for enabling use in Synchronous Mode 2332:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note In Synchronous mode, the following bits must be kept cleared: 2333:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - LINEN bit in the USART_CR2 register, 2334:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - SCEN bit in the USART_CR3 register, 2335:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - IREN bit in the USART_CR3 register, 2336:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - HDSEL bit in the USART_CR3 register. 2337:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * This function also sets the USART in Synchronous mode. 2338:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not 2339:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Synchronous mode is supported by the USARTx instance. 2340:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Call of this function is equivalent to following function call sequence : 2341:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function 2342:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function 2343:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function 2344:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function 2345:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Set CLKEN in CR2 using @ref LL_USART_EnableSCLKOutput() function 2346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Other remaining configurations items related to Synchronous Mode 2347:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * (as Baud Rate, Word length, Parity, Clock Polarity, ...) should be set using 2348:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * dedicated functions 2349:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 LINEN LL_USART_ConfigSyncMode\n 2350:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR2 CLKEN LL_USART_ConfigSyncMode\n 2351:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR3 SCEN LL_USART_ConfigSyncMode\n 2352:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR3 IREN LL_USART_ConfigSyncMode\n 2353:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR3 HDSEL LL_USART_ConfigSyncMode 2354:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2355:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 2356:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2357:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_ConfigSyncMode(USART_TypeDef *USARTx) ARM GAS /tmp/ccdsDELB.s page 385 2358:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2359:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* In Synchronous mode, the following bits must be kept cleared: 2360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** - LINEN bit in the USART_CR2 register, 2361:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** - SCEN, IREN and HDSEL bits in the USART_CR3 register. 2362:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2363:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN)); 2364:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN | USART_CR3_HDSEL)); 2365:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* set the UART/USART in Synchronous mode */ 2366:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** SET_BIT(USARTx->CR2, USART_CR2_CLKEN); 2367:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2368:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2369:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Perform basic configuration of USART for enabling use in LIN Mode 2371:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note In LIN mode, the following bits must be kept cleared: 2372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - STOP and CLKEN bits in the USART_CR2 register, 2373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - SCEN bit in the USART_CR3 register, 2374:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - IREN bit in the USART_CR3 register, 2375:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - HDSEL bit in the USART_CR3 register. 2376:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * This function also set the UART/USART in LIN mode. 2377:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not 2378:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * LIN feature is supported by the USARTx instance. 2379:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Call of this function is equivalent to following function call sequence : 2380:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function 2381:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Clear STOP in CR2 using @ref LL_USART_SetStopBitsLength() function 2382:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function 2383:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function 2384:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function 2385:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Set LINEN in CR2 using @ref LL_USART_EnableLIN() function 2386:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Other remaining configurations items related to LIN Mode 2387:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * (as Baud Rate, Word length, LIN Break Detection Length, ...) should be set using 2388:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * dedicated functions 2389:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 CLKEN LL_USART_ConfigLINMode\n 2390:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR2 STOP LL_USART_ConfigLINMode\n 2391:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR2 LINEN LL_USART_ConfigLINMode\n 2392:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR3 IREN LL_USART_ConfigLINMode\n 2393:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR3 SCEN LL_USART_ConfigLINMode\n 2394:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR3 HDSEL LL_USART_ConfigLINMode 2395:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2396:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 2397:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2398:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_ConfigLINMode(USART_TypeDef *USARTx) 2399:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2400:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* In LIN mode, the following bits must be kept cleared: 2401:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** - STOP and CLKEN bits in the USART_CR2 register, 2402:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** - IREN, SCEN and HDSEL bits in the USART_CR3 register. 2403:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2404:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** CLEAR_BIT(USARTx->CR2, (USART_CR2_CLKEN | USART_CR2_STOP)); 2405:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** CLEAR_BIT(USARTx->CR3, (USART_CR3_IREN | USART_CR3_SCEN | USART_CR3_HDSEL)); 2406:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* Set the UART/USART in LIN mode */ 2407:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** SET_BIT(USARTx->CR2, USART_CR2_LINEN); 2408:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2409:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2410:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2411:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Perform basic configuration of USART for enabling use in Half Duplex Mode 2412:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note In Half Duplex mode, the following bits must be kept cleared: 2413:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - LINEN bit in the USART_CR2 register, 2414:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - CLKEN bit in the USART_CR2 register, ARM GAS /tmp/ccdsDELB.s page 386 2415:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - SCEN bit in the USART_CR3 register, 2416:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - IREN bit in the USART_CR3 register, 2417:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * This function also sets the UART/USART in Half Duplex mode. 2418:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not 2419:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Half-Duplex mode is supported by the USARTx instance. 2420:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Call of this function is equivalent to following function call sequence : 2421:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function 2422:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function 2423:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function 2424:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function 2425:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Set HDSEL in CR3 using @ref LL_USART_EnableHalfDuplex() function 2426:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Other remaining configurations items related to Half Duplex Mode 2427:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * (as Baud Rate, Word length, Parity, ...) should be set using 2428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * dedicated functions 2429:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 LINEN LL_USART_ConfigHalfDuplexMode\n 2430:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR2 CLKEN LL_USART_ConfigHalfDuplexMode\n 2431:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR3 HDSEL LL_USART_ConfigHalfDuplexMode\n 2432:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR3 SCEN LL_USART_ConfigHalfDuplexMode\n 2433:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR3 IREN LL_USART_ConfigHalfDuplexMode 2434:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2435:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 2436:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2437:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_ConfigHalfDuplexMode(USART_TypeDef *USARTx) 2438:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2439:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* In Half Duplex mode, the following bits must be kept cleared: 2440:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** - LINEN and CLKEN bits in the USART_CR2 register, 2441:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** - SCEN and IREN bits in the USART_CR3 register. 2442:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2443:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); 2444:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN)); 2445:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* set the UART/USART in Half Duplex mode */ 2446:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** SET_BIT(USARTx->CR3, USART_CR3_HDSEL); 2447:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2448:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2449:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2450:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Perform basic configuration of USART for enabling use in Smartcard Mode 2451:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note In Smartcard mode, the following bits must be kept cleared: 2452:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - LINEN bit in the USART_CR2 register, 2453:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - IREN bit in the USART_CR3 register, 2454:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - HDSEL bit in the USART_CR3 register. 2455:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * This function also configures Stop bits to 1.5 bits and 2456:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * sets the USART in Smartcard mode (SCEN bit). 2457:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Clock Output is also enabled (CLKEN). 2458:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not 2459:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Smartcard feature is supported by the USARTx instance. 2460:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Call of this function is equivalent to following function call sequence : 2461:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function 2462:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function 2463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function 2464:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Configure STOP in CR2 using @ref LL_USART_SetStopBitsLength() function 2465:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Set CLKEN in CR2 using @ref LL_USART_EnableSCLKOutput() function 2466:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Set SCEN in CR3 using @ref LL_USART_EnableSmartcard() function 2467:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Other remaining configurations items related to Smartcard Mode 2468:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * (as Baud Rate, Word length, Parity, ...) should be set using 2469:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * dedicated functions 2470:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 LINEN LL_USART_ConfigSmartcardMode\n 2471:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR2 STOP LL_USART_ConfigSmartcardMode\n ARM GAS /tmp/ccdsDELB.s page 387 2472:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR2 CLKEN LL_USART_ConfigSmartcardMode\n 2473:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR3 HDSEL LL_USART_ConfigSmartcardMode\n 2474:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR3 SCEN LL_USART_ConfigSmartcardMode 2475:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2476:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 2477:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2478:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_ConfigSmartcardMode(USART_TypeDef *USARTx) 2479:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2480:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* In Smartcard mode, the following bits must be kept cleared: 2481:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** - LINEN bit in the USART_CR2 register, 2482:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** - IREN and HDSEL bits in the USART_CR3 register. 2483:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2484:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN)); 2485:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** CLEAR_BIT(USARTx->CR3, (USART_CR3_IREN | USART_CR3_HDSEL)); 2486:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* Configure Stop bits to 1.5 bits */ 2487:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* Synchronous mode is activated by default */ 2488:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** SET_BIT(USARTx->CR2, (USART_CR2_STOP_0 | USART_CR2_STOP_1 | USART_CR2_CLKEN)); 2489:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* set the UART/USART in Smartcard mode */ 2490:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** SET_BIT(USARTx->CR3, USART_CR3_SCEN); 2491:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2492:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2493:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2494:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Perform basic configuration of USART for enabling use in Irda Mode 2495:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note In IRDA mode, the following bits must be kept cleared: 2496:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - LINEN bit in the USART_CR2 register, 2497:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - STOP and CLKEN bits in the USART_CR2 register, 2498:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - SCEN bit in the USART_CR3 register, 2499:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - HDSEL bit in the USART_CR3 register. 2500:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * This function also sets the UART/USART in IRDA mode (IREN bit). 2501:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not 2502:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * IrDA feature is supported by the USARTx instance. 2503:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Call of this function is equivalent to following function call sequence : 2504:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function 2505:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function 2506:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function 2507:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function 2508:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Configure STOP in CR2 using @ref LL_USART_SetStopBitsLength() function 2509:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Set IREN in CR3 using @ref LL_USART_EnableIrda() function 2510:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Other remaining configurations items related to Irda Mode 2511:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * (as Baud Rate, Word length, Power mode, ...) should be set using 2512:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * dedicated functions 2513:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 LINEN LL_USART_ConfigIrdaMode\n 2514:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR2 CLKEN LL_USART_ConfigIrdaMode\n 2515:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR2 STOP LL_USART_ConfigIrdaMode\n 2516:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR3 SCEN LL_USART_ConfigIrdaMode\n 2517:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR3 HDSEL LL_USART_ConfigIrdaMode\n 2518:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR3 IREN LL_USART_ConfigIrdaMode 2519:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2520:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 2521:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2522:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_ConfigIrdaMode(USART_TypeDef *USARTx) 2523:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2524:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* In IRDA mode, the following bits must be kept cleared: 2525:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** - LINEN, STOP and CLKEN bits in the USART_CR2 register, 2526:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** - SCEN and HDSEL bits in the USART_CR3 register. 2527:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2528:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN | USART_CR2_STOP)); ARM GAS /tmp/ccdsDELB.s page 388 2529:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL)); 2530:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* set the UART/USART in IRDA mode */ 2531:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** SET_BIT(USARTx->CR3, USART_CR3_IREN); 2532:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2533:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2534:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2535:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Perform basic configuration of USART for enabling use in Multi processor Mode 2536:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * (several USARTs connected in a network, one of the USARTs can be the master, 2537:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * its TX output connected to the RX inputs of the other slaves USARTs). 2538:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note In MultiProcessor mode, the following bits must be kept cleared: 2539:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - LINEN bit in the USART_CR2 register, 2540:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - CLKEN bit in the USART_CR2 register, 2541:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - SCEN bit in the USART_CR3 register, 2542:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - IREN bit in the USART_CR3 register, 2543:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - HDSEL bit in the USART_CR3 register. 2544:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Call of this function is equivalent to following function call sequence : 2545:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function 2546:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function 2547:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function 2548:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function 2549:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function 2550:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Other remaining configurations items related to Multi processor Mode 2551:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * (as Baud Rate, Wake Up Method, Node address, ...) should be set using 2552:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * dedicated functions 2553:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 LINEN LL_USART_ConfigMultiProcessMode\n 2554:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR2 CLKEN LL_USART_ConfigMultiProcessMode\n 2555:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR3 SCEN LL_USART_ConfigMultiProcessMode\n 2556:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR3 HDSEL LL_USART_ConfigMultiProcessMode\n 2557:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR3 IREN LL_USART_ConfigMultiProcessMode 2558:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2559:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 2560:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2561:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_ConfigMultiProcessMode(USART_TypeDef *USARTx) 2562:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2563:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* In Multi Processor mode, the following bits must be kept cleared: 2564:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** - LINEN and CLKEN bits in the USART_CR2 register, 2565:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** - IREN, SCEN and HDSEL bits in the USART_CR3 register. 2566:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2567:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); 2568:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN)); 2569:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2570:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2571:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2572:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} 2573:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2574:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2575:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EF_FLAG_Management FLAG_Management 2576:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ 2577:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2578:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2579:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2580:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if the USART Parity Error Flag is set or not 2581:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll ISR PE LL_USART_IsActiveFlag_PE 2582:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2583:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). 2584:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2585:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_PE(const USART_TypeDef *USARTx) ARM GAS /tmp/ccdsDELB.s page 389 2586:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2587:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->ISR, USART_ISR_PE) == (USART_ISR_PE)) ? 1UL : 0UL); 2588:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2589:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2590:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2591:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if the USART Framing Error Flag is set or not 2592:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll ISR FE LL_USART_IsActiveFlag_FE 2593:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2594:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). 2595:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2596:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_FE(const USART_TypeDef *USARTx) 2597:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2598:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->ISR, USART_ISR_FE) == (USART_ISR_FE)) ? 1UL : 0UL); 2599:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2600:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2601:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2602:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if the USART Noise error detected Flag is set or not 2603:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll ISR NE LL_USART_IsActiveFlag_NE 2604:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2605:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). 2606:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2607:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_NE(const USART_TypeDef *USARTx) 2608:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2609:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->ISR, USART_ISR_NE) == (USART_ISR_NE)) ? 1UL : 0UL); 2610:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2611:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2612:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2613:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if the USART OverRun Error Flag is set or not 2614:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll ISR ORE LL_USART_IsActiveFlag_ORE 2615:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2616:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). 2617:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2618:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ORE(const USART_TypeDef *USARTx) 2619:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2620:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->ISR, USART_ISR_ORE) == (USART_ISR_ORE)) ? 1UL : 0UL); 2621:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2622:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2623:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2624:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if the USART IDLE line detected Flag is set or not 2625:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll ISR IDLE LL_USART_IsActiveFlag_IDLE 2626:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2627:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). 2628:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2629:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_IDLE(const USART_TypeDef *USARTx) 2630:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2631:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->ISR, USART_ISR_IDLE) == (USART_ISR_IDLE)) ? 1UL : 0UL); 2632:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2633:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2634:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2635:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if the USART Read Data Register Not Empty Flag is set or not 2636:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll ISR RXNE LL_USART_IsActiveFlag_RXNE 2637:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2638:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). 2639:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2640:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXNE(const USART_TypeDef *USARTx) 2641:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2642:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->ISR, USART_ISR_RXNE) == (USART_ISR_RXNE)) ? 1UL : 0UL); ARM GAS /tmp/ccdsDELB.s page 390 2643:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2644:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2645:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2646:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if the USART Transmission Complete Flag is set or not 2647:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll ISR TC LL_USART_IsActiveFlag_TC 2648:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2649:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). 2650:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2651:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TC(const USART_TypeDef *USARTx) 2652:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2653:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->ISR, USART_ISR_TC) == (USART_ISR_TC)) ? 1UL : 0UL); 2654:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2655:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2656:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2657:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if the USART Transmit Data Register Empty Flag is set or not 2658:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll ISR TXE LL_USART_IsActiveFlag_TXE 2659:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2660:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). 2661:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2662:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXE(const USART_TypeDef *USARTx) 2663:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2664:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->ISR, USART_ISR_TXE) == (USART_ISR_TXE)) ? 1UL : 0UL); 2665:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2666:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2667:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2668:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if the USART LIN Break Detection Flag is set or not 2669:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not 2670:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * LIN feature is supported by the USARTx instance. 2671:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll ISR LBDF LL_USART_IsActiveFlag_LBD 2672:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2673:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). 2674:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2675:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_LBD(const USART_TypeDef *USARTx) 2676:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2677:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->ISR, USART_ISR_LBDF) == (USART_ISR_LBDF)) ? 1UL : 0UL); 2678:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2679:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2680:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2681:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if the USART CTS interrupt Flag is set or not 2682:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not 2683:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Hardware Flow control feature is supported by the USARTx instance. 2684:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll ISR CTSIF LL_USART_IsActiveFlag_nCTS 2685:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2686:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). 2687:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2688:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_nCTS(const USART_TypeDef *USARTx) 2689:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2690:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->ISR, USART_ISR_CTSIF) == (USART_ISR_CTSIF)) ? 1UL : 0UL); 2691:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2692:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2693:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2694:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if the USART CTS Flag is set or not 2695:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not 2696:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Hardware Flow control feature is supported by the USARTx instance. 2697:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll ISR CTS LL_USART_IsActiveFlag_CTS 2698:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2699:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). ARM GAS /tmp/ccdsDELB.s page 391 2700:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2701:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_CTS(const USART_TypeDef *USARTx) 2702:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2703:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->ISR, USART_ISR_CTS) == (USART_ISR_CTS)) ? 1UL : 0UL); 2704:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2705:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2706:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2707:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if the USART Receiver Time Out Flag is set or not 2708:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll ISR RTOF LL_USART_IsActiveFlag_RTO 2709:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2710:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). 2711:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2712:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RTO(const USART_TypeDef *USARTx) 2713:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2714:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->ISR, USART_ISR_RTOF) == (USART_ISR_RTOF)) ? 1UL : 0UL); 2715:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2716:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2717:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2718:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if the USART End Of Block Flag is set or not 2719:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not 2720:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Smartcard feature is supported by the USARTx instance. 2721:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll ISR EOBF LL_USART_IsActiveFlag_EOB 2722:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2723:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). 2724:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2725:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_EOB(const USART_TypeDef *USARTx) 2726:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2727:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->ISR, USART_ISR_EOBF) == (USART_ISR_EOBF)) ? 1UL : 0UL); 2728:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2729:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2730:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2731:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if the USART Auto-Baud Rate Error Flag is set or not 2732:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or 2733:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Auto Baud Rate detection feature is supported by the USARTx instance. 2734:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll ISR ABRE LL_USART_IsActiveFlag_ABRE 2735:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2736:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). 2737:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2738:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ABRE(const USART_TypeDef *USARTx) 2739:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2740:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->ISR, USART_ISR_ABRE) == (USART_ISR_ABRE)) ? 1UL : 0UL); 2741:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2742:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2743:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2744:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if the USART Auto-Baud Rate Flag is set or not 2745:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or 2746:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Auto Baud Rate detection feature is supported by the USARTx instance. 2747:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll ISR ABRF LL_USART_IsActiveFlag_ABR 2748:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2749:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). 2750:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2751:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ABR(const USART_TypeDef *USARTx) 2752:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2753:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->ISR, USART_ISR_ABRF) == (USART_ISR_ABRF)) ? 1UL : 0UL); 2754:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2755:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2756:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** ARM GAS /tmp/ccdsDELB.s page 392 2757:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if the USART Busy Flag is set or not 2758:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll ISR BUSY LL_USART_IsActiveFlag_BUSY 2759:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2760:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). 2761:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2762:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_BUSY(const USART_TypeDef *USARTx) 2763:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2764:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->ISR, USART_ISR_BUSY) == (USART_ISR_BUSY)) ? 1UL : 0UL); 2765:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2766:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2767:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2768:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if the USART Character Match Flag is set or not 2769:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll ISR CMF LL_USART_IsActiveFlag_CM 2770:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2771:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). 2772:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2773:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_CM(const USART_TypeDef *USARTx) 2774:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2775:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->ISR, USART_ISR_CMF) == (USART_ISR_CMF)) ? 1UL : 0UL); 2776:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2777:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2778:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2779:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if the USART Send Break Flag is set or not 2780:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll ISR SBKF LL_USART_IsActiveFlag_SBK 2781:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2782:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). 2783:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2784:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_SBK(const USART_TypeDef *USARTx) 2785:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2786:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->ISR, USART_ISR_SBKF) == (USART_ISR_SBKF)) ? 1UL : 0UL); 2787:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2788:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2789:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2790:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if the USART Receive Wake Up from mute mode Flag is set or not 2791:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll ISR RWU LL_USART_IsActiveFlag_RWU 2792:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2793:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). 2794:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2795:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RWU(const USART_TypeDef *USARTx) 2796:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2797:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->ISR, USART_ISR_RWU) == (USART_ISR_RWU)) ? 1UL : 0UL); 2798:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2799:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2800:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_CR1_UESM) 2801:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_CR3_WUFIE) 2802:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2803:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if the USART Wake Up from stop mode Flag is set or not 2804:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not 2805:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Wake-up from Stop mode feature is supported by the USARTx instance. 2806:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll ISR WUF LL_USART_IsActiveFlag_WKUP 2807:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2808:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). 2809:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2810:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_WKUP(const USART_TypeDef *USARTx) 2811:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2812:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->ISR, USART_ISR_WUF) == (USART_ISR_WUF)) ? 1UL : 0UL); 2813:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } ARM GAS /tmp/ccdsDELB.s page 393 2814:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2815:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_CR3_WUFIE */ 2816:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_CR1_UESM */ 2817:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2818:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if the USART Transmit Enable Acknowledge Flag is set or not 2819:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll ISR TEACK LL_USART_IsActiveFlag_TEACK 2820:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2821:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). 2822:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2823:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TEACK(const USART_TypeDef *USARTx) 2824:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2825:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->ISR, USART_ISR_TEACK) == (USART_ISR_TEACK)) ? 1UL : 0UL); 2826:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2827:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2828:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_ISR_REACK) 2829:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2830:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if the USART Receive Enable Acknowledge Flag is set or not 2831:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll ISR REACK LL_USART_IsActiveFlag_REACK 2832:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2833:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). 2834:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2835:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_REACK(const USART_TypeDef *USARTx) 2836:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2837:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->ISR, USART_ISR_REACK) == (USART_ISR_REACK)) ? 1UL : 0UL); 2838:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2839:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2840:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_ISR_REACK */ 2841:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_TCBGT_SUPPORT) 2842:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* Function available only on devices supporting Transmit Complete before Guard Time feature */ 2843:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2844:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if the Smartcard Transmission Complete Before Guard Time Flag is set or not 2845:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll ISR TCBGT LL_USART_IsActiveFlag_TCBGT 2846:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2847:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). 2848:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2849:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TCBGT(const USART_TypeDef *USARTx) 2850:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2851:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->ISR, USART_ISR_TCBGT) == (USART_ISR_TCBGT)) ? 1UL : 0UL); 2852:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2853:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2854:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_TCBGT_SUPPORT */ 2855:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2856:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Clear Parity Error Flag 2857:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll ICR PECF LL_USART_ClearFlag_PE 2858:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2859:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 2860:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2861:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_ClearFlag_PE(USART_TypeDef *USARTx) 2862:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2863:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** WRITE_REG(USARTx->ICR, USART_ICR_PECF); 2864:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2865:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2866:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2867:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Clear Framing Error Flag 2868:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll ICR FECF LL_USART_ClearFlag_FE 2869:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2870:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None ARM GAS /tmp/ccdsDELB.s page 394 2871:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2872:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_ClearFlag_FE(USART_TypeDef *USARTx) 2873:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2874:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** WRITE_REG(USARTx->ICR, USART_ICR_FECF); 2875:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2876:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2877:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2878:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Clear Noise Error detected Flag 2879:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll ICR NCF LL_USART_ClearFlag_NE 2880:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2881:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 2882:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2883:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_ClearFlag_NE(USART_TypeDef *USARTx) 2884:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2885:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** WRITE_REG(USARTx->ICR, USART_ICR_NCF); 2886:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2887:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2888:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2889:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Clear OverRun Error Flag 2890:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll ICR ORECF LL_USART_ClearFlag_ORE 2891:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2892:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 2893:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2894:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_ClearFlag_ORE(USART_TypeDef *USARTx) 2895:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2896:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** WRITE_REG(USARTx->ICR, USART_ICR_ORECF); 2897:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2898:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2899:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2900:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Clear IDLE line detected Flag 2901:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll ICR IDLECF LL_USART_ClearFlag_IDLE 2902:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2903:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 2904:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2905:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_ClearFlag_IDLE(USART_TypeDef *USARTx) 2906:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** WRITE_REG(USARTx->ICR, USART_ICR_IDLECF); 2908:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2909:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2910:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2911:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Clear Transmission Complete Flag 2912:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll ICR TCCF LL_USART_ClearFlag_TC 2913:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2914:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 2915:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2916:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_ClearFlag_TC(USART_TypeDef *USARTx) 2917:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** WRITE_REG(USARTx->ICR, USART_ICR_TCCF); 2919:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2920:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2921:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_TCBGT_SUPPORT) 2922:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* Function available only on devices supporting Transmit Complete before Guard Time feature */ 2923:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2924:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Clear Smartcard Transmission Complete Before Guard Time Flag 2925:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll ICR TCBGTCF LL_USART_ClearFlag_TCBGT 2926:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2927:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None ARM GAS /tmp/ccdsDELB.s page 395 2928:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2929:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_ClearFlag_TCBGT(USART_TypeDef *USARTx) 2930:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2931:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** WRITE_REG(USARTx->ICR, USART_ICR_TCBGTCF); 2932:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2933:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_TCBGT_SUPPORT */ 2934:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2935:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2936:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Clear LIN Break Detection Flag 2937:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not 2938:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * LIN feature is supported by the USARTx instance. 2939:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll ICR LBDCF LL_USART_ClearFlag_LBD 2940:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2941:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 2942:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2943:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_ClearFlag_LBD(USART_TypeDef *USARTx) 2944:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2945:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** WRITE_REG(USARTx->ICR, USART_ICR_LBDCF); 2946:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2947:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2948:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2949:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Clear CTS Interrupt Flag 2950:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not 2951:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Hardware Flow control feature is supported by the USARTx instance. 2952:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll ICR CTSCF LL_USART_ClearFlag_nCTS 2953:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2954:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 2955:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2956:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_ClearFlag_nCTS(USART_TypeDef *USARTx) 2957:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2958:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** WRITE_REG(USARTx->ICR, USART_ICR_CTSCF); 2959:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2960:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2961:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2962:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Clear Receiver Time Out Flag 2963:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll ICR RTOCF LL_USART_ClearFlag_RTO 2964:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2965:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 2966:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2967:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_ClearFlag_RTO(USART_TypeDef *USARTx) 2968:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2969:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** WRITE_REG(USARTx->ICR, USART_ICR_RTOCF); 2970:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2971:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2972:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2973:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Clear End Of Block Flag 2974:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not 2975:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Smartcard feature is supported by the USARTx instance. 2976:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll ICR EOBCF LL_USART_ClearFlag_EOB 2977:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2978:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 2979:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2980:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_ClearFlag_EOB(USART_TypeDef *USARTx) 2981:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2982:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** WRITE_REG(USARTx->ICR, USART_ICR_EOBCF); 2983:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2984:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ARM GAS /tmp/ccdsDELB.s page 396 2985:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2986:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Clear Character Match Flag 2987:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll ICR CMCF LL_USART_ClearFlag_CM 2988:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2989:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 2990:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2991:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_ClearFlag_CM(USART_TypeDef *USARTx) 2992:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2993:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** WRITE_REG(USARTx->ICR, USART_ICR_CMCF); 2994:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2995:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2996:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_CR1_UESM) 2997:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_CR3_WUFIE) 2998:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2999:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Clear Wake Up from stop mode Flag 3000:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not 3001:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Wake-up from Stop mode feature is supported by the USARTx instance. 3002:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll ICR WUCF LL_USART_ClearFlag_WKUP 3003:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 3004:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 3005:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3006:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_ClearFlag_WKUP(USART_TypeDef *USARTx) 3007:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 3008:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** WRITE_REG(USARTx->ICR, USART_ICR_WUCF); 3009:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 3010:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3011:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_CR3_WUFIE */ 3012:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_CR1_UESM */ 3013:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 3014:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} 3015:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3016:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3017:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EF_IT_Management IT_Management 3018:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ 3019:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3020:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3021:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 3022:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Enable IDLE Interrupt 3023:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 IDLEIE LL_USART_EnableIT_IDLE 3024:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 3025:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 3026:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3027:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableIT_IDLE(USART_TypeDef *USARTx) 3028:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 3029:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_IDLEIE); 3030:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 3031:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3032:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 3033:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Enable RX Not Empty Interrupt 3034:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 RXNEIE LL_USART_EnableIT_RXNE 3035:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 3036:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 3037:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3038:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableIT_RXNE(USART_TypeDef *USARTx) 3039:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 3040:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_RXNEIE); 3041:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } ARM GAS /tmp/ccdsDELB.s page 397 3042:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3043:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 3044:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Enable Transmission Complete Interrupt 3045:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 TCIE LL_USART_EnableIT_TC 3046:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 3047:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 3048:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3049:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableIT_TC(USART_TypeDef *USARTx) 3050:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 3051:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_TCIE); 3052:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 3053:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3054:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 3055:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Enable TX Empty Interrupt 3056:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 TXEIE LL_USART_EnableIT_TXE 3057:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 3058:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 3059:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3060:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableIT_TXE(USART_TypeDef *USARTx) 3061:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 3062:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_TXEIE); 3063:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 3064:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3065:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 3066:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Enable Parity Error Interrupt 3067:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 PEIE LL_USART_EnableIT_PE 3068:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 3069:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 3070:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3071:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableIT_PE(USART_TypeDef *USARTx) 3072:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 3073:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_PEIE); 3074:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 3075:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3076:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 3077:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Enable Character Match Interrupt 3078:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 CMIE LL_USART_EnableIT_CM 3079:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 3080:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 3081:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3082:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableIT_CM(USART_TypeDef *USARTx) 3083:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 3084:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_CMIE); 3085:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 3086:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3087:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 3088:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Enable Receiver Timeout Interrupt 3089:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 RTOIE LL_USART_EnableIT_RTO 3090:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 3091:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 3092:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3093:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableIT_RTO(USART_TypeDef *USARTx) 3094:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 3095:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_RTOIE); 3096:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 3097:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3098:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** ARM GAS /tmp/ccdsDELB.s page 398 3099:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Enable End Of Block Interrupt 3100:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not 3101:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Smartcard feature is supported by the USARTx instance. 3102:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 EOBIE LL_USART_EnableIT_EOB 3103:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 3104:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 3105:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3106:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableIT_EOB(USART_TypeDef *USARTx) 3107:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 3108:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_EOBIE); 3109:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 3110:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3111:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 3112:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Enable LIN Break Detection Interrupt 3113:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not 3114:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * LIN feature is supported by the USARTx instance. 3115:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 LBDIE LL_USART_EnableIT_LBD 3116:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 3117:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 3118:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3119:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableIT_LBD(USART_TypeDef *USARTx) 3120:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 3121:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** SET_BIT(USARTx->CR2, USART_CR2_LBDIE); 3122:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 3123:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3124:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 3125:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Enable Error Interrupt 3126:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a fram 3127:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the USARTx_ISR register). 3128:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * 0: Interrupt is inhibited 3129:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * 1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the USARTx_ISR register. 3130:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 EIE LL_USART_EnableIT_ERROR 3131:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 3132:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 3133:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3134:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableIT_ERROR(USART_TypeDef *USARTx) 3135:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 3136:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_EIE); 3137:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 3138:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3139:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 3140:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Enable CTS Interrupt 3141:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not 3142:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Hardware Flow control feature is supported by the USARTx instance. 3143:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 CTSIE LL_USART_EnableIT_CTS 3144:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 3145:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 3146:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3147:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableIT_CTS(USART_TypeDef *USARTx) 3148:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 3149:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_CTSIE); 3150:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 3151:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3152:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_CR1_UESM) 3153:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_CR3_WUFIE) 3154:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 3155:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Enable Wake Up from Stop Mode Interrupt ARM GAS /tmp/ccdsDELB.s page 399 3156:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not 3157:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Wake-up from Stop mode feature is supported by the USARTx instance. 3158:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 WUFIE LL_USART_EnableIT_WKUP 3159:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 3160:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 3161:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3162:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableIT_WKUP(USART_TypeDef *USARTx) 3163:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 3164:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_WUFIE); 3165:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 3166:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3167:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_CR3_WUFIE */ 3168:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_CR1_UESM */ 3169:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_TCBGT_SUPPORT) 3170:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* Function available only on devices supporting Transmit Complete before Guard Time feature */ 3171:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 3172:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Enable Smartcard Transmission Complete Before Guard Time Interrupt 3173:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not 3174:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Smartcard feature is supported by the USARTx instance. 3175:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 TCBGTIE LL_USART_EnableIT_TCBGT 3176:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 3177:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 3178:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3179:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableIT_TCBGT(USART_TypeDef *USARTx) 3180:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 3181:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_TCBGTIE); 3182:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 3183:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_TCBGT_SUPPORT */ 3184:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3185:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 3186:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Disable IDLE Interrupt 3187:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 IDLEIE LL_USART_DisableIT_IDLE 3188:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 3189:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 3190:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3191:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableIT_IDLE(USART_TypeDef *USARTx) 3192:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 3193:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_IDLEIE); 3194:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 3195:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3196:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 3197:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Disable RX Not Empty Interrupt 3198:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 RXNEIE LL_USART_DisableIT_RXNE 3199:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 3200:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 3201:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3202:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableIT_RXNE(USART_TypeDef *USARTx) 3203:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 3204:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_RXNEIE); 3205:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 3206:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3207:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 3208:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Disable Transmission Complete Interrupt 3209:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 TCIE LL_USART_DisableIT_TC 3210:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 3211:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 3212:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ ARM GAS /tmp/ccdsDELB.s page 400 3213:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableIT_TC(USART_TypeDef *USARTx) 3214:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 3215:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_TCIE); 3216:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 3217:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3218:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 3219:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Disable TX Empty Interrupt 3220:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 TXEIE LL_USART_DisableIT_TXE 3221:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 3222:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 3223:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3224:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableIT_TXE(USART_TypeDef *USARTx) 3225:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 3226:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_TXEIE); 3227:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 3228:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3229:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 3230:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Disable Parity Error Interrupt 3231:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 PEIE LL_USART_DisableIT_PE 3232:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 3233:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 3234:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3235:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableIT_PE(USART_TypeDef *USARTx) 3236:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 3237:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_PEIE); 3238:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 3239:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3240:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 3241:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Disable Character Match Interrupt 3242:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 CMIE LL_USART_DisableIT_CM 3243:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 3244:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 3245:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3246:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableIT_CM(USART_TypeDef *USARTx) 3247:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 3248:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_CMIE); 3249:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 3250:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3251:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 3252:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Disable Receiver Timeout Interrupt 3253:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 RTOIE LL_USART_DisableIT_RTO 3254:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 3255:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 3256:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3257:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableIT_RTO(USART_TypeDef *USARTx) 3258:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 3259:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_RTOIE); 3260:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 3261:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3262:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 3263:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Disable End Of Block Interrupt 3264:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not 3265:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Smartcard feature is supported by the USARTx instance. 3266:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 EOBIE LL_USART_DisableIT_EOB 3267:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 3268:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 3269:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ ARM GAS /tmp/ccdsDELB.s page 401 3270:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableIT_EOB(USART_TypeDef *USARTx) 3271:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 3272:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_EOBIE); 3273:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 3274:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3275:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 3276:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Disable LIN Break Detection Interrupt 3277:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not 3278:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * LIN feature is supported by the USARTx instance. 3279:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 LBDIE LL_USART_DisableIT_LBD 3280:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 3281:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 3282:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3283:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableIT_LBD(USART_TypeDef *USARTx) 3284:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 3285:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** CLEAR_BIT(USARTx->CR2, USART_CR2_LBDIE); 3286:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 3287:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3288:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 3289:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Disable Error Interrupt 3290:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a fram 3291:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the USARTx_ISR register). 3292:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * 0: Interrupt is inhibited 3293:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * 1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the USARTx_ISR register. 3294:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 EIE LL_USART_DisableIT_ERROR 3295:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 3296:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 3297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3298:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableIT_ERROR(USART_TypeDef *USARTx) 3299:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 3300:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_EIE); 3301:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 3302:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3303:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 3304:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Disable CTS Interrupt 3305:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not 3306:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Hardware Flow control feature is supported by the USARTx instance. 3307:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 CTSIE LL_USART_DisableIT_CTS 3308:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 3309:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 3310:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3311:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableIT_CTS(USART_TypeDef *USARTx) 3312:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 3313:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_CTSIE); 3314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 3315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3316:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_CR1_UESM) 3317:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_CR3_WUFIE) 3318:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 3319:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Disable Wake Up from Stop Mode Interrupt 3320:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not 3321:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Wake-up from Stop mode feature is supported by the USARTx instance. 3322:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 WUFIE LL_USART_DisableIT_WKUP 3323:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 3324:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 3325:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3326:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableIT_WKUP(USART_TypeDef *USARTx) ARM GAS /tmp/ccdsDELB.s page 402 3327:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 3328:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_WUFIE); 3329:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 3330:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3331:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_CR3_WUFIE */ 3332:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_CR1_UESM */ 3333:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_TCBGT_SUPPORT) 3334:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* Function available only on devices supporting Transmit Complete before Guard Time feature */ 3335:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 3336:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Disable Smartcard Transmission Complete Before Guard Time Interrupt 3337:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not 3338:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Smartcard feature is supported by the USARTx instance. 3339:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 TCBGTIE LL_USART_DisableIT_TCBGT 3340:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 3341:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 3342:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3343:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableIT_TCBGT(USART_TypeDef *USARTx) 3344:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 3345:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_TCBGTIE); 3346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 3347:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_TCBGT_SUPPORT */ 3348:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3349:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 3350:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if the USART IDLE Interrupt source is enabled or disabled. 3351:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 IDLEIE LL_USART_IsEnabledIT_IDLE 3352:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 3353:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). 3354:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3355:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_IDLE(const USART_TypeDef *USARTx) 3356:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 3357:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->CR1, USART_CR1_IDLEIE) == (USART_CR1_IDLEIE)) ? 1UL : 0UL); 3358:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 3359:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 3361:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if the USART RX Not Empty Interrupt is enabled or disabled. 3362:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 RXNEIE LL_USART_IsEnabledIT_RXNE 3363:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 3364:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). 3365:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3366:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXNE(const USART_TypeDef *USARTx) 3367:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 3368:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->CR1, USART_CR1_RXNEIE) == (USART_CR1_RXNEIE)) ? 1U : 0U); 3369:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 3370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3371:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 3372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if the USART Transmission Complete Interrupt is enabled or disabled. 3373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 TCIE LL_USART_IsEnabledIT_TC 3374:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 3375:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). 3376:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3377:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TC(const USART_TypeDef *USARTx) 3378:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 3379:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->CR1, USART_CR1_TCIE) == (USART_CR1_TCIE)) ? 1UL : 0UL); 3380:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 3381:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3382:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 3383:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if the USART TX Empty Interrupt is enabled or disabled. ARM GAS /tmp/ccdsDELB.s page 403 3384:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 TXEIE LL_USART_IsEnabledIT_TXE 3385:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 3386:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). 3387:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3388:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXE(const USART_TypeDef *USARTx) 3389:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 3390:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->CR1, USART_CR1_TXEIE) == (USART_CR1_TXEIE)) ? 1U : 0U); 3391:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 3392:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3393:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 3394:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if the USART Parity Error Interrupt is enabled or disabled. 3395:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 PEIE LL_USART_IsEnabledIT_PE 3396:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 3397:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). 3398:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3399:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_PE(const USART_TypeDef *USARTx) 3400:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 3401:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->CR1, USART_CR1_PEIE) == (USART_CR1_PEIE)) ? 1UL : 0UL); 3402:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 3403:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3404:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 3405:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if the USART Character Match Interrupt is enabled or disabled. 3406:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 CMIE LL_USART_IsEnabledIT_CM 3407:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 3408:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). 3409:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3410:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_CM(const USART_TypeDef *USARTx) 3411:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 3412:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->CR1, USART_CR1_CMIE) == (USART_CR1_CMIE)) ? 1UL : 0UL); 3413:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 3414:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3415:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 3416:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if the USART Receiver Timeout Interrupt is enabled or disabled. 3417:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 RTOIE LL_USART_IsEnabledIT_RTO 3418:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 3419:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). 3420:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3421:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RTO(const USART_TypeDef *USARTx) 3422:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 3423:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->CR1, USART_CR1_RTOIE) == (USART_CR1_RTOIE)) ? 1UL : 0UL); 3424:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 3425:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3426:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 3427:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if the USART End Of Block Interrupt is enabled or disabled. 3428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not 3429:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Smartcard feature is supported by the USARTx instance. 3430:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 EOBIE LL_USART_IsEnabledIT_EOB 3431:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 3432:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). 3433:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3434:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_EOB(const USART_TypeDef *USARTx) 3435:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 3436:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->CR1, USART_CR1_EOBIE) == (USART_CR1_EOBIE)) ? 1UL : 0UL); 3437:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 3438:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3439:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 3440:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if the USART LIN Break Detection Interrupt is enabled or disabled. ARM GAS /tmp/ccdsDELB.s page 404 3441:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not 3442:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * LIN feature is supported by the USARTx instance. 3443:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 LBDIE LL_USART_IsEnabledIT_LBD 3444:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 3445:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). 3446:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3447:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_LBD(const USART_TypeDef *USARTx) 3448:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 3449:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->CR2, USART_CR2_LBDIE) == (USART_CR2_LBDIE)) ? 1UL : 0UL); 3450:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 3451:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3452:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 3453:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if the USART Error Interrupt is enabled or disabled. 3454:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 EIE LL_USART_IsEnabledIT_ERROR 3455:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 3456:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). 3457:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3458:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_ERROR(const USART_TypeDef *USARTx) 3459:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 3460:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->CR3, USART_CR3_EIE) == (USART_CR3_EIE)) ? 1UL : 0UL); 3461:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 3462:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 3464:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if the USART CTS Interrupt is enabled or disabled. 3465:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not 3466:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Hardware Flow control feature is supported by the USARTx instance. 3467:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 CTSIE LL_USART_IsEnabledIT_CTS 3468:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 3469:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). 3470:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3471:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_CTS(const USART_TypeDef *USARTx) 3472:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 3473:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->CR3, USART_CR3_CTSIE) == (USART_CR3_CTSIE)) ? 1UL : 0UL); 3474:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 3475:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3476:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_CR1_UESM) 3477:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_CR3_WUFIE) 3478:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 3479:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if the USART Wake Up from Stop Mode Interrupt is enabled or disabled. 3480:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not 3481:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Wake-up from Stop mode feature is supported by the USARTx instance. 3482:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 WUFIE LL_USART_IsEnabledIT_WKUP 3483:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 3484:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). 3485:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3486:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_WKUP(const USART_TypeDef *USARTx) 3487:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 3488:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->CR3, USART_CR3_WUFIE) == (USART_CR3_WUFIE)) ? 1UL : 0UL); 3489:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 3490:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3491:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_CR3_WUFIE */ 3492:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_CR1_UESM */ 3493:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_TCBGT_SUPPORT) 3494:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* Function available only on devices supporting Transmit Complete before Guard Time feature */ 3495:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 3496:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if the Smartcard Transmission Complete Before Guard Time Interrupt is enabled or 3497:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not ARM GAS /tmp/ccdsDELB.s page 405 3498:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Smartcard feature is supported by the USARTx instance. 3499:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 TCBGTIE LL_USART_IsEnabledIT_TCBGT 3500:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 3501:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). 3502:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3503:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TCBGT(const USART_TypeDef *USARTx) 3504:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 3505:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->CR3, USART_CR3_TCBGTIE) == (USART_CR3_TCBGTIE)) ? 1UL : 0UL); 3506:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 3507:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_TCBGT_SUPPORT */ 3508:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3509:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 3510:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} 3511:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3512:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3513:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EF_DMA_Management DMA_Management 3514:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ 3515:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3516:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3517:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 3518:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Enable DMA Mode for reception 3519:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 DMAR LL_USART_EnableDMAReq_RX 3520:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 3521:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 3522:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3523:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableDMAReq_RX(USART_TypeDef *USARTx) 3524:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 3525:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_DMAR); 3526:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 3527:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3528:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 3529:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Disable DMA Mode for reception 3530:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 DMAR LL_USART_DisableDMAReq_RX 3531:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 3532:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 3533:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3534:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableDMAReq_RX(USART_TypeDef *USARTx) 3535:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 3536:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_DMAR); 3537:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 3538:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3539:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 3540:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if DMA Mode is enabled for reception 3541:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 DMAR LL_USART_IsEnabledDMAReq_RX 3542:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 3543:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). 3544:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3545:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_RX(const USART_TypeDef *USARTx) 3546:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 3547:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->CR3, USART_CR3_DMAR) == (USART_CR3_DMAR)) ? 1UL : 0UL); 3548:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 3549:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3550:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 3551:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Enable DMA Mode for transmission 3552:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 DMAT LL_USART_EnableDMAReq_TX 3553:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 3554:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None ARM GAS /tmp/ccdsDELB.s page 406 3555:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3556:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableDMAReq_TX(USART_TypeDef *USARTx) 3557:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 3558:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_DMAT); 4712 .loc 7 3558 3 is_stmt 1 view .LVU1612 4713 .LBB471: 4714 .LBB472: 4715 .loc 7 3558 3 view .LVU1613 4716 .loc 7 3558 3 view .LVU1614 4717 .loc 7 3558 3 view .LVU1615 4718 00e8 764A ldr r2, .L182+76 4719 .LVL340: 4720 .LBB473: 4721 .LBI473: 4722 .file 8 "Drivers/CMSIS/Include/cmsis_gcc.h" 1:Drivers/CMSIS/Include/cmsis_gcc.h **** /**************************************************************************//** 2:Drivers/CMSIS/Include/cmsis_gcc.h **** * @file cmsis_gcc.h 3:Drivers/CMSIS/Include/cmsis_gcc.h **** * @brief CMSIS compiler GCC header file 4:Drivers/CMSIS/Include/cmsis_gcc.h **** * @version V5.0.4 5:Drivers/CMSIS/Include/cmsis_gcc.h **** * @date 09. April 2018 6:Drivers/CMSIS/Include/cmsis_gcc.h **** ******************************************************************************/ 7:Drivers/CMSIS/Include/cmsis_gcc.h **** /* 8:Drivers/CMSIS/Include/cmsis_gcc.h **** * Copyright (c) 2009-2018 Arm Limited. All rights reserved. 9:Drivers/CMSIS/Include/cmsis_gcc.h **** * 10:Drivers/CMSIS/Include/cmsis_gcc.h **** * SPDX-License-Identifier: Apache-2.0 11:Drivers/CMSIS/Include/cmsis_gcc.h **** * 12:Drivers/CMSIS/Include/cmsis_gcc.h **** * Licensed under the Apache License, Version 2.0 (the License); you may 13:Drivers/CMSIS/Include/cmsis_gcc.h **** * not use this file except in compliance with the License. 14:Drivers/CMSIS/Include/cmsis_gcc.h **** * You may obtain a copy of the License at 15:Drivers/CMSIS/Include/cmsis_gcc.h **** * 16:Drivers/CMSIS/Include/cmsis_gcc.h **** * www.apache.org/licenses/LICENSE-2.0 17:Drivers/CMSIS/Include/cmsis_gcc.h **** * 18:Drivers/CMSIS/Include/cmsis_gcc.h **** * Unless required by applicable law or agreed to in writing, software 19:Drivers/CMSIS/Include/cmsis_gcc.h **** * distributed under the License is distributed on an AS IS BASIS, WITHOUT 20:Drivers/CMSIS/Include/cmsis_gcc.h **** * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 21:Drivers/CMSIS/Include/cmsis_gcc.h **** * See the License for the specific language governing permissions and 22:Drivers/CMSIS/Include/cmsis_gcc.h **** * limitations under the License. 23:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 24:Drivers/CMSIS/Include/cmsis_gcc.h **** 25:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __CMSIS_GCC_H 26:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_H 27:Drivers/CMSIS/Include/cmsis_gcc.h **** 28:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ignore some GCC warnings */ 29:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push 30:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wsign-conversion" 31:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wconversion" 32:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wunused-parameter" 33:Drivers/CMSIS/Include/cmsis_gcc.h **** 34:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Fallback for __has_builtin */ 35:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __has_builtin 36:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __has_builtin(x) (0) 37:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 38:Drivers/CMSIS/Include/cmsis_gcc.h **** 39:Drivers/CMSIS/Include/cmsis_gcc.h **** /* CMSIS compiler specific defines */ 40:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __ASM 41:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __ASM __asm 42:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif ARM GAS /tmp/ccdsDELB.s page 407 43:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __INLINE 44:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __INLINE inline 45:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 46:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __STATIC_INLINE 47:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __STATIC_INLINE static inline 48:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 49:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __STATIC_FORCEINLINE 50:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline 51:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 52:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __NO_RETURN 53:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __NO_RETURN __attribute__((__noreturn__)) 54:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 55:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __USED 56:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __USED __attribute__((used)) 57:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 58:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __WEAK 59:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __WEAK __attribute__((weak)) 60:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 61:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PACKED 62:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PACKED __attribute__((packed, aligned(1))) 63:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 64:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PACKED_STRUCT 65:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) 66:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 67:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PACKED_UNION 68:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PACKED_UNION union __attribute__((packed, aligned(1))) 69:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 70:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT32 /* deprecated */ 71:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push 72:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" 73:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" 74:Drivers/CMSIS/Include/cmsis_gcc.h **** struct __attribute__((packed)) T_UINT32 { uint32_t v; }; 75:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop 76:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) 77:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 78:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT16_WRITE 79:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push 80:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" 81:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" 82:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; 83:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop 84:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))- 85:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 86:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT16_READ 87:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push 88:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" 89:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" 90:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; 91:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop 92:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(add 93:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 94:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT32_WRITE 95:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push 96:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" 97:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" 98:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; 99:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop ARM GAS /tmp/ccdsDELB.s page 408 100:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))- 101:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 102:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT32_READ 103:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push 104:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" 105:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" 106:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; 107:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop 108:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(add 109:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 110:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __ALIGNED 111:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __ALIGNED(x) __attribute__((aligned(x))) 112:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 113:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __RESTRICT 114:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __RESTRICT __restrict 115:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 116:Drivers/CMSIS/Include/cmsis_gcc.h **** 117:Drivers/CMSIS/Include/cmsis_gcc.h **** 118:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ########################### Core Function Access ########################### */ 119:Drivers/CMSIS/Include/cmsis_gcc.h **** /** \ingroup CMSIS_Core_FunctionInterface 120:Drivers/CMSIS/Include/cmsis_gcc.h **** \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions 121:Drivers/CMSIS/Include/cmsis_gcc.h **** @{ 122:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 123:Drivers/CMSIS/Include/cmsis_gcc.h **** 124:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 125:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Enable IRQ Interrupts 126:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Enables IRQ interrupts by clearing the I-bit in the CPSR. 127:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes. 128:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 129:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __enable_irq(void) 130:Drivers/CMSIS/Include/cmsis_gcc.h **** { 131:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsie i" : : : "memory"); 132:Drivers/CMSIS/Include/cmsis_gcc.h **** } 133:Drivers/CMSIS/Include/cmsis_gcc.h **** 134:Drivers/CMSIS/Include/cmsis_gcc.h **** 135:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 136:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Disable IRQ Interrupts 137:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Disables IRQ interrupts by setting the I-bit in the CPSR. 138:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes. 139:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 140:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __disable_irq(void) 141:Drivers/CMSIS/Include/cmsis_gcc.h **** { 142:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsid i" : : : "memory"); 143:Drivers/CMSIS/Include/cmsis_gcc.h **** } 144:Drivers/CMSIS/Include/cmsis_gcc.h **** 145:Drivers/CMSIS/Include/cmsis_gcc.h **** 146:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 147:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Control Register 148:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the Control Register. 149:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Control Register value 150:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 151:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_CONTROL(void) 152:Drivers/CMSIS/Include/cmsis_gcc.h **** { 153:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 154:Drivers/CMSIS/Include/cmsis_gcc.h **** 155:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, control" : "=r" (result) ); 156:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); ARM GAS /tmp/ccdsDELB.s page 409 157:Drivers/CMSIS/Include/cmsis_gcc.h **** } 158:Drivers/CMSIS/Include/cmsis_gcc.h **** 159:Drivers/CMSIS/Include/cmsis_gcc.h **** 160:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) 161:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 162:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Control Register (non-secure) 163:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the non-secure Control Register when in secure mode. 164:Drivers/CMSIS/Include/cmsis_gcc.h **** \return non-secure Control Register value 165:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 166:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) 167:Drivers/CMSIS/Include/cmsis_gcc.h **** { 168:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 169:Drivers/CMSIS/Include/cmsis_gcc.h **** 170:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); 171:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 172:Drivers/CMSIS/Include/cmsis_gcc.h **** } 173:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 174:Drivers/CMSIS/Include/cmsis_gcc.h **** 175:Drivers/CMSIS/Include/cmsis_gcc.h **** 176:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 177:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Control Register 178:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Writes the given value to the Control Register. 179:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] control Control Register value to set 180:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 181:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) 182:Drivers/CMSIS/Include/cmsis_gcc.h **** { 183:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); 184:Drivers/CMSIS/Include/cmsis_gcc.h **** } 185:Drivers/CMSIS/Include/cmsis_gcc.h **** 186:Drivers/CMSIS/Include/cmsis_gcc.h **** 187:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) 188:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 189:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Control Register (non-secure) 190:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Writes the given value to the non-secure Control Register when in secure state. 191:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] control Control Register value to set 192:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 193:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) 194:Drivers/CMSIS/Include/cmsis_gcc.h **** { 195:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); 196:Drivers/CMSIS/Include/cmsis_gcc.h **** } 197:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 198:Drivers/CMSIS/Include/cmsis_gcc.h **** 199:Drivers/CMSIS/Include/cmsis_gcc.h **** 200:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 201:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get IPSR Register 202:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the IPSR Register. 203:Drivers/CMSIS/Include/cmsis_gcc.h **** \return IPSR Register value 204:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 205:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_IPSR(void) 206:Drivers/CMSIS/Include/cmsis_gcc.h **** { 207:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 208:Drivers/CMSIS/Include/cmsis_gcc.h **** 209:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); 210:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 211:Drivers/CMSIS/Include/cmsis_gcc.h **** } 212:Drivers/CMSIS/Include/cmsis_gcc.h **** 213:Drivers/CMSIS/Include/cmsis_gcc.h **** ARM GAS /tmp/ccdsDELB.s page 410 214:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 215:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get APSR Register 216:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the APSR Register. 217:Drivers/CMSIS/Include/cmsis_gcc.h **** \return APSR Register value 218:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 219:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_APSR(void) 220:Drivers/CMSIS/Include/cmsis_gcc.h **** { 221:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 222:Drivers/CMSIS/Include/cmsis_gcc.h **** 223:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, apsr" : "=r" (result) ); 224:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 225:Drivers/CMSIS/Include/cmsis_gcc.h **** } 226:Drivers/CMSIS/Include/cmsis_gcc.h **** 227:Drivers/CMSIS/Include/cmsis_gcc.h **** 228:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 229:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get xPSR Register 230:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the xPSR Register. 231:Drivers/CMSIS/Include/cmsis_gcc.h **** \return xPSR Register value 232:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 233:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_xPSR(void) 234:Drivers/CMSIS/Include/cmsis_gcc.h **** { 235:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 236:Drivers/CMSIS/Include/cmsis_gcc.h **** 237:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); 238:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 239:Drivers/CMSIS/Include/cmsis_gcc.h **** } 240:Drivers/CMSIS/Include/cmsis_gcc.h **** 241:Drivers/CMSIS/Include/cmsis_gcc.h **** 242:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 243:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Process Stack Pointer 244:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Process Stack Pointer (PSP). 245:Drivers/CMSIS/Include/cmsis_gcc.h **** \return PSP Register value 246:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 247:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_PSP(void) 248:Drivers/CMSIS/Include/cmsis_gcc.h **** { 249:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 250:Drivers/CMSIS/Include/cmsis_gcc.h **** 251:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, psp" : "=r" (result) ); 252:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 253:Drivers/CMSIS/Include/cmsis_gcc.h **** } 254:Drivers/CMSIS/Include/cmsis_gcc.h **** 255:Drivers/CMSIS/Include/cmsis_gcc.h **** 256:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) 257:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 258:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Process Stack Pointer (non-secure) 259:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure s 260:Drivers/CMSIS/Include/cmsis_gcc.h **** \return PSP Register value 261:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 262:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) 263:Drivers/CMSIS/Include/cmsis_gcc.h **** { 264:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 265:Drivers/CMSIS/Include/cmsis_gcc.h **** 266:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); 267:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 268:Drivers/CMSIS/Include/cmsis_gcc.h **** } 269:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 270:Drivers/CMSIS/Include/cmsis_gcc.h **** ARM GAS /tmp/ccdsDELB.s page 411 271:Drivers/CMSIS/Include/cmsis_gcc.h **** 272:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 273:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Process Stack Pointer 274:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Process Stack Pointer (PSP). 275:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfProcStack Process Stack Pointer value to set 276:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 277:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) 278:Drivers/CMSIS/Include/cmsis_gcc.h **** { 279:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); 280:Drivers/CMSIS/Include/cmsis_gcc.h **** } 281:Drivers/CMSIS/Include/cmsis_gcc.h **** 282:Drivers/CMSIS/Include/cmsis_gcc.h **** 283:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) 284:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 285:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Process Stack Pointer (non-secure) 286:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure sta 287:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfProcStack Process Stack Pointer value to set 288:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 289:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) 290:Drivers/CMSIS/Include/cmsis_gcc.h **** { 291:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); 292:Drivers/CMSIS/Include/cmsis_gcc.h **** } 293:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 294:Drivers/CMSIS/Include/cmsis_gcc.h **** 295:Drivers/CMSIS/Include/cmsis_gcc.h **** 296:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 297:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Main Stack Pointer 298:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Main Stack Pointer (MSP). 299:Drivers/CMSIS/Include/cmsis_gcc.h **** \return MSP Register value 300:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 301:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_MSP(void) 302:Drivers/CMSIS/Include/cmsis_gcc.h **** { 303:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 304:Drivers/CMSIS/Include/cmsis_gcc.h **** 305:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, msp" : "=r" (result) ); 306:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 307:Drivers/CMSIS/Include/cmsis_gcc.h **** } 308:Drivers/CMSIS/Include/cmsis_gcc.h **** 309:Drivers/CMSIS/Include/cmsis_gcc.h **** 310:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) 311:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 312:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Main Stack Pointer (non-secure) 313:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure stat 314:Drivers/CMSIS/Include/cmsis_gcc.h **** \return MSP Register value 315:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 316:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) 317:Drivers/CMSIS/Include/cmsis_gcc.h **** { 318:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 319:Drivers/CMSIS/Include/cmsis_gcc.h **** 320:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); 321:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 322:Drivers/CMSIS/Include/cmsis_gcc.h **** } 323:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 324:Drivers/CMSIS/Include/cmsis_gcc.h **** 325:Drivers/CMSIS/Include/cmsis_gcc.h **** 326:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 327:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Main Stack Pointer ARM GAS /tmp/ccdsDELB.s page 412 328:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Main Stack Pointer (MSP). 329:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfMainStack Main Stack Pointer value to set 330:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 331:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) 332:Drivers/CMSIS/Include/cmsis_gcc.h **** { 333:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); 334:Drivers/CMSIS/Include/cmsis_gcc.h **** } 335:Drivers/CMSIS/Include/cmsis_gcc.h **** 336:Drivers/CMSIS/Include/cmsis_gcc.h **** 337:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) 338:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 339:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Main Stack Pointer (non-secure) 340:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. 341:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfMainStack Main Stack Pointer value to set 342:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 343:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) 344:Drivers/CMSIS/Include/cmsis_gcc.h **** { 345:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); 346:Drivers/CMSIS/Include/cmsis_gcc.h **** } 347:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 348:Drivers/CMSIS/Include/cmsis_gcc.h **** 349:Drivers/CMSIS/Include/cmsis_gcc.h **** 350:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) 351:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 352:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Stack Pointer (non-secure) 353:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. 354:Drivers/CMSIS/Include/cmsis_gcc.h **** \return SP Register value 355:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 356:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) 357:Drivers/CMSIS/Include/cmsis_gcc.h **** { 358:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 359:Drivers/CMSIS/Include/cmsis_gcc.h **** 360:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); 361:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 362:Drivers/CMSIS/Include/cmsis_gcc.h **** } 363:Drivers/CMSIS/Include/cmsis_gcc.h **** 364:Drivers/CMSIS/Include/cmsis_gcc.h **** 365:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 366:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Stack Pointer (non-secure) 367:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. 368:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfStack Stack Pointer value to set 369:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 370:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) 371:Drivers/CMSIS/Include/cmsis_gcc.h **** { 372:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); 373:Drivers/CMSIS/Include/cmsis_gcc.h **** } 374:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 375:Drivers/CMSIS/Include/cmsis_gcc.h **** 376:Drivers/CMSIS/Include/cmsis_gcc.h **** 377:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 378:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Priority Mask 379:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current state of the priority mask bit from the Priority Mask Register. 380:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Priority Mask value 381:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 382:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) 383:Drivers/CMSIS/Include/cmsis_gcc.h **** { 384:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; ARM GAS /tmp/ccdsDELB.s page 413 385:Drivers/CMSIS/Include/cmsis_gcc.h **** 386:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); 387:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 388:Drivers/CMSIS/Include/cmsis_gcc.h **** } 389:Drivers/CMSIS/Include/cmsis_gcc.h **** 390:Drivers/CMSIS/Include/cmsis_gcc.h **** 391:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) 392:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 393:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Priority Mask (non-secure) 394:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current state of the non-secure priority mask bit from the Priority Mask Reg 395:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Priority Mask value 396:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 397:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) 398:Drivers/CMSIS/Include/cmsis_gcc.h **** { 399:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 400:Drivers/CMSIS/Include/cmsis_gcc.h **** 401:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, primask_ns" : "=r" (result) :: "memory"); 402:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 403:Drivers/CMSIS/Include/cmsis_gcc.h **** } 404:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 405:Drivers/CMSIS/Include/cmsis_gcc.h **** 406:Drivers/CMSIS/Include/cmsis_gcc.h **** 407:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 408:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Priority Mask 409:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Priority Mask Register. 410:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] priMask Priority Mask 411:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 412:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) 413:Drivers/CMSIS/Include/cmsis_gcc.h **** { 414:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); 415:Drivers/CMSIS/Include/cmsis_gcc.h **** } 416:Drivers/CMSIS/Include/cmsis_gcc.h **** 417:Drivers/CMSIS/Include/cmsis_gcc.h **** 418:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) 419:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 420:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Priority Mask (non-secure) 421:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Priority Mask Register when in secure state. 422:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] priMask Priority Mask 423:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 424:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) 425:Drivers/CMSIS/Include/cmsis_gcc.h **** { 426:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); 427:Drivers/CMSIS/Include/cmsis_gcc.h **** } 428:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 429:Drivers/CMSIS/Include/cmsis_gcc.h **** 430:Drivers/CMSIS/Include/cmsis_gcc.h **** 431:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ 432:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ 433:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) 434:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 435:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Enable FIQ 436:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Enables FIQ interrupts by clearing the F-bit in the CPSR. 437:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes. 438:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 439:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __enable_fault_irq(void) 440:Drivers/CMSIS/Include/cmsis_gcc.h **** { 441:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsie f" : : : "memory"); ARM GAS /tmp/ccdsDELB.s page 414 442:Drivers/CMSIS/Include/cmsis_gcc.h **** } 443:Drivers/CMSIS/Include/cmsis_gcc.h **** 444:Drivers/CMSIS/Include/cmsis_gcc.h **** 445:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 446:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Disable FIQ 447:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Disables FIQ interrupts by setting the F-bit in the CPSR. 448:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes. 449:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 450:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __disable_fault_irq(void) 451:Drivers/CMSIS/Include/cmsis_gcc.h **** { 452:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsid f" : : : "memory"); 453:Drivers/CMSIS/Include/cmsis_gcc.h **** } 454:Drivers/CMSIS/Include/cmsis_gcc.h **** 455:Drivers/CMSIS/Include/cmsis_gcc.h **** 456:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 457:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Base Priority 458:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Base Priority register. 459:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Base Priority register value 460:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 461:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) 462:Drivers/CMSIS/Include/cmsis_gcc.h **** { 463:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 464:Drivers/CMSIS/Include/cmsis_gcc.h **** 465:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, basepri" : "=r" (result) ); 466:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 467:Drivers/CMSIS/Include/cmsis_gcc.h **** } 468:Drivers/CMSIS/Include/cmsis_gcc.h **** 469:Drivers/CMSIS/Include/cmsis_gcc.h **** 470:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) 471:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 472:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Base Priority (non-secure) 473:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Base Priority register when in secure state. 474:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Base Priority register value 475:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 476:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) 477:Drivers/CMSIS/Include/cmsis_gcc.h **** { 478:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 479:Drivers/CMSIS/Include/cmsis_gcc.h **** 480:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); 481:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 482:Drivers/CMSIS/Include/cmsis_gcc.h **** } 483:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 484:Drivers/CMSIS/Include/cmsis_gcc.h **** 485:Drivers/CMSIS/Include/cmsis_gcc.h **** 486:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 487:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Base Priority 488:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Base Priority register. 489:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] basePri Base Priority value to set 490:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 491:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) 492:Drivers/CMSIS/Include/cmsis_gcc.h **** { 493:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); 494:Drivers/CMSIS/Include/cmsis_gcc.h **** } 495:Drivers/CMSIS/Include/cmsis_gcc.h **** 496:Drivers/CMSIS/Include/cmsis_gcc.h **** 497:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) 498:Drivers/CMSIS/Include/cmsis_gcc.h **** /** ARM GAS /tmp/ccdsDELB.s page 415 499:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Base Priority (non-secure) 500:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Base Priority register when in secure state. 501:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] basePri Base Priority value to set 502:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 503:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) 504:Drivers/CMSIS/Include/cmsis_gcc.h **** { 505:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); 506:Drivers/CMSIS/Include/cmsis_gcc.h **** } 507:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 508:Drivers/CMSIS/Include/cmsis_gcc.h **** 509:Drivers/CMSIS/Include/cmsis_gcc.h **** 510:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 511:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Base Priority with condition 512:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Base Priority register only if BASEPRI masking is disable 513:Drivers/CMSIS/Include/cmsis_gcc.h **** or the new value increases the BASEPRI priority level. 514:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] basePri Base Priority value to set 515:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 516:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) 517:Drivers/CMSIS/Include/cmsis_gcc.h **** { 518:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); 519:Drivers/CMSIS/Include/cmsis_gcc.h **** } 520:Drivers/CMSIS/Include/cmsis_gcc.h **** 521:Drivers/CMSIS/Include/cmsis_gcc.h **** 522:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 523:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Fault Mask 524:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Fault Mask register. 525:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Fault Mask register value 526:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 527:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) 528:Drivers/CMSIS/Include/cmsis_gcc.h **** { 529:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 530:Drivers/CMSIS/Include/cmsis_gcc.h **** 531:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); 532:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 533:Drivers/CMSIS/Include/cmsis_gcc.h **** } 534:Drivers/CMSIS/Include/cmsis_gcc.h **** 535:Drivers/CMSIS/Include/cmsis_gcc.h **** 536:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) 537:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 538:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Fault Mask (non-secure) 539:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Fault Mask register when in secure state. 540:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Fault Mask register value 541:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 542:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) 543:Drivers/CMSIS/Include/cmsis_gcc.h **** { 544:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 545:Drivers/CMSIS/Include/cmsis_gcc.h **** 546:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); 547:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 548:Drivers/CMSIS/Include/cmsis_gcc.h **** } 549:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 550:Drivers/CMSIS/Include/cmsis_gcc.h **** 551:Drivers/CMSIS/Include/cmsis_gcc.h **** 552:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 553:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Fault Mask 554:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Fault Mask register. 555:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] faultMask Fault Mask value to set ARM GAS /tmp/ccdsDELB.s page 416 556:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 557:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) 558:Drivers/CMSIS/Include/cmsis_gcc.h **** { 559:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); 560:Drivers/CMSIS/Include/cmsis_gcc.h **** } 561:Drivers/CMSIS/Include/cmsis_gcc.h **** 562:Drivers/CMSIS/Include/cmsis_gcc.h **** 563:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) 564:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 565:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Fault Mask (non-secure) 566:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Fault Mask register when in secure state. 567:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] faultMask Fault Mask value to set 568:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 569:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) 570:Drivers/CMSIS/Include/cmsis_gcc.h **** { 571:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); 572:Drivers/CMSIS/Include/cmsis_gcc.h **** } 573:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 574:Drivers/CMSIS/Include/cmsis_gcc.h **** 575:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ 576:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ 577:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ 578:Drivers/CMSIS/Include/cmsis_gcc.h **** 579:Drivers/CMSIS/Include/cmsis_gcc.h **** 580:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ 581:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) 582:Drivers/CMSIS/Include/cmsis_gcc.h **** 583:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 584:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Process Stack Pointer Limit 585:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure 586:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence zero is returned always in non-secure 587:Drivers/CMSIS/Include/cmsis_gcc.h **** mode. 588:Drivers/CMSIS/Include/cmsis_gcc.h **** 589:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). 590:Drivers/CMSIS/Include/cmsis_gcc.h **** \return PSPLIM Register value 591:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 592:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) 593:Drivers/CMSIS/Include/cmsis_gcc.h **** { 594:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ 595:Drivers/CMSIS/Include/cmsis_gcc.h **** (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) 596:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure PSPLIM is RAZ/WI 597:Drivers/CMSIS/Include/cmsis_gcc.h **** return 0U; 598:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 599:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 600:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, psplim" : "=r" (result) ); 601:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; 602:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 603:Drivers/CMSIS/Include/cmsis_gcc.h **** } 604:Drivers/CMSIS/Include/cmsis_gcc.h **** 605:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) 606:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 607:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Process Stack Pointer Limit (non-secure) 608:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure 609:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence zero is returned always. 610:Drivers/CMSIS/Include/cmsis_gcc.h **** 611:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in 612:Drivers/CMSIS/Include/cmsis_gcc.h **** \return PSPLIM Register value ARM GAS /tmp/ccdsDELB.s page 417 613:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 614:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) 615:Drivers/CMSIS/Include/cmsis_gcc.h **** { 616:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) 617:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure PSPLIM is RAZ/WI 618:Drivers/CMSIS/Include/cmsis_gcc.h **** return 0U; 619:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 620:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 621:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); 622:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; 623:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 624:Drivers/CMSIS/Include/cmsis_gcc.h **** } 625:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 626:Drivers/CMSIS/Include/cmsis_gcc.h **** 627:Drivers/CMSIS/Include/cmsis_gcc.h **** 628:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 629:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Process Stack Pointer Limit 630:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure 631:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence the write is silently ignored in non-secure 632:Drivers/CMSIS/Include/cmsis_gcc.h **** mode. 633:Drivers/CMSIS/Include/cmsis_gcc.h **** 634:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). 635:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set 636:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 637:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) 638:Drivers/CMSIS/Include/cmsis_gcc.h **** { 639:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ 640:Drivers/CMSIS/Include/cmsis_gcc.h **** (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) 641:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure PSPLIM is RAZ/WI 642:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)ProcStackPtrLimit; 643:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 644:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); 645:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 646:Drivers/CMSIS/Include/cmsis_gcc.h **** } 647:Drivers/CMSIS/Include/cmsis_gcc.h **** 648:Drivers/CMSIS/Include/cmsis_gcc.h **** 649:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) 650:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 651:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Process Stack Pointer (non-secure) 652:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure 653:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence the write is silently ignored. 654:Drivers/CMSIS/Include/cmsis_gcc.h **** 655:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in s 656:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set 657:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 658:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) 659:Drivers/CMSIS/Include/cmsis_gcc.h **** { 660:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) 661:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure PSPLIM is RAZ/WI 662:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)ProcStackPtrLimit; 663:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 664:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); 665:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 666:Drivers/CMSIS/Include/cmsis_gcc.h **** } 667:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 668:Drivers/CMSIS/Include/cmsis_gcc.h **** 669:Drivers/CMSIS/Include/cmsis_gcc.h **** ARM GAS /tmp/ccdsDELB.s page 418 670:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 671:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Main Stack Pointer Limit 672:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure 673:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence zero is returned always in non-secure 674:Drivers/CMSIS/Include/cmsis_gcc.h **** mode. 675:Drivers/CMSIS/Include/cmsis_gcc.h **** 676:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). 677:Drivers/CMSIS/Include/cmsis_gcc.h **** \return MSPLIM Register value 678:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 679:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) 680:Drivers/CMSIS/Include/cmsis_gcc.h **** { 681:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ 682:Drivers/CMSIS/Include/cmsis_gcc.h **** (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) 683:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure MSPLIM is RAZ/WI 684:Drivers/CMSIS/Include/cmsis_gcc.h **** return 0U; 685:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 686:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 687:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, msplim" : "=r" (result) ); 688:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; 689:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 690:Drivers/CMSIS/Include/cmsis_gcc.h **** } 691:Drivers/CMSIS/Include/cmsis_gcc.h **** 692:Drivers/CMSIS/Include/cmsis_gcc.h **** 693:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) 694:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 695:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Main Stack Pointer Limit (non-secure) 696:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure 697:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence zero is returned always. 698:Drivers/CMSIS/Include/cmsis_gcc.h **** 699:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in sec 700:Drivers/CMSIS/Include/cmsis_gcc.h **** \return MSPLIM Register value 701:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 702:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) 703:Drivers/CMSIS/Include/cmsis_gcc.h **** { 704:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) 705:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure MSPLIM is RAZ/WI 706:Drivers/CMSIS/Include/cmsis_gcc.h **** return 0U; 707:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 708:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 709:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); 710:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; 711:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 712:Drivers/CMSIS/Include/cmsis_gcc.h **** } 713:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 714:Drivers/CMSIS/Include/cmsis_gcc.h **** 715:Drivers/CMSIS/Include/cmsis_gcc.h **** 716:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 717:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Main Stack Pointer Limit 718:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure 719:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence the write is silently ignored in non-secure 720:Drivers/CMSIS/Include/cmsis_gcc.h **** mode. 721:Drivers/CMSIS/Include/cmsis_gcc.h **** 722:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). 723:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set 724:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 725:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) 726:Drivers/CMSIS/Include/cmsis_gcc.h **** { ARM GAS /tmp/ccdsDELB.s page 419 727:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ 728:Drivers/CMSIS/Include/cmsis_gcc.h **** (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) 729:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure MSPLIM is RAZ/WI 730:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)MainStackPtrLimit; 731:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 732:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); 733:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 734:Drivers/CMSIS/Include/cmsis_gcc.h **** } 735:Drivers/CMSIS/Include/cmsis_gcc.h **** 736:Drivers/CMSIS/Include/cmsis_gcc.h **** 737:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) 738:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 739:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Main Stack Pointer Limit (non-secure) 740:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure 741:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence the write is silently ignored. 742:Drivers/CMSIS/Include/cmsis_gcc.h **** 743:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secu 744:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] MainStackPtrLimit Main Stack Pointer value to set 745:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 746:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) 747:Drivers/CMSIS/Include/cmsis_gcc.h **** { 748:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) 749:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure MSPLIM is RAZ/WI 750:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)MainStackPtrLimit; 751:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 752:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); 753:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 754:Drivers/CMSIS/Include/cmsis_gcc.h **** } 755:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 756:Drivers/CMSIS/Include/cmsis_gcc.h **** 757:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ 758:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ 759:Drivers/CMSIS/Include/cmsis_gcc.h **** 760:Drivers/CMSIS/Include/cmsis_gcc.h **** 761:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 762:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get FPSCR 763:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Floating Point Status/Control register. 764:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Floating Point Status/Control register value 765:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 766:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_FPSCR(void) 767:Drivers/CMSIS/Include/cmsis_gcc.h **** { 768:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ 769:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) 770:Drivers/CMSIS/Include/cmsis_gcc.h **** #if __has_builtin(__builtin_arm_get_fpscr) 771:Drivers/CMSIS/Include/cmsis_gcc.h **** // Re-enable using built-in when GCC has been fixed 772:Drivers/CMSIS/Include/cmsis_gcc.h **** // || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) 773:Drivers/CMSIS/Include/cmsis_gcc.h **** /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ 774:Drivers/CMSIS/Include/cmsis_gcc.h **** return __builtin_arm_get_fpscr(); 775:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 776:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 777:Drivers/CMSIS/Include/cmsis_gcc.h **** 778:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); 779:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 780:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 781:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 782:Drivers/CMSIS/Include/cmsis_gcc.h **** return(0U); 783:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif ARM GAS /tmp/ccdsDELB.s page 420 784:Drivers/CMSIS/Include/cmsis_gcc.h **** } 785:Drivers/CMSIS/Include/cmsis_gcc.h **** 786:Drivers/CMSIS/Include/cmsis_gcc.h **** 787:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 788:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set FPSCR 789:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Floating Point Status/Control register. 790:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] fpscr Floating Point Status/Control value to set 791:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 792:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) 793:Drivers/CMSIS/Include/cmsis_gcc.h **** { 794:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ 795:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) 796:Drivers/CMSIS/Include/cmsis_gcc.h **** #if __has_builtin(__builtin_arm_set_fpscr) 797:Drivers/CMSIS/Include/cmsis_gcc.h **** // Re-enable using built-in when GCC has been fixed 798:Drivers/CMSIS/Include/cmsis_gcc.h **** // || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) 799:Drivers/CMSIS/Include/cmsis_gcc.h **** /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ 800:Drivers/CMSIS/Include/cmsis_gcc.h **** __builtin_arm_set_fpscr(fpscr); 801:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 802:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory"); 803:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 804:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 805:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)fpscr; 806:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 807:Drivers/CMSIS/Include/cmsis_gcc.h **** } 808:Drivers/CMSIS/Include/cmsis_gcc.h **** 809:Drivers/CMSIS/Include/cmsis_gcc.h **** 810:Drivers/CMSIS/Include/cmsis_gcc.h **** /*@} end of CMSIS_Core_RegAccFunctions */ 811:Drivers/CMSIS/Include/cmsis_gcc.h **** 812:Drivers/CMSIS/Include/cmsis_gcc.h **** 813:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ########################## Core Instruction Access ######################### */ 814:Drivers/CMSIS/Include/cmsis_gcc.h **** /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface 815:Drivers/CMSIS/Include/cmsis_gcc.h **** Access to dedicated instructions 816:Drivers/CMSIS/Include/cmsis_gcc.h **** @{ 817:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 818:Drivers/CMSIS/Include/cmsis_gcc.h **** 819:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Define macros for porting to both thumb1 and thumb2. 820:Drivers/CMSIS/Include/cmsis_gcc.h **** * For thumb1, use low register (r0-r7), specified by constraint "l" 821:Drivers/CMSIS/Include/cmsis_gcc.h **** * Otherwise, use general registers, specified by constraint "r" */ 822:Drivers/CMSIS/Include/cmsis_gcc.h **** #if defined (__thumb__) && !defined (__thumb2__) 823:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_OUT_REG(r) "=l" (r) 824:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_RW_REG(r) "+l" (r) 825:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_USE_REG(r) "l" (r) 826:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 827:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_OUT_REG(r) "=r" (r) 828:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_RW_REG(r) "+r" (r) 829:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_USE_REG(r) "r" (r) 830:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 831:Drivers/CMSIS/Include/cmsis_gcc.h **** 832:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 833:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief No Operation 834:Drivers/CMSIS/Include/cmsis_gcc.h **** \details No Operation does nothing. This instruction can be used for code alignment purposes. 835:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 836:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __NOP() __ASM volatile ("nop") 837:Drivers/CMSIS/Include/cmsis_gcc.h **** 838:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 839:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Wait For Interrupt 840:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Wait For Interrupt is a hint instruction that suspends execution until one of a number o ARM GAS /tmp/ccdsDELB.s page 421 841:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 842:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __WFI() __ASM volatile ("wfi") 843:Drivers/CMSIS/Include/cmsis_gcc.h **** 844:Drivers/CMSIS/Include/cmsis_gcc.h **** 845:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 846:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Wait For Event 847:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Wait For Event is a hint instruction that permits the processor to enter 848:Drivers/CMSIS/Include/cmsis_gcc.h **** a low-power state until one of a number of events occurs. 849:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 850:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __WFE() __ASM volatile ("wfe") 851:Drivers/CMSIS/Include/cmsis_gcc.h **** 852:Drivers/CMSIS/Include/cmsis_gcc.h **** 853:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 854:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Send Event 855:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. 856:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 857:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __SEV() __ASM volatile ("sev") 858:Drivers/CMSIS/Include/cmsis_gcc.h **** 859:Drivers/CMSIS/Include/cmsis_gcc.h **** 860:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 861:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Instruction Synchronization Barrier 862:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Instruction Synchronization Barrier flushes the pipeline in the processor, 863:Drivers/CMSIS/Include/cmsis_gcc.h **** so that all instructions following the ISB are fetched from cache or memory, 864:Drivers/CMSIS/Include/cmsis_gcc.h **** after the instruction has been completed. 865:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 866:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __ISB(void) 867:Drivers/CMSIS/Include/cmsis_gcc.h **** { 868:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("isb 0xF":::"memory"); 869:Drivers/CMSIS/Include/cmsis_gcc.h **** } 870:Drivers/CMSIS/Include/cmsis_gcc.h **** 871:Drivers/CMSIS/Include/cmsis_gcc.h **** 872:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 873:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Data Synchronization Barrier 874:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Acts as a special kind of Data Memory Barrier. 875:Drivers/CMSIS/Include/cmsis_gcc.h **** It completes when all explicit memory accesses before this instruction complete. 876:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 877:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __DSB(void) 878:Drivers/CMSIS/Include/cmsis_gcc.h **** { 879:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("dsb 0xF":::"memory"); 880:Drivers/CMSIS/Include/cmsis_gcc.h **** } 881:Drivers/CMSIS/Include/cmsis_gcc.h **** 882:Drivers/CMSIS/Include/cmsis_gcc.h **** 883:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 884:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Data Memory Barrier 885:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Ensures the apparent order of the explicit memory operations before 886:Drivers/CMSIS/Include/cmsis_gcc.h **** and after the instruction, without ensuring their completion. 887:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 888:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __DMB(void) 889:Drivers/CMSIS/Include/cmsis_gcc.h **** { 890:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("dmb 0xF":::"memory"); 891:Drivers/CMSIS/Include/cmsis_gcc.h **** } 892:Drivers/CMSIS/Include/cmsis_gcc.h **** 893:Drivers/CMSIS/Include/cmsis_gcc.h **** 894:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 895:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Reverse byte order (32 bit) 896:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x785 897:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to reverse ARM GAS /tmp/ccdsDELB.s page 422 898:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Reversed value 899:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 900:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __REV(uint32_t value) 901:Drivers/CMSIS/Include/cmsis_gcc.h **** { 902:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) 903:Drivers/CMSIS/Include/cmsis_gcc.h **** return __builtin_bswap32(value); 904:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 905:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 906:Drivers/CMSIS/Include/cmsis_gcc.h **** 907:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); 908:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; 909:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 910:Drivers/CMSIS/Include/cmsis_gcc.h **** } 911:Drivers/CMSIS/Include/cmsis_gcc.h **** 912:Drivers/CMSIS/Include/cmsis_gcc.h **** 913:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 914:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Reverse byte order (16 bit) 915:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 916:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to reverse 917:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Reversed value 918:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 919:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __REV16(uint32_t value) 920:Drivers/CMSIS/Include/cmsis_gcc.h **** { 921:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 922:Drivers/CMSIS/Include/cmsis_gcc.h **** 923:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); 924:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; 925:Drivers/CMSIS/Include/cmsis_gcc.h **** } 926:Drivers/CMSIS/Include/cmsis_gcc.h **** 927:Drivers/CMSIS/Include/cmsis_gcc.h **** 928:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 929:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Reverse byte order (16 bit) 930:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For exam 931:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to reverse 932:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Reversed value 933:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 934:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE int16_t __REVSH(int16_t value) 935:Drivers/CMSIS/Include/cmsis_gcc.h **** { 936:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) 937:Drivers/CMSIS/Include/cmsis_gcc.h **** return (int16_t)__builtin_bswap16(value); 938:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 939:Drivers/CMSIS/Include/cmsis_gcc.h **** int16_t result; 940:Drivers/CMSIS/Include/cmsis_gcc.h **** 941:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); 942:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; 943:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 944:Drivers/CMSIS/Include/cmsis_gcc.h **** } 945:Drivers/CMSIS/Include/cmsis_gcc.h **** 946:Drivers/CMSIS/Include/cmsis_gcc.h **** 947:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 948:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Rotate Right in unsigned value (32 bit) 949:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Rotate Right (immediate) provides the value of the contents of a register rotated by a v 950:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] op1 Value to rotate 951:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] op2 Number of Bits to rotate 952:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Rotated value 953:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 954:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) ARM GAS /tmp/ccdsDELB.s page 423 955:Drivers/CMSIS/Include/cmsis_gcc.h **** { 956:Drivers/CMSIS/Include/cmsis_gcc.h **** op2 %= 32U; 957:Drivers/CMSIS/Include/cmsis_gcc.h **** if (op2 == 0U) 958:Drivers/CMSIS/Include/cmsis_gcc.h **** { 959:Drivers/CMSIS/Include/cmsis_gcc.h **** return op1; 960:Drivers/CMSIS/Include/cmsis_gcc.h **** } 961:Drivers/CMSIS/Include/cmsis_gcc.h **** return (op1 >> op2) | (op1 << (32U - op2)); 962:Drivers/CMSIS/Include/cmsis_gcc.h **** } 963:Drivers/CMSIS/Include/cmsis_gcc.h **** 964:Drivers/CMSIS/Include/cmsis_gcc.h **** 965:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 966:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Breakpoint 967:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Causes the processor to enter Debug state. 968:Drivers/CMSIS/Include/cmsis_gcc.h **** Debug tools can use this to investigate system state when the instruction at a particula 969:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value is ignored by the processor. 970:Drivers/CMSIS/Include/cmsis_gcc.h **** If required, a debugger can use it to store additional information about the break 971:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 972:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __BKPT(value) __ASM volatile ("bkpt "#value) 973:Drivers/CMSIS/Include/cmsis_gcc.h **** 974:Drivers/CMSIS/Include/cmsis_gcc.h **** 975:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 976:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Reverse bit order of value 977:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Reverses the bit order of the given value. 978:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to reverse 979:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Reversed value 980:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 981:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value) 982:Drivers/CMSIS/Include/cmsis_gcc.h **** { 983:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 984:Drivers/CMSIS/Include/cmsis_gcc.h **** 985:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ 986:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ 987:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) 988:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 989:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 990:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ 991:Drivers/CMSIS/Include/cmsis_gcc.h **** 992:Drivers/CMSIS/Include/cmsis_gcc.h **** result = value; /* r will be reversed bits of v; first get LSB of v */ 993:Drivers/CMSIS/Include/cmsis_gcc.h **** for (value >>= 1U; value != 0U; value >>= 1U) 994:Drivers/CMSIS/Include/cmsis_gcc.h **** { 995:Drivers/CMSIS/Include/cmsis_gcc.h **** result <<= 1U; 996:Drivers/CMSIS/Include/cmsis_gcc.h **** result |= value & 1U; 997:Drivers/CMSIS/Include/cmsis_gcc.h **** s--; 998:Drivers/CMSIS/Include/cmsis_gcc.h **** } 999:Drivers/CMSIS/Include/cmsis_gcc.h **** result <<= s; /* shift when v's highest bits are zero */ 1000:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 1001:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; 1002:Drivers/CMSIS/Include/cmsis_gcc.h **** } 1003:Drivers/CMSIS/Include/cmsis_gcc.h **** 1004:Drivers/CMSIS/Include/cmsis_gcc.h **** 1005:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 1006:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Count leading zeros 1007:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Counts the number of leading zeros of a data value. 1008:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to count the leading zeros 1009:Drivers/CMSIS/Include/cmsis_gcc.h **** \return number of leading zeros in value 1010:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 1011:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CLZ (uint8_t)__builtin_clz ARM GAS /tmp/ccdsDELB.s page 424 1012:Drivers/CMSIS/Include/cmsis_gcc.h **** 1013:Drivers/CMSIS/Include/cmsis_gcc.h **** 1014:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ 1015:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ 1016:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ 1017:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) 1018:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 1019:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief LDR Exclusive (8 bit) 1020:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Executes a exclusive LDR instruction for 8 bit value. 1021:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ptr Pointer to data 1022:Drivers/CMSIS/Include/cmsis_gcc.h **** \return value of type uint8_t at (*ptr) 1023:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 1024:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr) 1025:Drivers/CMSIS/Include/cmsis_gcc.h **** { 1026:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 1027:Drivers/CMSIS/Include/cmsis_gcc.h **** 1028:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) 1029:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); 1030:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 1031:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not 1032:Drivers/CMSIS/Include/cmsis_gcc.h **** accepted by assembler. So has to use following less efficient pattern. 1033:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 1034:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); 1035:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 1036:Drivers/CMSIS/Include/cmsis_gcc.h **** return ((uint8_t) result); /* Add explicit type cast here */ 1037:Drivers/CMSIS/Include/cmsis_gcc.h **** } 1038:Drivers/CMSIS/Include/cmsis_gcc.h **** 1039:Drivers/CMSIS/Include/cmsis_gcc.h **** 1040:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 1041:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief LDR Exclusive (16 bit) 1042:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Executes a exclusive LDR instruction for 16 bit values. 1043:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ptr Pointer to data 1044:Drivers/CMSIS/Include/cmsis_gcc.h **** \return value of type uint16_t at (*ptr) 1045:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 1046:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr) 1047:Drivers/CMSIS/Include/cmsis_gcc.h **** { 1048:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 1049:Drivers/CMSIS/Include/cmsis_gcc.h **** 1050:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) 1051:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); 1052:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 1053:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not 1054:Drivers/CMSIS/Include/cmsis_gcc.h **** accepted by assembler. So has to use following less efficient pattern. 1055:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 1056:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); 1057:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 1058:Drivers/CMSIS/Include/cmsis_gcc.h **** return ((uint16_t) result); /* Add explicit type cast here */ 1059:Drivers/CMSIS/Include/cmsis_gcc.h **** } 1060:Drivers/CMSIS/Include/cmsis_gcc.h **** 1061:Drivers/CMSIS/Include/cmsis_gcc.h **** 1062:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 1063:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief LDR Exclusive (32 bit) 1064:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Executes a exclusive LDR instruction for 32 bit values. 1065:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ptr Pointer to data 1066:Drivers/CMSIS/Include/cmsis_gcc.h **** \return value of type uint32_t at (*ptr) 1067:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 1068:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr) ARM GAS /tmp/ccdsDELB.s page 425 4723 .loc 8 1068 31 view .LVU1616 4724 .LBB474: 1069:Drivers/CMSIS/Include/cmsis_gcc.h **** { 1070:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 4725 .loc 8 1070 5 view .LVU1617 1071:Drivers/CMSIS/Include/cmsis_gcc.h **** 1072:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 4726 .loc 8 1072 4 view .LVU1618 4727 .syntax unified 4728 @ 1072 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 4729 00ea 52E8003F ldrex r3, [r2] 4730 @ 0 "" 2 4731 .LVL341: 1073:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 4732 .loc 8 1073 4 view .LVU1619 4733 .loc 8 1073 4 is_stmt 0 view .LVU1620 4734 .thumb 4735 .syntax unified 4736 .LBE474: 4737 .LBE473: 4738 .loc 7 3558 3 view .LVU1621 4739 00ee 43F08003 orr r3, r3, #128 4740 .LVL342: 4741 .loc 7 3558 3 is_stmt 1 view .LVU1622 4742 .LBB475: 4743 .LBI475: 1074:Drivers/CMSIS/Include/cmsis_gcc.h **** } 1075:Drivers/CMSIS/Include/cmsis_gcc.h **** 1076:Drivers/CMSIS/Include/cmsis_gcc.h **** 1077:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 1078:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief STR Exclusive (8 bit) 1079:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Executes a exclusive STR instruction for 8 bit values. 1080:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to store 1081:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ptr Pointer to location 1082:Drivers/CMSIS/Include/cmsis_gcc.h **** \return 0 Function succeeded 1083:Drivers/CMSIS/Include/cmsis_gcc.h **** \return 1 Function failed 1084:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 1085:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) 1086:Drivers/CMSIS/Include/cmsis_gcc.h **** { 1087:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 1088:Drivers/CMSIS/Include/cmsis_gcc.h **** 1089:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); 1090:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 1091:Drivers/CMSIS/Include/cmsis_gcc.h **** } 1092:Drivers/CMSIS/Include/cmsis_gcc.h **** 1093:Drivers/CMSIS/Include/cmsis_gcc.h **** 1094:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 1095:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief STR Exclusive (16 bit) 1096:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Executes a exclusive STR instruction for 16 bit values. 1097:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to store 1098:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ptr Pointer to location 1099:Drivers/CMSIS/Include/cmsis_gcc.h **** \return 0 Function succeeded 1100:Drivers/CMSIS/Include/cmsis_gcc.h **** \return 1 Function failed 1101:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 1102:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) 1103:Drivers/CMSIS/Include/cmsis_gcc.h **** { 1104:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; ARM GAS /tmp/ccdsDELB.s page 426 1105:Drivers/CMSIS/Include/cmsis_gcc.h **** 1106:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); 1107:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 1108:Drivers/CMSIS/Include/cmsis_gcc.h **** } 1109:Drivers/CMSIS/Include/cmsis_gcc.h **** 1110:Drivers/CMSIS/Include/cmsis_gcc.h **** 1111:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 1112:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief STR Exclusive (32 bit) 1113:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Executes a exclusive STR instruction for 32 bit values. 1114:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to store 1115:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ptr Pointer to location 1116:Drivers/CMSIS/Include/cmsis_gcc.h **** \return 0 Function succeeded 1117:Drivers/CMSIS/Include/cmsis_gcc.h **** \return 1 Function failed 1118:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 1119:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) 4744 .loc 8 1119 31 view .LVU1623 4745 .LBB476: 1120:Drivers/CMSIS/Include/cmsis_gcc.h **** { 1121:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 4746 .loc 8 1121 4 view .LVU1624 1122:Drivers/CMSIS/Include/cmsis_gcc.h **** 1123:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 4747 .loc 8 1123 4 view .LVU1625 4748 .syntax unified 4749 @ 1123 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 4750 00f2 42E80031 strex r1, r3, [r2] 4751 @ 0 "" 2 4752 .LVL343: 1124:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 4753 .loc 8 1124 4 view .LVU1626 4754 .loc 8 1124 4 is_stmt 0 view .LVU1627 4755 .thumb 4756 .syntax unified 4757 .LBE476: 4758 .LBE475: 4759 .loc 7 3558 3 view .LVU1628 4760 00f6 0029 cmp r1, #0 4761 00f8 F6D1 bne .L173 4762 .LBE472: 4763 .LBE471: 4764 .loc 7 3558 3 is_stmt 1 view .LVU1629 4765 .LVL344: 1522:Src/main.c **** LL_DMA_EnableIT_TE(DMA2, LL_DMA_STREAM_7); 4766 .loc 2 1522 3 view .LVU1630 4767 .LBB477: 4768 .LBI477: 2368:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 2369:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 2370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 2371:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Clear Stream 0 direct mode error flag. 2372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LIFCR CDMEIF0 LL_DMA_ClearFlag_DME0 2373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 2374:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 2375:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 2376:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_DME0(DMA_TypeDef *DMAx) 2377:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 2378:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CDMEIF0); ARM GAS /tmp/ccdsDELB.s page 427 2379:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 2380:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 2381:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 2382:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Clear Stream 1 direct mode error flag. 2383:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LIFCR CDMEIF1 LL_DMA_ClearFlag_DME1 2384:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 2385:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 2386:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 2387:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_DME1(DMA_TypeDef *DMAx) 2388:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 2389:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CDMEIF1); 2390:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 2391:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 2392:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 2393:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Clear Stream 2 direct mode error flag. 2394:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LIFCR CDMEIF2 LL_DMA_ClearFlag_DME2 2395:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 2396:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 2397:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 2398:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_DME2(DMA_TypeDef *DMAx) 2399:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 2400:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CDMEIF2); 2401:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 2402:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 2403:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 2404:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Clear Stream 3 direct mode error flag. 2405:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LIFCR CDMEIF3 LL_DMA_ClearFlag_DME3 2406:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 2407:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 2408:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 2409:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_DME3(DMA_TypeDef *DMAx) 2410:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 2411:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CDMEIF3); 2412:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 2413:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 2414:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 2415:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Clear Stream 4 direct mode error flag. 2416:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HIFCR CDMEIF4 LL_DMA_ClearFlag_DME4 2417:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 2418:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 2419:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 2420:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_DME4(DMA_TypeDef *DMAx) 2421:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 2422:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CDMEIF4); 2423:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 2424:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 2425:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 2426:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Clear Stream 5 direct mode error flag. 2427:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HIFCR CDMEIF5 LL_DMA_ClearFlag_DME5 2428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 2429:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 2430:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 2431:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_DME5(DMA_TypeDef *DMAx) 2432:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 2433:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CDMEIF5); 2434:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 2435:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** ARM GAS /tmp/ccdsDELB.s page 428 2436:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 2437:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Clear Stream 6 direct mode error flag. 2438:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HIFCR CDMEIF6 LL_DMA_ClearFlag_DME6 2439:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 2440:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 2441:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 2442:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_DME6(DMA_TypeDef *DMAx) 2443:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 2444:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CDMEIF6); 2445:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 2446:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 2447:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 2448:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Clear Stream 7 direct mode error flag. 2449:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HIFCR CDMEIF7 LL_DMA_ClearFlag_DME7 2450:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 2451:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 2452:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 2453:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_DME7(DMA_TypeDef *DMAx) 2454:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 2455:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CDMEIF7); 2456:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 2457:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 2458:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 2459:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Clear Stream 0 FIFO error flag. 2460:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LIFCR CFEIF0 LL_DMA_ClearFlag_FE0 2461:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 2462:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 2463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 2464:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_FE0(DMA_TypeDef *DMAx) 2465:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 2466:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CFEIF0); 2467:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 2468:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 2469:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 2470:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Clear Stream 1 FIFO error flag. 2471:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LIFCR CFEIF1 LL_DMA_ClearFlag_FE1 2472:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 2473:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 2474:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 2475:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_FE1(DMA_TypeDef *DMAx) 2476:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 2477:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CFEIF1); 2478:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 2479:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 2480:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 2481:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Clear Stream 2 FIFO error flag. 2482:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LIFCR CFEIF2 LL_DMA_ClearFlag_FE2 2483:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 2484:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 2485:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 2486:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_FE2(DMA_TypeDef *DMAx) 2487:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 2488:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CFEIF2); 2489:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 2490:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 2491:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 2492:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Clear Stream 3 FIFO error flag. ARM GAS /tmp/ccdsDELB.s page 429 2493:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LIFCR CFEIF3 LL_DMA_ClearFlag_FE3 2494:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 2495:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 2496:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 2497:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_FE3(DMA_TypeDef *DMAx) 2498:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 2499:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CFEIF3); 2500:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 2501:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 2502:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 2503:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Clear Stream 4 FIFO error flag. 2504:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HIFCR CFEIF4 LL_DMA_ClearFlag_FE4 2505:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 2506:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 2507:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 2508:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_FE4(DMA_TypeDef *DMAx) 2509:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 2510:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CFEIF4); 2511:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 2512:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 2513:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 2514:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Clear Stream 5 FIFO error flag. 2515:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HIFCR CFEIF5 LL_DMA_ClearFlag_FE5 2516:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 2517:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 2518:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 2519:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_FE5(DMA_TypeDef *DMAx) 2520:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 2521:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CFEIF5); 2522:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 2523:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 2524:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 2525:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Clear Stream 6 FIFO error flag. 2526:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HIFCR CFEIF6 LL_DMA_ClearFlag_FE6 2527:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 2528:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 2529:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 2530:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_FE6(DMA_TypeDef *DMAx) 2531:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 2532:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CFEIF6); 2533:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 2534:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 2535:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 2536:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Clear Stream 7 FIFO error flag. 2537:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HIFCR CFEIF7 LL_DMA_ClearFlag_FE7 2538:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 2539:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 2540:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 2541:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_FE7(DMA_TypeDef *DMAx) 2542:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 2543:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CFEIF7); 2544:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 2545:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 2546:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 2547:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @} 2548:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 2549:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** ARM GAS /tmp/ccdsDELB.s page 430 2550:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_EF_IT_Management IT_Management 2551:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @{ 2552:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 2553:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 2554:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 2555:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Enable Half transfer interrupt. 2556:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR HTIE LL_DMA_EnableIT_HT 2557:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 2558:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: 2559:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 2560:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 2561:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 2562:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 2563:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 2564:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 2565:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 2566:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 2567:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 2568:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 2569:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_EnableIT_HT(DMA_TypeDef *DMAx, uint32_t Stream) 2570:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 2571:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA 2572:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 2573:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 2574:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 2575:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Enable Transfer error interrupt. 2576:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR TEIE LL_DMA_EnableIT_TE 2577:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 2578:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: 2579:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 2580:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 2581:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 2582:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 2583:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 2584:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 2585:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 2586:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 2587:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 2588:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 2589:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_EnableIT_TE(DMA_TypeDef *DMAx, uint32_t Stream) 2590:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 2591:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA 2592:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 2593:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 2594:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 2595:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Enable Transfer complete interrupt. 2596:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR TCIE LL_DMA_EnableIT_TC 2597:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 2598:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: 2599:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 2600:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 2601:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 2602:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 2603:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 2604:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 2605:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 2606:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 ARM GAS /tmp/ccdsDELB.s page 431 2607:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 2608:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 2609:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_EnableIT_TC(DMA_TypeDef *DMAx, uint32_t Stream) 4769 .loc 6 2609 22 view .LVU1631 4770 .LBB478: 2610:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 2611:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA 4771 .loc 6 2611 3 view .LVU1632 4772 00fa 734B ldr r3, .L182+80 4773 00fc D3F8B820 ldr r2, [r3, #184] 4774 0100 42F01002 orr r2, r2, #16 4775 0104 C3F8B820 str r2, [r3, #184] 4776 .LVL345: 4777 .loc 6 2611 3 is_stmt 0 view .LVU1633 4778 .LBE478: 4779 .LBE477: 1523:Src/main.c **** LL_DMA_ClearFlag_TC7(DMA2); 4780 .loc 2 1523 3 is_stmt 1 view .LVU1634 4781 .LBB479: 4782 .LBI479: 2589:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 4783 .loc 6 2589 22 view .LVU1635 4784 .LBB480: 2591:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 4785 .loc 6 2591 3 view .LVU1636 4786 0108 D3F8B820 ldr r2, [r3, #184] 4787 010c 42F00402 orr r2, r2, #4 4788 0110 C3F8B820 str r2, [r3, #184] 4789 .LVL346: 2591:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 4790 .loc 6 2591 3 is_stmt 0 view .LVU1637 4791 .LBE480: 4792 .LBE479: 1524:Src/main.c **** LL_DMA_ClearFlag_TE7(DMA2); 4793 .loc 2 1524 3 is_stmt 1 view .LVU1638 4794 .LBB481: 4795 .LBI481: 2277:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 4796 .loc 6 2277 22 view .LVU1639 4797 .LBB482: 2279:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 4798 .loc 6 2279 3 view .LVU1640 4799 0114 4FF00062 mov r2, #134217728 4800 0118 DA60 str r2, [r3, #12] 4801 .LVL347: 2279:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 4802 .loc 6 2279 3 is_stmt 0 view .LVU1641 4803 .LBE482: 4804 .LBE481: 1525:Src/main.c **** LL_DMA_ConfigAddresses(DMA2, LL_DMA_STREAM_7, (uint32_t)&UART_DATA, LL_USART_DMA_GetRegAddr(USART 4805 .loc 2 1525 3 is_stmt 1 view .LVU1642 4806 .LBB483: 4807 .LBI483: 2365:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 4808 .loc 6 2365 22 view .LVU1643 4809 .LBB484: 2367:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } ARM GAS /tmp/ccdsDELB.s page 432 4810 .loc 6 2367 3 view .LVU1644 4811 011a 4FF00072 mov r2, #33554432 4812 011e DA60 str r2, [r3, #12] 4813 .LVL348: 2367:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 4814 .loc 6 2367 3 is_stmt 0 view .LVU1645 4815 .LBE484: 4816 .LBE483: 1526:Src/main.c **** 4817 .loc 2 1526 3 is_stmt 1 view .LVU1646 4818 0120 6A49 ldr r1, .L182+84 4819 .LVL349: 4820 .LBB485: 4821 .LBI485: 3559:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 3560:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3561:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 3562:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Disable DMA Mode for transmission 3563:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 DMAT LL_USART_DisableDMAReq_TX 3564:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 3565:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 3566:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3567:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableDMAReq_TX(USART_TypeDef *USARTx) 3568:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 3569:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_DMAT); 3570:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 3571:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3572:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 3573:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if DMA Mode is enabled for transmission 3574:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 DMAT LL_USART_IsEnabledDMAReq_TX 3575:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 3576:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). 3577:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3578:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_TX(const USART_TypeDef *USARTx) 3579:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 3580:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->CR3, USART_CR3_DMAT) == (USART_CR3_DMAT)) ? 1UL : 0UL); 3581:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 3582:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3583:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 3584:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Enable DMA Disabling on Reception Error 3585:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 DDRE LL_USART_EnableDMADeactOnRxErr 3586:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 3587:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 3588:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3589:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableDMADeactOnRxErr(USART_TypeDef *USARTx) 3590:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 3591:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** SET_BIT(USARTx->CR3, USART_CR3_DDRE); 3592:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 3593:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3594:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 3595:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Disable DMA Disabling on Reception Error 3596:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 DDRE LL_USART_DisableDMADeactOnRxErr 3597:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 3598:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 3599:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3600:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableDMADeactOnRxErr(USART_TypeDef *USARTx) 3601:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { ARM GAS /tmp/ccdsDELB.s page 433 3602:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** CLEAR_BIT(USARTx->CR3, USART_CR3_DDRE); 3603:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 3604:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3605:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 3606:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Indicate if DMA Disabling on Reception Error is disabled 3607:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 DDRE LL_USART_IsEnabledDMADeactOnRxErr 3608:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 3609:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). 3610:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3611:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledDMADeactOnRxErr(const USART_TypeDef *USARTx) 3612:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 3613:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->CR3, USART_CR3_DDRE) == (USART_CR3_DDRE)) ? 1UL : 0UL); 3614:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 3615:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3616:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 3617:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Get the data register address used for DMA transfer 3618:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll RDR RDR LL_USART_DMA_GetRegAddr\n 3619:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll TDR TDR LL_USART_DMA_GetRegAddr 3620:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 3621:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param Direction This parameter can be one of the following values: 3622:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_DMA_REG_DATA_TRANSMIT 3623:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_DMA_REG_DATA_RECEIVE 3624:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Address of data register 3625:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3626:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_DMA_GetRegAddr(const USART_TypeDef *USARTx, uint32_t Direction) 4822 .loc 7 3626 26 view .LVU1647 4823 .LBB486: 3627:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 3628:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** uint32_t data_reg_addr; 4824 .loc 7 3628 3 view .LVU1648 3629:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3630:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** if (Direction == LL_USART_DMA_REG_DATA_TRANSMIT) 4825 .loc 7 3630 3 view .LVU1649 3631:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 3632:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* return address of TDR register */ 3633:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** data_reg_addr = (uint32_t) &(USARTx->TDR); 4826 .loc 7 3633 5 view .LVU1650 4827 .loc 7 3633 32 is_stmt 0 view .LVU1651 4828 0122 6B4A ldr r2, .L182+88 4829 .LVL350: 3634:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 3635:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** else 3636:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 3637:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* return address of RDR register */ 3638:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** data_reg_addr = (uint32_t) &(USARTx->RDR); 3639:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 3640:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3641:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return data_reg_addr; 4830 .loc 7 3641 3 is_stmt 1 view .LVU1652 4831 .loc 7 3641 3 is_stmt 0 view .LVU1653 4832 .LBE486: 4833 .LBE485: 4834 .LBB487: 4835 .LBI487: 621:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 4836 .loc 6 621 26 is_stmt 1 view .LVU1654 4837 .LBB488: ARM GAS /tmp/ccdsDELB.s page 434 623:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 4838 .loc 6 623 3 view .LVU1655 623:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 4839 .loc 6 623 11 is_stmt 0 view .LVU1656 4840 0124 D3F8B830 ldr r3, [r3, #184] 4841 0128 03F0C003 and r3, r3, #192 4842 .LVL351: 623:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 4843 .loc 6 623 11 view .LVU1657 4844 .LBE488: 4845 .LBE487: 4846 .LBB489: 4847 .LBI489: 1425:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 4848 .loc 6 1425 22 is_stmt 1 view .LVU1658 4849 .LBB490: 1428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 4850 .loc 6 1428 3 view .LVU1659 1428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 4851 .loc 6 1428 6 is_stmt 0 view .LVU1660 4852 012c 402B cmp r3, #64 4853 012e 7AD0 beq .L179 1436:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR 4854 .loc 6 1436 5 is_stmt 1 view .LVU1661 4855 0130 654B ldr r3, .L182+80 4856 .LVL352: 1436:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR 4857 .loc 6 1436 5 is_stmt 0 view .LVU1662 4858 0132 C3F8C010 str r1, [r3, #192] 1437:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 4859 .loc 6 1437 5 is_stmt 1 view .LVU1663 4860 0136 C3F8C420 str r2, [r3, #196] 4861 .L175: 4862 .LVL353: 1437:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 4863 .loc 6 1437 5 is_stmt 0 view .LVU1664 4864 .LBE490: 4865 .LBE489: 1531:Src/main.c **** SD_SLIDE = 0; 4866 .loc 2 1531 2 is_stmt 1 view .LVU1665 1531:Src/main.c **** SD_SLIDE = 0; 4867 .loc 2 1531 10 is_stmt 0 view .LVU1666 4868 013a 0024 movs r4, #0 4869 013c 654B ldr r3, .L182+92 4870 013e 1C60 str r4, [r3] 1532:Src/main.c **** //Reset all periphery 4871 .loc 2 1532 2 is_stmt 1 view .LVU1667 1532:Src/main.c **** //Reset all periphery 4872 .loc 2 1532 11 is_stmt 0 view .LVU1668 4873 0140 654B ldr r3, .L182+96 4874 0142 1C60 str r4, [r3] 1534:Src/main.c **** HAL_GPIO_WritePin(EN_5V2_GPIO_Port, EN_5V2_Pin, GPIO_PIN_RESET); 4875 .loc 2 1534 2 is_stmt 1 view .LVU1669 4876 0144 654F ldr r7, .L182+100 4877 0146 2246 mov r2, r4 4878 0148 0821 movs r1, #8 4879 014a 3846 mov r0, r7 ARM GAS /tmp/ccdsDELB.s page 435 4880 014c FFF7FEFF bl HAL_GPIO_WritePin 4881 .LVL354: 1535:Src/main.c **** HAL_GPIO_WritePin(LD1_EN_GPIO_Port, LD1_EN_Pin, GPIO_PIN_RESET); 4882 .loc 2 1535 2 view .LVU1670 4883 0150 2246 mov r2, r4 4884 0152 0421 movs r1, #4 4885 0154 3846 mov r0, r7 4886 0156 FFF7FEFF bl HAL_GPIO_WritePin 4887 .LVL355: 1536:Src/main.c **** HAL_GPIO_WritePin(LD2_EN_GPIO_Port, LD2_EN_Pin, GPIO_PIN_RESET); 4888 .loc 2 1536 2 view .LVU1671 4889 015a DFF8A481 ldr r8, .L182+136 4890 015e 2246 mov r2, r4 4891 0160 4FF48071 mov r1, #256 4892 0164 4046 mov r0, r8 4893 0166 FFF7FEFF bl HAL_GPIO_WritePin 4894 .LVL356: 1537:Src/main.c **** HAL_GPIO_WritePin(REF0_EN_GPIO_Port, REF0_EN_Pin, GPIO_PIN_RESET); 4895 .loc 2 1537 2 view .LVU1672 4896 016a 2246 mov r2, r4 4897 016c 1021 movs r1, #16 4898 016e 3846 mov r0, r7 4899 0170 FFF7FEFF bl HAL_GPIO_WritePin 4900 .LVL357: 1538:Src/main.c **** HAL_GPIO_WritePin(REF2_ON_GPIO_Port, REF2_ON_Pin, GPIO_PIN_RESET); 4901 .loc 2 1538 2 view .LVU1673 4902 0174 5A4E ldr r6, .L182+104 4903 0176 2246 mov r2, r4 4904 0178 4FF48061 mov r1, #1024 4905 017c 3046 mov r0, r6 4906 017e FFF7FEFF bl HAL_GPIO_WritePin 4907 .LVL358: 1539:Src/main.c **** HAL_GPIO_WritePin(TECEN1_GPIO_Port, TECEN1_Pin, GPIO_PIN_RESET); 4908 .loc 2 1539 2 view .LVU1674 4909 0182 584D ldr r5, .L182+108 4910 0184 2246 mov r2, r4 4911 0186 0821 movs r1, #8 4912 0188 2846 mov r0, r5 4913 018a FFF7FEFF bl HAL_GPIO_WritePin 4914 .LVL359: 1540:Src/main.c **** HAL_GPIO_WritePin(TECEN2_GPIO_Port, TECEN2_Pin, GPIO_PIN_RESET); 4915 .loc 2 1540 2 view .LVU1675 4916 018e 2246 mov r2, r4 4917 0190 0121 movs r1, #1 4918 0192 2846 mov r0, r5 4919 0194 FFF7FEFF bl HAL_GPIO_WritePin 4920 .LVL360: 1541:Src/main.c **** HAL_GPIO_WritePin(TEC1_PD_GPIO_Port, TEC1_PD_Pin, GPIO_PIN_RESET); 4921 .loc 2 1541 2 view .LVU1676 4922 0198 2246 mov r2, r4 4923 019a 0221 movs r1, #2 4924 019c 2846 mov r0, r5 4925 019e FFF7FEFF bl HAL_GPIO_WritePin 4926 .LVL361: 1542:Src/main.c **** HAL_GPIO_WritePin(TEC2_PD_GPIO_Port, TEC2_PD_Pin, GPIO_PIN_RESET); 4927 .loc 2 1542 2 view .LVU1677 4928 01a2 2246 mov r2, r4 ARM GAS /tmp/ccdsDELB.s page 436 4929 01a4 4FF40061 mov r1, #2048 4930 01a8 3046 mov r0, r6 4931 01aa FFF7FEFF bl HAL_GPIO_WritePin 4932 .LVL362: 1543:Src/main.c **** // for (uint16_t i = 0; i < SD_Length; i++) 4933 .loc 2 1543 2 view .LVU1678 4934 01ae 2246 mov r2, r4 4935 01b0 2021 movs r1, #32 4936 01b2 3846 mov r0, r7 4937 01b4 FFF7FEFF bl HAL_GPIO_WritePin 4938 .LVL363: 1553:Src/main.c **** HAL_GPIO_WritePin(ADC_MPD2_CS_GPIO_Port, ADC_MPD2_CS_Pin, GPIO_PIN_SET);//Enable SPI for MPhD2 ADC 4939 .loc 2 1553 2 view .LVU1679 4940 01b8 07F50067 add r7, r7, #2048 4941 01bc 0122 movs r2, #1 4942 01be 4FF48061 mov r1, #1024 4943 01c2 3846 mov r0, r7 4944 01c4 FFF7FEFF bl HAL_GPIO_WritePin 4945 .LVL364: 1554:Src/main.c **** HAL_GPIO_WritePin(SPI4_CNV_GPIO_Port, SPI4_CNV_Pin, GPIO_PIN_SET); 4946 .loc 2 1554 2 view .LVU1680 4947 01c8 474C ldr r4, .L182+112 4948 01ca 0122 movs r2, #1 4949 01cc 4021 movs r1, #64 4950 01ce 2046 mov r0, r4 4951 01d0 FFF7FEFF bl HAL_GPIO_WritePin 4952 .LVL365: 1555:Src/main.c **** HAL_GPIO_WritePin(SPI5_CNV_GPIO_Port, SPI4_CNV_Pin, GPIO_PIN_SET); 4953 .loc 2 1555 2 view .LVU1681 4954 01d4 0122 movs r2, #1 4955 01d6 4FF48041 mov r1, #16384 4956 01da 3846 mov r0, r7 4957 01dc FFF7FEFF bl HAL_GPIO_WritePin 4958 .LVL366: 1556:Src/main.c **** HAL_GPIO_WritePin(DAC_LD1_CS_GPIO_Port, DAC_LD1_CS_Pin, GPIO_PIN_SET);//End operation with LDAC1 4959 .loc 2 1556 2 view .LVU1682 4960 01e0 0122 movs r2, #1 4961 01e2 4FF48041 mov r1, #16384 4962 01e6 2046 mov r0, r4 4963 01e8 FFF7FEFF bl HAL_GPIO_WritePin 4964 .LVL367: 1557:Src/main.c **** HAL_GPIO_WritePin(DAC_LD2_CS_GPIO_Port, DAC_LD2_CS_Pin, GPIO_PIN_SET);//End operation with LDAC2 4965 .loc 2 1557 2 view .LVU1683 4966 01ec 0122 movs r2, #1 4967 01ee 4FF48041 mov r1, #16384 4968 01f2 3046 mov r0, r6 4969 01f4 FFF7FEFF bl HAL_GPIO_WritePin 4970 .LVL368: 1558:Src/main.c **** HAL_GPIO_WritePin(DAC_TEC1_CS_GPIO_Port, DAC_TEC1_CS_Pin, GPIO_PIN_SET);//End operation with TEC1 4971 .loc 2 1558 2 view .LVU1684 4972 01f8 0122 movs r2, #1 4973 01fa 4021 movs r1, #64 4974 01fc 2846 mov r0, r5 4975 01fe FFF7FEFF bl HAL_GPIO_WritePin 4976 .LVL369: 1559:Src/main.c **** HAL_GPIO_WritePin(DAC_TEC2_CS_GPIO_Port, DAC_TEC2_CS_Pin, GPIO_PIN_SET);//End operation with TEC2 4977 .loc 2 1559 2 view .LVU1685 ARM GAS /tmp/ccdsDELB.s page 437 4978 0202 0122 movs r2, #1 4979 0204 4FF48051 mov r1, #4096 4980 0208 3046 mov r0, r6 4981 020a FFF7FEFF bl HAL_GPIO_WritePin 4982 .LVL370: 1560:Src/main.c **** 4983 .loc 2 1560 2 view .LVU1686 4984 020e 0122 movs r2, #1 4985 0210 1021 movs r1, #16 4986 0212 2846 mov r0, r5 4987 0214 FFF7FEFF bl HAL_GPIO_WritePin 4988 .LVL371: 1564:Src/main.c **** { 4989 .loc 2 1564 2 view .LVU1687 1564:Src/main.c **** { 4990 .loc 2 1564 6 is_stmt 0 view .LVU1688 4991 0218 0121 movs r1, #1 4992 021a 4046 mov r0, r8 4993 021c FFF7FEFF bl HAL_GPIO_ReadPin 4994 .LVL372: 1564:Src/main.c **** { 4995 .loc 2 1564 5 view .LVU1689 4996 0220 38B1 cbz r0, .L180 4997 .L170: 1594:Src/main.c **** static void Decode_uart(uint16_t *Command, LDx_SetupTypeDef *LD1_curr_setup, LDx_SetupTypeDef *LD2_ 4998 .loc 2 1594 1 view .LVU1690 4999 0222 BDE8F081 pop {r4, r5, r6, r7, r8, pc} 5000 .LVL373: 5001 .L179: 5002 .LBB492: 5003 .LBB491: 1430:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR, 5004 .loc 6 1430 5 is_stmt 1 view .LVU1691 5005 0226 284B ldr r3, .L182+80 5006 .LVL374: 1430:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR, 5007 .loc 6 1430 5 is_stmt 0 view .LVU1692 5008 0228 C3F8C410 str r1, [r3, #196] 1431:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 5009 .loc 6 1431 5 is_stmt 1 view .LVU1693 5010 022c C3F8C020 str r2, [r3, #192] 5011 0230 83E7 b .L175 5012 .LVL375: 5013 .L180: 1431:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 5014 .loc 6 1431 5 is_stmt 0 view .LVU1694 5015 .LBE491: 5016 .LBE492: 1567:Src/main.c **** { 5017 .loc 2 1567 3 is_stmt 1 view .LVU1695 1567:Src/main.c **** { 5018 .loc 2 1567 7 is_stmt 0 view .LVU1696 5019 0232 4FF48071 mov r1, #256 5020 0236 2846 mov r0, r5 5021 0238 FFF7FEFF bl HAL_GPIO_ReadPin 5022 .LVL376: 1567:Src/main.c **** { ARM GAS /tmp/ccdsDELB.s page 438 5023 .loc 2 1567 6 view .LVU1697 5024 023c 0028 cmp r0, #0 5025 023e F0D1 bne .L170 1570:Src/main.c **** if (test == 0) //0 - suc 5026 .loc 2 1570 4 is_stmt 1 view .LVU1698 1570:Src/main.c **** if (test == 0) //0 - suc 5027 .loc 2 1570 11 is_stmt 0 view .LVU1699 5028 0240 2A48 ldr r0, .L182+116 5029 0242 FFF7FEFF bl Mount_SD 5030 .LVL377: 1570:Src/main.c **** if (test == 0) //0 - suc 5031 .loc 2 1570 9 view .LVU1700 5032 0246 2A4B ldr r3, .L182+120 5033 0248 1860 str r0, [r3] 1571:Src/main.c **** { 5034 .loc 2 1571 4 is_stmt 1 view .LVU1701 1571:Src/main.c **** { 5035 .loc 2 1571 7 is_stmt 0 view .LVU1702 5036 024a 18B1 cbz r0, .L181 5037 .L177: 1583:Src/main.c **** } 5038 .loc 2 1583 4 is_stmt 1 view .LVU1703 1583:Src/main.c **** } 5039 .loc 2 1583 14 is_stmt 0 view .LVU1704 5040 024c 294B ldr r3, .L182+124 5041 024e 0122 movs r2, #1 5042 0250 1A70 strb r2, [r3] 1594:Src/main.c **** static void Decode_uart(uint16_t *Command, LDx_SetupTypeDef *LD1_curr_setup, LDx_SetupTypeDef *LD2_ 5043 .loc 2 1594 1 view .LVU1705 5044 0252 E6E7 b .L170 5045 .L181: 1574:Src/main.c **** test = Unmount_SD("/"); // 0 - succ 5046 .loc 2 1574 5 is_stmt 1 view .LVU1706 1574:Src/main.c **** test = Unmount_SD("/"); // 0 - succ 5047 .loc 2 1574 12 is_stmt 0 view .LVU1707 5048 0254 1E23 movs r3, #30 5049 0256 1A46 mov r2, r3 5050 0258 2749 ldr r1, .L182+128 5051 025a 2848 ldr r0, .L182+132 5052 025c FFF7FEFF bl Seek_Read_File 5053 .LVL378: 1574:Src/main.c **** test = Unmount_SD("/"); // 0 - succ 5054 .loc 2 1574 10 view .LVU1708 5055 0260 234C ldr r4, .L182+120 5056 0262 2060 str r0, [r4] 1575:Src/main.c **** UART_rec_incr = 0; 5057 .loc 2 1575 5 is_stmt 1 view .LVU1709 1575:Src/main.c **** UART_rec_incr = 0; 5058 .loc 2 1575 12 is_stmt 0 view .LVU1710 5059 0264 2148 ldr r0, .L182+116 5060 0266 FFF7FEFF bl Unmount_SD 5061 .LVL379: 1575:Src/main.c **** UART_rec_incr = 0; 5062 .loc 2 1575 10 view .LVU1711 5063 026a 2060 str r0, [r4] 1576:Src/main.c **** flg_tmt = 0;//Reset the timeout flag 5064 .loc 2 1576 5 is_stmt 1 view .LVU1712 ARM GAS /tmp/ccdsDELB.s page 439 1576:Src/main.c **** flg_tmt = 0;//Reset the timeout flag 5065 .loc 2 1576 19 is_stmt 0 view .LVU1713 5066 026c 0023 movs r3, #0 5067 026e 084A ldr r2, .L182+24 5068 0270 1380 strh r3, [r2] @ movhi 1577:Src/main.c **** } 5069 .loc 2 1577 5 is_stmt 1 view .LVU1714 1577:Src/main.c **** } 5070 .loc 2 1577 13 is_stmt 0 view .LVU1715 5071 0272 064A ldr r2, .L182+20 5072 0274 1370 strb r3, [r2] 5073 0276 E9E7 b .L177 5074 .L183: 5075 .align 2 5076 .L182: 5077 0278 00000000 .word .LANCHOR7 5078 027c 00000000 .word .LANCHOR3 5079 0280 00000000 .word .LANCHOR8 5080 0284 00000000 .word .LANCHOR9 5081 0288 00000000 .word .LANCHOR10 5082 028c 00000000 .word .LANCHOR11 5083 0290 00000000 .word .LANCHOR12 5084 0294 00000000 .word .LANCHOR13 5085 0298 00000000 .word .LANCHOR14 5086 029c 00000000 .word .LANCHOR15 5087 02a0 00000000 .word .LANCHOR16 5088 02a4 00000000 .word .LANCHOR6 5089 02a8 00000000 .word .LANCHOR17 5090 02ac 00000000 .word .LANCHOR18 5091 02b0 00000000 .word .LANCHOR19 5092 02b4 00000000 .word .LANCHOR20 5093 02b8 00000000 .word .LANCHOR21 5094 02bc 00000000 .word .LANCHOR22 5095 02c0 00100040 .word 1073745920 5096 02c4 08100140 .word 1073811464 5097 02c8 00640240 .word 1073898496 5098 02cc 00000000 .word .LANCHOR23 5099 02d0 28100140 .word 1073811496 5100 02d4 00000000 .word .LANCHOR24 5101 02d8 00000000 .word .LANCHOR25 5102 02dc 00080240 .word 1073874944 5103 02e0 00040240 .word 1073873920 5104 02e4 00000240 .word 1073872896 5105 02e8 00140240 .word 1073878016 5106 02ec 00000000 .word .LC0 5107 02f0 00000000 .word .LANCHOR5 5108 02f4 00000000 .word .LANCHOR27 5109 02f8 00000000 .word .LANCHOR26 5110 02fc 04000000 .word .LC1 5111 0300 000C0240 .word 1073875968 5112 .cfi_endproc 5113 .LFE1203: 5115 .section .text.Get_ADC,"ax",%progbits 5116 .align 1 5117 .syntax unified 5118 .thumb 5119 .thumb_func ARM GAS /tmp/ccdsDELB.s page 440 5120 .fpu fpv5-d16 5122 Get_ADC: 5123 .LVL380: 5124 .LFB1208: 1965:Src/main.c **** uint16_t OUT; 5125 .loc 2 1965 1 is_stmt 1 view -0 5126 .cfi_startproc 5127 @ args = 0, pretend = 0, frame = 0 5128 @ frame_needed = 0, uses_anonymous_args = 0 1965:Src/main.c **** uint16_t OUT; 5129 .loc 2 1965 1 is_stmt 0 view .LVU1717 5130 0000 10B5 push {r4, lr} 5131 .LCFI39: 5132 .cfi_def_cfa_offset 8 5133 .cfi_offset 4, -8 5134 .cfi_offset 14, -4 5135 0002 0024 movs r4, #0 1966:Src/main.c **** switch (num) 5136 .loc 2 1966 2 is_stmt 1 view .LVU1718 1967:Src/main.c **** { 5137 .loc 2 1967 2 view .LVU1719 5138 0004 0528 cmp r0, #5 5139 0006 2CD8 bhi .L193 5140 0008 DFE800F0 tbb [pc, r0] 5141 .L187: 5142 000c 03 .byte (.L192-.L187)/2 5143 000d 08 .byte (.L191-.L187)/2 5144 000e 12 .byte (.L190-.L187)/2 5145 000f 17 .byte (.L189-.L187)/2 5146 0010 1C .byte (.L188-.L187)/2 5147 0011 26 .byte (.L186-.L187)/2 5148 .p2align 1 5149 .L192: 1970:Src/main.c **** break; 5150 .loc 2 1970 5 view .LVU1720 5151 0012 1548 ldr r0, .L195 5152 .LVL381: 1970:Src/main.c **** break; 5153 .loc 2 1970 5 is_stmt 0 view .LVU1721 5154 0014 FFF7FEFF bl HAL_ADC_Start 5155 .LVL382: 1971:Src/main.c **** case 1: 5156 .loc 2 1971 4 is_stmt 1 view .LVU1722 5157 0018 2046 mov r0, r4 5158 .L185: 5159 .LVL383: 1990:Src/main.c **** } 5160 .loc 2 1990 2 view .LVU1723 1991:Src/main.c **** uint16_t PID_Controller_Temp(LDx_SetupTypeDef * LDx_curr_setup, LDx_ParamTypeDef * LDx_results, uin 5161 .loc 2 1991 1 is_stmt 0 view .LVU1724 5162 001a 10BD pop {r4, pc} 5163 .LVL384: 5164 .L191: 1973:Src/main.c **** OUT = HAL_ADC_GetValue(&hadc1); // Get value adc 5165 .loc 2 1973 5 is_stmt 1 view .LVU1725 5166 001c 124C ldr r4, .L195 5167 001e 6421 movs r1, #100 ARM GAS /tmp/ccdsDELB.s page 441 5168 0020 2046 mov r0, r4 5169 .LVL385: 1973:Src/main.c **** OUT = HAL_ADC_GetValue(&hadc1); // Get value adc 5170 .loc 2 1973 5 is_stmt 0 view .LVU1726 5171 0022 FFF7FEFF bl HAL_ADC_PollForConversion 5172 .LVL386: 1974:Src/main.c **** break; 5173 .loc 2 1974 9 is_stmt 1 view .LVU1727 1974:Src/main.c **** break; 5174 .loc 2 1974 15 is_stmt 0 view .LVU1728 5175 0026 2046 mov r0, r4 5176 0028 FFF7FEFF bl HAL_ADC_GetValue 5177 .LVL387: 1974:Src/main.c **** break; 5178 .loc 2 1974 13 view .LVU1729 5179 002c 80B2 uxth r0, r0 5180 .LVL388: 1975:Src/main.c **** case 2: 5181 .loc 2 1975 4 is_stmt 1 view .LVU1730 5182 002e F4E7 b .L185 5183 .LVL389: 5184 .L190: 1977:Src/main.c **** break; 5185 .loc 2 1977 5 view .LVU1731 5186 0030 0D48 ldr r0, .L195 5187 .LVL390: 1977:Src/main.c **** break; 5188 .loc 2 1977 5 is_stmt 0 view .LVU1732 5189 0032 FFF7FEFF bl HAL_ADC_Stop 5190 .LVL391: 1978:Src/main.c **** case 3: 5191 .loc 2 1978 4 is_stmt 1 view .LVU1733 5192 0036 2046 mov r0, r4 5193 0038 EFE7 b .L185 5194 .LVL392: 5195 .L189: 1980:Src/main.c **** break; 5196 .loc 2 1980 5 view .LVU1734 5197 003a 0C48 ldr r0, .L195+4 5198 .LVL393: 1980:Src/main.c **** break; 5199 .loc 2 1980 5 is_stmt 0 view .LVU1735 5200 003c FFF7FEFF bl HAL_ADC_Start 5201 .LVL394: 1981:Src/main.c **** case 4: 5202 .loc 2 1981 4 is_stmt 1 view .LVU1736 5203 0040 2046 mov r0, r4 5204 0042 EAE7 b .L185 5205 .LVL395: 5206 .L188: 1983:Src/main.c **** OUT = HAL_ADC_GetValue(&hadc3); // Get value adc 5207 .loc 2 1983 5 view .LVU1737 5208 0044 094C ldr r4, .L195+4 5209 0046 6421 movs r1, #100 5210 0048 2046 mov r0, r4 5211 .LVL396: 1983:Src/main.c **** OUT = HAL_ADC_GetValue(&hadc3); // Get value adc ARM GAS /tmp/ccdsDELB.s page 442 5212 .loc 2 1983 5 is_stmt 0 view .LVU1738 5213 004a FFF7FEFF bl HAL_ADC_PollForConversion 5214 .LVL397: 1984:Src/main.c **** break; 5215 .loc 2 1984 9 is_stmt 1 view .LVU1739 1984:Src/main.c **** break; 5216 .loc 2 1984 15 is_stmt 0 view .LVU1740 5217 004e 2046 mov r0, r4 5218 0050 FFF7FEFF bl HAL_ADC_GetValue 5219 .LVL398: 1984:Src/main.c **** break; 5220 .loc 2 1984 13 view .LVU1741 5221 0054 80B2 uxth r0, r0 5222 .LVL399: 1985:Src/main.c **** case 5: 5223 .loc 2 1985 4 is_stmt 1 view .LVU1742 5224 0056 E0E7 b .L185 5225 .LVL400: 5226 .L186: 1987:Src/main.c **** break; 5227 .loc 2 1987 9 view .LVU1743 5228 0058 0448 ldr r0, .L195+4 5229 .LVL401: 1987:Src/main.c **** break; 5230 .loc 2 1987 9 is_stmt 0 view .LVU1744 5231 005a FFF7FEFF bl HAL_ADC_Stop 5232 .LVL402: 1988:Src/main.c **** } 5233 .loc 2 1988 4 is_stmt 1 view .LVU1745 5234 005e 2046 mov r0, r4 5235 0060 DBE7 b .L185 5236 .LVL403: 5237 .L193: 1967:Src/main.c **** { 5238 .loc 2 1967 2 is_stmt 0 view .LVU1746 5239 0062 2046 mov r0, r4 5240 .LVL404: 1967:Src/main.c **** { 5241 .loc 2 1967 2 view .LVU1747 5242 0064 D9E7 b .L185 5243 .L196: 5244 0066 00BF .align 2 5245 .L195: 5246 0068 00000000 .word .LANCHOR28 5247 006c 00000000 .word .LANCHOR29 5248 .cfi_endproc 5249 .LFE1208: 5251 .section .text.Stop_TIM10,"ax",%progbits 5252 .align 1 5253 .syntax unified 5254 .thumb 5255 .thumb_func 5256 .fpu fpv5-d16 5258 Stop_TIM10: 5259 .LFB1217: 2030:Src/main.c **** uint8_t CheckChecksum(uint16_t *pbuff) 2031:Src/main.c **** { ARM GAS /tmp/ccdsDELB.s page 443 2032:Src/main.c **** uint16_t cl_ind; 2033:Src/main.c **** 2034:Src/main.c **** switch (UART_header) 2035:Src/main.c **** { 2036:Src/main.c **** case 0x7777: 2037:Src/main.c **** cl_ind = TSK_16 - 2; 2038:Src/main.c **** break; 2039:Src/main.c **** case 0x1111: 2040:Src/main.c **** cl_ind = CL_16 - 2; 2041:Src/main.c **** break; 2042:Src/main.c **** default: 2043:Src/main.c **** return 0; 2044:Src/main.c **** break; 2045:Src/main.c **** } 2046:Src/main.c **** 2047:Src/main.c **** CS_result = CalculateChecksum(pbuff, cl_ind); 2048:Src/main.c **** 2049:Src/main.c **** return ((CS_result == COMMAND[cl_ind]) ? 1 : 0); 2050:Src/main.c **** } 2051:Src/main.c **** uint16_t CalculateChecksum(uint16_t *pbuff, uint16_t len) 2052:Src/main.c **** { 2053:Src/main.c **** short i; 2054:Src/main.c **** uint16_t cs = *pbuff; 2055:Src/main.c **** 2056:Src/main.c **** for(i = 1; i < len; i++) 2057:Src/main.c **** { 2058:Src/main.c **** cs ^= *(pbuff+i); 2059:Src/main.c **** } 2060:Src/main.c **** return cs; 2061:Src/main.c **** } 2062:Src/main.c **** 2063:Src/main.c **** /*int SD_Init(void) 2064:Src/main.c **** { 2065:Src/main.c **** int test=0; 2066:Src/main.c **** if (HAL_GPIO_ReadPin(SDMMC1_EN_GPIO_Port, SDMMC1_EN_Pin)==GPIO_PIN_RESET) 2067:Src/main.c **** { 2068:Src/main.c **** test = Mount_SD("/"); 2069:Src/main.c **** if (test == 0) //0 - suc 2070:Src/main.c **** { 2071:Src/main.c **** //Format_SD(); 2072:Src/main.c **** test = Create_File("FILE1.TXT"); // 0 -suc 2073:Src/main.c **** //Create_File("FILE2.TXT"); 2074:Src/main.c **** Write_File ("FILE1.TXT", "____OSGG main borad information. Program made by Kazakov Viktor. Part 2075:Src/main.c **** test = Unmount_SD("/"); // 0 - succ 2076:Src/main.c **** return test; 2077:Src/main.c **** } 2078:Src/main.c **** else 2079:Src/main.c **** { 2080:Src/main.c **** return 1; 2081:Src/main.c **** } 2082:Src/main.c **** } 2083:Src/main.c **** else 2084:Src/main.c **** { 2085:Src/main.c **** return 1; 2086:Src/main.c **** } 2087:Src/main.c **** }*/ 2088:Src/main.c **** ARM GAS /tmp/ccdsDELB.s page 444 2089:Src/main.c **** int SD_SAVE(uint16_t *pbuff) 2090:Src/main.c **** { 2091:Src/main.c **** int test=0; 2092:Src/main.c **** if (HAL_GPIO_ReadPin(SDMMC1_EN_GPIO_Port, SDMMC1_EN_Pin)==GPIO_PIN_RESET) 2093:Src/main.c **** { 2094:Src/main.c **** test = Mount_SD("/"); 2095:Src/main.c **** if (test == 0) //0 - suc 2096:Src/main.c **** { 2097:Src/main.c **** //Format_SD(); 2098:Src/main.c **** test = Update_File_byte("FILE1.TXT", (uint8_t *)pbuff, DL_8); 2099:Src/main.c **** test = Unmount_SD("/"); // 0 - succ 2100:Src/main.c **** return test; 2101:Src/main.c **** } 2102:Src/main.c **** else 2103:Src/main.c **** { 2104:Src/main.c **** return 1; 2105:Src/main.c **** } 2106:Src/main.c **** } 2107:Src/main.c **** else 2108:Src/main.c **** { 2109:Src/main.c **** return 1; 2110:Src/main.c **** } 2111:Src/main.c **** } 2112:Src/main.c **** 2113:Src/main.c **** 2114:Src/main.c **** 2115:Src/main.c **** //uint32_t Get_Length(void) 2116:Src/main.c **** //{ 2117:Src/main.c **** // return SD_matr[0][0] + ((uint32_t) (SD_matr[0][1])<<16); 2118:Src/main.c **** //} 2119:Src/main.c **** 2120:Src/main.c **** int SD_READ(uint16_t *pbuff) 2121:Src/main.c **** { 2122:Src/main.c **** int test=0; 2123:Src/main.c **** if (HAL_GPIO_ReadPin(SDMMC1_EN_GPIO_Port, SDMMC1_EN_Pin)==GPIO_PIN_RESET) 2124:Src/main.c **** { 2125:Src/main.c **** test = Mount_SD("/"); 2126:Src/main.c **** if (test == 0) //0 - suc 2127:Src/main.c **** { 2128:Src/main.c **** //Format_SD(); 2129:Src/main.c **** test = Seek_Read_File ("FILE1.TXT", (uint8_t *)pbuff, DL_8, fgoto);//Read next 246 bytes 2130:Src/main.c **** fgoto+=DL_8; 2131:Src/main.c **** test = Unmount_SD("/"); // 0 - succ 2132:Src/main.c **** return test; 2133:Src/main.c **** } 2134:Src/main.c **** else 2135:Src/main.c **** { 2136:Src/main.c **** return 1; 2137:Src/main.c **** } 2138:Src/main.c **** } 2139:Src/main.c **** else 2140:Src/main.c **** { 2141:Src/main.c **** return 1; 2142:Src/main.c **** } 2143:Src/main.c **** 2144:Src/main.c **** /* for (uint16_t j = 0; j < DL_16; j++) 2145:Src/main.c **** { ARM GAS /tmp/ccdsDELB.s page 445 2146:Src/main.c **** *(pbuff+j) = SD_matr[SD_SLIDE][j]; 2147:Src/main.c **** } 2148:Src/main.c **** if (SD_SLIDERDR, USART_RDR_RDR) & 0xFFU); 3661:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 3662:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3663:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 3664:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Read Receiver Data register (Receive Data value, 9 bits) 3665:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll RDR RDR LL_USART_ReceiveData9 3666:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 3667:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Value between Min_Data=0x00 and Max_Data=0x1FF 3668:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3669:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint16_t LL_USART_ReceiveData9(const USART_TypeDef *USARTx) 3670:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 3671:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return (uint16_t)(READ_BIT(USARTx->RDR, USART_RDR_RDR)); 3672:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 3673:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3674:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 3675:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Write in Transmitter Data Register (Transmit Data value, 8 bits) 3676:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll TDR TDR LL_USART_TransmitData8 3677:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance ARM GAS /tmp/ccdsDELB.s page 457 3678:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param Value between Min_Data=0x00 and Max_Data=0xFF 3679:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 3680:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3681:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_TransmitData8(USART_TypeDef *USARTx, uint8_t Value) 5738 .loc 7 3681 22 view .LVU1870 5739 .LBB496: 3682:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 3683:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** USARTx->TDR = Value; 5740 .loc 7 3683 3 view .LVU1871 5741 .loc 7 3683 15 is_stmt 0 view .LVU1872 5742 0014 044A ldr r2, .L246 5743 0016 9462 str r4, [r2, #40] 5744 .LVL458: 5745 .loc 7 3683 15 view .LVU1873 5746 .LBE496: 5747 .LBE495: 2192:Src/main.c **** } 5748 .loc 2 2192 5 is_stmt 1 view .LVU1874 2192:Src/main.c **** } 5749 .loc 2 2192 8 is_stmt 0 view .LVU1875 5750 0018 0133 adds r3, r3, #1 5751 .LVL459: 2192:Src/main.c **** } 5752 .loc 2 2192 8 view .LVU1876 5753 001a 9BB2 uxth r3, r3 5754 .LVL460: 2188:Src/main.c **** { 5755 .loc 2 2188 9 is_stmt 1 view .LVU1877 5756 001c 8B42 cmp r3, r1 5757 001e F3D3 bcc .L241 2194:Src/main.c **** 5758 .loc 2 2194 1 is_stmt 0 view .LVU1878 5759 0020 5DF8044B ldr r4, [sp], #4 5760 .LCFI46: 5761 .cfi_restore 4 5762 .cfi_def_cfa_offset 0 5763 0024 7047 bx lr 5764 .L245: 2194:Src/main.c **** 5765 .loc 2 2194 1 view .LVU1879 5766 0026 7047 bx lr 5767 .L247: 5768 .align 2 5769 .L246: 5770 0028 00100140 .word 1073811456 5771 .cfi_endproc 5772 .LFE1215: 5774 .section .text.USART_TX_DMA,"ax",%progbits 5775 .align 1 5776 .global USART_TX_DMA 5777 .syntax unified 5778 .thumb 5779 .thumb_func 5780 .fpu fpv5-d16 5782 USART_TX_DMA: 5783 .LFB1216: 2197:Src/main.c **** while (u_tx_flg) {}//Wait until previous transfer not complete. u_tx_flg is resetting in DMA inter ARM GAS /tmp/ccdsDELB.s page 458 5784 .loc 2 2197 1 is_stmt 1 view -0 5785 .cfi_startproc 5786 @ args = 0, pretend = 0, frame = 0 5787 @ frame_needed = 0, uses_anonymous_args = 0 5788 @ link register save eliminated. 5789 .LVL461: 5790 .L249: 2198:Src/main.c **** LL_DMA_DisableStream(DMA2, LL_DMA_STREAM_7); 5791 .loc 2 2198 20 discriminator 1 view .LVU1881 2198:Src/main.c **** LL_DMA_DisableStream(DMA2, LL_DMA_STREAM_7); 5792 .loc 2 2198 8 discriminator 1 view .LVU1882 2198:Src/main.c **** LL_DMA_DisableStream(DMA2, LL_DMA_STREAM_7); 5793 .loc 2 2198 9 is_stmt 0 discriminator 1 view .LVU1883 5794 0000 0D4B ldr r3, .L250 5795 0002 1B78 ldrb r3, [r3] @ zero_extendqisi2 2198:Src/main.c **** LL_DMA_DisableStream(DMA2, LL_DMA_STREAM_7); 5796 .loc 2 2198 8 discriminator 1 view .LVU1884 5797 0004 002B cmp r3, #0 5798 0006 FBD1 bne .L249 2199:Src/main.c **** LL_DMA_SetDataLength(DMA2, LL_DMA_STREAM_7, sz); 5799 .loc 2 2199 2 is_stmt 1 view .LVU1885 5800 .LVL462: 5801 .LBB497: 5802 .LBI497: 517:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 5803 .loc 6 517 22 view .LVU1886 5804 .LBB498: 519:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 5805 .loc 6 519 3 view .LVU1887 5806 0008 0C4B ldr r3, .L250+4 5807 000a D3F8B820 ldr r2, [r3, #184] 5808 000e 22F00102 bic r2, r2, #1 5809 0012 C3F8B820 str r2, [r3, #184] 5810 .LVL463: 519:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 5811 .loc 6 519 3 is_stmt 0 view .LVU1888 5812 .LBE498: 5813 .LBE497: 2200:Src/main.c **** LL_DMA_EnableStream(DMA2, LL_DMA_STREAM_7); 5814 .loc 2 2200 3 is_stmt 1 view .LVU1889 5815 .LBB499: 5816 .LBI499: 971:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 5817 .loc 6 971 22 view .LVU1890 5818 .LBB500: 973:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 5819 .loc 6 973 3 view .LVU1891 5820 0016 D3F8BC10 ldr r1, [r3, #188] 5821 001a 094A ldr r2, .L250+8 5822 001c 0A40 ands r2, r2, r1 5823 001e 1043 orrs r0, r0, r2 5824 .LVL464: 973:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 5825 .loc 6 973 3 is_stmt 0 view .LVU1892 5826 0020 C3F8BC00 str r0, [r3, #188] 5827 .LVL465: 973:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } ARM GAS /tmp/ccdsDELB.s page 459 5828 .loc 6 973 3 view .LVU1893 5829 .LBE500: 5830 .LBE499: 2201:Src/main.c **** u_tx_flg = 1;//indicate that transfer begin 5831 .loc 2 2201 3 is_stmt 1 view .LVU1894 5832 .LBB501: 5833 .LBI501: 497:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 5834 .loc 6 497 22 view .LVU1895 5835 .LBB502: 499:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 5836 .loc 6 499 3 view .LVU1896 5837 0024 D3F8B820 ldr r2, [r3, #184] 5838 0028 42F00102 orr r2, r2, #1 5839 002c C3F8B820 str r2, [r3, #184] 5840 .LVL466: 499:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 5841 .loc 6 499 3 is_stmt 0 view .LVU1897 5842 .LBE502: 5843 .LBE501: 2202:Src/main.c **** } 5844 .loc 2 2202 2 is_stmt 1 view .LVU1898 2202:Src/main.c **** } 5845 .loc 2 2202 11 is_stmt 0 view .LVU1899 5846 0030 014B ldr r3, .L250 5847 0032 0122 movs r2, #1 5848 0034 1A70 strb r2, [r3] 2203:Src/main.c **** 5849 .loc 2 2203 1 view .LVU1900 5850 0036 7047 bx lr 5851 .L251: 5852 .align 2 5853 .L250: 5854 0038 00000000 .word .LANCHOR15 5855 003c 00640240 .word 1073898496 5856 0040 0000FFFF .word -65536 5857 .cfi_endproc 5858 .LFE1216: 5860 .section .text.Error_Handler,"ax",%progbits 5861 .align 1 5862 .global Error_Handler 5863 .syntax unified 5864 .thumb 5865 .thumb_func 5866 .fpu fpv5-d16 5868 Error_Handler: 5869 .LFB1218: 2211:Src/main.c **** //------------------------------------------------------- 2212:Src/main.c **** /* USER CODE END 4 */ 2213:Src/main.c **** 2214:Src/main.c **** /** 2215:Src/main.c **** * @brief This function is executed in case of error occurrence. 2216:Src/main.c **** * @retval None 2217:Src/main.c **** */ 2218:Src/main.c **** void Error_Handler(void) 2219:Src/main.c **** { 5870 .loc 2 2219 1 is_stmt 1 view -0 ARM GAS /tmp/ccdsDELB.s page 460 5871 .cfi_startproc 5872 @ Volatile: function does not return. 5873 @ args = 0, pretend = 0, frame = 0 5874 @ frame_needed = 0, uses_anonymous_args = 0 5875 @ link register save eliminated. 2220:Src/main.c **** /* USER CODE BEGIN Error_Handler_Debug */ 2221:Src/main.c **** /* User can add his own implementation to report the HAL error return state */ 2222:Src/main.c **** __disable_irq(); 5876 .loc 2 2222 3 view .LVU1902 5877 .LBB503: 5878 .LBI503: 140:Drivers/CMSIS/Include/cmsis_gcc.h **** { 5879 .loc 8 140 27 view .LVU1903 5880 .LBB504: 142:Drivers/CMSIS/Include/cmsis_gcc.h **** } 5881 .loc 8 142 3 view .LVU1904 5882 .syntax unified 5883 @ 142 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 5884 0000 72B6 cpsid i 5885 @ 0 "" 2 5886 .thumb 5887 .syntax unified 5888 .L253: 5889 .LBE504: 5890 .LBE503: 2223:Src/main.c **** while (1) 5891 .loc 2 2223 3 discriminator 1 view .LVU1905 2224:Src/main.c **** { 2225:Src/main.c **** } 5892 .loc 2 2225 3 discriminator 1 view .LVU1906 2223:Src/main.c **** while (1) 5893 .loc 2 2223 9 discriminator 1 view .LVU1907 5894 0002 FEE7 b .L253 5895 .cfi_endproc 5896 .LFE1218: 5898 .section .text.MX_ADC1_Init,"ax",%progbits 5899 .align 1 5900 .syntax unified 5901 .thumb 5902 .thumb_func 5903 .fpu fpv5-d16 5905 MX_ADC1_Init: 5906 .LFB1188: 605:Src/main.c **** 5907 .loc 2 605 1 view -0 5908 .cfi_startproc 5909 @ args = 0, pretend = 0, frame = 16 5910 @ frame_needed = 0, uses_anonymous_args = 0 5911 0000 00B5 push {lr} 5912 .LCFI47: 5913 .cfi_def_cfa_offset 4 5914 .cfi_offset 14, -4 5915 0002 85B0 sub sp, sp, #20 5916 .LCFI48: 5917 .cfi_def_cfa_offset 24 611:Src/main.c **** 5918 .loc 2 611 3 view .LVU1909 ARM GAS /tmp/ccdsDELB.s page 461 611:Src/main.c **** 5919 .loc 2 611 26 is_stmt 0 view .LVU1910 5920 0004 0023 movs r3, #0 5921 0006 0093 str r3, [sp] 5922 0008 0193 str r3, [sp, #4] 5923 000a 0293 str r3, [sp, #8] 5924 000c 0393 str r3, [sp, #12] 619:Src/main.c **** hadc1.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV8; 5925 .loc 2 619 3 is_stmt 1 view .LVU1911 619:Src/main.c **** hadc1.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV8; 5926 .loc 2 619 18 is_stmt 0 view .LVU1912 5927 000e 2B48 ldr r0, .L268 5928 0010 2B4A ldr r2, .L268+4 5929 0012 0260 str r2, [r0] 620:Src/main.c **** hadc1.Init.Resolution = ADC_RESOLUTION_12B; 5930 .loc 2 620 3 is_stmt 1 view .LVU1913 620:Src/main.c **** hadc1.Init.Resolution = ADC_RESOLUTION_12B; 5931 .loc 2 620 29 is_stmt 0 view .LVU1914 5932 0014 4FF44032 mov r2, #196608 5933 0018 4260 str r2, [r0, #4] 621:Src/main.c **** hadc1.Init.ScanConvMode = ADC_SCAN_ENABLE; 5934 .loc 2 621 3 is_stmt 1 view .LVU1915 621:Src/main.c **** hadc1.Init.ScanConvMode = ADC_SCAN_ENABLE; 5935 .loc 2 621 25 is_stmt 0 view .LVU1916 5936 001a 8360 str r3, [r0, #8] 622:Src/main.c **** hadc1.Init.ContinuousConvMode = DISABLE; 5937 .loc 2 622 3 is_stmt 1 view .LVU1917 622:Src/main.c **** hadc1.Init.ContinuousConvMode = DISABLE; 5938 .loc 2 622 27 is_stmt 0 view .LVU1918 5939 001c 0122 movs r2, #1 5940 001e 0261 str r2, [r0, #16] 623:Src/main.c **** hadc1.Init.DiscontinuousConvMode = DISABLE; 5941 .loc 2 623 3 is_stmt 1 view .LVU1919 623:Src/main.c **** hadc1.Init.DiscontinuousConvMode = DISABLE; 5942 .loc 2 623 33 is_stmt 0 view .LVU1920 5943 0020 8361 str r3, [r0, #24] 624:Src/main.c **** hadc1.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE; 5944 .loc 2 624 3 is_stmt 1 view .LVU1921 624:Src/main.c **** hadc1.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE; 5945 .loc 2 624 36 is_stmt 0 view .LVU1922 5946 0022 80F82030 strb r3, [r0, #32] 625:Src/main.c **** hadc1.Init.ExternalTrigConv = ADC_SOFTWARE_START; 5947 .loc 2 625 3 is_stmt 1 view .LVU1923 625:Src/main.c **** hadc1.Init.ExternalTrigConv = ADC_SOFTWARE_START; 5948 .loc 2 625 35 is_stmt 0 view .LVU1924 5949 0026 C362 str r3, [r0, #44] 626:Src/main.c **** hadc1.Init.DataAlign = ADC_DATAALIGN_RIGHT; 5950 .loc 2 626 3 is_stmt 1 view .LVU1925 626:Src/main.c **** hadc1.Init.DataAlign = ADC_DATAALIGN_RIGHT; 5951 .loc 2 626 31 is_stmt 0 view .LVU1926 5952 0028 2649 ldr r1, .L268+8 5953 002a 8162 str r1, [r0, #40] 627:Src/main.c **** hadc1.Init.NbrOfConversion = 5; 5954 .loc 2 627 3 is_stmt 1 view .LVU1927 627:Src/main.c **** hadc1.Init.NbrOfConversion = 5; 5955 .loc 2 627 24 is_stmt 0 view .LVU1928 5956 002c C360 str r3, [r0, #12] ARM GAS /tmp/ccdsDELB.s page 462 628:Src/main.c **** hadc1.Init.DMAContinuousRequests = DISABLE; 5957 .loc 2 628 3 is_stmt 1 view .LVU1929 628:Src/main.c **** hadc1.Init.DMAContinuousRequests = DISABLE; 5958 .loc 2 628 30 is_stmt 0 view .LVU1930 5959 002e 0521 movs r1, #5 5960 0030 C161 str r1, [r0, #28] 629:Src/main.c **** hadc1.Init.EOCSelection = ADC_EOC_SINGLE_CONV; 5961 .loc 2 629 3 is_stmt 1 view .LVU1931 629:Src/main.c **** hadc1.Init.EOCSelection = ADC_EOC_SINGLE_CONV; 5962 .loc 2 629 36 is_stmt 0 view .LVU1932 5963 0032 80F83030 strb r3, [r0, #48] 630:Src/main.c **** if (HAL_ADC_Init(&hadc1) != HAL_OK) 5964 .loc 2 630 3 is_stmt 1 view .LVU1933 630:Src/main.c **** if (HAL_ADC_Init(&hadc1) != HAL_OK) 5965 .loc 2 630 27 is_stmt 0 view .LVU1934 5966 0036 4261 str r2, [r0, #20] 631:Src/main.c **** { 5967 .loc 2 631 3 is_stmt 1 view .LVU1935 631:Src/main.c **** { 5968 .loc 2 631 7 is_stmt 0 view .LVU1936 5969 0038 FFF7FEFF bl HAL_ADC_Init 5970 .LVL467: 631:Src/main.c **** { 5971 .loc 2 631 6 view .LVU1937 5972 003c 0028 cmp r0, #0 5973 003e 31D1 bne .L262 638:Src/main.c **** sConfig.Rank = ADC_REGULAR_RANK_1; 5974 .loc 2 638 3 is_stmt 1 view .LVU1938 638:Src/main.c **** sConfig.Rank = ADC_REGULAR_RANK_1; 5975 .loc 2 638 19 is_stmt 0 view .LVU1939 5976 0040 0923 movs r3, #9 5977 0042 0093 str r3, [sp] 639:Src/main.c **** sConfig.SamplingTime = ADC_SAMPLETIME_480CYCLES; 5978 .loc 2 639 3 is_stmt 1 view .LVU1940 639:Src/main.c **** sConfig.SamplingTime = ADC_SAMPLETIME_480CYCLES; 5979 .loc 2 639 16 is_stmt 0 view .LVU1941 5980 0044 0123 movs r3, #1 5981 0046 0193 str r3, [sp, #4] 640:Src/main.c **** if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 5982 .loc 2 640 3 is_stmt 1 view .LVU1942 640:Src/main.c **** if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 5983 .loc 2 640 24 is_stmt 0 view .LVU1943 5984 0048 0723 movs r3, #7 5985 004a 0293 str r3, [sp, #8] 641:Src/main.c **** { 5986 .loc 2 641 3 is_stmt 1 view .LVU1944 641:Src/main.c **** { 5987 .loc 2 641 7 is_stmt 0 view .LVU1945 5988 004c 6946 mov r1, sp 5989 004e 1B48 ldr r0, .L268 5990 0050 FFF7FEFF bl HAL_ADC_ConfigChannel 5991 .LVL468: 641:Src/main.c **** { 5992 .loc 2 641 6 view .LVU1946 5993 0054 40BB cbnz r0, .L263 648:Src/main.c **** sConfig.Rank = ADC_REGULAR_RANK_2; 5994 .loc 2 648 3 is_stmt 1 view .LVU1947 ARM GAS /tmp/ccdsDELB.s page 463 648:Src/main.c **** sConfig.Rank = ADC_REGULAR_RANK_2; 5995 .loc 2 648 19 is_stmt 0 view .LVU1948 5996 0056 0823 movs r3, #8 5997 0058 0093 str r3, [sp] 649:Src/main.c **** if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 5998 .loc 2 649 3 is_stmt 1 view .LVU1949 649:Src/main.c **** if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 5999 .loc 2 649 16 is_stmt 0 view .LVU1950 6000 005a 0223 movs r3, #2 6001 005c 0193 str r3, [sp, #4] 650:Src/main.c **** { 6002 .loc 2 650 3 is_stmt 1 view .LVU1951 650:Src/main.c **** { 6003 .loc 2 650 7 is_stmt 0 view .LVU1952 6004 005e 6946 mov r1, sp 6005 0060 1648 ldr r0, .L268 6006 0062 FFF7FEFF bl HAL_ADC_ConfigChannel 6007 .LVL469: 650:Src/main.c **** { 6008 .loc 2 650 6 view .LVU1953 6009 0066 08BB cbnz r0, .L264 657:Src/main.c **** sConfig.Rank = ADC_REGULAR_RANK_3; 6010 .loc 2 657 3 is_stmt 1 view .LVU1954 657:Src/main.c **** sConfig.Rank = ADC_REGULAR_RANK_3; 6011 .loc 2 657 19 is_stmt 0 view .LVU1955 6012 0068 0223 movs r3, #2 6013 006a 0093 str r3, [sp] 658:Src/main.c **** if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 6014 .loc 2 658 3 is_stmt 1 view .LVU1956 658:Src/main.c **** if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 6015 .loc 2 658 16 is_stmt 0 view .LVU1957 6016 006c 0323 movs r3, #3 6017 006e 0193 str r3, [sp, #4] 659:Src/main.c **** { 6018 .loc 2 659 3 is_stmt 1 view .LVU1958 659:Src/main.c **** { 6019 .loc 2 659 7 is_stmt 0 view .LVU1959 6020 0070 6946 mov r1, sp 6021 0072 1248 ldr r0, .L268 6022 0074 FFF7FEFF bl HAL_ADC_ConfigChannel 6023 .LVL470: 659:Src/main.c **** { 6024 .loc 2 659 6 view .LVU1960 6025 0078 D0B9 cbnz r0, .L265 666:Src/main.c **** sConfig.Rank = ADC_REGULAR_RANK_4; 6026 .loc 2 666 3 is_stmt 1 view .LVU1961 666:Src/main.c **** sConfig.Rank = ADC_REGULAR_RANK_4; 6027 .loc 2 666 19 is_stmt 0 view .LVU1962 6028 007a 0A23 movs r3, #10 6029 007c 0093 str r3, [sp] 667:Src/main.c **** if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 6030 .loc 2 667 3 is_stmt 1 view .LVU1963 667:Src/main.c **** if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 6031 .loc 2 667 16 is_stmt 0 view .LVU1964 6032 007e 0423 movs r3, #4 6033 0080 0193 str r3, [sp, #4] 668:Src/main.c **** { ARM GAS /tmp/ccdsDELB.s page 464 6034 .loc 2 668 3 is_stmt 1 view .LVU1965 668:Src/main.c **** { 6035 .loc 2 668 7 is_stmt 0 view .LVU1966 6036 0082 6946 mov r1, sp 6037 0084 0D48 ldr r0, .L268 6038 0086 FFF7FEFF bl HAL_ADC_ConfigChannel 6039 .LVL471: 668:Src/main.c **** { 6040 .loc 2 668 6 view .LVU1967 6041 008a 98B9 cbnz r0, .L266 675:Src/main.c **** sConfig.Rank = ADC_REGULAR_RANK_5; 6042 .loc 2 675 3 is_stmt 1 view .LVU1968 675:Src/main.c **** sConfig.Rank = ADC_REGULAR_RANK_5; 6043 .loc 2 675 19 is_stmt 0 view .LVU1969 6044 008c 0B23 movs r3, #11 6045 008e 0093 str r3, [sp] 676:Src/main.c **** if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 6046 .loc 2 676 3 is_stmt 1 view .LVU1970 676:Src/main.c **** if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 6047 .loc 2 676 16 is_stmt 0 view .LVU1971 6048 0090 0523 movs r3, #5 6049 0092 0193 str r3, [sp, #4] 677:Src/main.c **** { 6050 .loc 2 677 3 is_stmt 1 view .LVU1972 677:Src/main.c **** { 6051 .loc 2 677 7 is_stmt 0 view .LVU1973 6052 0094 6946 mov r1, sp 6053 0096 0948 ldr r0, .L268 6054 0098 FFF7FEFF bl HAL_ADC_ConfigChannel 6055 .LVL472: 677:Src/main.c **** { 6056 .loc 2 677 6 view .LVU1974 6057 009c 60B9 cbnz r0, .L267 685:Src/main.c **** 6058 .loc 2 685 1 view .LVU1975 6059 009e 05B0 add sp, sp, #20 6060 .LCFI49: 6061 .cfi_remember_state 6062 .cfi_def_cfa_offset 4 6063 @ sp needed 6064 00a0 5DF804FB ldr pc, [sp], #4 6065 .L262: 6066 .LCFI50: 6067 .cfi_restore_state 633:Src/main.c **** } 6068 .loc 2 633 5 is_stmt 1 view .LVU1976 6069 00a4 FFF7FEFF bl Error_Handler 6070 .LVL473: 6071 .L263: 643:Src/main.c **** } 6072 .loc 2 643 5 view .LVU1977 6073 00a8 FFF7FEFF bl Error_Handler 6074 .LVL474: 6075 .L264: 652:Src/main.c **** } 6076 .loc 2 652 5 view .LVU1978 6077 00ac FFF7FEFF bl Error_Handler ARM GAS /tmp/ccdsDELB.s page 465 6078 .LVL475: 6079 .L265: 661:Src/main.c **** } 6080 .loc 2 661 5 view .LVU1979 6081 00b0 FFF7FEFF bl Error_Handler 6082 .LVL476: 6083 .L266: 670:Src/main.c **** } 6084 .loc 2 670 5 view .LVU1980 6085 00b4 FFF7FEFF bl Error_Handler 6086 .LVL477: 6087 .L267: 679:Src/main.c **** } 6088 .loc 2 679 5 view .LVU1981 6089 00b8 FFF7FEFF bl Error_Handler 6090 .LVL478: 6091 .L269: 6092 .align 2 6093 .L268: 6094 00bc 00000000 .word .LANCHOR28 6095 00c0 00200140 .word 1073815552 6096 00c4 0100000F .word 251658241 6097 .cfi_endproc 6098 .LFE1188: 6100 .section .text.MX_ADC3_Init,"ax",%progbits 6101 .align 1 6102 .syntax unified 6103 .thumb 6104 .thumb_func 6105 .fpu fpv5-d16 6107 MX_ADC3_Init: 6108 .LFB1189: 693:Src/main.c **** 6109 .loc 2 693 1 view -0 6110 .cfi_startproc 6111 @ args = 0, pretend = 0, frame = 16 6112 @ frame_needed = 0, uses_anonymous_args = 0 6113 0000 00B5 push {lr} 6114 .LCFI51: 6115 .cfi_def_cfa_offset 4 6116 .cfi_offset 14, -4 6117 0002 85B0 sub sp, sp, #20 6118 .LCFI52: 6119 .cfi_def_cfa_offset 24 699:Src/main.c **** 6120 .loc 2 699 3 view .LVU1983 699:Src/main.c **** 6121 .loc 2 699 26 is_stmt 0 view .LVU1984 6122 0004 0023 movs r3, #0 6123 0006 0093 str r3, [sp] 6124 0008 0193 str r3, [sp, #4] 6125 000a 0293 str r3, [sp, #8] 6126 000c 0393 str r3, [sp, #12] 707:Src/main.c **** hadc3.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV8; 6127 .loc 2 707 3 is_stmt 1 view .LVU1985 707:Src/main.c **** hadc3.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV8; 6128 .loc 2 707 18 is_stmt 0 view .LVU1986 ARM GAS /tmp/ccdsDELB.s page 466 6129 000e 1448 ldr r0, .L276 6130 0010 144A ldr r2, .L276+4 6131 0012 0260 str r2, [r0] 708:Src/main.c **** hadc3.Init.Resolution = ADC_RESOLUTION_12B; 6132 .loc 2 708 3 is_stmt 1 view .LVU1987 708:Src/main.c **** hadc3.Init.Resolution = ADC_RESOLUTION_12B; 6133 .loc 2 708 29 is_stmt 0 view .LVU1988 6134 0014 4FF44032 mov r2, #196608 6135 0018 4260 str r2, [r0, #4] 709:Src/main.c **** hadc3.Init.ScanConvMode = ADC_SCAN_DISABLE; 6136 .loc 2 709 3 is_stmt 1 view .LVU1989 709:Src/main.c **** hadc3.Init.ScanConvMode = ADC_SCAN_DISABLE; 6137 .loc 2 709 25 is_stmt 0 view .LVU1990 6138 001a 8360 str r3, [r0, #8] 710:Src/main.c **** hadc3.Init.ContinuousConvMode = DISABLE; 6139 .loc 2 710 3 is_stmt 1 view .LVU1991 710:Src/main.c **** hadc3.Init.ContinuousConvMode = DISABLE; 6140 .loc 2 710 27 is_stmt 0 view .LVU1992 6141 001c 0361 str r3, [r0, #16] 711:Src/main.c **** hadc3.Init.DiscontinuousConvMode = DISABLE; 6142 .loc 2 711 3 is_stmt 1 view .LVU1993 711:Src/main.c **** hadc3.Init.DiscontinuousConvMode = DISABLE; 6143 .loc 2 711 33 is_stmt 0 view .LVU1994 6144 001e 8361 str r3, [r0, #24] 712:Src/main.c **** hadc3.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE; 6145 .loc 2 712 3 is_stmt 1 view .LVU1995 712:Src/main.c **** hadc3.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE; 6146 .loc 2 712 36 is_stmt 0 view .LVU1996 6147 0020 80F82030 strb r3, [r0, #32] 713:Src/main.c **** hadc3.Init.ExternalTrigConv = ADC_SOFTWARE_START; 6148 .loc 2 713 3 is_stmt 1 view .LVU1997 713:Src/main.c **** hadc3.Init.ExternalTrigConv = ADC_SOFTWARE_START; 6149 .loc 2 713 35 is_stmt 0 view .LVU1998 6150 0024 C362 str r3, [r0, #44] 714:Src/main.c **** hadc3.Init.DataAlign = ADC_DATAALIGN_RIGHT; 6151 .loc 2 714 3 is_stmt 1 view .LVU1999 714:Src/main.c **** hadc3.Init.DataAlign = ADC_DATAALIGN_RIGHT; 6152 .loc 2 714 31 is_stmt 0 view .LVU2000 6153 0026 104A ldr r2, .L276+8 6154 0028 8262 str r2, [r0, #40] 715:Src/main.c **** hadc3.Init.NbrOfConversion = 1; 6155 .loc 2 715 3 is_stmt 1 view .LVU2001 715:Src/main.c **** hadc3.Init.NbrOfConversion = 1; 6156 .loc 2 715 24 is_stmt 0 view .LVU2002 6157 002a C360 str r3, [r0, #12] 716:Src/main.c **** hadc3.Init.DMAContinuousRequests = DISABLE; 6158 .loc 2 716 3 is_stmt 1 view .LVU2003 716:Src/main.c **** hadc3.Init.DMAContinuousRequests = DISABLE; 6159 .loc 2 716 30 is_stmt 0 view .LVU2004 6160 002c 0122 movs r2, #1 6161 002e C261 str r2, [r0, #28] 717:Src/main.c **** hadc3.Init.EOCSelection = ADC_EOC_SINGLE_CONV; 6162 .loc 2 717 3 is_stmt 1 view .LVU2005 717:Src/main.c **** hadc3.Init.EOCSelection = ADC_EOC_SINGLE_CONV; 6163 .loc 2 717 36 is_stmt 0 view .LVU2006 6164 0030 80F83030 strb r3, [r0, #48] 718:Src/main.c **** if (HAL_ADC_Init(&hadc3) != HAL_OK) ARM GAS /tmp/ccdsDELB.s page 467 6165 .loc 2 718 3 is_stmt 1 view .LVU2007 718:Src/main.c **** if (HAL_ADC_Init(&hadc3) != HAL_OK) 6166 .loc 2 718 27 is_stmt 0 view .LVU2008 6167 0034 4261 str r2, [r0, #20] 719:Src/main.c **** { 6168 .loc 2 719 3 is_stmt 1 view .LVU2009 719:Src/main.c **** { 6169 .loc 2 719 7 is_stmt 0 view .LVU2010 6170 0036 FFF7FEFF bl HAL_ADC_Init 6171 .LVL479: 719:Src/main.c **** { 6172 .loc 2 719 6 view .LVU2011 6173 003a 68B9 cbnz r0, .L274 726:Src/main.c **** sConfig.Rank = ADC_REGULAR_RANK_1; 6174 .loc 2 726 3 is_stmt 1 view .LVU2012 726:Src/main.c **** sConfig.Rank = ADC_REGULAR_RANK_1; 6175 .loc 2 726 19 is_stmt 0 view .LVU2013 6176 003c 0F23 movs r3, #15 6177 003e 0093 str r3, [sp] 727:Src/main.c **** sConfig.SamplingTime = ADC_SAMPLETIME_480CYCLES; 6178 .loc 2 727 3 is_stmt 1 view .LVU2014 727:Src/main.c **** sConfig.SamplingTime = ADC_SAMPLETIME_480CYCLES; 6179 .loc 2 727 16 is_stmt 0 view .LVU2015 6180 0040 0123 movs r3, #1 6181 0042 0193 str r3, [sp, #4] 728:Src/main.c **** if (HAL_ADC_ConfigChannel(&hadc3, &sConfig) != HAL_OK) 6182 .loc 2 728 3 is_stmt 1 view .LVU2016 728:Src/main.c **** if (HAL_ADC_ConfigChannel(&hadc3, &sConfig) != HAL_OK) 6183 .loc 2 728 24 is_stmt 0 view .LVU2017 6184 0044 0723 movs r3, #7 6185 0046 0293 str r3, [sp, #8] 729:Src/main.c **** { 6186 .loc 2 729 3 is_stmt 1 view .LVU2018 729:Src/main.c **** { 6187 .loc 2 729 7 is_stmt 0 view .LVU2019 6188 0048 6946 mov r1, sp 6189 004a 0548 ldr r0, .L276 6190 004c FFF7FEFF bl HAL_ADC_ConfigChannel 6191 .LVL480: 729:Src/main.c **** { 6192 .loc 2 729 6 view .LVU2020 6193 0050 20B9 cbnz r0, .L275 737:Src/main.c **** 6194 .loc 2 737 1 view .LVU2021 6195 0052 05B0 add sp, sp, #20 6196 .LCFI53: 6197 .cfi_remember_state 6198 .cfi_def_cfa_offset 4 6199 @ sp needed 6200 0054 5DF804FB ldr pc, [sp], #4 6201 .L274: 6202 .LCFI54: 6203 .cfi_restore_state 721:Src/main.c **** } 6204 .loc 2 721 5 is_stmt 1 view .LVU2022 6205 0058 FFF7FEFF bl Error_Handler 6206 .LVL481: ARM GAS /tmp/ccdsDELB.s page 468 6207 .L275: 731:Src/main.c **** } 6208 .loc 2 731 5 view .LVU2023 6209 005c FFF7FEFF bl Error_Handler 6210 .LVL482: 6211 .L277: 6212 .align 2 6213 .L276: 6214 0060 00000000 .word .LANCHOR29 6215 0064 00220140 .word 1073816064 6216 0068 0100000F .word 251658241 6217 .cfi_endproc 6218 .LFE1189: 6220 .section .text.MX_USART1_UART_Init,"ax",%progbits 6221 .align 1 6222 .syntax unified 6223 .thumb 6224 .thumb_func 6225 .fpu fpv5-d16 6227 MX_USART1_UART_Init: 6228 .LFB1200: 1208:Src/main.c **** 6229 .loc 2 1208 1 view -0 6230 .cfi_startproc 6231 @ args = 0, pretend = 0, frame = 208 6232 @ frame_needed = 0, uses_anonymous_args = 0 6233 0000 2DE9F041 push {r4, r5, r6, r7, r8, lr} 6234 .LCFI55: 6235 .cfi_def_cfa_offset 24 6236 .cfi_offset 4, -24 6237 .cfi_offset 5, -20 6238 .cfi_offset 6, -16 6239 .cfi_offset 7, -12 6240 .cfi_offset 8, -8 6241 .cfi_offset 14, -4 6242 0004 B4B0 sub sp, sp, #208 6243 .LCFI56: 6244 .cfi_def_cfa_offset 232 1214:Src/main.c **** 6245 .loc 2 1214 3 view .LVU2025 1214:Src/main.c **** 6246 .loc 2 1214 24 is_stmt 0 view .LVU2026 6247 0006 0021 movs r1, #0 6248 0008 2D91 str r1, [sp, #180] 6249 000a 2E91 str r1, [sp, #184] 6250 000c 2F91 str r1, [sp, #188] 6251 000e 3091 str r1, [sp, #192] 6252 0010 3191 str r1, [sp, #196] 6253 0012 3291 str r1, [sp, #200] 6254 0014 3391 str r1, [sp, #204] 1216:Src/main.c **** RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; 6255 .loc 2 1216 3 is_stmt 1 view .LVU2027 1216:Src/main.c **** RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; 6256 .loc 2 1216 23 is_stmt 0 view .LVU2028 6257 0016 2791 str r1, [sp, #156] 6258 0018 2891 str r1, [sp, #160] 6259 001a 2991 str r1, [sp, #164] ARM GAS /tmp/ccdsDELB.s page 469 6260 001c 2A91 str r1, [sp, #168] 6261 001e 2B91 str r1, [sp, #172] 6262 0020 2C91 str r1, [sp, #176] 1217:Src/main.c **** 6263 .loc 2 1217 3 is_stmt 1 view .LVU2029 1217:Src/main.c **** 6264 .loc 2 1217 28 is_stmt 0 view .LVU2030 6265 0022 9022 movs r2, #144 6266 0024 03A8 add r0, sp, #12 6267 0026 FFF7FEFF bl memset 6268 .LVL483: 1221:Src/main.c **** PeriphClkInitStruct.Usart1ClockSelection = RCC_USART1CLKSOURCE_PCLK2; 6269 .loc 2 1221 3 is_stmt 1 view .LVU2031 1221:Src/main.c **** PeriphClkInitStruct.Usart1ClockSelection = RCC_USART1CLKSOURCE_PCLK2; 6270 .loc 2 1221 44 is_stmt 0 view .LVU2032 6271 002a 4023 movs r3, #64 6272 002c 0393 str r3, [sp, #12] 1222:Src/main.c **** if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) 6273 .loc 2 1222 3 is_stmt 1 view .LVU2033 1223:Src/main.c **** { 6274 .loc 2 1223 3 view .LVU2034 1223:Src/main.c **** { 6275 .loc 2 1223 7 is_stmt 0 view .LVU2035 6276 002e 03A8 add r0, sp, #12 6277 0030 FFF7FEFF bl HAL_RCCEx_PeriphCLKConfig 6278 .LVL484: 1223:Src/main.c **** { 6279 .loc 2 1223 6 view .LVU2036 6280 0034 0028 cmp r0, #0 6281 0036 40F09E80 bne .L281 1229:Src/main.c **** 6282 .loc 2 1229 3 is_stmt 1 view .LVU2037 6283 .LVL485: 6284 .LBB505: 6285 .LBI505: 1587:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { 6286 .loc 3 1587 22 view .LVU2038 6287 .LBB506: 1589:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** SET_BIT(RCC->APB2ENR, Periphs); 6288 .loc 3 1589 3 view .LVU2039 1590:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Delay after an RCC peripheral clock enabling */ 6289 .loc 3 1590 3 view .LVU2040 6290 003a 504B ldr r3, .L282 6291 003c 5A6C ldr r2, [r3, #68] 6292 003e 42F01002 orr r2, r2, #16 6293 0042 5A64 str r2, [r3, #68] 1592:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; 6294 .loc 3 1592 3 view .LVU2041 1592:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; 6295 .loc 3 1592 12 is_stmt 0 view .LVU2042 6296 0044 5A6C ldr r2, [r3, #68] 6297 0046 02F01002 and r2, r2, #16 1592:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; 6298 .loc 3 1592 10 view .LVU2043 6299 004a 0292 str r2, [sp, #8] 6300 .loc 3 1593 3 is_stmt 1 view .LVU2044 6301 004c 029A ldr r2, [sp, #8] ARM GAS /tmp/ccdsDELB.s page 470 6302 .LVL486: 6303 .loc 3 1593 3 is_stmt 0 view .LVU2045 6304 .LBE506: 6305 .LBE505: 1231:Src/main.c **** /**USART1 GPIO Configuration 6306 .loc 2 1231 3 is_stmt 1 view .LVU2046 6307 .LBB507: 6308 .LBI507: 309:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { 6309 .loc 3 309 22 view .LVU2047 6310 .LBB508: 311:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** SET_BIT(RCC->AHB1ENR, Periphs); 6311 .loc 3 311 3 view .LVU2048 312:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Delay after an RCC peripheral clock enabling */ 6312 .loc 3 312 3 view .LVU2049 6313 004e 1A6B ldr r2, [r3, #48] 6314 0050 42F00102 orr r2, r2, #1 6315 0054 1A63 str r2, [r3, #48] 314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; 6316 .loc 3 314 3 view .LVU2050 314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; 6317 .loc 3 314 12 is_stmt 0 view .LVU2051 6318 0056 1B6B ldr r3, [r3, #48] 6319 0058 03F00103 and r3, r3, #1 314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; 6320 .loc 3 314 10 view .LVU2052 6321 005c 0193 str r3, [sp, #4] 315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } 6322 .loc 3 315 3 is_stmt 1 view .LVU2053 6323 005e 019B ldr r3, [sp, #4] 6324 .LVL487: 315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } 6325 .loc 3 315 3 is_stmt 0 view .LVU2054 6326 .LBE508: 6327 .LBE507: 1236:Src/main.c **** GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE; 6328 .loc 2 1236 3 is_stmt 1 view .LVU2055 1236:Src/main.c **** GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE; 6329 .loc 2 1236 23 is_stmt 0 view .LVU2056 6330 0060 4FF40073 mov r3, #512 6331 0064 2793 str r3, [sp, #156] 1237:Src/main.c **** GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH; 6332 .loc 2 1237 3 is_stmt 1 view .LVU2057 1237:Src/main.c **** GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH; 6333 .loc 2 1237 24 is_stmt 0 view .LVU2058 6334 0066 4FF00208 mov r8, #2 6335 006a CDF8A080 str r8, [sp, #160] 1238:Src/main.c **** GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; 6336 .loc 2 1238 3 is_stmt 1 view .LVU2059 1238:Src/main.c **** GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; 6337 .loc 2 1238 25 is_stmt 0 view .LVU2060 6338 006e 0327 movs r7, #3 6339 0070 2997 str r7, [sp, #164] 1239:Src/main.c **** GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; 6340 .loc 2 1239 3 is_stmt 1 view .LVU2061 1239:Src/main.c **** GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; 6341 .loc 2 1239 30 is_stmt 0 view .LVU2062 ARM GAS /tmp/ccdsDELB.s page 471 6342 0072 0024 movs r4, #0 6343 0074 2A94 str r4, [sp, #168] 1240:Src/main.c **** GPIO_InitStruct.Alternate = LL_GPIO_AF_7; 6344 .loc 2 1240 3 is_stmt 1 view .LVU2063 1240:Src/main.c **** GPIO_InitStruct.Alternate = LL_GPIO_AF_7; 6345 .loc 2 1240 24 is_stmt 0 view .LVU2064 6346 0076 2B94 str r4, [sp, #172] 1241:Src/main.c **** LL_GPIO_Init(GPIOA, &GPIO_InitStruct); 6347 .loc 2 1241 3 is_stmt 1 view .LVU2065 1241:Src/main.c **** LL_GPIO_Init(GPIOA, &GPIO_InitStruct); 6348 .loc 2 1241 29 is_stmt 0 view .LVU2066 6349 0078 0726 movs r6, #7 6350 007a 2C96 str r6, [sp, #176] 1242:Src/main.c **** 6351 .loc 2 1242 3 is_stmt 1 view .LVU2067 6352 007c 404D ldr r5, .L282+4 6353 007e 27A9 add r1, sp, #156 6354 0080 2846 mov r0, r5 6355 0082 FFF7FEFF bl LL_GPIO_Init 6356 .LVL488: 1244:Src/main.c **** GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE; 6357 .loc 2 1244 3 view .LVU2068 1244:Src/main.c **** GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE; 6358 .loc 2 1244 23 is_stmt 0 view .LVU2069 6359 0086 4FF48063 mov r3, #1024 6360 008a 2793 str r3, [sp, #156] 1245:Src/main.c **** GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH; 6361 .loc 2 1245 3 is_stmt 1 view .LVU2070 1245:Src/main.c **** GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH; 6362 .loc 2 1245 24 is_stmt 0 view .LVU2071 6363 008c CDF8A080 str r8, [sp, #160] 1246:Src/main.c **** GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; 6364 .loc 2 1246 3 is_stmt 1 view .LVU2072 1246:Src/main.c **** GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; 6365 .loc 2 1246 25 is_stmt 0 view .LVU2073 6366 0090 2997 str r7, [sp, #164] 1247:Src/main.c **** GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; 6367 .loc 2 1247 3 is_stmt 1 view .LVU2074 1247:Src/main.c **** GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; 6368 .loc 2 1247 30 is_stmt 0 view .LVU2075 6369 0092 2A94 str r4, [sp, #168] 1248:Src/main.c **** GPIO_InitStruct.Alternate = LL_GPIO_AF_7; 6370 .loc 2 1248 3 is_stmt 1 view .LVU2076 1248:Src/main.c **** GPIO_InitStruct.Alternate = LL_GPIO_AF_7; 6371 .loc 2 1248 24 is_stmt 0 view .LVU2077 6372 0094 2B94 str r4, [sp, #172] 1249:Src/main.c **** LL_GPIO_Init(GPIOA, &GPIO_InitStruct); 6373 .loc 2 1249 3 is_stmt 1 view .LVU2078 1249:Src/main.c **** LL_GPIO_Init(GPIOA, &GPIO_InitStruct); 6374 .loc 2 1249 29 is_stmt 0 view .LVU2079 6375 0096 2C96 str r6, [sp, #176] 1250:Src/main.c **** 6376 .loc 2 1250 3 is_stmt 1 view .LVU2080 6377 0098 27A9 add r1, sp, #156 6378 009a 2846 mov r0, r5 6379 009c FFF7FEFF bl LL_GPIO_Init 6380 .LVL489: ARM GAS /tmp/ccdsDELB.s page 472 1255:Src/main.c **** 6381 .loc 2 1255 3 view .LVU2081 6382 .LBB509: 6383 .LBI509: 1032:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 6384 .loc 6 1032 22 view .LVU2082 6385 .LBB510: 1034:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 6386 .loc 6 1034 3 view .LVU2083 6387 00a0 384B ldr r3, .L282+8 6388 00a2 D3F8B820 ldr r2, [r3, #184] 6389 00a6 22F0F052 bic r2, r2, #503316480 6390 00aa 42F00062 orr r2, r2, #134217728 6391 00ae C3F8B820 str r2, [r3, #184] 6392 .LVL490: 1034:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 6393 .loc 6 1034 3 is_stmt 0 view .LVU2084 6394 .LBE510: 6395 .LBE509: 1257:Src/main.c **** 6396 .loc 2 1257 3 is_stmt 1 view .LVU2085 6397 .LBB511: 6398 .LBI511: 598:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 6399 .loc 6 598 22 view .LVU2086 6400 .LBB512: 600:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 6401 .loc 6 600 3 view .LVU2087 6402 00b2 D3F8B820 ldr r2, [r3, #184] 6403 00b6 22F0C002 bic r2, r2, #192 6404 00ba 42F04002 orr r2, r2, #64 6405 00be C3F8B820 str r2, [r3, #184] 6406 .LVL491: 600:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 6407 .loc 6 600 3 is_stmt 0 view .LVU2088 6408 .LBE512: 6409 .LBE511: 1259:Src/main.c **** 6410 .loc 2 1259 3 is_stmt 1 view .LVU2089 6411 .LBB513: 6412 .LBI513: 924:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 6413 .loc 6 924 22 view .LVU2090 6414 .LBB514: 926:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 6415 .loc 6 926 3 view .LVU2091 6416 00c2 D3F8B820 ldr r2, [r3, #184] 6417 00c6 42F44032 orr r2, r2, #196608 6418 00ca C3F8B820 str r2, [r3, #184] 6419 .LVL492: 926:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 6420 .loc 6 926 3 is_stmt 0 view .LVU2092 6421 .LBE514: 6422 .LBE513: 1261:Src/main.c **** 6423 .loc 2 1261 3 is_stmt 1 view .LVU2093 6424 .LBB515: ARM GAS /tmp/ccdsDELB.s page 473 6425 .LBI515: 646:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 6426 .loc 6 646 22 view .LVU2094 6427 .LBB516: 648:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 6428 .loc 6 648 3 view .LVU2095 6429 00ce D3F8B820 ldr r2, [r3, #184] 6430 00d2 22F49072 bic r2, r2, #288 6431 00d6 C3F8B820 str r2, [r3, #184] 6432 .LVL493: 648:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 6433 .loc 6 648 3 is_stmt 0 view .LVU2096 6434 .LBE516: 6435 .LBE515: 1263:Src/main.c **** 6436 .loc 2 1263 3 is_stmt 1 view .LVU2097 6437 .LBB517: 6438 .LBI517: 693:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 6439 .loc 6 693 22 view .LVU2098 6440 .LBB518: 695:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 6441 .loc 6 695 3 view .LVU2099 6442 00da D3F8B820 ldr r2, [r3, #184] 6443 00de 22F40072 bic r2, r2, #512 6444 00e2 C3F8B820 str r2, [r3, #184] 6445 .LVL494: 695:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 6446 .loc 6 695 3 is_stmt 0 view .LVU2100 6447 .LBE518: 6448 .LBE517: 1265:Src/main.c **** 6449 .loc 2 1265 3 is_stmt 1 view .LVU2101 6450 .LBB519: 6451 .LBI519: 738:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 6452 .loc 6 738 22 view .LVU2102 6453 .LBB520: 740:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 6454 .loc 6 740 3 view .LVU2103 6455 00e6 D3F8B820 ldr r2, [r3, #184] 6456 00ea 42F48062 orr r2, r2, #1024 6457 00ee C3F8B820 str r2, [r3, #184] 6458 .LVL495: 740:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 6459 .loc 6 740 3 is_stmt 0 view .LVU2104 6460 .LBE520: 6461 .LBE519: 1267:Src/main.c **** 6462 .loc 2 1267 3 is_stmt 1 view .LVU2105 6463 .LBB521: 6464 .LBI521: 784:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 6465 .loc 6 784 22 view .LVU2106 6466 .LBB522: 786:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 6467 .loc 6 786 3 view .LVU2107 ARM GAS /tmp/ccdsDELB.s page 474 6468 00f2 D3F8B820 ldr r2, [r3, #184] 6469 00f6 22F4C052 bic r2, r2, #6144 6470 00fa C3F8B820 str r2, [r3, #184] 6471 .LVL496: 786:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 6472 .loc 6 786 3 is_stmt 0 view .LVU2108 6473 .LBE522: 6474 .LBE521: 1269:Src/main.c **** 6475 .loc 2 1269 3 is_stmt 1 view .LVU2109 6476 .LBB523: 6477 .LBI523: 831:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 6478 .loc 6 831 22 view .LVU2110 6479 .LBB524: 833:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 6480 .loc 6 833 3 view .LVU2111 6481 00fe D3F8B820 ldr r2, [r3, #184] 6482 0102 22F4C042 bic r2, r2, #24576 6483 0106 C3F8B820 str r2, [r3, #184] 6484 .LVL497: 833:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 6485 .loc 6 833 3 is_stmt 0 view .LVU2112 6486 .LBE524: 6487 .LBE523: 1271:Src/main.c **** 6488 .loc 2 1271 3 is_stmt 1 view .LVU2113 6489 .LBB525: 6490 .LBI525: 1299:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 6491 .loc 6 1299 22 view .LVU2114 6492 .LBB526: 1301:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 6493 .loc 6 1301 3 view .LVU2115 6494 010a D3F8CC20 ldr r2, [r3, #204] 6495 010e 22F00402 bic r2, r2, #4 6496 0112 C3F8CC20 str r2, [r3, #204] 6497 .LVL498: 1301:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 6498 .loc 6 1301 3 is_stmt 0 view .LVU2116 6499 .LBE526: 6500 .LBE525: 1274:Src/main.c **** NVIC_EnableIRQ(USART1_IRQn); 6501 .loc 2 1274 3 is_stmt 1 view .LVU2117 6502 .LBB527: 6503 .LBI527: 1884:Drivers/CMSIS/Include/core_cm7.h **** { 6504 .loc 1 1884 26 view .LVU2118 6505 .LBB528: 1886:Drivers/CMSIS/Include/core_cm7.h **** } 6506 .loc 1 1886 3 view .LVU2119 1886:Drivers/CMSIS/Include/core_cm7.h **** } 6507 .loc 1 1886 26 is_stmt 0 view .LVU2120 6508 0116 1C4B ldr r3, .L282+12 6509 0118 D868 ldr r0, [r3, #12] 6510 .LBE528: 6511 .LBE527: ARM GAS /tmp/ccdsDELB.s page 475 1274:Src/main.c **** NVIC_EnableIRQ(USART1_IRQn); 6512 .loc 2 1274 3 view .LVU2121 6513 011a 2246 mov r2, r4 6514 011c 2146 mov r1, r4 6515 011e C0F30220 ubfx r0, r0, #8, #3 6516 0122 FFF7FEFF bl NVIC_EncodePriority 6517 .LVL499: 6518 .LBB529: 6519 .LBI529: 2024:Drivers/CMSIS/Include/core_cm7.h **** { 6520 .loc 1 2024 22 is_stmt 1 view .LVU2122 6521 .LBB530: 2026:Drivers/CMSIS/Include/core_cm7.h **** { 6522 .loc 1 2026 3 view .LVU2123 2028:Drivers/CMSIS/Include/core_cm7.h **** } 6523 .loc 1 2028 5 view .LVU2124 2028:Drivers/CMSIS/Include/core_cm7.h **** } 6524 .loc 1 2028 49 is_stmt 0 view .LVU2125 6525 0126 0001 lsls r0, r0, #4 6526 .LVL500: 2028:Drivers/CMSIS/Include/core_cm7.h **** } 6527 .loc 1 2028 49 view .LVU2126 6528 0128 C0B2 uxtb r0, r0 2028:Drivers/CMSIS/Include/core_cm7.h **** } 6529 .loc 1 2028 47 view .LVU2127 6530 012a 184B ldr r3, .L282+16 6531 012c 83F82503 strb r0, [r3, #805] 6532 .LVL501: 2028:Drivers/CMSIS/Include/core_cm7.h **** } 6533 .loc 1 2028 47 view .LVU2128 6534 .LBE530: 6535 .LBE529: 1275:Src/main.c **** 6536 .loc 2 1275 3 is_stmt 1 view .LVU2129 6537 .LBB531: 6538 .LBI531: 1896:Drivers/CMSIS/Include/core_cm7.h **** { 6539 .loc 1 1896 22 view .LVU2130 6540 .LBB532: 1898:Drivers/CMSIS/Include/core_cm7.h **** { 6541 .loc 1 1898 3 view .LVU2131 1900:Drivers/CMSIS/Include/core_cm7.h **** } 6542 .loc 1 1900 5 view .LVU2132 1900:Drivers/CMSIS/Include/core_cm7.h **** } 6543 .loc 1 1900 43 is_stmt 0 view .LVU2133 6544 0130 2022 movs r2, #32 6545 0132 5A60 str r2, [r3, #4] 6546 .LVL502: 1900:Drivers/CMSIS/Include/core_cm7.h **** } 6547 .loc 1 1900 43 view .LVU2134 6548 .LBE532: 6549 .LBE531: 1280:Src/main.c **** USART_InitStruct.DataWidth = LL_USART_DATAWIDTH_8B; 6550 .loc 2 1280 3 is_stmt 1 view .LVU2135 1280:Src/main.c **** USART_InitStruct.DataWidth = LL_USART_DATAWIDTH_8B; 6551 .loc 2 1280 29 is_stmt 0 view .LVU2136 6552 0134 4FF4E133 mov r3, #115200 ARM GAS /tmp/ccdsDELB.s page 476 6553 0138 2D93 str r3, [sp, #180] 1281:Src/main.c **** USART_InitStruct.StopBits = LL_USART_STOPBITS_1; 6554 .loc 2 1281 3 is_stmt 1 view .LVU2137 1281:Src/main.c **** USART_InitStruct.StopBits = LL_USART_STOPBITS_1; 6555 .loc 2 1281 30 is_stmt 0 view .LVU2138 6556 013a 2E94 str r4, [sp, #184] 1282:Src/main.c **** USART_InitStruct.Parity = LL_USART_PARITY_NONE; 6557 .loc 2 1282 3 is_stmt 1 view .LVU2139 1282:Src/main.c **** USART_InitStruct.Parity = LL_USART_PARITY_NONE; 6558 .loc 2 1282 29 is_stmt 0 view .LVU2140 6559 013c 2F94 str r4, [sp, #188] 1283:Src/main.c **** USART_InitStruct.TransferDirection = LL_USART_DIRECTION_TX_RX; 6560 .loc 2 1283 3 is_stmt 1 view .LVU2141 1283:Src/main.c **** USART_InitStruct.TransferDirection = LL_USART_DIRECTION_TX_RX; 6561 .loc 2 1283 27 is_stmt 0 view .LVU2142 6562 013e 3094 str r4, [sp, #192] 1284:Src/main.c **** USART_InitStruct.HardwareFlowControl = LL_USART_HWCONTROL_NONE; 6563 .loc 2 1284 3 is_stmt 1 view .LVU2143 1284:Src/main.c **** USART_InitStruct.HardwareFlowControl = LL_USART_HWCONTROL_NONE; 6564 .loc 2 1284 38 is_stmt 0 view .LVU2144 6565 0140 0C23 movs r3, #12 6566 0142 3193 str r3, [sp, #196] 1285:Src/main.c **** USART_InitStruct.OverSampling = LL_USART_OVERSAMPLING_16; 6567 .loc 2 1285 3 is_stmt 1 view .LVU2145 1285:Src/main.c **** USART_InitStruct.OverSampling = LL_USART_OVERSAMPLING_16; 6568 .loc 2 1285 40 is_stmt 0 view .LVU2146 6569 0144 3294 str r4, [sp, #200] 1286:Src/main.c **** LL_USART_Init(USART1, &USART_InitStruct); 6570 .loc 2 1286 3 is_stmt 1 view .LVU2147 1286:Src/main.c **** LL_USART_Init(USART1, &USART_InitStruct); 6571 .loc 2 1286 33 is_stmt 0 view .LVU2148 6572 0146 3394 str r4, [sp, #204] 1287:Src/main.c **** LL_USART_ConfigAsyncMode(USART1); 6573 .loc 2 1287 3 is_stmt 1 view .LVU2149 6574 0148 04F18044 add r4, r4, #1073741824 6575 014c 04F58834 add r4, r4, #69632 6576 0150 2DA9 add r1, sp, #180 6577 0152 2046 mov r0, r4 6578 0154 FFF7FEFF bl LL_USART_Init 6579 .LVL503: 1288:Src/main.c **** LL_USART_Enable(USART1); 6580 .loc 2 1288 3 view .LVU2150 6581 .LBB533: 6582 .LBI533: 2320:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 6583 .loc 7 2320 22 view .LVU2151 6584 .LBB534: 2326:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN | USART_CR3_HDSEL)); 6585 .loc 7 2326 3 view .LVU2152 6586 0158 6368 ldr r3, [r4, #4] 6587 015a 23F49043 bic r3, r3, #18432 6588 015e 6360 str r3, [r4, #4] 2327:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 6589 .loc 7 2327 3 view .LVU2153 6590 0160 A368 ldr r3, [r4, #8] 6591 0162 23F02A03 bic r3, r3, #42 6592 0166 A360 str r3, [r4, #8] ARM GAS /tmp/ccdsDELB.s page 477 6593 .LVL504: 2327:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 6594 .loc 7 2327 3 is_stmt 0 view .LVU2154 6595 .LBE534: 6596 .LBE533: 1289:Src/main.c **** /* USER CODE BEGIN USART1_Init 2 */ 6597 .loc 2 1289 3 is_stmt 1 view .LVU2155 6598 .LBB535: 6599 .LBI535: 560:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 6600 .loc 7 560 22 view .LVU2156 6601 .LBB536: 562:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 6602 .loc 7 562 3 view .LVU2157 6603 0168 2368 ldr r3, [r4] 6604 016a 43F00103 orr r3, r3, #1 6605 016e 2360 str r3, [r4] 6606 .LVL505: 562:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 6607 .loc 7 562 3 is_stmt 0 view .LVU2158 6608 .LBE536: 6609 .LBE535: 1294:Src/main.c **** 6610 .loc 2 1294 1 view .LVU2159 6611 0170 34B0 add sp, sp, #208 6612 .LCFI57: 6613 .cfi_remember_state 6614 .cfi_def_cfa_offset 24 6615 @ sp needed 6616 0172 BDE8F081 pop {r4, r5, r6, r7, r8, pc} 6617 .L281: 6618 .LCFI58: 6619 .cfi_restore_state 1225:Src/main.c **** } 6620 .loc 2 1225 5 is_stmt 1 view .LVU2160 6621 0176 FFF7FEFF bl Error_Handler 6622 .LVL506: 6623 .L283: 6624 017a 00BF .align 2 6625 .L282: 6626 017c 00380240 .word 1073887232 6627 0180 00000240 .word 1073872896 6628 0184 00640240 .word 1073898496 6629 0188 00ED00E0 .word -536810240 6630 018c 00E100E0 .word -536813312 6631 .cfi_endproc 6632 .LFE1200: 6634 .section .text.MX_TIM10_Init,"ax",%progbits 6635 .align 1 6636 .syntax unified 6637 .thumb 6638 .thumb_func 6639 .fpu fpv5-d16 6641 MX_TIM10_Init: 6642 .LFB1199: 1177:Src/main.c **** 6643 .loc 2 1177 1 view -0 ARM GAS /tmp/ccdsDELB.s page 478 6644 .cfi_startproc 6645 @ args = 0, pretend = 0, frame = 0 6646 @ frame_needed = 0, uses_anonymous_args = 0 6647 0000 08B5 push {r3, lr} 6648 .LCFI59: 6649 .cfi_def_cfa_offset 8 6650 .cfi_offset 3, -8 6651 .cfi_offset 14, -4 1186:Src/main.c **** htim10.Init.Prescaler = 183; 6652 .loc 2 1186 3 view .LVU2162 1186:Src/main.c **** htim10.Init.Prescaler = 183; 6653 .loc 2 1186 19 is_stmt 0 view .LVU2163 6654 0002 0848 ldr r0, .L288 6655 0004 084B ldr r3, .L288+4 6656 0006 0360 str r3, [r0] 1187:Src/main.c **** htim10.Init.CounterMode = TIM_COUNTERMODE_UP; 6657 .loc 2 1187 3 is_stmt 1 view .LVU2164 1187:Src/main.c **** htim10.Init.CounterMode = TIM_COUNTERMODE_UP; 6658 .loc 2 1187 25 is_stmt 0 view .LVU2165 6659 0008 B723 movs r3, #183 6660 000a 4360 str r3, [r0, #4] 1188:Src/main.c **** htim10.Init.Period = 9; 6661 .loc 2 1188 3 is_stmt 1 view .LVU2166 1188:Src/main.c **** htim10.Init.Period = 9; 6662 .loc 2 1188 27 is_stmt 0 view .LVU2167 6663 000c 0023 movs r3, #0 6664 000e 8360 str r3, [r0, #8] 1189:Src/main.c **** htim10.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; 6665 .loc 2 1189 3 is_stmt 1 view .LVU2168 1189:Src/main.c **** htim10.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; 6666 .loc 2 1189 22 is_stmt 0 view .LVU2169 6667 0010 0922 movs r2, #9 6668 0012 C260 str r2, [r0, #12] 1190:Src/main.c **** htim10.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; 6669 .loc 2 1190 3 is_stmt 1 view .LVU2170 1190:Src/main.c **** htim10.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; 6670 .loc 2 1190 29 is_stmt 0 view .LVU2171 6671 0014 0361 str r3, [r0, #16] 1191:Src/main.c **** if (HAL_TIM_Base_Init(&htim10) != HAL_OK) 6672 .loc 2 1191 3 is_stmt 1 view .LVU2172 1191:Src/main.c **** if (HAL_TIM_Base_Init(&htim10) != HAL_OK) 6673 .loc 2 1191 33 is_stmt 0 view .LVU2173 6674 0016 8361 str r3, [r0, #24] 1192:Src/main.c **** { 6675 .loc 2 1192 3 is_stmt 1 view .LVU2174 1192:Src/main.c **** { 6676 .loc 2 1192 7 is_stmt 0 view .LVU2175 6677 0018 FFF7FEFF bl HAL_TIM_Base_Init 6678 .LVL507: 1192:Src/main.c **** { 6679 .loc 2 1192 6 view .LVU2176 6680 001c 00B9 cbnz r0, .L287 1200:Src/main.c **** 6681 .loc 2 1200 1 view .LVU2177 6682 001e 08BD pop {r3, pc} 6683 .L287: 1194:Src/main.c **** } ARM GAS /tmp/ccdsDELB.s page 479 6684 .loc 2 1194 5 is_stmt 1 view .LVU2178 6685 0020 FFF7FEFF bl Error_Handler 6686 .LVL508: 6687 .L289: 6688 .align 2 6689 .L288: 6690 0024 00000000 .word .LANCHOR30 6691 0028 00440140 .word 1073824768 6692 .cfi_endproc 6693 .LFE1199: 6695 .section .text.SystemClock_Config,"ax",%progbits 6696 .align 1 6697 .global SystemClock_Config 6698 .syntax unified 6699 .thumb 6700 .thumb_func 6701 .fpu fpv5-d16 6703 SystemClock_Config: 6704 .LFB1187: 551:Src/main.c **** RCC_OscInitTypeDef RCC_OscInitStruct = {0}; 6705 .loc 2 551 1 view -0 6706 .cfi_startproc 6707 @ args = 0, pretend = 0, frame = 80 6708 @ frame_needed = 0, uses_anonymous_args = 0 6709 0000 00B5 push {lr} 6710 .LCFI60: 6711 .cfi_def_cfa_offset 4 6712 .cfi_offset 14, -4 6713 0002 95B0 sub sp, sp, #84 6714 .LCFI61: 6715 .cfi_def_cfa_offset 88 552:Src/main.c **** RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; 6716 .loc 2 552 3 view .LVU2180 552:Src/main.c **** RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; 6717 .loc 2 552 22 is_stmt 0 view .LVU2181 6718 0004 3422 movs r2, #52 6719 0006 0021 movs r1, #0 6720 0008 07A8 add r0, sp, #28 6721 000a FFF7FEFF bl memset 6722 .LVL509: 553:Src/main.c **** 6723 .loc 2 553 3 is_stmt 1 view .LVU2182 553:Src/main.c **** 6724 .loc 2 553 22 is_stmt 0 view .LVU2183 6725 000e 0023 movs r3, #0 6726 0010 0293 str r3, [sp, #8] 6727 0012 0393 str r3, [sp, #12] 6728 0014 0493 str r3, [sp, #16] 6729 0016 0593 str r3, [sp, #20] 6730 0018 0693 str r3, [sp, #24] 557:Src/main.c **** __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); 6731 .loc 2 557 3 is_stmt 1 view .LVU2184 6732 .LBB537: 557:Src/main.c **** __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); 6733 .loc 2 557 3 view .LVU2185 557:Src/main.c **** __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); 6734 .loc 2 557 3 view .LVU2186 ARM GAS /tmp/ccdsDELB.s page 480 6735 001a 244B ldr r3, .L298 6736 001c 1A6C ldr r2, [r3, #64] 6737 001e 42F08052 orr r2, r2, #268435456 6738 0022 1A64 str r2, [r3, #64] 557:Src/main.c **** __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); 6739 .loc 2 557 3 view .LVU2187 6740 0024 1B6C ldr r3, [r3, #64] 6741 0026 03F08053 and r3, r3, #268435456 6742 002a 0093 str r3, [sp] 557:Src/main.c **** __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); 6743 .loc 2 557 3 view .LVU2188 6744 002c 009B ldr r3, [sp] 6745 .LBE537: 557:Src/main.c **** __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); 6746 .loc 2 557 3 view .LVU2189 558:Src/main.c **** 6747 .loc 2 558 3 view .LVU2190 6748 .LBB538: 558:Src/main.c **** 6749 .loc 2 558 3 view .LVU2191 558:Src/main.c **** 6750 .loc 2 558 3 view .LVU2192 6751 002e 204B ldr r3, .L298+4 6752 0030 1A68 ldr r2, [r3] 6753 0032 42F44042 orr r2, r2, #49152 6754 0036 1A60 str r2, [r3] 558:Src/main.c **** 6755 .loc 2 558 3 view .LVU2193 6756 0038 1B68 ldr r3, [r3] 6757 003a 03F44043 and r3, r3, #49152 6758 003e 0193 str r3, [sp, #4] 558:Src/main.c **** 6759 .loc 2 558 3 view .LVU2194 6760 0040 019B ldr r3, [sp, #4] 6761 .LBE538: 558:Src/main.c **** 6762 .loc 2 558 3 view .LVU2195 563:Src/main.c **** RCC_OscInitStruct.HSEState = RCC_HSE_ON; 6763 .loc 2 563 3 view .LVU2196 563:Src/main.c **** RCC_OscInitStruct.HSEState = RCC_HSE_ON; 6764 .loc 2 563 36 is_stmt 0 view .LVU2197 6765 0042 0123 movs r3, #1 6766 0044 0793 str r3, [sp, #28] 564:Src/main.c **** RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; 6767 .loc 2 564 3 is_stmt 1 view .LVU2198 564:Src/main.c **** RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; 6768 .loc 2 564 30 is_stmt 0 view .LVU2199 6769 0046 4FF48033 mov r3, #65536 6770 004a 0893 str r3, [sp, #32] 565:Src/main.c **** RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; 6771 .loc 2 565 3 is_stmt 1 view .LVU2200 565:Src/main.c **** RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; 6772 .loc 2 565 34 is_stmt 0 view .LVU2201 6773 004c 0223 movs r3, #2 6774 004e 0D93 str r3, [sp, #52] 566:Src/main.c **** RCC_OscInitStruct.PLL.PLLM = 25; 6775 .loc 2 566 3 is_stmt 1 view .LVU2202 ARM GAS /tmp/ccdsDELB.s page 481 566:Src/main.c **** RCC_OscInitStruct.PLL.PLLM = 25; 6776 .loc 2 566 35 is_stmt 0 view .LVU2203 6777 0050 4FF48002 mov r2, #4194304 6778 0054 0E92 str r2, [sp, #56] 567:Src/main.c **** RCC_OscInitStruct.PLL.PLLN = 368; 6779 .loc 2 567 3 is_stmt 1 view .LVU2204 567:Src/main.c **** RCC_OscInitStruct.PLL.PLLN = 368; 6780 .loc 2 567 30 is_stmt 0 view .LVU2205 6781 0056 1922 movs r2, #25 6782 0058 0F92 str r2, [sp, #60] 568:Src/main.c **** RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; 6783 .loc 2 568 3 is_stmt 1 view .LVU2206 568:Src/main.c **** RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; 6784 .loc 2 568 30 is_stmt 0 view .LVU2207 6785 005a 4FF4B872 mov r2, #368 6786 005e 1092 str r2, [sp, #64] 569:Src/main.c **** RCC_OscInitStruct.PLL.PLLQ = 8; 6787 .loc 2 569 3 is_stmt 1 view .LVU2208 569:Src/main.c **** RCC_OscInitStruct.PLL.PLLQ = 8; 6788 .loc 2 569 30 is_stmt 0 view .LVU2209 6789 0060 1193 str r3, [sp, #68] 570:Src/main.c **** RCC_OscInitStruct.PLL.PLLR = 2; 6790 .loc 2 570 3 is_stmt 1 view .LVU2210 570:Src/main.c **** RCC_OscInitStruct.PLL.PLLR = 2; 6791 .loc 2 570 30 is_stmt 0 view .LVU2211 6792 0062 0822 movs r2, #8 6793 0064 1292 str r2, [sp, #72] 571:Src/main.c **** if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) 6794 .loc 2 571 3 is_stmt 1 view .LVU2212 571:Src/main.c **** if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) 6795 .loc 2 571 30 is_stmt 0 view .LVU2213 6796 0066 1393 str r3, [sp, #76] 572:Src/main.c **** { 6797 .loc 2 572 3 is_stmt 1 view .LVU2214 572:Src/main.c **** { 6798 .loc 2 572 7 is_stmt 0 view .LVU2215 6799 0068 07A8 add r0, sp, #28 6800 006a FFF7FEFF bl HAL_RCC_OscConfig 6801 .LVL510: 572:Src/main.c **** { 6802 .loc 2 572 6 view .LVU2216 6803 006e B0B9 cbnz r0, .L295 579:Src/main.c **** { 6804 .loc 2 579 3 is_stmt 1 view .LVU2217 579:Src/main.c **** { 6805 .loc 2 579 7 is_stmt 0 view .LVU2218 6806 0070 FFF7FEFF bl HAL_PWREx_EnableOverDrive 6807 .LVL511: 579:Src/main.c **** { 6808 .loc 2 579 6 view .LVU2219 6809 0074 A8B9 cbnz r0, .L296 586:Src/main.c **** |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; 6810 .loc 2 586 3 is_stmt 1 view .LVU2220 586:Src/main.c **** |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; 6811 .loc 2 586 31 is_stmt 0 view .LVU2221 6812 0076 0F23 movs r3, #15 6813 0078 0293 str r3, [sp, #8] ARM GAS /tmp/ccdsDELB.s page 482 588:Src/main.c **** RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; 6814 .loc 2 588 3 is_stmt 1 view .LVU2222 588:Src/main.c **** RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; 6815 .loc 2 588 34 is_stmt 0 view .LVU2223 6816 007a 0223 movs r3, #2 6817 007c 0393 str r3, [sp, #12] 589:Src/main.c **** RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4; 6818 .loc 2 589 3 is_stmt 1 view .LVU2224 589:Src/main.c **** RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4; 6819 .loc 2 589 35 is_stmt 0 view .LVU2225 6820 007e 0023 movs r3, #0 6821 0080 0493 str r3, [sp, #16] 590:Src/main.c **** RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; 6822 .loc 2 590 3 is_stmt 1 view .LVU2226 590:Src/main.c **** RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; 6823 .loc 2 590 36 is_stmt 0 view .LVU2227 6824 0082 4FF4A053 mov r3, #5120 6825 0086 0593 str r3, [sp, #20] 591:Src/main.c **** 6826 .loc 2 591 3 is_stmt 1 view .LVU2228 591:Src/main.c **** 6827 .loc 2 591 36 is_stmt 0 view .LVU2229 6828 0088 4FF48053 mov r3, #4096 6829 008c 0693 str r3, [sp, #24] 593:Src/main.c **** { 6830 .loc 2 593 3 is_stmt 1 view .LVU2230 593:Src/main.c **** { 6831 .loc 2 593 7 is_stmt 0 view .LVU2231 6832 008e 0621 movs r1, #6 6833 0090 02A8 add r0, sp, #8 6834 0092 FFF7FEFF bl HAL_RCC_ClockConfig 6835 .LVL512: 593:Src/main.c **** { 6836 .loc 2 593 6 view .LVU2232 6837 0096 30B9 cbnz r0, .L297 597:Src/main.c **** 6838 .loc 2 597 1 view .LVU2233 6839 0098 15B0 add sp, sp, #84 6840 .LCFI62: 6841 .cfi_remember_state 6842 .cfi_def_cfa_offset 4 6843 @ sp needed 6844 009a 5DF804FB ldr pc, [sp], #4 6845 .L295: 6846 .LCFI63: 6847 .cfi_restore_state 574:Src/main.c **** } 6848 .loc 2 574 5 is_stmt 1 view .LVU2234 6849 009e FFF7FEFF bl Error_Handler 6850 .LVL513: 6851 .L296: 581:Src/main.c **** } 6852 .loc 2 581 5 view .LVU2235 6853 00a2 FFF7FEFF bl Error_Handler 6854 .LVL514: 6855 .L297: 595:Src/main.c **** } ARM GAS /tmp/ccdsDELB.s page 483 6856 .loc 2 595 5 view .LVU2236 6857 00a6 FFF7FEFF bl Error_Handler 6858 .LVL515: 6859 .L299: 6860 00aa 00BF .align 2 6861 .L298: 6862 00ac 00380240 .word 1073887232 6863 00b0 00700040 .word 1073770496 6864 .cfi_endproc 6865 .LFE1187: 6867 .section .text.main,"ax",%progbits 6868 .align 1 6869 .global main 6870 .syntax unified 6871 .thumb 6872 .thumb_func 6873 .fpu fpv5-d16 6875 main: 6876 .LFB1186: 115:Src/main.c **** /* USER CODE BEGIN 1 */ 6877 .loc 2 115 1 view -0 6878 .cfi_startproc 6879 @ args = 0, pretend = 0, frame = 0 6880 @ frame_needed = 0, uses_anonymous_args = 0 6881 0000 2DE9F843 push {r3, r4, r5, r6, r7, r8, r9, lr} 6882 .LCFI64: 6883 .cfi_def_cfa_offset 32 6884 .cfi_offset 3, -32 6885 .cfi_offset 4, -28 6886 .cfi_offset 5, -24 6887 .cfi_offset 6, -20 6888 .cfi_offset 7, -16 6889 .cfi_offset 8, -12 6890 .cfi_offset 9, -8 6891 .cfi_offset 14, -4 117:Src/main.c **** /* USER CODE END 1 */ 6892 .loc 2 117 2 view .LVU2238 123:Src/main.c **** 6893 .loc 2 123 3 view .LVU2239 6894 0004 FFF7FEFF bl HAL_Init 6895 .LVL516: 130:Src/main.c **** 6896 .loc 2 130 3 view .LVU2240 6897 0008 FFF7FEFF bl SystemClock_Config 6898 .LVL517: 137:Src/main.c **** MX_DMA_Init(); 6899 .loc 2 137 3 view .LVU2241 6900 000c FFF7FEFF bl MX_GPIO_Init 6901 .LVL518: 138:Src/main.c **** MX_SPI4_Init(); 6902 .loc 2 138 3 view .LVU2242 6903 0010 FFF7FEFF bl MX_DMA_Init 6904 .LVL519: 139:Src/main.c **** MX_FATFS_Init(); 6905 .loc 2 139 3 view .LVU2243 6906 0014 FFF7FEFF bl MX_SPI4_Init 6907 .LVL520: ARM GAS /tmp/ccdsDELB.s page 484 140:Src/main.c **** MX_TIM2_Init(); 6908 .loc 2 140 3 view .LVU2244 6909 0018 FFF7FEFF bl MX_FATFS_Init 6910 .LVL521: 141:Src/main.c **** MX_TIM5_Init(); 6911 .loc 2 141 3 view .LVU2245 6912 001c FFF7FEFF bl MX_TIM2_Init 6913 .LVL522: 142:Src/main.c **** MX_ADC1_Init(); 6914 .loc 2 142 3 view .LVU2246 6915 0020 FFF7FEFF bl MX_TIM5_Init 6916 .LVL523: 143:Src/main.c **** MX_ADC3_Init(); 6917 .loc 2 143 3 view .LVU2247 6918 0024 FFF7FEFF bl MX_ADC1_Init 6919 .LVL524: 144:Src/main.c **** MX_SPI2_Init(); 6920 .loc 2 144 3 view .LVU2248 6921 0028 FFF7FEFF bl MX_ADC3_Init 6922 .LVL525: 145:Src/main.c **** MX_SPI5_Init(); 6923 .loc 2 145 3 view .LVU2249 6924 002c FFF7FEFF bl MX_SPI2_Init 6925 .LVL526: 146:Src/main.c **** MX_SPI6_Init(); 6926 .loc 2 146 3 view .LVU2250 6927 0030 FFF7FEFF bl MX_SPI5_Init 6928 .LVL527: 147:Src/main.c **** MX_USART1_UART_Init(); 6929 .loc 2 147 3 view .LVU2251 6930 0034 FFF7FEFF bl MX_SPI6_Init 6931 .LVL528: 148:Src/main.c **** MX_SDMMC1_SD_Init(); 6932 .loc 2 148 3 view .LVU2252 6933 0038 FFF7FEFF bl MX_USART1_UART_Init 6934 .LVL529: 149:Src/main.c **** MX_TIM7_Init(); 6935 .loc 2 149 3 view .LVU2253 6936 003c FFF7FEFF bl MX_SDMMC1_SD_Init 6937 .LVL530: 150:Src/main.c **** MX_TIM6_Init(); 6938 .loc 2 150 3 view .LVU2254 6939 0040 FFF7FEFF bl MX_TIM7_Init 6940 .LVL531: 151:Src/main.c **** MX_TIM10_Init(); 6941 .loc 2 151 3 view .LVU2255 6942 0044 FFF7FEFF bl MX_TIM6_Init 6943 .LVL532: 152:Src/main.c **** /* USER CODE BEGIN 2 */ 6944 .loc 2 152 3 view .LVU2256 6945 0048 FFF7FEFF bl MX_TIM10_Init 6946 .LVL533: 154:Src/main.c **** /* USER CODE END 2 */ 6947 .loc 2 154 2 view .LVU2257 6948 004c FFF7FEFF bl Init_params 6949 .LVL534: 6950 0050 3FE0 b .L301 ARM GAS /tmp/ccdsDELB.s page 485 6951 .L352: 161:Src/main.c **** { 6952 .loc 2 161 85 is_stmt 0 discriminator 1 view .LVU2258 6953 0052 744B ldr r3, .L359 6954 0054 1B78 ldrb r3, [r3] @ zero_extendqisi2 161:Src/main.c **** { 6955 .loc 2 161 73 discriminator 1 view .LVU2259 6956 0056 002B cmp r3, #0 6957 0058 42D1 bne .L302 6958 .L303: 3073:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 6959 .loc 7 3073 3 is_stmt 1 view .LVU2260 6960 .LBB539: 6961 .LBB540: 3073:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 6962 .loc 7 3073 3 view .LVU2261 3073:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 6963 .loc 7 3073 3 view .LVU2262 3073:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 6964 .loc 7 3073 3 view .LVU2263 6965 005a 734B ldr r3, .L359+4 6966 .LVL535: 6967 .LBB541: 6968 .LBI541: 1068:Drivers/CMSIS/Include/cmsis_gcc.h **** { 6969 .loc 8 1068 31 view .LVU2264 6970 .LBB542: 1070:Drivers/CMSIS/Include/cmsis_gcc.h **** 6971 .loc 8 1070 5 view .LVU2265 1072:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 6972 .loc 8 1072 4 view .LVU2266 6973 .syntax unified 6974 @ 1072 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 6975 005c 53E8002F ldrex r2, [r3] 6976 @ 0 "" 2 6977 .LVL536: 1073:Drivers/CMSIS/Include/cmsis_gcc.h **** } 6978 .loc 8 1073 4 view .LVU2267 1073:Drivers/CMSIS/Include/cmsis_gcc.h **** } 6979 .loc 8 1073 4 is_stmt 0 view .LVU2268 6980 .thumb 6981 .syntax unified 6982 .LBE542: 6983 .LBE541: 3073:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 6984 .loc 7 3073 3 view .LVU2269 6985 0060 42F48072 orr r2, r2, #256 6986 .LVL537: 3073:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 6987 .loc 7 3073 3 is_stmt 1 view .LVU2270 6988 .LBB543: 6989 .LBI543: 1119:Drivers/CMSIS/Include/cmsis_gcc.h **** { 6990 .loc 8 1119 31 view .LVU2271 6991 .LBB544: 1121:Drivers/CMSIS/Include/cmsis_gcc.h **** 6992 .loc 8 1121 4 view .LVU2272 ARM GAS /tmp/ccdsDELB.s page 486 1123:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 6993 .loc 8 1123 4 view .LVU2273 6994 .syntax unified 6995 @ 1123 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 6996 0064 43E80021 strex r1, r2, [r3] 6997 @ 0 "" 2 6998 .LVL538: 6999 .loc 8 1124 4 view .LVU2274 7000 .loc 8 1124 4 is_stmt 0 view .LVU2275 7001 .thumb 7002 .syntax unified 7003 .LBE544: 7004 .LBE543: 3073:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 7005 .loc 7 3073 3 view .LVU2276 7006 0068 0029 cmp r1, #0 7007 006a F6D1 bne .L303 7008 .LVL539: 7009 .L304: 3073:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 7010 .loc 7 3073 3 view .LVU2277 7011 .LBE540: 7012 .LBE539: 3040:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 7013 .loc 7 3040 3 is_stmt 1 view .LVU2278 7014 .LBB545: 7015 .LBB546: 3040:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 7016 .loc 7 3040 3 view .LVU2279 3040:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 7017 .loc 7 3040 3 view .LVU2280 3040:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 7018 .loc 7 3040 3 view .LVU2281 7019 .LBB547: 7020 .LBI547: 1068:Drivers/CMSIS/Include/cmsis_gcc.h **** { 7021 .loc 8 1068 31 view .LVU2282 7022 .LBB548: 1070:Drivers/CMSIS/Include/cmsis_gcc.h **** 7023 .loc 8 1070 5 view .LVU2283 1072:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 7024 .loc 8 1072 4 view .LVU2284 7025 .syntax unified 7026 @ 1072 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 7027 006c 53E8002F ldrex r2, [r3] 7028 @ 0 "" 2 7029 .LVL540: 1073:Drivers/CMSIS/Include/cmsis_gcc.h **** } 7030 .loc 8 1073 4 view .LVU2285 1073:Drivers/CMSIS/Include/cmsis_gcc.h **** } 7031 .loc 8 1073 4 is_stmt 0 view .LVU2286 7032 .thumb 7033 .syntax unified 7034 .LBE548: 7035 .LBE547: 3040:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 7036 .loc 7 3040 3 view .LVU2287 ARM GAS /tmp/ccdsDELB.s page 487 7037 0070 42F02002 orr r2, r2, #32 7038 .LVL541: 3040:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 7039 .loc 7 3040 3 is_stmt 1 view .LVU2288 7040 .LBB549: 7041 .LBI549: 1119:Drivers/CMSIS/Include/cmsis_gcc.h **** { 7042 .loc 8 1119 31 view .LVU2289 7043 .LBB550: 1121:Drivers/CMSIS/Include/cmsis_gcc.h **** 7044 .loc 8 1121 4 view .LVU2290 1123:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 7045 .loc 8 1123 4 view .LVU2291 7046 .syntax unified 7047 @ 1123 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 7048 0074 43E80021 strex r1, r2, [r3] 7049 @ 0 "" 2 7050 .LVL542: 7051 .loc 8 1124 4 view .LVU2292 7052 .loc 8 1124 4 is_stmt 0 view .LVU2293 7053 .thumb 7054 .syntax unified 7055 .LBE550: 7056 .LBE549: 3040:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 7057 .loc 7 3040 3 view .LVU2294 7058 0078 0029 cmp r1, #0 7059 007a F7D1 bne .L304 7060 .LVL543: 7061 .L305: 3040:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 7062 .loc 7 3040 3 view .LVU2295 7063 .LBE546: 7064 .LBE545: 3136:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 7065 .loc 7 3136 3 is_stmt 1 view .LVU2296 7066 .LBB551: 7067 .LBB552: 3136:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 7068 .loc 7 3136 3 view .LVU2297 3136:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 7069 .loc 7 3136 3 view .LVU2298 3136:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 7070 .loc 7 3136 3 view .LVU2299 7071 007c 6B4A ldr r2, .L359+8 7072 .LVL544: 7073 .LBB553: 7074 .LBI553: 1068:Drivers/CMSIS/Include/cmsis_gcc.h **** { 7075 .loc 8 1068 31 view .LVU2300 7076 .LBB554: 1070:Drivers/CMSIS/Include/cmsis_gcc.h **** 7077 .loc 8 1070 5 view .LVU2301 1072:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 7078 .loc 8 1072 4 view .LVU2302 7079 .syntax unified 7080 @ 1072 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 ARM GAS /tmp/ccdsDELB.s page 488 7081 007e 52E8003F ldrex r3, [r2] 7082 @ 0 "" 2 7083 .LVL545: 1073:Drivers/CMSIS/Include/cmsis_gcc.h **** } 7084 .loc 8 1073 4 view .LVU2303 1073:Drivers/CMSIS/Include/cmsis_gcc.h **** } 7085 .loc 8 1073 4 is_stmt 0 view .LVU2304 7086 .thumb 7087 .syntax unified 7088 .LBE554: 7089 .LBE553: 3136:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 7090 .loc 7 3136 3 view .LVU2305 7091 0082 43F00103 orr r3, r3, #1 7092 .LVL546: 3136:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 7093 .loc 7 3136 3 is_stmt 1 view .LVU2306 7094 .LBB555: 7095 .LBI555: 1119:Drivers/CMSIS/Include/cmsis_gcc.h **** { 7096 .loc 8 1119 31 view .LVU2307 7097 .LBB556: 1121:Drivers/CMSIS/Include/cmsis_gcc.h **** 7098 .loc 8 1121 4 view .LVU2308 1123:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 7099 .loc 8 1123 4 view .LVU2309 7100 .syntax unified 7101 @ 1123 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 7102 0086 42E80031 strex r1, r3, [r2] 7103 @ 0 "" 2 7104 .LVL547: 7105 .loc 8 1124 4 view .LVU2310 7106 .loc 8 1124 4 is_stmt 0 view .LVU2311 7107 .thumb 7108 .syntax unified 7109 .LBE556: 7110 .LBE555: 3136:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 7111 .loc 7 3136 3 view .LVU2312 7112 008a 0029 cmp r1, #0 7113 008c F6D1 bne .L305 7114 .LBE552: 7115 .LBE551: 3136:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 7116 .loc 7 3136 3 is_stmt 1 view .LVU2313 7117 .LVL548: 167:Src/main.c **** NVIC_EnableIRQ(USART1_IRQn);//In other case you have FE error flag... 7118 .loc 2 167 4 view .LVU2314 7119 .LBB557: 7120 .LBI557: 2024:Drivers/CMSIS/Include/core_cm7.h **** { 7121 .loc 1 2024 22 view .LVU2315 7122 .LBB558: 2026:Drivers/CMSIS/Include/core_cm7.h **** { 7123 .loc 1 2026 3 view .LVU2316 2028:Drivers/CMSIS/Include/core_cm7.h **** } 7124 .loc 1 2028 5 view .LVU2317 ARM GAS /tmp/ccdsDELB.s page 489 2028:Drivers/CMSIS/Include/core_cm7.h **** } 7125 .loc 1 2028 47 is_stmt 0 view .LVU2318 7126 008e 684B ldr r3, .L359+12 7127 0090 0022 movs r2, #0 7128 0092 83F82523 strb r2, [r3, #805] 7129 .LVL549: 2028:Drivers/CMSIS/Include/core_cm7.h **** } 7130 .loc 1 2028 47 view .LVU2319 7131 .LBE558: 7132 .LBE557: 168:Src/main.c **** u_rx_flg = 1; 7133 .loc 2 168 4 is_stmt 1 view .LVU2320 7134 .LBB559: 7135 .LBI559: 1896:Drivers/CMSIS/Include/core_cm7.h **** { 7136 .loc 1 1896 22 view .LVU2321 7137 .LBB560: 1898:Drivers/CMSIS/Include/core_cm7.h **** { 7138 .loc 1 1898 3 view .LVU2322 1900:Drivers/CMSIS/Include/core_cm7.h **** } 7139 .loc 1 1900 5 view .LVU2323 1900:Drivers/CMSIS/Include/core_cm7.h **** } 7140 .loc 1 1900 43 is_stmt 0 view .LVU2324 7141 0096 2022 movs r2, #32 7142 0098 5A60 str r2, [r3, #4] 7143 .LVL550: 1900:Drivers/CMSIS/Include/core_cm7.h **** } 7144 .loc 1 1900 43 view .LVU2325 7145 .LBE560: 7146 .LBE559: 169:Src/main.c **** } 7147 .loc 2 169 4 is_stmt 1 view .LVU2326 169:Src/main.c **** } 7148 .loc 2 169 13 is_stmt 0 view .LVU2327 7149 009a 624B ldr r3, .L359 7150 009c 0122 movs r2, #1 7151 009e 1A70 strb r2, [r3] 7152 00a0 1EE0 b .L302 7153 .L317: 179:Src/main.c **** task.current_param = task.min_param; 7154 .loc 2 179 6 is_stmt 1 view .LVU2328 179:Src/main.c **** task.current_param = task.min_param; 7155 .loc 2 179 20 is_stmt 0 view .LVU2329 7156 00a2 644B ldr r3, .L359+16 7157 00a4 0022 movs r2, #0 7158 00a6 1A70 strb r2, [r3] 180:Src/main.c **** Stop_TIM10(); 7159 .loc 2 180 6 is_stmt 1 view .LVU2330 180:Src/main.c **** Stop_TIM10(); 7160 .loc 2 180 31 is_stmt 0 view .LVU2331 7161 00a8 634B ldr r3, .L359+20 7162 00aa 5A68 ldr r2, [r3, #4] @ float 180:Src/main.c **** Stop_TIM10(); 7163 .loc 2 180 25 view .LVU2332 7164 00ac 1A61 str r2, [r3, #16] @ float 181:Src/main.c **** break; 7165 .loc 2 181 6 is_stmt 1 view .LVU2333 ARM GAS /tmp/ccdsDELB.s page 490 7166 00ae FFF7FEFF bl Stop_TIM10 7167 .LVL551: 182:Src/main.c **** case DECODE_ENABLE://1 - Decode rec. message 7168 .loc 2 182 5 view .LVU2334 7169 .L306: 490:Src/main.c **** { 7170 .loc 2 490 3 view .LVU2335 7171 00b2 624B ldr r3, .L359+24 7172 00b4 1B78 ldrb r3, [r3] @ zero_extendqisi2 7173 00b6 022B cmp r3, #2 7174 00b8 00F07583 beq .L341 7175 00bc 032B cmp r3, #3 7176 00be 00F0A683 beq .L348 7177 00c2 012B cmp r3, #1 7178 00c4 00F06483 beq .L350 7179 .L343: 532:Src/main.c **** { 7180 .loc 2 532 5 view .LVU2336 532:Src/main.c **** { 7181 .loc 2 532 17 is_stmt 0 view .LVU2337 7182 00c8 5D4B ldr r3, .L359+28 7183 00ca 1B78 ldrb r3, [r3] @ zero_extendqisi2 532:Src/main.c **** { 7184 .loc 2 532 8 view .LVU2338 7185 00cc 012B cmp r3, #1 7186 00ce 00F0A083 beq .L351 7187 .L301: 159:Src/main.c **** { 7188 .loc 2 159 3 is_stmt 1 view .LVU2339 161:Src/main.c **** { 7189 .loc 2 161 3 view .LVU2340 161:Src/main.c **** { 7190 .loc 2 161 8 is_stmt 0 view .LVU2341 7191 00d2 4FF48071 mov r1, #256 7192 00d6 5B48 ldr r0, .L359+32 7193 00d8 FFF7FEFF bl HAL_GPIO_ReadPin 7194 .LVL552: 161:Src/main.c **** { 7195 .loc 2 161 6 view .LVU2342 7196 00dc 0128 cmp r0, #1 7197 00de B8D0 beq .L352 7198 .L302: 176:Src/main.c **** { 7199 .loc 2 176 4 is_stmt 1 view .LVU2343 7200 00e0 594B ldr r3, .L359+36 7201 00e2 1B78 ldrb r3, [r3] @ zero_extendqisi2 7202 00e4 092B cmp r3, #9 7203 00e6 E4D8 bhi .L306 7204 00e8 01A2 adr r2, .L308 7205 00ea 52F823F0 ldr pc, [r2, r3, lsl #2] 7206 00ee 00BF .p2align 2 7207 .L308: 7208 00f0 A3000000 .word .L317+1 7209 00f4 19010000 .word .L316+1 7210 00f8 83010000 .word .L315+1 7211 00fc B9010000 .word .L314+1 7212 0100 E9010000 .word .L313+1 ARM GAS /tmp/ccdsDELB.s page 491 7213 0104 F9010000 .word .L312+1 7214 0108 15020000 .word .L311+1 7215 010c 79020000 .word .L310+1 7216 0110 C9030000 .word .L309+1 7217 0114 0F040000 .word .L307+1 7218 .p2align 1 7219 .L316: 184:Src/main.c **** if (CheckChecksum(COMMAND)) 7220 .loc 2 184 6 view .LVU2344 184:Src/main.c **** if (CheckChecksum(COMMAND)) 7221 .loc 2 184 18 is_stmt 0 view .LVU2345 7222 0118 4C4C ldr r4, .L359+40 7223 011a 0D21 movs r1, #13 7224 011c 2046 mov r0, r4 7225 011e FFF7FEFF bl CalculateChecksum 7226 .LVL553: 184:Src/main.c **** if (CheckChecksum(COMMAND)) 7227 .loc 2 184 16 view .LVU2346 7228 0122 4B4B ldr r3, .L359+44 7229 0124 1880 strh r0, [r3] @ movhi 185:Src/main.c **** { 7230 .loc 2 185 6 is_stmt 1 view .LVU2347 185:Src/main.c **** { 7231 .loc 2 185 10 is_stmt 0 view .LVU2348 7232 0126 2046 mov r0, r4 7233 0128 FFF7FEFF bl CheckChecksum 7234 .LVL554: 185:Src/main.c **** { 7235 .loc 2 185 9 view .LVU2349 7236 012c 70B9 cbnz r0, .L353 198:Src/main.c **** CPU_state = DEFAULT_ENABLE; 7237 .loc 2 198 7 is_stmt 1 view .LVU2350 198:Src/main.c **** CPU_state = DEFAULT_ENABLE; 7238 .loc 2 198 21 is_stmt 0 view .LVU2351 7239 012e 494A ldr r2, .L359+48 7240 0130 1378 ldrb r3, [r2] @ zero_extendqisi2 7241 0132 43F00403 orr r3, r3, #4 7242 0136 1370 strb r3, [r2] 199:Src/main.c **** CPU_state_old = HALT;//Save main current cycle 7243 .loc 2 199 7 is_stmt 1 view .LVU2352 199:Src/main.c **** CPU_state_old = HALT;//Save main current cycle 7244 .loc 2 199 17 is_stmt 0 view .LVU2353 7245 0138 434B ldr r3, .L359+36 7246 013a 0222 movs r2, #2 7247 013c 1A70 strb r2, [r3] 200:Src/main.c **** } 7248 .loc 2 200 7 is_stmt 1 view .LVU2354 200:Src/main.c **** } 7249 .loc 2 200 21 is_stmt 0 view .LVU2355 7250 013e 3D4B ldr r3, .L359+16 7251 0140 0022 movs r2, #0 7252 0142 1A70 strb r2, [r3] 7253 .L319: 202:Src/main.c **** break; 7254 .loc 2 202 6 is_stmt 1 view .LVU2356 202:Src/main.c **** break; 7255 .loc 2 202 32 is_stmt 0 view .LVU2357 ARM GAS /tmp/ccdsDELB.s page 492 7256 0144 3D4B ldr r3, .L359+24 7257 0146 0122 movs r2, #1 7258 0148 1A70 strb r2, [r3] 203:Src/main.c **** case DEFAULT_ENABLE://2 - Go to HALT 7259 .loc 2 203 5 is_stmt 1 view .LVU2358 7260 014a B2E7 b .L306 7261 .L353: 187:Src/main.c **** LL_SPI_Enable(SPI6);//Enable SPI for Laser2 DAC & TEC2 7262 .loc 2 187 7 view .LVU2359 7263 .LVL555: 7264 .LBB561: 7265 .LBI561: 358:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 7266 .loc 4 358 22 view .LVU2360 7267 .LBB562: 360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 7268 .loc 4 360 3 view .LVU2361 7269 014c 424A ldr r2, .L359+52 7270 014e 1368 ldr r3, [r2] 7271 0150 43F04003 orr r3, r3, #64 7272 0154 1360 str r3, [r2] 7273 .LVL556: 360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 7274 .loc 4 360 3 is_stmt 0 view .LVU2362 7275 .LBE562: 7276 .LBE561: 188:Src/main.c **** Decode_uart(COMMAND, &LD1_curr_setup, &LD2_curr_setup, &Curr_setup); 7277 .loc 2 188 7 is_stmt 1 view .LVU2363 7278 .LBB563: 7279 .LBI563: 358:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 7280 .loc 4 358 22 view .LVU2364 7281 .LBB564: 360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 7282 .loc 4 360 3 view .LVU2365 7283 0156 02F58E32 add r2, r2, #72704 7284 015a 1368 ldr r3, [r2] 7285 015c 43F04003 orr r3, r3, #64 7286 0160 1360 str r3, [r2] 7287 .LVL557: 360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 7288 .loc 4 360 3 is_stmt 0 view .LVU2366 7289 .LBE564: 7290 .LBE563: 189:Src/main.c **** TO6_before = TO6; 7291 .loc 2 189 7 is_stmt 1 view .LVU2367 7292 0162 3E4B ldr r3, .L359+56 7293 0164 3E4A ldr r2, .L359+60 7294 0166 3F49 ldr r1, .L359+64 7295 0168 2046 mov r0, r4 7296 016a FFF7FEFF bl Decode_uart 7297 .LVL558: 190:Src/main.c **** //LD1_param.LD_TEMP_Before = LD1_param.LD_TEMP; 7298 .loc 2 190 7 view .LVU2368 190:Src/main.c **** //LD1_param.LD_TEMP_Before = LD1_param.LD_TEMP; 7299 .loc 2 190 18 is_stmt 0 view .LVU2369 7300 016e 3E4B ldr r3, .L359+68 ARM GAS /tmp/ccdsDELB.s page 493 7301 0170 1A68 ldr r2, [r3] 7302 0172 3E4B ldr r3, .L359+72 7303 0174 1A60 str r2, [r3] 193:Src/main.c **** CPU_state_old = WORK_ENABLE;//Save main current cycle 7304 .loc 2 193 7 is_stmt 1 view .LVU2370 193:Src/main.c **** CPU_state_old = WORK_ENABLE;//Save main current cycle 7305 .loc 2 193 17 is_stmt 0 view .LVU2371 7306 0176 0723 movs r3, #7 7307 0178 334A ldr r2, .L359+36 7308 017a 1370 strb r3, [r2] 194:Src/main.c **** } 7309 .loc 2 194 7 is_stmt 1 view .LVU2372 194:Src/main.c **** } 7310 .loc 2 194 21 is_stmt 0 view .LVU2373 7311 017c 2D4A ldr r2, .L359+16 7312 017e 1370 strb r3, [r2] 7313 0180 E0E7 b .L319 7314 .L315: 206:Src/main.c **** Stop_TIM10(); 7315 .loc 2 206 6 is_stmt 1 view .LVU2374 206:Src/main.c **** Stop_TIM10(); 7316 .loc 2 206 31 is_stmt 0 view .LVU2375 7317 0182 2D4B ldr r3, .L359+20 7318 0184 5A68 ldr r2, [r3, #4] @ float 206:Src/main.c **** Stop_TIM10(); 7319 .loc 2 206 25 view .LVU2376 7320 0186 1A61 str r2, [r3, #16] @ float 207:Src/main.c **** Init_params(); 7321 .loc 2 207 6 is_stmt 1 view .LVU2377 7322 0188 FFF7FEFF bl Stop_TIM10 7323 .LVL559: 208:Src/main.c **** LL_SPI_Disable(SPI2);//Disable SPI for Laser1 DAC & TEC1 7324 .loc 2 208 6 view .LVU2378 7325 018c FFF7FEFF bl Init_params 7326 .LVL560: 209:Src/main.c **** LL_SPI_Disable(SPI6);//Disable SPI for Laser2 DAC & TEC2 7327 .loc 2 209 6 view .LVU2379 7328 .LBB565: 7329 .LBI565: 370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 7330 .loc 4 370 22 view .LVU2380 7331 .LBB566: 372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 7332 .loc 4 372 3 view .LVU2381 7333 0190 314A ldr r2, .L359+52 7334 0192 1368 ldr r3, [r2] 7335 0194 23F04003 bic r3, r3, #64 7336 0198 1360 str r3, [r2] 7337 .LVL561: 372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 7338 .loc 4 372 3 is_stmt 0 view .LVU2382 7339 .LBE566: 7340 .LBE565: 210:Src/main.c **** CPU_state = HALT; 7341 .loc 2 210 6 is_stmt 1 view .LVU2383 7342 .LBB567: 7343 .LBI567: ARM GAS /tmp/ccdsDELB.s page 494 370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 7344 .loc 4 370 22 view .LVU2384 7345 .LBB568: 372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 7346 .loc 4 372 3 view .LVU2385 7347 019a 02F58E32 add r2, r2, #72704 7348 019e 1368 ldr r3, [r2] 7349 01a0 23F04003 bic r3, r3, #64 7350 01a4 1360 str r3, [r2] 7351 .LVL562: 372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 7352 .loc 4 372 3 is_stmt 0 view .LVU2386 7353 .LBE568: 7354 .LBE567: 211:Src/main.c **** CPU_state_old = HALT;//Save main current cycle 7355 .loc 2 211 6 is_stmt 1 view .LVU2387 211:Src/main.c **** CPU_state_old = HALT;//Save main current cycle 7356 .loc 2 211 16 is_stmt 0 view .LVU2388 7357 01a6 0023 movs r3, #0 7358 01a8 274A ldr r2, .L359+36 7359 01aa 1370 strb r3, [r2] 212:Src/main.c **** UART_transmission_request = MESS_01; 7360 .loc 2 212 6 is_stmt 1 view .LVU2389 212:Src/main.c **** UART_transmission_request = MESS_01; 7361 .loc 2 212 20 is_stmt 0 view .LVU2390 7362 01ac 214A ldr r2, .L359+16 7363 01ae 1370 strb r3, [r2] 213:Src/main.c **** break; 7364 .loc 2 213 6 is_stmt 1 view .LVU2391 213:Src/main.c **** break; 7365 .loc 2 213 32 is_stmt 0 view .LVU2392 7366 01b0 224B ldr r3, .L359+24 7367 01b2 0122 movs r2, #1 7368 01b4 1A70 strb r2, [r3] 214:Src/main.c **** case TRANS_S_ENABLE://3 - Transmith saved packet Before this operation must to be defaulting! 7369 .loc 2 214 5 is_stmt 1 view .LVU2393 7370 01b6 7CE7 b .L306 7371 .L314: 216:Src/main.c **** State_Data[0]|=temp16&0xff; 7372 .loc 2 216 6 view .LVU2394 216:Src/main.c **** State_Data[0]|=temp16&0xff; 7373 .loc 2 216 15 is_stmt 0 view .LVU2395 7374 01b8 2D48 ldr r0, .L359+76 7375 01ba FFF7FEFF bl SD_READ 7376 .LVL563: 216:Src/main.c **** State_Data[0]|=temp16&0xff; 7377 .loc 2 216 13 view .LVU2396 7378 01be 80B2 uxth r0, r0 7379 01c0 2C4B ldr r3, .L359+80 7380 01c2 1880 strh r0, [r3] @ movhi 217:Src/main.c **** if (temp16==0) 7381 .loc 2 217 6 is_stmt 1 view .LVU2397 217:Src/main.c **** if (temp16==0) 7382 .loc 2 217 19 is_stmt 0 view .LVU2398 7383 01c4 234A ldr r2, .L359+48 7384 01c6 1378 ldrb r3, [r2] @ zero_extendqisi2 7385 01c8 0343 orrs r3, r3, r0 ARM GAS /tmp/ccdsDELB.s page 495 7386 01ca 1370 strb r3, [r2] 218:Src/main.c **** { 7387 .loc 2 218 6 is_stmt 1 view .LVU2399 218:Src/main.c **** { 7388 .loc 2 218 9 is_stmt 0 view .LVU2400 7389 01cc 40B9 cbnz r0, .L320 220:Src/main.c **** } 7390 .loc 2 220 7 is_stmt 1 view .LVU2401 220:Src/main.c **** } 7391 .loc 2 220 33 is_stmt 0 view .LVU2402 7392 01ce 1B4B ldr r3, .L359+24 7393 01d0 0322 movs r2, #3 7394 01d2 1A70 strb r2, [r3] 7395 .L321: 226:Src/main.c **** CPU_state = CPU_state_old;//Return to main current cycle 7396 .loc 2 226 6 is_stmt 1 view .LVU2403 226:Src/main.c **** CPU_state = CPU_state_old;//Return to main current cycle 7397 .loc 2 226 20 is_stmt 0 view .LVU2404 7398 01d4 0023 movs r3, #0 7399 01d6 174A ldr r2, .L359+16 7400 01d8 1370 strb r3, [r2] 227:Src/main.c **** break; 7401 .loc 2 227 6 is_stmt 1 view .LVU2405 227:Src/main.c **** break; 7402 .loc 2 227 16 is_stmt 0 view .LVU2406 7403 01da 1B4A ldr r2, .L359+36 7404 01dc 1370 strb r3, [r2] 228:Src/main.c **** case TRANS_ENABLE://4 - Transmith current packet 7405 .loc 2 228 5 is_stmt 1 view .LVU2407 7406 01de 68E7 b .L306 7407 .L320: 224:Src/main.c **** } 7408 .loc 2 224 7 view .LVU2408 224:Src/main.c **** } 7409 .loc 2 224 33 is_stmt 0 view .LVU2409 7410 01e0 164B ldr r3, .L359+24 7411 01e2 0122 movs r2, #1 7412 01e4 1A70 strb r2, [r3] 7413 01e6 F5E7 b .L321 7414 .L313: 230:Src/main.c **** CPU_state = CPU_state_old;//Return to main current cycle 7415 .loc 2 230 6 is_stmt 1 view .LVU2410 230:Src/main.c **** CPU_state = CPU_state_old;//Return to main current cycle 7416 .loc 2 230 32 is_stmt 0 view .LVU2411 7417 01e8 144B ldr r3, .L359+24 7418 01ea 0222 movs r2, #2 7419 01ec 1A70 strb r2, [r3] 231:Src/main.c **** break; 7420 .loc 2 231 6 is_stmt 1 view .LVU2412 231:Src/main.c **** break; 7421 .loc 2 231 16 is_stmt 0 view .LVU2413 7422 01ee 114B ldr r3, .L359+16 7423 01f0 1A78 ldrb r2, [r3] @ zero_extendqisi2 7424 01f2 154B ldr r3, .L359+36 7425 01f4 1A70 strb r2, [r3] 232:Src/main.c **** case REMOVE_FILE://5 - Remove file from SD 7426 .loc 2 232 5 is_stmt 1 view .LVU2414 ARM GAS /tmp/ccdsDELB.s page 496 7427 01f6 5CE7 b .L306 7428 .L312: 234:Src/main.c **** UART_transmission_request = MESS_01; 7429 .loc 2 234 6 view .LVU2415 234:Src/main.c **** UART_transmission_request = MESS_01; 7430 .loc 2 234 21 is_stmt 0 view .LVU2416 7431 01f8 FFF7FEFF bl SD_REMOVE 7432 .LVL564: 234:Src/main.c **** UART_transmission_request = MESS_01; 7433 .loc 2 234 19 view .LVU2417 7434 01fc 154A ldr r2, .L359+48 7435 01fe 1378 ldrb r3, [r2] @ zero_extendqisi2 7436 0200 0343 orrs r3, r3, r0 7437 0202 1370 strb r3, [r2] 235:Src/main.c **** CPU_state = CPU_state_old; 7438 .loc 2 235 6 is_stmt 1 view .LVU2418 235:Src/main.c **** CPU_state = CPU_state_old; 7439 .loc 2 235 32 is_stmt 0 view .LVU2419 7440 0204 0D4B ldr r3, .L359+24 7441 0206 0122 movs r2, #1 7442 0208 1A70 strb r2, [r3] 236:Src/main.c **** break; 7443 .loc 2 236 6 is_stmt 1 view .LVU2420 236:Src/main.c **** break; 7444 .loc 2 236 16 is_stmt 0 view .LVU2421 7445 020a 0A4B ldr r3, .L359+16 7446 020c 1A78 ldrb r2, [r3] @ zero_extendqisi2 7447 020e 0E4B ldr r3, .L359+36 7448 0210 1A70 strb r2, [r3] 237:Src/main.c **** case STATE://6 - Transmith state message 7449 .loc 2 237 5 is_stmt 1 view .LVU2422 7450 0212 4EE7 b .L306 7451 .L311: 239:Src/main.c **** CPU_state = CPU_state_old;//Return to main current cycle 7452 .loc 2 239 6 view .LVU2423 239:Src/main.c **** CPU_state = CPU_state_old;//Return to main current cycle 7453 .loc 2 239 32 is_stmt 0 view .LVU2424 7454 0214 094B ldr r3, .L359+24 7455 0216 0122 movs r2, #1 7456 0218 1A70 strb r2, [r3] 240:Src/main.c **** break; 7457 .loc 2 240 6 is_stmt 1 view .LVU2425 240:Src/main.c **** break; 7458 .loc 2 240 16 is_stmt 0 view .LVU2426 7459 021a 064B ldr r3, .L359+16 7460 021c 1A78 ldrb r2, [r3] @ zero_extendqisi2 7461 021e 0A4B ldr r3, .L359+36 7462 0220 1A70 strb r2, [r3] 241:Src/main.c **** case WORK_ENABLE://7 - Main work cycle 7463 .loc 2 241 5 is_stmt 1 view .LVU2427 7464 0222 46E7 b .L306 7465 .L360: 7466 .align 2 7467 .L359: 7468 0224 00000000 .word .LANCHOR16 7469 0228 00100140 .word 1073811456 7470 022c 08100140 .word 1073811464 ARM GAS /tmp/ccdsDELB.s page 497 7471 0230 00E100E0 .word -536813312 7472 0234 00000000 .word .LANCHOR35 7473 0238 00000000 .word .LANCHOR1 7474 023c 00000000 .word .LANCHOR37 7475 0240 00000000 .word .LANCHOR11 7476 0244 00000240 .word 1073872896 7477 0248 00000000 .word .LANCHOR27 7478 024c 00000000 .word .LANCHOR26 7479 0250 00000000 .word .LANCHOR34 7480 0254 00000000 .word .LANCHOR36 7481 0258 00380040 .word 1073756160 7482 025c 00000000 .word .LANCHOR20 7483 0260 00000000 .word .LANCHOR22 7484 0264 00000000 .word .LANCHOR21 7485 0268 00000000 .word .LANCHOR7 7486 026c 00000000 .word .LANCHOR9 7487 0270 00000000 .word .LANCHOR6 7488 0274 00000000 .word .LANCHOR38 7489 .L310: 243:Src/main.c **** Stop_TIM10(); 7490 .loc 2 243 6 view .LVU2428 243:Src/main.c **** Stop_TIM10(); 7491 .loc 2 243 31 is_stmt 0 view .LVU2429 7492 0278 AC4B ldr r3, .L361 7493 027a 5A68 ldr r2, [r3, #4] @ float 243:Src/main.c **** Stop_TIM10(); 7494 .loc 2 243 25 view .LVU2430 7495 027c 1A61 str r2, [r3, #16] @ float 244:Src/main.c **** if (TO7>TO7_before)//Main work cycle go with the timer 7 (1000 us or 1 kHz) 7496 .loc 2 244 6 is_stmt 1 view .LVU2431 7497 027e FFF7FEFF bl Stop_TIM10 7498 .LVL565: 245:Src/main.c **** { 7499 .loc 2 245 6 view .LVU2432 245:Src/main.c **** { 7500 .loc 2 245 13 is_stmt 0 view .LVU2433 7501 0282 AB4B ldr r3, .L361+4 7502 0284 1B68 ldr r3, [r3] 7503 0286 AB4A ldr r2, .L361+8 7504 0288 1268 ldr r2, [r2] 245:Src/main.c **** { 7505 .loc 2 245 9 view .LVU2434 7506 028a 9342 cmp r3, r2 7507 028c 7FF611AF bls .L306 247:Src/main.c **** LD1_param.POWER = MPhD_T(1);//Get Data from monitor photodiode of LD1 7508 .loc 2 247 7 is_stmt 1 view .LVU2435 247:Src/main.c **** LD1_param.POWER = MPhD_T(1);//Get Data from monitor photodiode of LD1 7509 .loc 2 247 18 is_stmt 0 view .LVU2436 7510 0290 A84A ldr r2, .L361+8 7511 0292 1360 str r3, [r2] 248:Src/main.c **** LD1_param.POWER = MPhD_T(1);//Get Data from monitor photodiode of LD1 7512 .loc 2 248 7 is_stmt 1 view .LVU2437 248:Src/main.c **** LD1_param.POWER = MPhD_T(1);//Get Data from monitor photodiode of LD1 7513 .loc 2 248 25 is_stmt 0 view .LVU2438 7514 0294 0120 movs r0, #1 7515 0296 FFF7FEFF bl MPhD_T 7516 .LVL566: ARM GAS /tmp/ccdsDELB.s page 498 248:Src/main.c **** LD1_param.POWER = MPhD_T(1);//Get Data from monitor photodiode of LD1 7517 .loc 2 248 23 view .LVU2439 7518 029a A74F ldr r7, .L361+12 7519 029c 3881 strh r0, [r7, #8] @ movhi 249:Src/main.c **** LD2_param.POWER = MPhD_T(2);//Get Data from monitor photodiode of LD2 7520 .loc 2 249 7 is_stmt 1 view .LVU2440 249:Src/main.c **** LD2_param.POWER = MPhD_T(2);//Get Data from monitor photodiode of LD2 7521 .loc 2 249 25 is_stmt 0 view .LVU2441 7522 029e 0120 movs r0, #1 7523 02a0 FFF7FEFF bl MPhD_T 7524 .LVL567: 249:Src/main.c **** LD2_param.POWER = MPhD_T(2);//Get Data from monitor photodiode of LD2 7525 .loc 2 249 23 view .LVU2442 7526 02a4 3881 strh r0, [r7, #8] @ movhi 250:Src/main.c **** LD2_param.POWER = MPhD_T(2);//Get Data from monitor photodiode of LD2 7527 .loc 2 250 7 is_stmt 1 view .LVU2443 250:Src/main.c **** LD2_param.POWER = MPhD_T(2);//Get Data from monitor photodiode of LD2 7528 .loc 2 250 25 is_stmt 0 view .LVU2444 7529 02a6 0220 movs r0, #2 7530 02a8 FFF7FEFF bl MPhD_T 7531 .LVL568: 250:Src/main.c **** LD2_param.POWER = MPhD_T(2);//Get Data from monitor photodiode of LD2 7532 .loc 2 250 23 view .LVU2445 7533 02ac A34E ldr r6, .L361+16 7534 02ae 3081 strh r0, [r6, #8] @ movhi 251:Src/main.c **** 7535 .loc 2 251 7 is_stmt 1 view .LVU2446 251:Src/main.c **** 7536 .loc 2 251 25 is_stmt 0 view .LVU2447 7537 02b0 0220 movs r0, #2 7538 02b2 FFF7FEFF bl MPhD_T 7539 .LVL569: 251:Src/main.c **** 7540 .loc 2 251 23 view .LVU2448 7541 02b6 3081 strh r0, [r6, #8] @ movhi 254:Src/main.c **** LD1_param.LD_CURR_TEMP = MPhD_T(3); 7542 .loc 2 254 7 is_stmt 1 view .LVU2449 254:Src/main.c **** LD1_param.LD_CURR_TEMP = MPhD_T(3); 7543 .loc 2 254 14 is_stmt 0 view .LVU2450 7544 02b8 0320 movs r0, #3 7545 02ba FFF7FEFF bl MPhD_T 7546 .LVL570: 255:Src/main.c **** (void) MPhD_T(4); 7547 .loc 2 255 7 is_stmt 1 view .LVU2451 255:Src/main.c **** (void) MPhD_T(4); 7548 .loc 2 255 32 is_stmt 0 view .LVU2452 7549 02be 0320 movs r0, #3 7550 02c0 FFF7FEFF bl MPhD_T 7551 .LVL571: 255:Src/main.c **** (void) MPhD_T(4); 7552 .loc 2 255 30 view .LVU2453 7553 02c4 3880 strh r0, [r7] @ movhi 256:Src/main.c **** LD2_param.LD_CURR_TEMP = MPhD_T(4); 7554 .loc 2 256 7 is_stmt 1 view .LVU2454 256:Src/main.c **** LD2_param.LD_CURR_TEMP = MPhD_T(4); 7555 .loc 2 256 14 is_stmt 0 view .LVU2455 7556 02c6 0420 movs r0, #4 ARM GAS /tmp/ccdsDELB.s page 499 7557 02c8 FFF7FEFF bl MPhD_T 7558 .LVL572: 257:Src/main.c **** temp16=PID_Controller_Temp(&LD1_curr_setup, &LD1_param, 1); 7559 .loc 2 257 7 is_stmt 1 view .LVU2456 257:Src/main.c **** temp16=PID_Controller_Temp(&LD1_curr_setup, &LD1_param, 1); 7560 .loc 2 257 32 is_stmt 0 view .LVU2457 7561 02cc 0420 movs r0, #4 7562 02ce FFF7FEFF bl MPhD_T 7563 .LVL573: 257:Src/main.c **** temp16=PID_Controller_Temp(&LD1_curr_setup, &LD1_param, 1); 7564 .loc 2 257 30 view .LVU2458 7565 02d2 3080 strh r0, [r6] @ movhi 258:Src/main.c **** Set_LTEC(3, temp16);//Drive Laser TEC 1 7566 .loc 2 258 7 is_stmt 1 view .LVU2459 258:Src/main.c **** Set_LTEC(3, temp16);//Drive Laser TEC 1 7567 .loc 2 258 14 is_stmt 0 view .LVU2460 7568 02d4 DFF89882 ldr r8, .L361+68 7569 02d8 0122 movs r2, #1 7570 02da 3946 mov r1, r7 7571 02dc 4046 mov r0, r8 7572 02de FFF7FEFF bl PID_Controller_Temp 7573 .LVL574: 7574 02e2 0146 mov r1, r0 258:Src/main.c **** Set_LTEC(3, temp16);//Drive Laser TEC 1 7575 .loc 2 258 13 view .LVU2461 7576 02e4 964D ldr r5, .L361+20 7577 02e6 2880 strh r0, [r5] @ movhi 259:Src/main.c **** temp16=PID_Controller_Temp(&LD2_curr_setup, &LD2_param, 2); 7578 .loc 2 259 7 is_stmt 1 view .LVU2462 7579 02e8 0320 movs r0, #3 7580 02ea FFF7FEFF bl Set_LTEC 7581 .LVL575: 260:Src/main.c **** Set_LTEC(4, temp16);//Drive Laser TEC 2 7582 .loc 2 260 7 view .LVU2463 260:Src/main.c **** Set_LTEC(4, temp16);//Drive Laser TEC 2 7583 .loc 2 260 14 is_stmt 0 view .LVU2464 7584 02ee DFF87C92 ldr r9, .L361+64 7585 02f2 0222 movs r2, #2 7586 02f4 3146 mov r1, r6 7587 02f6 4846 mov r0, r9 7588 02f8 FFF7FEFF bl PID_Controller_Temp 7589 .LVL576: 7590 02fc 0146 mov r1, r0 260:Src/main.c **** Set_LTEC(4, temp16);//Drive Laser TEC 2 7591 .loc 2 260 13 view .LVU2465 7592 02fe 2880 strh r0, [r5] @ movhi 261:Src/main.c **** 7593 .loc 2 261 7 is_stmt 1 view .LVU2466 7594 0300 0420 movs r0, #4 7595 0302 FFF7FEFF bl Set_LTEC 7596 .LVL577: 263:Src/main.c **** Long_Data[2] = LD2_param.POWER;//Translate Data from monitor photodiode of LD2 to Long_Data 7597 .loc 2 263 7 view .LVU2467 263:Src/main.c **** Long_Data[2] = LD2_param.POWER;//Translate Data from monitor photodiode of LD2 to Long_Data 7598 .loc 2 263 31 is_stmt 0 view .LVU2468 7599 0306 3B89 ldrh r3, [r7, #8] 263:Src/main.c **** Long_Data[2] = LD2_param.POWER;//Translate Data from monitor photodiode of LD2 to Long_Data ARM GAS /tmp/ccdsDELB.s page 500 7600 .loc 2 263 20 view .LVU2469 7601 0308 8E4C ldr r4, .L361+24 7602 030a 6380 strh r3, [r4, #2] @ movhi 264:Src/main.c **** 7603 .loc 2 264 7 is_stmt 1 view .LVU2470 264:Src/main.c **** 7604 .loc 2 264 31 is_stmt 0 view .LVU2471 7605 030c 3389 ldrh r3, [r6, #8] 264:Src/main.c **** 7606 .loc 2 264 20 view .LVU2472 7607 030e A380 strh r3, [r4, #4] @ movhi 266:Src/main.c **** Set_LTEC(2,LD2_curr_setup.CURRENT);//Drive Laser diode 2 7608 .loc 2 266 7 is_stmt 1 view .LVU2473 7609 0310 B8F80C10 ldrh r1, [r8, #12] 7610 0314 0120 movs r0, #1 7611 0316 FFF7FEFF bl Set_LTEC 7612 .LVL578: 267:Src/main.c **** 7613 .loc 2 267 7 view .LVU2474 7614 031a B9F80C10 ldrh r1, [r9, #12] 7615 031e 0220 movs r0, #2 7616 0320 FFF7FEFF bl Set_LTEC 7617 .LVL579: 271:Src/main.c **** temp16 = Get_ADC(1); 7618 .loc 2 271 7 view .LVU2475 271:Src/main.c **** temp16 = Get_ADC(1); 7619 .loc 2 271 16 is_stmt 0 view .LVU2476 7620 0324 0020 movs r0, #0 7621 0326 FFF7FEFF bl Get_ADC 7622 .LVL580: 271:Src/main.c **** temp16 = Get_ADC(1); 7623 .loc 2 271 14 view .LVU2477 7624 032a 2880 strh r0, [r5] @ movhi 272:Src/main.c **** Long_Data[7] = temp16; 7625 .loc 2 272 7 is_stmt 1 view .LVU2478 272:Src/main.c **** Long_Data[7] = temp16; 7626 .loc 2 272 16 is_stmt 0 view .LVU2479 7627 032c 0120 movs r0, #1 7628 032e FFF7FEFF bl Get_ADC 7629 .LVL581: 272:Src/main.c **** Long_Data[7] = temp16; 7630 .loc 2 272 14 view .LVU2480 7631 0332 2880 strh r0, [r5] @ movhi 273:Src/main.c **** 7632 .loc 2 273 7 is_stmt 1 view .LVU2481 273:Src/main.c **** 7633 .loc 2 273 20 is_stmt 0 view .LVU2482 7634 0334 E081 strh r0, [r4, #14] @ movhi 276:Src/main.c **** Long_Data[8] = temp16; 7635 .loc 2 276 7 is_stmt 1 view .LVU2483 276:Src/main.c **** Long_Data[8] = temp16; 7636 .loc 2 276 16 is_stmt 0 view .LVU2484 7637 0336 0120 movs r0, #1 7638 0338 FFF7FEFF bl Get_ADC 7639 .LVL582: 276:Src/main.c **** Long_Data[8] = temp16; 7640 .loc 2 276 14 view .LVU2485 ARM GAS /tmp/ccdsDELB.s page 501 7641 033c 2880 strh r0, [r5] @ movhi 277:Src/main.c **** 7642 .loc 2 277 7 is_stmt 1 view .LVU2486 277:Src/main.c **** 7643 .loc 2 277 20 is_stmt 0 view .LVU2487 7644 033e 2082 strh r0, [r4, #16] @ movhi 280:Src/main.c **** Long_Data[9] = temp16; 7645 .loc 2 280 7 is_stmt 1 view .LVU2488 280:Src/main.c **** Long_Data[9] = temp16; 7646 .loc 2 280 16 is_stmt 0 view .LVU2489 7647 0340 0120 movs r0, #1 7648 0342 FFF7FEFF bl Get_ADC 7649 .LVL583: 280:Src/main.c **** Long_Data[9] = temp16; 7650 .loc 2 280 14 view .LVU2490 7651 0346 2880 strh r0, [r5] @ movhi 281:Src/main.c **** 7652 .loc 2 281 7 is_stmt 1 view .LVU2491 281:Src/main.c **** 7653 .loc 2 281 20 is_stmt 0 view .LVU2492 7654 0348 6082 strh r0, [r4, #18] @ movhi 284:Src/main.c **** Long_Data[10] = temp16; 7655 .loc 2 284 7 is_stmt 1 view .LVU2493 284:Src/main.c **** Long_Data[10] = temp16; 7656 .loc 2 284 16 is_stmt 0 view .LVU2494 7657 034a 0120 movs r0, #1 7658 034c FFF7FEFF bl Get_ADC 7659 .LVL584: 284:Src/main.c **** Long_Data[10] = temp16; 7660 .loc 2 284 14 view .LVU2495 7661 0350 2880 strh r0, [r5] @ movhi 285:Src/main.c **** 7662 .loc 2 285 7 is_stmt 1 view .LVU2496 285:Src/main.c **** 7663 .loc 2 285 21 is_stmt 0 view .LVU2497 7664 0352 A082 strh r0, [r4, #20] @ movhi 288:Src/main.c **** Long_Data[11] = temp16; 7665 .loc 2 288 7 is_stmt 1 view .LVU2498 288:Src/main.c **** Long_Data[11] = temp16; 7666 .loc 2 288 16 is_stmt 0 view .LVU2499 7667 0354 0120 movs r0, #1 7668 0356 FFF7FEFF bl Get_ADC 7669 .LVL585: 288:Src/main.c **** Long_Data[11] = temp16; 7670 .loc 2 288 14 view .LVU2500 7671 035a 2880 strh r0, [r5] @ movhi 289:Src/main.c **** temp16 = Get_ADC(2); 7672 .loc 2 289 7 is_stmt 1 view .LVU2501 289:Src/main.c **** temp16 = Get_ADC(2); 7673 .loc 2 289 21 is_stmt 0 view .LVU2502 7674 035c E082 strh r0, [r4, #22] @ movhi 290:Src/main.c **** 7675 .loc 2 290 7 is_stmt 1 view .LVU2503 290:Src/main.c **** 7676 .loc 2 290 16 is_stmt 0 view .LVU2504 7677 035e 0220 movs r0, #2 7678 0360 FFF7FEFF bl Get_ADC ARM GAS /tmp/ccdsDELB.s page 502 7679 .LVL586: 290:Src/main.c **** 7680 .loc 2 290 14 view .LVU2505 7681 0364 2880 strh r0, [r5] @ movhi 293:Src/main.c **** temp16 = Get_ADC(4); 7682 .loc 2 293 7 is_stmt 1 view .LVU2506 293:Src/main.c **** temp16 = Get_ADC(4); 7683 .loc 2 293 16 is_stmt 0 view .LVU2507 7684 0366 0320 movs r0, #3 7685 0368 FFF7FEFF bl Get_ADC 7686 .LVL587: 293:Src/main.c **** temp16 = Get_ADC(4); 7687 .loc 2 293 14 view .LVU2508 7688 036c 2880 strh r0, [r5] @ movhi 294:Src/main.c **** Long_Data[12] = temp16; 7689 .loc 2 294 7 is_stmt 1 view .LVU2509 294:Src/main.c **** Long_Data[12] = temp16; 7690 .loc 2 294 16 is_stmt 0 view .LVU2510 7691 036e 0420 movs r0, #4 7692 0370 FFF7FEFF bl Get_ADC 7693 .LVL588: 294:Src/main.c **** Long_Data[12] = temp16; 7694 .loc 2 294 14 view .LVU2511 7695 0374 2880 strh r0, [r5] @ movhi 295:Src/main.c **** temp16 = Get_ADC(5); 7696 .loc 2 295 7 is_stmt 1 view .LVU2512 295:Src/main.c **** temp16 = Get_ADC(5); 7697 .loc 2 295 21 is_stmt 0 view .LVU2513 7698 0376 2083 strh r0, [r4, #24] @ movhi 296:Src/main.c **** 7699 .loc 2 296 7 is_stmt 1 view .LVU2514 296:Src/main.c **** 7700 .loc 2 296 16 is_stmt 0 view .LVU2515 7701 0378 0520 movs r0, #5 7702 037a FFF7FEFF bl Get_ADC 7703 .LVL589: 296:Src/main.c **** 7704 .loc 2 296 14 view .LVU2516 7705 037e 2880 strh r0, [r5] @ movhi 299:Src/main.c **** Long_Data[3] = (TO6_stop)&0xffff; 7706 .loc 2 299 7 is_stmt 1 view .LVU2517 299:Src/main.c **** Long_Data[3] = (TO6_stop)&0xffff; 7707 .loc 2 299 16 is_stmt 0 view .LVU2518 7708 0380 714B ldr r3, .L361+28 7709 0382 1B68 ldr r3, [r3] 7710 0384 714A ldr r2, .L361+32 7711 0386 1360 str r3, [r2] 300:Src/main.c **** Long_Data[4] = (TO6_stop>>16)&0xffff; 7712 .loc 2 300 7 is_stmt 1 view .LVU2519 300:Src/main.c **** Long_Data[4] = (TO6_stop>>16)&0xffff; 7713 .loc 2 300 20 is_stmt 0 view .LVU2520 7714 0388 E380 strh r3, [r4, #6] @ movhi 301:Src/main.c **** 7715 .loc 2 301 7 is_stmt 1 view .LVU2521 301:Src/main.c **** 7716 .loc 2 301 31 is_stmt 0 view .LVU2522 7717 038a 1B0C lsrs r3, r3, #16 ARM GAS /tmp/ccdsDELB.s page 503 301:Src/main.c **** 7718 .loc 2 301 20 view .LVU2523 7719 038c 2381 strh r3, [r4, #8] @ movhi 304:Src/main.c **** 7720 .loc 2 304 7 is_stmt 1 view .LVU2524 304:Src/main.c **** 7721 .loc 2 304 31 is_stmt 0 view .LVU2525 7722 038e 3B88 ldrh r3, [r7] 304:Src/main.c **** 7723 .loc 2 304 20 view .LVU2526 7724 0390 6381 strh r3, [r4, #10] @ movhi 307:Src/main.c **** 7725 .loc 2 307 7 is_stmt 1 view .LVU2527 307:Src/main.c **** 7726 .loc 2 307 31 is_stmt 0 view .LVU2528 7727 0392 3388 ldrh r3, [r6] 307:Src/main.c **** 7728 .loc 2 307 20 view .LVU2529 7729 0394 A381 strh r3, [r4, #12] @ movhi 309:Src/main.c **** { 7730 .loc 2 309 7 is_stmt 1 view .LVU2530 309:Src/main.c **** { 7731 .loc 2 309 21 is_stmt 0 view .LVU2531 7732 0396 6E4B ldr r3, .L361+36 7733 0398 DB7A ldrb r3, [r3, #11] @ zero_extendqisi2 309:Src/main.c **** { 7734 .loc 2 309 10 view .LVU2532 7735 039a 012B cmp r3, #1 7736 039c 03D0 beq .L354 7737 .L322: 316:Src/main.c **** } 7738 .loc 2 316 7 is_stmt 1 view .LVU2533 316:Src/main.c **** } 7739 .loc 2 316 21 is_stmt 0 view .LVU2534 7740 039e 6D4B ldr r3, .L361+40 7741 03a0 0722 movs r2, #7 7742 03a2 1A70 strb r2, [r3] 7743 03a4 85E6 b .L306 7744 .L354: 311:Src/main.c **** Long_Data[DL_16-1] = CS_result; 7745 .loc 2 311 8 is_stmt 1 view .LVU2535 311:Src/main.c **** Long_Data[DL_16-1] = CS_result; 7746 .loc 2 311 20 is_stmt 0 view .LVU2536 7747 03a6 0D21 movs r1, #13 7748 03a8 A01C adds r0, r4, #2 7749 03aa FFF7FEFF bl CalculateChecksum 7750 .LVL590: 311:Src/main.c **** Long_Data[DL_16-1] = CS_result; 7751 .loc 2 311 18 view .LVU2537 7752 03ae 6A4A ldr r2, .L361+44 7753 03b0 1080 strh r0, [r2] @ movhi 312:Src/main.c **** temp16 = SD_SAVE(&Long_Data[0]); 7754 .loc 2 312 8 is_stmt 1 view .LVU2538 312:Src/main.c **** temp16 = SD_SAVE(&Long_Data[0]); 7755 .loc 2 312 27 is_stmt 0 view .LVU2539 7756 03b2 A083 strh r0, [r4, #28] @ movhi 313:Src/main.c **** State_Data[0]|=temp16&0xff; ARM GAS /tmp/ccdsDELB.s page 504 7757 .loc 2 313 8 is_stmt 1 view .LVU2540 313:Src/main.c **** State_Data[0]|=temp16&0xff; 7758 .loc 2 313 17 is_stmt 0 view .LVU2541 7759 03b4 2046 mov r0, r4 7760 03b6 FFF7FEFF bl SD_SAVE 7761 .LVL591: 313:Src/main.c **** State_Data[0]|=temp16&0xff; 7762 .loc 2 313 15 view .LVU2542 7763 03ba 83B2 uxth r3, r0 7764 03bc 2B80 strh r3, [r5] @ movhi 314:Src/main.c **** } 7765 .loc 2 314 8 is_stmt 1 view .LVU2543 314:Src/main.c **** } 7766 .loc 2 314 21 is_stmt 0 view .LVU2544 7767 03be 6749 ldr r1, .L361+48 7768 03c0 0A78 ldrb r2, [r1] @ zero_extendqisi2 7769 03c2 1343 orrs r3, r3, r2 7770 03c4 0B70 strb r3, [r1] 7771 03c6 EAE7 b .L322 7772 .L309: 320:Src/main.c **** { 7773 .loc 2 320 6 is_stmt 1 view .LVU2545 320:Src/main.c **** { 7774 .loc 2 320 10 is_stmt 0 view .LVU2546 7775 03c8 6548 ldr r0, .L361+52 7776 03ca FFF7FEFF bl CheckChecksum 7777 .LVL592: 320:Src/main.c **** { 7778 .loc 2 320 9 view .LVU2547 7779 03ce 70B9 cbnz r0, .L355 329:Src/main.c **** CPU_state = DEFAULT_ENABLE; 7780 .loc 2 329 7 is_stmt 1 view .LVU2548 329:Src/main.c **** CPU_state = DEFAULT_ENABLE; 7781 .loc 2 329 21 is_stmt 0 view .LVU2549 7782 03d0 624A ldr r2, .L361+48 7783 03d2 1378 ldrb r3, [r2] @ zero_extendqisi2 7784 03d4 43F00403 orr r3, r3, #4 7785 03d8 1370 strb r3, [r2] 330:Src/main.c **** CPU_state_old = HALT;//Save main current cycle 7786 .loc 2 330 7 is_stmt 1 view .LVU2550 330:Src/main.c **** CPU_state_old = HALT;//Save main current cycle 7787 .loc 2 330 17 is_stmt 0 view .LVU2551 7788 03da 624B ldr r3, .L361+56 7789 03dc 0222 movs r2, #2 7790 03de 1A70 strb r2, [r3] 331:Src/main.c **** } 7791 .loc 2 331 7 is_stmt 1 view .LVU2552 331:Src/main.c **** } 7792 .loc 2 331 21 is_stmt 0 view .LVU2553 7793 03e0 5C4B ldr r3, .L361+40 7794 03e2 0022 movs r2, #0 7795 03e4 1A70 strb r2, [r3] 7796 .L324: 333:Src/main.c **** break; 7797 .loc 2 333 6 is_stmt 1 view .LVU2554 333:Src/main.c **** break; 7798 .loc 2 333 32 is_stmt 0 view .LVU2555 ARM GAS /tmp/ccdsDELB.s page 505 7799 03e6 604B ldr r3, .L361+60 7800 03e8 0122 movs r2, #1 7801 03ea 1A70 strb r2, [r3] 334:Src/main.c **** case RUN_TASK: 7802 .loc 2 334 5 is_stmt 1 view .LVU2556 7803 03ec 61E6 b .L306 7804 .L355: 322:Src/main.c **** TO6_before = TO6; 7805 .loc 2 322 7 view .LVU2557 7806 03ee 584B ldr r3, .L361+36 7807 03f0 5E4A ldr r2, .L361+64 7808 03f2 5F49 ldr r1, .L361+68 7809 03f4 5A48 ldr r0, .L361+52 7810 03f6 FFF7FEFF bl Decode_task 7811 .LVL593: 323:Src/main.c **** CPU_state = RUN_TASK; 7812 .loc 2 323 7 view .LVU2558 323:Src/main.c **** CPU_state = RUN_TASK; 7813 .loc 2 323 18 is_stmt 0 view .LVU2559 7814 03fa 534B ldr r3, .L361+28 7815 03fc 1A68 ldr r2, [r3] 7816 03fe 5D4B ldr r3, .L361+72 7817 0400 1A60 str r2, [r3] 324:Src/main.c **** CPU_state_old = RUN_TASK;//Save main current cycle 7818 .loc 2 324 7 is_stmt 1 view .LVU2560 324:Src/main.c **** CPU_state_old = RUN_TASK;//Save main current cycle 7819 .loc 2 324 17 is_stmt 0 view .LVU2561 7820 0402 0923 movs r3, #9 7821 0404 574A ldr r2, .L361+56 7822 0406 1370 strb r3, [r2] 325:Src/main.c **** } 7823 .loc 2 325 7 is_stmt 1 view .LVU2562 325:Src/main.c **** } 7824 .loc 2 325 21 is_stmt 0 view .LVU2563 7825 0408 524A ldr r2, .L361+40 7826 040a 1370 strb r3, [r2] 7827 040c EBE7 b .L324 7828 .L307: 336:Src/main.c **** { 7829 .loc 2 336 6 is_stmt 1 view .LVU2564 336:Src/main.c **** { 7830 .loc 2 336 18 is_stmt 0 view .LVU2565 7831 040e 474B ldr r3, .L361 7832 0410 1B78 ldrb r3, [r3] @ zero_extendqisi2 7833 0412 012B cmp r3, #1 7834 0414 24D0 beq .L325 7835 0416 022B cmp r3, #2 7836 0418 00F0DF80 beq .L326 7837 .L327: 424:Src/main.c **** { 7838 .loc 2 424 6 is_stmt 1 view .LVU2566 424:Src/main.c **** { 7839 .loc 2 424 13 is_stmt 0 view .LVU2567 7840 041c 444B ldr r3, .L361+4 7841 041e 1B68 ldr r3, [r3] 7842 0420 444A ldr r2, .L361+8 7843 0422 1268 ldr r2, [r2] ARM GAS /tmp/ccdsDELB.s page 506 424:Src/main.c **** { 7844 .loc 2 424 9 view .LVU2568 7845 0424 9342 cmp r3, r2 7846 0426 00F26081 bhi .L356 7847 .L339: 476:Src/main.c **** 7848 .loc 2 476 27 is_stmt 1 discriminator 1 view .LVU2569 476:Src/main.c **** 7849 .loc 2 476 12 discriminator 1 view .LVU2570 476:Src/main.c **** 7850 .loc 2 476 13 is_stmt 0 discriminator 1 view .LVU2571 7851 042a 534B ldr r3, .L361+76 7852 042c 1B78 ldrb r3, [r3] @ zero_extendqisi2 476:Src/main.c **** 7853 .loc 2 476 12 discriminator 1 view .LVU2572 7854 042e 002B cmp r3, #0 7855 0430 FBD0 beq .L339 478:Src/main.c **** 7856 .loc 2 478 6 is_stmt 1 view .LVU2573 7857 0432 FFF7FEFF bl Stop_TIM10 7858 .LVL594: 480:Src/main.c **** { 7859 .loc 2 480 6 view .LVU2574 480:Src/main.c **** { 7860 .loc 2 480 14 is_stmt 0 view .LVU2575 7861 0436 3D4B ldr r3, .L361 7862 0438 DB8A ldrh r3, [r3, #22] 480:Src/main.c **** { 7863 .loc 2 480 9 view .LVU2576 7864 043a 032B cmp r3, #3 7865 043c 0CD9 bls .L340 482:Src/main.c **** TO10_counter = task.dt / 10 - 1; 7866 .loc 2 482 7 is_stmt 1 view .LVU2577 482:Src/main.c **** TO10_counter = task.dt / 10 - 1; 7867 .loc 2 482 26 is_stmt 0 view .LVU2578 7868 043e 4F4B ldr r3, .L361+80 7869 0440 1A68 ldr r2, [r3] 7870 0442 4F4B ldr r3, .L361+84 7871 0444 DA60 str r2, [r3, #12] 483:Src/main.c **** } 7872 .loc 2 483 7 is_stmt 1 view .LVU2579 483:Src/main.c **** } 7873 .loc 2 483 26 is_stmt 0 view .LVU2580 7874 0446 394B ldr r3, .L361 7875 0448 1B7D ldrb r3, [r3, #20] @ zero_extendqisi2 483:Src/main.c **** } 7876 .loc 2 483 30 view .LVU2581 7877 044a 4E4A ldr r2, .L361+88 7878 044c A2FB0323 umull r2, r3, r2, r3 7879 0450 DB08 lsrs r3, r3, #3 483:Src/main.c **** } 7880 .loc 2 483 35 view .LVU2582 7881 0452 013B subs r3, r3, #1 483:Src/main.c **** } 7882 .loc 2 483 20 view .LVU2583 7883 0454 4C4A ldr r2, .L361+92 7884 0456 1360 str r3, [r2] ARM GAS /tmp/ccdsDELB.s page 507 7885 .L340: 486:Src/main.c **** break; 7886 .loc 2 486 6 is_stmt 1 view .LVU2584 486:Src/main.c **** break; 7887 .loc 2 486 20 is_stmt 0 view .LVU2585 7888 0458 3E4B ldr r3, .L361+40 7889 045a 0922 movs r2, #9 7890 045c 1A70 strb r2, [r3] 487:Src/main.c **** } 7891 .loc 2 487 9 is_stmt 1 view .LVU2586 7892 045e 28E6 b .L306 7893 .L325: 339:Src/main.c **** (void) MPhD_T(TT_CHANGE_TEMP_1); 7894 .loc 2 339 7 view .LVU2587 339:Src/main.c **** (void) MPhD_T(TT_CHANGE_TEMP_1); 7895 .loc 2 339 38 is_stmt 0 view .LVU2588 7896 0460 324B ldr r3, .L361 7897 0462 D3ED077A vldr.32 s15, [r3, #28] 339:Src/main.c **** (void) MPhD_T(TT_CHANGE_TEMP_1); 7898 .loc 2 339 7 view .LVU2589 7899 0466 FCEEE77A vcvt.u32.f32 s15, s15 7900 046a 17EE903A vmov r3, s15 @ int 7901 046e 99B2 uxth r1, r3 7902 0470 0220 movs r0, #2 7903 0472 FFF7FEFF bl Set_LTEC 7904 .LVL595: 340:Src/main.c **** LD1_param.LD_CURR_TEMP = MPhD_T(TT_CHANGE_TEMP_1); 7905 .loc 2 340 7 is_stmt 1 view .LVU2590 340:Src/main.c **** LD1_param.LD_CURR_TEMP = MPhD_T(TT_CHANGE_TEMP_1); 7906 .loc 2 340 14 is_stmt 0 view .LVU2591 7907 0476 0320 movs r0, #3 7908 0478 FFF7FEFF bl MPhD_T 7909 .LVL596: 341:Src/main.c **** (void) MPhD_T(TT_CHANGE_TEMP_2); 7910 .loc 2 341 7 is_stmt 1 view .LVU2592 341:Src/main.c **** (void) MPhD_T(TT_CHANGE_TEMP_2); 7911 .loc 2 341 32 is_stmt 0 view .LVU2593 7912 047c 0320 movs r0, #3 7913 047e FFF7FEFF bl MPhD_T 7914 .LVL597: 341:Src/main.c **** (void) MPhD_T(TT_CHANGE_TEMP_2); 7915 .loc 2 341 30 view .LVU2594 7916 0482 2D4C ldr r4, .L361+12 7917 0484 2080 strh r0, [r4] @ movhi 342:Src/main.c **** LD2_param.LD_CURR_TEMP = MPhD_T(TT_CHANGE_TEMP_2); 7918 .loc 2 342 7 is_stmt 1 view .LVU2595 342:Src/main.c **** LD2_param.LD_CURR_TEMP = MPhD_T(TT_CHANGE_TEMP_2); 7919 .loc 2 342 14 is_stmt 0 view .LVU2596 7920 0486 0420 movs r0, #4 7921 0488 FFF7FEFF bl MPhD_T 7922 .LVL598: 343:Src/main.c **** temp16=PID_Controller_Temp(&LD1_curr_setup, &LD1_param, 1); 7923 .loc 2 343 7 is_stmt 1 view .LVU2597 343:Src/main.c **** temp16=PID_Controller_Temp(&LD1_curr_setup, &LD1_param, 1); 7924 .loc 2 343 32 is_stmt 0 view .LVU2598 7925 048c 0420 movs r0, #4 7926 048e FFF7FEFF bl MPhD_T ARM GAS /tmp/ccdsDELB.s page 508 7927 .LVL599: 343:Src/main.c **** temp16=PID_Controller_Temp(&LD1_curr_setup, &LD1_param, 1); 7928 .loc 2 343 30 view .LVU2599 7929 0492 2A4D ldr r5, .L361+16 7930 0494 2880 strh r0, [r5] @ movhi 344:Src/main.c **** Set_LTEC(TT_CHANGE_TEMP_1, temp16);//Drive Laser TEC 1 7931 .loc 2 344 7 is_stmt 1 view .LVU2600 344:Src/main.c **** Set_LTEC(TT_CHANGE_TEMP_1, temp16);//Drive Laser TEC 1 7932 .loc 2 344 14 is_stmt 0 view .LVU2601 7933 0496 0122 movs r2, #1 7934 0498 2146 mov r1, r4 7935 049a 3548 ldr r0, .L361+68 7936 049c FFF7FEFF bl PID_Controller_Temp 7937 .LVL600: 7938 04a0 0146 mov r1, r0 344:Src/main.c **** Set_LTEC(TT_CHANGE_TEMP_1, temp16);//Drive Laser TEC 1 7939 .loc 2 344 13 view .LVU2602 7940 04a2 274C ldr r4, .L361+20 7941 04a4 2080 strh r0, [r4] @ movhi 345:Src/main.c **** temp16=PID_Controller_Temp(&LD2_curr_setup, &LD2_param, 2); 7942 .loc 2 345 7 is_stmt 1 view .LVU2603 7943 04a6 0320 movs r0, #3 7944 04a8 FFF7FEFF bl Set_LTEC 7945 .LVL601: 346:Src/main.c **** Set_LTEC(TT_CHANGE_TEMP_2, temp16);//Drive Laser TEC 2 7946 .loc 2 346 7 view .LVU2604 346:Src/main.c **** Set_LTEC(TT_CHANGE_TEMP_2, temp16);//Drive Laser TEC 2 7947 .loc 2 346 14 is_stmt 0 view .LVU2605 7948 04ac 0222 movs r2, #2 7949 04ae 2946 mov r1, r5 7950 04b0 2E48 ldr r0, .L361+64 7951 04b2 FFF7FEFF bl PID_Controller_Temp 7952 .LVL602: 7953 04b6 0146 mov r1, r0 346:Src/main.c **** Set_LTEC(TT_CHANGE_TEMP_2, temp16);//Drive Laser TEC 2 7954 .loc 2 346 13 view .LVU2606 7955 04b8 2080 strh r0, [r4] @ movhi 347:Src/main.c **** 7956 .loc 2 347 7 is_stmt 1 view .LVU2607 7957 04ba 0420 movs r0, #4 7958 04bc FFF7FEFF bl Set_LTEC 7959 .LVL603: 350:Src/main.c **** HAL_GPIO_WritePin(GPIOD, GPIO_PIN_7, GPIO_PIN_RESET); 7960 .loc 2 350 7 view .LVU2608 7961 04c0 324C ldr r4, .L361+96 7962 04c2 0122 movs r2, #1 7963 04c4 8021 movs r1, #128 7964 04c6 2046 mov r0, r4 7965 04c8 FFF7FEFF bl HAL_GPIO_WritePin 7966 .LVL604: 351:Src/main.c **** 7967 .loc 2 351 7 view .LVU2609 7968 04cc 0022 movs r2, #0 7969 04ce 8021 movs r1, #128 7970 04d0 2046 mov r0, r4 7971 04d2 FFF7FEFF bl HAL_GPIO_WritePin 7972 .LVL605: ARM GAS /tmp/ccdsDELB.s page 509 353:Src/main.c **** if (st != HAL_OK) 7973 .loc 2 353 7 view .LVU2610 353:Src/main.c **** if (st != HAL_OK) 7974 .loc 2 353 12 is_stmt 0 view .LVU2611 7975 04d6 2A48 ldr r0, .L361+84 7976 04d8 FFF7FEFF bl HAL_TIM_Base_Start_IT 7977 .LVL606: 354:Src/main.c **** while(1); 7978 .loc 2 354 7 is_stmt 1 view .LVU2612 354:Src/main.c **** while(1); 7979 .loc 2 354 10 is_stmt 0 view .LVU2613 7980 04dc 20BB cbnz r0, .L329 7981 .LVL607: 7982 .L330: 356:Src/main.c **** { 7983 .loc 2 356 13 is_stmt 1 view .LVU2614 356:Src/main.c **** { 7984 .loc 2 356 18 is_stmt 0 view .LVU2615 7985 04de 134B ldr r3, .L361 7986 04e0 D3ED047A vldr.32 s15, [r3, #16] 356:Src/main.c **** { 7987 .loc 2 356 39 view .LVU2616 7988 04e4 93ED027A vldr.32 s14, [r3, #8] 356:Src/main.c **** { 7989 .loc 2 356 13 view .LVU2617 7990 04e8 F4EEC77A vcmpe.f32 s15, s14 7991 04ec F1EE10FA vmrs APSR_nzcv, FPSCR 7992 04f0 50D5 bpl .L357 358:Src/main.c **** { 7993 .loc 2 358 8 is_stmt 1 view .LVU2618 358:Src/main.c **** { 7994 .loc 2 358 12 is_stmt 0 view .LVU2619 7995 04f2 214B ldr r3, .L361+76 7996 04f4 1B78 ldrb r3, [r3] @ zero_extendqisi2 358:Src/main.c **** { 7997 .loc 2 358 11 view .LVU2620 7998 04f6 002B cmp r3, #0 7999 04f8 F1D0 beq .L330 360:Src/main.c **** task.current_param += task.delta_param; 8000 .loc 2 360 9 is_stmt 1 view .LVU2621 8001 04fa FCEEE77A vcvt.u32.f32 s15, s15 8002 04fe 17EE903A vmov r3, s15 @ int 8003 0502 99B2 uxth r1, r3 8004 0504 0120 movs r0, #1 8005 0506 FFF7FEFF bl Set_LTEC 8006 .LVL608: 361:Src/main.c **** TO10 = 0; 8007 .loc 2 361 9 view .LVU2622 361:Src/main.c **** TO10 = 0; 8008 .loc 2 361 35 is_stmt 0 view .LVU2623 8009 050a 084B ldr r3, .L361 8010 050c 93ED037A vldr.32 s14, [r3, #12] 361:Src/main.c **** TO10 = 0; 8011 .loc 2 361 28 view .LVU2624 8012 0510 D3ED047A vldr.32 s15, [r3, #16] 8013 0514 77EE877A vadd.f32 s15, s15, s14 8014 0518 C3ED047A vstr.32 s15, [r3, #16] ARM GAS /tmp/ccdsDELB.s page 510 362:Src/main.c **** TIM10_coflag = 0; 8015 .loc 2 362 9 is_stmt 1 view .LVU2625 362:Src/main.c **** TIM10_coflag = 0; 8016 .loc 2 362 14 is_stmt 0 view .LVU2626 8017 051c 0023 movs r3, #0 8018 051e 1C4A ldr r2, .L361+100 8019 0520 1360 str r3, [r2] 363:Src/main.c **** } 8020 .loc 2 363 9 is_stmt 1 view .LVU2627 363:Src/main.c **** } 8021 .loc 2 363 22 is_stmt 0 view .LVU2628 8022 0522 154A ldr r2, .L361+76 8023 0524 1370 strb r3, [r2] 8024 0526 DAE7 b .L330 8025 .LVL609: 8026 .L329: 355:Src/main.c **** while (task.current_param < task.max_param) 8027 .loc 2 355 8 is_stmt 1 discriminator 1 view .LVU2629 355:Src/main.c **** while (task.current_param < task.max_param) 8028 .loc 2 355 16 discriminator 1 view .LVU2630 355:Src/main.c **** while (task.current_param < task.max_param) 8029 .loc 2 355 13 discriminator 1 view .LVU2631 8030 0528 FEE7 b .L329 8031 .L362: 8032 052a 00BF .align 2 8033 .L361: 8034 052c 00000000 .word .LANCHOR1 8035 0530 00000000 .word .LANCHOR3 8036 0534 00000000 .word .LANCHOR8 8037 0538 00000000 .word .LANCHOR39 8038 053c 00000000 .word .LANCHOR40 8039 0540 00000000 .word .LANCHOR38 8040 0544 00000000 .word .LANCHOR6 8041 0548 00000000 .word .LANCHOR7 8042 054c 00000000 .word .LANCHOR41 8043 0550 00000000 .word .LANCHOR20 8044 0554 00000000 .word .LANCHOR35 8045 0558 00000000 .word .LANCHOR34 8046 055c 00000000 .word .LANCHOR36 8047 0560 00000000 .word .LANCHOR26 8048 0564 00000000 .word .LANCHOR27 8049 0568 00000000 .word .LANCHOR37 8050 056c 00000000 .word .LANCHOR22 8051 0570 00000000 .word .LANCHOR21 8052 0574 00000000 .word .LANCHOR9 8053 0578 00000000 .word .LANCHOR31 8054 057c 00000000 .word .LANCHOR42 8055 0580 00000000 .word .LANCHOR30 8056 0584 CDCCCCCC .word -858993459 8057 0588 00000000 .word .LANCHOR2 8058 058c 000C0240 .word 1073875968 8059 0590 00000000 .word .LANCHOR32 8060 .LVL610: 8061 .L357: 366:Src/main.c **** task.current_param = task.min_param; 8062 .loc 2 366 7 view .LVU2632 8063 0594 FFF7FEFF bl Stop_TIM10 ARM GAS /tmp/ccdsDELB.s page 511 8064 .LVL611: 367:Src/main.c **** Set_LTEC(TT_CHANGE_CURR_1, task.current_param); 8065 .loc 2 367 7 view .LVU2633 367:Src/main.c **** Set_LTEC(TT_CHANGE_CURR_1, task.current_param); 8066 .loc 2 367 32 is_stmt 0 view .LVU2634 8067 0598 A94C ldr r4, .L363 8068 059a D4ED017A vldr.32 s15, [r4, #4] 367:Src/main.c **** Set_LTEC(TT_CHANGE_CURR_1, task.current_param); 8069 .loc 2 367 26 view .LVU2635 8070 059e C4ED047A vstr.32 s15, [r4, #16] 368:Src/main.c **** if (task.tau > 3) 8071 .loc 2 368 7 is_stmt 1 view .LVU2636 8072 05a2 FCEEE77A vcvt.u32.f32 s15, s15 8073 05a6 17EE903A vmov r3, s15 @ int 8074 05aa 99B2 uxth r1, r3 8075 05ac 0120 movs r0, #1 8076 05ae FFF7FEFF bl Set_LTEC 8077 .LVL612: 369:Src/main.c **** { 8078 .loc 2 369 7 view .LVU2637 369:Src/main.c **** { 8079 .loc 2 369 15 is_stmt 0 view .LVU2638 8080 05b2 E38A ldrh r3, [r4, #22] 369:Src/main.c **** { 8081 .loc 2 369 10 view .LVU2639 8082 05b4 032B cmp r3, #3 8083 05b6 0CD9 bls .L332 371:Src/main.c **** htim10.Init.Period = 9999; 8084 .loc 2 371 8 is_stmt 1 view .LVU2640 371:Src/main.c **** htim10.Init.Period = 9999; 8085 .loc 2 371 34 is_stmt 0 view .LVU2641 8086 05b8 A24A ldr r2, .L363+4 8087 05ba D068 ldr r0, [r2, #12] 371:Src/main.c **** htim10.Init.Period = 9999; 8088 .loc 2 371 21 view .LVU2642 8089 05bc A249 ldr r1, .L363+8 8090 05be 0860 str r0, [r1] 372:Src/main.c **** TO10_counter = (task.tau - 1) * 100; 8091 .loc 2 372 8 is_stmt 1 view .LVU2643 372:Src/main.c **** TO10_counter = (task.tau - 1) * 100; 8092 .loc 2 372 27 is_stmt 0 view .LVU2644 8093 05c0 42F20F71 movw r1, #9999 8094 05c4 D160 str r1, [r2, #12] 373:Src/main.c **** } 8095 .loc 2 373 8 is_stmt 1 view .LVU2645 373:Src/main.c **** } 8096 .loc 2 373 33 is_stmt 0 view .LVU2646 8097 05c6 013B subs r3, r3, #1 373:Src/main.c **** } 8098 .loc 2 373 38 view .LVU2647 8099 05c8 6422 movs r2, #100 8100 05ca 02FB03F3 mul r3, r2, r3 373:Src/main.c **** } 8101 .loc 2 373 21 view .LVU2648 8102 05ce 9F4A ldr r2, .L363+12 8103 05d0 1360 str r3, [r2] 8104 .L332: ARM GAS /tmp/ccdsDELB.s page 512 375:Src/main.c **** break; 8105 .loc 2 375 7 is_stmt 1 view .LVU2649 8106 05d2 9C48 ldr r0, .L363+4 8107 05d4 FFF7FEFF bl HAL_TIM_Base_Start_IT 8108 .LVL613: 376:Src/main.c **** case TT_CHANGE_CURR_2: 8109 .loc 2 376 6 view .LVU2650 8110 05d8 20E7 b .L327 8111 .L326: 378:Src/main.c **** (void) MPhD_T(TT_CHANGE_TEMP_1); 8112 .loc 2 378 7 view .LVU2651 378:Src/main.c **** (void) MPhD_T(TT_CHANGE_TEMP_1); 8113 .loc 2 378 38 is_stmt 0 view .LVU2652 8114 05da 994B ldr r3, .L363 8115 05dc D3ED077A vldr.32 s15, [r3, #28] 378:Src/main.c **** (void) MPhD_T(TT_CHANGE_TEMP_1); 8116 .loc 2 378 7 view .LVU2653 8117 05e0 FCEEE77A vcvt.u32.f32 s15, s15 8118 05e4 17EE903A vmov r3, s15 @ int 8119 05e8 99B2 uxth r1, r3 8120 05ea 0120 movs r0, #1 8121 05ec FFF7FEFF bl Set_LTEC 8122 .LVL614: 379:Src/main.c **** LD1_param.LD_CURR_TEMP = MPhD_T(TT_CHANGE_TEMP_1); 8123 .loc 2 379 7 is_stmt 1 view .LVU2654 379:Src/main.c **** LD1_param.LD_CURR_TEMP = MPhD_T(TT_CHANGE_TEMP_1); 8124 .loc 2 379 14 is_stmt 0 view .LVU2655 8125 05f0 0320 movs r0, #3 8126 05f2 FFF7FEFF bl MPhD_T 8127 .LVL615: 380:Src/main.c **** (void) MPhD_T(TT_CHANGE_TEMP_2); 8128 .loc 2 380 7 is_stmt 1 view .LVU2656 380:Src/main.c **** (void) MPhD_T(TT_CHANGE_TEMP_2); 8129 .loc 2 380 32 is_stmt 0 view .LVU2657 8130 05f6 0320 movs r0, #3 8131 05f8 FFF7FEFF bl MPhD_T 8132 .LVL616: 380:Src/main.c **** (void) MPhD_T(TT_CHANGE_TEMP_2); 8133 .loc 2 380 30 view .LVU2658 8134 05fc 944C ldr r4, .L363+16 8135 05fe 2080 strh r0, [r4] @ movhi 381:Src/main.c **** LD2_param.LD_CURR_TEMP = MPhD_T(TT_CHANGE_TEMP_2); 8136 .loc 2 381 7 is_stmt 1 view .LVU2659 381:Src/main.c **** LD2_param.LD_CURR_TEMP = MPhD_T(TT_CHANGE_TEMP_2); 8137 .loc 2 381 14 is_stmt 0 view .LVU2660 8138 0600 0420 movs r0, #4 8139 0602 FFF7FEFF bl MPhD_T 8140 .LVL617: 382:Src/main.c **** temp16=PID_Controller_Temp(&LD1_curr_setup, &LD1_param, 1); 8141 .loc 2 382 7 is_stmt 1 view .LVU2661 382:Src/main.c **** temp16=PID_Controller_Temp(&LD1_curr_setup, &LD1_param, 1); 8142 .loc 2 382 32 is_stmt 0 view .LVU2662 8143 0606 0420 movs r0, #4 8144 0608 FFF7FEFF bl MPhD_T 8145 .LVL618: 382:Src/main.c **** temp16=PID_Controller_Temp(&LD1_curr_setup, &LD1_param, 1); 8146 .loc 2 382 30 view .LVU2663 ARM GAS /tmp/ccdsDELB.s page 513 8147 060c 914D ldr r5, .L363+20 8148 060e 2880 strh r0, [r5] @ movhi 383:Src/main.c **** Set_LTEC(TT_CHANGE_TEMP_1, temp16);//Drive Laser TEC 1 8149 .loc 2 383 7 is_stmt 1 view .LVU2664 383:Src/main.c **** Set_LTEC(TT_CHANGE_TEMP_1, temp16);//Drive Laser TEC 1 8150 .loc 2 383 14 is_stmt 0 view .LVU2665 8151 0610 0122 movs r2, #1 8152 0612 2146 mov r1, r4 8153 0614 9048 ldr r0, .L363+24 8154 0616 FFF7FEFF bl PID_Controller_Temp 8155 .LVL619: 8156 061a 0146 mov r1, r0 383:Src/main.c **** Set_LTEC(TT_CHANGE_TEMP_1, temp16);//Drive Laser TEC 1 8157 .loc 2 383 13 view .LVU2666 8158 061c 8F4C ldr r4, .L363+28 8159 061e 2080 strh r0, [r4] @ movhi 384:Src/main.c **** temp16=PID_Controller_Temp(&LD2_curr_setup, &LD2_param, 2); 8160 .loc 2 384 7 is_stmt 1 view .LVU2667 8161 0620 0320 movs r0, #3 8162 0622 FFF7FEFF bl Set_LTEC 8163 .LVL620: 385:Src/main.c **** Set_LTEC(TT_CHANGE_TEMP_2, temp16);//Drive Laser TEC 2 8164 .loc 2 385 7 view .LVU2668 385:Src/main.c **** Set_LTEC(TT_CHANGE_TEMP_2, temp16);//Drive Laser TEC 2 8165 .loc 2 385 14 is_stmt 0 view .LVU2669 8166 0626 0222 movs r2, #2 8167 0628 2946 mov r1, r5 8168 062a 8D48 ldr r0, .L363+32 8169 062c FFF7FEFF bl PID_Controller_Temp 8170 .LVL621: 8171 0630 0146 mov r1, r0 385:Src/main.c **** Set_LTEC(TT_CHANGE_TEMP_2, temp16);//Drive Laser TEC 2 8172 .loc 2 385 13 view .LVU2670 8173 0632 2080 strh r0, [r4] @ movhi 386:Src/main.c **** 8174 .loc 2 386 7 is_stmt 1 view .LVU2671 8175 0634 0420 movs r0, #4 8176 0636 FFF7FEFF bl Set_LTEC 8177 .LVL622: 389:Src/main.c **** HAL_GPIO_WritePin(GPIOD, GPIO_PIN_7, GPIO_PIN_RESET); 8178 .loc 2 389 7 view .LVU2672 8179 063a 8A4C ldr r4, .L363+36 8180 063c 0122 movs r2, #1 8181 063e 8021 movs r1, #128 8182 0640 2046 mov r0, r4 8183 0642 FFF7FEFF bl HAL_GPIO_WritePin 8184 .LVL623: 390:Src/main.c **** 8185 .loc 2 390 7 view .LVU2673 8186 0646 0022 movs r2, #0 8187 0648 8021 movs r1, #128 8188 064a 2046 mov r0, r4 8189 064c FFF7FEFF bl HAL_GPIO_WritePin 8190 .LVL624: 392:Src/main.c **** if (st != HAL_OK) 8191 .loc 2 392 7 view .LVU2674 392:Src/main.c **** if (st != HAL_OK) ARM GAS /tmp/ccdsDELB.s page 514 8192 .loc 2 392 12 is_stmt 0 view .LVU2675 8193 0650 7C48 ldr r0, .L363+4 8194 0652 FFF7FEFF bl HAL_TIM_Base_Start_IT 8195 .LVL625: 393:Src/main.c **** while(1); 8196 .loc 2 393 7 is_stmt 1 view .LVU2676 393:Src/main.c **** while(1); 8197 .loc 2 393 10 is_stmt 0 view .LVU2677 8198 0656 20BB cbnz r0, .L334 8199 .LVL626: 8200 .L335: 395:Src/main.c **** { 8201 .loc 2 395 13 is_stmt 1 view .LVU2678 395:Src/main.c **** { 8202 .loc 2 395 18 is_stmt 0 view .LVU2679 8203 0658 794B ldr r3, .L363 8204 065a D3ED047A vldr.32 s15, [r3, #16] 395:Src/main.c **** { 8205 .loc 2 395 39 view .LVU2680 8206 065e 93ED027A vldr.32 s14, [r3, #8] 395:Src/main.c **** { 8207 .loc 2 395 13 view .LVU2681 8208 0662 F4EEC77A vcmpe.f32 s15, s14 8209 0666 F1EE10FA vmrs APSR_nzcv, FPSCR 8210 066a 1BD5 bpl .L358 397:Src/main.c **** { 8211 .loc 2 397 8 is_stmt 1 view .LVU2682 397:Src/main.c **** { 8212 .loc 2 397 12 is_stmt 0 view .LVU2683 8213 066c 7E4B ldr r3, .L363+40 8214 066e 1B78 ldrb r3, [r3] @ zero_extendqisi2 397:Src/main.c **** { 8215 .loc 2 397 11 view .LVU2684 8216 0670 002B cmp r3, #0 8217 0672 F1D0 beq .L335 399:Src/main.c **** task.current_param += task.delta_param; 8218 .loc 2 399 9 is_stmt 1 view .LVU2685 8219 0674 FCEEE77A vcvt.u32.f32 s15, s15 8220 0678 17EE903A vmov r3, s15 @ int 8221 067c 99B2 uxth r1, r3 8222 067e 0220 movs r0, #2 8223 0680 FFF7FEFF bl Set_LTEC 8224 .LVL627: 400:Src/main.c **** TO10 = 0; 8225 .loc 2 400 9 view .LVU2686 400:Src/main.c **** TO10 = 0; 8226 .loc 2 400 35 is_stmt 0 view .LVU2687 8227 0684 6E4B ldr r3, .L363 8228 0686 93ED037A vldr.32 s14, [r3, #12] 400:Src/main.c **** TO10 = 0; 8229 .loc 2 400 28 view .LVU2688 8230 068a D3ED047A vldr.32 s15, [r3, #16] 8231 068e 77EE877A vadd.f32 s15, s15, s14 8232 0692 C3ED047A vstr.32 s15, [r3, #16] 401:Src/main.c **** TIM10_coflag = 0; 8233 .loc 2 401 9 is_stmt 1 view .LVU2689 401:Src/main.c **** TIM10_coflag = 0; ARM GAS /tmp/ccdsDELB.s page 515 8234 .loc 2 401 14 is_stmt 0 view .LVU2690 8235 0696 0023 movs r3, #0 8236 0698 744A ldr r2, .L363+44 8237 069a 1360 str r3, [r2] 402:Src/main.c **** } 8238 .loc 2 402 9 is_stmt 1 view .LVU2691 402:Src/main.c **** } 8239 .loc 2 402 22 is_stmt 0 view .LVU2692 8240 069c 724A ldr r2, .L363+40 8241 069e 1370 strb r3, [r2] 8242 06a0 DAE7 b .L335 8243 .LVL628: 8244 .L334: 394:Src/main.c **** while (task.current_param < task.max_param) 8245 .loc 2 394 8 is_stmt 1 discriminator 2 view .LVU2693 394:Src/main.c **** while (task.current_param < task.max_param) 8246 .loc 2 394 16 discriminator 2 view .LVU2694 394:Src/main.c **** while (task.current_param < task.max_param) 8247 .loc 2 394 13 discriminator 2 view .LVU2695 8248 06a2 FEE7 b .L334 8249 .LVL629: 8250 .L358: 405:Src/main.c **** task.current_param = task.min_param; 8251 .loc 2 405 7 view .LVU2696 8252 06a4 FFF7FEFF bl Stop_TIM10 8253 .LVL630: 406:Src/main.c **** Set_LTEC(TT_CHANGE_CURR_2, task.current_param); 8254 .loc 2 406 7 view .LVU2697 406:Src/main.c **** Set_LTEC(TT_CHANGE_CURR_2, task.current_param); 8255 .loc 2 406 32 is_stmt 0 view .LVU2698 8256 06a8 654C ldr r4, .L363 8257 06aa D4ED017A vldr.32 s15, [r4, #4] 406:Src/main.c **** Set_LTEC(TT_CHANGE_CURR_2, task.current_param); 8258 .loc 2 406 26 view .LVU2699 8259 06ae C4ED047A vstr.32 s15, [r4, #16] 407:Src/main.c **** if (task.tau > 3) 8260 .loc 2 407 7 is_stmt 1 view .LVU2700 8261 06b2 FCEEE77A vcvt.u32.f32 s15, s15 8262 06b6 17EE903A vmov r3, s15 @ int 8263 06ba 99B2 uxth r1, r3 8264 06bc 0220 movs r0, #2 8265 06be FFF7FEFF bl Set_LTEC 8266 .LVL631: 408:Src/main.c **** { 8267 .loc 2 408 7 view .LVU2701 408:Src/main.c **** { 8268 .loc 2 408 15 is_stmt 0 view .LVU2702 8269 06c2 E38A ldrh r3, [r4, #22] 408:Src/main.c **** { 8270 .loc 2 408 10 view .LVU2703 8271 06c4 032B cmp r3, #3 8272 06c6 0CD9 bls .L337 410:Src/main.c **** htim10.Init.Period = 9999; 8273 .loc 2 410 8 is_stmt 1 view .LVU2704 410:Src/main.c **** htim10.Init.Period = 9999; 8274 .loc 2 410 34 is_stmt 0 view .LVU2705 8275 06c8 5E4A ldr r2, .L363+4 ARM GAS /tmp/ccdsDELB.s page 516 8276 06ca D068 ldr r0, [r2, #12] 410:Src/main.c **** htim10.Init.Period = 9999; 8277 .loc 2 410 21 view .LVU2706 8278 06cc 5E49 ldr r1, .L363+8 8279 06ce 0860 str r0, [r1] 411:Src/main.c **** TO10_counter = (task.tau - 1) * 100; 8280 .loc 2 411 8 is_stmt 1 view .LVU2707 411:Src/main.c **** TO10_counter = (task.tau - 1) * 100; 8281 .loc 2 411 27 is_stmt 0 view .LVU2708 8282 06d0 42F20F71 movw r1, #9999 8283 06d4 D160 str r1, [r2, #12] 412:Src/main.c **** } 8284 .loc 2 412 8 is_stmt 1 view .LVU2709 412:Src/main.c **** } 8285 .loc 2 412 33 is_stmt 0 view .LVU2710 8286 06d6 013B subs r3, r3, #1 412:Src/main.c **** } 8287 .loc 2 412 38 view .LVU2711 8288 06d8 6422 movs r2, #100 8289 06da 02FB03F3 mul r3, r2, r3 412:Src/main.c **** } 8290 .loc 2 412 21 view .LVU2712 8291 06de 5B4A ldr r2, .L363+12 8292 06e0 1360 str r3, [r2] 8293 .L337: 414:Src/main.c **** break; 8294 .loc 2 414 7 is_stmt 1 view .LVU2713 8295 06e2 5848 ldr r0, .L363+4 8296 06e4 FFF7FEFF bl HAL_TIM_Base_Start_IT 8297 .LVL632: 415:Src/main.c **** case TT_CHANGE_TEMP_1: 8298 .loc 2 415 6 view .LVU2714 8299 06e8 98E6 b .L327 8300 .L356: 426:Src/main.c **** 8301 .loc 2 426 7 view .LVU2715 426:Src/main.c **** 8302 .loc 2 426 18 is_stmt 0 view .LVU2716 8303 06ea 614A ldr r2, .L363+48 8304 06ec 1360 str r3, [r2] 428:Src/main.c **** LD1_param.POWER = MPhD_T(1);//Get Data from monitor photodiode of LD1 8305 .loc 2 428 7 is_stmt 1 view .LVU2717 428:Src/main.c **** LD1_param.POWER = MPhD_T(1);//Get Data from monitor photodiode of LD1 8306 .loc 2 428 25 is_stmt 0 view .LVU2718 8307 06ee 0120 movs r0, #1 8308 06f0 FFF7FEFF bl MPhD_T 8309 .LVL633: 428:Src/main.c **** LD1_param.POWER = MPhD_T(1);//Get Data from monitor photodiode of LD1 8310 .loc 2 428 23 view .LVU2719 8311 06f4 564E ldr r6, .L363+16 8312 06f6 3081 strh r0, [r6, #8] @ movhi 429:Src/main.c **** LD2_param.POWER = MPhD_T(2);//Get Data from monitor photodiode of LD2 8313 .loc 2 429 7 is_stmt 1 view .LVU2720 429:Src/main.c **** LD2_param.POWER = MPhD_T(2);//Get Data from monitor photodiode of LD2 8314 .loc 2 429 25 is_stmt 0 view .LVU2721 8315 06f8 0120 movs r0, #1 8316 06fa FFF7FEFF bl MPhD_T ARM GAS /tmp/ccdsDELB.s page 517 8317 .LVL634: 429:Src/main.c **** LD2_param.POWER = MPhD_T(2);//Get Data from monitor photodiode of LD2 8318 .loc 2 429 23 view .LVU2722 8319 06fe 3081 strh r0, [r6, #8] @ movhi 430:Src/main.c **** LD2_param.POWER = MPhD_T(2);//Get Data from monitor photodiode of LD2 8320 .loc 2 430 7 is_stmt 1 view .LVU2723 430:Src/main.c **** LD2_param.POWER = MPhD_T(2);//Get Data from monitor photodiode of LD2 8321 .loc 2 430 25 is_stmt 0 view .LVU2724 8322 0700 0220 movs r0, #2 8323 0702 FFF7FEFF bl MPhD_T 8324 .LVL635: 430:Src/main.c **** LD2_param.POWER = MPhD_T(2);//Get Data from monitor photodiode of LD2 8325 .loc 2 430 23 view .LVU2725 8326 0706 534F ldr r7, .L363+20 8327 0708 3881 strh r0, [r7, #8] @ movhi 431:Src/main.c **** 8328 .loc 2 431 7 is_stmt 1 view .LVU2726 431:Src/main.c **** 8329 .loc 2 431 25 is_stmt 0 view .LVU2727 8330 070a 0220 movs r0, #2 8331 070c FFF7FEFF bl MPhD_T 8332 .LVL636: 431:Src/main.c **** 8333 .loc 2 431 23 view .LVU2728 8334 0710 3881 strh r0, [r7, #8] @ movhi 433:Src/main.c **** Long_Data[2] = LD2_param.POWER;//Translate Data from monitor photodiode of LD2 to Long_Data 8335 .loc 2 433 7 is_stmt 1 view .LVU2729 433:Src/main.c **** Long_Data[2] = LD2_param.POWER;//Translate Data from monitor photodiode of LD2 to Long_Data 8336 .loc 2 433 31 is_stmt 0 view .LVU2730 8337 0712 3389 ldrh r3, [r6, #8] 433:Src/main.c **** Long_Data[2] = LD2_param.POWER;//Translate Data from monitor photodiode of LD2 to Long_Data 8338 .loc 2 433 20 view .LVU2731 8339 0714 574C ldr r4, .L363+52 8340 0716 6380 strh r3, [r4, #2] @ movhi 434:Src/main.c **** 8341 .loc 2 434 7 is_stmt 1 view .LVU2732 434:Src/main.c **** 8342 .loc 2 434 20 is_stmt 0 view .LVU2733 8343 0718 A080 strh r0, [r4, #4] @ movhi 438:Src/main.c **** temp16 = Get_ADC(1); 8344 .loc 2 438 7 is_stmt 1 view .LVU2734 438:Src/main.c **** temp16 = Get_ADC(1); 8345 .loc 2 438 16 is_stmt 0 view .LVU2735 8346 071a 0020 movs r0, #0 8347 071c FFF7FEFF bl Get_ADC 8348 .LVL637: 438:Src/main.c **** temp16 = Get_ADC(1); 8349 .loc 2 438 14 view .LVU2736 8350 0720 4E4D ldr r5, .L363+28 8351 0722 2880 strh r0, [r5] @ movhi 439:Src/main.c **** Long_Data[7] = temp16; 8352 .loc 2 439 7 is_stmt 1 view .LVU2737 439:Src/main.c **** Long_Data[7] = temp16; 8353 .loc 2 439 16 is_stmt 0 view .LVU2738 8354 0724 0120 movs r0, #1 8355 0726 FFF7FEFF bl Get_ADC 8356 .LVL638: ARM GAS /tmp/ccdsDELB.s page 518 439:Src/main.c **** Long_Data[7] = temp16; 8357 .loc 2 439 14 view .LVU2739 8358 072a 2880 strh r0, [r5] @ movhi 440:Src/main.c **** 8359 .loc 2 440 7 is_stmt 1 view .LVU2740 440:Src/main.c **** 8360 .loc 2 440 20 is_stmt 0 view .LVU2741 8361 072c E081 strh r0, [r4, #14] @ movhi 443:Src/main.c **** Long_Data[8] = temp16; 8362 .loc 2 443 7 is_stmt 1 view .LVU2742 443:Src/main.c **** Long_Data[8] = temp16; 8363 .loc 2 443 16 is_stmt 0 view .LVU2743 8364 072e 0120 movs r0, #1 8365 0730 FFF7FEFF bl Get_ADC 8366 .LVL639: 443:Src/main.c **** Long_Data[8] = temp16; 8367 .loc 2 443 14 view .LVU2744 8368 0734 2880 strh r0, [r5] @ movhi 444:Src/main.c **** 8369 .loc 2 444 7 is_stmt 1 view .LVU2745 444:Src/main.c **** 8370 .loc 2 444 20 is_stmt 0 view .LVU2746 8371 0736 2082 strh r0, [r4, #16] @ movhi 447:Src/main.c **** Long_Data[9] = temp16; 8372 .loc 2 447 7 is_stmt 1 view .LVU2747 447:Src/main.c **** Long_Data[9] = temp16; 8373 .loc 2 447 16 is_stmt 0 view .LVU2748 8374 0738 0120 movs r0, #1 8375 073a FFF7FEFF bl Get_ADC 8376 .LVL640: 447:Src/main.c **** Long_Data[9] = temp16; 8377 .loc 2 447 14 view .LVU2749 8378 073e 2880 strh r0, [r5] @ movhi 448:Src/main.c **** 8379 .loc 2 448 7 is_stmt 1 view .LVU2750 448:Src/main.c **** 8380 .loc 2 448 20 is_stmt 0 view .LVU2751 8381 0740 6082 strh r0, [r4, #18] @ movhi 451:Src/main.c **** Long_Data[10] = temp16; 8382 .loc 2 451 7 is_stmt 1 view .LVU2752 451:Src/main.c **** Long_Data[10] = temp16; 8383 .loc 2 451 16 is_stmt 0 view .LVU2753 8384 0742 0120 movs r0, #1 8385 0744 FFF7FEFF bl Get_ADC 8386 .LVL641: 451:Src/main.c **** Long_Data[10] = temp16; 8387 .loc 2 451 14 view .LVU2754 8388 0748 2880 strh r0, [r5] @ movhi 452:Src/main.c **** 8389 .loc 2 452 7 is_stmt 1 view .LVU2755 452:Src/main.c **** 8390 .loc 2 452 21 is_stmt 0 view .LVU2756 8391 074a A082 strh r0, [r4, #20] @ movhi 455:Src/main.c **** Long_Data[11] = temp16; 8392 .loc 2 455 7 is_stmt 1 view .LVU2757 455:Src/main.c **** Long_Data[11] = temp16; 8393 .loc 2 455 16 is_stmt 0 view .LVU2758 ARM GAS /tmp/ccdsDELB.s page 519 8394 074c 0120 movs r0, #1 8395 074e FFF7FEFF bl Get_ADC 8396 .LVL642: 455:Src/main.c **** Long_Data[11] = temp16; 8397 .loc 2 455 14 view .LVU2759 8398 0752 2880 strh r0, [r5] @ movhi 456:Src/main.c **** temp16 = Get_ADC(2); 8399 .loc 2 456 7 is_stmt 1 view .LVU2760 456:Src/main.c **** temp16 = Get_ADC(2); 8400 .loc 2 456 21 is_stmt 0 view .LVU2761 8401 0754 E082 strh r0, [r4, #22] @ movhi 457:Src/main.c **** 8402 .loc 2 457 7 is_stmt 1 view .LVU2762 457:Src/main.c **** 8403 .loc 2 457 16 is_stmt 0 view .LVU2763 8404 0756 0220 movs r0, #2 8405 0758 FFF7FEFF bl Get_ADC 8406 .LVL643: 457:Src/main.c **** 8407 .loc 2 457 14 view .LVU2764 8408 075c 2880 strh r0, [r5] @ movhi 460:Src/main.c **** temp16 = Get_ADC(4); 8409 .loc 2 460 7 is_stmt 1 view .LVU2765 460:Src/main.c **** temp16 = Get_ADC(4); 8410 .loc 2 460 16 is_stmt 0 view .LVU2766 8411 075e 0320 movs r0, #3 8412 0760 FFF7FEFF bl Get_ADC 8413 .LVL644: 460:Src/main.c **** temp16 = Get_ADC(4); 8414 .loc 2 460 14 view .LVU2767 8415 0764 2880 strh r0, [r5] @ movhi 461:Src/main.c **** Long_Data[12] = temp16; 8416 .loc 2 461 7 is_stmt 1 view .LVU2768 461:Src/main.c **** Long_Data[12] = temp16; 8417 .loc 2 461 16 is_stmt 0 view .LVU2769 8418 0766 0420 movs r0, #4 8419 0768 FFF7FEFF bl Get_ADC 8420 .LVL645: 461:Src/main.c **** Long_Data[12] = temp16; 8421 .loc 2 461 14 view .LVU2770 8422 076c 2880 strh r0, [r5] @ movhi 462:Src/main.c **** temp16 = Get_ADC(5); 8423 .loc 2 462 7 is_stmt 1 view .LVU2771 462:Src/main.c **** temp16 = Get_ADC(5); 8424 .loc 2 462 21 is_stmt 0 view .LVU2772 8425 076e 2083 strh r0, [r4, #24] @ movhi 463:Src/main.c **** 8426 .loc 2 463 7 is_stmt 1 view .LVU2773 463:Src/main.c **** 8427 .loc 2 463 16 is_stmt 0 view .LVU2774 8428 0770 0520 movs r0, #5 8429 0772 FFF7FEFF bl Get_ADC 8430 .LVL646: 463:Src/main.c **** 8431 .loc 2 463 14 view .LVU2775 8432 0776 2880 strh r0, [r5] @ movhi 466:Src/main.c **** Long_Data[3] = (TO6_stop)&0xffff; ARM GAS /tmp/ccdsDELB.s page 520 8433 .loc 2 466 7 is_stmt 1 view .LVU2776 466:Src/main.c **** Long_Data[3] = (TO6_stop)&0xffff; 8434 .loc 2 466 16 is_stmt 0 view .LVU2777 8435 0778 3F4B ldr r3, .L363+56 8436 077a 1B68 ldr r3, [r3] 8437 077c 3F4A ldr r2, .L363+60 8438 077e 1360 str r3, [r2] 467:Src/main.c **** Long_Data[4] = (TO6_stop>>16)&0xffff; 8439 .loc 2 467 7 is_stmt 1 view .LVU2778 467:Src/main.c **** Long_Data[4] = (TO6_stop>>16)&0xffff; 8440 .loc 2 467 20 is_stmt 0 view .LVU2779 8441 0780 E380 strh r3, [r4, #6] @ movhi 468:Src/main.c **** 8442 .loc 2 468 7 is_stmt 1 view .LVU2780 468:Src/main.c **** 8443 .loc 2 468 31 is_stmt 0 view .LVU2781 8444 0782 1B0C lsrs r3, r3, #16 468:Src/main.c **** 8445 .loc 2 468 20 view .LVU2782 8446 0784 2381 strh r3, [r4, #8] @ movhi 471:Src/main.c **** 8447 .loc 2 471 7 is_stmt 1 view .LVU2783 471:Src/main.c **** 8448 .loc 2 471 31 is_stmt 0 view .LVU2784 8449 0786 3388 ldrh r3, [r6] 471:Src/main.c **** 8450 .loc 2 471 20 view .LVU2785 8451 0788 6381 strh r3, [r4, #10] @ movhi 474:Src/main.c **** } 8452 .loc 2 474 7 is_stmt 1 view .LVU2786 474:Src/main.c **** } 8453 .loc 2 474 31 is_stmt 0 view .LVU2787 8454 078a 3B88 ldrh r3, [r7] 474:Src/main.c **** } 8455 .loc 2 474 20 view .LVU2788 8456 078c A381 strh r3, [r4, #12] @ movhi 8457 078e 4CE6 b .L339 8458 .L350: 493:Src/main.c **** //HAL_UART_Transmit(&huart1, State_Data, 2, 10); 8459 .loc 2 493 5 is_stmt 1 view .LVU2789 8460 0790 3B4C ldr r4, .L363+64 8461 0792 0221 movs r1, #2 8462 0794 2046 mov r0, r4 8463 0796 FFF7FEFF bl USART_TX 8464 .LVL647: 495:Src/main.c **** State_Data[1]=0;//All OK! 8465 .loc 2 495 5 view .LVU2790 495:Src/main.c **** State_Data[1]=0;//All OK! 8466 .loc 2 495 18 is_stmt 0 view .LVU2791 8467 079a 0023 movs r3, #0 8468 079c 2370 strb r3, [r4] 496:Src/main.c **** UART_transmission_request = NO_MESS; 8469 .loc 2 496 5 is_stmt 1 view .LVU2792 496:Src/main.c **** UART_transmission_request = NO_MESS; 8470 .loc 2 496 18 is_stmt 0 view .LVU2793 8471 079e 6370 strb r3, [r4, #1] 497:Src/main.c **** break; ARM GAS /tmp/ccdsDELB.s page 521 8472 .loc 2 497 5 is_stmt 1 view .LVU2794 497:Src/main.c **** break; 8473 .loc 2 497 31 is_stmt 0 view .LVU2795 8474 07a0 384A ldr r2, .L363+68 8475 07a2 1370 strb r3, [r2] 498:Src/main.c **** case MESS_02://Transmith packet 8476 .loc 2 498 4 is_stmt 1 view .LVU2796 8477 07a4 90E4 b .L343 8478 .L341: 502:Src/main.c **** Long_Data[DL_16-1] = CS_result; 8479 .loc 2 502 5 view .LVU2797 502:Src/main.c **** Long_Data[DL_16-1] = CS_result; 8480 .loc 2 502 17 is_stmt 0 view .LVU2798 8481 07a6 334C ldr r4, .L363+52 8482 07a8 0D21 movs r1, #13 8483 07aa A01C adds r0, r4, #2 8484 07ac FFF7FEFF bl CalculateChecksum 8485 .LVL648: 502:Src/main.c **** Long_Data[DL_16-1] = CS_result; 8486 .loc 2 502 15 view .LVU2799 8487 07b0 354B ldr r3, .L363+72 8488 07b2 1880 strh r0, [r3] @ movhi 503:Src/main.c **** 8489 .loc 2 503 5 is_stmt 1 view .LVU2800 503:Src/main.c **** 8490 .loc 2 503 24 is_stmt 0 view .LVU2801 8491 07b4 A083 strh r0, [r4, #28] @ movhi 505:Src/main.c **** { 8492 .loc 2 505 5 is_stmt 1 view .LVU2802 8493 .LBB569: 505:Src/main.c **** { 8494 .loc 2 505 10 view .LVU2803 8495 .LVL649: 505:Src/main.c **** { 8496 .loc 2 505 19 is_stmt 0 view .LVU2804 8497 07b6 0023 movs r3, #0 505:Src/main.c **** { 8498 .loc 2 505 5 view .LVU2805 8499 07b8 0BE0 b .L344 8500 .LVL650: 8501 .L345: 507:Src/main.c **** UART_DATA[i*2+1] = (Long_Data[i]>>8)&0xff; 8502 .loc 2 507 6 is_stmt 1 discriminator 3 view .LVU2806 507:Src/main.c **** UART_DATA[i*2+1] = (Long_Data[i]>>8)&0xff; 8503 .loc 2 507 33 is_stmt 0 discriminator 3 view .LVU2807 8504 07ba 2E4A ldr r2, .L363+52 8505 07bc 32F81320 ldrh r2, [r2, r3, lsl #1] 507:Src/main.c **** UART_DATA[i*2+1] = (Long_Data[i]>>8)&0xff; 8506 .loc 2 507 17 discriminator 3 view .LVU2808 8507 07c0 5900 lsls r1, r3, #1 507:Src/main.c **** UART_DATA[i*2+1] = (Long_Data[i]>>8)&0xff; 8508 .loc 2 507 21 discriminator 3 view .LVU2809 8509 07c2 3248 ldr r0, .L363+76 8510 07c4 00F81320 strb r2, [r0, r3, lsl #1] 508:Src/main.c **** } 8511 .loc 2 508 6 is_stmt 1 discriminator 3 view .LVU2810 508:Src/main.c **** } ARM GAS /tmp/ccdsDELB.s page 522 8512 .loc 2 508 19 is_stmt 0 discriminator 3 view .LVU2811 8513 07c8 0131 adds r1, r1, #1 508:Src/main.c **** } 8514 .loc 2 508 23 discriminator 3 view .LVU2812 8515 07ca 120A lsrs r2, r2, #8 8516 07cc 4254 strb r2, [r0, r1] 505:Src/main.c **** { 8517 .loc 2 505 37 is_stmt 1 discriminator 3 view .LVU2813 505:Src/main.c **** { 8518 .loc 2 505 38 is_stmt 0 discriminator 3 view .LVU2814 8519 07ce 0133 adds r3, r3, #1 8520 .LVL651: 505:Src/main.c **** { 8521 .loc 2 505 38 discriminator 3 view .LVU2815 8522 07d0 9BB2 uxth r3, r3 8523 .LVL652: 8524 .L344: 505:Src/main.c **** { 8525 .loc 2 505 26 is_stmt 1 discriminator 1 view .LVU2816 505:Src/main.c **** { 8526 .loc 2 505 5 is_stmt 0 discriminator 1 view .LVU2817 8527 07d2 0E2B cmp r3, #14 8528 07d4 F1D9 bls .L345 8529 .LBE569: 515:Src/main.c **** UART_transmission_request = NO_MESS; 8530 .loc 2 515 5 is_stmt 1 view .LVU2818 8531 07d6 1E20 movs r0, #30 8532 07d8 FFF7FEFF bl USART_TX_DMA 8533 .LVL653: 516:Src/main.c **** break; 8534 .loc 2 516 5 view .LVU2819 516:Src/main.c **** break; 8535 .loc 2 516 31 is_stmt 0 view .LVU2820 8536 07dc 294B ldr r3, .L363+68 8537 07de 0022 movs r2, #0 8538 07e0 1A70 strb r2, [r3] 517:Src/main.c **** case MESS_03://Transmith saved packet 8539 .loc 2 517 4 is_stmt 1 view .LVU2821 8540 07e2 71E4 b .L343 8541 .LVL654: 8542 .L346: 8543 .LBB570: 521:Src/main.c **** UART_DATA[i*2+1] = (Long_Data[i]>>8)&0xff; 8544 .loc 2 521 6 discriminator 3 view .LVU2822 521:Src/main.c **** UART_DATA[i*2+1] = (Long_Data[i]>>8)&0xff; 8545 .loc 2 521 33 is_stmt 0 discriminator 3 view .LVU2823 8546 07e4 234A ldr r2, .L363+52 8547 07e6 32F81320 ldrh r2, [r2, r3, lsl #1] 521:Src/main.c **** UART_DATA[i*2+1] = (Long_Data[i]>>8)&0xff; 8548 .loc 2 521 17 discriminator 3 view .LVU2824 8549 07ea 5900 lsls r1, r3, #1 521:Src/main.c **** UART_DATA[i*2+1] = (Long_Data[i]>>8)&0xff; 8550 .loc 2 521 21 discriminator 3 view .LVU2825 8551 07ec 2748 ldr r0, .L363+76 8552 07ee 00F81320 strb r2, [r0, r3, lsl #1] 522:Src/main.c **** } 8553 .loc 2 522 6 is_stmt 1 discriminator 3 view .LVU2826 ARM GAS /tmp/ccdsDELB.s page 523 522:Src/main.c **** } 8554 .loc 2 522 19 is_stmt 0 discriminator 3 view .LVU2827 8555 07f2 0131 adds r1, r1, #1 522:Src/main.c **** } 8556 .loc 2 522 23 discriminator 3 view .LVU2828 8557 07f4 120A lsrs r2, r2, #8 8558 07f6 4254 strb r2, [r0, r1] 519:Src/main.c **** { 8559 .loc 2 519 37 is_stmt 1 discriminator 3 view .LVU2829 519:Src/main.c **** { 8560 .loc 2 519 38 is_stmt 0 discriminator 3 view .LVU2830 8561 07f8 0133 adds r3, r3, #1 8562 .LVL655: 519:Src/main.c **** { 8563 .loc 2 519 38 discriminator 3 view .LVU2831 8564 07fa 9BB2 uxth r3, r3 8565 .LVL656: 8566 .L342: 519:Src/main.c **** { 8567 .loc 2 519 26 is_stmt 1 discriminator 1 view .LVU2832 519:Src/main.c **** { 8568 .loc 2 519 5 is_stmt 0 discriminator 1 view .LVU2833 8569 07fc 0E2B cmp r3, #14 8570 07fe F1D9 bls .L346 8571 .LBE570: 528:Src/main.c **** UART_transmission_request = NO_MESS; 8572 .loc 2 528 5 is_stmt 1 view .LVU2834 8573 0800 1E20 movs r0, #30 8574 0802 FFF7FEFF bl USART_TX_DMA 8575 .LVL657: 529:Src/main.c **** break; 8576 .loc 2 529 5 view .LVU2835 529:Src/main.c **** break; 8577 .loc 2 529 31 is_stmt 0 view .LVU2836 8578 0806 1F4B ldr r3, .L363+68 8579 0808 0022 movs r2, #0 8580 080a 1A70 strb r2, [r3] 530:Src/main.c **** } 8581 .loc 2 530 4 is_stmt 1 view .LVU2837 8582 080c 5CE4 b .L343 8583 .L348: 490:Src/main.c **** { 8584 .loc 2 490 3 is_stmt 0 view .LVU2838 8585 080e 0023 movs r3, #0 8586 0810 F4E7 b .L342 8587 .L351: 532:Src/main.c **** { 8588 .loc 2 532 28 discriminator 1 view .LVU2839 8589 0812 194B ldr r3, .L363+56 8590 0814 1B68 ldr r3, [r3] 8591 0816 1E4A ldr r2, .L363+80 8592 0818 1268 ldr r2, [r2] 8593 081a 9B1A subs r3, r3, r2 532:Src/main.c **** { 8594 .loc 2 532 21 discriminator 1 view .LVU2840 8595 081c 642B cmp r3, #100 8596 081e 7FF658AC bls .L301 ARM GAS /tmp/ccdsDELB.s page 524 534:Src/main.c **** State_Data[0] |= UART_ERR;//timeout error! 8597 .loc 2 534 4 is_stmt 1 view .LVU2841 534:Src/main.c **** State_Data[0] |= UART_ERR;//timeout error! 8598 .loc 2 534 18 is_stmt 0 view .LVU2842 8599 0822 0022 movs r2, #0 8600 0824 1B4B ldr r3, .L363+84 8601 0826 1A80 strh r2, [r3] @ movhi 535:Src/main.c **** UART_transmission_request = MESS_01;//Send status 8602 .loc 2 535 4 is_stmt 1 view .LVU2843 535:Src/main.c **** UART_transmission_request = MESS_01;//Send status 8603 .loc 2 535 18 is_stmt 0 view .LVU2844 8604 0828 1549 ldr r1, .L363+64 8605 082a 0B78 ldrb r3, [r1] @ zero_extendqisi2 8606 082c 43F00203 orr r3, r3, #2 8607 0830 0B70 strb r3, [r1] 536:Src/main.c **** flg_tmt = 0;//Reset timeout flag 8608 .loc 2 536 4 is_stmt 1 view .LVU2845 536:Src/main.c **** flg_tmt = 0;//Reset timeout flag 8609 .loc 2 536 30 is_stmt 0 view .LVU2846 8610 0832 144B ldr r3, .L363+68 8611 0834 0121 movs r1, #1 8612 0836 1970 strb r1, [r3] 537:Src/main.c **** } 8613 .loc 2 537 4 is_stmt 1 view .LVU2847 537:Src/main.c **** } 8614 .loc 2 537 12 is_stmt 0 view .LVU2848 8615 0838 174B ldr r3, .L363+88 8616 083a 1A70 strb r2, [r3] 8617 083c 49E4 b .L301 8618 .L364: 8619 083e 00BF .align 2 8620 .L363: 8621 0840 00000000 .word .LANCHOR1 8622 0844 00000000 .word .LANCHOR30 8623 0848 00000000 .word .LANCHOR42 8624 084c 00000000 .word .LANCHOR2 8625 0850 00000000 .word .LANCHOR39 8626 0854 00000000 .word .LANCHOR40 8627 0858 00000000 .word .LANCHOR21 8628 085c 00000000 .word .LANCHOR38 8629 0860 00000000 .word .LANCHOR22 8630 0864 000C0240 .word 1073875968 8631 0868 00000000 .word .LANCHOR31 8632 086c 00000000 .word .LANCHOR32 8633 0870 00000000 .word .LANCHOR8 8634 0874 00000000 .word .LANCHOR6 8635 0878 00000000 .word .LANCHOR7 8636 087c 00000000 .word .LANCHOR41 8637 0880 00000000 .word .LANCHOR36 8638 0884 00000000 .word .LANCHOR37 8639 0888 00000000 .word .LANCHOR34 8640 088c 00000000 .word .LANCHOR23 8641 0890 00000000 .word .LANCHOR10 8642 0894 00000000 .word .LANCHOR12 8643 0898 00000000 .word .LANCHOR11 8644 .cfi_endproc 8645 .LFE1186: ARM GAS /tmp/ccdsDELB.s page 525 8647 .global task 8648 .global LD2_param 8649 .global LD1_param 8650 .global Def_setup 8651 .global Curr_setup 8652 .global LD2_def_setup 8653 .global LD1_def_setup 8654 .global LD2_curr_setup 8655 .global LD1_curr_setup 8656 .global sizeoffile 8657 .global fgoto 8658 .global test 8659 .global fresult 8660 .global COMMAND 8661 .global Long_Data 8662 .global temp16 8663 .global CS_result 8664 .global UART_header 8665 .global UART_rec_incr 8666 .global TIM10_coflag 8667 .global u_rx_flg 8668 .global u_tx_flg 8669 .global flg_tmt 8670 .global UART_DATA 8671 .global State_Data 8672 .global UART_transmission_request 8673 .global CPU_state_old 8674 .global CPU_state 8675 .global uart_buf 8676 .global TIM10_period 8677 .global TO10_counter 8678 .global TO10 8679 .global TO7_PID 8680 .global TO7_before 8681 .global TO7 8682 .global temp32 8683 .global SD_SLIDE 8684 .global SD_SEEK 8685 .global TO6_uart 8686 .global TO6_stop 8687 .global TO6_before 8688 .global TO6 8689 .global htim10 8690 .global hsd1 8691 .global hadc3 8692 .global hadc1 8693 .section .bss.COMMAND,"aw",%nobits 8694 .align 2 8695 .set .LANCHOR26,. + 0 8698 COMMAND: 8699 0000 00000000 .space 30 8699 00000000 8699 00000000 8699 00000000 8699 00000000 8700 .section .bss.CPU_state,"aw",%nobits 8701 .set .LANCHOR27,. + 0 ARM GAS /tmp/ccdsDELB.s page 526 8704 CPU_state: 8705 0000 00 .space 1 8706 .section .bss.CPU_state_old,"aw",%nobits 8707 .set .LANCHOR35,. + 0 8710 CPU_state_old: 8711 0000 00 .space 1 8712 .section .bss.CS_result,"aw",%nobits 8713 .align 1 8714 .set .LANCHOR34,. + 0 8717 CS_result: 8718 0000 0000 .space 2 8719 .section .bss.Curr_setup,"aw",%nobits 8720 .align 2 8721 .set .LANCHOR20,. + 0 8724 Curr_setup: 8725 0000 00000000 .space 18 8725 00000000 8725 00000000 8725 00000000 8725 0000 8726 .section .bss.Def_setup,"aw",%nobits 8727 .align 2 8728 .set .LANCHOR17,. + 0 8731 Def_setup: 8732 0000 00000000 .space 18 8732 00000000 8732 00000000 8732 00000000 8732 0000 8733 .section .bss.LD1_curr_setup,"aw",%nobits 8734 .align 2 8735 .set .LANCHOR21,. + 0 8738 LD1_curr_setup: 8739 0000 00000000 .space 16 8739 00000000 8739 00000000 8739 00000000 8740 .section .bss.LD1_def_setup,"aw",%nobits 8741 .align 2 8742 .set .LANCHOR18,. + 0 8745 LD1_def_setup: 8746 0000 00000000 .space 16 8746 00000000 8746 00000000 8746 00000000 8747 .section .bss.LD1_param,"aw",%nobits 8748 .align 2 8749 .set .LANCHOR39,. + 0 8752 LD1_param: 8753 0000 00000000 .space 12 8753 00000000 8753 00000000 8754 .section .bss.LD2_curr_setup,"aw",%nobits 8755 .align 2 8756 .set .LANCHOR22,. + 0 8759 LD2_curr_setup: 8760 0000 00000000 .space 16 ARM GAS /tmp/ccdsDELB.s page 527 8760 00000000 8760 00000000 8760 00000000 8761 .section .bss.LD2_def_setup,"aw",%nobits 8762 .align 2 8763 .set .LANCHOR19,. + 0 8766 LD2_def_setup: 8767 0000 00000000 .space 16 8767 00000000 8767 00000000 8767 00000000 8768 .section .bss.LD2_param,"aw",%nobits 8769 .align 2 8770 .set .LANCHOR40,. + 0 8773 LD2_param: 8774 0000 00000000 .space 12 8774 00000000 8774 00000000 8775 .section .bss.Long_Data,"aw",%nobits 8776 .align 2 8777 .set .LANCHOR6,. + 0 8780 Long_Data: 8781 0000 00000000 .space 30 8781 00000000 8781 00000000 8781 00000000 8781 00000000 8782 .section .bss.SD_SEEK,"aw",%nobits 8783 .align 2 8784 .set .LANCHOR24,. + 0 8787 SD_SEEK: 8788 0000 00000000 .space 4 8789 .section .bss.SD_SLIDE,"aw",%nobits 8790 .align 2 8791 .set .LANCHOR25,. + 0 8794 SD_SLIDE: 8795 0000 00000000 .space 4 8796 .section .bss.State_Data,"aw",%nobits 8797 .align 2 8798 .set .LANCHOR36,. + 0 8801 State_Data: 8802 0000 0000 .space 2 8803 .section .bss.TIM10_coflag,"aw",%nobits 8804 .set .LANCHOR31,. + 0 8807 TIM10_coflag: 8808 0000 00 .space 1 8809 .section .bss.TIM10_period,"aw",%nobits 8810 .align 2 8811 .set .LANCHOR42,. + 0 8814 TIM10_period: 8815 0000 00000000 .space 4 8816 .section .bss.TO10,"aw",%nobits 8817 .align 2 8818 .set .LANCHOR32,. + 0 8821 TO10: 8822 0000 00000000 .space 4 8823 .section .bss.TO10_counter,"aw",%nobits ARM GAS /tmp/ccdsDELB.s page 528 8824 .align 2 8825 .set .LANCHOR2,. + 0 8828 TO10_counter: 8829 0000 00000000 .space 4 8830 .section .bss.TO6,"aw",%nobits 8831 .align 2 8832 .set .LANCHOR7,. + 0 8835 TO6: 8836 0000 00000000 .space 4 8837 .section .bss.TO6_before,"aw",%nobits 8838 .align 2 8839 .set .LANCHOR9,. + 0 8842 TO6_before: 8843 0000 00000000 .space 4 8844 .section .bss.TO6_stop,"aw",%nobits 8845 .align 2 8846 .set .LANCHOR41,. + 0 8849 TO6_stop: 8850 0000 00000000 .space 4 8851 .section .bss.TO6_uart,"aw",%nobits 8852 .align 2 8853 .set .LANCHOR10,. + 0 8856 TO6_uart: 8857 0000 00000000 .space 4 8858 .section .bss.TO7,"aw",%nobits 8859 .align 2 8860 .set .LANCHOR3,. + 0 8863 TO7: 8864 0000 00000000 .space 4 8865 .section .bss.TO7_PID,"aw",%nobits 8866 .align 2 8867 .set .LANCHOR4,. + 0 8870 TO7_PID: 8871 0000 00000000 .space 4 8872 .section .bss.TO7_before,"aw",%nobits 8873 .align 2 8874 .set .LANCHOR8,. + 0 8877 TO7_before: 8878 0000 00000000 .space 4 8879 .section .bss.UART_DATA,"aw",%nobits 8880 .align 2 8881 .set .LANCHOR23,. + 0 8884 UART_DATA: 8885 0000 00000000 .space 30 8885 00000000 8885 00000000 8885 00000000 8885 00000000 8886 .section .bss.UART_header,"aw",%nobits 8887 .align 1 8888 .set .LANCHOR33,. + 0 8891 UART_header: 8892 0000 0000 .space 2 8893 .section .bss.UART_rec_incr,"aw",%nobits 8894 .align 1 8895 .set .LANCHOR12,. + 0 8898 UART_rec_incr: ARM GAS /tmp/ccdsDELB.s page 529 8899 0000 0000 .space 2 8900 .section .bss.UART_transmission_request,"aw",%nobits 8901 .set .LANCHOR37,. + 0 8904 UART_transmission_request: 8905 0000 00 .space 1 8906 .section .bss.fgoto,"aw",%nobits 8907 .align 2 8908 .set .LANCHOR13,. + 0 8911 fgoto: 8912 0000 00000000 .space 4 8913 .section .bss.flg_tmt,"aw",%nobits 8914 .set .LANCHOR11,. + 0 8917 flg_tmt: 8918 0000 00 .space 1 8919 .section .bss.fresult,"aw",%nobits 8922 fresult: 8923 0000 00 .space 1 8924 .section .bss.hadc1,"aw",%nobits 8925 .align 2 8926 .set .LANCHOR28,. + 0 8929 hadc1: 8930 0000 00000000 .space 72 8930 00000000 8930 00000000 8930 00000000 8930 00000000 8931 .section .bss.hadc3,"aw",%nobits 8932 .align 2 8933 .set .LANCHOR29,. + 0 8936 hadc3: 8937 0000 00000000 .space 72 8937 00000000 8937 00000000 8937 00000000 8937 00000000 8938 .section .bss.hsd1,"aw",%nobits 8939 .align 2 8940 .set .LANCHOR0,. + 0 8943 hsd1: 8944 0000 00000000 .space 132 8944 00000000 8944 00000000 8944 00000000 8944 00000000 8945 .section .bss.htim10,"aw",%nobits 8946 .align 2 8947 .set .LANCHOR30,. + 0 8950 htim10: 8951 0000 00000000 .space 76 8951 00000000 8951 00000000 8951 00000000 8951 00000000 8952 .section .bss.sizeoffile,"aw",%nobits 8953 .align 2 8954 .set .LANCHOR14,. + 0 8957 sizeoffile: ARM GAS /tmp/ccdsDELB.s page 530 8958 0000 00000000 .space 4 8959 .section .bss.task,"aw",%nobits 8960 .align 2 8961 .set .LANCHOR1,. + 0 8964 task: 8965 0000 00000000 .space 52 8965 00000000 8965 00000000 8965 00000000 8965 00000000 8966 .section .bss.temp16,"aw",%nobits 8967 .align 1 8968 .set .LANCHOR38,. + 0 8971 temp16: 8972 0000 0000 .space 2 8973 .section .bss.temp32,"aw",%nobits 8974 .align 2 8977 temp32: 8978 0000 00000000 .space 4 8979 .section .bss.test,"aw",%nobits 8980 .align 2 8981 .set .LANCHOR5,. + 0 8984 test: 8985 0000 00000000 .space 4 8986 .section .bss.u_rx_flg,"aw",%nobits 8987 .set .LANCHOR16,. + 0 8990 u_rx_flg: 8991 0000 00 .space 1 8992 .section .bss.u_tx_flg,"aw",%nobits 8993 .set .LANCHOR15,. + 0 8996 u_tx_flg: 8997 0000 00 .space 1 8998 .section .bss.uart_buf,"aw",%nobits 9001 uart_buf: 9002 0000 00 .space 1 9003 .text 9004 .Letext0: 9005 .file 9 "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h" 9006 .file 10 "/usr/lib/gcc/arm-none-eabi/10.3.1/include/stdint.h" 9007 .file 11 "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h" 9008 .file 12 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h" 9009 .file 13 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h" 9010 .file 14 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h" 9011 .file 15 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h" 9012 .file 16 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h" 9013 .file 17 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h" 9014 .file 18 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_sdmmc.h" 9015 .file 19 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sd.h" 9016 .file 20 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h" 9017 .file 21 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h" 9018 .file 22 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h" 9019 .file 23 "Inc/main.h" 9020 .file 24 "Middlewares/Third_Party/FatFs/src/ff.h" 9021 .file 25 "Inc/File_Handling.h" 9022 .file 26 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h" 9023 .file 27 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h" 9024 .file 28 "Inc/fatfs.h" ARM GAS /tmp/ccdsDELB.s page 531 9025 .file 29 "" ARM GAS /tmp/ccdsDELB.s page 532 DEFINED SYMBOLS *ABS*:0000000000000000 main.c /tmp/ccdsDELB.s:17 .text.NVIC_EncodePriority:0000000000000000 $t /tmp/ccdsDELB.s:24 .text.NVIC_EncodePriority:0000000000000000 NVIC_EncodePriority /tmp/ccdsDELB.s:84 .text.MX_SDMMC1_SD_Init:0000000000000000 $t /tmp/ccdsDELB.s:90 .text.MX_SDMMC1_SD_Init:0000000000000000 MX_SDMMC1_SD_Init /tmp/ccdsDELB.s:129 .text.MX_SDMMC1_SD_Init:000000000000001c $d /tmp/ccdsDELB.s:135 .text.MX_DMA_Init:0000000000000000 $t /tmp/ccdsDELB.s:141 .text.MX_DMA_Init:0000000000000000 MX_DMA_Init /tmp/ccdsDELB.s:237 .text.MX_DMA_Init:000000000000003c $d /tmp/ccdsDELB.s:244 .text.Decode_task:0000000000000000 $t /tmp/ccdsDELB.s:250 .text.Decode_task:0000000000000000 Decode_task /tmp/ccdsDELB.s:529 .text.Decode_task:0000000000000150 $d /tmp/ccdsDELB.s:539 .text.PID_Controller_Temp:0000000000000000 $t /tmp/ccdsDELB.s:545 .text.PID_Controller_Temp:0000000000000000 PID_Controller_Temp /tmp/ccdsDELB.s:714 .text.PID_Controller_Temp:00000000000000cc $d /tmp/ccdsDELB.s:724 .text.Set_LTEC:0000000000000000 $t /tmp/ccdsDELB.s:730 .text.Set_LTEC:0000000000000000 Set_LTEC /tmp/ccdsDELB.s:755 .text.Set_LTEC:000000000000000e $d /tmp/ccdsDELB.s:759 .text.Set_LTEC:0000000000000012 $t /tmp/ccdsDELB.s:1168 .text.Set_LTEC:0000000000000148 $d /tmp/ccdsDELB.s:1176 .text.MPhD_T:0000000000000000 $t /tmp/ccdsDELB.s:1182 .text.MPhD_T:0000000000000000 MPhD_T /tmp/ccdsDELB.s:1793 .text.MPhD_T:0000000000000214 $d /tmp/ccdsDELB.s:1803 .text.MX_GPIO_Init:0000000000000000 $t /tmp/ccdsDELB.s:1809 .text.MX_GPIO_Init:0000000000000000 MX_GPIO_Init /tmp/ccdsDELB.s:2219 .text.MX_GPIO_Init:00000000000001f4 $d /tmp/ccdsDELB.s:2230 .text.MX_SPI4_Init:0000000000000000 $t /tmp/ccdsDELB.s:2236 .text.MX_SPI4_Init:0000000000000000 MX_SPI4_Init /tmp/ccdsDELB.s:2441 .text.MX_SPI4_Init:00000000000000c8 $d /tmp/ccdsDELB.s:2448 .text.MX_SPI2_Init:0000000000000000 $t /tmp/ccdsDELB.s:2454 .text.MX_SPI2_Init:0000000000000000 MX_SPI2_Init /tmp/ccdsDELB.s:2659 .text.MX_SPI2_Init:00000000000000c4 $d /tmp/ccdsDELB.s:2666 .text.MX_SPI5_Init:0000000000000000 $t /tmp/ccdsDELB.s:2672 .text.MX_SPI5_Init:0000000000000000 MX_SPI5_Init /tmp/ccdsDELB.s:2877 .text.MX_SPI5_Init:00000000000000c4 $d /tmp/ccdsDELB.s:2884 .text.MX_SPI6_Init:0000000000000000 $t /tmp/ccdsDELB.s:2890 .text.MX_SPI6_Init:0000000000000000 MX_SPI6_Init /tmp/ccdsDELB.s:3095 .text.MX_SPI6_Init:00000000000000c4 $d /tmp/ccdsDELB.s:3102 .text.MX_TIM2_Init:0000000000000000 $t /tmp/ccdsDELB.s:3108 .text.MX_TIM2_Init:0000000000000000 MX_TIM2_Init /tmp/ccdsDELB.s:3286 .text.MX_TIM2_Init:0000000000000088 $d /tmp/ccdsDELB.s:3295 .text.MX_TIM5_Init:0000000000000000 $t /tmp/ccdsDELB.s:3301 .text.MX_TIM5_Init:0000000000000000 MX_TIM5_Init /tmp/ccdsDELB.s:3478 .text.MX_TIM5_Init:0000000000000084 $d /tmp/ccdsDELB.s:3487 .text.MX_TIM7_Init:0000000000000000 $t /tmp/ccdsDELB.s:3493 .text.MX_TIM7_Init:0000000000000000 MX_TIM7_Init /tmp/ccdsDELB.s:3654 .text.MX_TIM7_Init:000000000000007c $d /tmp/ccdsDELB.s:3662 .text.MX_TIM6_Init:0000000000000000 $t /tmp/ccdsDELB.s:3668 .text.MX_TIM6_Init:0000000000000000 MX_TIM6_Init /tmp/ccdsDELB.s:3829 .text.MX_TIM6_Init:000000000000007c $d /tmp/ccdsDELB.s:3837 .rodata.Decode_uart.str1.4:0000000000000000 $d /tmp/ccdsDELB.s:3844 .text.Decode_uart:0000000000000000 $t /tmp/ccdsDELB.s:3850 .text.Decode_uart:0000000000000000 Decode_uart /tmp/ccdsDELB.s:4413 .text.Decode_uart:00000000000002cc $d /tmp/ccdsDELB.s:4428 .text.Init_params:0000000000000000 $t /tmp/ccdsDELB.s:4434 .text.Init_params:0000000000000000 Init_params ARM GAS /tmp/ccdsDELB.s page 533 /tmp/ccdsDELB.s:5077 .text.Init_params:0000000000000278 $d /tmp/ccdsDELB.s:5116 .text.Get_ADC:0000000000000000 $t /tmp/ccdsDELB.s:5122 .text.Get_ADC:0000000000000000 Get_ADC /tmp/ccdsDELB.s:5142 .text.Get_ADC:000000000000000c $d /tmp/ccdsDELB.s:5148 .text.Get_ADC:0000000000000012 $t /tmp/ccdsDELB.s:5246 .text.Get_ADC:0000000000000068 $d /tmp/ccdsDELB.s:5252 .text.Stop_TIM10:0000000000000000 $t /tmp/ccdsDELB.s:5258 .text.Stop_TIM10:0000000000000000 Stop_TIM10 /tmp/ccdsDELB.s:5287 .text.Stop_TIM10:0000000000000014 $d /tmp/ccdsDELB.s:5294 .text.CalculateChecksum:0000000000000000 $t /tmp/ccdsDELB.s:5301 .text.CalculateChecksum:0000000000000000 CalculateChecksum /tmp/ccdsDELB.s:5348 .text.CheckChecksum:0000000000000000 $t /tmp/ccdsDELB.s:5355 .text.CheckChecksum:0000000000000000 CheckChecksum /tmp/ccdsDELB.s:5417 .text.CheckChecksum:000000000000003c $d /tmp/ccdsDELB.s:5424 .rodata.SD_SAVE.str1.4:0000000000000000 $d /tmp/ccdsDELB.s:5428 .text.SD_SAVE:0000000000000000 $t /tmp/ccdsDELB.s:5435 .text.SD_SAVE:0000000000000000 SD_SAVE /tmp/ccdsDELB.s:5504 .text.SD_SAVE:0000000000000030 $d /tmp/ccdsDELB.s:5511 .text.SD_READ:0000000000000000 $t /tmp/ccdsDELB.s:5518 .text.SD_READ:0000000000000000 SD_READ /tmp/ccdsDELB.s:5596 .text.SD_READ:000000000000003c $d /tmp/ccdsDELB.s:5604 .text.SD_REMOVE:0000000000000000 $t /tmp/ccdsDELB.s:5611 .text.SD_REMOVE:0000000000000000 SD_REMOVE /tmp/ccdsDELB.s:5679 .text.SD_REMOVE:0000000000000034 $d /tmp/ccdsDELB.s:5686 .text.USART_TX:0000000000000000 $t /tmp/ccdsDELB.s:5693 .text.USART_TX:0000000000000000 USART_TX /tmp/ccdsDELB.s:5770 .text.USART_TX:0000000000000028 $d /tmp/ccdsDELB.s:5775 .text.USART_TX_DMA:0000000000000000 $t /tmp/ccdsDELB.s:5782 .text.USART_TX_DMA:0000000000000000 USART_TX_DMA /tmp/ccdsDELB.s:5854 .text.USART_TX_DMA:0000000000000038 $d /tmp/ccdsDELB.s:5861 .text.Error_Handler:0000000000000000 $t /tmp/ccdsDELB.s:5868 .text.Error_Handler:0000000000000000 Error_Handler /tmp/ccdsDELB.s:5899 .text.MX_ADC1_Init:0000000000000000 $t /tmp/ccdsDELB.s:5905 .text.MX_ADC1_Init:0000000000000000 MX_ADC1_Init /tmp/ccdsDELB.s:6094 .text.MX_ADC1_Init:00000000000000bc $d /tmp/ccdsDELB.s:6101 .text.MX_ADC3_Init:0000000000000000 $t /tmp/ccdsDELB.s:6107 .text.MX_ADC3_Init:0000000000000000 MX_ADC3_Init /tmp/ccdsDELB.s:6214 .text.MX_ADC3_Init:0000000000000060 $d /tmp/ccdsDELB.s:6221 .text.MX_USART1_UART_Init:0000000000000000 $t /tmp/ccdsDELB.s:6227 .text.MX_USART1_UART_Init:0000000000000000 MX_USART1_UART_Init /tmp/ccdsDELB.s:6626 .text.MX_USART1_UART_Init:000000000000017c $d /tmp/ccdsDELB.s:6635 .text.MX_TIM10_Init:0000000000000000 $t /tmp/ccdsDELB.s:6641 .text.MX_TIM10_Init:0000000000000000 MX_TIM10_Init /tmp/ccdsDELB.s:6690 .text.MX_TIM10_Init:0000000000000024 $d /tmp/ccdsDELB.s:6696 .text.SystemClock_Config:0000000000000000 $t /tmp/ccdsDELB.s:6703 .text.SystemClock_Config:0000000000000000 SystemClock_Config /tmp/ccdsDELB.s:6862 .text.SystemClock_Config:00000000000000ac $d /tmp/ccdsDELB.s:6868 .text.main:0000000000000000 $t /tmp/ccdsDELB.s:6875 .text.main:0000000000000000 main /tmp/ccdsDELB.s:7208 .text.main:00000000000000f0 $d /tmp/ccdsDELB.s:7218 .text.main:0000000000000118 $t /tmp/ccdsDELB.s:7468 .text.main:0000000000000224 $d /tmp/ccdsDELB.s:7492 .text.main:0000000000000278 $t /tmp/ccdsDELB.s:8034 .text.main:000000000000052c $d /tmp/ccdsDELB.s:8063 .text.main:0000000000000594 $t /tmp/ccdsDELB.s:8621 .text.main:0000000000000840 $d /tmp/ccdsDELB.s:8964 .bss.task:0000000000000000 task ARM GAS /tmp/ccdsDELB.s page 534 /tmp/ccdsDELB.s:8773 .bss.LD2_param:0000000000000000 LD2_param /tmp/ccdsDELB.s:8752 .bss.LD1_param:0000000000000000 LD1_param /tmp/ccdsDELB.s:8731 .bss.Def_setup:0000000000000000 Def_setup /tmp/ccdsDELB.s:8724 .bss.Curr_setup:0000000000000000 Curr_setup /tmp/ccdsDELB.s:8766 .bss.LD2_def_setup:0000000000000000 LD2_def_setup /tmp/ccdsDELB.s:8745 .bss.LD1_def_setup:0000000000000000 LD1_def_setup /tmp/ccdsDELB.s:8759 .bss.LD2_curr_setup:0000000000000000 LD2_curr_setup /tmp/ccdsDELB.s:8738 .bss.LD1_curr_setup:0000000000000000 LD1_curr_setup /tmp/ccdsDELB.s:8957 .bss.sizeoffile:0000000000000000 sizeoffile /tmp/ccdsDELB.s:8911 .bss.fgoto:0000000000000000 fgoto /tmp/ccdsDELB.s:8984 .bss.test:0000000000000000 test /tmp/ccdsDELB.s:8922 .bss.fresult:0000000000000000 fresult /tmp/ccdsDELB.s:8698 .bss.COMMAND:0000000000000000 COMMAND /tmp/ccdsDELB.s:8780 .bss.Long_Data:0000000000000000 Long_Data /tmp/ccdsDELB.s:8971 .bss.temp16:0000000000000000 temp16 /tmp/ccdsDELB.s:8717 .bss.CS_result:0000000000000000 CS_result /tmp/ccdsDELB.s:8891 .bss.UART_header:0000000000000000 UART_header /tmp/ccdsDELB.s:8898 .bss.UART_rec_incr:0000000000000000 UART_rec_incr /tmp/ccdsDELB.s:8807 .bss.TIM10_coflag:0000000000000000 TIM10_coflag /tmp/ccdsDELB.s:8990 .bss.u_rx_flg:0000000000000000 u_rx_flg /tmp/ccdsDELB.s:8996 .bss.u_tx_flg:0000000000000000 u_tx_flg /tmp/ccdsDELB.s:8917 .bss.flg_tmt:0000000000000000 flg_tmt /tmp/ccdsDELB.s:8884 .bss.UART_DATA:0000000000000000 UART_DATA /tmp/ccdsDELB.s:8801 .bss.State_Data:0000000000000000 State_Data /tmp/ccdsDELB.s:8904 .bss.UART_transmission_request:0000000000000000 UART_transmission_request /tmp/ccdsDELB.s:8710 .bss.CPU_state_old:0000000000000000 CPU_state_old /tmp/ccdsDELB.s:8704 .bss.CPU_state:0000000000000000 CPU_state /tmp/ccdsDELB.s:9001 .bss.uart_buf:0000000000000000 uart_buf /tmp/ccdsDELB.s:8814 .bss.TIM10_period:0000000000000000 TIM10_period /tmp/ccdsDELB.s:8828 .bss.TO10_counter:0000000000000000 TO10_counter /tmp/ccdsDELB.s:8821 .bss.TO10:0000000000000000 TO10 /tmp/ccdsDELB.s:8870 .bss.TO7_PID:0000000000000000 TO7_PID /tmp/ccdsDELB.s:8877 .bss.TO7_before:0000000000000000 TO7_before /tmp/ccdsDELB.s:8863 .bss.TO7:0000000000000000 TO7 /tmp/ccdsDELB.s:8977 .bss.temp32:0000000000000000 temp32 /tmp/ccdsDELB.s:8794 .bss.SD_SLIDE:0000000000000000 SD_SLIDE /tmp/ccdsDELB.s:8787 .bss.SD_SEEK:0000000000000000 SD_SEEK /tmp/ccdsDELB.s:8856 .bss.TO6_uart:0000000000000000 TO6_uart /tmp/ccdsDELB.s:8849 .bss.TO6_stop:0000000000000000 TO6_stop /tmp/ccdsDELB.s:8842 .bss.TO6_before:0000000000000000 TO6_before /tmp/ccdsDELB.s:8835 .bss.TO6:0000000000000000 TO6 /tmp/ccdsDELB.s:8950 .bss.htim10:0000000000000000 htim10 /tmp/ccdsDELB.s:8943 .bss.hsd1:0000000000000000 hsd1 /tmp/ccdsDELB.s:8936 .bss.hadc3:0000000000000000 hadc3 /tmp/ccdsDELB.s:8929 .bss.hadc1:0000000000000000 hadc1 /tmp/ccdsDELB.s:8694 .bss.COMMAND:0000000000000000 $d /tmp/ccdsDELB.s:8705 .bss.CPU_state:0000000000000000 $d /tmp/ccdsDELB.s:8711 .bss.CPU_state_old:0000000000000000 $d /tmp/ccdsDELB.s:8713 .bss.CS_result:0000000000000000 $d /tmp/ccdsDELB.s:8720 .bss.Curr_setup:0000000000000000 $d /tmp/ccdsDELB.s:8727 .bss.Def_setup:0000000000000000 $d /tmp/ccdsDELB.s:8734 .bss.LD1_curr_setup:0000000000000000 $d /tmp/ccdsDELB.s:8741 .bss.LD1_def_setup:0000000000000000 $d /tmp/ccdsDELB.s:8748 .bss.LD1_param:0000000000000000 $d /tmp/ccdsDELB.s:8755 .bss.LD2_curr_setup:0000000000000000 $d /tmp/ccdsDELB.s:8762 .bss.LD2_def_setup:0000000000000000 $d /tmp/ccdsDELB.s:8769 .bss.LD2_param:0000000000000000 $d ARM GAS /tmp/ccdsDELB.s page 535 /tmp/ccdsDELB.s:8776 .bss.Long_Data:0000000000000000 $d /tmp/ccdsDELB.s:8783 .bss.SD_SEEK:0000000000000000 $d /tmp/ccdsDELB.s:8790 .bss.SD_SLIDE:0000000000000000 $d /tmp/ccdsDELB.s:8797 .bss.State_Data:0000000000000000 $d /tmp/ccdsDELB.s:8808 .bss.TIM10_coflag:0000000000000000 $d /tmp/ccdsDELB.s:8810 .bss.TIM10_period:0000000000000000 $d /tmp/ccdsDELB.s:8817 .bss.TO10:0000000000000000 $d /tmp/ccdsDELB.s:8824 .bss.TO10_counter:0000000000000000 $d /tmp/ccdsDELB.s:8831 .bss.TO6:0000000000000000 $d /tmp/ccdsDELB.s:8838 .bss.TO6_before:0000000000000000 $d /tmp/ccdsDELB.s:8845 .bss.TO6_stop:0000000000000000 $d /tmp/ccdsDELB.s:8852 .bss.TO6_uart:0000000000000000 $d /tmp/ccdsDELB.s:8859 .bss.TO7:0000000000000000 $d /tmp/ccdsDELB.s:8866 .bss.TO7_PID:0000000000000000 $d /tmp/ccdsDELB.s:8873 .bss.TO7_before:0000000000000000 $d /tmp/ccdsDELB.s:8880 .bss.UART_DATA:0000000000000000 $d /tmp/ccdsDELB.s:8887 .bss.UART_header:0000000000000000 $d /tmp/ccdsDELB.s:8894 .bss.UART_rec_incr:0000000000000000 $d /tmp/ccdsDELB.s:8905 .bss.UART_transmission_request:0000000000000000 $d /tmp/ccdsDELB.s:8907 .bss.fgoto:0000000000000000 $d /tmp/ccdsDELB.s:8918 .bss.flg_tmt:0000000000000000 $d /tmp/ccdsDELB.s:8923 .bss.fresult:0000000000000000 $d /tmp/ccdsDELB.s:8925 .bss.hadc1:0000000000000000 $d /tmp/ccdsDELB.s:8932 .bss.hadc3:0000000000000000 $d /tmp/ccdsDELB.s:8939 .bss.hsd1:0000000000000000 $d /tmp/ccdsDELB.s:8946 .bss.htim10:0000000000000000 $d /tmp/ccdsDELB.s:8953 .bss.sizeoffile:0000000000000000 $d /tmp/ccdsDELB.s:8960 .bss.task:0000000000000000 $d /tmp/ccdsDELB.s:8967 .bss.temp16:0000000000000000 $d /tmp/ccdsDELB.s:8974 .bss.temp32:0000000000000000 $d /tmp/ccdsDELB.s:8980 .bss.test:0000000000000000 $d /tmp/ccdsDELB.s:8991 .bss.u_rx_flg:0000000000000000 $d /tmp/ccdsDELB.s:8997 .bss.u_tx_flg:0000000000000000 $d /tmp/ccdsDELB.s:9002 .bss.uart_buf:0000000000000000 $d UNDEFINED SYMBOLS HAL_GPIO_WritePin HAL_GPIO_Init memset LL_GPIO_Init LL_SPI_Init LL_TIM_Init HAL_GPIO_ReadPin Mount_SD Remove_File Create_File Write_File_byte Update_File_byte Unmount_SD Seek_Read_File HAL_ADC_Start HAL_ADC_PollForConversion HAL_ADC_GetValue HAL_ADC_Stop HAL_TIM_Base_Stop_IT HAL_ADC_Init HAL_ADC_ConfigChannel ARM GAS /tmp/ccdsDELB.s page 536 HAL_RCCEx_PeriphCLKConfig LL_USART_Init HAL_TIM_Base_Init HAL_RCC_OscConfig HAL_PWREx_EnableOverDrive HAL_RCC_ClockConfig HAL_Init MX_FATFS_Init HAL_TIM_Base_Start_IT