ARM GAS /tmp/ccLSPxIe.s page 1 1 .cpu cortex-m7 2 .arch armv7e-m 3 .fpu fpv5-d16 4 .eabi_attribute 28, 1 5 .eabi_attribute 20, 1 6 .eabi_attribute 21, 1 7 .eabi_attribute 23, 3 8 .eabi_attribute 24, 1 9 .eabi_attribute 25, 1 10 .eabi_attribute 26, 1 11 .eabi_attribute 30, 1 12 .eabi_attribute 34, 1 13 .eabi_attribute 18, 4 14 .file "main.c" 15 .text 16 .Ltext0: 17 .cfi_sections .debug_frame 18 .file 1 "Src/main.c" 19 .section .text.NVIC_EncodePriority,"ax",%progbits 20 .align 1 21 .syntax unified 22 .thumb 23 .thumb_func 25 NVIC_EncodePriority: 26 .LVL0: 27 .LFB113: 28 .file 2 "Drivers/CMSIS/Include/core_cm7.h" 1:Drivers/CMSIS/Include/core_cm7.h **** /**************************************************************************//** 2:Drivers/CMSIS/Include/core_cm7.h **** * @file core_cm7.h 3:Drivers/CMSIS/Include/core_cm7.h **** * @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File 4:Drivers/CMSIS/Include/core_cm7.h **** * @version V5.0.8 5:Drivers/CMSIS/Include/core_cm7.h **** * @date 04. June 2018 6:Drivers/CMSIS/Include/core_cm7.h **** ******************************************************************************/ 7:Drivers/CMSIS/Include/core_cm7.h **** /* 8:Drivers/CMSIS/Include/core_cm7.h **** * Copyright (c) 2009-2018 Arm Limited. All rights reserved. 9:Drivers/CMSIS/Include/core_cm7.h **** * 10:Drivers/CMSIS/Include/core_cm7.h **** * SPDX-License-Identifier: Apache-2.0 11:Drivers/CMSIS/Include/core_cm7.h **** * 12:Drivers/CMSIS/Include/core_cm7.h **** * Licensed under the Apache License, Version 2.0 (the License); you may 13:Drivers/CMSIS/Include/core_cm7.h **** * not use this file except in compliance with the License. 14:Drivers/CMSIS/Include/core_cm7.h **** * You may obtain a copy of the License at 15:Drivers/CMSIS/Include/core_cm7.h **** * 16:Drivers/CMSIS/Include/core_cm7.h **** * www.apache.org/licenses/LICENSE-2.0 17:Drivers/CMSIS/Include/core_cm7.h **** * 18:Drivers/CMSIS/Include/core_cm7.h **** * Unless required by applicable law or agreed to in writing, software 19:Drivers/CMSIS/Include/core_cm7.h **** * distributed under the License is distributed on an AS IS BASIS, WITHOUT 20:Drivers/CMSIS/Include/core_cm7.h **** * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 21:Drivers/CMSIS/Include/core_cm7.h **** * See the License for the specific language governing permissions and 22:Drivers/CMSIS/Include/core_cm7.h **** * limitations under the License. 23:Drivers/CMSIS/Include/core_cm7.h **** */ 24:Drivers/CMSIS/Include/core_cm7.h **** 25:Drivers/CMSIS/Include/core_cm7.h **** #if defined ( __ICCARM__ ) 26:Drivers/CMSIS/Include/core_cm7.h **** #pragma system_include /* treat file as system include file for MISRA check */ 27:Drivers/CMSIS/Include/core_cm7.h **** #elif defined (__clang__) 28:Drivers/CMSIS/Include/core_cm7.h **** #pragma clang system_header /* treat file as system include file */ 29:Drivers/CMSIS/Include/core_cm7.h **** #endif 30:Drivers/CMSIS/Include/core_cm7.h **** ARM GAS /tmp/ccLSPxIe.s page 2 31:Drivers/CMSIS/Include/core_cm7.h **** #ifndef __CORE_CM7_H_GENERIC 32:Drivers/CMSIS/Include/core_cm7.h **** #define __CORE_CM7_H_GENERIC 33:Drivers/CMSIS/Include/core_cm7.h **** 34:Drivers/CMSIS/Include/core_cm7.h **** #include 35:Drivers/CMSIS/Include/core_cm7.h **** 36:Drivers/CMSIS/Include/core_cm7.h **** #ifdef __cplusplus 37:Drivers/CMSIS/Include/core_cm7.h **** extern "C" { 38:Drivers/CMSIS/Include/core_cm7.h **** #endif 39:Drivers/CMSIS/Include/core_cm7.h **** 40:Drivers/CMSIS/Include/core_cm7.h **** /** 41:Drivers/CMSIS/Include/core_cm7.h **** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions 42:Drivers/CMSIS/Include/core_cm7.h **** CMSIS violates the following MISRA-C:2004 rules: 43:Drivers/CMSIS/Include/core_cm7.h **** 44:Drivers/CMSIS/Include/core_cm7.h **** \li Required Rule 8.5, object/function definition in header file.
45:Drivers/CMSIS/Include/core_cm7.h **** Function definitions in header files are used to allow 'inlining'. 46:Drivers/CMSIS/Include/core_cm7.h **** 47:Drivers/CMSIS/Include/core_cm7.h **** \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
48:Drivers/CMSIS/Include/core_cm7.h **** Unions are used for effective representation of core registers. 49:Drivers/CMSIS/Include/core_cm7.h **** 50:Drivers/CMSIS/Include/core_cm7.h **** \li Advisory Rule 19.7, Function-like macro defined.
51:Drivers/CMSIS/Include/core_cm7.h **** Function-like macros are used to allow more efficient code. 52:Drivers/CMSIS/Include/core_cm7.h **** */ 53:Drivers/CMSIS/Include/core_cm7.h **** 54:Drivers/CMSIS/Include/core_cm7.h **** 55:Drivers/CMSIS/Include/core_cm7.h **** /******************************************************************************* 56:Drivers/CMSIS/Include/core_cm7.h **** * CMSIS definitions 57:Drivers/CMSIS/Include/core_cm7.h **** ******************************************************************************/ 58:Drivers/CMSIS/Include/core_cm7.h **** /** 59:Drivers/CMSIS/Include/core_cm7.h **** \ingroup Cortex_M7 60:Drivers/CMSIS/Include/core_cm7.h **** @{ 61:Drivers/CMSIS/Include/core_cm7.h **** */ 62:Drivers/CMSIS/Include/core_cm7.h **** 63:Drivers/CMSIS/Include/core_cm7.h **** #include "cmsis_version.h" 64:Drivers/CMSIS/Include/core_cm7.h **** 65:Drivers/CMSIS/Include/core_cm7.h **** /* CMSIS CM7 definitions */ 66:Drivers/CMSIS/Include/core_cm7.h **** #define __CM7_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:1 67:Drivers/CMSIS/Include/core_cm7.h **** #define __CM7_CMSIS_VERSION_SUB ( __CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0 68:Drivers/CMSIS/Include/core_cm7.h **** #define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16U) | \ 69:Drivers/CMSIS/Include/core_cm7.h **** __CM7_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS 70:Drivers/CMSIS/Include/core_cm7.h **** 71:Drivers/CMSIS/Include/core_cm7.h **** #define __CORTEX_M (7U) /*!< Cortex-M Core */ 72:Drivers/CMSIS/Include/core_cm7.h **** 73:Drivers/CMSIS/Include/core_cm7.h **** /** __FPU_USED indicates whether an FPU is used or not. 74:Drivers/CMSIS/Include/core_cm7.h **** For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and fun 75:Drivers/CMSIS/Include/core_cm7.h **** */ 76:Drivers/CMSIS/Include/core_cm7.h **** #if defined ( __CC_ARM ) 77:Drivers/CMSIS/Include/core_cm7.h **** #if defined __TARGET_FPU_VFP 78:Drivers/CMSIS/Include/core_cm7.h **** #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) 79:Drivers/CMSIS/Include/core_cm7.h **** #define __FPU_USED 1U 80:Drivers/CMSIS/Include/core_cm7.h **** #else 81:Drivers/CMSIS/Include/core_cm7.h **** #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT) 82:Drivers/CMSIS/Include/core_cm7.h **** #define __FPU_USED 0U 83:Drivers/CMSIS/Include/core_cm7.h **** #endif 84:Drivers/CMSIS/Include/core_cm7.h **** #else 85:Drivers/CMSIS/Include/core_cm7.h **** #define __FPU_USED 0U 86:Drivers/CMSIS/Include/core_cm7.h **** #endif 87:Drivers/CMSIS/Include/core_cm7.h **** ARM GAS /tmp/ccLSPxIe.s page 3 88:Drivers/CMSIS/Include/core_cm7.h **** #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) 89:Drivers/CMSIS/Include/core_cm7.h **** #if defined __ARM_PCS_VFP 90:Drivers/CMSIS/Include/core_cm7.h **** #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) 91:Drivers/CMSIS/Include/core_cm7.h **** #define __FPU_USED 1U 92:Drivers/CMSIS/Include/core_cm7.h **** #else 93:Drivers/CMSIS/Include/core_cm7.h **** #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESEN 94:Drivers/CMSIS/Include/core_cm7.h **** #define __FPU_USED 0U 95:Drivers/CMSIS/Include/core_cm7.h **** #endif 96:Drivers/CMSIS/Include/core_cm7.h **** #else 97:Drivers/CMSIS/Include/core_cm7.h **** #define __FPU_USED 0U 98:Drivers/CMSIS/Include/core_cm7.h **** #endif 99:Drivers/CMSIS/Include/core_cm7.h **** 100:Drivers/CMSIS/Include/core_cm7.h **** #elif defined ( __GNUC__ ) 101:Drivers/CMSIS/Include/core_cm7.h **** #if defined (__VFP_FP__) && !defined(__SOFTFP__) 102:Drivers/CMSIS/Include/core_cm7.h **** #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) 103:Drivers/CMSIS/Include/core_cm7.h **** #define __FPU_USED 1U 104:Drivers/CMSIS/Include/core_cm7.h **** #else 105:Drivers/CMSIS/Include/core_cm7.h **** #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT) 106:Drivers/CMSIS/Include/core_cm7.h **** #define __FPU_USED 0U 107:Drivers/CMSIS/Include/core_cm7.h **** #endif 108:Drivers/CMSIS/Include/core_cm7.h **** #else 109:Drivers/CMSIS/Include/core_cm7.h **** #define __FPU_USED 0U 110:Drivers/CMSIS/Include/core_cm7.h **** #endif 111:Drivers/CMSIS/Include/core_cm7.h **** 112:Drivers/CMSIS/Include/core_cm7.h **** #elif defined ( __ICCARM__ ) 113:Drivers/CMSIS/Include/core_cm7.h **** #if defined __ARMVFP__ 114:Drivers/CMSIS/Include/core_cm7.h **** #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) 115:Drivers/CMSIS/Include/core_cm7.h **** #define __FPU_USED 1U 116:Drivers/CMSIS/Include/core_cm7.h **** #else 117:Drivers/CMSIS/Include/core_cm7.h **** #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT) 118:Drivers/CMSIS/Include/core_cm7.h **** #define __FPU_USED 0U 119:Drivers/CMSIS/Include/core_cm7.h **** #endif 120:Drivers/CMSIS/Include/core_cm7.h **** #else 121:Drivers/CMSIS/Include/core_cm7.h **** #define __FPU_USED 0U 122:Drivers/CMSIS/Include/core_cm7.h **** #endif 123:Drivers/CMSIS/Include/core_cm7.h **** 124:Drivers/CMSIS/Include/core_cm7.h **** #elif defined ( __TI_ARM__ ) 125:Drivers/CMSIS/Include/core_cm7.h **** #if defined __TI_VFP_SUPPORT__ 126:Drivers/CMSIS/Include/core_cm7.h **** #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) 127:Drivers/CMSIS/Include/core_cm7.h **** #define __FPU_USED 1U 128:Drivers/CMSIS/Include/core_cm7.h **** #else 129:Drivers/CMSIS/Include/core_cm7.h **** #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT) 130:Drivers/CMSIS/Include/core_cm7.h **** #define __FPU_USED 0U 131:Drivers/CMSIS/Include/core_cm7.h **** #endif 132:Drivers/CMSIS/Include/core_cm7.h **** #else 133:Drivers/CMSIS/Include/core_cm7.h **** #define __FPU_USED 0U 134:Drivers/CMSIS/Include/core_cm7.h **** #endif 135:Drivers/CMSIS/Include/core_cm7.h **** 136:Drivers/CMSIS/Include/core_cm7.h **** #elif defined ( __TASKING__ ) 137:Drivers/CMSIS/Include/core_cm7.h **** #if defined __FPU_VFP__ 138:Drivers/CMSIS/Include/core_cm7.h **** #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) 139:Drivers/CMSIS/Include/core_cm7.h **** #define __FPU_USED 1U 140:Drivers/CMSIS/Include/core_cm7.h **** #else 141:Drivers/CMSIS/Include/core_cm7.h **** #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT) 142:Drivers/CMSIS/Include/core_cm7.h **** #define __FPU_USED 0U 143:Drivers/CMSIS/Include/core_cm7.h **** #endif 144:Drivers/CMSIS/Include/core_cm7.h **** #else ARM GAS /tmp/ccLSPxIe.s page 4 145:Drivers/CMSIS/Include/core_cm7.h **** #define __FPU_USED 0U 146:Drivers/CMSIS/Include/core_cm7.h **** #endif 147:Drivers/CMSIS/Include/core_cm7.h **** 148:Drivers/CMSIS/Include/core_cm7.h **** #elif defined ( __CSMC__ ) 149:Drivers/CMSIS/Include/core_cm7.h **** #if ( __CSMC__ & 0x400U) 150:Drivers/CMSIS/Include/core_cm7.h **** #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) 151:Drivers/CMSIS/Include/core_cm7.h **** #define __FPU_USED 1U 152:Drivers/CMSIS/Include/core_cm7.h **** #else 153:Drivers/CMSIS/Include/core_cm7.h **** #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT) 154:Drivers/CMSIS/Include/core_cm7.h **** #define __FPU_USED 0U 155:Drivers/CMSIS/Include/core_cm7.h **** #endif 156:Drivers/CMSIS/Include/core_cm7.h **** #else 157:Drivers/CMSIS/Include/core_cm7.h **** #define __FPU_USED 0U 158:Drivers/CMSIS/Include/core_cm7.h **** #endif 159:Drivers/CMSIS/Include/core_cm7.h **** 160:Drivers/CMSIS/Include/core_cm7.h **** #endif 161:Drivers/CMSIS/Include/core_cm7.h **** 162:Drivers/CMSIS/Include/core_cm7.h **** #include "cmsis_compiler.h" /* CMSIS compiler specific defines */ 163:Drivers/CMSIS/Include/core_cm7.h **** 164:Drivers/CMSIS/Include/core_cm7.h **** 165:Drivers/CMSIS/Include/core_cm7.h **** #ifdef __cplusplus 166:Drivers/CMSIS/Include/core_cm7.h **** } 167:Drivers/CMSIS/Include/core_cm7.h **** #endif 168:Drivers/CMSIS/Include/core_cm7.h **** 169:Drivers/CMSIS/Include/core_cm7.h **** #endif /* __CORE_CM7_H_GENERIC */ 170:Drivers/CMSIS/Include/core_cm7.h **** 171:Drivers/CMSIS/Include/core_cm7.h **** #ifndef __CMSIS_GENERIC 172:Drivers/CMSIS/Include/core_cm7.h **** 173:Drivers/CMSIS/Include/core_cm7.h **** #ifndef __CORE_CM7_H_DEPENDANT 174:Drivers/CMSIS/Include/core_cm7.h **** #define __CORE_CM7_H_DEPENDANT 175:Drivers/CMSIS/Include/core_cm7.h **** 176:Drivers/CMSIS/Include/core_cm7.h **** #ifdef __cplusplus 177:Drivers/CMSIS/Include/core_cm7.h **** extern "C" { 178:Drivers/CMSIS/Include/core_cm7.h **** #endif 179:Drivers/CMSIS/Include/core_cm7.h **** 180:Drivers/CMSIS/Include/core_cm7.h **** /* check device defines and use defaults */ 181:Drivers/CMSIS/Include/core_cm7.h **** #if defined __CHECK_DEVICE_DEFINES 182:Drivers/CMSIS/Include/core_cm7.h **** #ifndef __CM7_REV 183:Drivers/CMSIS/Include/core_cm7.h **** #define __CM7_REV 0x0000U 184:Drivers/CMSIS/Include/core_cm7.h **** #warning "__CM7_REV not defined in device header file; using default!" 185:Drivers/CMSIS/Include/core_cm7.h **** #endif 186:Drivers/CMSIS/Include/core_cm7.h **** 187:Drivers/CMSIS/Include/core_cm7.h **** #ifndef __FPU_PRESENT 188:Drivers/CMSIS/Include/core_cm7.h **** #define __FPU_PRESENT 0U 189:Drivers/CMSIS/Include/core_cm7.h **** #warning "__FPU_PRESENT not defined in device header file; using default!" 190:Drivers/CMSIS/Include/core_cm7.h **** #endif 191:Drivers/CMSIS/Include/core_cm7.h **** 192:Drivers/CMSIS/Include/core_cm7.h **** #ifndef __MPU_PRESENT 193:Drivers/CMSIS/Include/core_cm7.h **** #define __MPU_PRESENT 0U 194:Drivers/CMSIS/Include/core_cm7.h **** #warning "__MPU_PRESENT not defined in device header file; using default!" 195:Drivers/CMSIS/Include/core_cm7.h **** #endif 196:Drivers/CMSIS/Include/core_cm7.h **** 197:Drivers/CMSIS/Include/core_cm7.h **** #ifndef __ICACHE_PRESENT 198:Drivers/CMSIS/Include/core_cm7.h **** #define __ICACHE_PRESENT 0U 199:Drivers/CMSIS/Include/core_cm7.h **** #warning "__ICACHE_PRESENT not defined in device header file; using default!" 200:Drivers/CMSIS/Include/core_cm7.h **** #endif 201:Drivers/CMSIS/Include/core_cm7.h **** ARM GAS /tmp/ccLSPxIe.s page 5 202:Drivers/CMSIS/Include/core_cm7.h **** #ifndef __DCACHE_PRESENT 203:Drivers/CMSIS/Include/core_cm7.h **** #define __DCACHE_PRESENT 0U 204:Drivers/CMSIS/Include/core_cm7.h **** #warning "__DCACHE_PRESENT not defined in device header file; using default!" 205:Drivers/CMSIS/Include/core_cm7.h **** #endif 206:Drivers/CMSIS/Include/core_cm7.h **** 207:Drivers/CMSIS/Include/core_cm7.h **** #ifndef __DTCM_PRESENT 208:Drivers/CMSIS/Include/core_cm7.h **** #define __DTCM_PRESENT 0U 209:Drivers/CMSIS/Include/core_cm7.h **** #warning "__DTCM_PRESENT not defined in device header file; using default!" 210:Drivers/CMSIS/Include/core_cm7.h **** #endif 211:Drivers/CMSIS/Include/core_cm7.h **** 212:Drivers/CMSIS/Include/core_cm7.h **** #ifndef __NVIC_PRIO_BITS 213:Drivers/CMSIS/Include/core_cm7.h **** #define __NVIC_PRIO_BITS 3U 214:Drivers/CMSIS/Include/core_cm7.h **** #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" 215:Drivers/CMSIS/Include/core_cm7.h **** #endif 216:Drivers/CMSIS/Include/core_cm7.h **** 217:Drivers/CMSIS/Include/core_cm7.h **** #ifndef __Vendor_SysTickConfig 218:Drivers/CMSIS/Include/core_cm7.h **** #define __Vendor_SysTickConfig 0U 219:Drivers/CMSIS/Include/core_cm7.h **** #warning "__Vendor_SysTickConfig not defined in device header file; using default!" 220:Drivers/CMSIS/Include/core_cm7.h **** #endif 221:Drivers/CMSIS/Include/core_cm7.h **** #endif 222:Drivers/CMSIS/Include/core_cm7.h **** 223:Drivers/CMSIS/Include/core_cm7.h **** /* IO definitions (access restrictions to peripheral registers) */ 224:Drivers/CMSIS/Include/core_cm7.h **** /** 225:Drivers/CMSIS/Include/core_cm7.h **** \defgroup CMSIS_glob_defs CMSIS Global Defines 226:Drivers/CMSIS/Include/core_cm7.h **** 227:Drivers/CMSIS/Include/core_cm7.h **** IO Type Qualifiers are used 228:Drivers/CMSIS/Include/core_cm7.h **** \li to specify the access to peripheral variables. 229:Drivers/CMSIS/Include/core_cm7.h **** \li for automatic generation of peripheral register debug information. 230:Drivers/CMSIS/Include/core_cm7.h **** */ 231:Drivers/CMSIS/Include/core_cm7.h **** #ifdef __cplusplus 232:Drivers/CMSIS/Include/core_cm7.h **** #define __I volatile /*!< Defines 'read only' permissions */ 233:Drivers/CMSIS/Include/core_cm7.h **** #else 234:Drivers/CMSIS/Include/core_cm7.h **** #define __I volatile const /*!< Defines 'read only' permissions */ 235:Drivers/CMSIS/Include/core_cm7.h **** #endif 236:Drivers/CMSIS/Include/core_cm7.h **** #define __O volatile /*!< Defines 'write only' permissions */ 237:Drivers/CMSIS/Include/core_cm7.h **** #define __IO volatile /*!< Defines 'read / write' permissions */ 238:Drivers/CMSIS/Include/core_cm7.h **** 239:Drivers/CMSIS/Include/core_cm7.h **** /* following defines should be used for structure members */ 240:Drivers/CMSIS/Include/core_cm7.h **** #define __IM volatile const /*! Defines 'read only' structure member permissions */ 241:Drivers/CMSIS/Include/core_cm7.h **** #define __OM volatile /*! Defines 'write only' structure member permissions */ 242:Drivers/CMSIS/Include/core_cm7.h **** #define __IOM volatile /*! Defines 'read / write' structure member permissions */ 243:Drivers/CMSIS/Include/core_cm7.h **** 244:Drivers/CMSIS/Include/core_cm7.h **** /*@} end of group Cortex_M7 */ 245:Drivers/CMSIS/Include/core_cm7.h **** 246:Drivers/CMSIS/Include/core_cm7.h **** 247:Drivers/CMSIS/Include/core_cm7.h **** 248:Drivers/CMSIS/Include/core_cm7.h **** /******************************************************************************* 249:Drivers/CMSIS/Include/core_cm7.h **** * Register Abstraction 250:Drivers/CMSIS/Include/core_cm7.h **** Core Register contain: 251:Drivers/CMSIS/Include/core_cm7.h **** - Core Register 252:Drivers/CMSIS/Include/core_cm7.h **** - Core NVIC Register 253:Drivers/CMSIS/Include/core_cm7.h **** - Core SCB Register 254:Drivers/CMSIS/Include/core_cm7.h **** - Core SysTick Register 255:Drivers/CMSIS/Include/core_cm7.h **** - Core Debug Register 256:Drivers/CMSIS/Include/core_cm7.h **** - Core MPU Register 257:Drivers/CMSIS/Include/core_cm7.h **** - Core FPU Register 258:Drivers/CMSIS/Include/core_cm7.h **** ******************************************************************************/ ARM GAS /tmp/ccLSPxIe.s page 6 259:Drivers/CMSIS/Include/core_cm7.h **** /** 260:Drivers/CMSIS/Include/core_cm7.h **** \defgroup CMSIS_core_register Defines and Type Definitions 261:Drivers/CMSIS/Include/core_cm7.h **** \brief Type definitions and defines for Cortex-M processor based devices. 262:Drivers/CMSIS/Include/core_cm7.h **** */ 263:Drivers/CMSIS/Include/core_cm7.h **** 264:Drivers/CMSIS/Include/core_cm7.h **** /** 265:Drivers/CMSIS/Include/core_cm7.h **** \ingroup CMSIS_core_register 266:Drivers/CMSIS/Include/core_cm7.h **** \defgroup CMSIS_CORE Status and Control Registers 267:Drivers/CMSIS/Include/core_cm7.h **** \brief Core Register type definitions. 268:Drivers/CMSIS/Include/core_cm7.h **** @{ 269:Drivers/CMSIS/Include/core_cm7.h **** */ 270:Drivers/CMSIS/Include/core_cm7.h **** 271:Drivers/CMSIS/Include/core_cm7.h **** /** 272:Drivers/CMSIS/Include/core_cm7.h **** \brief Union type to access the Application Program Status Register (APSR). 273:Drivers/CMSIS/Include/core_cm7.h **** */ 274:Drivers/CMSIS/Include/core_cm7.h **** typedef union 275:Drivers/CMSIS/Include/core_cm7.h **** { 276:Drivers/CMSIS/Include/core_cm7.h **** struct 277:Drivers/CMSIS/Include/core_cm7.h **** { 278:Drivers/CMSIS/Include/core_cm7.h **** uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ 279:Drivers/CMSIS/Include/core_cm7.h **** uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ 280:Drivers/CMSIS/Include/core_cm7.h **** uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ 281:Drivers/CMSIS/Include/core_cm7.h **** uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ 282:Drivers/CMSIS/Include/core_cm7.h **** uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ 283:Drivers/CMSIS/Include/core_cm7.h **** uint32_t C:1; /*!< bit: 29 Carry condition code flag */ 284:Drivers/CMSIS/Include/core_cm7.h **** uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ 285:Drivers/CMSIS/Include/core_cm7.h **** uint32_t N:1; /*!< bit: 31 Negative condition code flag */ 286:Drivers/CMSIS/Include/core_cm7.h **** } b; /*!< Structure used for bit access */ 287:Drivers/CMSIS/Include/core_cm7.h **** uint32_t w; /*!< Type used for word access */ 288:Drivers/CMSIS/Include/core_cm7.h **** } APSR_Type; 289:Drivers/CMSIS/Include/core_cm7.h **** 290:Drivers/CMSIS/Include/core_cm7.h **** /* APSR Register Definitions */ 291:Drivers/CMSIS/Include/core_cm7.h **** #define APSR_N_Pos 31U /*!< APSR 292:Drivers/CMSIS/Include/core_cm7.h **** #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR 293:Drivers/CMSIS/Include/core_cm7.h **** 294:Drivers/CMSIS/Include/core_cm7.h **** #define APSR_Z_Pos 30U /*!< APSR 295:Drivers/CMSIS/Include/core_cm7.h **** #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR 296:Drivers/CMSIS/Include/core_cm7.h **** 297:Drivers/CMSIS/Include/core_cm7.h **** #define APSR_C_Pos 29U /*!< APSR 298:Drivers/CMSIS/Include/core_cm7.h **** #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR 299:Drivers/CMSIS/Include/core_cm7.h **** 300:Drivers/CMSIS/Include/core_cm7.h **** #define APSR_V_Pos 28U /*!< APSR 301:Drivers/CMSIS/Include/core_cm7.h **** #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR 302:Drivers/CMSIS/Include/core_cm7.h **** 303:Drivers/CMSIS/Include/core_cm7.h **** #define APSR_Q_Pos 27U /*!< APSR 304:Drivers/CMSIS/Include/core_cm7.h **** #define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR 305:Drivers/CMSIS/Include/core_cm7.h **** 306:Drivers/CMSIS/Include/core_cm7.h **** #define APSR_GE_Pos 16U /*!< APSR 307:Drivers/CMSIS/Include/core_cm7.h **** #define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR 308:Drivers/CMSIS/Include/core_cm7.h **** 309:Drivers/CMSIS/Include/core_cm7.h **** 310:Drivers/CMSIS/Include/core_cm7.h **** /** 311:Drivers/CMSIS/Include/core_cm7.h **** \brief Union type to access the Interrupt Program Status Register (IPSR). 312:Drivers/CMSIS/Include/core_cm7.h **** */ 313:Drivers/CMSIS/Include/core_cm7.h **** typedef union 314:Drivers/CMSIS/Include/core_cm7.h **** { 315:Drivers/CMSIS/Include/core_cm7.h **** struct ARM GAS /tmp/ccLSPxIe.s page 7 316:Drivers/CMSIS/Include/core_cm7.h **** { 317:Drivers/CMSIS/Include/core_cm7.h **** uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ 318:Drivers/CMSIS/Include/core_cm7.h **** uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ 319:Drivers/CMSIS/Include/core_cm7.h **** } b; /*!< Structure used for bit access */ 320:Drivers/CMSIS/Include/core_cm7.h **** uint32_t w; /*!< Type used for word access */ 321:Drivers/CMSIS/Include/core_cm7.h **** } IPSR_Type; 322:Drivers/CMSIS/Include/core_cm7.h **** 323:Drivers/CMSIS/Include/core_cm7.h **** /* IPSR Register Definitions */ 324:Drivers/CMSIS/Include/core_cm7.h **** #define IPSR_ISR_Pos 0U /*!< IPSR 325:Drivers/CMSIS/Include/core_cm7.h **** #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR 326:Drivers/CMSIS/Include/core_cm7.h **** 327:Drivers/CMSIS/Include/core_cm7.h **** 328:Drivers/CMSIS/Include/core_cm7.h **** /** 329:Drivers/CMSIS/Include/core_cm7.h **** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). 330:Drivers/CMSIS/Include/core_cm7.h **** */ 331:Drivers/CMSIS/Include/core_cm7.h **** typedef union 332:Drivers/CMSIS/Include/core_cm7.h **** { 333:Drivers/CMSIS/Include/core_cm7.h **** struct 334:Drivers/CMSIS/Include/core_cm7.h **** { 335:Drivers/CMSIS/Include/core_cm7.h **** uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ 336:Drivers/CMSIS/Include/core_cm7.h **** uint32_t _reserved0:1; /*!< bit: 9 Reserved */ 337:Drivers/CMSIS/Include/core_cm7.h **** uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ 338:Drivers/CMSIS/Include/core_cm7.h **** uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ 339:Drivers/CMSIS/Include/core_cm7.h **** uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ 340:Drivers/CMSIS/Include/core_cm7.h **** uint32_t T:1; /*!< bit: 24 Thumb bit */ 341:Drivers/CMSIS/Include/core_cm7.h **** uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ 342:Drivers/CMSIS/Include/core_cm7.h **** uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ 343:Drivers/CMSIS/Include/core_cm7.h **** uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ 344:Drivers/CMSIS/Include/core_cm7.h **** uint32_t C:1; /*!< bit: 29 Carry condition code flag */ 345:Drivers/CMSIS/Include/core_cm7.h **** uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ 346:Drivers/CMSIS/Include/core_cm7.h **** uint32_t N:1; /*!< bit: 31 Negative condition code flag */ 347:Drivers/CMSIS/Include/core_cm7.h **** } b; /*!< Structure used for bit access */ 348:Drivers/CMSIS/Include/core_cm7.h **** uint32_t w; /*!< Type used for word access */ 349:Drivers/CMSIS/Include/core_cm7.h **** } xPSR_Type; 350:Drivers/CMSIS/Include/core_cm7.h **** 351:Drivers/CMSIS/Include/core_cm7.h **** /* xPSR Register Definitions */ 352:Drivers/CMSIS/Include/core_cm7.h **** #define xPSR_N_Pos 31U /*!< xPSR 353:Drivers/CMSIS/Include/core_cm7.h **** #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR 354:Drivers/CMSIS/Include/core_cm7.h **** 355:Drivers/CMSIS/Include/core_cm7.h **** #define xPSR_Z_Pos 30U /*!< xPSR 356:Drivers/CMSIS/Include/core_cm7.h **** #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR 357:Drivers/CMSIS/Include/core_cm7.h **** 358:Drivers/CMSIS/Include/core_cm7.h **** #define xPSR_C_Pos 29U /*!< xPSR 359:Drivers/CMSIS/Include/core_cm7.h **** #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR 360:Drivers/CMSIS/Include/core_cm7.h **** 361:Drivers/CMSIS/Include/core_cm7.h **** #define xPSR_V_Pos 28U /*!< xPSR 362:Drivers/CMSIS/Include/core_cm7.h **** #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR 363:Drivers/CMSIS/Include/core_cm7.h **** 364:Drivers/CMSIS/Include/core_cm7.h **** #define xPSR_Q_Pos 27U /*!< xPSR 365:Drivers/CMSIS/Include/core_cm7.h **** #define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR 366:Drivers/CMSIS/Include/core_cm7.h **** 367:Drivers/CMSIS/Include/core_cm7.h **** #define xPSR_ICI_IT_2_Pos 25U /*!< xPSR 368:Drivers/CMSIS/Include/core_cm7.h **** #define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR 369:Drivers/CMSIS/Include/core_cm7.h **** 370:Drivers/CMSIS/Include/core_cm7.h **** #define xPSR_T_Pos 24U /*!< xPSR 371:Drivers/CMSIS/Include/core_cm7.h **** #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR 372:Drivers/CMSIS/Include/core_cm7.h **** ARM GAS /tmp/ccLSPxIe.s page 8 373:Drivers/CMSIS/Include/core_cm7.h **** #define xPSR_GE_Pos 16U /*!< xPSR 374:Drivers/CMSIS/Include/core_cm7.h **** #define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR 375:Drivers/CMSIS/Include/core_cm7.h **** 376:Drivers/CMSIS/Include/core_cm7.h **** #define xPSR_ICI_IT_1_Pos 10U /*!< xPSR 377:Drivers/CMSIS/Include/core_cm7.h **** #define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR 378:Drivers/CMSIS/Include/core_cm7.h **** 379:Drivers/CMSIS/Include/core_cm7.h **** #define xPSR_ISR_Pos 0U /*!< xPSR 380:Drivers/CMSIS/Include/core_cm7.h **** #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR 381:Drivers/CMSIS/Include/core_cm7.h **** 382:Drivers/CMSIS/Include/core_cm7.h **** 383:Drivers/CMSIS/Include/core_cm7.h **** /** 384:Drivers/CMSIS/Include/core_cm7.h **** \brief Union type to access the Control Registers (CONTROL). 385:Drivers/CMSIS/Include/core_cm7.h **** */ 386:Drivers/CMSIS/Include/core_cm7.h **** typedef union 387:Drivers/CMSIS/Include/core_cm7.h **** { 388:Drivers/CMSIS/Include/core_cm7.h **** struct 389:Drivers/CMSIS/Include/core_cm7.h **** { 390:Drivers/CMSIS/Include/core_cm7.h **** uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ 391:Drivers/CMSIS/Include/core_cm7.h **** uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ 392:Drivers/CMSIS/Include/core_cm7.h **** uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ 393:Drivers/CMSIS/Include/core_cm7.h **** uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ 394:Drivers/CMSIS/Include/core_cm7.h **** } b; /*!< Structure used for bit access */ 395:Drivers/CMSIS/Include/core_cm7.h **** uint32_t w; /*!< Type used for word access */ 396:Drivers/CMSIS/Include/core_cm7.h **** } CONTROL_Type; 397:Drivers/CMSIS/Include/core_cm7.h **** 398:Drivers/CMSIS/Include/core_cm7.h **** /* CONTROL Register Definitions */ 399:Drivers/CMSIS/Include/core_cm7.h **** #define CONTROL_FPCA_Pos 2U /*!< CONT 400:Drivers/CMSIS/Include/core_cm7.h **** #define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONT 401:Drivers/CMSIS/Include/core_cm7.h **** 402:Drivers/CMSIS/Include/core_cm7.h **** #define CONTROL_SPSEL_Pos 1U /*!< CONT 403:Drivers/CMSIS/Include/core_cm7.h **** #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONT 404:Drivers/CMSIS/Include/core_cm7.h **** 405:Drivers/CMSIS/Include/core_cm7.h **** #define CONTROL_nPRIV_Pos 0U /*!< CONT 406:Drivers/CMSIS/Include/core_cm7.h **** #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONT 407:Drivers/CMSIS/Include/core_cm7.h **** 408:Drivers/CMSIS/Include/core_cm7.h **** /*@} end of group CMSIS_CORE */ 409:Drivers/CMSIS/Include/core_cm7.h **** 410:Drivers/CMSIS/Include/core_cm7.h **** 411:Drivers/CMSIS/Include/core_cm7.h **** /** 412:Drivers/CMSIS/Include/core_cm7.h **** \ingroup CMSIS_core_register 413:Drivers/CMSIS/Include/core_cm7.h **** \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) 414:Drivers/CMSIS/Include/core_cm7.h **** \brief Type definitions for the NVIC Registers 415:Drivers/CMSIS/Include/core_cm7.h **** @{ 416:Drivers/CMSIS/Include/core_cm7.h **** */ 417:Drivers/CMSIS/Include/core_cm7.h **** 418:Drivers/CMSIS/Include/core_cm7.h **** /** 419:Drivers/CMSIS/Include/core_cm7.h **** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). 420:Drivers/CMSIS/Include/core_cm7.h **** */ 421:Drivers/CMSIS/Include/core_cm7.h **** typedef struct 422:Drivers/CMSIS/Include/core_cm7.h **** { 423:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ 424:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED0[24U]; 425:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register 426:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RSERVED1[24U]; 427:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register * 428:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED2[24U]; 429:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register ARM GAS /tmp/ccLSPxIe.s page 9 430:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED3[24U]; 431:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ 432:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED4[56U]; 433:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bi 434:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED5[644U]; 435:Drivers/CMSIS/Include/core_cm7.h **** __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Regis 436:Drivers/CMSIS/Include/core_cm7.h **** } NVIC_Type; 437:Drivers/CMSIS/Include/core_cm7.h **** 438:Drivers/CMSIS/Include/core_cm7.h **** /* Software Triggered Interrupt Register Definitions */ 439:Drivers/CMSIS/Include/core_cm7.h **** #define NVIC_STIR_INTID_Pos 0U /*!< STIR: I 440:Drivers/CMSIS/Include/core_cm7.h **** #define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: I 441:Drivers/CMSIS/Include/core_cm7.h **** 442:Drivers/CMSIS/Include/core_cm7.h **** /*@} end of group CMSIS_NVIC */ 443:Drivers/CMSIS/Include/core_cm7.h **** 444:Drivers/CMSIS/Include/core_cm7.h **** 445:Drivers/CMSIS/Include/core_cm7.h **** /** 446:Drivers/CMSIS/Include/core_cm7.h **** \ingroup CMSIS_core_register 447:Drivers/CMSIS/Include/core_cm7.h **** \defgroup CMSIS_SCB System Control Block (SCB) 448:Drivers/CMSIS/Include/core_cm7.h **** \brief Type definitions for the System Control Block Registers 449:Drivers/CMSIS/Include/core_cm7.h **** @{ 450:Drivers/CMSIS/Include/core_cm7.h **** */ 451:Drivers/CMSIS/Include/core_cm7.h **** 452:Drivers/CMSIS/Include/core_cm7.h **** /** 453:Drivers/CMSIS/Include/core_cm7.h **** \brief Structure type to access the System Control Block (SCB). 454:Drivers/CMSIS/Include/core_cm7.h **** */ 455:Drivers/CMSIS/Include/core_cm7.h **** typedef struct 456:Drivers/CMSIS/Include/core_cm7.h **** { 457:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ 458:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Regi 459:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ 460:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset 461:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ 462:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register * 463:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registe 464:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State 465:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Regist 466:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ 467:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ 468:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register 469:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ 470:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register 471:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ 472:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ 473:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ 474:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t ID_MFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ 475:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t ID_ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Regis 476:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED0[1U]; 477:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ 478:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ 479:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ 480:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ 481:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Regis 482:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED3[93U]; 483:Drivers/CMSIS/Include/core_cm7.h **** __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Reg 484:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED4[15U]; 485:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 486:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 ARM GAS /tmp/ccLSPxIe.s page 10 487:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 488:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED5[1U]; 489:Drivers/CMSIS/Include/core_cm7.h **** __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ 490:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED6[1U]; 491:Drivers/CMSIS/Include/core_cm7.h **** __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU 492:Drivers/CMSIS/Include/core_cm7.h **** __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC 493:Drivers/CMSIS/Include/core_cm7.h **** __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ 494:Drivers/CMSIS/Include/core_cm7.h **** __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ 495:Drivers/CMSIS/Include/core_cm7.h **** __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ 496:Drivers/CMSIS/Include/core_cm7.h **** __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ 497:Drivers/CMSIS/Include/core_cm7.h **** __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by 498:Drivers/CMSIS/Include/core_cm7.h **** __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by 499:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED7[6U]; 500:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memo 501:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Cont 502:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ 503:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ 504:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ 505:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED8[1U]; 506:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Regis 507:Drivers/CMSIS/Include/core_cm7.h **** } SCB_Type; 508:Drivers/CMSIS/Include/core_cm7.h **** 509:Drivers/CMSIS/Include/core_cm7.h **** /* SCB CPUID Register Definitions */ 510:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB 511:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB 512:Drivers/CMSIS/Include/core_cm7.h **** 513:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB 514:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB 515:Drivers/CMSIS/Include/core_cm7.h **** 516:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB 517:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB 518:Drivers/CMSIS/Include/core_cm7.h **** 519:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB 520:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB 521:Drivers/CMSIS/Include/core_cm7.h **** 522:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CPUID_REVISION_Pos 0U /*!< SCB 523:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB 524:Drivers/CMSIS/Include/core_cm7.h **** 525:Drivers/CMSIS/Include/core_cm7.h **** /* SCB Interrupt Control State Register Definitions */ 526:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB 527:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB 528:Drivers/CMSIS/Include/core_cm7.h **** 529:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB 530:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB 531:Drivers/CMSIS/Include/core_cm7.h **** 532:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB 533:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB 534:Drivers/CMSIS/Include/core_cm7.h **** 535:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB 536:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB 537:Drivers/CMSIS/Include/core_cm7.h **** 538:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB 539:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB 540:Drivers/CMSIS/Include/core_cm7.h **** 541:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB 542:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB 543:Drivers/CMSIS/Include/core_cm7.h **** ARM GAS /tmp/ccLSPxIe.s page 11 544:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB 545:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB 546:Drivers/CMSIS/Include/core_cm7.h **** 547:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB 548:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB 549:Drivers/CMSIS/Include/core_cm7.h **** 550:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB 551:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB 552:Drivers/CMSIS/Include/core_cm7.h **** 553:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB 554:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB 555:Drivers/CMSIS/Include/core_cm7.h **** 556:Drivers/CMSIS/Include/core_cm7.h **** /* SCB Vector Table Offset Register Definitions */ 557:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB 558:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB 559:Drivers/CMSIS/Include/core_cm7.h **** 560:Drivers/CMSIS/Include/core_cm7.h **** /* SCB Application Interrupt and Reset Control Register Definitions */ 561:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB 562:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB 563:Drivers/CMSIS/Include/core_cm7.h **** 564:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB 565:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB 566:Drivers/CMSIS/Include/core_cm7.h **** 567:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB 568:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB 569:Drivers/CMSIS/Include/core_cm7.h **** 570:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB 571:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB 572:Drivers/CMSIS/Include/core_cm7.h **** 573:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB 574:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB 575:Drivers/CMSIS/Include/core_cm7.h **** 576:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB 577:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB 578:Drivers/CMSIS/Include/core_cm7.h **** 579:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB 580:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB 581:Drivers/CMSIS/Include/core_cm7.h **** 582:Drivers/CMSIS/Include/core_cm7.h **** /* SCB System Control Register Definitions */ 583:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB 584:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB 585:Drivers/CMSIS/Include/core_cm7.h **** 586:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB 587:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB 588:Drivers/CMSIS/Include/core_cm7.h **** 589:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB 590:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB 591:Drivers/CMSIS/Include/core_cm7.h **** 592:Drivers/CMSIS/Include/core_cm7.h **** /* SCB Configuration Control Register Definitions */ 593:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCR_BP_Pos 18U /*!< SCB 594:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB 595:Drivers/CMSIS/Include/core_cm7.h **** 596:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCR_IC_Pos 17U /*!< SCB 597:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB 598:Drivers/CMSIS/Include/core_cm7.h **** 599:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCR_DC_Pos 16U /*!< SCB 600:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB ARM GAS /tmp/ccLSPxIe.s page 12 601:Drivers/CMSIS/Include/core_cm7.h **** 602:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCR_STKALIGN_Pos 9U /*!< SCB 603:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB 604:Drivers/CMSIS/Include/core_cm7.h **** 605:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB 606:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB 607:Drivers/CMSIS/Include/core_cm7.h **** 608:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB 609:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB 610:Drivers/CMSIS/Include/core_cm7.h **** 611:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB 612:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB 613:Drivers/CMSIS/Include/core_cm7.h **** 614:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB 615:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB 616:Drivers/CMSIS/Include/core_cm7.h **** 617:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB 618:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB 619:Drivers/CMSIS/Include/core_cm7.h **** 620:Drivers/CMSIS/Include/core_cm7.h **** /* SCB System Handler Control and State Register Definitions */ 621:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB 622:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB 623:Drivers/CMSIS/Include/core_cm7.h **** 624:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB 625:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB 626:Drivers/CMSIS/Include/core_cm7.h **** 627:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB 628:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB 629:Drivers/CMSIS/Include/core_cm7.h **** 630:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB 631:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB 632:Drivers/CMSIS/Include/core_cm7.h **** 633:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB 634:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB 635:Drivers/CMSIS/Include/core_cm7.h **** 636:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB 637:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB 638:Drivers/CMSIS/Include/core_cm7.h **** 639:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB 640:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB 641:Drivers/CMSIS/Include/core_cm7.h **** 642:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB 643:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB 644:Drivers/CMSIS/Include/core_cm7.h **** 645:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB 646:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB 647:Drivers/CMSIS/Include/core_cm7.h **** 648:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB 649:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB 650:Drivers/CMSIS/Include/core_cm7.h **** 651:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB 652:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB 653:Drivers/CMSIS/Include/core_cm7.h **** 654:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB 655:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB 656:Drivers/CMSIS/Include/core_cm7.h **** 657:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB ARM GAS /tmp/ccLSPxIe.s page 13 658:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB 659:Drivers/CMSIS/Include/core_cm7.h **** 660:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB 661:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB 662:Drivers/CMSIS/Include/core_cm7.h **** 663:Drivers/CMSIS/Include/core_cm7.h **** /* SCB Configurable Fault Status Register Definitions */ 664:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB 665:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB 666:Drivers/CMSIS/Include/core_cm7.h **** 667:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB 668:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB 669:Drivers/CMSIS/Include/core_cm7.h **** 670:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB 671:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB 672:Drivers/CMSIS/Include/core_cm7.h **** 673:Drivers/CMSIS/Include/core_cm7.h **** /* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ 674:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB 675:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB 676:Drivers/CMSIS/Include/core_cm7.h **** 677:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB 678:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB 679:Drivers/CMSIS/Include/core_cm7.h **** 680:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB 681:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB 682:Drivers/CMSIS/Include/core_cm7.h **** 683:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB 684:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB 685:Drivers/CMSIS/Include/core_cm7.h **** 686:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB 687:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB 688:Drivers/CMSIS/Include/core_cm7.h **** 689:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB 690:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB 691:Drivers/CMSIS/Include/core_cm7.h **** 692:Drivers/CMSIS/Include/core_cm7.h **** /* BusFault Status Register (part of SCB Configurable Fault Status Register) */ 693:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB 694:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB 695:Drivers/CMSIS/Include/core_cm7.h **** 696:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB 697:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB 698:Drivers/CMSIS/Include/core_cm7.h **** 699:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB 700:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB 701:Drivers/CMSIS/Include/core_cm7.h **** 702:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB 703:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB 704:Drivers/CMSIS/Include/core_cm7.h **** 705:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB 706:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB 707:Drivers/CMSIS/Include/core_cm7.h **** 708:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB 709:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB 710:Drivers/CMSIS/Include/core_cm7.h **** 711:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB 712:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB 713:Drivers/CMSIS/Include/core_cm7.h **** 714:Drivers/CMSIS/Include/core_cm7.h **** /* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ ARM GAS /tmp/ccLSPxIe.s page 14 715:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB 716:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB 717:Drivers/CMSIS/Include/core_cm7.h **** 718:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB 719:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB 720:Drivers/CMSIS/Include/core_cm7.h **** 721:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB 722:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB 723:Drivers/CMSIS/Include/core_cm7.h **** 724:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB 725:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB 726:Drivers/CMSIS/Include/core_cm7.h **** 727:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB 728:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB 729:Drivers/CMSIS/Include/core_cm7.h **** 730:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB 731:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB 732:Drivers/CMSIS/Include/core_cm7.h **** 733:Drivers/CMSIS/Include/core_cm7.h **** /* SCB Hard Fault Status Register Definitions */ 734:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB 735:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB 736:Drivers/CMSIS/Include/core_cm7.h **** 737:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_HFSR_FORCED_Pos 30U /*!< SCB 738:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB 739:Drivers/CMSIS/Include/core_cm7.h **** 740:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB 741:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB 742:Drivers/CMSIS/Include/core_cm7.h **** 743:Drivers/CMSIS/Include/core_cm7.h **** /* SCB Debug Fault Status Register Definitions */ 744:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB 745:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB 746:Drivers/CMSIS/Include/core_cm7.h **** 747:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DFSR_VCATCH_Pos 3U /*!< SCB 748:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB 749:Drivers/CMSIS/Include/core_cm7.h **** 750:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB 751:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB 752:Drivers/CMSIS/Include/core_cm7.h **** 753:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DFSR_BKPT_Pos 1U /*!< SCB 754:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB 755:Drivers/CMSIS/Include/core_cm7.h **** 756:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DFSR_HALTED_Pos 0U /*!< SCB 757:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB 758:Drivers/CMSIS/Include/core_cm7.h **** 759:Drivers/CMSIS/Include/core_cm7.h **** /* SCB Cache Level ID Register Definitions */ 760:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CLIDR_LOUU_Pos 27U /*!< SCB 761:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB 762:Drivers/CMSIS/Include/core_cm7.h **** 763:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CLIDR_LOC_Pos 24U /*!< SCB 764:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB 765:Drivers/CMSIS/Include/core_cm7.h **** 766:Drivers/CMSIS/Include/core_cm7.h **** /* SCB Cache Type Register Definitions */ 767:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CTR_FORMAT_Pos 29U /*!< SCB 768:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB 769:Drivers/CMSIS/Include/core_cm7.h **** 770:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CTR_CWG_Pos 24U /*!< SCB 771:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB ARM GAS /tmp/ccLSPxIe.s page 15 772:Drivers/CMSIS/Include/core_cm7.h **** 773:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CTR_ERG_Pos 20U /*!< SCB 774:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB 775:Drivers/CMSIS/Include/core_cm7.h **** 776:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CTR_DMINLINE_Pos 16U /*!< SCB 777:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB 778:Drivers/CMSIS/Include/core_cm7.h **** 779:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CTR_IMINLINE_Pos 0U /*!< SCB 780:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB 781:Drivers/CMSIS/Include/core_cm7.h **** 782:Drivers/CMSIS/Include/core_cm7.h **** /* SCB Cache Size ID Register Definitions */ 783:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCSIDR_WT_Pos 31U /*!< SCB 784:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB 785:Drivers/CMSIS/Include/core_cm7.h **** 786:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCSIDR_WB_Pos 30U /*!< SCB 787:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB 788:Drivers/CMSIS/Include/core_cm7.h **** 789:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCSIDR_RA_Pos 29U /*!< SCB 790:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB 791:Drivers/CMSIS/Include/core_cm7.h **** 792:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCSIDR_WA_Pos 28U /*!< SCB 793:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB 794:Drivers/CMSIS/Include/core_cm7.h **** 795:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB 796:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB 797:Drivers/CMSIS/Include/core_cm7.h **** 798:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB 799:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB 800:Drivers/CMSIS/Include/core_cm7.h **** 801:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB 802:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB 803:Drivers/CMSIS/Include/core_cm7.h **** 804:Drivers/CMSIS/Include/core_cm7.h **** /* SCB Cache Size Selection Register Definitions */ 805:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB 806:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB 807:Drivers/CMSIS/Include/core_cm7.h **** 808:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CSSELR_IND_Pos 0U /*!< SCB 809:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB 810:Drivers/CMSIS/Include/core_cm7.h **** 811:Drivers/CMSIS/Include/core_cm7.h **** /* SCB Software Triggered Interrupt Register Definitions */ 812:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_STIR_INTID_Pos 0U /*!< SCB 813:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB 814:Drivers/CMSIS/Include/core_cm7.h **** 815:Drivers/CMSIS/Include/core_cm7.h **** /* SCB D-Cache Invalidate by Set-way Register Definitions */ 816:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DCISW_WAY_Pos 30U /*!< SCB 817:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB 818:Drivers/CMSIS/Include/core_cm7.h **** 819:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DCISW_SET_Pos 5U /*!< SCB 820:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB 821:Drivers/CMSIS/Include/core_cm7.h **** 822:Drivers/CMSIS/Include/core_cm7.h **** /* SCB D-Cache Clean by Set-way Register Definitions */ 823:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DCCSW_WAY_Pos 30U /*!< SCB 824:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB 825:Drivers/CMSIS/Include/core_cm7.h **** 826:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DCCSW_SET_Pos 5U /*!< SCB 827:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB 828:Drivers/CMSIS/Include/core_cm7.h **** ARM GAS /tmp/ccLSPxIe.s page 16 829:Drivers/CMSIS/Include/core_cm7.h **** /* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ 830:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DCCISW_WAY_Pos 30U /*!< SCB 831:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB 832:Drivers/CMSIS/Include/core_cm7.h **** 833:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DCCISW_SET_Pos 5U /*!< SCB 834:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB 835:Drivers/CMSIS/Include/core_cm7.h **** 836:Drivers/CMSIS/Include/core_cm7.h **** /* Instruction Tightly-Coupled Memory Control Register Definitions */ 837:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ITCMCR_SZ_Pos 3U /*!< SCB 838:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB 839:Drivers/CMSIS/Include/core_cm7.h **** 840:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB 841:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB 842:Drivers/CMSIS/Include/core_cm7.h **** 843:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ITCMCR_RMW_Pos 1U /*!< SCB 844:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB 845:Drivers/CMSIS/Include/core_cm7.h **** 846:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ITCMCR_EN_Pos 0U /*!< SCB 847:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB 848:Drivers/CMSIS/Include/core_cm7.h **** 849:Drivers/CMSIS/Include/core_cm7.h **** /* Data Tightly-Coupled Memory Control Register Definitions */ 850:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DTCMCR_SZ_Pos 3U /*!< SCB 851:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB 852:Drivers/CMSIS/Include/core_cm7.h **** 853:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB 854:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB 855:Drivers/CMSIS/Include/core_cm7.h **** 856:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DTCMCR_RMW_Pos 1U /*!< SCB 857:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB 858:Drivers/CMSIS/Include/core_cm7.h **** 859:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DTCMCR_EN_Pos 0U /*!< SCB 860:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB 861:Drivers/CMSIS/Include/core_cm7.h **** 862:Drivers/CMSIS/Include/core_cm7.h **** /* AHBP Control Register Definitions */ 863:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AHBPCR_SZ_Pos 1U /*!< SCB 864:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB 865:Drivers/CMSIS/Include/core_cm7.h **** 866:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AHBPCR_EN_Pos 0U /*!< SCB 867:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB 868:Drivers/CMSIS/Include/core_cm7.h **** 869:Drivers/CMSIS/Include/core_cm7.h **** /* L1 Cache Control Register Definitions */ 870:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CACR_FORCEWT_Pos 2U /*!< SCB 871:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB 872:Drivers/CMSIS/Include/core_cm7.h **** 873:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CACR_ECCEN_Pos 1U /*!< SCB 874:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB 875:Drivers/CMSIS/Include/core_cm7.h **** 876:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CACR_SIWT_Pos 0U /*!< SCB 877:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB 878:Drivers/CMSIS/Include/core_cm7.h **** 879:Drivers/CMSIS/Include/core_cm7.h **** /* AHBS Control Register Definitions */ 880:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB 881:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB 882:Drivers/CMSIS/Include/core_cm7.h **** 883:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB 884:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB 885:Drivers/CMSIS/Include/core_cm7.h **** ARM GAS /tmp/ccLSPxIe.s page 17 886:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AHBSCR_CTL_Pos 0U /*!< SCB 887:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB 888:Drivers/CMSIS/Include/core_cm7.h **** 889:Drivers/CMSIS/Include/core_cm7.h **** /* Auxiliary Bus Fault Status Register Definitions */ 890:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB 891:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB 892:Drivers/CMSIS/Include/core_cm7.h **** 893:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ABFSR_EPPB_Pos 4U /*!< SCB 894:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB 895:Drivers/CMSIS/Include/core_cm7.h **** 896:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ABFSR_AXIM_Pos 3U /*!< SCB 897:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB 898:Drivers/CMSIS/Include/core_cm7.h **** 899:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ABFSR_AHBP_Pos 2U /*!< SCB 900:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB 901:Drivers/CMSIS/Include/core_cm7.h **** 902:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ABFSR_DTCM_Pos 1U /*!< SCB 903:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB 904:Drivers/CMSIS/Include/core_cm7.h **** 905:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ABFSR_ITCM_Pos 0U /*!< SCB 906:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB 907:Drivers/CMSIS/Include/core_cm7.h **** 908:Drivers/CMSIS/Include/core_cm7.h **** /*@} end of group CMSIS_SCB */ 909:Drivers/CMSIS/Include/core_cm7.h **** 910:Drivers/CMSIS/Include/core_cm7.h **** 911:Drivers/CMSIS/Include/core_cm7.h **** /** 912:Drivers/CMSIS/Include/core_cm7.h **** \ingroup CMSIS_core_register 913:Drivers/CMSIS/Include/core_cm7.h **** \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) 914:Drivers/CMSIS/Include/core_cm7.h **** \brief Type definitions for the System Control and ID Register not in the SCB 915:Drivers/CMSIS/Include/core_cm7.h **** @{ 916:Drivers/CMSIS/Include/core_cm7.h **** */ 917:Drivers/CMSIS/Include/core_cm7.h **** 918:Drivers/CMSIS/Include/core_cm7.h **** /** 919:Drivers/CMSIS/Include/core_cm7.h **** \brief Structure type to access the System Control and ID Register not in the SCB. 920:Drivers/CMSIS/Include/core_cm7.h **** */ 921:Drivers/CMSIS/Include/core_cm7.h **** typedef struct 922:Drivers/CMSIS/Include/core_cm7.h **** { 923:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED0[1U]; 924:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Regist 925:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ 926:Drivers/CMSIS/Include/core_cm7.h **** } SCnSCB_Type; 927:Drivers/CMSIS/Include/core_cm7.h **** 928:Drivers/CMSIS/Include/core_cm7.h **** /* Interrupt Controller Type Register Definitions */ 929:Drivers/CMSIS/Include/core_cm7.h **** #define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: I 930:Drivers/CMSIS/Include/core_cm7.h **** #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: I 931:Drivers/CMSIS/Include/core_cm7.h **** 932:Drivers/CMSIS/Include/core_cm7.h **** /* Auxiliary Control Register Definitions */ 933:Drivers/CMSIS/Include/core_cm7.h **** #define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12U /*!< ACTLR: 934:Drivers/CMSIS/Include/core_cm7.h **** #define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: 935:Drivers/CMSIS/Include/core_cm7.h **** 936:Drivers/CMSIS/Include/core_cm7.h **** #define SCnSCB_ACTLR_DISRAMODE_Pos 11U /*!< ACTLR: 937:Drivers/CMSIS/Include/core_cm7.h **** #define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) /*!< ACTLR: 938:Drivers/CMSIS/Include/core_cm7.h **** 939:Drivers/CMSIS/Include/core_cm7.h **** #define SCnSCB_ACTLR_FPEXCODIS_Pos 10U /*!< ACTLR: 940:Drivers/CMSIS/Include/core_cm7.h **** #define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: 941:Drivers/CMSIS/Include/core_cm7.h **** 942:Drivers/CMSIS/Include/core_cm7.h **** #define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: ARM GAS /tmp/ccLSPxIe.s page 18 943:Drivers/CMSIS/Include/core_cm7.h **** #define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: 944:Drivers/CMSIS/Include/core_cm7.h **** 945:Drivers/CMSIS/Include/core_cm7.h **** #define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: 946:Drivers/CMSIS/Include/core_cm7.h **** #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: 947:Drivers/CMSIS/Include/core_cm7.h **** 948:Drivers/CMSIS/Include/core_cm7.h **** /*@} end of group CMSIS_SCnotSCB */ 949:Drivers/CMSIS/Include/core_cm7.h **** 950:Drivers/CMSIS/Include/core_cm7.h **** 951:Drivers/CMSIS/Include/core_cm7.h **** /** 952:Drivers/CMSIS/Include/core_cm7.h **** \ingroup CMSIS_core_register 953:Drivers/CMSIS/Include/core_cm7.h **** \defgroup CMSIS_SysTick System Tick Timer (SysTick) 954:Drivers/CMSIS/Include/core_cm7.h **** \brief Type definitions for the System Timer Registers. 955:Drivers/CMSIS/Include/core_cm7.h **** @{ 956:Drivers/CMSIS/Include/core_cm7.h **** */ 957:Drivers/CMSIS/Include/core_cm7.h **** 958:Drivers/CMSIS/Include/core_cm7.h **** /** 959:Drivers/CMSIS/Include/core_cm7.h **** \brief Structure type to access the System Timer (SysTick). 960:Drivers/CMSIS/Include/core_cm7.h **** */ 961:Drivers/CMSIS/Include/core_cm7.h **** typedef struct 962:Drivers/CMSIS/Include/core_cm7.h **** { 963:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Regis 964:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ 965:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register * 966:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ 967:Drivers/CMSIS/Include/core_cm7.h **** } SysTick_Type; 968:Drivers/CMSIS/Include/core_cm7.h **** 969:Drivers/CMSIS/Include/core_cm7.h **** /* SysTick Control / Status Register Definitions */ 970:Drivers/CMSIS/Include/core_cm7.h **** #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysT 971:Drivers/CMSIS/Include/core_cm7.h **** #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysT 972:Drivers/CMSIS/Include/core_cm7.h **** 973:Drivers/CMSIS/Include/core_cm7.h **** #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysT 974:Drivers/CMSIS/Include/core_cm7.h **** #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysT 975:Drivers/CMSIS/Include/core_cm7.h **** 976:Drivers/CMSIS/Include/core_cm7.h **** #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysT 977:Drivers/CMSIS/Include/core_cm7.h **** #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysT 978:Drivers/CMSIS/Include/core_cm7.h **** 979:Drivers/CMSIS/Include/core_cm7.h **** #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysT 980:Drivers/CMSIS/Include/core_cm7.h **** #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysT 981:Drivers/CMSIS/Include/core_cm7.h **** 982:Drivers/CMSIS/Include/core_cm7.h **** /* SysTick Reload Register Definitions */ 983:Drivers/CMSIS/Include/core_cm7.h **** #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysT 984:Drivers/CMSIS/Include/core_cm7.h **** #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysT 985:Drivers/CMSIS/Include/core_cm7.h **** 986:Drivers/CMSIS/Include/core_cm7.h **** /* SysTick Current Register Definitions */ 987:Drivers/CMSIS/Include/core_cm7.h **** #define SysTick_VAL_CURRENT_Pos 0U /*!< SysT 988:Drivers/CMSIS/Include/core_cm7.h **** #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysT 989:Drivers/CMSIS/Include/core_cm7.h **** 990:Drivers/CMSIS/Include/core_cm7.h **** /* SysTick Calibration Register Definitions */ 991:Drivers/CMSIS/Include/core_cm7.h **** #define SysTick_CALIB_NOREF_Pos 31U /*!< SysT 992:Drivers/CMSIS/Include/core_cm7.h **** #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysT 993:Drivers/CMSIS/Include/core_cm7.h **** 994:Drivers/CMSIS/Include/core_cm7.h **** #define SysTick_CALIB_SKEW_Pos 30U /*!< SysT 995:Drivers/CMSIS/Include/core_cm7.h **** #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysT 996:Drivers/CMSIS/Include/core_cm7.h **** 997:Drivers/CMSIS/Include/core_cm7.h **** #define SysTick_CALIB_TENMS_Pos 0U /*!< SysT 998:Drivers/CMSIS/Include/core_cm7.h **** #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysT 999:Drivers/CMSIS/Include/core_cm7.h **** ARM GAS /tmp/ccLSPxIe.s page 19 1000:Drivers/CMSIS/Include/core_cm7.h **** /*@} end of group CMSIS_SysTick */ 1001:Drivers/CMSIS/Include/core_cm7.h **** 1002:Drivers/CMSIS/Include/core_cm7.h **** 1003:Drivers/CMSIS/Include/core_cm7.h **** /** 1004:Drivers/CMSIS/Include/core_cm7.h **** \ingroup CMSIS_core_register 1005:Drivers/CMSIS/Include/core_cm7.h **** \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) 1006:Drivers/CMSIS/Include/core_cm7.h **** \brief Type definitions for the Instrumentation Trace Macrocell (ITM) 1007:Drivers/CMSIS/Include/core_cm7.h **** @{ 1008:Drivers/CMSIS/Include/core_cm7.h **** */ 1009:Drivers/CMSIS/Include/core_cm7.h **** 1010:Drivers/CMSIS/Include/core_cm7.h **** /** 1011:Drivers/CMSIS/Include/core_cm7.h **** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). 1012:Drivers/CMSIS/Include/core_cm7.h **** */ 1013:Drivers/CMSIS/Include/core_cm7.h **** typedef struct 1014:Drivers/CMSIS/Include/core_cm7.h **** { 1015:Drivers/CMSIS/Include/core_cm7.h **** __OM union 1016:Drivers/CMSIS/Include/core_cm7.h **** { 1017:Drivers/CMSIS/Include/core_cm7.h **** __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ 1018:Drivers/CMSIS/Include/core_cm7.h **** __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ 1019:Drivers/CMSIS/Include/core_cm7.h **** __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ 1020:Drivers/CMSIS/Include/core_cm7.h **** } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ 1021:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED0[864U]; 1022:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ 1023:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED1[15U]; 1024:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ 1025:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED2[15U]; 1026:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ 1027:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED3[29U]; 1028:Drivers/CMSIS/Include/core_cm7.h **** __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register * 1029:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ 1030:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Reg 1031:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED4[43U]; 1032:Drivers/CMSIS/Include/core_cm7.h **** __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ 1033:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ 1034:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED5[6U]; 1035:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Re 1036:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Re 1037:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Re 1038:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Re 1039:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Re 1040:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Re 1041:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Re 1042:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Re 1043:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Re 1044:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Re 1045:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Re 1046:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Re 1047:Drivers/CMSIS/Include/core_cm7.h **** } ITM_Type; 1048:Drivers/CMSIS/Include/core_cm7.h **** 1049:Drivers/CMSIS/Include/core_cm7.h **** /* ITM Trace Privilege Register Definitions */ 1050:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM 1051:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM 1052:Drivers/CMSIS/Include/core_cm7.h **** 1053:Drivers/CMSIS/Include/core_cm7.h **** /* ITM Trace Control Register Definitions */ 1054:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TCR_BUSY_Pos 23U /*!< ITM 1055:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM 1056:Drivers/CMSIS/Include/core_cm7.h **** ARM GAS /tmp/ccLSPxIe.s page 20 1057:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TCR_TraceBusID_Pos 16U /*!< ITM 1058:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM 1059:Drivers/CMSIS/Include/core_cm7.h **** 1060:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM 1061:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM 1062:Drivers/CMSIS/Include/core_cm7.h **** 1063:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TCR_TSPrescale_Pos 8U /*!< ITM 1064:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM 1065:Drivers/CMSIS/Include/core_cm7.h **** 1066:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TCR_SWOENA_Pos 4U /*!< ITM 1067:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM 1068:Drivers/CMSIS/Include/core_cm7.h **** 1069:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TCR_DWTENA_Pos 3U /*!< ITM 1070:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM 1071:Drivers/CMSIS/Include/core_cm7.h **** 1072:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TCR_SYNCENA_Pos 2U /*!< ITM 1073:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM 1074:Drivers/CMSIS/Include/core_cm7.h **** 1075:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TCR_TSENA_Pos 1U /*!< ITM 1076:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM 1077:Drivers/CMSIS/Include/core_cm7.h **** 1078:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TCR_ITMENA_Pos 0U /*!< ITM 1079:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM 1080:Drivers/CMSIS/Include/core_cm7.h **** 1081:Drivers/CMSIS/Include/core_cm7.h **** /* ITM Integration Write Register Definitions */ 1082:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM 1083:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM 1084:Drivers/CMSIS/Include/core_cm7.h **** 1085:Drivers/CMSIS/Include/core_cm7.h **** /* ITM Integration Read Register Definitions */ 1086:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_IRR_ATREADYM_Pos 0U /*!< ITM 1087:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM 1088:Drivers/CMSIS/Include/core_cm7.h **** 1089:Drivers/CMSIS/Include/core_cm7.h **** /* ITM Integration Mode Control Register Definitions */ 1090:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM 1091:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM 1092:Drivers/CMSIS/Include/core_cm7.h **** 1093:Drivers/CMSIS/Include/core_cm7.h **** /* ITM Lock Status Register Definitions */ 1094:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_LSR_ByteAcc_Pos 2U /*!< ITM 1095:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM 1096:Drivers/CMSIS/Include/core_cm7.h **** 1097:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_LSR_Access_Pos 1U /*!< ITM 1098:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM 1099:Drivers/CMSIS/Include/core_cm7.h **** 1100:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_LSR_Present_Pos 0U /*!< ITM 1101:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM 1102:Drivers/CMSIS/Include/core_cm7.h **** 1103:Drivers/CMSIS/Include/core_cm7.h **** /*@}*/ /* end of group CMSIS_ITM */ 1104:Drivers/CMSIS/Include/core_cm7.h **** 1105:Drivers/CMSIS/Include/core_cm7.h **** 1106:Drivers/CMSIS/Include/core_cm7.h **** /** 1107:Drivers/CMSIS/Include/core_cm7.h **** \ingroup CMSIS_core_register 1108:Drivers/CMSIS/Include/core_cm7.h **** \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) 1109:Drivers/CMSIS/Include/core_cm7.h **** \brief Type definitions for the Data Watchpoint and Trace (DWT) 1110:Drivers/CMSIS/Include/core_cm7.h **** @{ 1111:Drivers/CMSIS/Include/core_cm7.h **** */ 1112:Drivers/CMSIS/Include/core_cm7.h **** 1113:Drivers/CMSIS/Include/core_cm7.h **** /** ARM GAS /tmp/ccLSPxIe.s page 21 1114:Drivers/CMSIS/Include/core_cm7.h **** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). 1115:Drivers/CMSIS/Include/core_cm7.h **** */ 1116:Drivers/CMSIS/Include/core_cm7.h **** typedef struct 1117:Drivers/CMSIS/Include/core_cm7.h **** { 1118:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ 1119:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ 1120:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ 1121:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Registe 1122:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ 1123:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ 1124:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Registe 1125:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register 1126:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ 1127:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ 1128:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ 1129:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED0[1U]; 1130:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ 1131:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ 1132:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ 1133:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED1[1U]; 1134:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ 1135:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ 1136:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ 1137:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED2[1U]; 1138:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ 1139:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ 1140:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ 1141:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED3[981U]; 1142:Drivers/CMSIS/Include/core_cm7.h **** __OM uint32_t LAR; /*!< Offset: 0xFB0 ( W) Lock Access Register */ 1143:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ 1144:Drivers/CMSIS/Include/core_cm7.h **** } DWT_Type; 1145:Drivers/CMSIS/Include/core_cm7.h **** 1146:Drivers/CMSIS/Include/core_cm7.h **** /* DWT Control Register Definitions */ 1147:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTR 1148:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTR 1149:Drivers/CMSIS/Include/core_cm7.h **** 1150:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTR 1151:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTR 1152:Drivers/CMSIS/Include/core_cm7.h **** 1153:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTR 1154:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTR 1155:Drivers/CMSIS/Include/core_cm7.h **** 1156:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTR 1157:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTR 1158:Drivers/CMSIS/Include/core_cm7.h **** 1159:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTR 1160:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTR 1161:Drivers/CMSIS/Include/core_cm7.h **** 1162:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTR 1163:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTR 1164:Drivers/CMSIS/Include/core_cm7.h **** 1165:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTR 1166:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTR 1167:Drivers/CMSIS/Include/core_cm7.h **** 1168:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTR 1169:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTR 1170:Drivers/CMSIS/Include/core_cm7.h **** ARM GAS /tmp/ccLSPxIe.s page 22 1171:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTR 1172:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTR 1173:Drivers/CMSIS/Include/core_cm7.h **** 1174:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTR 1175:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTR 1176:Drivers/CMSIS/Include/core_cm7.h **** 1177:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTR 1178:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTR 1179:Drivers/CMSIS/Include/core_cm7.h **** 1180:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTR 1181:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTR 1182:Drivers/CMSIS/Include/core_cm7.h **** 1183:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTR 1184:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTR 1185:Drivers/CMSIS/Include/core_cm7.h **** 1186:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTR 1187:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTR 1188:Drivers/CMSIS/Include/core_cm7.h **** 1189:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTR 1190:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTR 1191:Drivers/CMSIS/Include/core_cm7.h **** 1192:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTR 1193:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTR 1194:Drivers/CMSIS/Include/core_cm7.h **** 1195:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTR 1196:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTR 1197:Drivers/CMSIS/Include/core_cm7.h **** 1198:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTR 1199:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTR 1200:Drivers/CMSIS/Include/core_cm7.h **** 1201:Drivers/CMSIS/Include/core_cm7.h **** /* DWT CPI Count Register Definitions */ 1202:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPI 1203:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPI 1204:Drivers/CMSIS/Include/core_cm7.h **** 1205:Drivers/CMSIS/Include/core_cm7.h **** /* DWT Exception Overhead Count Register Definitions */ 1206:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXC 1207:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXC 1208:Drivers/CMSIS/Include/core_cm7.h **** 1209:Drivers/CMSIS/Include/core_cm7.h **** /* DWT Sleep Count Register Definitions */ 1210:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLE 1211:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLE 1212:Drivers/CMSIS/Include/core_cm7.h **** 1213:Drivers/CMSIS/Include/core_cm7.h **** /* DWT LSU Count Register Definitions */ 1214:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSU 1215:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSU 1216:Drivers/CMSIS/Include/core_cm7.h **** 1217:Drivers/CMSIS/Include/core_cm7.h **** /* DWT Folded-instruction Count Register Definitions */ 1218:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOL 1219:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOL 1220:Drivers/CMSIS/Include/core_cm7.h **** 1221:Drivers/CMSIS/Include/core_cm7.h **** /* DWT Comparator Mask Register Definitions */ 1222:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_MASK_MASK_Pos 0U /*!< DWT MAS 1223:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MAS 1224:Drivers/CMSIS/Include/core_cm7.h **** 1225:Drivers/CMSIS/Include/core_cm7.h **** /* DWT Comparator Function Register Definitions */ 1226:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUN 1227:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUN ARM GAS /tmp/ccLSPxIe.s page 23 1228:Drivers/CMSIS/Include/core_cm7.h **** 1229:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUN 1230:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUN 1231:Drivers/CMSIS/Include/core_cm7.h **** 1232:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUN 1233:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUN 1234:Drivers/CMSIS/Include/core_cm7.h **** 1235:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUN 1236:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUN 1237:Drivers/CMSIS/Include/core_cm7.h **** 1238:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUN 1239:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUN 1240:Drivers/CMSIS/Include/core_cm7.h **** 1241:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUN 1242:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUN 1243:Drivers/CMSIS/Include/core_cm7.h **** 1244:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUN 1245:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUN 1246:Drivers/CMSIS/Include/core_cm7.h **** 1247:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUN 1248:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUN 1249:Drivers/CMSIS/Include/core_cm7.h **** 1250:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUN 1251:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUN 1252:Drivers/CMSIS/Include/core_cm7.h **** 1253:Drivers/CMSIS/Include/core_cm7.h **** /*@}*/ /* end of group CMSIS_DWT */ 1254:Drivers/CMSIS/Include/core_cm7.h **** 1255:Drivers/CMSIS/Include/core_cm7.h **** 1256:Drivers/CMSIS/Include/core_cm7.h **** /** 1257:Drivers/CMSIS/Include/core_cm7.h **** \ingroup CMSIS_core_register 1258:Drivers/CMSIS/Include/core_cm7.h **** \defgroup CMSIS_TPI Trace Port Interface (TPI) 1259:Drivers/CMSIS/Include/core_cm7.h **** \brief Type definitions for the Trace Port Interface (TPI) 1260:Drivers/CMSIS/Include/core_cm7.h **** @{ 1261:Drivers/CMSIS/Include/core_cm7.h **** */ 1262:Drivers/CMSIS/Include/core_cm7.h **** 1263:Drivers/CMSIS/Include/core_cm7.h **** /** 1264:Drivers/CMSIS/Include/core_cm7.h **** \brief Structure type to access the Trace Port Interface Register (TPI). 1265:Drivers/CMSIS/Include/core_cm7.h **** */ 1266:Drivers/CMSIS/Include/core_cm7.h **** typedef struct 1267:Drivers/CMSIS/Include/core_cm7.h **** { 1268:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Reg 1269:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Regis 1270:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED0[2U]; 1271:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Reg 1272:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED1[55U]; 1273:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register * 1274:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED2[131U]; 1275:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Regis 1276:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Regi 1277:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counte 1278:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED3[759U]; 1279:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ 1280:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ 1281:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ 1282:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED4[1U]; 1283:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ 1284:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ ARM GAS /tmp/ccLSPxIe.s page 24 1285:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ 1286:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED5[39U]; 1287:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ 1288:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ 1289:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED7[8U]; 1290:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ 1291:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ 1292:Drivers/CMSIS/Include/core_cm7.h **** } TPI_Type; 1293:Drivers/CMSIS/Include/core_cm7.h **** 1294:Drivers/CMSIS/Include/core_cm7.h **** /* TPI Asynchronous Clock Prescaler Register Definitions */ 1295:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACP 1296:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACP 1297:Drivers/CMSIS/Include/core_cm7.h **** 1298:Drivers/CMSIS/Include/core_cm7.h **** /* TPI Selected Pin Protocol Register Definitions */ 1299:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPP 1300:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPP 1301:Drivers/CMSIS/Include/core_cm7.h **** 1302:Drivers/CMSIS/Include/core_cm7.h **** /* TPI Formatter and Flush Status Register Definitions */ 1303:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFS 1304:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFS 1305:Drivers/CMSIS/Include/core_cm7.h **** 1306:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFS 1307:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFS 1308:Drivers/CMSIS/Include/core_cm7.h **** 1309:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFS 1310:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFS 1311:Drivers/CMSIS/Include/core_cm7.h **** 1312:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFS 1313:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFS 1314:Drivers/CMSIS/Include/core_cm7.h **** 1315:Drivers/CMSIS/Include/core_cm7.h **** /* TPI Formatter and Flush Control Register Definitions */ 1316:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFC 1317:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFC 1318:Drivers/CMSIS/Include/core_cm7.h **** 1319:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFC 1320:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFC 1321:Drivers/CMSIS/Include/core_cm7.h **** 1322:Drivers/CMSIS/Include/core_cm7.h **** /* TPI TRIGGER Register Definitions */ 1323:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRI 1324:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRI 1325:Drivers/CMSIS/Include/core_cm7.h **** 1326:Drivers/CMSIS/Include/core_cm7.h **** /* TPI Integration ETM Data Register Definitions (FIFO0) */ 1327:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIF 1328:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIF 1329:Drivers/CMSIS/Include/core_cm7.h **** 1330:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIF 1331:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIF 1332:Drivers/CMSIS/Include/core_cm7.h **** 1333:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIF 1334:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIF 1335:Drivers/CMSIS/Include/core_cm7.h **** 1336:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIF 1337:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIF 1338:Drivers/CMSIS/Include/core_cm7.h **** 1339:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIF 1340:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIF 1341:Drivers/CMSIS/Include/core_cm7.h **** ARM GAS /tmp/ccLSPxIe.s page 25 1342:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIF 1343:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIF 1344:Drivers/CMSIS/Include/core_cm7.h **** 1345:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIF 1346:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIF 1347:Drivers/CMSIS/Include/core_cm7.h **** 1348:Drivers/CMSIS/Include/core_cm7.h **** /* TPI ITATBCTR2 Register Definitions */ 1349:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITA 1350:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITA 1351:Drivers/CMSIS/Include/core_cm7.h **** 1352:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITA 1353:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITA 1354:Drivers/CMSIS/Include/core_cm7.h **** 1355:Drivers/CMSIS/Include/core_cm7.h **** /* TPI Integration ITM Data Register Definitions (FIFO1) */ 1356:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIF 1357:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIF 1358:Drivers/CMSIS/Include/core_cm7.h **** 1359:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIF 1360:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIF 1361:Drivers/CMSIS/Include/core_cm7.h **** 1362:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIF 1363:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIF 1364:Drivers/CMSIS/Include/core_cm7.h **** 1365:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIF 1366:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIF 1367:Drivers/CMSIS/Include/core_cm7.h **** 1368:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIF 1369:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIF 1370:Drivers/CMSIS/Include/core_cm7.h **** 1371:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIF 1372:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIF 1373:Drivers/CMSIS/Include/core_cm7.h **** 1374:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIF 1375:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIF 1376:Drivers/CMSIS/Include/core_cm7.h **** 1377:Drivers/CMSIS/Include/core_cm7.h **** /* TPI ITATBCTR0 Register Definitions */ 1378:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITA 1379:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITA 1380:Drivers/CMSIS/Include/core_cm7.h **** 1381:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITA 1382:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITA 1383:Drivers/CMSIS/Include/core_cm7.h **** 1384:Drivers/CMSIS/Include/core_cm7.h **** /* TPI Integration Mode Control Register Definitions */ 1385:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITC 1386:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITC 1387:Drivers/CMSIS/Include/core_cm7.h **** 1388:Drivers/CMSIS/Include/core_cm7.h **** /* TPI DEVID Register Definitions */ 1389:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEV 1390:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEV 1391:Drivers/CMSIS/Include/core_cm7.h **** 1392:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEV 1393:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEV 1394:Drivers/CMSIS/Include/core_cm7.h **** 1395:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEV 1396:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEV 1397:Drivers/CMSIS/Include/core_cm7.h **** 1398:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEV ARM GAS /tmp/ccLSPxIe.s page 26 1399:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEV 1400:Drivers/CMSIS/Include/core_cm7.h **** 1401:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEV 1402:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEV 1403:Drivers/CMSIS/Include/core_cm7.h **** 1404:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEV 1405:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEV 1406:Drivers/CMSIS/Include/core_cm7.h **** 1407:Drivers/CMSIS/Include/core_cm7.h **** /* TPI DEVTYPE Register Definitions */ 1408:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEV 1409:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEV 1410:Drivers/CMSIS/Include/core_cm7.h **** 1411:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEV 1412:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEV 1413:Drivers/CMSIS/Include/core_cm7.h **** 1414:Drivers/CMSIS/Include/core_cm7.h **** /*@}*/ /* end of group CMSIS_TPI */ 1415:Drivers/CMSIS/Include/core_cm7.h **** 1416:Drivers/CMSIS/Include/core_cm7.h **** 1417:Drivers/CMSIS/Include/core_cm7.h **** #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) 1418:Drivers/CMSIS/Include/core_cm7.h **** /** 1419:Drivers/CMSIS/Include/core_cm7.h **** \ingroup CMSIS_core_register 1420:Drivers/CMSIS/Include/core_cm7.h **** \defgroup CMSIS_MPU Memory Protection Unit (MPU) 1421:Drivers/CMSIS/Include/core_cm7.h **** \brief Type definitions for the Memory Protection Unit (MPU) 1422:Drivers/CMSIS/Include/core_cm7.h **** @{ 1423:Drivers/CMSIS/Include/core_cm7.h **** */ 1424:Drivers/CMSIS/Include/core_cm7.h **** 1425:Drivers/CMSIS/Include/core_cm7.h **** /** 1426:Drivers/CMSIS/Include/core_cm7.h **** \brief Structure type to access the Memory Protection Unit (MPU). 1427:Drivers/CMSIS/Include/core_cm7.h **** */ 1428:Drivers/CMSIS/Include/core_cm7.h **** typedef struct 1429:Drivers/CMSIS/Include/core_cm7.h **** { 1430:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ 1431:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ 1432:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ 1433:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register 1434:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Re 1435:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address 1436:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and 1437:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address 1438:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and 1439:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address 1440:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and 1441:Drivers/CMSIS/Include/core_cm7.h **** } MPU_Type; 1442:Drivers/CMSIS/Include/core_cm7.h **** 1443:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_TYPE_RALIASES 4U 1444:Drivers/CMSIS/Include/core_cm7.h **** 1445:Drivers/CMSIS/Include/core_cm7.h **** /* MPU Type Register Definitions */ 1446:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_TYPE_IREGION_Pos 16U /*!< MPU 1447:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU 1448:Drivers/CMSIS/Include/core_cm7.h **** 1449:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_TYPE_DREGION_Pos 8U /*!< MPU 1450:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU 1451:Drivers/CMSIS/Include/core_cm7.h **** 1452:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU 1453:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU 1454:Drivers/CMSIS/Include/core_cm7.h **** 1455:Drivers/CMSIS/Include/core_cm7.h **** /* MPU Control Register Definitions */ ARM GAS /tmp/ccLSPxIe.s page 27 1456:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU 1457:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU 1458:Drivers/CMSIS/Include/core_cm7.h **** 1459:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU 1460:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU 1461:Drivers/CMSIS/Include/core_cm7.h **** 1462:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU 1463:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU 1464:Drivers/CMSIS/Include/core_cm7.h **** 1465:Drivers/CMSIS/Include/core_cm7.h **** /* MPU Region Number Register Definitions */ 1466:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RNR_REGION_Pos 0U /*!< MPU 1467:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU 1468:Drivers/CMSIS/Include/core_cm7.h **** 1469:Drivers/CMSIS/Include/core_cm7.h **** /* MPU Region Base Address Register Definitions */ 1470:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RBAR_ADDR_Pos 5U /*!< MPU 1471:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU 1472:Drivers/CMSIS/Include/core_cm7.h **** 1473:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RBAR_VALID_Pos 4U /*!< MPU 1474:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU 1475:Drivers/CMSIS/Include/core_cm7.h **** 1476:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RBAR_REGION_Pos 0U /*!< MPU 1477:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU 1478:Drivers/CMSIS/Include/core_cm7.h **** 1479:Drivers/CMSIS/Include/core_cm7.h **** /* MPU Region Attribute and Size Register Definitions */ 1480:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RASR_ATTRS_Pos 16U /*!< MPU 1481:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU 1482:Drivers/CMSIS/Include/core_cm7.h **** 1483:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RASR_XN_Pos 28U /*!< MPU 1484:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU 1485:Drivers/CMSIS/Include/core_cm7.h **** 1486:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RASR_AP_Pos 24U /*!< MPU 1487:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU 1488:Drivers/CMSIS/Include/core_cm7.h **** 1489:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RASR_TEX_Pos 19U /*!< MPU 1490:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU 1491:Drivers/CMSIS/Include/core_cm7.h **** 1492:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RASR_S_Pos 18U /*!< MPU 1493:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU 1494:Drivers/CMSIS/Include/core_cm7.h **** 1495:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RASR_C_Pos 17U /*!< MPU 1496:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU 1497:Drivers/CMSIS/Include/core_cm7.h **** 1498:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RASR_B_Pos 16U /*!< MPU 1499:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU 1500:Drivers/CMSIS/Include/core_cm7.h **** 1501:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RASR_SRD_Pos 8U /*!< MPU 1502:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU 1503:Drivers/CMSIS/Include/core_cm7.h **** 1504:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RASR_SIZE_Pos 1U /*!< MPU 1505:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU 1506:Drivers/CMSIS/Include/core_cm7.h **** 1507:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RASR_ENABLE_Pos 0U /*!< MPU 1508:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU 1509:Drivers/CMSIS/Include/core_cm7.h **** 1510:Drivers/CMSIS/Include/core_cm7.h **** /*@} end of group CMSIS_MPU */ 1511:Drivers/CMSIS/Include/core_cm7.h **** #endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */ 1512:Drivers/CMSIS/Include/core_cm7.h **** ARM GAS /tmp/ccLSPxIe.s page 28 1513:Drivers/CMSIS/Include/core_cm7.h **** 1514:Drivers/CMSIS/Include/core_cm7.h **** /** 1515:Drivers/CMSIS/Include/core_cm7.h **** \ingroup CMSIS_core_register 1516:Drivers/CMSIS/Include/core_cm7.h **** \defgroup CMSIS_FPU Floating Point Unit (FPU) 1517:Drivers/CMSIS/Include/core_cm7.h **** \brief Type definitions for the Floating Point Unit (FPU) 1518:Drivers/CMSIS/Include/core_cm7.h **** @{ 1519:Drivers/CMSIS/Include/core_cm7.h **** */ 1520:Drivers/CMSIS/Include/core_cm7.h **** 1521:Drivers/CMSIS/Include/core_cm7.h **** /** 1522:Drivers/CMSIS/Include/core_cm7.h **** \brief Structure type to access the Floating Point Unit (FPU). 1523:Drivers/CMSIS/Include/core_cm7.h **** */ 1524:Drivers/CMSIS/Include/core_cm7.h **** typedef struct 1525:Drivers/CMSIS/Include/core_cm7.h **** { 1526:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED0[1U]; 1527:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control R 1528:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address R 1529:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Co 1530:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 1531:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 1532:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 1533:Drivers/CMSIS/Include/core_cm7.h **** } FPU_Type; 1534:Drivers/CMSIS/Include/core_cm7.h **** 1535:Drivers/CMSIS/Include/core_cm7.h **** /* Floating-Point Context Control Register Definitions */ 1536:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCC 1537:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCC 1538:Drivers/CMSIS/Include/core_cm7.h **** 1539:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCC 1540:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCC 1541:Drivers/CMSIS/Include/core_cm7.h **** 1542:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCC 1543:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCC 1544:Drivers/CMSIS/Include/core_cm7.h **** 1545:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCC 1546:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCC 1547:Drivers/CMSIS/Include/core_cm7.h **** 1548:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCC 1549:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCC 1550:Drivers/CMSIS/Include/core_cm7.h **** 1551:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCC 1552:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCC 1553:Drivers/CMSIS/Include/core_cm7.h **** 1554:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPCCR_THREAD_Pos 3U /*!< FPCC 1555:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCC 1556:Drivers/CMSIS/Include/core_cm7.h **** 1557:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPCCR_USER_Pos 1U /*!< FPCC 1558:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCC 1559:Drivers/CMSIS/Include/core_cm7.h **** 1560:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCC 1561:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCC 1562:Drivers/CMSIS/Include/core_cm7.h **** 1563:Drivers/CMSIS/Include/core_cm7.h **** /* Floating-Point Context Address Register Definitions */ 1564:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCA 1565:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCA 1566:Drivers/CMSIS/Include/core_cm7.h **** 1567:Drivers/CMSIS/Include/core_cm7.h **** /* Floating-Point Default Status Control Register Definitions */ 1568:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPDSCR_AHP_Pos 26U /*!< FPDS 1569:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDS ARM GAS /tmp/ccLSPxIe.s page 29 1570:Drivers/CMSIS/Include/core_cm7.h **** 1571:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPDSCR_DN_Pos 25U /*!< FPDS 1572:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDS 1573:Drivers/CMSIS/Include/core_cm7.h **** 1574:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPDSCR_FZ_Pos 24U /*!< FPDS 1575:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDS 1576:Drivers/CMSIS/Include/core_cm7.h **** 1577:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPDSCR_RMode_Pos 22U /*!< FPDS 1578:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDS 1579:Drivers/CMSIS/Include/core_cm7.h **** 1580:Drivers/CMSIS/Include/core_cm7.h **** /* Media and FP Feature Register 0 Definitions */ 1581:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR 1582:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR 1583:Drivers/CMSIS/Include/core_cm7.h **** 1584:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR 1585:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR 1586:Drivers/CMSIS/Include/core_cm7.h **** 1587:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR 1588:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR 1589:Drivers/CMSIS/Include/core_cm7.h **** 1590:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR0_Divide_Pos 16U /*!< MVFR 1591:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR 1592:Drivers/CMSIS/Include/core_cm7.h **** 1593:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR 1594:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR 1595:Drivers/CMSIS/Include/core_cm7.h **** 1596:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR 1597:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR 1598:Drivers/CMSIS/Include/core_cm7.h **** 1599:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR 1600:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR 1601:Drivers/CMSIS/Include/core_cm7.h **** 1602:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR 1603:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR 1604:Drivers/CMSIS/Include/core_cm7.h **** 1605:Drivers/CMSIS/Include/core_cm7.h **** /* Media and FP Feature Register 1 Definitions */ 1606:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR 1607:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR 1608:Drivers/CMSIS/Include/core_cm7.h **** 1609:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR 1610:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR 1611:Drivers/CMSIS/Include/core_cm7.h **** 1612:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR 1613:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR 1614:Drivers/CMSIS/Include/core_cm7.h **** 1615:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR 1616:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR 1617:Drivers/CMSIS/Include/core_cm7.h **** 1618:Drivers/CMSIS/Include/core_cm7.h **** /* Media and FP Feature Register 2 Definitions */ 1619:Drivers/CMSIS/Include/core_cm7.h **** 1620:Drivers/CMSIS/Include/core_cm7.h **** /*@} end of group CMSIS_FPU */ 1621:Drivers/CMSIS/Include/core_cm7.h **** 1622:Drivers/CMSIS/Include/core_cm7.h **** 1623:Drivers/CMSIS/Include/core_cm7.h **** /** 1624:Drivers/CMSIS/Include/core_cm7.h **** \ingroup CMSIS_core_register 1625:Drivers/CMSIS/Include/core_cm7.h **** \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) 1626:Drivers/CMSIS/Include/core_cm7.h **** \brief Type definitions for the Core Debug Registers ARM GAS /tmp/ccLSPxIe.s page 30 1627:Drivers/CMSIS/Include/core_cm7.h **** @{ 1628:Drivers/CMSIS/Include/core_cm7.h **** */ 1629:Drivers/CMSIS/Include/core_cm7.h **** 1630:Drivers/CMSIS/Include/core_cm7.h **** /** 1631:Drivers/CMSIS/Include/core_cm7.h **** \brief Structure type to access the Core Debug Register (CoreDebug). 1632:Drivers/CMSIS/Include/core_cm7.h **** */ 1633:Drivers/CMSIS/Include/core_cm7.h **** typedef struct 1634:Drivers/CMSIS/Include/core_cm7.h **** { 1635:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status 1636:Drivers/CMSIS/Include/core_cm7.h **** __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Reg 1637:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Registe 1638:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Cont 1639:Drivers/CMSIS/Include/core_cm7.h **** } CoreDebug_Type; 1640:Drivers/CMSIS/Include/core_cm7.h **** 1641:Drivers/CMSIS/Include/core_cm7.h **** /* Debug Halting Control and Status Register Definitions */ 1642:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< Core 1643:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< Core 1644:Drivers/CMSIS/Include/core_cm7.h **** 1645:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< Core 1646:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< Core 1647:Drivers/CMSIS/Include/core_cm7.h **** 1648:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< Core 1649:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< Core 1650:Drivers/CMSIS/Include/core_cm7.h **** 1651:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< Core 1652:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< Core 1653:Drivers/CMSIS/Include/core_cm7.h **** 1654:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< Core 1655:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< Core 1656:Drivers/CMSIS/Include/core_cm7.h **** 1657:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< Core 1658:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< Core 1659:Drivers/CMSIS/Include/core_cm7.h **** 1660:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< Core 1661:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< Core 1662:Drivers/CMSIS/Include/core_cm7.h **** 1663:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< Core 1664:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< Core 1665:Drivers/CMSIS/Include/core_cm7.h **** 1666:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< Core 1667:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< Core 1668:Drivers/CMSIS/Include/core_cm7.h **** 1669:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< Core 1670:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< Core 1671:Drivers/CMSIS/Include/core_cm7.h **** 1672:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< Core 1673:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< Core 1674:Drivers/CMSIS/Include/core_cm7.h **** 1675:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< Core 1676:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< Core 1677:Drivers/CMSIS/Include/core_cm7.h **** 1678:Drivers/CMSIS/Include/core_cm7.h **** /* Debug Core Register Selector Register Definitions */ 1679:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< Core 1680:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< Core 1681:Drivers/CMSIS/Include/core_cm7.h **** 1682:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< Core 1683:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< Core ARM GAS /tmp/ccLSPxIe.s page 31 1684:Drivers/CMSIS/Include/core_cm7.h **** 1685:Drivers/CMSIS/Include/core_cm7.h **** /* Debug Exception and Monitor Control Register Definitions */ 1686:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< Core 1687:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< Core 1688:Drivers/CMSIS/Include/core_cm7.h **** 1689:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< Core 1690:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< Core 1691:Drivers/CMSIS/Include/core_cm7.h **** 1692:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< Core 1693:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< Core 1694:Drivers/CMSIS/Include/core_cm7.h **** 1695:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< Core 1696:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< Core 1697:Drivers/CMSIS/Include/core_cm7.h **** 1698:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< Core 1699:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< Core 1700:Drivers/CMSIS/Include/core_cm7.h **** 1701:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< Core 1702:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< Core 1703:Drivers/CMSIS/Include/core_cm7.h **** 1704:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< Core 1705:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< Core 1706:Drivers/CMSIS/Include/core_cm7.h **** 1707:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< Core 1708:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< Core 1709:Drivers/CMSIS/Include/core_cm7.h **** 1710:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< Core 1711:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< Core 1712:Drivers/CMSIS/Include/core_cm7.h **** 1713:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< Core 1714:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< Core 1715:Drivers/CMSIS/Include/core_cm7.h **** 1716:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< Core 1717:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< Core 1718:Drivers/CMSIS/Include/core_cm7.h **** 1719:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< Core 1720:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< Core 1721:Drivers/CMSIS/Include/core_cm7.h **** 1722:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< Core 1723:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< Core 1724:Drivers/CMSIS/Include/core_cm7.h **** 1725:Drivers/CMSIS/Include/core_cm7.h **** /*@} end of group CMSIS_CoreDebug */ 1726:Drivers/CMSIS/Include/core_cm7.h **** 1727:Drivers/CMSIS/Include/core_cm7.h **** 1728:Drivers/CMSIS/Include/core_cm7.h **** /** 1729:Drivers/CMSIS/Include/core_cm7.h **** \ingroup CMSIS_core_register 1730:Drivers/CMSIS/Include/core_cm7.h **** \defgroup CMSIS_core_bitfield Core register bit field macros 1731:Drivers/CMSIS/Include/core_cm7.h **** \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). 1732:Drivers/CMSIS/Include/core_cm7.h **** @{ 1733:Drivers/CMSIS/Include/core_cm7.h **** */ 1734:Drivers/CMSIS/Include/core_cm7.h **** 1735:Drivers/CMSIS/Include/core_cm7.h **** /** 1736:Drivers/CMSIS/Include/core_cm7.h **** \brief Mask and shift a bit field value for use in a register bit range. 1737:Drivers/CMSIS/Include/core_cm7.h **** \param[in] field Name of the register bit field. 1738:Drivers/CMSIS/Include/core_cm7.h **** \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. 1739:Drivers/CMSIS/Include/core_cm7.h **** \return Masked and shifted value. 1740:Drivers/CMSIS/Include/core_cm7.h **** */ ARM GAS /tmp/ccLSPxIe.s page 32 1741:Drivers/CMSIS/Include/core_cm7.h **** #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) 1742:Drivers/CMSIS/Include/core_cm7.h **** 1743:Drivers/CMSIS/Include/core_cm7.h **** /** 1744:Drivers/CMSIS/Include/core_cm7.h **** \brief Mask and shift a register value to extract a bit filed value. 1745:Drivers/CMSIS/Include/core_cm7.h **** \param[in] field Name of the register bit field. 1746:Drivers/CMSIS/Include/core_cm7.h **** \param[in] value Value of register. This parameter is interpreted as an uint32_t type. 1747:Drivers/CMSIS/Include/core_cm7.h **** \return Masked and shifted bit field value. 1748:Drivers/CMSIS/Include/core_cm7.h **** */ 1749:Drivers/CMSIS/Include/core_cm7.h **** #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) 1750:Drivers/CMSIS/Include/core_cm7.h **** 1751:Drivers/CMSIS/Include/core_cm7.h **** /*@} end of group CMSIS_core_bitfield */ 1752:Drivers/CMSIS/Include/core_cm7.h **** 1753:Drivers/CMSIS/Include/core_cm7.h **** 1754:Drivers/CMSIS/Include/core_cm7.h **** /** 1755:Drivers/CMSIS/Include/core_cm7.h **** \ingroup CMSIS_core_register 1756:Drivers/CMSIS/Include/core_cm7.h **** \defgroup CMSIS_core_base Core Definitions 1757:Drivers/CMSIS/Include/core_cm7.h **** \brief Definitions for base addresses, unions, and structures. 1758:Drivers/CMSIS/Include/core_cm7.h **** @{ 1759:Drivers/CMSIS/Include/core_cm7.h **** */ 1760:Drivers/CMSIS/Include/core_cm7.h **** 1761:Drivers/CMSIS/Include/core_cm7.h **** /* Memory mapping of Core Hardware */ 1762:Drivers/CMSIS/Include/core_cm7.h **** #define SCS_BASE (0xE000E000UL) /*!< System Control Space Bas 1763:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ 1764:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ 1765:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ 1766:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address 1767:Drivers/CMSIS/Include/core_cm7.h **** #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ 1768:Drivers/CMSIS/Include/core_cm7.h **** #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ 1769:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Bas 1770:Drivers/CMSIS/Include/core_cm7.h **** 1771:Drivers/CMSIS/Include/core_cm7.h **** #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register 1772:Drivers/CMSIS/Include/core_cm7.h **** #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct 1773:Drivers/CMSIS/Include/core_cm7.h **** #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration st 1774:Drivers/CMSIS/Include/core_cm7.h **** #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struc 1775:Drivers/CMSIS/Include/core_cm7.h **** #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct 1776:Drivers/CMSIS/Include/core_cm7.h **** #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct 1777:Drivers/CMSIS/Include/core_cm7.h **** #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct 1778:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration 1779:Drivers/CMSIS/Include/core_cm7.h **** 1780:Drivers/CMSIS/Include/core_cm7.h **** #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) 1781:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit * 1782:Drivers/CMSIS/Include/core_cm7.h **** #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit * 1783:Drivers/CMSIS/Include/core_cm7.h **** #endif 1784:Drivers/CMSIS/Include/core_cm7.h **** 1785:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ 1786:Drivers/CMSIS/Include/core_cm7.h **** #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ 1787:Drivers/CMSIS/Include/core_cm7.h **** 1788:Drivers/CMSIS/Include/core_cm7.h **** /*@} */ 1789:Drivers/CMSIS/Include/core_cm7.h **** 1790:Drivers/CMSIS/Include/core_cm7.h **** 1791:Drivers/CMSIS/Include/core_cm7.h **** 1792:Drivers/CMSIS/Include/core_cm7.h **** /******************************************************************************* 1793:Drivers/CMSIS/Include/core_cm7.h **** * Hardware Abstraction Layer 1794:Drivers/CMSIS/Include/core_cm7.h **** Core Function Interface contains: 1795:Drivers/CMSIS/Include/core_cm7.h **** - Core NVIC Functions 1796:Drivers/CMSIS/Include/core_cm7.h **** - Core SysTick Functions 1797:Drivers/CMSIS/Include/core_cm7.h **** - Core Debug Functions ARM GAS /tmp/ccLSPxIe.s page 33 1798:Drivers/CMSIS/Include/core_cm7.h **** - Core Register Access Functions 1799:Drivers/CMSIS/Include/core_cm7.h **** ******************************************************************************/ 1800:Drivers/CMSIS/Include/core_cm7.h **** /** 1801:Drivers/CMSIS/Include/core_cm7.h **** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference 1802:Drivers/CMSIS/Include/core_cm7.h **** */ 1803:Drivers/CMSIS/Include/core_cm7.h **** 1804:Drivers/CMSIS/Include/core_cm7.h **** 1805:Drivers/CMSIS/Include/core_cm7.h **** 1806:Drivers/CMSIS/Include/core_cm7.h **** /* ########################## NVIC functions #################################### */ 1807:Drivers/CMSIS/Include/core_cm7.h **** /** 1808:Drivers/CMSIS/Include/core_cm7.h **** \ingroup CMSIS_Core_FunctionInterface 1809:Drivers/CMSIS/Include/core_cm7.h **** \defgroup CMSIS_Core_NVICFunctions NVIC Functions 1810:Drivers/CMSIS/Include/core_cm7.h **** \brief Functions that manage interrupts and exceptions via the NVIC. 1811:Drivers/CMSIS/Include/core_cm7.h **** @{ 1812:Drivers/CMSIS/Include/core_cm7.h **** */ 1813:Drivers/CMSIS/Include/core_cm7.h **** 1814:Drivers/CMSIS/Include/core_cm7.h **** #ifdef CMSIS_NVIC_VIRTUAL 1815:Drivers/CMSIS/Include/core_cm7.h **** #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE 1816:Drivers/CMSIS/Include/core_cm7.h **** #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" 1817:Drivers/CMSIS/Include/core_cm7.h **** #endif 1818:Drivers/CMSIS/Include/core_cm7.h **** #include CMSIS_NVIC_VIRTUAL_HEADER_FILE 1819:Drivers/CMSIS/Include/core_cm7.h **** #else 1820:Drivers/CMSIS/Include/core_cm7.h **** #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping 1821:Drivers/CMSIS/Include/core_cm7.h **** #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping 1822:Drivers/CMSIS/Include/core_cm7.h **** #define NVIC_EnableIRQ __NVIC_EnableIRQ 1823:Drivers/CMSIS/Include/core_cm7.h **** #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ 1824:Drivers/CMSIS/Include/core_cm7.h **** #define NVIC_DisableIRQ __NVIC_DisableIRQ 1825:Drivers/CMSIS/Include/core_cm7.h **** #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ 1826:Drivers/CMSIS/Include/core_cm7.h **** #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ 1827:Drivers/CMSIS/Include/core_cm7.h **** #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ 1828:Drivers/CMSIS/Include/core_cm7.h **** #define NVIC_GetActive __NVIC_GetActive 1829:Drivers/CMSIS/Include/core_cm7.h **** #define NVIC_SetPriority __NVIC_SetPriority 1830:Drivers/CMSIS/Include/core_cm7.h **** #define NVIC_GetPriority __NVIC_GetPriority 1831:Drivers/CMSIS/Include/core_cm7.h **** #define NVIC_SystemReset __NVIC_SystemReset 1832:Drivers/CMSIS/Include/core_cm7.h **** #endif /* CMSIS_NVIC_VIRTUAL */ 1833:Drivers/CMSIS/Include/core_cm7.h **** 1834:Drivers/CMSIS/Include/core_cm7.h **** #ifdef CMSIS_VECTAB_VIRTUAL 1835:Drivers/CMSIS/Include/core_cm7.h **** #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE 1836:Drivers/CMSIS/Include/core_cm7.h **** #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" 1837:Drivers/CMSIS/Include/core_cm7.h **** #endif 1838:Drivers/CMSIS/Include/core_cm7.h **** #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE 1839:Drivers/CMSIS/Include/core_cm7.h **** #else 1840:Drivers/CMSIS/Include/core_cm7.h **** #define NVIC_SetVector __NVIC_SetVector 1841:Drivers/CMSIS/Include/core_cm7.h **** #define NVIC_GetVector __NVIC_GetVector 1842:Drivers/CMSIS/Include/core_cm7.h **** #endif /* (CMSIS_VECTAB_VIRTUAL) */ 1843:Drivers/CMSIS/Include/core_cm7.h **** 1844:Drivers/CMSIS/Include/core_cm7.h **** #define NVIC_USER_IRQ_OFFSET 16 1845:Drivers/CMSIS/Include/core_cm7.h **** 1846:Drivers/CMSIS/Include/core_cm7.h **** 1847:Drivers/CMSIS/Include/core_cm7.h **** /* The following EXC_RETURN values are saved the LR on exception entry */ 1848:Drivers/CMSIS/Include/core_cm7.h **** #define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after ret 1849:Drivers/CMSIS/Include/core_cm7.h **** #define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after retu 1850:Drivers/CMSIS/Include/core_cm7.h **** #define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after retu 1851:Drivers/CMSIS/Include/core_cm7.h **** #define EXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after ret 1852:Drivers/CMSIS/Include/core_cm7.h **** #define EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after retu 1853:Drivers/CMSIS/Include/core_cm7.h **** #define EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after retu 1854:Drivers/CMSIS/Include/core_cm7.h **** ARM GAS /tmp/ccLSPxIe.s page 34 1855:Drivers/CMSIS/Include/core_cm7.h **** 1856:Drivers/CMSIS/Include/core_cm7.h **** /** 1857:Drivers/CMSIS/Include/core_cm7.h **** \brief Set Priority Grouping 1858:Drivers/CMSIS/Include/core_cm7.h **** \details Sets the priority grouping field using the required unlock sequence. 1859:Drivers/CMSIS/Include/core_cm7.h **** The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. 1860:Drivers/CMSIS/Include/core_cm7.h **** Only values from 0..7 are used. 1861:Drivers/CMSIS/Include/core_cm7.h **** In case of a conflict between priority grouping and available 1862:Drivers/CMSIS/Include/core_cm7.h **** priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. 1863:Drivers/CMSIS/Include/core_cm7.h **** \param [in] PriorityGroup Priority grouping field. 1864:Drivers/CMSIS/Include/core_cm7.h **** */ 1865:Drivers/CMSIS/Include/core_cm7.h **** __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) 1866:Drivers/CMSIS/Include/core_cm7.h **** { 1867:Drivers/CMSIS/Include/core_cm7.h **** uint32_t reg_value; 1868:Drivers/CMSIS/Include/core_cm7.h **** uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 a 1869:Drivers/CMSIS/Include/core_cm7.h **** 1870:Drivers/CMSIS/Include/core_cm7.h **** reg_value = SCB->AIRCR; /* read old register 1871:Drivers/CMSIS/Include/core_cm7.h **** reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to chan 1872:Drivers/CMSIS/Include/core_cm7.h **** reg_value = (reg_value | 1873:Drivers/CMSIS/Include/core_cm7.h **** ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | 1874:Drivers/CMSIS/Include/core_cm7.h **** (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key a 1875:Drivers/CMSIS/Include/core_cm7.h **** SCB->AIRCR = reg_value; 1876:Drivers/CMSIS/Include/core_cm7.h **** } 1877:Drivers/CMSIS/Include/core_cm7.h **** 1878:Drivers/CMSIS/Include/core_cm7.h **** 1879:Drivers/CMSIS/Include/core_cm7.h **** /** 1880:Drivers/CMSIS/Include/core_cm7.h **** \brief Get Priority Grouping 1881:Drivers/CMSIS/Include/core_cm7.h **** \details Reads the priority grouping field from the NVIC Interrupt Controller. 1882:Drivers/CMSIS/Include/core_cm7.h **** \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). 1883:Drivers/CMSIS/Include/core_cm7.h **** */ 1884:Drivers/CMSIS/Include/core_cm7.h **** __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) 1885:Drivers/CMSIS/Include/core_cm7.h **** { 1886:Drivers/CMSIS/Include/core_cm7.h **** return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); 1887:Drivers/CMSIS/Include/core_cm7.h **** } 1888:Drivers/CMSIS/Include/core_cm7.h **** 1889:Drivers/CMSIS/Include/core_cm7.h **** 1890:Drivers/CMSIS/Include/core_cm7.h **** /** 1891:Drivers/CMSIS/Include/core_cm7.h **** \brief Enable Interrupt 1892:Drivers/CMSIS/Include/core_cm7.h **** \details Enables a device specific interrupt in the NVIC interrupt controller. 1893:Drivers/CMSIS/Include/core_cm7.h **** \param [in] IRQn Device specific interrupt number. 1894:Drivers/CMSIS/Include/core_cm7.h **** \note IRQn must not be negative. 1895:Drivers/CMSIS/Include/core_cm7.h **** */ 1896:Drivers/CMSIS/Include/core_cm7.h **** __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) 1897:Drivers/CMSIS/Include/core_cm7.h **** { 1898:Drivers/CMSIS/Include/core_cm7.h **** if ((int32_t)(IRQn) >= 0) 1899:Drivers/CMSIS/Include/core_cm7.h **** { 1900:Drivers/CMSIS/Include/core_cm7.h **** NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 1901:Drivers/CMSIS/Include/core_cm7.h **** } 1902:Drivers/CMSIS/Include/core_cm7.h **** } 1903:Drivers/CMSIS/Include/core_cm7.h **** 1904:Drivers/CMSIS/Include/core_cm7.h **** 1905:Drivers/CMSIS/Include/core_cm7.h **** /** 1906:Drivers/CMSIS/Include/core_cm7.h **** \brief Get Interrupt Enable status 1907:Drivers/CMSIS/Include/core_cm7.h **** \details Returns a device specific interrupt enable status from the NVIC interrupt controller. 1908:Drivers/CMSIS/Include/core_cm7.h **** \param [in] IRQn Device specific interrupt number. 1909:Drivers/CMSIS/Include/core_cm7.h **** \return 0 Interrupt is not enabled. 1910:Drivers/CMSIS/Include/core_cm7.h **** \return 1 Interrupt is enabled. 1911:Drivers/CMSIS/Include/core_cm7.h **** \note IRQn must not be negative. ARM GAS /tmp/ccLSPxIe.s page 35 1912:Drivers/CMSIS/Include/core_cm7.h **** */ 1913:Drivers/CMSIS/Include/core_cm7.h **** __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) 1914:Drivers/CMSIS/Include/core_cm7.h **** { 1915:Drivers/CMSIS/Include/core_cm7.h **** if ((int32_t)(IRQn) >= 0) 1916:Drivers/CMSIS/Include/core_cm7.h **** { 1917:Drivers/CMSIS/Include/core_cm7.h **** return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL) 1918:Drivers/CMSIS/Include/core_cm7.h **** } 1919:Drivers/CMSIS/Include/core_cm7.h **** else 1920:Drivers/CMSIS/Include/core_cm7.h **** { 1921:Drivers/CMSIS/Include/core_cm7.h **** return(0U); 1922:Drivers/CMSIS/Include/core_cm7.h **** } 1923:Drivers/CMSIS/Include/core_cm7.h **** } 1924:Drivers/CMSIS/Include/core_cm7.h **** 1925:Drivers/CMSIS/Include/core_cm7.h **** 1926:Drivers/CMSIS/Include/core_cm7.h **** /** 1927:Drivers/CMSIS/Include/core_cm7.h **** \brief Disable Interrupt 1928:Drivers/CMSIS/Include/core_cm7.h **** \details Disables a device specific interrupt in the NVIC interrupt controller. 1929:Drivers/CMSIS/Include/core_cm7.h **** \param [in] IRQn Device specific interrupt number. 1930:Drivers/CMSIS/Include/core_cm7.h **** \note IRQn must not be negative. 1931:Drivers/CMSIS/Include/core_cm7.h **** */ 1932:Drivers/CMSIS/Include/core_cm7.h **** __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) 1933:Drivers/CMSIS/Include/core_cm7.h **** { 1934:Drivers/CMSIS/Include/core_cm7.h **** if ((int32_t)(IRQn) >= 0) 1935:Drivers/CMSIS/Include/core_cm7.h **** { 1936:Drivers/CMSIS/Include/core_cm7.h **** NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 1937:Drivers/CMSIS/Include/core_cm7.h **** __DSB(); 1938:Drivers/CMSIS/Include/core_cm7.h **** __ISB(); 1939:Drivers/CMSIS/Include/core_cm7.h **** } 1940:Drivers/CMSIS/Include/core_cm7.h **** } 1941:Drivers/CMSIS/Include/core_cm7.h **** 1942:Drivers/CMSIS/Include/core_cm7.h **** 1943:Drivers/CMSIS/Include/core_cm7.h **** /** 1944:Drivers/CMSIS/Include/core_cm7.h **** \brief Get Pending Interrupt 1945:Drivers/CMSIS/Include/core_cm7.h **** \details Reads the NVIC pending register and returns the pending bit for the specified device spe 1946:Drivers/CMSIS/Include/core_cm7.h **** \param [in] IRQn Device specific interrupt number. 1947:Drivers/CMSIS/Include/core_cm7.h **** \return 0 Interrupt status is not pending. 1948:Drivers/CMSIS/Include/core_cm7.h **** \return 1 Interrupt status is pending. 1949:Drivers/CMSIS/Include/core_cm7.h **** \note IRQn must not be negative. 1950:Drivers/CMSIS/Include/core_cm7.h **** */ 1951:Drivers/CMSIS/Include/core_cm7.h **** __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) 1952:Drivers/CMSIS/Include/core_cm7.h **** { 1953:Drivers/CMSIS/Include/core_cm7.h **** if ((int32_t)(IRQn) >= 0) 1954:Drivers/CMSIS/Include/core_cm7.h **** { 1955:Drivers/CMSIS/Include/core_cm7.h **** return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL) 1956:Drivers/CMSIS/Include/core_cm7.h **** } 1957:Drivers/CMSIS/Include/core_cm7.h **** else 1958:Drivers/CMSIS/Include/core_cm7.h **** { 1959:Drivers/CMSIS/Include/core_cm7.h **** return(0U); 1960:Drivers/CMSIS/Include/core_cm7.h **** } 1961:Drivers/CMSIS/Include/core_cm7.h **** } 1962:Drivers/CMSIS/Include/core_cm7.h **** 1963:Drivers/CMSIS/Include/core_cm7.h **** 1964:Drivers/CMSIS/Include/core_cm7.h **** /** 1965:Drivers/CMSIS/Include/core_cm7.h **** \brief Set Pending Interrupt 1966:Drivers/CMSIS/Include/core_cm7.h **** \details Sets the pending bit of a device specific interrupt in the NVIC pending register. 1967:Drivers/CMSIS/Include/core_cm7.h **** \param [in] IRQn Device specific interrupt number. 1968:Drivers/CMSIS/Include/core_cm7.h **** \note IRQn must not be negative. ARM GAS /tmp/ccLSPxIe.s page 36 1969:Drivers/CMSIS/Include/core_cm7.h **** */ 1970:Drivers/CMSIS/Include/core_cm7.h **** __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) 1971:Drivers/CMSIS/Include/core_cm7.h **** { 1972:Drivers/CMSIS/Include/core_cm7.h **** if ((int32_t)(IRQn) >= 0) 1973:Drivers/CMSIS/Include/core_cm7.h **** { 1974:Drivers/CMSIS/Include/core_cm7.h **** NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 1975:Drivers/CMSIS/Include/core_cm7.h **** } 1976:Drivers/CMSIS/Include/core_cm7.h **** } 1977:Drivers/CMSIS/Include/core_cm7.h **** 1978:Drivers/CMSIS/Include/core_cm7.h **** 1979:Drivers/CMSIS/Include/core_cm7.h **** /** 1980:Drivers/CMSIS/Include/core_cm7.h **** \brief Clear Pending Interrupt 1981:Drivers/CMSIS/Include/core_cm7.h **** \details Clears the pending bit of a device specific interrupt in the NVIC pending register. 1982:Drivers/CMSIS/Include/core_cm7.h **** \param [in] IRQn Device specific interrupt number. 1983:Drivers/CMSIS/Include/core_cm7.h **** \note IRQn must not be negative. 1984:Drivers/CMSIS/Include/core_cm7.h **** */ 1985:Drivers/CMSIS/Include/core_cm7.h **** __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) 1986:Drivers/CMSIS/Include/core_cm7.h **** { 1987:Drivers/CMSIS/Include/core_cm7.h **** if ((int32_t)(IRQn) >= 0) 1988:Drivers/CMSIS/Include/core_cm7.h **** { 1989:Drivers/CMSIS/Include/core_cm7.h **** NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 1990:Drivers/CMSIS/Include/core_cm7.h **** } 1991:Drivers/CMSIS/Include/core_cm7.h **** } 1992:Drivers/CMSIS/Include/core_cm7.h **** 1993:Drivers/CMSIS/Include/core_cm7.h **** 1994:Drivers/CMSIS/Include/core_cm7.h **** /** 1995:Drivers/CMSIS/Include/core_cm7.h **** \brief Get Active Interrupt 1996:Drivers/CMSIS/Include/core_cm7.h **** \details Reads the active register in the NVIC and returns the active bit for the device specific 1997:Drivers/CMSIS/Include/core_cm7.h **** \param [in] IRQn Device specific interrupt number. 1998:Drivers/CMSIS/Include/core_cm7.h **** \return 0 Interrupt status is not active. 1999:Drivers/CMSIS/Include/core_cm7.h **** \return 1 Interrupt status is active. 2000:Drivers/CMSIS/Include/core_cm7.h **** \note IRQn must not be negative. 2001:Drivers/CMSIS/Include/core_cm7.h **** */ 2002:Drivers/CMSIS/Include/core_cm7.h **** __STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) 2003:Drivers/CMSIS/Include/core_cm7.h **** { 2004:Drivers/CMSIS/Include/core_cm7.h **** if ((int32_t)(IRQn) >= 0) 2005:Drivers/CMSIS/Include/core_cm7.h **** { 2006:Drivers/CMSIS/Include/core_cm7.h **** return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL) 2007:Drivers/CMSIS/Include/core_cm7.h **** } 2008:Drivers/CMSIS/Include/core_cm7.h **** else 2009:Drivers/CMSIS/Include/core_cm7.h **** { 2010:Drivers/CMSIS/Include/core_cm7.h **** return(0U); 2011:Drivers/CMSIS/Include/core_cm7.h **** } 2012:Drivers/CMSIS/Include/core_cm7.h **** } 2013:Drivers/CMSIS/Include/core_cm7.h **** 2014:Drivers/CMSIS/Include/core_cm7.h **** 2015:Drivers/CMSIS/Include/core_cm7.h **** /** 2016:Drivers/CMSIS/Include/core_cm7.h **** \brief Set Interrupt Priority 2017:Drivers/CMSIS/Include/core_cm7.h **** \details Sets the priority of a device specific interrupt or a processor exception. 2018:Drivers/CMSIS/Include/core_cm7.h **** The interrupt number can be positive to specify a device specific interrupt, 2019:Drivers/CMSIS/Include/core_cm7.h **** or negative to specify a processor exception. 2020:Drivers/CMSIS/Include/core_cm7.h **** \param [in] IRQn Interrupt number. 2021:Drivers/CMSIS/Include/core_cm7.h **** \param [in] priority Priority to set. 2022:Drivers/CMSIS/Include/core_cm7.h **** \note The priority cannot be set for every processor exception. 2023:Drivers/CMSIS/Include/core_cm7.h **** */ 2024:Drivers/CMSIS/Include/core_cm7.h **** __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) 2025:Drivers/CMSIS/Include/core_cm7.h **** { ARM GAS /tmp/ccLSPxIe.s page 37 2026:Drivers/CMSIS/Include/core_cm7.h **** if ((int32_t)(IRQn) >= 0) 2027:Drivers/CMSIS/Include/core_cm7.h **** { 2028:Drivers/CMSIS/Include/core_cm7.h **** NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & ( 2029:Drivers/CMSIS/Include/core_cm7.h **** } 2030:Drivers/CMSIS/Include/core_cm7.h **** else 2031:Drivers/CMSIS/Include/core_cm7.h **** { 2032:Drivers/CMSIS/Include/core_cm7.h **** SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & ( 2033:Drivers/CMSIS/Include/core_cm7.h **** } 2034:Drivers/CMSIS/Include/core_cm7.h **** } 2035:Drivers/CMSIS/Include/core_cm7.h **** 2036:Drivers/CMSIS/Include/core_cm7.h **** 2037:Drivers/CMSIS/Include/core_cm7.h **** /** 2038:Drivers/CMSIS/Include/core_cm7.h **** \brief Get Interrupt Priority 2039:Drivers/CMSIS/Include/core_cm7.h **** \details Reads the priority of a device specific interrupt or a processor exception. 2040:Drivers/CMSIS/Include/core_cm7.h **** The interrupt number can be positive to specify a device specific interrupt, 2041:Drivers/CMSIS/Include/core_cm7.h **** or negative to specify a processor exception. 2042:Drivers/CMSIS/Include/core_cm7.h **** \param [in] IRQn Interrupt number. 2043:Drivers/CMSIS/Include/core_cm7.h **** \return Interrupt Priority. 2044:Drivers/CMSIS/Include/core_cm7.h **** Value is aligned automatically to the implemented priority bits of the microc 2045:Drivers/CMSIS/Include/core_cm7.h **** */ 2046:Drivers/CMSIS/Include/core_cm7.h **** __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) 2047:Drivers/CMSIS/Include/core_cm7.h **** { 2048:Drivers/CMSIS/Include/core_cm7.h **** 2049:Drivers/CMSIS/Include/core_cm7.h **** if ((int32_t)(IRQn) >= 0) 2050:Drivers/CMSIS/Include/core_cm7.h **** { 2051:Drivers/CMSIS/Include/core_cm7.h **** return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); 2052:Drivers/CMSIS/Include/core_cm7.h **** } 2053:Drivers/CMSIS/Include/core_cm7.h **** else 2054:Drivers/CMSIS/Include/core_cm7.h **** { 2055:Drivers/CMSIS/Include/core_cm7.h **** return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); 2056:Drivers/CMSIS/Include/core_cm7.h **** } 2057:Drivers/CMSIS/Include/core_cm7.h **** } 2058:Drivers/CMSIS/Include/core_cm7.h **** 2059:Drivers/CMSIS/Include/core_cm7.h **** 2060:Drivers/CMSIS/Include/core_cm7.h **** /** 2061:Drivers/CMSIS/Include/core_cm7.h **** \brief Encode Priority 2062:Drivers/CMSIS/Include/core_cm7.h **** \details Encodes the priority for an interrupt with the given priority group, 2063:Drivers/CMSIS/Include/core_cm7.h **** preemptive priority value, and subpriority value. 2064:Drivers/CMSIS/Include/core_cm7.h **** In case of a conflict between priority grouping and available 2065:Drivers/CMSIS/Include/core_cm7.h **** priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. 2066:Drivers/CMSIS/Include/core_cm7.h **** \param [in] PriorityGroup Used priority group. 2067:Drivers/CMSIS/Include/core_cm7.h **** \param [in] PreemptPriority Preemptive priority value (starting from 0). 2068:Drivers/CMSIS/Include/core_cm7.h **** \param [in] SubPriority Subpriority value (starting from 0). 2069:Drivers/CMSIS/Include/core_cm7.h **** \return Encoded priority. Value can be used in the function \ref NVIC_SetP 2070:Drivers/CMSIS/Include/core_cm7.h **** */ 2071:Drivers/CMSIS/Include/core_cm7.h **** __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uin 2072:Drivers/CMSIS/Include/core_cm7.h **** { 29 .loc 2 2072 1 view -0 30 .cfi_startproc 31 @ args = 0, pretend = 0, frame = 0 32 @ frame_needed = 0, uses_anonymous_args = 0 33 .loc 2 2072 1 is_stmt 0 view .LVU1 34 0000 00B5 push {lr} 35 .LCFI0: 36 .cfi_def_cfa_offset 4 37 .cfi_offset 14, -4 2073:Drivers/CMSIS/Include/core_cm7.h **** uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used ARM GAS /tmp/ccLSPxIe.s page 38 38 .loc 2 2073 3 is_stmt 1 view .LVU2 39 .loc 2 2073 12 is_stmt 0 view .LVU3 40 0002 00F00700 and r0, r0, #7 41 .LVL1: 2074:Drivers/CMSIS/Include/core_cm7.h **** uint32_t PreemptPriorityBits; 42 .loc 2 2074 3 is_stmt 1 view .LVU4 2075:Drivers/CMSIS/Include/core_cm7.h **** uint32_t SubPriorityBits; 43 .loc 2 2075 3 view .LVU5 2076:Drivers/CMSIS/Include/core_cm7.h **** 2077:Drivers/CMSIS/Include/core_cm7.h **** PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NV 44 .loc 2 2077 3 view .LVU6 45 .loc 2 2077 31 is_stmt 0 view .LVU7 46 0006 C0F1070C rsb ip, r0, #7 47 .loc 2 2077 23 view .LVU8 48 000a BCF1040F cmp ip, #4 49 000e 28BF it cs 50 0010 4FF0040C movcs ip, #4 51 .LVL2: 2078:Drivers/CMSIS/Include/core_cm7.h **** SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint 52 .loc 2 2078 3 is_stmt 1 view .LVU9 53 .loc 2 2078 44 is_stmt 0 view .LVU10 54 0014 031D adds r3, r0, #4 55 .loc 2 2078 109 view .LVU11 56 0016 062B cmp r3, #6 57 0018 0FD9 bls .L3 58 .loc 2 2078 109 discriminator 1 view .LVU12 59 001a C31E subs r3, r0, #3 60 .L2: 61 .LVL3: 2079:Drivers/CMSIS/Include/core_cm7.h **** 2080:Drivers/CMSIS/Include/core_cm7.h **** return ( 62 .loc 2 2080 3 is_stmt 1 view .LVU13 2081:Drivers/CMSIS/Include/core_cm7.h **** ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits 63 .loc 2 2081 30 is_stmt 0 view .LVU14 64 001c 4FF0FF3E mov lr, #-1 65 0020 0EFA0CF0 lsl r0, lr, ip 66 .LVL4: 67 .loc 2 2081 30 view .LVU15 68 0024 21EA0001 bic r1, r1, r0 69 .LVL5: 70 .loc 2 2081 82 view .LVU16 71 0028 9940 lsls r1, r1, r3 2082:Drivers/CMSIS/Include/core_cm7.h **** ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) 72 .loc 2 2082 30 view .LVU17 73 002a 0EFA03FE lsl lr, lr, r3 74 002e 22EA0E02 bic r2, r2, lr 75 .LVL6: 2083:Drivers/CMSIS/Include/core_cm7.h **** ); 2084:Drivers/CMSIS/Include/core_cm7.h **** } 76 .loc 2 2084 1 view .LVU18 77 0032 41EA0200 orr r0, r1, r2 78 0036 5DF804FB ldr pc, [sp], #4 79 .LVL7: 80 .L3: 2078:Drivers/CMSIS/Include/core_cm7.h **** 81 .loc 2 2078 109 discriminator 2 view .LVU19 82 003a 0023 movs r3, #0 ARM GAS /tmp/ccLSPxIe.s page 39 83 003c EEE7 b .L2 84 .cfi_endproc 85 .LFE113: 87 .section .text.MX_SDMMC1_SD_Init,"ax",%progbits 88 .align 1 89 .syntax unified 90 .thumb 91 .thumb_func 93 MX_SDMMC1_SD_Init: 94 .LFB1190: 1:Src/main.c **** /* USER CODE BEGIN Header */ 2:Src/main.c **** /** 3:Src/main.c **** ****************************************************************************** 4:Src/main.c **** * @file : main.c 5:Src/main.c **** * @brief : Main program body 6:Src/main.c **** ****************************************************************************** 7:Src/main.c **** * @attention 8:Src/main.c **** * 9:Src/main.c **** * Copyright (c) 2023 STMicroelectronics. 10:Src/main.c **** * All rights reserved. 11:Src/main.c **** * 12:Src/main.c **** * This software is licensed under terms that can be found in the LICENSE file 13:Src/main.c **** * in the root directory of this software component. 14:Src/main.c **** * If no LICENSE file comes with this software, it is provided AS-IS. 15:Src/main.c **** * 16:Src/main.c **** ****************************************************************************** 17:Src/main.c **** */ 18:Src/main.c **** /* USER CODE END Header */ 19:Src/main.c **** /* Includes ------------------------------------------------------------------*/ 20:Src/main.c **** #include "main.h" 21:Src/main.c **** #include "fatfs.h" 22:Src/main.c **** 23:Src/main.c **** /* Private includes ----------------------------------------------------------*/ 24:Src/main.c **** /* USER CODE BEGIN Includes */ 25:Src/main.c **** // #include "math.h" 26:Src/main.c **** #include "File_Handling.h" 27:Src/main.c **** #include 28:Src/main.c **** /* USER CODE END Includes */ 29:Src/main.c **** 30:Src/main.c **** /* Private typedef -----------------------------------------------------------*/ 31:Src/main.c **** /* USER CODE BEGIN PTD */ 32:Src/main.c **** 33:Src/main.c **** /* USER CODE END PTD */ 34:Src/main.c **** 35:Src/main.c **** /* Private define ------------------------------------------------------------*/ 36:Src/main.c **** /* USER CODE BEGIN PD */ 37:Src/main.c **** // AD9102 register addresses and bit fields (see ad9102.pdf) 38:Src/main.c **** #define AD9102_REG_RAMUPDATE 0x001Du 39:Src/main.c **** #define AD9102_REG_PAT_STATUS 0x001Eu 40:Src/main.c **** #define AD9102_REG_PAT_TYPE 0x001Fu 41:Src/main.c **** #define AD9102_REG_SPICONFIG 0x0000u 42:Src/main.c **** #define AD9102_REG_POWERCONFIG 0x0001u 43:Src/main.c **** #define AD9102_REG_CLOCKCONFIG 0x0002u 44:Src/main.c **** #define AD9102_REG_WAV_CONFIG 0x0027u 45:Src/main.c **** #define AD9102_REG_PAT_TIMEBASE 0x0028u 46:Src/main.c **** #define AD9102_REG_PAT_PERIOD 0x0029u 47:Src/main.c **** #define AD9102_REG_DAC_PAT 0x002Bu ARM GAS /tmp/ccLSPxIe.s page 40 48:Src/main.c **** #define AD9102_REG_SAW_CONFIG 0x0037u 49:Src/main.c **** #define AD9102_REG_START_DLY 0x005Cu 50:Src/main.c **** #define AD9102_REG_START_ADDR 0x005Du 51:Src/main.c **** #define AD9102_REG_STOP_ADDR 0x005Eu 52:Src/main.c **** #define AD9102_REG_SRAM_DATA_BASE 0x6000u 53:Src/main.c **** #define AD9102_REG_CFG_ERROR 0x0060u 54:Src/main.c **** 55:Src/main.c **** #define AD9102_PAT_STATUS_RUN (1u << 0) 56:Src/main.c **** 57:Src/main.c **** #define AD9102_WAV_PRESTORE_SEL_SHIFT 4 58:Src/main.c **** #define AD9102_WAV_WAVE_SEL_SHIFT 0 59:Src/main.c **** #define AD9102_WAV_PRESTORE_SAW 1u 60:Src/main.c **** #define AD9102_WAV_WAVE_SEL_PRESTORE 1u 61:Src/main.c **** 62:Src/main.c **** #define AD9102_SAW_STEP_SHIFT 2 63:Src/main.c **** #define AD9102_SAW_TYPE_SHIFT 0 64:Src/main.c **** #define AD9102_SAW_TYPE_UP 0u 65:Src/main.c **** #define AD9102_SAW_TYPE_DOWN 1u 66:Src/main.c **** #define AD9102_SAW_TYPE_TRI 2u 67:Src/main.c **** #define AD9102_SAW_TYPE_ZERO 3u 68:Src/main.c **** 69:Src/main.c **** #define AD9102_REG_COUNT 66u 70:Src/main.c **** 71:Src/main.c **** #define AD9102_EX4_WAV_CONFIG 0x3212u 72:Src/main.c **** #define AD9102_EX4_PAT_TIMEBASE 0x0121u 73:Src/main.c **** #define AD9102_EX4_PAT_PERIOD 0xFFFFu 74:Src/main.c **** #define AD9102_EX4_SAW_CONFIG 0x0606u 75:Src/main.c **** 76:Src/main.c **** #define AD9102_EX2_WAV_CONFIG 0x3030u 77:Src/main.c **** #define AD9102_EX2_DAC_PAT 0x0101u 78:Src/main.c **** #define AD9102_EX2_SAW_CONFIG 0x0200u 79:Src/main.c **** #define AD9102_SRAM_PAT_PERIOD_BASE_DEFAULT 0x1u 80:Src/main.c **** #define AD9102_SRAM_START_DELAY_BASE_DEFAULT 0x1u 81:Src/main.c **** #define AD9102_SRAM_START_DLY_DEFAULT 0x0000u 82:Src/main.c **** #define AD9102_SRAM_HOLD_DEFAULT 0x1u 83:Src/main.c **** #define AD9102_SRAM_AMP_DEFAULT 8191u 84:Src/main.c **** #define AD9102_SRAM_SAMPLES_DEFAULT 16u 85:Src/main.c **** #define AD9102_SRAM_MAX_SAMPLES 4096u 86:Src/main.c **** #define AD9102_SRAM_RAMP_MIN (-8192) 87:Src/main.c **** #define AD9102_SRAM_RAMP_MAX (8191) 88:Src/main.c **** #define AD9102_SRAM_RAMP_SPAN (AD9102_SRAM_RAMP_MAX - AD9102_SRAM_RAMP_MIN) 89:Src/main.c **** 90:Src/main.c **** #define AD9102_SAW_STEP_DEFAULT 1u 91:Src/main.c **** #define AD9102_PAT_PERIOD_BASE_DEFAULT 0x2u 92:Src/main.c **** #define AD9102_START_DELAY_BASE_DEFAULT 0x1u 93:Src/main.c **** #define AD9102_PAT_TIMEBASE_HOLD_DEFAULT 0x1u 94:Src/main.c **** #define AD9102_PAT_PERIOD_DEFAULT 0xFFFFu 95:Src/main.c **** 96:Src/main.c **** #define AD9102_FLAG_ENABLE 0x0001u 97:Src/main.c **** #define AD9102_FLAG_TRIANGLE 0x0002u 98:Src/main.c **** #define AD9102_FLAG_SRAM 0x0004u 99:Src/main.c **** #define AD9102_FLAG_SRAM_FMT 0x0008u 100:Src/main.c **** #define AD9102_WAVE_OPCODE_BEGIN 0x0001u 101:Src/main.c **** #define AD9102_WAVE_OPCODE_COMMIT 0x0002u 102:Src/main.c **** #define AD9102_WAVE_OPCODE_CANCEL 0x0003u 103:Src/main.c **** #define AD9102_WAVE_MAX_CHUNK_SAMPLES 12u 104:Src/main.c **** ARM GAS /tmp/ccLSPxIe.s page 41 105:Src/main.c **** #define AD9833_FLAG_ENABLE 0x0001u 106:Src/main.c **** #define AD9833_FLAG_TRIANGLE 0x0002u 107:Src/main.c **** #define DS1809_FLAG_UC 0x0001u 108:Src/main.c **** #define DS1809_FLAG_DC 0x0002u 109:Src/main.c **** #define DS1809_PULSE_MS_DEFAULT 2u 110:Src/main.c **** #define STM32_DAC_FLAG_ENABLE 0x0001u 111:Src/main.c **** #define STM32_DAC_CODE_MAX 4095u 112:Src/main.c **** /* USER CODE END PD */ 113:Src/main.c **** 114:Src/main.c **** /* Private macro -------------------------------------------------------------*/ 115:Src/main.c **** /* USER CODE BEGIN PM */ 116:Src/main.c **** 117:Src/main.c **** /* USER CODE END PM */ 118:Src/main.c **** 119:Src/main.c **** /* Private variables ---------------------------------------------------------*/ 120:Src/main.c **** ADC_HandleTypeDef hadc1; 121:Src/main.c **** ADC_HandleTypeDef hadc3; 122:Src/main.c **** 123:Src/main.c **** SD_HandleTypeDef hsd1; 124:Src/main.c **** 125:Src/main.c **** TIM_HandleTypeDef htim4; 126:Src/main.c **** TIM_HandleTypeDef htim8; 127:Src/main.c **** TIM_HandleTypeDef htim1; 128:Src/main.c **** TIM_HandleTypeDef htim10; 129:Src/main.c **** TIM_HandleTypeDef htim11; 130:Src/main.c **** 131:Src/main.c **** UART_HandleTypeDef huart8; 132:Src/main.c **** 133:Src/main.c **** /* USER CODE BEGIN PV */ 134:Src/main.c **** uint32_t TO6, TO6_before, TO6_stop, TO6_uart, SD_SEEK, SD_SLIDE, temp32, TO7, TO7_before, TO7_PID, 135:Src/main.c **** uint8_t uart_buf, CPU_state, CPU_state_old, UART_transmission_request, State_Data[2], UART_DATA[DL_ 136:Src/main.c **** uint16_t UART_rec_incr, UART_header, CS_result, temp16, Long_Data[DL_16], COMMAND[CL_16];//, SD_mat 137:Src/main.c **** FRESULT fresult; // result 138:Src/main.c **** int test; 139:Src/main.c **** unsigned long fgoto, sizeoffile;//file pointer of the file object & size of file FPGA_RECEIVE_DATA_ 140:Src/main.c **** 141:Src/main.c **** LDx_SetupTypeDef LD1_curr_setup, LD2_curr_setup, LD1_def_setup, LD2_def_setup; 142:Src/main.c **** Work_SetupTypeDef Curr_setup, Def_setup; 143:Src/main.c **** LDx_ParamTypeDef LD1_param, LD2_param; 144:Src/main.c **** 145:Src/main.c **** LD_Blinker_StateTypeDef LD_blinker; 146:Src/main.c **** 147:Src/main.c **** task_t task; 148:Src/main.c **** 149:Src/main.c **** static const uint16_t ad9102_reg_addr[AD9102_REG_COUNT] = { 150:Src/main.c **** 0x0000u, 0x0001u, 0x0002u, 0x0003u, 0x0004u, 0x0005u, 0x0006u, 0x0007u, 151:Src/main.c **** 0x0008u, 0x0009u, 0x000au, 0x000bu, 0x000cu, 0x000du, 0x000eu, 0x001fu, 152:Src/main.c **** 0x0020u, 0x0022u, 0x0023u, 0x0024u, 0x0025u, 0x0026u, 0x0027u, 0x0028u, 153:Src/main.c **** 0x0029u, 0x002au, 0x002bu, 0x002cu, 0x002du, 0x002eu, 0x002fu, 0x0030u, 154:Src/main.c **** 0x0031u, 0x0032u, 0x0033u, 0x0034u, 0x0035u, 0x0036u, 0x0037u, 0x003eu, 155:Src/main.c **** 0x003fu, 0x0040u, 0x0041u, 0x0042u, 0x0043u, 0x0044u, 0x0045u, 0x0047u, 156:Src/main.c **** 0x0050u, 0x0051u, 0x0052u, 0x0053u, 0x0054u, 0x0055u, 0x0056u, 0x0057u, 157:Src/main.c **** 0x0058u, 0x0059u, 0x005au, 0x005bu, 0x005cu, 0x005du, 0x005eu, 0x005fu, 158:Src/main.c **** 0x001eu, 0x001du 159:Src/main.c **** }; 160:Src/main.c **** 161:Src/main.c **** static const uint16_t ad9102_example4_regval[AD9102_REG_COUNT] = { ARM GAS /tmp/ccLSPxIe.s page 42 162:Src/main.c **** 0x0000u, 0x0000u, 0x0000u, 0x0000u, 0x0000u, 0x0000u, 0x0000u, 0x4000u, 163:Src/main.c **** 0x0000u, 0x0000u, 0x0000u, 0x0000u, 0x1f00u, 0x0000u, 0x0000u, 0x0000u, 164:Src/main.c **** 0x000eu, 0x0000u, 0x0000u, 0x0000u, 0x0000u, 0x0000u, 0x3212u, 0x0121u, 165:Src/main.c **** 0xffffu, 0x0000u, 0x0101u, 0x0003u, 0x0000u, 0x0000u, 0x0000u, 0x0000u, 166:Src/main.c **** 0x0000u, 0x0000u, 0x0000u, 0x0000u, 0x4000u, 0x0000u, 0x0606u, 0x1999u, 167:Src/main.c **** 0x9a00u, 0x0000u, 0x0000u, 0x0000u, 0x0000u, 0x0000u, 0x0000u, 0x0000u, 168:Src/main.c **** 0x0fa0u, 0x0000u, 0x0000u, 0x0000u, 0x0000u, 0x0000u, 0x0000u, 0x0000u, 169:Src/main.c **** 0x0000u, 0x0000u, 0x0000u, 0x0000u, 0x0000u, 0x0000u, 0x0000u, 0x16ffu, 170:Src/main.c **** 0x0001u, 0x0001u 171:Src/main.c **** }; 172:Src/main.c **** 173:Src/main.c **** static const uint16_t ad9102_example2_regval[AD9102_REG_COUNT] = { 174:Src/main.c **** 0x0000u, 0x0e00u, 0x0000u, 0x0000u, 0x0000u, 0x0000u, 0x0000u, 0x4000u, 175:Src/main.c **** 0x0000u, 0x0000u, 0x0000u, 0x0000u, 0x1f00u, 0x0000u, 0x0000u, 0x0000u, 176:Src/main.c **** 0x000eu, 0x0000u, 0x0000u, 0x0000u, 0x0000u, 0x0000u, 0x3030u, 0x0111u, 177:Src/main.c **** 0xffffu, 0x0000u, 0x0101u, 0x0003u, 0x0000u, 0x0000u, 0x0000u, 0x0000u, 178:Src/main.c **** 0x0000u, 0x0000u, 0x0000u, 0x0000u, 0x4000u, 0x0000u, 0x0200u, 0x0000u, 179:Src/main.c **** 0x0000u, 0x0000u, 0x0000u, 0x0000u, 0x0000u, 0x0000u, 0x0000u, 0x0000u, 180:Src/main.c **** 0x0000u, 0x0000u, 0x0000u, 0x0000u, 0x0000u, 0x0000u, 0x0000u, 0x0000u, 181:Src/main.c **** 0x0000u, 0x0000u, 0x0000u, 0x0000u, 0x0fa0u, 0x0000u, 0x3ff0u, 0x0100u, 182:Src/main.c **** 0x0001u, 0x0001u 183:Src/main.c **** }; 184:Src/main.c **** 185:Src/main.c **** static uint8_t ad9102_wave_upload_active = 0u; 186:Src/main.c **** static uint16_t ad9102_wave_expected_samples = 0u; 187:Src/main.c **** static uint16_t ad9102_wave_written_samples = 0u; 188:Src/main.c **** 189:Src/main.c **** 190:Src/main.c **** 191:Src/main.c **** 192:Src/main.c **** /* USER CODE END PV */ 193:Src/main.c **** 194:Src/main.c **** /* Private function prototypes -----------------------------------------------*/ 195:Src/main.c **** void SystemClock_Config(void); 196:Src/main.c **** static void MX_GPIO_Init(void); 197:Src/main.c **** static void MX_DMA_Init(void); 198:Src/main.c **** static void MX_SPI4_Init(void); 199:Src/main.c **** static void MX_TIM2_Init(void); 200:Src/main.c **** static void MX_TIM5_Init(void); 201:Src/main.c **** static void MX_ADC1_Init(void); 202:Src/main.c **** static void MX_ADC3_Init(void); 203:Src/main.c **** static void MX_SPI2_Init(void); 204:Src/main.c **** static void MX_SPI5_Init(void); 205:Src/main.c **** static void MX_SPI6_Init(void); 206:Src/main.c **** static void MX_USART1_UART_Init(void); 207:Src/main.c **** static void MX_SDMMC1_SD_Init(void); 208:Src/main.c **** static void MX_TIM7_Init(void); 209:Src/main.c **** static void MX_TIM6_Init(void); 210:Src/main.c **** static void MX_TIM10_Init(void); 211:Src/main.c **** static void MX_UART8_Init(void); 212:Src/main.c **** static void MX_TIM8_Init(void); 213:Src/main.c **** static void MX_TIM11_Init(void); 214:Src/main.c **** static void MX_TIM4_Init(void); 215:Src/main.c **** static void MX_TIM1_Init(void); 216:Src/main.c **** /* USER CODE BEGIN PFP */ 217:Src/main.c **** static void Init_params(void); 218:Src/main.c **** static void Decode_uart(uint16_t *Command, LDx_SetupTypeDef *LD1_curr_setup, LDx_SetupTypeDef *LD2_ ARM GAS /tmp/ccLSPxIe.s page 43 219:Src/main.c **** static void Decode_task(uint16_t *Command, LDx_SetupTypeDef *LD1_curr_setup, LDx_SetupTypeDef *LD2_ 220:Src/main.c **** void Set_LTEC(uint8_t num, uint16_t DATA); 221:Src/main.c **** static uint16_t MPhD_T(uint8_t num); 222:Src/main.c **** static uint16_t Get_ADC(uint8_t num); 223:Src/main.c **** static uint16_t PID_Controller_Temp(LDx_SetupTypeDef * LDx_curr_setup, LDx_ParamTypeDef * LDx_resul 224:Src/main.c **** static void AD9102_Init(void); 225:Src/main.c **** static void AD9102_WriteReg(uint16_t addr, uint16_t value); 226:Src/main.c **** static uint16_t AD9102_ReadReg(uint16_t addr); 227:Src/main.c **** static void AD9102_WriteRegTable(const uint16_t *values, uint16_t count); 228:Src/main.c **** static uint16_t AD9102_Apply(uint8_t saw_type, uint8_t enable, uint8_t saw_step, uint8_t pat_base, 229:Src/main.c **** static uint16_t AD9102_ApplySram(uint8_t enable, uint16_t samples, uint8_t hold, uint8_t triangle, 230:Src/main.c **** static void AD9102_LoadSramRamp(uint16_t samples, uint8_t triangle, uint16_t amplitude); 231:Src/main.c **** static void AD9102_ResetWaveUploadState(void); 232:Src/main.c **** static void AD9102_StopOutput(void); 233:Src/main.c **** static void AD9102_StartOutput(void); 234:Src/main.c **** static void AD9102_ConfigureSramPlayback(uint16_t samples, uint8_t hold); 235:Src/main.c **** static uint8_t AD9102_BeginWaveUpload(uint16_t samples); 236:Src/main.c **** static uint8_t AD9102_WriteWaveUploadChunk(const uint16_t *samples, uint16_t chunk_count); 237:Src/main.c **** static uint16_t AD9102_CommitWaveUpload(uint8_t *ok); 238:Src/main.c **** static void AD9102_CancelWaveUpload(void); 239:Src/main.c **** static uint8_t AD9102_CheckFlags(uint16_t pat_status, uint8_t expect_run, uint8_t saw_type, uint8_t 240:Src/main.c **** static uint8_t AD9102_CheckFlagsSram(uint16_t pat_status, uint8_t expect_run, uint16_t samples, uin 241:Src/main.c **** static void SPI2_SetMode(uint32_t polarity, uint32_t phase); 242:Src/main.c **** static void AD9833_WriteWord(uint16_t word); 243:Src/main.c **** static void AD9833_Apply(uint8_t enable, uint8_t triangle, uint32_t freq_word); 244:Src/main.c **** static void DS1809_Pulse(uint8_t uc, uint8_t dc, uint16_t count, uint16_t pulse_ms); 245:Src/main.c **** static void PA4_DAC_Init(void); 246:Src/main.c **** static void PA4_DAC_Set(uint16_t dac_code, uint8_t enable); 247:Src/main.c **** uint8_t CheckChecksum(uint16_t *pbuff); 248:Src/main.c **** uint16_t CalculateChecksum(uint16_t *pbuff, uint16_t len); 249:Src/main.c **** //int SD_Init(void); 250:Src/main.c **** int SD_SAVE(uint16_t *pbuff); 251:Src/main.c **** //uint32_t Get_Length(void); 252:Src/main.c **** int SD_READ(uint16_t *pbuff); 253:Src/main.c **** int SD_REMOVE(void); 254:Src/main.c **** void USART_TX (uint8_t* dt, uint16_t sz); 255:Src/main.c **** void USART_TX_DMA (uint16_t sz); 256:Src/main.c **** static void Stop_TIM10(); 257:Src/main.c **** static void OUT_trigger(uint8_t); 258:Src/main.c **** /* USER CODE END PFP */ 259:Src/main.c **** 260:Src/main.c **** /* Private user code ---------------------------------------------------------*/ 261:Src/main.c **** /* USER CODE BEGIN 0 */ 262:Src/main.c **** 263:Src/main.c **** /* USER CODE END 0 */ 264:Src/main.c **** 265:Src/main.c **** /** 266:Src/main.c **** * @brief The application entry point. 267:Src/main.c **** * @retval int 268:Src/main.c **** */ 269:Src/main.c **** int main(void) 270:Src/main.c **** { 271:Src/main.c **** 272:Src/main.c **** /* USER CODE BEGIN 1 */ 273:Src/main.c **** HAL_StatusTypeDef st; 274:Src/main.c **** /* USER CODE END 1 */ 275:Src/main.c **** ARM GAS /tmp/ccLSPxIe.s page 44 276:Src/main.c **** /* MCU Configuration--------------------------------------------------------*/ 277:Src/main.c **** 278:Src/main.c **** /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ 279:Src/main.c **** HAL_Init(); 280:Src/main.c **** 281:Src/main.c **** /* USER CODE BEGIN Init */ 282:Src/main.c **** /*I hope you don't forget that first - MX_DMA_Init(); and than - MX_USART1_UART_Init();*/ 283:Src/main.c **** /* USER CODE END Init */ 284:Src/main.c **** 285:Src/main.c **** /* Configure the system clock */ 286:Src/main.c **** SystemClock_Config(); 287:Src/main.c **** 288:Src/main.c **** /* USER CODE BEGIN SysInit */ 289:Src/main.c **** 290:Src/main.c **** /* USER CODE END SysInit */ 291:Src/main.c **** 292:Src/main.c **** /* Initialize all configured peripherals */ 293:Src/main.c **** MX_GPIO_Init(); 294:Src/main.c **** MX_DMA_Init(); 295:Src/main.c **** MX_SPI4_Init(); 296:Src/main.c **** MX_FATFS_Init(); 297:Src/main.c **** MX_TIM2_Init(); 298:Src/main.c **** MX_TIM5_Init(); 299:Src/main.c **** MX_ADC1_Init(); 300:Src/main.c **** MX_ADC3_Init(); 301:Src/main.c **** MX_SPI2_Init(); 302:Src/main.c **** MX_SPI5_Init(); 303:Src/main.c **** MX_SPI6_Init(); 304:Src/main.c **** MX_USART1_UART_Init(); 305:Src/main.c **** MX_SDMMC1_SD_Init(); 306:Src/main.c **** MX_TIM7_Init(); 307:Src/main.c **** MX_TIM6_Init(); 308:Src/main.c **** MX_TIM10_Init(); 309:Src/main.c **** MX_UART8_Init(); 310:Src/main.c **** MX_TIM8_Init(); 311:Src/main.c **** MX_TIM11_Init(); 312:Src/main.c **** MX_TIM4_Init(); 313:Src/main.c **** MX_TIM1_Init(); 314:Src/main.c **** PA4_DAC_Init(); 315:Src/main.c **** /* USER CODE BEGIN 2 */ 316:Src/main.c **** Init_params(); 317:Src/main.c **** //HAL_TIM_Base_Start(&htim11); 318:Src/main.c **** //HAL_TIM_PWM_Start(&htim11, TIM_CHANNEL_1); //start modulating by Mach-Zander modulator 319:Src/main.c **** 320:Src/main.c **** 321:Src/main.c **** //TIM4,11 clocks = 92 MHz 322:Src/main.c **** 323:Src/main.c **** //ADC clock 324:Src/main.c **** //TIM4 -> ARR = 60; // for 1.5 MHz 325:Src/main.c **** //TIM4 -> ARR = 91; // for 1 MHz 326:Src/main.c **** //TIM4 -> ARR = 45; // for 2 MHz 327:Src/main.c **** TIM4 -> ARR = 53; // for 1.735 MHz. It`s the highest frequency for correct ADC work. At higher fre 328:Src/main.c **** 329:Src/main.c **** TIM4 -> CCR3 = (TIM4 -> ARR +1)/2 - 1; 330:Src/main.c **** 331:Src/main.c **** 332:Src/main.c **** //Mach-Zander clock (should be 1/4 of ADC clock freq) ARM GAS /tmp/ccLSPxIe.s page 45 333:Src/main.c **** 334:Src/main.c **** TIM11 -> ARR = (TIM4 -> ARR +1)*4 - 1; 335:Src/main.c **** TIM11 -> CCR1 = (TIM11 -> ARR +1)/2 - 1; 336:Src/main.c **** 337:Src/main.c **** // AD9833 MCLK output on PE9 (TIM1_CH1) 338:Src/main.c **** // TIM1 clock = 184 MHz, ARR=8 -> ~20.44 MHz output 339:Src/main.c **** HAL_TIM_PWM_Start(&htim1, TIM_CHANNEL_1); 340:Src/main.c **** 341:Src/main.c **** /* 342:Src/main.c **** if (HAL_GPIO_ReadPin(INP_0_GPIO_Port, INP_0_Pin) == 0){ 343:Src/main.c **** 344:Src/main.c **** CPU_state = DECODE_ENABLE; 345:Src/main.c **** } 346:Src/main.c **** */ 347:Src/main.c **** /* USER CODE END 2 */ 348:Src/main.c **** 349:Src/main.c **** /* Infinite loop */ 350:Src/main.c **** /* USER CODE BEGIN WHILE */ 351:Src/main.c **** while (1) 352:Src/main.c **** { 353:Src/main.c **** if ((HAL_GPIO_ReadPin(USB_FLAG_GPIO_Port, USB_FLAG_Pin)==GPIO_PIN_SET)&&(u_rx_flg == 0)) 354:Src/main.c **** { 355:Src/main.c **** //NVIC_DisableIRQ(USART1_IRQn); 356:Src/main.c **** LL_USART_EnableIT_PE(USART1); 357:Src/main.c **** LL_USART_EnableIT_RXNE(USART1); 358:Src/main.c **** LL_USART_EnableIT_ERROR(USART1); 359:Src/main.c **** NVIC_SetPriority(USART1_IRQn, 0); 360:Src/main.c **** NVIC_EnableIRQ(USART1_IRQn);//In other case you have FE error flag... 361:Src/main.c **** u_rx_flg = 1; 362:Src/main.c **** } 363:Src/main.c **** // else 364:Src/main.c **** // { 365:Src/main.c **** // //NVIC_DisableIRQ(USART1_IRQn); 366:Src/main.c **** // u_rx_flg = 0; 367:Src/main.c **** // } 368:Src/main.c **** switch (CPU_state) 369:Src/main.c **** { 370:Src/main.c **** case HALT://0 - Default state 371:Src/main.c **** CPU_state_old = HALT;//Save main current cycle 372:Src/main.c **** task.current_param = task.min_param; 373:Src/main.c **** Stop_TIM10(); 374:Src/main.c **** break; 375:Src/main.c **** case DECODE_ENABLE://1 - Decode rec. message 376:Src/main.c **** CS_result = CalculateChecksum(COMMAND, CL_16-2); 377:Src/main.c **** if (CheckChecksum(COMMAND)) 378:Src/main.c **** { 379:Src/main.c **** LL_SPI_Enable(SPI2);//Enable SPI for Laser1 DAC & TEC1 380:Src/main.c **** LL_SPI_Enable(SPI6);//Enable SPI for Laser2 DAC & TEC2 381:Src/main.c **** Decode_uart(COMMAND, &LD1_curr_setup, &LD2_curr_setup, &Curr_setup); 382:Src/main.c **** TO6_before = TO6; 383:Src/main.c **** //LD1_param.LD_TEMP_Before = LD1_param.LD_TEMP; 384:Src/main.c **** //LD2_param.LD_TEMP_Before = LD2_param.LD_TEMP; 385:Src/main.c **** CPU_state = WORK_ENABLE; 386:Src/main.c **** CPU_state_old = WORK_ENABLE;//Save main current cycle 387:Src/main.c **** } 388:Src/main.c **** else 389:Src/main.c **** { ARM GAS /tmp/ccLSPxIe.s page 46 390:Src/main.c **** State_Data[0] |= UART_DECODE_ERR; 391:Src/main.c **** CPU_state = DEFAULT_ENABLE; 392:Src/main.c **** CPU_state_old = HALT;//Save main current cycle 393:Src/main.c **** } 394:Src/main.c **** UART_transmission_request = MESS_01; 395:Src/main.c **** break; 396:Src/main.c **** case DEFAULT_ENABLE://2 - Go to HALT 397:Src/main.c **** //Set current setup to default 398:Src/main.c **** task.current_param = task.min_param; 399:Src/main.c **** Stop_TIM10(); 400:Src/main.c **** Init_params(); 401:Src/main.c **** AD9102_CancelWaveUpload(); 402:Src/main.c **** LL_SPI_Disable(SPI2);//Disable SPI for Laser1 DAC & TEC1 403:Src/main.c **** LL_SPI_Disable(SPI6);//Disable SPI for Laser2 DAC & TEC2 404:Src/main.c **** CPU_state = HALT; 405:Src/main.c **** CPU_state_old = HALT;//Save main current cycle 406:Src/main.c **** UART_transmission_request = MESS_01; 407:Src/main.c **** break; 408:Src/main.c **** case TRANS_S_ENABLE://3 - Transmith saved packet Before this operation must to be defaulting! 409:Src/main.c **** temp16 = SD_READ(&Long_Data[0]); 410:Src/main.c **** State_Data[0]|=temp16&0xff; 411:Src/main.c **** if (temp16==0) 412:Src/main.c **** { 413:Src/main.c **** UART_transmission_request = MESS_03; 414:Src/main.c **** } 415:Src/main.c **** else 416:Src/main.c **** { 417:Src/main.c **** UART_transmission_request = MESS_01; 418:Src/main.c **** } 419:Src/main.c **** CPU_state_old = HALT; 420:Src/main.c **** CPU_state = CPU_state_old;//Return to main current cycle 421:Src/main.c **** break; 422:Src/main.c **** case TRANS_ENABLE://4 - Transmith current packet 423:Src/main.c **** UART_transmission_request = MESS_02; 424:Src/main.c **** CPU_state = CPU_state_old;//Return to main current cycle 425:Src/main.c **** break; 426:Src/main.c **** case REMOVE_FILE://5 - Remove file from SD 427:Src/main.c **** State_Data[0]|=SD_REMOVE()&0xff; 428:Src/main.c **** UART_transmission_request = MESS_01; 429:Src/main.c **** CPU_state = CPU_state_old; 430:Src/main.c **** break; 431:Src/main.c **** case STATE://6 - Transmith state message 432:Src/main.c **** UART_transmission_request = MESS_01; 433:Src/main.c **** CPU_state = CPU_state_old;//Return to main current cycle 434:Src/main.c **** break; 435:Src/main.c **** case WORK_ENABLE://7 - Main work cycle 436:Src/main.c **** task.current_param = task.min_param; 437:Src/main.c **** Stop_TIM10(); 438:Src/main.c **** if (TO7>TO7_before)//Main work cycle go with the timer 7 (1000 us or 1 kHz) 439:Src/main.c **** { 440:Src/main.c **** TO7_before = TO7; 441:Src/main.c **** LD1_param.POWER = MPhD_T(1);//Get Data from monitor photodiode of LD1 442:Src/main.c **** LD1_param.POWER = MPhD_T(1);//Get Data from monitor photodiode of LD1 443:Src/main.c **** LD2_param.POWER = MPhD_T(2);//Get Data from monitor photodiode of LD2 444:Src/main.c **** LD2_param.POWER = MPhD_T(2);//Get Data from monitor photodiode of LD2 445:Src/main.c **** 446:Src/main.c **** //Correct temperature in all pulses ARM GAS /tmp/ccLSPxIe.s page 47 447:Src/main.c **** (void) MPhD_T(3); 448:Src/main.c **** LD1_param.LD_CURR_TEMP = MPhD_T(3); 449:Src/main.c **** (void) MPhD_T(4); 450:Src/main.c **** LD2_param.LD_CURR_TEMP = MPhD_T(4); 451:Src/main.c **** temp16=PID_Controller_Temp(&LD1_curr_setup, &LD1_param, 1); 452:Src/main.c **** Set_LTEC(3, temp16);//Drive Laser TEC 1 453:Src/main.c **** temp16=PID_Controller_Temp(&LD2_curr_setup, &LD2_param, 2); 454:Src/main.c **** Set_LTEC(4, temp16);//Drive Laser TEC 2 455:Src/main.c **** 456:Src/main.c **** Long_Data[1] = LD1_param.POWER;//Translate Data from monitor photodiode of LD1 to Long_Data 457:Src/main.c **** Long_Data[2] = LD2_param.POWER;//Translate Data from monitor photodiode of LD2 to Long_Data 458:Src/main.c **** 459:Src/main.c **** Set_LTEC(1,LD1_curr_setup.CURRENT);//Drive Laser diode 1 460:Src/main.c **** Set_LTEC(2,LD2_curr_setup.CURRENT);//Drive Laser diode 2 461:Src/main.c **** 462:Src/main.c **** //Prepare DATA of internals ADCs 463:Src/main.c **** //Put the temperature of LD2 to Long_Data: 464:Src/main.c **** temp16 = Get_ADC(0); 465:Src/main.c **** temp16 = Get_ADC(1); 466:Src/main.c **** Long_Data[7] = temp16; // PA2 -- 3V_monitor // PB1 -- U_Rt1_ext_Gain 467:Src/main.c **** 468:Src/main.c **** //Put the temperature of LD2 to Long_Data: 469:Src/main.c **** temp16 = Get_ADC(1); 470:Src/main.c **** Long_Data[8] = temp16; // PB0 -- U_Rt2_ext_Gain // PB0 -- U_Rt2_ext_Gain 471:Src/main.c **** 472:Src/main.c **** //Put the temperature of LD2 to Long_Data: 473:Src/main.c **** temp16 = Get_ADC(1); 474:Src/main.c **** Long_Data[9] = temp16; // PB1 -- U_Rt1_ext_Gain // PA2 -- 3V_monitor 475:Src/main.c **** 476:Src/main.c **** //Put the temperature of LD2 to Long_Data: 477:Src/main.c **** temp16 = Get_ADC(1); 478:Src/main.c **** Long_Data[10] = temp16; // PC0 -- 5V1_monitor // PC0 -- 5V1_monitor 479:Src/main.c **** 480:Src/main.c **** //Put the temperature of LD2 to Long_Data: 481:Src/main.c **** temp16 = Get_ADC(1); 482:Src/main.c **** Long_Data[11] = temp16; // PC1 -- 5V2_monitor // PC1 -- 5V2_monitor 483:Src/main.c **** temp16 = Get_ADC(2); 484:Src/main.c **** 485:Src/main.c **** //Put the temperature of LD2 to Long_Data: 486:Src/main.c **** temp16 = Get_ADC(3); 487:Src/main.c **** temp16 = Get_ADC(4); 488:Src/main.c **** Long_Data[12] = temp16; 489:Src/main.c **** temp16 = Get_ADC(5); 490:Src/main.c **** 491:Src/main.c **** //Put the timer tick to Long_Data: 492:Src/main.c **** TO6_stop = TO6; 493:Src/main.c **** Long_Data[3] = (TO6_stop)&0xffff; 494:Src/main.c **** Long_Data[4] = (TO6_stop>>16)&0xffff; 495:Src/main.c **** 496:Src/main.c **** //Put the average temperature of LD1 to Long_Data: 497:Src/main.c **** Long_Data[5] = LD1_param.LD_CURR_TEMP; 498:Src/main.c **** 499:Src/main.c **** //Put the average temperature of LD2 to Long_Data: 500:Src/main.c **** Long_Data[6] = LD2_param.LD_CURR_TEMP; 501:Src/main.c **** 502:Src/main.c **** if (Curr_setup.SD_EN==1) 503:Src/main.c **** { ARM GAS /tmp/ccLSPxIe.s page 48 504:Src/main.c **** CS_result = CalculateChecksum(&Long_Data[1], DL_16-2); 505:Src/main.c **** Long_Data[DL_16-1] = CS_result; 506:Src/main.c **** temp16 = SD_SAVE(&Long_Data[0]); 507:Src/main.c **** State_Data[0]|=temp16&0xff; 508:Src/main.c **** } 509:Src/main.c **** CPU_state_old = WORK_ENABLE;//Save main current cycle 510:Src/main.c **** } 511:Src/main.c **** break; 512:Src/main.c **** case AD9102_CMD://10 - Configure AD9102 sawtooth output 513:Src/main.c **** if (CalculateChecksum(COMMAND, AD9102_CMD_WORDS - 1) == COMMAND[AD9102_CMD_WORDS - 1]) 514:Src/main.c **** { 515:Src/main.c **** uint16_t flags = COMMAND[0]; 516:Src/main.c **** uint16_t param0 = COMMAND[1]; 517:Src/main.c **** uint16_t param1 = COMMAND[2]; 518:Src/main.c **** uint8_t enable = (flags & AD9102_FLAG_ENABLE) ? 1u : 0u; 519:Src/main.c **** uint8_t triangle = (flags & AD9102_FLAG_TRIANGLE) ? 1u : 0u; 520:Src/main.c **** uint8_t sram_mode = (flags & AD9102_FLAG_SRAM) ? 1u : 0u; 521:Src/main.c **** 522:Src/main.c **** if (sram_mode) 523:Src/main.c **** { 524:Src/main.c **** uint8_t sram_fmt = (flags & AD9102_FLAG_SRAM_FMT) ? 1u : 0u; 525:Src/main.c **** uint16_t samples; 526:Src/main.c **** uint8_t hold; 527:Src/main.c **** uint16_t amplitude; 528:Src/main.c **** 529:Src/main.c **** if (sram_fmt) 530:Src/main.c **** { 531:Src/main.c **** amplitude = param0; 532:Src/main.c **** samples = param1; 533:Src/main.c **** hold = AD9102_SRAM_HOLD_DEFAULT; 534:Src/main.c **** } 535:Src/main.c **** else 536:Src/main.c **** { 537:Src/main.c **** samples = param0; 538:Src/main.c **** hold = (uint8_t)(param1 & 0x0Fu); 539:Src/main.c **** amplitude = AD9102_SRAM_AMP_DEFAULT; 540:Src/main.c **** } 541:Src/main.c **** 542:Src/main.c **** uint16_t pat_status = AD9102_ApplySram(enable, samples, hold, triangle, amplitude); 543:Src/main.c **** State_Data[1] = (uint8_t)(pat_status & 0x00FFu); 544:Src/main.c **** if (AD9102_CheckFlagsSram(pat_status, enable, samples, hold)) 545:Src/main.c **** { 546:Src/main.c **** State_Data[0] |= AD9102_ERR; 547:Src/main.c **** } 548:Src/main.c **** } 549:Src/main.c **** else 550:Src/main.c **** { 551:Src/main.c **** uint8_t saw_type = triangle ? AD9102_SAW_TYPE_TRI : AD9102_SAW_TYPE_UP; 552:Src/main.c **** uint8_t saw_step = (uint8_t)(param0 & 0x00FFu); 553:Src/main.c **** uint8_t pat_base = (uint8_t)((param0 >> 8) & 0x0Fu); 554:Src/main.c **** uint16_t pat_period = param1; 555:Src/main.c **** 556:Src/main.c **** if (param0 == 0u && param1 == 0u) 557:Src/main.c **** { 558:Src/main.c **** saw_step = AD9102_SAW_STEP_DEFAULT; 559:Src/main.c **** pat_base = AD9102_PAT_PERIOD_BASE_DEFAULT; 560:Src/main.c **** pat_period = AD9102_PAT_PERIOD_DEFAULT; ARM GAS /tmp/ccLSPxIe.s page 49 561:Src/main.c **** } 562:Src/main.c **** else 563:Src/main.c **** { 564:Src/main.c **** if (saw_step == 0u) 565:Src/main.c **** { 566:Src/main.c **** saw_step = AD9102_SAW_STEP_DEFAULT; 567:Src/main.c **** } 568:Src/main.c **** else if (saw_step > 63u) 569:Src/main.c **** { 570:Src/main.c **** saw_step = 63u; 571:Src/main.c **** } 572:Src/main.c **** if (pat_period == 0u) 573:Src/main.c **** { 574:Src/main.c **** pat_period = AD9102_PAT_PERIOD_DEFAULT; 575:Src/main.c **** } 576:Src/main.c **** } 577:Src/main.c **** 578:Src/main.c **** uint16_t pat_status = AD9102_Apply(saw_type, enable, saw_step, pat_base, pat_period); 579:Src/main.c **** State_Data[1] = (uint8_t)(pat_status & 0x00FFu); 580:Src/main.c **** if (AD9102_CheckFlags(pat_status, enable, saw_type, saw_step, pat_base, pat_period)) 581:Src/main.c **** { 582:Src/main.c **** State_Data[0] |= AD9102_ERR; 583:Src/main.c **** } 584:Src/main.c **** } 585:Src/main.c **** } 586:Src/main.c **** else 587:Src/main.c **** { 588:Src/main.c **** State_Data[0] |= UART_DECODE_ERR; 589:Src/main.c **** } 590:Src/main.c **** UART_transmission_request = MESS_01; 591:Src/main.c **** CPU_state = CPU_state_old; 592:Src/main.c **** break; 593:Src/main.c **** case AD9833_CMD://11 - Configure AD9833 triangle output 594:Src/main.c **** State_Data[1] = 0u; 595:Src/main.c **** if (CalculateChecksum(COMMAND, AD9833_CMD_WORDS - 1) == COMMAND[AD9833_CMD_WORDS - 1]) 596:Src/main.c **** { 597:Src/main.c **** uint16_t flags = COMMAND[0]; 598:Src/main.c **** uint16_t lsw = (uint16_t)(COMMAND[1] & 0x3FFFu); 599:Src/main.c **** uint16_t msw = (uint16_t)(COMMAND[2] & 0x3FFFu); 600:Src/main.c **** uint8_t enable = (flags & AD9833_FLAG_ENABLE) ? 1u : 0u; 601:Src/main.c **** uint8_t triangle = (flags & AD9833_FLAG_TRIANGLE) ? 1u : 0u; 602:Src/main.c **** uint32_t freq_word = ((uint32_t)msw << 14) | (uint32_t)lsw; 603:Src/main.c **** 604:Src/main.c **** AD9833_Apply(enable, triangle, freq_word); 605:Src/main.c **** } 606:Src/main.c **** else 607:Src/main.c **** { 608:Src/main.c **** State_Data[0] |= UART_DECODE_ERR; 609:Src/main.c **** } 610:Src/main.c **** UART_transmission_request = MESS_01; 611:Src/main.c **** CPU_state = CPU_state_old; 612:Src/main.c **** break; 613:Src/main.c **** case DS1809_CMD://12 - Pulse DS1809 UC/DC controls 614:Src/main.c **** if (CalculateChecksum(COMMAND, DS1809_CMD_WORDS - 1) == COMMAND[DS1809_CMD_WORDS - 1]) 615:Src/main.c **** { 616:Src/main.c **** uint16_t flags = COMMAND[0]; 617:Src/main.c **** uint16_t count = COMMAND[1]; ARM GAS /tmp/ccLSPxIe.s page 50 618:Src/main.c **** uint16_t pulse_ms = COMMAND[2]; 619:Src/main.c **** uint8_t uc = (flags & DS1809_FLAG_UC) ? 1u : 0u; 620:Src/main.c **** uint8_t dc = (flags & DS1809_FLAG_DC) ? 1u : 0u; 621:Src/main.c **** 622:Src/main.c **** if (uc && dc) 623:Src/main.c **** { 624:Src/main.c **** State_Data[0] |= UART_DECODE_ERR; 625:Src/main.c **** } 626:Src/main.c **** else 627:Src/main.c **** { 628:Src/main.c **** if (count == 0u) 629:Src/main.c **** { 630:Src/main.c **** count = 1u; 631:Src/main.c **** } 632:Src/main.c **** if (count > 64u) 633:Src/main.c **** { 634:Src/main.c **** count = 64u; 635:Src/main.c **** } 636:Src/main.c **** if (pulse_ms == 0u) 637:Src/main.c **** { 638:Src/main.c **** pulse_ms = DS1809_PULSE_MS_DEFAULT; 639:Src/main.c **** } 640:Src/main.c **** if (pulse_ms > 500u) 641:Src/main.c **** { 642:Src/main.c **** pulse_ms = 500u; 643:Src/main.c **** } 644:Src/main.c **** DS1809_Pulse(uc, dc, count, pulse_ms); 645:Src/main.c **** } 646:Src/main.c **** } 647:Src/main.c **** else 648:Src/main.c **** { 649:Src/main.c **** State_Data[0] |= UART_DECODE_ERR; 650:Src/main.c **** } 651:Src/main.c **** UART_transmission_request = MESS_01; 652:Src/main.c **** CPU_state = CPU_state_old; 653:Src/main.c **** break; 654:Src/main.c **** case STM32_DAC_CMD://13 - Set STM32 internal DAC (PA4) 655:Src/main.c **** if (CalculateChecksum(COMMAND, STM32_DAC_CMD_WORDS - 1) == COMMAND[STM32_DAC_CMD_WORDS - 1]) 656:Src/main.c **** { 657:Src/main.c **** uint16_t flags = COMMAND[0]; 658:Src/main.c **** uint16_t dac_code = (uint16_t)(COMMAND[1] & 0x0FFFu); 659:Src/main.c **** uint8_t enable = (flags & STM32_DAC_FLAG_ENABLE) ? 1u : 0u; 660:Src/main.c **** PA4_DAC_Set(dac_code, enable); 661:Src/main.c **** } 662:Src/main.c **** else 663:Src/main.c **** { 664:Src/main.c **** State_Data[0] |= UART_DECODE_ERR; 665:Src/main.c **** } 666:Src/main.c **** UART_transmission_request = MESS_01; 667:Src/main.c **** CPU_state = CPU_state_old; 668:Src/main.c **** break; 669:Src/main.c **** case AD9102_WAVE_CTRL_CMD://14 - Control custom AD9102 SRAM upload 670:Src/main.c **** State_Data[1] = 0u; 671:Src/main.c **** if (CalculateChecksum(COMMAND, AD9102_WAVE_CTRL_WORDS - 1) == COMMAND[AD9102_WAVE_CTRL_WORDS - 672:Src/main.c **** { 673:Src/main.c **** uint16_t opcode = COMMAND[0]; 674:Src/main.c **** uint16_t param0 = COMMAND[1]; ARM GAS /tmp/ccLSPxIe.s page 51 675:Src/main.c **** uint16_t param1 = COMMAND[2]; 676:Src/main.c **** 677:Src/main.c **** switch (opcode) 678:Src/main.c **** { 679:Src/main.c **** case AD9102_WAVE_OPCODE_BEGIN: 680:Src/main.c **** if ((param1 != 0u) || !AD9102_BeginWaveUpload(param0)) 681:Src/main.c **** { 682:Src/main.c **** AD9102_CancelWaveUpload(); 683:Src/main.c **** State_Data[0] |= AD9102_ERR; 684:Src/main.c **** } 685:Src/main.c **** break; 686:Src/main.c **** case AD9102_WAVE_OPCODE_COMMIT: 687:Src/main.c **** { 688:Src/main.c **** uint16_t samples = ad9102_wave_expected_samples; 689:Src/main.c **** uint8_t ok = 0u; 690:Src/main.c **** uint16_t pat_status; 691:Src/main.c **** 692:Src/main.c **** if ((param0 != 0u) || (param1 != 0u)) 693:Src/main.c **** { 694:Src/main.c **** AD9102_CancelWaveUpload(); 695:Src/main.c **** State_Data[0] |= AD9102_ERR; 696:Src/main.c **** break; 697:Src/main.c **** } 698:Src/main.c **** 699:Src/main.c **** pat_status = AD9102_CommitWaveUpload(&ok); 700:Src/main.c **** State_Data[1] = (uint8_t)(pat_status & 0x00FFu); 701:Src/main.c **** if ((!ok) || AD9102_CheckFlagsSram(pat_status, 1u, samples, AD9102_SRAM_HOLD_DEFAULT)) 702:Src/main.c **** { 703:Src/main.c **** State_Data[0] |= AD9102_ERR; 704:Src/main.c **** } 705:Src/main.c **** } 706:Src/main.c **** break; 707:Src/main.c **** case AD9102_WAVE_OPCODE_CANCEL: 708:Src/main.c **** if ((param0 != 0u) || (param1 != 0u)) 709:Src/main.c **** { 710:Src/main.c **** State_Data[0] |= AD9102_ERR; 711:Src/main.c **** } 712:Src/main.c **** AD9102_CancelWaveUpload(); 713:Src/main.c **** break; 714:Src/main.c **** default: 715:Src/main.c **** AD9102_CancelWaveUpload(); 716:Src/main.c **** State_Data[0] |= AD9102_ERR; 717:Src/main.c **** break; 718:Src/main.c **** } 719:Src/main.c **** } 720:Src/main.c **** else 721:Src/main.c **** { 722:Src/main.c **** State_Data[0] |= UART_DECODE_ERR; 723:Src/main.c **** } 724:Src/main.c **** UART_transmission_request = MESS_01; 725:Src/main.c **** CPU_state = CPU_state_old; 726:Src/main.c **** break; 727:Src/main.c **** case AD9102_WAVE_DATA_CMD://15 - Write custom AD9102 SRAM samples 728:Src/main.c **** State_Data[1] = 0u; 729:Src/main.c **** if (CalculateChecksum(COMMAND, AD9102_WAVE_DATA_WORDS - 1) == COMMAND[AD9102_WAVE_DATA_WORDS - 730:Src/main.c **** { 731:Src/main.c **** uint16_t chunk_count = COMMAND[0]; ARM GAS /tmp/ccLSPxIe.s page 52 732:Src/main.c **** if (!AD9102_WriteWaveUploadChunk(&COMMAND[1], chunk_count)) 733:Src/main.c **** { 734:Src/main.c **** AD9102_CancelWaveUpload(); 735:Src/main.c **** State_Data[0] |= AD9102_ERR; 736:Src/main.c **** } 737:Src/main.c **** } 738:Src/main.c **** else 739:Src/main.c **** { 740:Src/main.c **** AD9102_CancelWaveUpload(); 741:Src/main.c **** State_Data[0] |= UART_DECODE_ERR; 742:Src/main.c **** } 743:Src/main.c **** UART_transmission_request = MESS_01; 744:Src/main.c **** CPU_state = CPU_state_old; 745:Src/main.c **** break; 746:Src/main.c **** case DECODE_TASK: 747:Src/main.c **** if (CheckChecksum(COMMAND)) 748:Src/main.c **** { 749:Src/main.c **** Decode_task(COMMAND, &LD1_curr_setup, &LD2_curr_setup, &Curr_setup); 750:Src/main.c **** TO6_before = TO6; 751:Src/main.c **** CPU_state = RUN_TASK; 752:Src/main.c **** CPU_state_old = RUN_TASK;//Save main current cycle 753:Src/main.c **** } 754:Src/main.c **** else 755:Src/main.c **** { 756:Src/main.c **** State_Data[0] |= UART_DECODE_ERR; 757:Src/main.c **** CPU_state = DEFAULT_ENABLE; 758:Src/main.c **** CPU_state_old = HALT;//Save main current cycle 759:Src/main.c **** } 760:Src/main.c **** UART_transmission_request = MESS_01; 761:Src/main.c **** break; 762:Src/main.c **** case RUN_TASK: 763:Src/main.c **** switch (task.task_type) 764:Src/main.c **** { 765:Src/main.c **** case TT_CHANGE_CURR_1: 766:Src/main.c **** 767:Src/main.c **** 768:Src/main.c **** //calculating timer periods for ADC clock and Mach-Zander modulator 769:Src/main.c **** //ADC clock 770:Src/main.c **** //TIM4 -> ARR = 60; // for 1.5 MHz 771:Src/main.c **** //TIM4 -> ARR = 91; // for 1 MHz 772:Src/main.c **** //TIM4 -> ARR = 45; // for 2 MHz 773:Src/main.c **** 774:Src/main.c **** //online calculation for debug purposes: 775:Src/main.c **** //manually varying TIM4 -> ARR by debugger while running 776:Src/main.c **** //TIM4 -> CCR3 = (TIM4 -> ARR +1)/2 - 1; 777:Src/main.c **** 778:Src/main.c **** 779:Src/main.c **** //Mach-Zander clock (should be half of ADC clock freq) 780:Src/main.c **** //TIM11 -> ARR = (TIM4 -> ARR +1)*2 - 1; 781:Src/main.c **** //TIM11 -> CCR1 = (TIM11 -> ARR +1)/2 - 1; 782:Src/main.c **** 783:Src/main.c **** 784:Src/main.c **** 785:Src/main.c **** Set_LTEC(TT_CHANGE_CURR_2, task.curr); 786:Src/main.c **** (void) MPhD_T(TT_CHANGE_TEMP_1); 787:Src/main.c **** LD1_param.LD_CURR_TEMP = MPhD_T(TT_CHANGE_TEMP_1); 788:Src/main.c **** (void) MPhD_T(TT_CHANGE_TEMP_2); ARM GAS /tmp/ccLSPxIe.s page 53 789:Src/main.c **** LD2_param.LD_CURR_TEMP = MPhD_T(TT_CHANGE_TEMP_2); 790:Src/main.c **** temp16=PID_Controller_Temp(&LD1_curr_setup, &LD1_param, 1); 791:Src/main.c **** Set_LTEC(TT_CHANGE_TEMP_1, temp16);//Drive Laser TEC 1 792:Src/main.c **** temp16=PID_Controller_Temp(&LD2_curr_setup, &LD2_param, 2); 793:Src/main.c **** Set_LTEC(TT_CHANGE_TEMP_2, temp16);//Drive Laser TEC 2 794:Src/main.c **** 795:Src/main.c **** // Toggle pin for oscilloscope 796:Src/main.c **** HAL_GPIO_WritePin(GPIOD, GPIO_PIN_7, GPIO_PIN_SET); //start of the whole frequency sweep proc 797:Src/main.c **** HAL_GPIO_WritePin(GPIOD, GPIO_PIN_7, GPIO_PIN_RESET); 798:Src/main.c **** 799:Src/main.c **** st = HAL_TIM_Base_Start_IT(&htim10); 800:Src/main.c **** if (st != HAL_OK) 801:Src/main.c **** while(1); 802:Src/main.c **** 803:Src/main.c **** uint16_t step_counter = 0; 804:Src/main.c **** uint16_t trigger_counter = 0; 805:Src/main.c **** uint16_t trigger_step = (uint8_t )((task.max_param - task.current_param)/task.delta_param * 1 806:Src/main.c **** uint16_t task_sheduler = 0; 807:Src/main.c **** 808:Src/main.c **** 809:Src/main.c **** 810:Src/main.c **** HAL_TIM_PWM_Stop(&htim11, TIM_CHANNEL_1); //start modulating by Mach-Zander modulator 811:Src/main.c **** HAL_TIM_PWM_Stop(&htim4, TIM_CHANNEL_3); //start ADC clock 812:Src/main.c **** TIM11 -> CR1 &= ~(1 << 3); //disables one-pulse mode 813:Src/main.c **** TIM4 -> CR1 &= ~(1 << 3); //disables one-pulse mode 814:Src/main.c **** 815:Src/main.c **** 816:Src/main.c **** 817:Src/main.c **** TIM11 -> CNT = 0; 818:Src/main.c **** TIM4 -> CNT = 0; 819:Src/main.c **** 820:Src/main.c **** HAL_TIM_PWM_Start(&htim11, TIM_CHANNEL_1); //start modulating by Mach-Zander modulator 821:Src/main.c **** HAL_TIM_PWM_Start(&htim4, TIM_CHANNEL_3); //start ADC clock 822:Src/main.c **** //TIM4 -> CNT = 0; 823:Src/main.c **** 824:Src/main.c **** TIM4 -> CNT = TIM4 -> ARR - 20; // not zero to make phase shift that will be robust to big de 825:Src/main.c **** TIM11 -> CNT = 0; 826:Src/main.c **** 827:Src/main.c **** 828:Src/main.c **** while (task.current_param < task.max_param) 829:Src/main.c **** { 830:Src/main.c **** if (TIM10_coflag) 831:Src/main.c **** { 832:Src/main.c **** Set_LTEC(TT_CHANGE_CURR_1, task.current_param); 833:Src/main.c **** //TIM11 -> CNT = 0; // to link modulator phase 834:Src/main.c **** //TIM4 -> CNT = 0; // to link ADC clock phase 835:Src/main.c **** task.current_param += task.delta_param; 836:Src/main.c **** TO10 = 0; 837:Src/main.c **** TIM10_coflag = 0; 838:Src/main.c **** 839:Src/main.c **** HAL_GPIO_WritePin(GPIOG, GPIO_PIN_9, GPIO_PIN_SET); // set the current step laser current t 840:Src/main.c **** HAL_GPIO_WritePin(GPIOG, GPIO_PIN_9, GPIO_PIN_RESET); 841:Src/main.c **** //* 842:Src/main.c **** if (step_counter % trigger_step == 0){ //trigger at every 60 step 843:Src/main.c **** OUT_trigger(trigger_counter); 844:Src/main.c **** ++trigger_counter; 845:Src/main.c **** } ARM GAS /tmp/ccLSPxIe.s page 54 846:Src/main.c **** ++step_counter; 847:Src/main.c **** //*/ 848:Src/main.c **** /* 849:Src/main.c **** ++task_sheduler; 850:Src/main.c **** if (task_sheduler >= 10){ 851:Src/main.c **** task_sheduler = 0; 852:Src/main.c **** } 853:Src/main.c **** //maintain stable temperature of laser 2 854:Src/main.c **** if (task_sheduler == 0){ 855:Src/main.c **** (void) MPhD_T(TT_CHANGE_TEMP_2); 856:Src/main.c **** LD2_param.LD_CURR_TEMP = MPhD_T(TT_CHANGE_TEMP_2); 857:Src/main.c **** temp16=PID_Controller_Temp(&LD2_curr_setup, &LD2_param, 2); 858:Src/main.c **** Set_LTEC(TT_CHANGE_TEMP_2, temp16);//Drive Laser TEC 2 859:Src/main.c **** } 860:Src/main.c **** //maintain stable temperature of laser 1 861:Src/main.c **** //* 862:Src/main.c **** if (task_sheduler == 5){ 863:Src/main.c **** (void) MPhD_T(TT_CHANGE_TEMP_1); 864:Src/main.c **** LD1_param.LD_CURR_TEMP = MPhD_T(TT_CHANGE_TEMP_1); 865:Src/main.c **** temp16=PID_Controller_Temp(&LD1_curr_setup, &LD1_param, 1); 866:Src/main.c **** Set_LTEC(TT_CHANGE_TEMP_1, temp16);//Drive Laser TEC 1 867:Src/main.c **** } 868:Src/main.c **** //*/ 869:Src/main.c **** } 870:Src/main.c **** } 871:Src/main.c **** TIM11 -> DIER |= 1; //enable update interrupt. In this IRQ handler we will set both tims to o 872:Src/main.c **** //TIM11 -> CR1 |= 1 << 3; //sets timer to one-pulse mode. So it will turn off at the next Upd 873:Src/main.c **** //TIM4 -> CR1 |= 1 << 3; //sets timer to one-pulse mode. So it will turn off at the next Upda 874:Src/main.c **** //but one-pulse mode should be disabled 875:Src/main.c **** 876:Src/main.c **** //HAL_TIM_PWM_Stop(&htim11, TIM_CHANNEL_1); //start modulating by Mach-Zander modulator 877:Src/main.c **** //HAL_TIM_PWM_Stop(&htim4, TIM_CHANNEL_3); //start ADC clock 878:Src/main.c **** 879:Src/main.c **** 880:Src/main.c **** 881:Src/main.c **** Stop_TIM10(); 882:Src/main.c **** 883:Src/main.c **** task.current_param = task.min_param; 884:Src/main.c **** Set_LTEC(TT_CHANGE_CURR_1, task.current_param); 885:Src/main.c **** if (task.tau > 3) 886:Src/main.c **** { 887:Src/main.c **** TIM10_period = htim10.Init.Period; 888:Src/main.c **** htim10.Init.Period = 9999; 889:Src/main.c **** TO10_counter = (task.tau - 1) * 100; 890:Src/main.c **** } 891:Src/main.c **** HAL_TIM_Base_Start_IT(&htim10); 892:Src/main.c **** break; 893:Src/main.c **** case TT_CHANGE_CURR_2: 894:Src/main.c **** //Blink laser 2 895:Src/main.c **** //* 896:Src/main.c **** Set_LTEC(TT_CHANGE_CURR_1, task.curr); 897:Src/main.c **** (void) MPhD_T(TT_CHANGE_TEMP_1); 898:Src/main.c **** LD1_param.LD_CURR_TEMP = MPhD_T(TT_CHANGE_TEMP_1); 899:Src/main.c **** (void) MPhD_T(TT_CHANGE_TEMP_2); 900:Src/main.c **** LD2_param.LD_CURR_TEMP = MPhD_T(TT_CHANGE_TEMP_2); 901:Src/main.c **** temp16=PID_Controller_Temp(&LD1_curr_setup, &LD1_param, 1); 902:Src/main.c **** Set_LTEC(TT_CHANGE_TEMP_1, temp16);//Drive Laser TEC 1 ARM GAS /tmp/ccLSPxIe.s page 55 903:Src/main.c **** temp16=PID_Controller_Temp(&LD2_curr_setup, &LD2_param, 2); 904:Src/main.c **** Set_LTEC(TT_CHANGE_TEMP_2, temp16);//Drive Laser TEC 2 905:Src/main.c **** 906:Src/main.c **** LD_blinker.task_type = 2; 907:Src/main.c **** LD_blinker.state = 0; // 0 -- disabled (do nothing); 1 -- update LD current; 2 -- blinking, L 908:Src/main.c **** //LD_blinker.param = task.current_param; 909:Src/main.c **** LD_blinker.param = 0; 910:Src/main.c **** LD_blinker.param = 1000; // LD2 current (in unspecified units) 911:Src/main.c **** LD_blinker.signal_port = OUT_9_GPIO_Port; 912:Src/main.c **** LD_blinker.signal_pin = OUT_9_Pin; 913:Src/main.c **** 914:Src/main.c **** TIM8->ARR = 10000; //zero to LD_blinker.param change frequency (also in unspecified units). 915:Src/main.c **** //When it is too low -- Desktop app crashes (there is not so much compute sources on MCU 916:Src/main.c **** st = HAL_TIM_Base_Start_IT(&htim8); 917:Src/main.c **** if (st != HAL_OK) 918:Src/main.c **** while(1); 919:Src/main.c **** // */ 920:Src/main.c **** 921:Src/main.c **** // Toggle pin for oscilloscope 922:Src/main.c **** HAL_GPIO_WritePin(GPIOD, GPIO_PIN_7, GPIO_PIN_SET); 923:Src/main.c **** uint32_t i = 10000; while (--i){} 924:Src/main.c **** HAL_GPIO_WritePin(GPIOD, GPIO_PIN_7, GPIO_PIN_RESET); 925:Src/main.c **** LD_blinker.state = 2; 926:Src/main.c **** 927:Src/main.c **** st = HAL_TIM_Base_Start_IT(&htim10); 928:Src/main.c **** if (st != HAL_OK) 929:Src/main.c **** while(1); 930:Src/main.c **** while (task.current_param < task.max_param) 931:Src/main.c **** { 932:Src/main.c **** if (TIM10_coflag) 933:Src/main.c **** { 934:Src/main.c **** //Set_LTEC(TT_CHANGE_CURR_2, task.current_param); 935:Src/main.c **** //LD_blinker.param = task.current_param; 936:Src/main.c **** //++LD_blinker.param; 937:Src/main.c **** task.current_param += task.delta_param; 938:Src/main.c **** TO10 = 0; 939:Src/main.c **** TIM10_coflag = 0; 940:Src/main.c **** 941:Src/main.c **** 942:Src/main.c **** } 943:Src/main.c **** } 944:Src/main.c **** HAL_TIM_Base_Stop(&htim10); 945:Src/main.c **** HAL_GPIO_WritePin(GPIOD, GPIO_PIN_7, GPIO_PIN_SET); 946:Src/main.c **** 947:Src/main.c **** HAL_GPIO_WritePin(GPIOD, GPIO_PIN_7, GPIO_PIN_RESET); 948:Src/main.c **** 949:Src/main.c **** HAL_TIM_Base_Stop_IT(&htim8); 950:Src/main.c **** TIM8->CNT = 0; 951:Src/main.c **** 952:Src/main.c **** Stop_TIM10(); 953:Src/main.c **** task.current_param = task.min_param; 954:Src/main.c **** Set_LTEC(TT_CHANGE_CURR_2, task.current_param); 955:Src/main.c **** if (task.tau > 3) 956:Src/main.c **** { 957:Src/main.c **** TIM10_period = htim10.Init.Period; 958:Src/main.c **** htim10.Init.Period = 9999; 959:Src/main.c **** TO10_counter = (task.tau - 1) * 100; ARM GAS /tmp/ccLSPxIe.s page 56 960:Src/main.c **** } 961:Src/main.c **** HAL_TIM_Base_Start_IT(&htim10); 962:Src/main.c **** 963:Src/main.c **** 964:Src/main.c **** //*/ 965:Src/main.c **** 966:Src/main.c **** /* // Backup 967:Src/main.c **** Set_LTEC(TT_CHANGE_CURR_1, task.curr); 968:Src/main.c **** (void) MPhD_T(TT_CHANGE_TEMP_1); 969:Src/main.c **** LD1_param.LD_CURR_TEMP = MPhD_T(TT_CHANGE_TEMP_1); 970:Src/main.c **** (void) MPhD_T(TT_CHANGE_TEMP_2); 971:Src/main.c **** LD2_param.LD_CURR_TEMP = MPhD_T(TT_CHANGE_TEMP_2); 972:Src/main.c **** temp16=PID_Controller_Temp(&LD1_curr_setup, &LD1_param, 1); 973:Src/main.c **** Set_LTEC(TT_CHANGE_TEMP_1, temp16);//Drive Laser TEC 1 974:Src/main.c **** temp16=PID_Controller_Temp(&LD2_curr_setup, &LD2_param, 2); 975:Src/main.c **** Set_LTEC(TT_CHANGE_TEMP_2, temp16);//Drive Laser TEC 2 976:Src/main.c **** 977:Src/main.c **** // Toggle pin for oscilloscope 978:Src/main.c **** HAL_GPIO_WritePin(GPIOD, GPIO_PIN_7, GPIO_PIN_SET); 979:Src/main.c **** HAL_GPIO_WritePin(GPIOD, GPIO_PIN_7, GPIO_PIN_RESET); 980:Src/main.c **** 981:Src/main.c **** st = HAL_TIM_Base_Start_IT(&htim10); 982:Src/main.c **** if (st != HAL_OK) 983:Src/main.c **** while(1); 984:Src/main.c **** while (task.current_param < task.max_param) 985:Src/main.c **** { 986:Src/main.c **** if (TIM10_coflag) 987:Src/main.c **** { 988:Src/main.c **** Set_LTEC(TT_CHANGE_CURR_2, task.current_param); 989:Src/main.c **** task.current_param += task.delta_param; 990:Src/main.c **** TO10 = 0; 991:Src/main.c **** TIM10_coflag = 0; 992:Src/main.c **** 993:Src/main.c **** 994:Src/main.c **** } 995:Src/main.c **** } 996:Src/main.c **** Stop_TIM10(); 997:Src/main.c **** task.current_param = task.min_param; 998:Src/main.c **** Set_LTEC(TT_CHANGE_CURR_2, task.current_param); 999:Src/main.c **** if (task.tau > 3) 1000:Src/main.c **** { 1001:Src/main.c **** TIM10_period = htim10.Init.Period; 1002:Src/main.c **** htim10.Init.Period = 9999; 1003:Src/main.c **** TO10_counter = (task.tau - 1) * 100; 1004:Src/main.c **** } 1005:Src/main.c **** HAL_TIM_Base_Start_IT(&htim10); 1006:Src/main.c **** */ 1007:Src/main.c **** 1008:Src/main.c **** 1009:Src/main.c **** break; 1010:Src/main.c **** case TT_CHANGE_TEMP_1: 1011:Src/main.c **** // isn't implemented 1012:Src/main.c **** break; 1013:Src/main.c **** case TT_CHANGE_TEMP_2: 1014:Src/main.c **** // isn't implemented 1015:Src/main.c **** break; 1016:Src/main.c **** } ARM GAS /tmp/ccLSPxIe.s page 57 1017:Src/main.c **** 1018:Src/main.c **** if (TO7>TO7_before) 1019:Src/main.c **** { 1020:Src/main.c **** TO7_before = TO7; 1021:Src/main.c **** 1022:Src/main.c **** LD1_param.POWER = MPhD_T(1);//Get Data from monitor photodiode of LD1 1023:Src/main.c **** LD1_param.POWER = MPhD_T(1);//Get Data from monitor photodiode of LD1 1024:Src/main.c **** LD2_param.POWER = MPhD_T(2);//Get Data from monitor photodiode of LD2 1025:Src/main.c **** LD2_param.POWER = MPhD_T(2);//Get Data from monitor photodiode of LD2 1026:Src/main.c **** 1027:Src/main.c **** Long_Data[1] = LD1_param.POWER;//Translate Data from monitor photodiode of LD1 to Long_Data 1028:Src/main.c **** Long_Data[2] = LD2_param.POWER;//Translate Data from monitor photodiode of LD2 to Long_Data 1029:Src/main.c **** 1030:Src/main.c **** //Prepare DATA of internals ADCs 1031:Src/main.c **** //Put the temperature of LD2 to Long_Data: 1032:Src/main.c **** temp16 = Get_ADC(0); 1033:Src/main.c **** temp16 = Get_ADC(1); 1034:Src/main.c **** Long_Data[7] = temp16; 1035:Src/main.c **** 1036:Src/main.c **** //Put the temperature of LD2 to Long_Data: 1037:Src/main.c **** temp16 = Get_ADC(1); 1038:Src/main.c **** Long_Data[8] = temp16; 1039:Src/main.c **** 1040:Src/main.c **** //Put the temperature of LD2 to Long_Data: 1041:Src/main.c **** temp16 = Get_ADC(1); 1042:Src/main.c **** Long_Data[9] = temp16; 1043:Src/main.c **** 1044:Src/main.c **** //Put the temperature of LD2 to Long_Data: 1045:Src/main.c **** temp16 = Get_ADC(1); 1046:Src/main.c **** Long_Data[10] = temp16; 1047:Src/main.c **** 1048:Src/main.c **** //Put the temperature of LD2 to Long_Data: 1049:Src/main.c **** temp16 = Get_ADC(1); 1050:Src/main.c **** Long_Data[11] = temp16; 1051:Src/main.c **** temp16 = Get_ADC(2); 1052:Src/main.c **** 1053:Src/main.c **** //Put the temperature of LD2 to Long_Data: 1054:Src/main.c **** temp16 = Get_ADC(3); 1055:Src/main.c **** temp16 = Get_ADC(4); 1056:Src/main.c **** Long_Data[12] = temp16; 1057:Src/main.c **** temp16 = Get_ADC(5); 1058:Src/main.c **** 1059:Src/main.c **** //Put the timer tick to Long_Data: 1060:Src/main.c **** TO6_stop = TO6; 1061:Src/main.c **** Long_Data[3] = (TO6_stop)&0xffff; 1062:Src/main.c **** Long_Data[4] = (TO6_stop>>16)&0xffff; 1063:Src/main.c **** 1064:Src/main.c **** //Put the average temperature of LD1 to Long_Data: 1065:Src/main.c **** Long_Data[5] = LD1_param.LD_CURR_TEMP; 1066:Src/main.c **** 1067:Src/main.c **** //Put the average temperature of LD2 to Long_Data: 1068:Src/main.c **** Long_Data[6] = LD2_param.LD_CURR_TEMP; 1069:Src/main.c **** } 1070:Src/main.c **** while (!TIM10_coflag); 1071:Src/main.c **** 1072:Src/main.c **** Stop_TIM10(); 1073:Src/main.c **** ARM GAS /tmp/ccLSPxIe.s page 58 1074:Src/main.c **** if (task.tau > 3) 1075:Src/main.c **** { 1076:Src/main.c **** htim10.Init.Period = TIM10_period; 1077:Src/main.c **** TO10_counter = task.dt / 10; 1078:Src/main.c **** } 1079:Src/main.c **** 1080:Src/main.c **** CPU_state_old = RUN_TASK; 1081:Src/main.c **** break; 1082:Src/main.c **** } 1083:Src/main.c **** 1084:Src/main.c **** switch (UART_transmission_request) 1085:Src/main.c **** { 1086:Src/main.c **** case MESS_01://Default state 1087:Src/main.c **** USART_TX(State_Data,2); 1088:Src/main.c **** //HAL_UART_Transmit(&huart1, State_Data, 2, 10); 1089:Src/main.c **** State_Data[0]=0; 1090:Src/main.c **** State_Data[1]=0;//All OK! 1091:Src/main.c **** UART_transmission_request = NO_MESS; 1092:Src/main.c **** break; 1093:Src/main.c **** case MESS_02://Transmith packet 1094:Src/main.c **** 1095:Src/main.c **** //Find CS and put to Long_Data: 1096:Src/main.c **** CS_result = CalculateChecksum(&Long_Data[1], DL_16-2); 1097:Src/main.c **** Long_Data[DL_16-1] = CS_result; 1098:Src/main.c **** 1099:Src/main.c **** for (uint16_t i = 0; i < DL_16; i++) 1100:Src/main.c **** { 1101:Src/main.c **** UART_DATA[i*2] = (Long_Data[i])&0xff; 1102:Src/main.c **** UART_DATA[i*2+1] = (Long_Data[i]>>8)&0xff; 1103:Src/main.c **** } 1104:Src/main.c **** //HAL_NVIC_SetPriority(DMA2_Stream7_IRQn, 0, 0); 1105:Src/main.c **** //HAL_NVIC_EnableIRQ(DMA2_Stream7_IRQn); 1106:Src/main.c **** //HAL_UART_Transmit_DMA(&huart1, UART_DATA, DL_8); 1107:Src/main.c **** //huart1.gState = HAL_UART_STATE_READY; 1108:Src/main.c **** //hdma_usart1_tx.State=HAL_DMA_STATE_BUSY; 1109:Src/main.c **** USART_TX_DMA (DL_8);//Send data by USART using DMA 1110:Src/main.c **** UART_transmission_request = NO_MESS; 1111:Src/main.c **** break; 1112:Src/main.c **** case MESS_03://Transmith saved packet 1113:Src/main.c **** for (uint16_t i = 0; i < DL_16; i++) 1114:Src/main.c **** { 1115:Src/main.c **** UART_DATA[i*2] = (Long_Data[i])&0xff; 1116:Src/main.c **** UART_DATA[i*2+1] = (Long_Data[i]>>8)&0xff; 1117:Src/main.c **** } 1118:Src/main.c **** //HAL_NVIC_EnableIRQ(DMA2_Stream7_IRQn); 1119:Src/main.c **** //HAL_UART_Transmit_DMA(&huart1, UART_DATA, DL_8); 1120:Src/main.c **** //huart1.gState = HAL_UART_STATE_READY; 1121:Src/main.c **** //hdma_usart1_tx.State=HAL_DMA_STATE_BUSY; 1122:Src/main.c **** USART_TX_DMA (DL_8);//Send data by USART using DMA 1123:Src/main.c **** UART_transmission_request = NO_MESS; 1124:Src/main.c **** break; 1125:Src/main.c **** } 1126:Src/main.c **** if ((flg_tmt==1)&&((TO6-TO6_uart)>100))//Uart timeout handle. if timeout beetween zero byte of 1127:Src/main.c **** { 1128:Src/main.c **** UART_rec_incr = 0;//Reset uart command counter 1129:Src/main.c **** State_Data[0] |= UART_ERR;//timeout error! 1130:Src/main.c **** UART_transmission_request = MESS_01;//Send status ARM GAS /tmp/ccLSPxIe.s page 59 1131:Src/main.c **** flg_tmt = 0;//Reset timeout flag 1132:Src/main.c **** } 1133:Src/main.c **** /* USER CODE END WHILE */ 1134:Src/main.c **** 1135:Src/main.c **** /* USER CODE BEGIN 3 */ 1136:Src/main.c **** } 1137:Src/main.c **** /* USER CODE END 3 */ 1138:Src/main.c **** } 1139:Src/main.c **** 1140:Src/main.c **** /** 1141:Src/main.c **** * @brief System Clock Configuration 1142:Src/main.c **** * @retval None 1143:Src/main.c **** */ 1144:Src/main.c **** void SystemClock_Config(void) 1145:Src/main.c **** { 1146:Src/main.c **** RCC_OscInitTypeDef RCC_OscInitStruct = {0}; 1147:Src/main.c **** RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; 1148:Src/main.c **** 1149:Src/main.c **** /** Configure the main internal regulator output voltage 1150:Src/main.c **** */ 1151:Src/main.c **** __HAL_RCC_PWR_CLK_ENABLE(); 1152:Src/main.c **** __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); 1153:Src/main.c **** 1154:Src/main.c **** /** Initializes the RCC Oscillators according to the specified parameters 1155:Src/main.c **** * in the RCC_OscInitTypeDef structure. 1156:Src/main.c **** */ 1157:Src/main.c **** RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; 1158:Src/main.c **** RCC_OscInitStruct.HSEState = RCC_HSE_ON; 1159:Src/main.c **** RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; 1160:Src/main.c **** RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; 1161:Src/main.c **** RCC_OscInitStruct.PLL.PLLM = 25; 1162:Src/main.c **** RCC_OscInitStruct.PLL.PLLN = 368; 1163:Src/main.c **** RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; 1164:Src/main.c **** RCC_OscInitStruct.PLL.PLLQ = 8; 1165:Src/main.c **** RCC_OscInitStruct.PLL.PLLR = 2; 1166:Src/main.c **** if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) 1167:Src/main.c **** { 1168:Src/main.c **** Error_Handler(); 1169:Src/main.c **** } 1170:Src/main.c **** 1171:Src/main.c **** /** Activate the Over-Drive mode 1172:Src/main.c **** */ 1173:Src/main.c **** if (HAL_PWREx_EnableOverDrive() != HAL_OK) 1174:Src/main.c **** { 1175:Src/main.c **** Error_Handler(); 1176:Src/main.c **** } 1177:Src/main.c **** 1178:Src/main.c **** /** Initializes the CPU, AHB and APB buses clocks 1179:Src/main.c **** */ 1180:Src/main.c **** RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK 1181:Src/main.c **** |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; 1182:Src/main.c **** RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; 1183:Src/main.c **** RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; 1184:Src/main.c **** RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4; 1185:Src/main.c **** RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; 1186:Src/main.c **** 1187:Src/main.c **** if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_6) != HAL_OK) ARM GAS /tmp/ccLSPxIe.s page 60 1188:Src/main.c **** { 1189:Src/main.c **** Error_Handler(); 1190:Src/main.c **** } 1191:Src/main.c **** } 1192:Src/main.c **** 1193:Src/main.c **** /** 1194:Src/main.c **** * @brief ADC1 Initialization Function 1195:Src/main.c **** * @param None 1196:Src/main.c **** * @retval None 1197:Src/main.c **** */ 1198:Src/main.c **** static void MX_ADC1_Init(void) 1199:Src/main.c **** { 1200:Src/main.c **** 1201:Src/main.c **** /* USER CODE BEGIN ADC1_Init 0 */ 1202:Src/main.c **** 1203:Src/main.c **** /* USER CODE END ADC1_Init 0 */ 1204:Src/main.c **** 1205:Src/main.c **** ADC_ChannelConfTypeDef sConfig = {0}; 1206:Src/main.c **** 1207:Src/main.c **** /* USER CODE BEGIN ADC1_Init 1 */ 1208:Src/main.c **** 1209:Src/main.c **** /* USER CODE END ADC1_Init 1 */ 1210:Src/main.c **** 1211:Src/main.c **** /** Configure the global features of the ADC (Clock, Resolution, Data Alignment and number of con 1212:Src/main.c **** */ 1213:Src/main.c **** hadc1.Instance = ADC1; 1214:Src/main.c **** hadc1.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV8; 1215:Src/main.c **** hadc1.Init.Resolution = ADC_RESOLUTION_12B; 1216:Src/main.c **** hadc1.Init.ScanConvMode = ADC_SCAN_ENABLE; 1217:Src/main.c **** hadc1.Init.ContinuousConvMode = DISABLE; 1218:Src/main.c **** hadc1.Init.DiscontinuousConvMode = DISABLE; 1219:Src/main.c **** hadc1.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE; 1220:Src/main.c **** hadc1.Init.ExternalTrigConv = ADC_SOFTWARE_START; 1221:Src/main.c **** hadc1.Init.DataAlign = ADC_DATAALIGN_RIGHT; 1222:Src/main.c **** hadc1.Init.NbrOfConversion = 5; 1223:Src/main.c **** hadc1.Init.DMAContinuousRequests = DISABLE; 1224:Src/main.c **** hadc1.Init.EOCSelection = ADC_EOC_SINGLE_CONV; 1225:Src/main.c **** if (HAL_ADC_Init(&hadc1) != HAL_OK) 1226:Src/main.c **** { 1227:Src/main.c **** Error_Handler(); 1228:Src/main.c **** } 1229:Src/main.c **** 1230:Src/main.c **** /** Configure for the selected ADC regular channel its corresponding rank in the sequencer and it 1231:Src/main.c **** */ 1232:Src/main.c **** sConfig.Channel = ADC_CHANNEL_9; 1233:Src/main.c **** sConfig.Rank = ADC_REGULAR_RANK_1; 1234:Src/main.c **** sConfig.SamplingTime = ADC_SAMPLETIME_480CYCLES; 1235:Src/main.c **** if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 1236:Src/main.c **** { 1237:Src/main.c **** Error_Handler(); 1238:Src/main.c **** } 1239:Src/main.c **** 1240:Src/main.c **** /** Configure for the selected ADC regular channel its corresponding rank in the sequencer and it 1241:Src/main.c **** */ 1242:Src/main.c **** sConfig.Channel = ADC_CHANNEL_8; 1243:Src/main.c **** sConfig.Rank = ADC_REGULAR_RANK_2; 1244:Src/main.c **** if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) ARM GAS /tmp/ccLSPxIe.s page 61 1245:Src/main.c **** { 1246:Src/main.c **** Error_Handler(); 1247:Src/main.c **** } 1248:Src/main.c **** 1249:Src/main.c **** /** Configure for the selected ADC regular channel its corresponding rank in the sequencer and it 1250:Src/main.c **** */ 1251:Src/main.c **** sConfig.Channel = ADC_CHANNEL_2; 1252:Src/main.c **** sConfig.Rank = ADC_REGULAR_RANK_3; 1253:Src/main.c **** if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 1254:Src/main.c **** { 1255:Src/main.c **** Error_Handler(); 1256:Src/main.c **** } 1257:Src/main.c **** 1258:Src/main.c **** /** Configure for the selected ADC regular channel its corresponding rank in the sequencer and it 1259:Src/main.c **** */ 1260:Src/main.c **** sConfig.Channel = ADC_CHANNEL_10; 1261:Src/main.c **** sConfig.Rank = ADC_REGULAR_RANK_4; 1262:Src/main.c **** if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 1263:Src/main.c **** { 1264:Src/main.c **** Error_Handler(); 1265:Src/main.c **** } 1266:Src/main.c **** 1267:Src/main.c **** /** Configure for the selected ADC regular channel its corresponding rank in the sequencer and it 1268:Src/main.c **** */ 1269:Src/main.c **** sConfig.Channel = ADC_CHANNEL_11; 1270:Src/main.c **** sConfig.Rank = ADC_REGULAR_RANK_5; 1271:Src/main.c **** if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 1272:Src/main.c **** { 1273:Src/main.c **** Error_Handler(); 1274:Src/main.c **** } 1275:Src/main.c **** /* USER CODE BEGIN ADC1_Init 2 */ 1276:Src/main.c **** 1277:Src/main.c **** /* USER CODE END ADC1_Init 2 */ 1278:Src/main.c **** 1279:Src/main.c **** } 1280:Src/main.c **** 1281:Src/main.c **** /** 1282:Src/main.c **** * @brief ADC3 Initialization Function 1283:Src/main.c **** * @param None 1284:Src/main.c **** * @retval None 1285:Src/main.c **** */ 1286:Src/main.c **** static void MX_ADC3_Init(void) 1287:Src/main.c **** { 1288:Src/main.c **** 1289:Src/main.c **** /* USER CODE BEGIN ADC3_Init 0 */ 1290:Src/main.c **** 1291:Src/main.c **** /* USER CODE END ADC3_Init 0 */ 1292:Src/main.c **** 1293:Src/main.c **** ADC_ChannelConfTypeDef sConfig = {0}; 1294:Src/main.c **** 1295:Src/main.c **** /* USER CODE BEGIN ADC3_Init 1 */ 1296:Src/main.c **** 1297:Src/main.c **** /* USER CODE END ADC3_Init 1 */ 1298:Src/main.c **** 1299:Src/main.c **** /** Configure the global features of the ADC (Clock, Resolution, Data Alignment and number of con 1300:Src/main.c **** */ 1301:Src/main.c **** hadc3.Instance = ADC3; ARM GAS /tmp/ccLSPxIe.s page 62 1302:Src/main.c **** hadc3.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV8; 1303:Src/main.c **** hadc3.Init.Resolution = ADC_RESOLUTION_12B; 1304:Src/main.c **** hadc3.Init.ScanConvMode = ADC_SCAN_DISABLE; 1305:Src/main.c **** hadc3.Init.ContinuousConvMode = DISABLE; 1306:Src/main.c **** hadc3.Init.DiscontinuousConvMode = DISABLE; 1307:Src/main.c **** hadc3.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE; 1308:Src/main.c **** hadc3.Init.ExternalTrigConv = ADC_SOFTWARE_START; 1309:Src/main.c **** hadc3.Init.DataAlign = ADC_DATAALIGN_RIGHT; 1310:Src/main.c **** hadc3.Init.NbrOfConversion = 1; 1311:Src/main.c **** hadc3.Init.DMAContinuousRequests = DISABLE; 1312:Src/main.c **** hadc3.Init.EOCSelection = ADC_EOC_SINGLE_CONV; 1313:Src/main.c **** if (HAL_ADC_Init(&hadc3) != HAL_OK) 1314:Src/main.c **** { 1315:Src/main.c **** Error_Handler(); 1316:Src/main.c **** } 1317:Src/main.c **** 1318:Src/main.c **** /** Configure for the selected ADC regular channel its corresponding rank in the sequencer and it 1319:Src/main.c **** */ 1320:Src/main.c **** sConfig.Channel = ADC_CHANNEL_15; 1321:Src/main.c **** sConfig.Rank = ADC_REGULAR_RANK_1; 1322:Src/main.c **** sConfig.SamplingTime = ADC_SAMPLETIME_480CYCLES; 1323:Src/main.c **** if (HAL_ADC_ConfigChannel(&hadc3, &sConfig) != HAL_OK) 1324:Src/main.c **** { 1325:Src/main.c **** Error_Handler(); 1326:Src/main.c **** } 1327:Src/main.c **** /* USER CODE BEGIN ADC3_Init 2 */ 1328:Src/main.c **** 1329:Src/main.c **** /* USER CODE END ADC3_Init 2 */ 1330:Src/main.c **** 1331:Src/main.c **** } 1332:Src/main.c **** 1333:Src/main.c **** /** 1334:Src/main.c **** * @brief SDMMC1 Initialization Function 1335:Src/main.c **** * @param None 1336:Src/main.c **** * @retval None 1337:Src/main.c **** */ 1338:Src/main.c **** static void MX_SDMMC1_SD_Init(void) 1339:Src/main.c **** { 95 .loc 1 1339 1 is_stmt 1 view -0 96 .cfi_startproc 97 @ args = 0, pretend = 0, frame = 0 98 @ frame_needed = 0, uses_anonymous_args = 0 99 @ link register save eliminated. 1340:Src/main.c **** 1341:Src/main.c **** /* USER CODE BEGIN SDMMC1_Init 0 */ 1342:Src/main.c **** 1343:Src/main.c **** /* USER CODE END SDMMC1_Init 0 */ 1344:Src/main.c **** 1345:Src/main.c **** /* USER CODE BEGIN SDMMC1_Init 1 */ 1346:Src/main.c **** 1347:Src/main.c **** /* USER CODE END SDMMC1_Init 1 */ 1348:Src/main.c **** hsd1.Instance = SDMMC1; 100 .loc 1 1348 3 view .LVU21 101 .loc 1 1348 17 is_stmt 0 view .LVU22 102 0000 064B ldr r3, .L6 103 0002 074A ldr r2, .L6+4 104 0004 1A60 str r2, [r3] ARM GAS /tmp/ccLSPxIe.s page 63 1349:Src/main.c **** hsd1.Init.ClockEdge = SDMMC_CLOCK_EDGE_RISING; 105 .loc 1 1349 3 is_stmt 1 view .LVU23 106 .loc 1 1349 23 is_stmt 0 view .LVU24 107 0006 0022 movs r2, #0 108 0008 5A60 str r2, [r3, #4] 1350:Src/main.c **** hsd1.Init.ClockBypass = SDMMC_CLOCK_BYPASS_DISABLE; 109 .loc 1 1350 3 is_stmt 1 view .LVU25 110 .loc 1 1350 25 is_stmt 0 view .LVU26 111 000a 9A60 str r2, [r3, #8] 1351:Src/main.c **** hsd1.Init.ClockPowerSave = SDMMC_CLOCK_POWER_SAVE_DISABLE; 112 .loc 1 1351 3 is_stmt 1 view .LVU27 113 .loc 1 1351 28 is_stmt 0 view .LVU28 114 000c DA60 str r2, [r3, #12] 1352:Src/main.c **** hsd1.Init.BusWide = SDMMC_BUS_WIDE_4B; 115 .loc 1 1352 3 is_stmt 1 view .LVU29 116 .loc 1 1352 21 is_stmt 0 view .LVU30 117 000e 4FF40061 mov r1, #2048 118 0012 1961 str r1, [r3, #16] 1353:Src/main.c **** hsd1.Init.HardwareFlowControl = SDMMC_HARDWARE_FLOW_CONTROL_DISABLE; 119 .loc 1 1353 3 is_stmt 1 view .LVU31 120 .loc 1 1353 33 is_stmt 0 view .LVU32 121 0014 5A61 str r2, [r3, #20] 1354:Src/main.c **** hsd1.Init.ClockDiv = 20; 122 .loc 1 1354 3 is_stmt 1 view .LVU33 123 .loc 1 1354 22 is_stmt 0 view .LVU34 124 0016 1422 movs r2, #20 125 0018 9A61 str r2, [r3, #24] 1355:Src/main.c **** /* USER CODE BEGIN SDMMC1_Init 2 */ 1356:Src/main.c **** 1357:Src/main.c **** /* USER CODE END SDMMC1_Init 2 */ 1358:Src/main.c **** 1359:Src/main.c **** } 126 .loc 1 1359 1 view .LVU35 127 001a 7047 bx lr 128 .L7: 129 .align 2 130 .L6: 131 001c 00000000 .word hsd1 132 0020 002C0140 .word 1073818624 133 .cfi_endproc 134 .LFE1190: 136 .section .text.MX_DMA_Init,"ax",%progbits 137 .align 1 138 .syntax unified 139 .thumb 140 .thumb_func 142 MX_DMA_Init: 143 .LFB1206: 1360:Src/main.c **** 1361:Src/main.c **** /** 1362:Src/main.c **** * @brief SPI2 Initialization Function 1363:Src/main.c **** * @param None 1364:Src/main.c **** * @retval None 1365:Src/main.c **** */ 1366:Src/main.c **** static void MX_SPI2_Init(void) 1367:Src/main.c **** { 1368:Src/main.c **** ARM GAS /tmp/ccLSPxIe.s page 64 1369:Src/main.c **** /* USER CODE BEGIN SPI2_Init 0 */ 1370:Src/main.c **** 1371:Src/main.c **** /* USER CODE END SPI2_Init 0 */ 1372:Src/main.c **** 1373:Src/main.c **** LL_SPI_InitTypeDef SPI_InitStruct = {0}; 1374:Src/main.c **** 1375:Src/main.c **** LL_GPIO_InitTypeDef GPIO_InitStruct = {0}; 1376:Src/main.c **** 1377:Src/main.c **** /* Peripheral clock enable */ 1378:Src/main.c **** LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_SPI2); 1379:Src/main.c **** 1380:Src/main.c **** LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_GPIOB); 1381:Src/main.c **** /**SPI2 GPIO Configuration 1382:Src/main.c **** PB13 ------> SPI2_SCK 1383:Src/main.c **** PB14 ------> SPI2_MISO 1384:Src/main.c **** PB15 ------> SPI2_MOSI 1385:Src/main.c **** */ 1386:Src/main.c **** GPIO_InitStruct.Pin = LL_GPIO_PIN_13; 1387:Src/main.c **** GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE; 1388:Src/main.c **** GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH; 1389:Src/main.c **** GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; 1390:Src/main.c **** GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; 1391:Src/main.c **** GPIO_InitStruct.Alternate = LL_GPIO_AF_5; 1392:Src/main.c **** LL_GPIO_Init(GPIOB, &GPIO_InitStruct); 1393:Src/main.c **** 1394:Src/main.c **** GPIO_InitStruct.Pin = LL_GPIO_PIN_14; 1395:Src/main.c **** GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE; 1396:Src/main.c **** GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH; 1397:Src/main.c **** GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; 1398:Src/main.c **** GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; 1399:Src/main.c **** GPIO_InitStruct.Alternate = LL_GPIO_AF_5; 1400:Src/main.c **** LL_GPIO_Init(GPIOB, &GPIO_InitStruct); 1401:Src/main.c **** 1402:Src/main.c **** GPIO_InitStruct.Pin = LL_GPIO_PIN_15; 1403:Src/main.c **** GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE; 1404:Src/main.c **** GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH; 1405:Src/main.c **** GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; 1406:Src/main.c **** GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; 1407:Src/main.c **** GPIO_InitStruct.Alternate = LL_GPIO_AF_5; 1408:Src/main.c **** LL_GPIO_Init(GPIOB, &GPIO_InitStruct); 1409:Src/main.c **** 1410:Src/main.c **** /* USER CODE BEGIN SPI2_Init 1 */ 1411:Src/main.c **** 1412:Src/main.c **** /* USER CODE END SPI2_Init 1 */ 1413:Src/main.c **** /* SPI2 parameter configuration*/ 1414:Src/main.c **** SPI_InitStruct.TransferDirection = LL_SPI_FULL_DUPLEX; 1415:Src/main.c **** SPI_InitStruct.Mode = LL_SPI_MODE_MASTER; 1416:Src/main.c **** SPI_InitStruct.DataWidth = LL_SPI_DATAWIDTH_16BIT; 1417:Src/main.c **** SPI_InitStruct.ClockPolarity = LL_SPI_POLARITY_LOW; 1418:Src/main.c **** SPI_InitStruct.ClockPhase = LL_SPI_PHASE_1EDGE; 1419:Src/main.c **** SPI_InitStruct.NSS = LL_SPI_NSS_SOFT; 1420:Src/main.c **** SPI_InitStruct.BaudRate = LL_SPI_BAUDRATEPRESCALER_DIV8; 1421:Src/main.c **** SPI_InitStruct.BitOrder = LL_SPI_MSB_FIRST; 1422:Src/main.c **** SPI_InitStruct.CRCCalculation = LL_SPI_CRCCALCULATION_DISABLE; 1423:Src/main.c **** SPI_InitStruct.CRCPoly = 7; 1424:Src/main.c **** LL_SPI_Init(SPI2, &SPI_InitStruct); 1425:Src/main.c **** LL_SPI_SetStandard(SPI2, LL_SPI_PROTOCOL_MOTOROLA); ARM GAS /tmp/ccLSPxIe.s page 65 1426:Src/main.c **** LL_SPI_DisableNSSPulseMgt(SPI2); 1427:Src/main.c **** /* USER CODE BEGIN SPI2_Init 2 */ 1428:Src/main.c **** 1429:Src/main.c **** /* USER CODE END SPI2_Init 2 */ 1430:Src/main.c **** 1431:Src/main.c **** } 1432:Src/main.c **** 1433:Src/main.c **** /** 1434:Src/main.c **** * @brief SPI4 Initialization Function 1435:Src/main.c **** * @param None 1436:Src/main.c **** * @retval None 1437:Src/main.c **** */ 1438:Src/main.c **** static void MX_SPI4_Init(void) 1439:Src/main.c **** { 1440:Src/main.c **** 1441:Src/main.c **** /* USER CODE BEGIN SPI4_Init 0 */ 1442:Src/main.c **** 1443:Src/main.c **** /* USER CODE END SPI4_Init 0 */ 1444:Src/main.c **** 1445:Src/main.c **** LL_SPI_InitTypeDef SPI_InitStruct = {0}; 1446:Src/main.c **** 1447:Src/main.c **** LL_GPIO_InitTypeDef GPIO_InitStruct = {0}; 1448:Src/main.c **** 1449:Src/main.c **** /* Peripheral clock enable */ 1450:Src/main.c **** LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_SPI4); 1451:Src/main.c **** 1452:Src/main.c **** LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_GPIOE); 1453:Src/main.c **** /**SPI4 GPIO Configuration 1454:Src/main.c **** PE12 ------> SPI4_SCK 1455:Src/main.c **** PE13 ------> SPI4_MISO 1456:Src/main.c **** */ 1457:Src/main.c **** GPIO_InitStruct.Pin = LL_GPIO_PIN_12; 1458:Src/main.c **** GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE; 1459:Src/main.c **** GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH; 1460:Src/main.c **** GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; 1461:Src/main.c **** GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; 1462:Src/main.c **** GPIO_InitStruct.Alternate = LL_GPIO_AF_5; 1463:Src/main.c **** LL_GPIO_Init(GPIOE, &GPIO_InitStruct); 1464:Src/main.c **** 1465:Src/main.c **** GPIO_InitStruct.Pin = LL_GPIO_PIN_13; 1466:Src/main.c **** GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE; 1467:Src/main.c **** GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH; 1468:Src/main.c **** GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; 1469:Src/main.c **** GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; 1470:Src/main.c **** GPIO_InitStruct.Alternate = LL_GPIO_AF_5; 1471:Src/main.c **** LL_GPIO_Init(GPIOE, &GPIO_InitStruct); 1472:Src/main.c **** 1473:Src/main.c **** /* USER CODE BEGIN SPI4_Init 1 */ 1474:Src/main.c **** 1475:Src/main.c **** /* USER CODE END SPI4_Init 1 */ 1476:Src/main.c **** /* SPI4 parameter configuration*/ 1477:Src/main.c **** SPI_InitStruct.TransferDirection = LL_SPI_SIMPLEX_RX; 1478:Src/main.c **** SPI_InitStruct.Mode = LL_SPI_MODE_MASTER; 1479:Src/main.c **** SPI_InitStruct.DataWidth = LL_SPI_DATAWIDTH_16BIT; 1480:Src/main.c **** SPI_InitStruct.ClockPolarity = LL_SPI_POLARITY_HIGH; 1481:Src/main.c **** SPI_InitStruct.ClockPhase = LL_SPI_PHASE_1EDGE; 1482:Src/main.c **** SPI_InitStruct.NSS = LL_SPI_NSS_SOFT; ARM GAS /tmp/ccLSPxIe.s page 66 1483:Src/main.c **** SPI_InitStruct.BaudRate = LL_SPI_BAUDRATEPRESCALER_DIV16; 1484:Src/main.c **** SPI_InitStruct.BitOrder = LL_SPI_MSB_FIRST; 1485:Src/main.c **** SPI_InitStruct.CRCCalculation = LL_SPI_CRCCALCULATION_DISABLE; 1486:Src/main.c **** SPI_InitStruct.CRCPoly = 7; 1487:Src/main.c **** LL_SPI_Init(SPI4, &SPI_InitStruct); 1488:Src/main.c **** LL_SPI_SetStandard(SPI4, LL_SPI_PROTOCOL_MOTOROLA); 1489:Src/main.c **** LL_SPI_DisableNSSPulseMgt(SPI4); 1490:Src/main.c **** /* USER CODE BEGIN SPI4_Init 2 */ 1491:Src/main.c **** 1492:Src/main.c **** /* USER CODE END SPI4_Init 2 */ 1493:Src/main.c **** 1494:Src/main.c **** } 1495:Src/main.c **** 1496:Src/main.c **** /** 1497:Src/main.c **** * @brief SPI5 Initialization Function 1498:Src/main.c **** * @param None 1499:Src/main.c **** * @retval None 1500:Src/main.c **** */ 1501:Src/main.c **** static void MX_SPI5_Init(void) 1502:Src/main.c **** { 1503:Src/main.c **** 1504:Src/main.c **** /* USER CODE BEGIN SPI5_Init 0 */ 1505:Src/main.c **** 1506:Src/main.c **** /* USER CODE END SPI5_Init 0 */ 1507:Src/main.c **** 1508:Src/main.c **** LL_SPI_InitTypeDef SPI_InitStruct = {0}; 1509:Src/main.c **** 1510:Src/main.c **** LL_GPIO_InitTypeDef GPIO_InitStruct = {0}; 1511:Src/main.c **** 1512:Src/main.c **** /* Peripheral clock enable */ 1513:Src/main.c **** LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_SPI5); 1514:Src/main.c **** 1515:Src/main.c **** LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_GPIOF); 1516:Src/main.c **** /**SPI5 GPIO Configuration 1517:Src/main.c **** PF7 ------> SPI5_SCK 1518:Src/main.c **** PF8 ------> SPI5_MISO 1519:Src/main.c **** */ 1520:Src/main.c **** GPIO_InitStruct.Pin = LL_GPIO_PIN_7; 1521:Src/main.c **** GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE; 1522:Src/main.c **** GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH; 1523:Src/main.c **** GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; 1524:Src/main.c **** GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; 1525:Src/main.c **** GPIO_InitStruct.Alternate = LL_GPIO_AF_5; 1526:Src/main.c **** LL_GPIO_Init(GPIOF, &GPIO_InitStruct); 1527:Src/main.c **** 1528:Src/main.c **** GPIO_InitStruct.Pin = LL_GPIO_PIN_8; 1529:Src/main.c **** GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE; 1530:Src/main.c **** GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH; 1531:Src/main.c **** GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; 1532:Src/main.c **** GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; 1533:Src/main.c **** GPIO_InitStruct.Alternate = LL_GPIO_AF_5; 1534:Src/main.c **** LL_GPIO_Init(GPIOF, &GPIO_InitStruct); 1535:Src/main.c **** 1536:Src/main.c **** /* USER CODE BEGIN SPI5_Init 1 */ 1537:Src/main.c **** 1538:Src/main.c **** /* USER CODE END SPI5_Init 1 */ 1539:Src/main.c **** /* SPI5 parameter configuration*/ ARM GAS /tmp/ccLSPxIe.s page 67 1540:Src/main.c **** SPI_InitStruct.TransferDirection = LL_SPI_SIMPLEX_RX; 1541:Src/main.c **** SPI_InitStruct.Mode = LL_SPI_MODE_MASTER; 1542:Src/main.c **** SPI_InitStruct.DataWidth = LL_SPI_DATAWIDTH_16BIT; 1543:Src/main.c **** SPI_InitStruct.ClockPolarity = LL_SPI_POLARITY_HIGH; 1544:Src/main.c **** SPI_InitStruct.ClockPhase = LL_SPI_PHASE_1EDGE; 1545:Src/main.c **** SPI_InitStruct.NSS = LL_SPI_NSS_SOFT; 1546:Src/main.c **** SPI_InitStruct.BaudRate = LL_SPI_BAUDRATEPRESCALER_DIV16; 1547:Src/main.c **** SPI_InitStruct.BitOrder = LL_SPI_MSB_FIRST; 1548:Src/main.c **** SPI_InitStruct.CRCCalculation = LL_SPI_CRCCALCULATION_DISABLE; 1549:Src/main.c **** SPI_InitStruct.CRCPoly = 7; 1550:Src/main.c **** LL_SPI_Init(SPI5, &SPI_InitStruct); 1551:Src/main.c **** LL_SPI_SetStandard(SPI5, LL_SPI_PROTOCOL_MOTOROLA); 1552:Src/main.c **** LL_SPI_DisableNSSPulseMgt(SPI5); 1553:Src/main.c **** /* USER CODE BEGIN SPI5_Init 2 */ 1554:Src/main.c **** 1555:Src/main.c **** /* USER CODE END SPI5_Init 2 */ 1556:Src/main.c **** 1557:Src/main.c **** } 1558:Src/main.c **** 1559:Src/main.c **** /** 1560:Src/main.c **** * @brief SPI6 Initialization Function 1561:Src/main.c **** * @param None 1562:Src/main.c **** * @retval None 1563:Src/main.c **** */ 1564:Src/main.c **** static void MX_SPI6_Init(void) 1565:Src/main.c **** { 1566:Src/main.c **** 1567:Src/main.c **** /* USER CODE BEGIN SPI6_Init 0 */ 1568:Src/main.c **** 1569:Src/main.c **** /* USER CODE END SPI6_Init 0 */ 1570:Src/main.c **** 1571:Src/main.c **** LL_SPI_InitTypeDef SPI_InitStruct = {0}; 1572:Src/main.c **** 1573:Src/main.c **** LL_GPIO_InitTypeDef GPIO_InitStruct = {0}; 1574:Src/main.c **** 1575:Src/main.c **** /* Peripheral clock enable */ 1576:Src/main.c **** LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_SPI6); 1577:Src/main.c **** 1578:Src/main.c **** LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_GPIOA); 1579:Src/main.c **** /**SPI6 GPIO Configuration 1580:Src/main.c **** PA5 ------> SPI6_SCK 1581:Src/main.c **** PA7 ------> SPI6_MOSI 1582:Src/main.c **** */ 1583:Src/main.c **** GPIO_InitStruct.Pin = LL_GPIO_PIN_5; 1584:Src/main.c **** GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE; 1585:Src/main.c **** GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH; 1586:Src/main.c **** GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; 1587:Src/main.c **** GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; 1588:Src/main.c **** GPIO_InitStruct.Alternate = LL_GPIO_AF_8; 1589:Src/main.c **** LL_GPIO_Init(GPIOA, &GPIO_InitStruct); 1590:Src/main.c **** 1591:Src/main.c **** GPIO_InitStruct.Pin = LL_GPIO_PIN_7; 1592:Src/main.c **** GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE; 1593:Src/main.c **** GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH; 1594:Src/main.c **** GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; 1595:Src/main.c **** GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; 1596:Src/main.c **** GPIO_InitStruct.Alternate = LL_GPIO_AF_8; ARM GAS /tmp/ccLSPxIe.s page 68 1597:Src/main.c **** LL_GPIO_Init(GPIOA, &GPIO_InitStruct); 1598:Src/main.c **** 1599:Src/main.c **** /* USER CODE BEGIN SPI6_Init 1 */ 1600:Src/main.c **** 1601:Src/main.c **** /* USER CODE END SPI6_Init 1 */ 1602:Src/main.c **** /* SPI6 parameter configuration*/ 1603:Src/main.c **** SPI_InitStruct.TransferDirection = LL_SPI_FULL_DUPLEX; 1604:Src/main.c **** SPI_InitStruct.Mode = LL_SPI_MODE_MASTER; 1605:Src/main.c **** SPI_InitStruct.DataWidth = LL_SPI_DATAWIDTH_16BIT; 1606:Src/main.c **** SPI_InitStruct.ClockPolarity = LL_SPI_POLARITY_HIGH; 1607:Src/main.c **** SPI_InitStruct.ClockPhase = LL_SPI_PHASE_2EDGE; 1608:Src/main.c **** SPI_InitStruct.NSS = LL_SPI_NSS_SOFT; 1609:Src/main.c **** SPI_InitStruct.BaudRate = LL_SPI_BAUDRATEPRESCALER_DIV16; 1610:Src/main.c **** SPI_InitStruct.BitOrder = LL_SPI_MSB_FIRST; 1611:Src/main.c **** SPI_InitStruct.CRCCalculation = LL_SPI_CRCCALCULATION_DISABLE; 1612:Src/main.c **** SPI_InitStruct.CRCPoly = 7; 1613:Src/main.c **** LL_SPI_Init(SPI6, &SPI_InitStruct); 1614:Src/main.c **** LL_SPI_SetStandard(SPI6, LL_SPI_PROTOCOL_MOTOROLA); 1615:Src/main.c **** LL_SPI_DisableNSSPulseMgt(SPI6); 1616:Src/main.c **** /* USER CODE BEGIN SPI6_Init 2 */ 1617:Src/main.c **** 1618:Src/main.c **** /* USER CODE END SPI6_Init 2 */ 1619:Src/main.c **** 1620:Src/main.c **** } 1621:Src/main.c **** 1622:Src/main.c **** /** 1623:Src/main.c **** * @brief TIM2 Initialization Function 1624:Src/main.c **** * @param None 1625:Src/main.c **** * @retval None 1626:Src/main.c **** */ 1627:Src/main.c **** static void MX_TIM2_Init(void) 1628:Src/main.c **** { 1629:Src/main.c **** 1630:Src/main.c **** /* USER CODE BEGIN TIM2_Init 0 */ 1631:Src/main.c **** 1632:Src/main.c **** /* USER CODE END TIM2_Init 0 */ 1633:Src/main.c **** 1634:Src/main.c **** LL_TIM_InitTypeDef TIM_InitStruct = {0}; 1635:Src/main.c **** 1636:Src/main.c **** /* Peripheral clock enable */ 1637:Src/main.c **** LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_TIM2); 1638:Src/main.c **** 1639:Src/main.c **** /* TIM2 interrupt Init */ 1640:Src/main.c **** NVIC_SetPriority(TIM2_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(),0, 0)); 1641:Src/main.c **** NVIC_EnableIRQ(TIM2_IRQn); 1642:Src/main.c **** 1643:Src/main.c **** /* USER CODE BEGIN TIM2_Init 1 */ 1644:Src/main.c **** 1645:Src/main.c **** /* USER CODE END TIM2_Init 1 */ 1646:Src/main.c **** TIM_InitStruct.Prescaler = 1000; 1647:Src/main.c **** TIM_InitStruct.CounterMode = LL_TIM_COUNTERMODE_UP; 1648:Src/main.c **** TIM_InitStruct.Autoreload = 840000; 1649:Src/main.c **** TIM_InitStruct.ClockDivision = LL_TIM_CLOCKDIVISION_DIV1; 1650:Src/main.c **** LL_TIM_Init(TIM2, &TIM_InitStruct); 1651:Src/main.c **** LL_TIM_DisableARRPreload(TIM2); 1652:Src/main.c **** LL_TIM_SetClockSource(TIM2, LL_TIM_CLOCKSOURCE_INTERNAL); 1653:Src/main.c **** LL_TIM_SetTriggerOutput(TIM2, LL_TIM_TRGO_RESET); ARM GAS /tmp/ccLSPxIe.s page 69 1654:Src/main.c **** LL_TIM_DisableMasterSlaveMode(TIM2); 1655:Src/main.c **** /* USER CODE BEGIN TIM2_Init 2 */ 1656:Src/main.c **** 1657:Src/main.c **** /* USER CODE END TIM2_Init 2 */ 1658:Src/main.c **** 1659:Src/main.c **** } 1660:Src/main.c **** 1661:Src/main.c **** /** 1662:Src/main.c **** * @brief TIM4 Initialization Function 1663:Src/main.c **** * @param None 1664:Src/main.c **** * @retval None 1665:Src/main.c **** */ 1666:Src/main.c **** static void MX_TIM4_Init(void) 1667:Src/main.c **** { 1668:Src/main.c **** 1669:Src/main.c **** /* USER CODE BEGIN TIM4_Init 0 */ 1670:Src/main.c **** 1671:Src/main.c **** /* USER CODE END TIM4_Init 0 */ 1672:Src/main.c **** 1673:Src/main.c **** TIM_ClockConfigTypeDef sClockSourceConfig = {0}; 1674:Src/main.c **** TIM_MasterConfigTypeDef sMasterConfig = {0}; 1675:Src/main.c **** TIM_OC_InitTypeDef sConfigOC = {0}; 1676:Src/main.c **** 1677:Src/main.c **** /* USER CODE BEGIN TIM4_Init 1 */ 1678:Src/main.c **** 1679:Src/main.c **** /* USER CODE END TIM4_Init 1 */ 1680:Src/main.c **** htim4.Instance = TIM4; 1681:Src/main.c **** htim4.Init.Prescaler = 0; 1682:Src/main.c **** htim4.Init.CounterMode = TIM_COUNTERMODE_UP; 1683:Src/main.c **** htim4.Init.Period = 45; 1684:Src/main.c **** htim4.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; 1685:Src/main.c **** htim4.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; 1686:Src/main.c **** if (HAL_TIM_Base_Init(&htim4) != HAL_OK) 1687:Src/main.c **** { 1688:Src/main.c **** Error_Handler(); 1689:Src/main.c **** } 1690:Src/main.c **** sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL; 1691:Src/main.c **** if (HAL_TIM_ConfigClockSource(&htim4, &sClockSourceConfig) != HAL_OK) 1692:Src/main.c **** { 1693:Src/main.c **** Error_Handler(); 1694:Src/main.c **** } 1695:Src/main.c **** if (HAL_TIM_PWM_Init(&htim4) != HAL_OK) 1696:Src/main.c **** { 1697:Src/main.c **** Error_Handler(); 1698:Src/main.c **** } 1699:Src/main.c **** sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; 1700:Src/main.c **** sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; 1701:Src/main.c **** if (HAL_TIMEx_MasterConfigSynchronization(&htim4, &sMasterConfig) != HAL_OK) 1702:Src/main.c **** { 1703:Src/main.c **** Error_Handler(); 1704:Src/main.c **** } 1705:Src/main.c **** sConfigOC.OCMode = TIM_OCMODE_PWM1; 1706:Src/main.c **** sConfigOC.Pulse = 22; 1707:Src/main.c **** sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH; 1708:Src/main.c **** sConfigOC.OCFastMode = TIM_OCFAST_DISABLE; 1709:Src/main.c **** if (HAL_TIM_PWM_ConfigChannel(&htim4, &sConfigOC, TIM_CHANNEL_3) != HAL_OK) 1710:Src/main.c **** { ARM GAS /tmp/ccLSPxIe.s page 70 1711:Src/main.c **** Error_Handler(); 1712:Src/main.c **** } 1713:Src/main.c **** /* USER CODE BEGIN TIM4_Init 2 */ 1714:Src/main.c **** 1715:Src/main.c **** /* USER CODE END TIM4_Init 2 */ 1716:Src/main.c **** HAL_TIM_MspPostInit(&htim4); 1717:Src/main.c **** 1718:Src/main.c **** } 1719:Src/main.c **** 1720:Src/main.c **** /** 1721:Src/main.c **** * @brief TIM5 Initialization Function 1722:Src/main.c **** * @param None 1723:Src/main.c **** * @retval None 1724:Src/main.c **** */ 1725:Src/main.c **** static void MX_TIM5_Init(void) 1726:Src/main.c **** { 1727:Src/main.c **** 1728:Src/main.c **** /* USER CODE BEGIN TIM5_Init 0 */ 1729:Src/main.c **** 1730:Src/main.c **** /* USER CODE END TIM5_Init 0 */ 1731:Src/main.c **** 1732:Src/main.c **** LL_TIM_InitTypeDef TIM_InitStruct = {0}; 1733:Src/main.c **** 1734:Src/main.c **** /* Peripheral clock enable */ 1735:Src/main.c **** LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_TIM5); 1736:Src/main.c **** 1737:Src/main.c **** /* TIM5 interrupt Init */ 1738:Src/main.c **** NVIC_SetPriority(TIM5_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(),0, 0)); 1739:Src/main.c **** NVIC_EnableIRQ(TIM5_IRQn); 1740:Src/main.c **** 1741:Src/main.c **** /* USER CODE BEGIN TIM5_Init 1 */ 1742:Src/main.c **** 1743:Src/main.c **** /* USER CODE END TIM5_Init 1 */ 1744:Src/main.c **** TIM_InitStruct.Prescaler = 10000; 1745:Src/main.c **** TIM_InitStruct.CounterMode = LL_TIM_COUNTERMODE_UP; 1746:Src/main.c **** TIM_InitStruct.Autoreload = 560; 1747:Src/main.c **** TIM_InitStruct.ClockDivision = LL_TIM_CLOCKDIVISION_DIV1; 1748:Src/main.c **** LL_TIM_Init(TIM5, &TIM_InitStruct); 1749:Src/main.c **** LL_TIM_DisableARRPreload(TIM5); 1750:Src/main.c **** LL_TIM_SetClockSource(TIM5, LL_TIM_CLOCKSOURCE_INTERNAL); 1751:Src/main.c **** LL_TIM_SetTriggerOutput(TIM5, LL_TIM_TRGO_RESET); 1752:Src/main.c **** LL_TIM_DisableMasterSlaveMode(TIM5); 1753:Src/main.c **** /* USER CODE BEGIN TIM5_Init 2 */ 1754:Src/main.c **** 1755:Src/main.c **** /* USER CODE END TIM5_Init 2 */ 1756:Src/main.c **** 1757:Src/main.c **** } 1758:Src/main.c **** 1759:Src/main.c **** /** 1760:Src/main.c **** * @brief TIM6 Initialization Function 1761:Src/main.c **** * @param None 1762:Src/main.c **** * @retval None 1763:Src/main.c **** */ 1764:Src/main.c **** static void MX_TIM6_Init(void) 1765:Src/main.c **** { 1766:Src/main.c **** 1767:Src/main.c **** /* USER CODE BEGIN TIM6_Init 0 */ ARM GAS /tmp/ccLSPxIe.s page 71 1768:Src/main.c **** 1769:Src/main.c **** /* USER CODE END TIM6_Init 0 */ 1770:Src/main.c **** 1771:Src/main.c **** LL_TIM_InitTypeDef TIM_InitStruct = {0}; 1772:Src/main.c **** 1773:Src/main.c **** /* Peripheral clock enable */ 1774:Src/main.c **** LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_TIM6); 1775:Src/main.c **** 1776:Src/main.c **** /* TIM6 interrupt Init */ 1777:Src/main.c **** NVIC_SetPriority(TIM6_DAC_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(),0, 0)); 1778:Src/main.c **** NVIC_EnableIRQ(TIM6_DAC_IRQn); 1779:Src/main.c **** 1780:Src/main.c **** /* USER CODE BEGIN TIM6_Init 1 */ 1781:Src/main.c **** 1782:Src/main.c **** /* USER CODE END TIM6_Init 1 */ 1783:Src/main.c **** TIM_InitStruct.Prescaler = 45999; 1784:Src/main.c **** TIM_InitStruct.CounterMode = LL_TIM_COUNTERMODE_UP; 1785:Src/main.c **** TIM_InitStruct.Autoreload = 19; 1786:Src/main.c **** LL_TIM_Init(TIM6, &TIM_InitStruct); 1787:Src/main.c **** LL_TIM_DisableARRPreload(TIM6); 1788:Src/main.c **** LL_TIM_SetTriggerOutput(TIM6, LL_TIM_TRGO_ENABLE); 1789:Src/main.c **** LL_TIM_DisableMasterSlaveMode(TIM6); 1790:Src/main.c **** /* USER CODE BEGIN TIM6_Init 2 */ 1791:Src/main.c **** 1792:Src/main.c **** /* USER CODE END TIM6_Init 2 */ 1793:Src/main.c **** 1794:Src/main.c **** } 1795:Src/main.c **** 1796:Src/main.c **** /** 1797:Src/main.c **** * @brief TIM7 Initialization Function 1798:Src/main.c **** * @param None 1799:Src/main.c **** * @retval None 1800:Src/main.c **** */ 1801:Src/main.c **** static void MX_TIM7_Init(void) 1802:Src/main.c **** { 1803:Src/main.c **** 1804:Src/main.c **** /* USER CODE BEGIN TIM7_Init 0 */ 1805:Src/main.c **** 1806:Src/main.c **** /* USER CODE END TIM7_Init 0 */ 1807:Src/main.c **** 1808:Src/main.c **** LL_TIM_InitTypeDef TIM_InitStruct = {0}; 1809:Src/main.c **** 1810:Src/main.c **** /* Peripheral clock enable */ 1811:Src/main.c **** LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_TIM7); 1812:Src/main.c **** 1813:Src/main.c **** /* TIM7 interrupt Init */ 1814:Src/main.c **** NVIC_SetPriority(TIM7_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(),0, 0)); 1815:Src/main.c **** NVIC_EnableIRQ(TIM7_IRQn); 1816:Src/main.c **** 1817:Src/main.c **** /* USER CODE BEGIN TIM7_Init 1 */ 1818:Src/main.c **** 1819:Src/main.c **** /* USER CODE END TIM7_Init 1 */ 1820:Src/main.c **** TIM_InitStruct.Prescaler = 919; 1821:Src/main.c **** TIM_InitStruct.CounterMode = LL_TIM_COUNTERMODE_UP; 1822:Src/main.c **** TIM_InitStruct.Autoreload = 99; 1823:Src/main.c **** LL_TIM_Init(TIM7, &TIM_InitStruct); 1824:Src/main.c **** LL_TIM_DisableARRPreload(TIM7); ARM GAS /tmp/ccLSPxIe.s page 72 1825:Src/main.c **** LL_TIM_SetTriggerOutput(TIM7, LL_TIM_TRGO_ENABLE); 1826:Src/main.c **** LL_TIM_DisableMasterSlaveMode(TIM7); 1827:Src/main.c **** /* USER CODE BEGIN TIM7_Init 2 */ 1828:Src/main.c **** 1829:Src/main.c **** /* USER CODE END TIM7_Init 2 */ 1830:Src/main.c **** 1831:Src/main.c **** } 1832:Src/main.c **** 1833:Src/main.c **** /** 1834:Src/main.c **** * @brief TIM8 Initialization Function 1835:Src/main.c **** * @param None 1836:Src/main.c **** * @retval None 1837:Src/main.c **** */ 1838:Src/main.c **** static void MX_TIM8_Init(void) 1839:Src/main.c **** { 1840:Src/main.c **** 1841:Src/main.c **** /* USER CODE BEGIN TIM8_Init 0 */ 1842:Src/main.c **** 1843:Src/main.c **** /* USER CODE END TIM8_Init 0 */ 1844:Src/main.c **** 1845:Src/main.c **** TIM_ClockConfigTypeDef sClockSourceConfig = {0}; 1846:Src/main.c **** TIM_MasterConfigTypeDef sMasterConfig = {0}; 1847:Src/main.c **** 1848:Src/main.c **** /* USER CODE BEGIN TIM8_Init 1 */ 1849:Src/main.c **** 1850:Src/main.c **** /* USER CODE END TIM8_Init 1 */ 1851:Src/main.c **** htim8.Instance = TIM8; 1852:Src/main.c **** htim8.Init.Prescaler = 0; 1853:Src/main.c **** htim8.Init.CounterMode = TIM_COUNTERMODE_UP; 1854:Src/main.c **** htim8.Init.Period = 91; 1855:Src/main.c **** htim8.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; 1856:Src/main.c **** htim8.Init.RepetitionCounter = 0; 1857:Src/main.c **** htim8.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; 1858:Src/main.c **** if (HAL_TIM_Base_Init(&htim8) != HAL_OK) 1859:Src/main.c **** { 1860:Src/main.c **** Error_Handler(); 1861:Src/main.c **** } 1862:Src/main.c **** sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL; 1863:Src/main.c **** if (HAL_TIM_ConfigClockSource(&htim8, &sClockSourceConfig) != HAL_OK) 1864:Src/main.c **** { 1865:Src/main.c **** Error_Handler(); 1866:Src/main.c **** } 1867:Src/main.c **** sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; 1868:Src/main.c **** sMasterConfig.MasterOutputTrigger2 = TIM_TRGO2_RESET; 1869:Src/main.c **** sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; 1870:Src/main.c **** if (HAL_TIMEx_MasterConfigSynchronization(&htim8, &sMasterConfig) != HAL_OK) 1871:Src/main.c **** { 1872:Src/main.c **** Error_Handler(); 1873:Src/main.c **** } 1874:Src/main.c **** /* USER CODE BEGIN TIM8_Init 2 */ 1875:Src/main.c **** 1876:Src/main.c **** /* USER CODE END TIM8_Init 2 */ 1877:Src/main.c **** 1878:Src/main.c **** } 1879:Src/main.c **** 1880:Src/main.c **** /** 1881:Src/main.c **** * @brief TIM10 Initialization Function ARM GAS /tmp/ccLSPxIe.s page 73 1882:Src/main.c **** * @param None 1883:Src/main.c **** * @retval None 1884:Src/main.c **** */ 1885:Src/main.c **** static void MX_TIM10_Init(void) 1886:Src/main.c **** { 1887:Src/main.c **** 1888:Src/main.c **** /* USER CODE BEGIN TIM10_Init 0 */ 1889:Src/main.c **** 1890:Src/main.c **** /* USER CODE END TIM10_Init 0 */ 1891:Src/main.c **** 1892:Src/main.c **** /* USER CODE BEGIN TIM10_Init 1 */ 1893:Src/main.c **** 1894:Src/main.c **** /* USER CODE END TIM10_Init 1 */ 1895:Src/main.c **** htim10.Instance = TIM10; 1896:Src/main.c **** htim10.Init.Prescaler = 183; 1897:Src/main.c **** htim10.Init.CounterMode = TIM_COUNTERMODE_UP; 1898:Src/main.c **** htim10.Init.Period = 9; 1899:Src/main.c **** htim10.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; 1900:Src/main.c **** htim10.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; 1901:Src/main.c **** if (HAL_TIM_Base_Init(&htim10) != HAL_OK) 1902:Src/main.c **** { 1903:Src/main.c **** Error_Handler(); 1904:Src/main.c **** } 1905:Src/main.c **** /* USER CODE BEGIN TIM10_Init 2 */ 1906:Src/main.c **** 1907:Src/main.c **** /* USER CODE END TIM10_Init 2 */ 1908:Src/main.c **** 1909:Src/main.c **** } 1910:Src/main.c **** 1911:Src/main.c **** /** 1912:Src/main.c **** * @brief TIM11 Initialization Function 1913:Src/main.c **** * @param None 1914:Src/main.c **** * @retval None 1915:Src/main.c **** */ 1916:Src/main.c **** static void MX_TIM11_Init(void) 1917:Src/main.c **** { 1918:Src/main.c **** 1919:Src/main.c **** /* USER CODE BEGIN TIM11_Init 0 */ 1920:Src/main.c **** 1921:Src/main.c **** /* USER CODE END TIM11_Init 0 */ 1922:Src/main.c **** 1923:Src/main.c **** TIM_OC_InitTypeDef sConfigOC = {0}; 1924:Src/main.c **** 1925:Src/main.c **** /* USER CODE BEGIN TIM11_Init 1 */ 1926:Src/main.c **** 1927:Src/main.c **** /* USER CODE END TIM11_Init 1 */ 1928:Src/main.c **** htim11.Instance = TIM11; 1929:Src/main.c **** htim11.Init.Prescaler = 1; 1930:Src/main.c **** htim11.Init.CounterMode = TIM_COUNTERMODE_UP; 1931:Src/main.c **** htim11.Init.Period = 91; 1932:Src/main.c **** htim11.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; 1933:Src/main.c **** htim11.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_ENABLE; 1934:Src/main.c **** if (HAL_TIM_Base_Init(&htim11) != HAL_OK) 1935:Src/main.c **** { 1936:Src/main.c **** Error_Handler(); 1937:Src/main.c **** } 1938:Src/main.c **** if (HAL_TIM_PWM_Init(&htim11) != HAL_OK) ARM GAS /tmp/ccLSPxIe.s page 74 1939:Src/main.c **** { 1940:Src/main.c **** Error_Handler(); 1941:Src/main.c **** } 1942:Src/main.c **** sConfigOC.OCMode = TIM_OCMODE_PWM1; 1943:Src/main.c **** sConfigOC.Pulse = 91; 1944:Src/main.c **** sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH; 1945:Src/main.c **** sConfigOC.OCFastMode = TIM_OCFAST_DISABLE; 1946:Src/main.c **** if (HAL_TIM_PWM_ConfigChannel(&htim11, &sConfigOC, TIM_CHANNEL_1) != HAL_OK) 1947:Src/main.c **** { 1948:Src/main.c **** Error_Handler(); 1949:Src/main.c **** } 1950:Src/main.c **** /* USER CODE BEGIN TIM11_Init 2 */ 1951:Src/main.c **** 1952:Src/main.c **** /* USER CODE END TIM11_Init 2 */ 1953:Src/main.c **** HAL_TIM_MspPostInit(&htim11); 1954:Src/main.c **** 1955:Src/main.c **** } 1956:Src/main.c **** 1957:Src/main.c **** /** 1958:Src/main.c **** * @brief TIM1 Initialization Function 1959:Src/main.c **** * @param None 1960:Src/main.c **** * @retval None 1961:Src/main.c **** */ 1962:Src/main.c **** static void MX_TIM1_Init(void) 1963:Src/main.c **** { 1964:Src/main.c **** 1965:Src/main.c **** /* USER CODE BEGIN TIM1_Init 0 */ 1966:Src/main.c **** 1967:Src/main.c **** /* USER CODE END TIM1_Init 0 */ 1968:Src/main.c **** 1969:Src/main.c **** TIM_ClockConfigTypeDef sClockSourceConfig = {0}; 1970:Src/main.c **** TIM_OC_InitTypeDef sConfigOC = {0}; 1971:Src/main.c **** TIM_BreakDeadTimeConfigTypeDef sBreakDeadTimeConfig = {0}; 1972:Src/main.c **** 1973:Src/main.c **** /* USER CODE BEGIN TIM1_Init 1 */ 1974:Src/main.c **** 1975:Src/main.c **** /* USER CODE END TIM1_Init 1 */ 1976:Src/main.c **** htim1.Instance = TIM1; 1977:Src/main.c **** htim1.Init.Prescaler = 0; 1978:Src/main.c **** htim1.Init.CounterMode = TIM_COUNTERMODE_UP; 1979:Src/main.c **** htim1.Init.Period = 8; 1980:Src/main.c **** htim1.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; 1981:Src/main.c **** htim1.Init.RepetitionCounter = 0; 1982:Src/main.c **** htim1.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; 1983:Src/main.c **** if (HAL_TIM_Base_Init(&htim1) != HAL_OK) 1984:Src/main.c **** { 1985:Src/main.c **** Error_Handler(); 1986:Src/main.c **** } 1987:Src/main.c **** sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL; 1988:Src/main.c **** if (HAL_TIM_ConfigClockSource(&htim1, &sClockSourceConfig) != HAL_OK) 1989:Src/main.c **** { 1990:Src/main.c **** Error_Handler(); 1991:Src/main.c **** } 1992:Src/main.c **** if (HAL_TIM_PWM_Init(&htim1) != HAL_OK) 1993:Src/main.c **** { 1994:Src/main.c **** Error_Handler(); 1995:Src/main.c **** } ARM GAS /tmp/ccLSPxIe.s page 75 1996:Src/main.c **** sConfigOC.OCMode = TIM_OCMODE_PWM1; 1997:Src/main.c **** sConfigOC.Pulse = 4; 1998:Src/main.c **** sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH; 1999:Src/main.c **** sConfigOC.OCFastMode = TIM_OCFAST_DISABLE; 2000:Src/main.c **** if (HAL_TIM_PWM_ConfigChannel(&htim1, &sConfigOC, TIM_CHANNEL_1) != HAL_OK) 2001:Src/main.c **** { 2002:Src/main.c **** Error_Handler(); 2003:Src/main.c **** } 2004:Src/main.c **** sBreakDeadTimeConfig.OffStateRunMode = TIM_OSSR_DISABLE; 2005:Src/main.c **** sBreakDeadTimeConfig.OffStateIDLEMode = TIM_OSSI_DISABLE; 2006:Src/main.c **** sBreakDeadTimeConfig.LockLevel = TIM_LOCKLEVEL_OFF; 2007:Src/main.c **** sBreakDeadTimeConfig.DeadTime = 0; 2008:Src/main.c **** sBreakDeadTimeConfig.BreakState = TIM_BREAK_DISABLE; 2009:Src/main.c **** sBreakDeadTimeConfig.BreakPolarity = TIM_BREAKPOLARITY_HIGH; 2010:Src/main.c **** sBreakDeadTimeConfig.BreakFilter = 0; 2011:Src/main.c **** sBreakDeadTimeConfig.Break2State = TIM_BREAK2_DISABLE; 2012:Src/main.c **** sBreakDeadTimeConfig.Break2Polarity = TIM_BREAK2POLARITY_HIGH; 2013:Src/main.c **** sBreakDeadTimeConfig.Break2Filter = 0; 2014:Src/main.c **** sBreakDeadTimeConfig.AutomaticOutput = TIM_AUTOMATICOUTPUT_DISABLE; 2015:Src/main.c **** if (HAL_TIMEx_ConfigBreakDeadTime(&htim1, &sBreakDeadTimeConfig) != HAL_OK) 2016:Src/main.c **** { 2017:Src/main.c **** Error_Handler(); 2018:Src/main.c **** } 2019:Src/main.c **** /* USER CODE BEGIN TIM1_Init 2 */ 2020:Src/main.c **** 2021:Src/main.c **** /* USER CODE END TIM1_Init 2 */ 2022:Src/main.c **** HAL_TIM_MspPostInit(&htim1); 2023:Src/main.c **** 2024:Src/main.c **** } 2025:Src/main.c **** 2026:Src/main.c **** /** 2027:Src/main.c **** * @brief UART8 Initialization Function 2028:Src/main.c **** * @param None 2029:Src/main.c **** * @retval None 2030:Src/main.c **** */ 2031:Src/main.c **** static void MX_UART8_Init(void) 2032:Src/main.c **** { 2033:Src/main.c **** 2034:Src/main.c **** /* USER CODE BEGIN UART8_Init 0 */ 2035:Src/main.c **** 2036:Src/main.c **** /* USER CODE END UART8_Init 0 */ 2037:Src/main.c **** 2038:Src/main.c **** /* USER CODE BEGIN UART8_Init 1 */ 2039:Src/main.c **** 2040:Src/main.c **** /* USER CODE END UART8_Init 1 */ 2041:Src/main.c **** huart8.Instance = UART8; 2042:Src/main.c **** huart8.Init.BaudRate = 115200; 2043:Src/main.c **** huart8.Init.WordLength = UART_WORDLENGTH_8B; 2044:Src/main.c **** huart8.Init.StopBits = UART_STOPBITS_1; 2045:Src/main.c **** huart8.Init.Parity = UART_PARITY_NONE; 2046:Src/main.c **** huart8.Init.Mode = UART_MODE_TX_RX; 2047:Src/main.c **** huart8.Init.HwFlowCtl = UART_HWCONTROL_NONE; 2048:Src/main.c **** huart8.Init.OverSampling = UART_OVERSAMPLING_16; 2049:Src/main.c **** huart8.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE; 2050:Src/main.c **** huart8.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT; 2051:Src/main.c **** if (HAL_UART_Init(&huart8) != HAL_OK) 2052:Src/main.c **** { ARM GAS /tmp/ccLSPxIe.s page 76 2053:Src/main.c **** Error_Handler(); 2054:Src/main.c **** } 2055:Src/main.c **** /* USER CODE BEGIN UART8_Init 2 */ 2056:Src/main.c **** 2057:Src/main.c **** /* USER CODE END UART8_Init 2 */ 2058:Src/main.c **** 2059:Src/main.c **** } 2060:Src/main.c **** 2061:Src/main.c **** /** 2062:Src/main.c **** * @brief USART1 Initialization Function 2063:Src/main.c **** * @param None 2064:Src/main.c **** * @retval None 2065:Src/main.c **** */ 2066:Src/main.c **** static void MX_USART1_UART_Init(void) 2067:Src/main.c **** { 2068:Src/main.c **** 2069:Src/main.c **** /* USER CODE BEGIN USART1_Init 0 */ 2070:Src/main.c **** 2071:Src/main.c **** /* USER CODE END USART1_Init 0 */ 2072:Src/main.c **** 2073:Src/main.c **** LL_USART_InitTypeDef USART_InitStruct = {0}; 2074:Src/main.c **** 2075:Src/main.c **** LL_GPIO_InitTypeDef GPIO_InitStruct = {0}; 2076:Src/main.c **** RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; 2077:Src/main.c **** 2078:Src/main.c **** /** Initializes the peripherals clock 2079:Src/main.c **** */ 2080:Src/main.c **** PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USART1; 2081:Src/main.c **** PeriphClkInitStruct.Usart1ClockSelection = RCC_USART1CLKSOURCE_PCLK2; 2082:Src/main.c **** if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) 2083:Src/main.c **** { 2084:Src/main.c **** Error_Handler(); 2085:Src/main.c **** } 2086:Src/main.c **** 2087:Src/main.c **** /* Peripheral clock enable */ 2088:Src/main.c **** LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_USART1); 2089:Src/main.c **** 2090:Src/main.c **** LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_GPIOA); 2091:Src/main.c **** /**USART1 GPIO Configuration 2092:Src/main.c **** PA9 ------> USART1_TX 2093:Src/main.c **** PA10 ------> USART1_RX 2094:Src/main.c **** */ 2095:Src/main.c **** GPIO_InitStruct.Pin = LL_GPIO_PIN_9; 2096:Src/main.c **** GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE; 2097:Src/main.c **** GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH; 2098:Src/main.c **** GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; 2099:Src/main.c **** GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; 2100:Src/main.c **** GPIO_InitStruct.Alternate = LL_GPIO_AF_7; 2101:Src/main.c **** LL_GPIO_Init(GPIOA, &GPIO_InitStruct); 2102:Src/main.c **** 2103:Src/main.c **** GPIO_InitStruct.Pin = LL_GPIO_PIN_10; 2104:Src/main.c **** GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE; 2105:Src/main.c **** GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH; 2106:Src/main.c **** GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; 2107:Src/main.c **** GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; 2108:Src/main.c **** GPIO_InitStruct.Alternate = LL_GPIO_AF_7; 2109:Src/main.c **** LL_GPIO_Init(GPIOA, &GPIO_InitStruct); ARM GAS /tmp/ccLSPxIe.s page 77 2110:Src/main.c **** 2111:Src/main.c **** /* USART1 DMA Init */ 2112:Src/main.c **** 2113:Src/main.c **** /* USART1_TX Init */ 2114:Src/main.c **** LL_DMA_SetChannelSelection(DMA2, LL_DMA_STREAM_7, LL_DMA_CHANNEL_4); 2115:Src/main.c **** 2116:Src/main.c **** LL_DMA_SetDataTransferDirection(DMA2, LL_DMA_STREAM_7, LL_DMA_DIRECTION_MEMORY_TO_PERIPH); 2117:Src/main.c **** 2118:Src/main.c **** LL_DMA_SetStreamPriorityLevel(DMA2, LL_DMA_STREAM_7, LL_DMA_PRIORITY_VERYHIGH); 2119:Src/main.c **** 2120:Src/main.c **** LL_DMA_SetMode(DMA2, LL_DMA_STREAM_7, LL_DMA_MODE_NORMAL); 2121:Src/main.c **** 2122:Src/main.c **** LL_DMA_SetPeriphIncMode(DMA2, LL_DMA_STREAM_7, LL_DMA_PERIPH_NOINCREMENT); 2123:Src/main.c **** 2124:Src/main.c **** LL_DMA_SetMemoryIncMode(DMA2, LL_DMA_STREAM_7, LL_DMA_MEMORY_INCREMENT); 2125:Src/main.c **** 2126:Src/main.c **** LL_DMA_SetPeriphSize(DMA2, LL_DMA_STREAM_7, LL_DMA_PDATAALIGN_BYTE); 2127:Src/main.c **** 2128:Src/main.c **** LL_DMA_SetMemorySize(DMA2, LL_DMA_STREAM_7, LL_DMA_MDATAALIGN_BYTE); 2129:Src/main.c **** 2130:Src/main.c **** LL_DMA_DisableFifoMode(DMA2, LL_DMA_STREAM_7); 2131:Src/main.c **** 2132:Src/main.c **** /* USART1 interrupt Init */ 2133:Src/main.c **** NVIC_SetPriority(USART1_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(),0, 0)); 2134:Src/main.c **** NVIC_EnableIRQ(USART1_IRQn); 2135:Src/main.c **** 2136:Src/main.c **** /* USER CODE BEGIN USART1_Init 1 */ 2137:Src/main.c **** 2138:Src/main.c **** /* USER CODE END USART1_Init 1 */ 2139:Src/main.c **** USART_InitStruct.BaudRate = 115200; 2140:Src/main.c **** USART_InitStruct.DataWidth = LL_USART_DATAWIDTH_8B; 2141:Src/main.c **** USART_InitStruct.StopBits = LL_USART_STOPBITS_1; 2142:Src/main.c **** USART_InitStruct.Parity = LL_USART_PARITY_NONE; 2143:Src/main.c **** USART_InitStruct.TransferDirection = LL_USART_DIRECTION_TX_RX; 2144:Src/main.c **** USART_InitStruct.HardwareFlowControl = LL_USART_HWCONTROL_NONE; 2145:Src/main.c **** USART_InitStruct.OverSampling = LL_USART_OVERSAMPLING_16; 2146:Src/main.c **** LL_USART_Init(USART1, &USART_InitStruct); 2147:Src/main.c **** LL_USART_ConfigAsyncMode(USART1); 2148:Src/main.c **** LL_USART_Enable(USART1); 2149:Src/main.c **** /* USER CODE BEGIN USART1_Init 2 */ 2150:Src/main.c **** 2151:Src/main.c **** /* USER CODE END USART1_Init 2 */ 2152:Src/main.c **** 2153:Src/main.c **** } 2154:Src/main.c **** 2155:Src/main.c **** /** 2156:Src/main.c **** * Enable DMA controller clock 2157:Src/main.c **** */ 2158:Src/main.c **** static void MX_DMA_Init(void) 2159:Src/main.c **** { 144 .loc 1 2159 1 is_stmt 1 view -0 145 .cfi_startproc 146 @ args = 0, pretend = 0, frame = 8 147 @ frame_needed = 0, uses_anonymous_args = 0 148 0000 00B5 push {lr} 149 .LCFI1: 150 .cfi_def_cfa_offset 4 ARM GAS /tmp/ccLSPxIe.s page 78 151 .cfi_offset 14, -4 152 0002 83B0 sub sp, sp, #12 153 .LCFI2: 154 .cfi_def_cfa_offset 16 2160:Src/main.c **** 2161:Src/main.c **** /* Init with LL driver */ 2162:Src/main.c **** /* DMA controller clock enable */ 2163:Src/main.c **** LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_DMA2); 155 .loc 1 2163 3 view .LVU37 156 .LVL8: 157 .LBB355: 158 .LBI355: 159 .file 3 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h" 1:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** 2:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** ****************************************************************************** 3:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @file stm32f7xx_ll_bus.h 4:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @author MCD Application Team 5:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Header file of BUS LL module. 6:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 7:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** @verbatim 8:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** ##### RCC Limitations ##### 9:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** ============================================================================== 10:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** [..] 11:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** A delay between an RCC peripheral clock enable and the effective peripheral 12:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** enabling should be taken into account in order to manage the peripheral read/write 13:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** from/to registers. 14:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (+) This delay depends on the peripheral mapping. 15:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (++) AHB & APB peripherals, 1 dummy read is necessary 16:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 17:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** [..] 18:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** Workarounds: 19:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (#) For AHB & APB peripherals, a dummy read to the peripheral register has been 20:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** inserted in each LL_{BUS}_GRP{x}_EnableClock() function. 21:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 22:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** @endverbatim 23:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** ****************************************************************************** 24:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @attention 25:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * 26:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * Copyright (c) 2017 STMicroelectronics. 27:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * All rights reserved. 28:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * 29:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * This software is licensed under terms that can be found in the LICENSE file in 30:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * the root directory of this software component. 31:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * If no LICENSE file comes with this software, it is provided AS-IS. 32:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** ****************************************************************************** 33:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ 34:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 35:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Define to prevent recursive inclusion -------------------------------------*/ 36:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #ifndef __STM32F7xx_LL_BUS_H 37:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define __STM32F7xx_LL_BUS_H 38:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 39:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #ifdef __cplusplus 40:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** extern "C" { 41:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif 42:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 43:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Includes ------------------------------------------------------------------*/ 44:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #include "stm32f7xx.h" ARM GAS /tmp/ccLSPxIe.s page 79 45:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 46:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** @addtogroup STM32F7xx_LL_Driver 47:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @{ 48:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ 49:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 50:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(RCC) 51:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 52:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** @defgroup BUS_LL BUS 53:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @{ 54:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ 55:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 56:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Private types -------------------------------------------------------------*/ 57:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Private variables ---------------------------------------------------------*/ 58:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Private constants ---------------------------------------------------------*/ 59:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Private macros ------------------------------------------------------------*/ 60:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Exported types ------------------------------------------------------------*/ 61:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Exported constants --------------------------------------------------------*/ 62:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** @defgroup BUS_LL_Exported_Constants BUS Exported Constants 63:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @{ 64:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ 65:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 66:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** @defgroup BUS_LL_EC_AHB1_GRP1_PERIPH AHB1 GRP1 PERIPH 67:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @{ 68:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ 69:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_ALL 0xFFFFFFFFU 70:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_GPIOA RCC_AHB1ENR_GPIOAEN 71:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_GPIOB RCC_AHB1ENR_GPIOBEN 72:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_GPIOC RCC_AHB1ENR_GPIOCEN 73:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_GPIOD RCC_AHB1ENR_GPIODEN 74:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_GPIOE RCC_AHB1ENR_GPIOEEN 75:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_GPIOF RCC_AHB1ENR_GPIOFEN 76:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_GPIOG RCC_AHB1ENR_GPIOGEN 77:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_GPIOH RCC_AHB1ENR_GPIOHEN 78:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_GPIOI RCC_AHB1ENR_GPIOIEN 79:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(GPIOJ) 80:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_GPIOJ RCC_AHB1ENR_GPIOJEN 81:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* GPIOJ */ 82:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(GPIOK) 83:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_GPIOK RCC_AHB1ENR_GPIOKEN 84:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* GPIOK */ 85:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_CRC RCC_AHB1ENR_CRCEN 86:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_BKPSRAM RCC_AHB1ENR_BKPSRAMEN 87:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_DTCMRAM RCC_AHB1ENR_DTCMRAMEN 88:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_DMA1 RCC_AHB1ENR_DMA1EN 89:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_DMA2 RCC_AHB1ENR_DMA2EN 90:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(DMA2D) 91:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_DMA2D RCC_AHB1ENR_DMA2DEN 92:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* DMA2D */ 93:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(ETH) 94:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_ETHMAC RCC_AHB1ENR_ETHMACEN 95:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_ETHMACTX RCC_AHB1ENR_ETHMACTXEN 96:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_ETHMACRX RCC_AHB1ENR_ETHMACRXEN 97:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_ETHMACPTP RCC_AHB1ENR_ETHMACPTPEN 98:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* ETH */ 99:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_OTGHS RCC_AHB1ENR_OTGHSEN 100:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_OTGHSULPI RCC_AHB1ENR_OTGHSULPIEN 101:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_AXI RCC_AHB1LPENR_AXILPEN ARM GAS /tmp/ccLSPxIe.s page 80 102:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_FLITF RCC_AHB1LPENR_FLITFLPEN 103:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_SRAM1 RCC_AHB1LPENR_SRAM1LPEN 104:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_SRAM2 RCC_AHB1LPENR_SRAM2LPEN 105:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** 106:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @} 107:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ 108:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 109:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** @defgroup BUS_LL_EC_AHB2_GRP1_PERIPH AHB2 GRP1 PERIPH 110:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @{ 111:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ 112:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB2_GRP1_PERIPH_ALL 0xFFFFFFFFU 113:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(DCMI) 114:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB2_GRP1_PERIPH_DCMI RCC_AHB2ENR_DCMIEN 115:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* DCMI */ 116:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(JPEG) 117:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB2_GRP1_PERIPH_JPEG RCC_AHB2ENR_JPEGEN 118:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* JPEG */ 119:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(CRYP) 120:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB2_GRP1_PERIPH_CRYP RCC_AHB2ENR_CRYPEN 121:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* CRYP */ 122:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(AES) 123:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB2_GRP1_PERIPH_AES RCC_AHB2ENR_AESEN 124:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* AES */ 125:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(HASH) 126:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB2_GRP1_PERIPH_HASH RCC_AHB2ENR_HASHEN 127:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* HASH */ 128:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB2_GRP1_PERIPH_RNG RCC_AHB2ENR_RNGEN 129:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB2_GRP1_PERIPH_OTGFS RCC_AHB2ENR_OTGFSEN 130:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** 131:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @} 132:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ 133:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 134:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** @defgroup BUS_LL_EC_AHB3_GRP1_PERIPH AHB3 GRP1 PERIPH 135:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @{ 136:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ 137:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB3_GRP1_PERIPH_ALL 0xFFFFFFFFU 138:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB3_GRP1_PERIPH_FMC RCC_AHB3ENR_FMCEN 139:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB3_GRP1_PERIPH_QSPI RCC_AHB3ENR_QSPIEN 140:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** 141:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @} 142:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ 143:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 144:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** @defgroup BUS_LL_EC_APB1_GRP1_PERIPH APB1 GRP1 PERIPH 145:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @{ 146:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ 147:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_ALL 0xFFFFFFFFU 148:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_TIM2 RCC_APB1ENR_TIM2EN 149:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_TIM3 RCC_APB1ENR_TIM3EN 150:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_TIM4 RCC_APB1ENR_TIM4EN 151:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_TIM5 RCC_APB1ENR_TIM5EN 152:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_TIM6 RCC_APB1ENR_TIM6EN 153:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_TIM7 RCC_APB1ENR_TIM7EN 154:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_TIM12 RCC_APB1ENR_TIM12EN 155:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_TIM13 RCC_APB1ENR_TIM13EN 156:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_TIM14 RCC_APB1ENR_TIM14EN 157:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_LPTIM1 RCC_APB1ENR_LPTIM1EN 158:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_WWDG RCC_APB1ENR_WWDGEN ARM GAS /tmp/ccLSPxIe.s page 81 159:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_SPI2 RCC_APB1ENR_SPI2EN 160:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_SPI3 RCC_APB1ENR_SPI3EN 161:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(SPDIFRX) 162:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_SPDIFRX RCC_APB1ENR_SPDIFRXEN 163:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* SPDIFRX */ 164:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_USART2 RCC_APB1ENR_USART2EN 165:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_USART3 RCC_APB1ENR_USART3EN 166:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_UART4 RCC_APB1ENR_UART4EN 167:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_UART5 RCC_APB1ENR_UART5EN 168:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_I2C1 RCC_APB1ENR_I2C1EN 169:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_I2C2 RCC_APB1ENR_I2C2EN 170:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_I2C3 RCC_APB1ENR_I2C3EN 171:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(I2C4) 172:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_I2C4 RCC_APB1ENR_I2C4EN 173:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* I2C4 */ 174:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_CAN1 RCC_APB1ENR_CAN1EN 175:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(CAN2) 176:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_CAN2 RCC_APB1ENR_CAN2EN 177:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* CAN2 */ 178:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(CAN3) 179:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_CAN3 RCC_APB1ENR_CAN3EN 180:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* CAN3 */ 181:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(CEC) 182:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_CEC RCC_APB1ENR_CECEN 183:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* CEC */ 184:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_PWR RCC_APB1ENR_PWREN 185:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_DAC1 RCC_APB1ENR_DACEN 186:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_UART7 RCC_APB1ENR_UART7EN 187:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_UART8 RCC_APB1ENR_UART8EN 188:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(RCC_APB1ENR_RTCEN) 189:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_RTCAPB RCC_APB1ENR_RTCEN 190:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* RCC_APB1ENR_RTCEN */ 191:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** 192:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @} 193:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ 194:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 195:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** @defgroup BUS_LL_EC_APB2_GRP1_PERIPH APB2 GRP1 PERIPH 196:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @{ 197:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ 198:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_ALL 0xFFFFFFFFU 199:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_TIM1 RCC_APB2ENR_TIM1EN 200:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_TIM8 RCC_APB2ENR_TIM8EN 201:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_USART1 RCC_APB2ENR_USART1EN 202:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_USART6 RCC_APB2ENR_USART6EN 203:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_ADC1 RCC_APB2ENR_ADC1EN 204:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_ADC2 RCC_APB2ENR_ADC2EN 205:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_ADC3 RCC_APB2ENR_ADC3EN 206:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_SDMMC1 RCC_APB2ENR_SDMMC1EN 207:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(SDMMC2) 208:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_SDMMC2 RCC_APB2ENR_SDMMC2EN 209:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* SDMMC2 */ 210:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_SPI1 RCC_APB2ENR_SPI1EN 211:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_SPI4 RCC_APB2ENR_SPI4EN 212:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_SYSCFG RCC_APB2ENR_SYSCFGEN 213:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_TIM9 RCC_APB2ENR_TIM9EN 214:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_TIM10 RCC_APB2ENR_TIM10EN 215:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_TIM11 RCC_APB2ENR_TIM11EN ARM GAS /tmp/ccLSPxIe.s page 82 216:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_SPI5 RCC_APB2ENR_SPI5EN 217:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(SPI6) 218:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_SPI6 RCC_APB2ENR_SPI6EN 219:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* SPI6 */ 220:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_SAI1 RCC_APB2ENR_SAI1EN 221:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_SAI2 RCC_APB2ENR_SAI2EN 222:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(LTDC) 223:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_LTDC RCC_APB2ENR_LTDCEN 224:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* LTDC */ 225:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(DSI) 226:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_DSI RCC_APB2ENR_DSIEN 227:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* DSI */ 228:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(DFSDM1_Channel0) 229:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_DFSDM1 RCC_APB2ENR_DFSDM1EN 230:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* DFSDM1_Channel0 */ 231:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(MDIOS) 232:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_MDIO RCC_APB2ENR_MDIOEN 233:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* MDIOS */ 234:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(USB_HS_PHYC) 235:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_OTGPHYC RCC_APB2ENR_OTGPHYCEN 236:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* USB_HS_PHYC */ 237:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_ADC RCC_APB2RSTR_ADCRST 238:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** 239:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @} 240:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ 241:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 242:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** 243:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @} 244:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ 245:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 246:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Exported macro ------------------------------------------------------------*/ 247:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Exported functions --------------------------------------------------------*/ 248:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** @defgroup BUS_LL_Exported_Functions BUS Exported Functions 249:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @{ 250:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ 251:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 252:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** @defgroup BUS_LL_EF_AHB1 AHB1 253:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @{ 254:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ 255:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 256:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** 257:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Enable AHB1 peripherals clock. 258:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll AHB1ENR GPIOAEN LL_AHB1_GRP1_EnableClock\n 259:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOBEN LL_AHB1_GRP1_EnableClock\n 260:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOCEN LL_AHB1_GRP1_EnableClock\n 261:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIODEN LL_AHB1_GRP1_EnableClock\n 262:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOEEN LL_AHB1_GRP1_EnableClock\n 263:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOFEN LL_AHB1_GRP1_EnableClock\n 264:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOGEN LL_AHB1_GRP1_EnableClock\n 265:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOHEN LL_AHB1_GRP1_EnableClock\n 266:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOIEN LL_AHB1_GRP1_EnableClock\n 267:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOJEN LL_AHB1_GRP1_EnableClock\n 268:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOKEN LL_AHB1_GRP1_EnableClock\n 269:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR CRCEN LL_AHB1_GRP1_EnableClock\n 270:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR BKPSRAMEN LL_AHB1_GRP1_EnableClock\n 271:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR DTCMRAMEN LL_AHB1_GRP1_EnableClock\n 272:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR DMA1EN LL_AHB1_GRP1_EnableClock\n ARM GAS /tmp/ccLSPxIe.s page 83 273:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR DMA2EN LL_AHB1_GRP1_EnableClock\n 274:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR DMA2DEN LL_AHB1_GRP1_EnableClock\n 275:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR ETHMACEN LL_AHB1_GRP1_EnableClock\n 276:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR ETHMACTXEN LL_AHB1_GRP1_EnableClock\n 277:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR ETHMACRXEN LL_AHB1_GRP1_EnableClock\n 278:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR ETHMACPTPEN LL_AHB1_GRP1_EnableClock\n 279:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR OTGHSEN LL_AHB1_GRP1_EnableClock\n 280:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR OTGHSULPIEN LL_AHB1_GRP1_EnableClock 281:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: 282:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA 283:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB 284:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC 285:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD 286:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE 287:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF 288:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG 289:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH 290:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI 291:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*) 292:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*) 293:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRC 294:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM 295:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DTCMRAM 296:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 298:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*) 299:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*) 300:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*) 301:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*) 302:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACPTP (*) 303:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS 304:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHSULPI 305:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * 306:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. 307:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval None 308:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ 309:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs) 160 .loc 3 309 22 view .LVU38 161 .LBB356: 310:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { 311:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __IO uint32_t tmpreg; 162 .loc 3 311 3 view .LVU39 312:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** SET_BIT(RCC->AHB1ENR, Periphs); 163 .loc 3 312 3 view .LVU40 164 0004 0D4B ldr r3, .L10 165 0006 1A6B ldr r2, [r3, #48] 166 0008 42F48002 orr r2, r2, #4194304 167 000c 1A63 str r2, [r3, #48] 313:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Delay after an RCC peripheral clock enabling */ 314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** tmpreg = READ_BIT(RCC->AHB1ENR, Periphs); 168 .loc 3 314 3 view .LVU41 169 .loc 3 314 12 is_stmt 0 view .LVU42 170 000e 1B6B ldr r3, [r3, #48] 171 0010 03F48003 and r3, r3, #4194304 172 .loc 3 314 10 view .LVU43 173 0014 0193 str r3, [sp, #4] 315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; ARM GAS /tmp/ccLSPxIe.s page 84 174 .loc 3 315 3 is_stmt 1 view .LVU44 175 0016 019B ldr r3, [sp, #4] 176 .LVL9: 177 .loc 3 315 3 is_stmt 0 view .LVU45 178 .LBE356: 179 .LBE355: 2164:Src/main.c **** 2165:Src/main.c **** /* DMA interrupt init */ 2166:Src/main.c **** /* DMA2_Stream7_IRQn interrupt configuration */ 2167:Src/main.c **** NVIC_SetPriority(DMA2_Stream7_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(),0, 0)); 180 .loc 1 2167 3 is_stmt 1 view .LVU46 181 .LBB357: 182 .LBI357: 1884:Drivers/CMSIS/Include/core_cm7.h **** { 183 .loc 2 1884 26 view .LVU47 184 .LBB358: 1886:Drivers/CMSIS/Include/core_cm7.h **** } 185 .loc 2 1886 3 view .LVU48 1886:Drivers/CMSIS/Include/core_cm7.h **** } 186 .loc 2 1886 26 is_stmt 0 view .LVU49 187 0018 094B ldr r3, .L10+4 188 001a D868 ldr r0, [r3, #12] 189 .LBE358: 190 .LBE357: 191 .loc 1 2167 3 discriminator 1 view .LVU50 192 001c 0022 movs r2, #0 193 001e 1146 mov r1, r2 194 0020 C0F30220 ubfx r0, r0, #8, #3 195 0024 FFF7FEFF bl NVIC_EncodePriority 196 .LVL10: 197 .LBB359: 198 .LBI359: 2024:Drivers/CMSIS/Include/core_cm7.h **** { 199 .loc 2 2024 22 is_stmt 1 view .LVU51 200 .LBB360: 2026:Drivers/CMSIS/Include/core_cm7.h **** { 201 .loc 2 2026 3 view .LVU52 2028:Drivers/CMSIS/Include/core_cm7.h **** } 202 .loc 2 2028 5 view .LVU53 2028:Drivers/CMSIS/Include/core_cm7.h **** } 203 .loc 2 2028 49 is_stmt 0 view .LVU54 204 0028 0001 lsls r0, r0, #4 205 .LVL11: 2028:Drivers/CMSIS/Include/core_cm7.h **** } 206 .loc 2 2028 49 view .LVU55 207 002a C0B2 uxtb r0, r0 2028:Drivers/CMSIS/Include/core_cm7.h **** } 208 .loc 2 2028 47 view .LVU56 209 002c 054B ldr r3, .L10+8 210 002e 83F84603 strb r0, [r3, #838] 211 .LVL12: 2028:Drivers/CMSIS/Include/core_cm7.h **** } 212 .loc 2 2028 47 view .LVU57 213 .LBE360: 214 .LBE359: 2168:Src/main.c **** NVIC_EnableIRQ(DMA2_Stream7_IRQn); 215 .loc 1 2168 3 is_stmt 1 view .LVU58 ARM GAS /tmp/ccLSPxIe.s page 85 216 .LBB361: 217 .LBI361: 1896:Drivers/CMSIS/Include/core_cm7.h **** { 218 .loc 2 1896 22 view .LVU59 219 .LBB362: 1898:Drivers/CMSIS/Include/core_cm7.h **** { 220 .loc 2 1898 3 view .LVU60 1900:Drivers/CMSIS/Include/core_cm7.h **** } 221 .loc 2 1900 5 view .LVU61 1900:Drivers/CMSIS/Include/core_cm7.h **** } 222 .loc 2 1900 43 is_stmt 0 view .LVU62 223 0032 4022 movs r2, #64 224 0034 9A60 str r2, [r3, #8] 225 .LVL13: 1900:Drivers/CMSIS/Include/core_cm7.h **** } 226 .loc 2 1900 43 view .LVU63 227 .LBE362: 228 .LBE361: 2169:Src/main.c **** 2170:Src/main.c **** } 229 .loc 1 2170 1 view .LVU64 230 0036 03B0 add sp, sp, #12 231 .LCFI3: 232 .cfi_def_cfa_offset 4 233 @ sp needed 234 0038 5DF804FB ldr pc, [sp], #4 235 .L11: 236 .align 2 237 .L10: 238 003c 00380240 .word 1073887232 239 0040 00ED00E0 .word -536810240 240 0044 00E100E0 .word -536813312 241 .cfi_endproc 242 .LFE1206: 244 .section .text.Decode_task,"ax",%progbits 245 .align 1 246 .syntax unified 247 .thumb 248 .thumb_func 250 Decode_task: 251 .LVL14: 252 .LFB1210: 2171:Src/main.c **** 2172:Src/main.c **** /** 2173:Src/main.c **** * @brief GPIO Initialization Function 2174:Src/main.c **** * @param None 2175:Src/main.c **** * @retval None 2176:Src/main.c **** */ 2177:Src/main.c **** static void MX_GPIO_Init(void) 2178:Src/main.c **** { 2179:Src/main.c **** GPIO_InitTypeDef GPIO_InitStruct = {0}; 2180:Src/main.c **** /* USER CODE BEGIN MX_GPIO_Init_1 */ 2181:Src/main.c **** /* USER CODE END MX_GPIO_Init_1 */ 2182:Src/main.c **** 2183:Src/main.c **** /* GPIO Ports Clock Enable */ 2184:Src/main.c **** __HAL_RCC_GPIOF_CLK_ENABLE(); 2185:Src/main.c **** __HAL_RCC_GPIOH_CLK_ENABLE(); ARM GAS /tmp/ccLSPxIe.s page 86 2186:Src/main.c **** __HAL_RCC_GPIOC_CLK_ENABLE(); 2187:Src/main.c **** __HAL_RCC_GPIOA_CLK_ENABLE(); 2188:Src/main.c **** __HAL_RCC_GPIOB_CLK_ENABLE(); 2189:Src/main.c **** __HAL_RCC_GPIOE_CLK_ENABLE(); 2190:Src/main.c **** __HAL_RCC_GPIOD_CLK_ENABLE(); 2191:Src/main.c **** __HAL_RCC_GPIOG_CLK_ENABLE(); 2192:Src/main.c **** 2193:Src/main.c **** /*Configure GPIO pin Output Level */ 2194:Src/main.c **** HAL_GPIO_WritePin(GPIOF, ADC_MPD2_CS_Pin|SPI5_CNV_Pin|ADC_ThrLD2_CS_Pin, GPIO_PIN_RESET); 2195:Src/main.c **** 2196:Src/main.c **** /*Configure GPIO pin Output Level */ 2197:Src/main.c **** HAL_GPIO_WritePin(GPIOC, EN_5V2_Pin|EN_5V1_Pin|LD2_EN_Pin|TEC2_PD_Pin, GPIO_PIN_RESET); 2198:Src/main.c **** HAL_GPIO_WritePin(AD9102_RESET_GPIO_Port, AD9102_RESET_Pin, GPIO_PIN_SET); 2199:Src/main.c **** 2200:Src/main.c **** /*Configure GPIO pin Output Level */ 2201:Src/main.c **** HAL_GPIO_WritePin(GPIOA, TECEN1_Pin|TECEN2_Pin|REF2_ON_Pin|DAC_LD2_CS_Pin, GPIO_PIN_RESET); 2202:Src/main.c **** 2203:Src/main.c **** /*Configure GPIO pin Output Level */ 2204:Src/main.c **** HAL_GPIO_WritePin(DAC_TEC2_CS_GPIO_Port, DAC_TEC2_CS_Pin, GPIO_PIN_SET); 2205:Src/main.c **** 2206:Src/main.c **** /*Configure GPIO pin Output Level */ 2207:Src/main.c **** HAL_GPIO_WritePin(GPIOE, ADC_MPD1_CS_Pin|ADC_ThrLD1_CS_Pin, GPIO_PIN_RESET); 2208:Src/main.c **** HAL_GPIO_WritePin(GPIOE, DS1809_UC_Pin|DS1809_DC_Pin, GPIO_PIN_SET); 2209:Src/main.c **** 2210:Src/main.c **** /*Configure GPIO pin Output Level */ 2211:Src/main.c **** HAL_GPIO_WritePin(SPI4_CNV_GPIO_Port, SPI4_CNV_Pin, GPIO_PIN_SET); 2212:Src/main.c **** 2213:Src/main.c **** /*Configure GPIO pin Output Level */ 2214:Src/main.c **** HAL_GPIO_WritePin(GPIOB, REF0_EN_Pin|TEC1_PD_Pin|OUT_6_Pin 2215:Src/main.c **** |OUT_7_Pin|OUT_8_Pin|OUT_9_Pin, GPIO_PIN_RESET); 2216:Src/main.c **** 2217:Src/main.c **** /*Configure GPIO pin Output Level */ 2218:Src/main.c **** HAL_GPIO_WritePin(DAC_TEC1_CS_GPIO_Port, DAC_TEC1_CS_Pin, GPIO_PIN_SET); 2219:Src/main.c **** HAL_GPIO_WritePin(AD9102_CS_GPIO_Port, AD9102_CS_Pin, GPIO_PIN_SET); 2220:Src/main.c **** 2221:Src/main.c **** /*Configure GPIO pin Output Level */ 2222:Src/main.c **** HAL_GPIO_WritePin(GPIOD, LD1_EN_Pin|TEST_01_Pin|GPIO_PIN_7, GPIO_PIN_RESET); 2223:Src/main.c **** HAL_GPIO_WritePin(AD9102_TRIG_GPIO_Port, AD9102_TRIG_Pin, GPIO_PIN_SET); 2224:Src/main.c **** HAL_GPIO_WritePin(AD9833_CS_GPIO_Port, AD9833_CS_Pin, GPIO_PIN_SET); 2225:Src/main.c **** 2226:Src/main.c **** /*Configure GPIO pin Output Level */ 2227:Src/main.c **** HAL_GPIO_WritePin(GPIOG, GPIO_PIN_9|OUT_0_Pin|OUT_1_Pin|OUT_2_Pin 2228:Src/main.c **** |OUT_3_Pin|OUT_4_Pin|OUT_5_Pin, GPIO_PIN_RESET); 2229:Src/main.c **** 2230:Src/main.c **** /*Configure GPIO pins : INP_0_Pin INP_1_Pin */ 2231:Src/main.c **** GPIO_InitStruct.Pin = INP_0_Pin|INP_1_Pin; 2232:Src/main.c **** GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 2233:Src/main.c **** GPIO_InitStruct.Pull = GPIO_PULLUP; 2234:Src/main.c **** HAL_GPIO_Init(GPIOF, &GPIO_InitStruct); 2235:Src/main.c **** 2236:Src/main.c **** /*Configure GPIO pins : ADC_MPD2_CS_Pin SPI5_CNV_Pin ADC_ThrLD2_CS_Pin */ 2237:Src/main.c **** GPIO_InitStruct.Pin = ADC_MPD2_CS_Pin|SPI5_CNV_Pin|ADC_ThrLD2_CS_Pin; 2238:Src/main.c **** GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 2239:Src/main.c **** GPIO_InitStruct.Pull = GPIO_NOPULL; 2240:Src/main.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 2241:Src/main.c **** HAL_GPIO_Init(GPIOF, &GPIO_InitStruct); 2242:Src/main.c **** ARM GAS /tmp/ccLSPxIe.s page 87 2243:Src/main.c **** /*Configure GPIO pins : EN_5V2_Pin LD2_EN_Pin TEC2_PD_Pin AD9102_RESET_Pin */ 2244:Src/main.c **** GPIO_InitStruct.Pin = EN_5V2_Pin|LD2_EN_Pin|TEC2_PD_Pin|AD9102_RESET_Pin; 2245:Src/main.c **** GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 2246:Src/main.c **** GPIO_InitStruct.Pull = GPIO_NOPULL; 2247:Src/main.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 2248:Src/main.c **** HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); 2249:Src/main.c **** 2250:Src/main.c **** /*Configure GPIO pin : EN_5V1_Pin */ 2251:Src/main.c **** GPIO_InitStruct.Pin = EN_5V1_Pin; 2252:Src/main.c **** GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 2253:Src/main.c **** GPIO_InitStruct.Pull = GPIO_NOPULL; 2254:Src/main.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; 2255:Src/main.c **** HAL_GPIO_Init(EN_5V1_GPIO_Port, &GPIO_InitStruct); 2256:Src/main.c **** 2257:Src/main.c **** /*Configure GPIO pins : TECEN1_Pin TECEN2_Pin REF2_ON_Pin DAC_LD2_CS_Pin */ 2258:Src/main.c **** GPIO_InitStruct.Pin = TECEN1_Pin|TECEN2_Pin|REF2_ON_Pin|DAC_LD2_CS_Pin; 2259:Src/main.c **** GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 2260:Src/main.c **** GPIO_InitStruct.Pull = GPIO_NOPULL; 2261:Src/main.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 2262:Src/main.c **** HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 2263:Src/main.c **** 2264:Src/main.c **** /*Configure GPIO pins : TEC2_FLAG1_Pin TEC2_FLAG2_Pin TEC1_FLAG1_Pin TEC1_FLAG2_Pin */ 2265:Src/main.c **** GPIO_InitStruct.Pin = TEC2_FLAG1_Pin|TEC2_FLAG2_Pin|TEC1_FLAG1_Pin|TEC1_FLAG2_Pin; 2266:Src/main.c **** GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 2267:Src/main.c **** GPIO_InitStruct.Pull = GPIO_NOPULL; 2268:Src/main.c **** HAL_GPIO_Init(GPIOF, &GPIO_InitStruct); 2269:Src/main.c **** 2270:Src/main.c **** /*Configure GPIO pins : ADC_MPD1_CS_Pin ADC_ThrLD1_CS_Pin DAC_TEC2_CS_Pin */ 2271:Src/main.c **** GPIO_InitStruct.Pin = ADC_MPD1_CS_Pin|ADC_ThrLD1_CS_Pin|DAC_TEC2_CS_Pin; 2272:Src/main.c **** GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 2273:Src/main.c **** GPIO_InitStruct.Pull = GPIO_NOPULL; 2274:Src/main.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 2275:Src/main.c **** HAL_GPIO_Init(GPIOE, &GPIO_InitStruct); 2276:Src/main.c **** 2277:Src/main.c **** /*Configure GPIO pins : DS1809_UC_Pin DS1809_DC_Pin */ 2278:Src/main.c **** GPIO_InitStruct.Pin = DS1809_UC_Pin|DS1809_DC_Pin; 2279:Src/main.c **** GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_OD; 2280:Src/main.c **** GPIO_InitStruct.Pull = GPIO_NOPULL; 2281:Src/main.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 2282:Src/main.c **** HAL_GPIO_Init(GPIOE, &GPIO_InitStruct); 2283:Src/main.c **** 2284:Src/main.c **** /*Configure GPIO pin : SPI4_CNV_Pin */ 2285:Src/main.c **** GPIO_InitStruct.Pin = SPI4_CNV_Pin; 2286:Src/main.c **** GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 2287:Src/main.c **** GPIO_InitStruct.Pull = GPIO_NOPULL; 2288:Src/main.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; 2289:Src/main.c **** HAL_GPIO_Init(SPI4_CNV_GPIO_Port, &GPIO_InitStruct); 2290:Src/main.c **** 2291:Src/main.c **** /*Configure GPIO pins : REF0_EN_Pin TEC1_PD_Pin AD9102_CS_Pin 2292:Src/main.c **** OUT_6_Pin OUT_7_Pin OUT_8_Pin OUT_9_Pin */ 2293:Src/main.c **** GPIO_InitStruct.Pin = REF0_EN_Pin|TEC1_PD_Pin|AD9102_CS_Pin 2294:Src/main.c **** |OUT_6_Pin|OUT_7_Pin|OUT_8_Pin|OUT_9_Pin; 2295:Src/main.c **** GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 2296:Src/main.c **** GPIO_InitStruct.Pull = GPIO_NOPULL; 2297:Src/main.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 2298:Src/main.c **** HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 2299:Src/main.c **** ARM GAS /tmp/ccLSPxIe.s page 88 2300:Src/main.c **** /*Configure GPIO pins : LD1_EN_Pin TEST_01_Pin PD7 AD9102_TRIG_Pin DAC_TEC1_CS_Pin AD9833_CS_Pin 2301:Src/main.c **** GPIO_InitStruct.Pin = LD1_EN_Pin|TEST_01_Pin|GPIO_PIN_7|AD9102_TRIG_Pin|DAC_TEC1_CS_Pin|AD9833_CS 2302:Src/main.c **** GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 2303:Src/main.c **** GPIO_InitStruct.Pull = GPIO_NOPULL; 2304:Src/main.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 2305:Src/main.c **** HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); 2306:Src/main.c **** 2307:Src/main.c **** /*Configure GPIO pin : USB_FLAG_Pin */ 2308:Src/main.c **** GPIO_InitStruct.Pin = USB_FLAG_Pin; 2309:Src/main.c **** GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 2310:Src/main.c **** GPIO_InitStruct.Pull = GPIO_NOPULL; 2311:Src/main.c **** HAL_GPIO_Init(USB_FLAG_GPIO_Port, &GPIO_InitStruct); 2312:Src/main.c **** 2313:Src/main.c **** /*Configure GPIO pin : SDMMC1_EN_Pin */ 2314:Src/main.c **** GPIO_InitStruct.Pin = SDMMC1_EN_Pin; 2315:Src/main.c **** GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 2316:Src/main.c **** GPIO_InitStruct.Pull = GPIO_NOPULL; 2317:Src/main.c **** HAL_GPIO_Init(SDMMC1_EN_GPIO_Port, &GPIO_InitStruct); 2318:Src/main.c **** 2319:Src/main.c **** /*Configure GPIO pins : PG9 OUT_0_Pin OUT_1_Pin OUT_2_Pin 2320:Src/main.c **** OUT_3_Pin OUT_4_Pin OUT_5_Pin */ 2321:Src/main.c **** GPIO_InitStruct.Pin = GPIO_PIN_9|OUT_0_Pin|OUT_1_Pin|OUT_2_Pin 2322:Src/main.c **** |OUT_3_Pin|OUT_4_Pin|OUT_5_Pin; 2323:Src/main.c **** GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 2324:Src/main.c **** GPIO_InitStruct.Pull = GPIO_NOPULL; 2325:Src/main.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 2326:Src/main.c **** HAL_GPIO_Init(GPIOG, &GPIO_InitStruct); 2327:Src/main.c **** 2328:Src/main.c **** /* USER CODE BEGIN MX_GPIO_Init_2 */ 2329:Src/main.c **** /* USER CODE END MX_GPIO_Init_2 */ 2330:Src/main.c **** } 2331:Src/main.c **** 2332:Src/main.c **** /* USER CODE BEGIN 4 */ 2333:Src/main.c **** 2334:Src/main.c **** //void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart) { 2335:Src/main.c **** 2336:Src/main.c **** // UART_transmission_request = NO_MESS; 2337:Src/main.c **** 2338:Src/main.c **** //} 2339:Src/main.c **** 2340:Src/main.c **** static void Init_params(void) 2341:Src/main.c **** { 2342:Src/main.c **** TO6 = 0; 2343:Src/main.c **** TO7 = 0; 2344:Src/main.c **** TO7_before = 0; 2345:Src/main.c **** TO6_before = 0; 2346:Src/main.c **** TO6_uart = 0; 2347:Src/main.c **** flg_tmt = 0; 2348:Src/main.c **** UART_rec_incr = 0; 2349:Src/main.c **** fgoto = 0; 2350:Src/main.c **** sizeoffile = 0; 2351:Src/main.c **** u_tx_flg = 0; 2352:Src/main.c **** u_rx_flg = 0; 2353:Src/main.c **** //State_Data[0]=0; 2354:Src/main.c **** //State_Data[1]=0;//All OK! 2355:Src/main.c **** for (uint16_t i=0; iWORK_EN = ((uint8_t)((*temp2)>>0))&0x01; 2510:Src/main.c **** Curr_setup->U5V1_EN = ((uint8_t)((*temp2)>>1))&0x01; 2511:Src/main.c **** Curr_setup->U5V2_EN = ((uint8_t)((*temp2)>>2))&0x01; 2512:Src/main.c **** Curr_setup->LD1_EN = ((uint8_t)((*temp2)>>3))&0x01; 2513:Src/main.c **** Curr_setup->LD2_EN = ((uint8_t)((*temp2)>>4))&0x01; 2514:Src/main.c **** Curr_setup->REF1_EN = ((uint8_t)((*temp2)>>5))&0x01; 2515:Src/main.c **** Curr_setup->REF2_EN = ((uint8_t)((*temp2)>>6))&0x01; 2516:Src/main.c **** Curr_setup->TEC1_EN = ((uint8_t)((*temp2)>>7))&0x01; 2517:Src/main.c **** Curr_setup->TEC2_EN = ((uint8_t)((*temp2)>>8))&0x01; 2518:Src/main.c **** Curr_setup->TS1_EN = ((uint8_t)((*temp2)>>9))&0x01; 2519:Src/main.c **** Curr_setup->TS2_EN = ((uint8_t)((*temp2)>>10))&0x01; 2520:Src/main.c **** Curr_setup->SD_EN = ((uint8_t)((*temp2)>>11))&0x01; 2521:Src/main.c **** Curr_setup->PI1_RD = ((uint8_t)((*temp2)>>12))&0x01; 2522:Src/main.c **** Curr_setup->PI2_RD = ((uint8_t)((*temp2)>>13))&0x01; 2523:Src/main.c **** 2524:Src/main.c **** temp2++; 2525:Src/main.c **** LD1_curr_setup->LD_TEMP = (uint16_t)(*temp2); 2526:Src/main.c **** temp2++; 2527:Src/main.c **** LD2_curr_setup->LD_TEMP = (uint16_t)(*temp2); ARM GAS /tmp/ccLSPxIe.s page 92 2528:Src/main.c **** temp2++; 2529:Src/main.c **** temp2++; 2530:Src/main.c **** temp2++; 2531:Src/main.c **** Curr_setup->AVERAGES = (uint16_t)(*temp2); 2532:Src/main.c **** temp2++; 2533:Src/main.c **** LD1_curr_setup->P_coef_temp = (float)((uint16_t)(*temp2))/((float)(256));//(float)(1/(float)((uint 2534:Src/main.c **** temp2++; 2535:Src/main.c **** LD1_curr_setup->I_coef_temp = (float)((uint16_t)(*temp2))/((float)(256));//(float)(1/(float)((uint 2536:Src/main.c **** temp2++; 2537:Src/main.c **** LD2_curr_setup->P_coef_temp = (float)((uint16_t)(*temp2))/((float)(256));//(float)(1/(float)((uint 2538:Src/main.c **** temp2++; 2539:Src/main.c **** LD2_curr_setup->I_coef_temp = (float)((uint16_t)(*temp2))/((float)(256));//(float)(1/(float)((uint 2540:Src/main.c **** temp2++; 2541:Src/main.c **** Long_Data[13] = (uint16_t)(*temp2);//Message ID 2542:Src/main.c **** temp2++; 2543:Src/main.c **** LD1_curr_setup->CURRENT = (uint16_t)(*temp2); 2544:Src/main.c **** temp2++; 2545:Src/main.c **** LD2_curr_setup->CURRENT = (uint16_t)(*temp2); 2546:Src/main.c **** temp2++; 2547:Src/main.c **** 2548:Src/main.c **** if (Curr_setup->U5V1_EN) 2549:Src/main.c **** { 2550:Src/main.c **** HAL_GPIO_WritePin(EN_5V1_GPIO_Port, EN_5V1_Pin, GPIO_PIN_SET); 2551:Src/main.c **** } 2552:Src/main.c **** else 2553:Src/main.c **** { 2554:Src/main.c **** HAL_GPIO_WritePin(EN_5V1_GPIO_Port, EN_5V1_Pin, GPIO_PIN_RESET); 2555:Src/main.c **** } 2556:Src/main.c **** 2557:Src/main.c **** if (Curr_setup->U5V2_EN) 2558:Src/main.c **** { 2559:Src/main.c **** HAL_GPIO_WritePin(EN_5V2_GPIO_Port, EN_5V2_Pin, GPIO_PIN_SET); 2560:Src/main.c **** } 2561:Src/main.c **** else 2562:Src/main.c **** { 2563:Src/main.c **** HAL_GPIO_WritePin(EN_5V2_GPIO_Port, EN_5V2_Pin, GPIO_PIN_RESET); 2564:Src/main.c **** } 2565:Src/main.c **** 2566:Src/main.c **** if (Curr_setup->LD1_EN) 2567:Src/main.c **** { 2568:Src/main.c **** HAL_GPIO_WritePin(LD1_EN_GPIO_Port, LD1_EN_Pin, GPIO_PIN_SET); 2569:Src/main.c **** //LL_SPI_Enable(SPI2);//Enable SPI for Laser1 DAC 2570:Src/main.c **** } 2571:Src/main.c **** else 2572:Src/main.c **** { 2573:Src/main.c **** HAL_GPIO_WritePin(LD1_EN_GPIO_Port, LD1_EN_Pin, GPIO_PIN_RESET); 2574:Src/main.c **** //LL_SPI_Disable(SPI2);//Disable SPI for Laser1 DAC 2575:Src/main.c **** } 2576:Src/main.c **** 2577:Src/main.c **** if (Curr_setup->LD2_EN) 2578:Src/main.c **** { 2579:Src/main.c **** HAL_GPIO_WritePin(LD2_EN_GPIO_Port, LD2_EN_Pin, GPIO_PIN_SET); 2580:Src/main.c **** //LL_SPI_Enable(SPI6);//Enable SPI for Laser2 DAC 2581:Src/main.c **** } 2582:Src/main.c **** else 2583:Src/main.c **** { 2584:Src/main.c **** HAL_GPIO_WritePin(LD2_EN_GPIO_Port, LD2_EN_Pin, GPIO_PIN_RESET); ARM GAS /tmp/ccLSPxIe.s page 93 2585:Src/main.c **** //LL_SPI_Disable(SPI6);//Disable SPI for Laser2 DAC 2586:Src/main.c **** } 2587:Src/main.c **** 2588:Src/main.c **** if (Curr_setup->REF1_EN) 2589:Src/main.c **** { 2590:Src/main.c **** HAL_GPIO_WritePin(REF0_EN_GPIO_Port, REF0_EN_Pin, GPIO_PIN_SET); 2591:Src/main.c **** } 2592:Src/main.c **** else 2593:Src/main.c **** { 2594:Src/main.c **** HAL_GPIO_WritePin(REF0_EN_GPIO_Port, REF0_EN_Pin, GPIO_PIN_RESET); 2595:Src/main.c **** } 2596:Src/main.c **** 2597:Src/main.c **** if (Curr_setup->REF2_EN) 2598:Src/main.c **** { 2599:Src/main.c **** HAL_GPIO_WritePin(REF2_ON_GPIO_Port, REF2_ON_Pin, GPIO_PIN_SET); 2600:Src/main.c **** } 2601:Src/main.c **** else 2602:Src/main.c **** { 2603:Src/main.c **** HAL_GPIO_WritePin(REF2_ON_GPIO_Port, REF2_ON_Pin, GPIO_PIN_RESET); 2604:Src/main.c **** } 2605:Src/main.c **** 2606:Src/main.c **** if ((Curr_setup->TS1_EN)&&(Curr_setup->TEC1_EN)) 2607:Src/main.c **** { 2608:Src/main.c **** Set_LTEC(3,32767); 2609:Src/main.c **** Set_LTEC(3,32767); 2610:Src/main.c **** HAL_GPIO_WritePin(TEC1_PD_GPIO_Port, TEC1_PD_Pin, GPIO_PIN_SET); 2611:Src/main.c **** HAL_GPIO_WritePin(TECEN1_GPIO_Port, TECEN1_Pin, GPIO_PIN_SET); 2612:Src/main.c **** } 2613:Src/main.c **** else 2614:Src/main.c **** { 2615:Src/main.c **** HAL_GPIO_WritePin(TECEN1_GPIO_Port, TECEN1_Pin, GPIO_PIN_RESET); 2616:Src/main.c **** HAL_GPIO_WritePin(TEC1_PD_GPIO_Port, TEC1_PD_Pin, GPIO_PIN_RESET); 2617:Src/main.c **** } 2618:Src/main.c **** 2619:Src/main.c **** if ((Curr_setup->TS2_EN)&&(Curr_setup->TEC2_EN)) 2620:Src/main.c **** { 2621:Src/main.c **** Set_LTEC(4,32767); 2622:Src/main.c **** Set_LTEC(4,32767); 2623:Src/main.c **** HAL_GPIO_WritePin(TEC2_PD_GPIO_Port, TEC2_PD_Pin, GPIO_PIN_SET); 2624:Src/main.c **** HAL_GPIO_WritePin(TECEN2_GPIO_Port, TECEN2_Pin, GPIO_PIN_SET); 2625:Src/main.c **** } 2626:Src/main.c **** else 2627:Src/main.c **** { 2628:Src/main.c **** HAL_GPIO_WritePin(TECEN2_GPIO_Port, TECEN2_Pin, GPIO_PIN_RESET); 2629:Src/main.c **** HAL_GPIO_WritePin(TEC2_PD_GPIO_Port, TEC2_PD_Pin, GPIO_PIN_RESET); 2630:Src/main.c **** } 2631:Src/main.c **** 2632:Src/main.c **** if (Curr_setup->PI1_RD==0) 2633:Src/main.c **** { 2634:Src/main.c **** LD1_curr_setup->P_coef_temp = 10; 2635:Src/main.c **** LD1_curr_setup->I_coef_temp = 0.01; 2636:Src/main.c **** } 2637:Src/main.c **** 2638:Src/main.c **** if (Curr_setup->PI2_RD==0) 2639:Src/main.c **** { 2640:Src/main.c **** LD2_curr_setup->P_coef_temp = 10; 2641:Src/main.c **** LD2_curr_setup->I_coef_temp = 0.01; ARM GAS /tmp/ccLSPxIe.s page 94 2642:Src/main.c **** } 2643:Src/main.c **** } 2644:Src/main.c **** 2645:Src/main.c **** static void Decode_task(uint16_t *Command, LDx_SetupTypeDef *LD1_curr_setup, LDx_SetupTypeDef *LD2_ 2646:Src/main.c **** { 253 .loc 1 2646 1 is_stmt 1 view -0 254 .cfi_startproc 255 @ args = 0, pretend = 0, frame = 8 256 @ frame_needed = 0, uses_anonymous_args = 0 257 @ link register save eliminated. 258 .loc 1 2646 1 is_stmt 0 view .LVU66 259 0000 82B0 sub sp, sp, #8 260 .LCFI4: 261 .cfi_def_cfa_offset 8 2647:Src/main.c **** uint16_t *temp2; 262 .loc 1 2647 2 is_stmt 1 view .LVU67 2648:Src/main.c **** 2649:Src/main.c **** temp2 = (uint16_t *)Command; 263 .loc 1 2649 2 view .LVU68 264 .LVL15: 2650:Src/main.c **** Curr_setup->WORK_EN = ((uint8_t)((*temp2)>>0))&0x01; 265 .loc 1 2650 2 view .LVU69 266 .loc 1 2650 36 is_stmt 0 view .LVU70 267 0002 0288 ldrh r2, [r0] 268 .LVL16: 269 .loc 1 2650 48 view .LVU71 270 0004 02F00102 and r2, r2, #1 271 .loc 1 2650 22 view .LVU72 272 0008 1A70 strb r2, [r3] 2651:Src/main.c **** Curr_setup->U5V1_EN = ((uint8_t)((*temp2)>>1))&0x01; 273 .loc 1 2651 2 is_stmt 1 view .LVU73 274 .loc 1 2651 36 is_stmt 0 view .LVU74 275 000a 0288 ldrh r2, [r0] 276 .loc 1 2651 48 view .LVU75 277 000c C2F34002 ubfx r2, r2, #1, #1 278 .loc 1 2651 22 view .LVU76 279 0010 5A70 strb r2, [r3, #1] 2652:Src/main.c **** Curr_setup->U5V2_EN = ((uint8_t)((*temp2)>>2))&0x01; 280 .loc 1 2652 2 is_stmt 1 view .LVU77 281 .loc 1 2652 36 is_stmt 0 view .LVU78 282 0012 0288 ldrh r2, [r0] 283 .loc 1 2652 48 view .LVU79 284 0014 C2F38002 ubfx r2, r2, #2, #1 285 .loc 1 2652 22 view .LVU80 286 0018 9A70 strb r2, [r3, #2] 2653:Src/main.c **** Curr_setup->LD1_EN = ((uint8_t)((*temp2)>>3))&0x01; 287 .loc 1 2653 2 is_stmt 1 view .LVU81 288 .loc 1 2653 35 is_stmt 0 view .LVU82 289 001a 0288 ldrh r2, [r0] 290 .loc 1 2653 47 view .LVU83 291 001c C2F3C002 ubfx r2, r2, #3, #1 292 .loc 1 2653 21 view .LVU84 293 0020 DA70 strb r2, [r3, #3] 2654:Src/main.c **** Curr_setup->LD2_EN = ((uint8_t)((*temp2)>>4))&0x01; 294 .loc 1 2654 2 is_stmt 1 view .LVU85 295 .loc 1 2654 35 is_stmt 0 view .LVU86 296 0022 0288 ldrh r2, [r0] ARM GAS /tmp/ccLSPxIe.s page 95 297 .loc 1 2654 47 view .LVU87 298 0024 C2F30012 ubfx r2, r2, #4, #1 299 .loc 1 2654 21 view .LVU88 300 0028 1A71 strb r2, [r3, #4] 2655:Src/main.c **** Curr_setup->REF1_EN = ((uint8_t)((*temp2)>>5))&0x01; 301 .loc 1 2655 2 is_stmt 1 view .LVU89 302 .loc 1 2655 36 is_stmt 0 view .LVU90 303 002a 0288 ldrh r2, [r0] 304 .loc 1 2655 48 view .LVU91 305 002c C2F34012 ubfx r2, r2, #5, #1 306 .loc 1 2655 22 view .LVU92 307 0030 5A71 strb r2, [r3, #5] 2656:Src/main.c **** Curr_setup->REF2_EN = ((uint8_t)((*temp2)>>6))&0x01; 308 .loc 1 2656 2 is_stmt 1 view .LVU93 309 .loc 1 2656 36 is_stmt 0 view .LVU94 310 0032 0288 ldrh r2, [r0] 311 .loc 1 2656 48 view .LVU95 312 0034 C2F38012 ubfx r2, r2, #6, #1 313 .loc 1 2656 22 view .LVU96 314 0038 9A71 strb r2, [r3, #6] 2657:Src/main.c **** Curr_setup->TEC1_EN = ((uint8_t)((*temp2)>>7))&0x01; 315 .loc 1 2657 2 is_stmt 1 view .LVU97 316 .loc 1 2657 36 is_stmt 0 view .LVU98 317 003a 0288 ldrh r2, [r0] 318 .loc 1 2657 48 view .LVU99 319 003c C2F3C012 ubfx r2, r2, #7, #1 320 .loc 1 2657 22 view .LVU100 321 0040 DA71 strb r2, [r3, #7] 2658:Src/main.c **** Curr_setup->TEC2_EN = ((uint8_t)((*temp2)>>8))&0x01; 322 .loc 1 2658 2 is_stmt 1 view .LVU101 323 .loc 1 2658 36 is_stmt 0 view .LVU102 324 0042 0288 ldrh r2, [r0] 325 .loc 1 2658 48 view .LVU103 326 0044 C2F30022 ubfx r2, r2, #8, #1 327 .loc 1 2658 22 view .LVU104 328 0048 1A72 strb r2, [r3, #8] 2659:Src/main.c **** Curr_setup->TS1_EN = ((uint8_t)((*temp2)>>9))&0x01; 329 .loc 1 2659 2 is_stmt 1 view .LVU105 330 .loc 1 2659 35 is_stmt 0 view .LVU106 331 004a 0288 ldrh r2, [r0] 332 .loc 1 2659 47 view .LVU107 333 004c C2F34022 ubfx r2, r2, #9, #1 334 .loc 1 2659 21 view .LVU108 335 0050 5A72 strb r2, [r3, #9] 2660:Src/main.c **** Curr_setup->TS2_EN = ((uint8_t)((*temp2)>>10))&0x01; 336 .loc 1 2660 2 is_stmt 1 view .LVU109 337 .loc 1 2660 35 is_stmt 0 view .LVU110 338 0052 0288 ldrh r2, [r0] 339 .loc 1 2660 48 view .LVU111 340 0054 C2F38022 ubfx r2, r2, #10, #1 341 .loc 1 2660 21 view .LVU112 342 0058 9A72 strb r2, [r3, #10] 2661:Src/main.c **** Curr_setup->SD_EN = ((uint8_t)((*temp2)>>11))&0x01; 343 .loc 1 2661 2 is_stmt 1 view .LVU113 344 .loc 1 2661 34 is_stmt 0 view .LVU114 345 005a 0288 ldrh r2, [r0] 346 .loc 1 2661 47 view .LVU115 ARM GAS /tmp/ccLSPxIe.s page 96 347 005c C2F3C022 ubfx r2, r2, #11, #1 348 .loc 1 2661 20 view .LVU116 349 0060 DA72 strb r2, [r3, #11] 2662:Src/main.c **** Curr_setup->PI1_RD = ((uint8_t)((*temp2)>>12))&0x01; 350 .loc 1 2662 2 is_stmt 1 view .LVU117 351 .loc 1 2662 35 is_stmt 0 view .LVU118 352 0062 0288 ldrh r2, [r0] 353 .loc 1 2662 48 view .LVU119 354 0064 C2F30032 ubfx r2, r2, #12, #1 355 .loc 1 2662 21 view .LVU120 356 0068 1A73 strb r2, [r3, #12] 2663:Src/main.c **** Curr_setup->PI2_RD = ((uint8_t)((*temp2)>>13))&0x01; 357 .loc 1 2663 2 is_stmt 1 view .LVU121 358 .loc 1 2663 35 is_stmt 0 view .LVU122 359 006a 0288 ldrh r2, [r0] 360 .loc 1 2663 48 view .LVU123 361 006c C2F34032 ubfx r2, r2, #13, #1 362 .loc 1 2663 21 view .LVU124 363 0070 5A73 strb r2, [r3, #13] 2664:Src/main.c **** 2665:Src/main.c **** temp2++; 364 .loc 1 2665 2 is_stmt 1 view .LVU125 365 .LVL17: 2666:Src/main.c **** task.task_type = (uint8_t)(*temp2); temp2++; 366 .loc 1 2666 2 view .LVU126 367 .loc 1 2666 21 is_stmt 0 view .LVU127 368 0072 8278 ldrb r2, [r0, #2] @ zero_extendqisi2 369 .loc 1 2666 19 view .LVU128 370 0074 384B ldr r3, .L14+8 371 .LVL18: 372 .loc 1 2666 19 view .LVU129 373 0076 1A70 strb r2, [r3] 374 .loc 1 2666 40 is_stmt 1 view .LVU130 375 .LVL19: 2667:Src/main.c **** task.min_param = (float)(*temp2); temp2++; 376 .loc 1 2667 2 view .LVU131 377 .loc 1 2667 29 is_stmt 0 view .LVU132 378 0078 8288 ldrh r2, [r0, #4] 379 007a 07EE902A vmov s15, r2 @ int 380 .loc 1 2667 21 view .LVU133 381 007e F8EE677A vcvt.f32.u32 s15, s15 382 .loc 1 2667 19 view .LVU134 383 0082 C3ED017A vstr.32 s15, [r3, #4] 384 .loc 1 2667 38 is_stmt 1 view .LVU135 385 .LVL20: 2668:Src/main.c **** task.max_param = (float)(*temp2); temp2++; 386 .loc 1 2668 2 view .LVU136 387 .loc 1 2668 29 is_stmt 0 view .LVU137 388 0086 C288 ldrh r2, [r0, #6] 389 0088 07EE902A vmov s15, r2 @ int 390 .loc 1 2668 21 view .LVU138 391 008c F8EE677A vcvt.f32.u32 s15, s15 392 .loc 1 2668 19 view .LVU139 393 0090 C3ED027A vstr.32 s15, [r3, #8] 394 .loc 1 2668 38 is_stmt 1 view .LVU140 395 .LVL21: 2669:Src/main.c **** task.delta_param = (float)(*temp2); temp2++; ARM GAS /tmp/ccLSPxIe.s page 97 396 .loc 1 2669 2 view .LVU141 397 .loc 1 2669 29 is_stmt 0 view .LVU142 398 0094 0289 ldrh r2, [r0, #8] 399 0096 07EE902A vmov s15, r2 @ int 400 .loc 1 2669 21 view .LVU143 401 009a F8EE677A vcvt.f32.u32 s15, s15 402 .loc 1 2669 19 view .LVU144 403 009e C3ED037A vstr.32 s15, [r3, #12] 404 .loc 1 2669 38 is_stmt 1 view .LVU145 405 .LVL22: 2670:Src/main.c **** task.dt = (float)(*temp2) / 100.0; temp2++; 406 .loc 1 2670 2 view .LVU146 407 .loc 1 2670 29 is_stmt 0 view .LVU147 408 00a2 4289 ldrh r2, [r0, #10] 409 00a4 07EE102A vmov s14, r2 @ int 410 .loc 1 2670 21 view .LVU148 411 00a8 B8EE477B vcvt.f64.u32 d7, s14 412 .loc 1 2670 37 view .LVU149 413 00ac 9FED285B vldr.64 d5, .L14 414 00b0 87EE056B vdiv.f64 d6, d7, d5 415 .loc 1 2670 19 view .LVU150 416 00b4 FCEEC67B vcvt.u32.f64 s15, d6 417 00b8 CDED017A vstr.32 s15, [sp, #4] @ int 418 00bc 9DF80420 ldrb r2, [sp, #4] @ zero_extendqisi2 419 00c0 1A75 strb r2, [r3, #20] 420 .loc 1 2670 46 is_stmt 1 view .LVU151 421 .LVL23: 2671:Src/main.c **** task.sec_param = (float)(*temp2); temp2++; 422 .loc 1 2671 2 view .LVU152 423 .loc 1 2671 29 is_stmt 0 view .LVU153 424 00c2 8189 ldrh r1, [r0, #12] 425 .LVL24: 426 .loc 1 2671 29 view .LVU154 427 00c4 07EE901A vmov s15, r1 @ int 428 .loc 1 2671 21 view .LVU155 429 00c8 F8EE677A vcvt.f32.u32 s15, s15 430 .loc 1 2671 19 view .LVU156 431 00cc C3ED067A vstr.32 s15, [r3, #24] 432 .loc 1 2671 38 is_stmt 1 view .LVU157 433 .LVL25: 2672:Src/main.c **** task.curr = (float)(*temp2); temp2++; 434 .loc 1 2672 2 view .LVU158 435 .loc 1 2672 29 is_stmt 0 view .LVU159 436 00d0 C189 ldrh r1, [r0, #14] 437 00d2 07EE901A vmov s15, r1 @ int 438 .loc 1 2672 21 view .LVU160 439 00d6 F8EE677A vcvt.f32.u32 s15, s15 440 .loc 1 2672 19 view .LVU161 441 00da C3ED077A vstr.32 s15, [r3, #28] 442 .loc 1 2672 38 is_stmt 1 view .LVU162 443 .LVL26: 2673:Src/main.c **** task.temp = (float)(*temp2); temp2++; 444 .loc 1 2673 2 view .LVU163 445 .loc 1 2673 29 is_stmt 0 view .LVU164 446 00de 018A ldrh r1, [r0, #16] 447 00e0 07EE901A vmov s15, r1 @ int 448 .loc 1 2673 21 view .LVU165 ARM GAS /tmp/ccLSPxIe.s page 98 449 00e4 F8EE677A vcvt.f32.u32 s15, s15 450 .loc 1 2673 19 view .LVU166 451 00e8 C3ED087A vstr.32 s15, [r3, #32] 452 .loc 1 2673 38 is_stmt 1 view .LVU167 453 .LVL27: 2674:Src/main.c **** task.tau = (float)(*temp2); temp2++; 454 .loc 1 2674 2 view .LVU168 455 .loc 1 2674 29 is_stmt 0 view .LVU169 456 00ec 418A ldrh r1, [r0, #18] 457 .loc 1 2674 19 view .LVU170 458 00ee D982 strh r1, [r3, #22] @ movhi 459 .loc 1 2674 38 is_stmt 1 view .LVU171 460 .LVL28: 2675:Src/main.c **** task.p_coef_1 = (float)(*temp2) * 256.0; temp2++; 461 .loc 1 2675 2 view .LVU172 462 .loc 1 2675 29 is_stmt 0 view .LVU173 463 00f0 818A ldrh r1, [r0, #20] 464 00f2 07EE901A vmov s15, r1 @ int 465 .loc 1 2675 21 view .LVU174 466 00f6 F8EE677A vcvt.f32.u32 s15, s15 467 .loc 1 2675 37 view .LVU175 468 00fa 9FED187A vldr.32 s14, .L14+12 469 00fe 67EE877A vmul.f32 s15, s15, s14 470 .loc 1 2675 19 view .LVU176 471 0102 C3ED0A7A vstr.32 s15, [r3, #40] 472 .loc 1 2675 46 is_stmt 1 view .LVU177 473 .LVL29: 2676:Src/main.c **** task.i_coef_1 = (float)(*temp2) * 256.0; temp2++; 474 .loc 1 2676 2 view .LVU178 475 .loc 1 2676 29 is_stmt 0 view .LVU179 476 0106 C18A ldrh r1, [r0, #22] 477 0108 07EE901A vmov s15, r1 @ int 478 .loc 1 2676 21 view .LVU180 479 010c F8EE677A vcvt.f32.u32 s15, s15 480 .loc 1 2676 37 view .LVU181 481 0110 67EE877A vmul.f32 s15, s15, s14 482 .loc 1 2676 19 view .LVU182 483 0114 C3ED097A vstr.32 s15, [r3, #36] 484 .loc 1 2676 46 is_stmt 1 view .LVU183 485 .LVL30: 2677:Src/main.c **** task.p_coef_2 = (float)(*temp2) * 256.0; temp2++; 486 .loc 1 2677 2 view .LVU184 487 .loc 1 2677 29 is_stmt 0 view .LVU185 488 0118 018B ldrh r1, [r0, #24] 489 011a 07EE901A vmov s15, r1 @ int 490 .loc 1 2677 21 view .LVU186 491 011e F8EE677A vcvt.f32.u32 s15, s15 492 .loc 1 2677 37 view .LVU187 493 0122 67EE877A vmul.f32 s15, s15, s14 494 .loc 1 2677 19 view .LVU188 495 0126 C3ED0C7A vstr.32 s15, [r3, #48] 496 .loc 1 2677 46 is_stmt 1 view .LVU189 497 .LVL31: 2678:Src/main.c **** task.i_coef_2 = (float)(*temp2) * 256.0; temp2++; 498 .loc 1 2678 2 view .LVU190 499 .loc 1 2678 29 is_stmt 0 view .LVU191 500 012a 418B ldrh r1, [r0, #26] ARM GAS /tmp/ccLSPxIe.s page 99 501 012c 07EE901A vmov s15, r1 @ int 502 .loc 1 2678 21 view .LVU192 503 0130 F8EE677A vcvt.f32.u32 s15, s15 504 .loc 1 2678 37 view .LVU193 505 0134 67EE877A vmul.f32 s15, s15, s14 506 .loc 1 2678 19 view .LVU194 507 0138 C3ED0B7A vstr.32 s15, [r3, #44] 508 .loc 1 2678 46 is_stmt 1 view .LVU195 509 .LVL32: 2679:Src/main.c **** 2680:Src/main.c **** TO10_counter = task.dt / 10; 510 .loc 1 2680 2 view .LVU196 511 .loc 1 2680 25 is_stmt 0 view .LVU197 512 013c 084B ldr r3, .L14+16 513 013e A3FB0232 umull r3, r2, r3, r2 514 0142 D208 lsrs r2, r2, #3 515 .loc 1 2680 15 view .LVU198 516 0144 074B ldr r3, .L14+20 517 0146 1A60 str r2, [r3] 2681:Src/main.c **** } 518 .loc 1 2681 1 view .LVU199 519 0148 02B0 add sp, sp, #8 520 .LCFI5: 521 .cfi_def_cfa_offset 0 522 @ sp needed 523 014a 7047 bx lr 524 .L15: 525 014c AFF30080 .align 3 526 .L14: 527 0150 00000000 .word 0 528 0154 00005940 .word 1079574528 529 0158 00000000 .word task 530 015c 00008043 .word 1132462080 531 0160 CDCCCCCC .word -858993459 532 0164 00000000 .word TO10_counter 533 .cfi_endproc 534 .LFE1210: 536 .section .text.SPI2_SetMode,"ax",%progbits 537 .align 1 538 .syntax unified 539 .thumb 540 .thumb_func 542 SPI2_SetMode: 543 .LVL33: 544 .LFB1213: 2682:Src/main.c **** 2683:Src/main.c **** void OUT_trigger(uint8_t out_n) 2684:Src/main.c **** { 2685:Src/main.c **** switch (out_n) 2686:Src/main.c **** { 2687:Src/main.c **** case 0: 2688:Src/main.c **** HAL_GPIO_WritePin(OUT_0_GPIO_Port, OUT_0_Pin, GPIO_PIN_SET); 2689:Src/main.c **** HAL_GPIO_WritePin(OUT_0_GPIO_Port, OUT_0_Pin, GPIO_PIN_RESET); 2690:Src/main.c **** break; 2691:Src/main.c **** 2692:Src/main.c **** case 1: 2693:Src/main.c **** HAL_GPIO_WritePin(OUT_1_GPIO_Port, OUT_1_Pin, GPIO_PIN_SET); ARM GAS /tmp/ccLSPxIe.s page 100 2694:Src/main.c **** HAL_GPIO_WritePin(OUT_1_GPIO_Port, OUT_1_Pin, GPIO_PIN_RESET); 2695:Src/main.c **** break; 2696:Src/main.c **** 2697:Src/main.c **** case 2: 2698:Src/main.c **** HAL_GPIO_WritePin(OUT_2_GPIO_Port, OUT_2_Pin, GPIO_PIN_SET); 2699:Src/main.c **** HAL_GPIO_WritePin(OUT_2_GPIO_Port, OUT_2_Pin, GPIO_PIN_RESET); 2700:Src/main.c **** break; 2701:Src/main.c **** 2702:Src/main.c **** case 3: 2703:Src/main.c **** HAL_GPIO_WritePin(OUT_3_GPIO_Port, OUT_3_Pin, GPIO_PIN_SET); 2704:Src/main.c **** HAL_GPIO_WritePin(OUT_3_GPIO_Port, OUT_3_Pin, GPIO_PIN_RESET); 2705:Src/main.c **** break; 2706:Src/main.c **** 2707:Src/main.c **** case 4: 2708:Src/main.c **** HAL_GPIO_WritePin(OUT_4_GPIO_Port, OUT_4_Pin, GPIO_PIN_SET); 2709:Src/main.c **** HAL_GPIO_WritePin(OUT_4_GPIO_Port, OUT_4_Pin, GPIO_PIN_RESET); 2710:Src/main.c **** break; 2711:Src/main.c **** 2712:Src/main.c **** case 5: 2713:Src/main.c **** HAL_GPIO_WritePin(OUT_5_GPIO_Port, OUT_5_Pin, GPIO_PIN_SET); 2714:Src/main.c **** HAL_GPIO_WritePin(OUT_5_GPIO_Port, OUT_5_Pin, GPIO_PIN_RESET); 2715:Src/main.c **** break; 2716:Src/main.c **** 2717:Src/main.c **** case 6: 2718:Src/main.c **** HAL_GPIO_WritePin(OUT_6_GPIO_Port, OUT_6_Pin, GPIO_PIN_SET); 2719:Src/main.c **** HAL_GPIO_WritePin(OUT_6_GPIO_Port, OUT_6_Pin, GPIO_PIN_RESET); 2720:Src/main.c **** break; 2721:Src/main.c **** 2722:Src/main.c **** case 7: 2723:Src/main.c **** HAL_GPIO_WritePin(OUT_7_GPIO_Port, OUT_7_Pin, GPIO_PIN_SET); 2724:Src/main.c **** HAL_GPIO_WritePin(OUT_7_GPIO_Port, OUT_7_Pin, GPIO_PIN_RESET); 2725:Src/main.c **** break; 2726:Src/main.c **** 2727:Src/main.c **** case 8: 2728:Src/main.c **** HAL_GPIO_WritePin(OUT_8_GPIO_Port, OUT_8_Pin, GPIO_PIN_SET); 2729:Src/main.c **** HAL_GPIO_WritePin(OUT_8_GPIO_Port, OUT_8_Pin, GPIO_PIN_RESET); 2730:Src/main.c **** break; 2731:Src/main.c **** 2732:Src/main.c **** case 9: 2733:Src/main.c **** HAL_GPIO_WritePin(OUT_9_GPIO_Port, OUT_9_Pin, GPIO_PIN_SET); 2734:Src/main.c **** HAL_GPIO_WritePin(OUT_9_GPIO_Port, OUT_9_Pin, GPIO_PIN_RESET); 2735:Src/main.c **** break; 2736:Src/main.c **** } 2737:Src/main.c **** } 2738:Src/main.c **** 2739:Src/main.c **** static void AD9102_Init(void) 2740:Src/main.c **** { 2741:Src/main.c **** HAL_GPIO_WritePin(AD9102_CS_GPIO_Port, AD9102_CS_Pin, GPIO_PIN_SET); 2742:Src/main.c **** HAL_GPIO_WritePin(AD9102_RESET_GPIO_Port, AD9102_RESET_Pin, GPIO_PIN_RESET); 2743:Src/main.c **** for (volatile uint32_t d = 0; d < 1000; d++) {} 2744:Src/main.c **** HAL_GPIO_WritePin(AD9102_RESET_GPIO_Port, AD9102_RESET_Pin, GPIO_PIN_SET); 2745:Src/main.c **** 2746:Src/main.c **** AD9102_WriteRegTable(ad9102_example4_regval, AD9102_REG_COUNT); 2747:Src/main.c **** AD9102_WriteReg(AD9102_REG_PAT_STATUS, 0x0000u); 2748:Src/main.c **** AD9102_WriteReg(AD9102_REG_RAMUPDATE, 0x0001u); 2749:Src/main.c **** HAL_GPIO_WritePin(AD9102_TRIG_GPIO_Port, AD9102_TRIG_Pin, GPIO_PIN_SET); 2750:Src/main.c **** } ARM GAS /tmp/ccLSPxIe.s page 101 2751:Src/main.c **** 2752:Src/main.c **** static void SPI2_SetMode(uint32_t polarity, uint32_t phase) 2753:Src/main.c **** { 545 .loc 1 2753 1 is_stmt 1 view -0 546 .cfi_startproc 547 @ args = 0, pretend = 0, frame = 0 548 @ frame_needed = 0, uses_anonymous_args = 0 549 @ link register save eliminated. 2754:Src/main.c **** if (LL_SPI_IsEnabled(SPI2)) 550 .loc 1 2754 2 view .LVU201 551 .LBB363: 552 .LBI363: 553 .file 4 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h" 1:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 2:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** ****************************************************************************** 3:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @file stm32f7xx_ll_spi.h 4:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @author MCD Application Team 5:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Header file of SPI LL module. 6:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** ****************************************************************************** 7:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @attention 8:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * 9:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * Copyright (c) 2017 STMicroelectronics. 10:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * All rights reserved. 11:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * 12:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * This software is licensed under terms that can be found in the LICENSE file 13:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * in the root directory of this software component. 14:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * If no LICENSE file comes with this software, it is provided AS-IS. 15:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * 16:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** ****************************************************************************** 17:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 18:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 19:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /* Define to prevent recursive inclusion -------------------------------------*/ 20:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #ifndef STM32F7xx_LL_SPI_H 21:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define STM32F7xx_LL_SPI_H 22:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 23:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #ifdef __cplusplus 24:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** extern "C" { 25:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #endif 26:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 27:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /* Includes ------------------------------------------------------------------*/ 28:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #include "stm32f7xx.h" 29:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 30:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @addtogroup STM32F7xx_LL_Driver 31:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @{ 32:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 33:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 34:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #if defined (SPI1) || defined (SPI2) || defined (SPI3) || defined (SPI4) || defined (SPI5) || defin 35:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 36:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL SPI 37:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @{ 38:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 39:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 40:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /* Private types -------------------------------------------------------------*/ 41:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /* Private variables ---------------------------------------------------------*/ 42:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /* Private macros ------------------------------------------------------------*/ 43:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 44:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /* Exported types ------------------------------------------------------------*/ ARM GAS /tmp/ccLSPxIe.s page 102 45:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #if defined(USE_FULL_LL_DRIVER) 46:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_ES_INIT SPI Exported Init structure 47:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @{ 48:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 49:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 50:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 51:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief SPI Init structures definition 52:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 53:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** typedef struct 54:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 55:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** uint32_t TransferDirection; /*!< Specifies the SPI unidirectional or bidirectional data mod 56:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** This parameter can be a value of @ref SPI_LL_EC_TRANSFER_M 57:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 58:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** This feature can be modified afterwards using unitary func 59:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 60:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** uint32_t Mode; /*!< Specifies the SPI mode (Master/Slave). 61:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** This parameter can be a value of @ref SPI_LL_EC_MODE. 62:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 63:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** This feature can be modified afterwards using unitary func 64:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 65:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** uint32_t DataWidth; /*!< Specifies the SPI data width. 66:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** This parameter can be a value of @ref SPI_LL_EC_DATAWIDTH. 67:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 68:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** This feature can be modified afterwards using unitary func 69:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 70:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** uint32_t ClockPolarity; /*!< Specifies the serial clock steady state. 71:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** This parameter can be a value of @ref SPI_LL_EC_POLARITY. 72:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 73:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** This feature can be modified afterwards using unitary func 74:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 75:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** uint32_t ClockPhase; /*!< Specifies the clock active edge for the bit capture. 76:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** This parameter can be a value of @ref SPI_LL_EC_PHASE. 77:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 78:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** This feature can be modified afterwards using unitary func 79:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 80:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** uint32_t NSS; /*!< Specifies whether the NSS signal is managed by hardware (N 81:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** This parameter can be a value of @ref SPI_LL_EC_NSS_MODE. 82:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 83:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** This feature can be modified afterwards using unitary func 84:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 85:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** uint32_t BaudRate; /*!< Specifies the BaudRate prescaler value which will be used 86:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** This parameter can be a value of @ref SPI_LL_EC_BAUDRATEPR 87:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** @note The communication clock is derived from the master c 88:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 89:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** This feature can be modified afterwards using unitary func 90:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 91:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** uint32_t BitOrder; /*!< Specifies whether data transfers start from MSB or LSB bit 92:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** This parameter can be a value of @ref SPI_LL_EC_BIT_ORDER. 93:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 94:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** This feature can be modified afterwards using unitary func 95:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 96:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** uint32_t CRCCalculation; /*!< Specifies if the CRC calculation is enabled or not. 97:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** This parameter can be a value of @ref SPI_LL_EC_CRC_CALCUL 98:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 99:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** This feature can be modified afterwards using unitary func 100:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 101:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** uint32_t CRCPoly; /*!< Specifies the polynomial used for the CRC calculation. ARM GAS /tmp/ccLSPxIe.s page 103 102:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** This parameter must be a number between Min_Data = 0x00 an 103:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 104:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** This feature can be modified afterwards using unitary func 105:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 106:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } LL_SPI_InitTypeDef; 107:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 108:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 109:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @} 110:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 111:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #endif /* USE_FULL_LL_DRIVER */ 112:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 113:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /* Exported constants --------------------------------------------------------*/ 114:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_Exported_Constants SPI Exported Constants 115:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @{ 116:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 117:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 118:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_EC_GET_FLAG Get Flags Defines 119:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Flags defines which can be used with LL_SPI_ReadReg function 120:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @{ 121:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 122:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_SR_RXNE SPI_SR_RXNE /*!< Rx buffer not empty flag 123:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_SR_TXE SPI_SR_TXE /*!< Tx buffer empty flag 124:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_SR_BSY SPI_SR_BSY /*!< Busy flag 125:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_SR_CRCERR SPI_SR_CRCERR /*!< CRC error flag 126:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_SR_MODF SPI_SR_MODF /*!< Mode fault flag 127:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_SR_OVR SPI_SR_OVR /*!< Overrun flag 128:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_SR_FRE SPI_SR_FRE /*!< TI mode frame format erro 129:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 130:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @} 131:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 132:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 133:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_EC_IT IT Defines 134:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief IT defines which can be used with LL_SPI_ReadReg and LL_SPI_WriteReg functions 135:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @{ 136:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 137:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_CR2_RXNEIE SPI_CR2_RXNEIE /*!< Rx buffer not empty inter 138:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_CR2_TXEIE SPI_CR2_TXEIE /*!< Tx buffer empty interrupt 139:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_CR2_ERRIE SPI_CR2_ERRIE /*!< Error interrupt enable 140:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 141:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @} 142:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 143:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 144:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_EC_MODE Operation Mode 145:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @{ 146:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 147:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_MODE_MASTER (SPI_CR1_MSTR | SPI_CR1_SSI) /*!< Master configuratio 148:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_MODE_SLAVE 0x00000000U /*!< Slave configuration 149:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 150:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @} 151:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 152:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 153:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_EC_PROTOCOL Serial Protocol 154:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @{ 155:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 156:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_PROTOCOL_MOTOROLA 0x00000000U /*!< Motorola mode. Used as de 157:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_PROTOCOL_TI (SPI_CR2_FRF) /*!< TI mode 158:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** ARM GAS /tmp/ccLSPxIe.s page 104 159:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @} 160:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 161:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 162:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_EC_PHASE Clock Phase 163:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @{ 164:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 165:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_PHASE_1EDGE 0x00000000U /*!< First clock transition is 166:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_PHASE_2EDGE (SPI_CR1_CPHA) /*!< Second clock transition i 167:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 168:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @} 169:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 170:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 171:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_EC_POLARITY Clock Polarity 172:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @{ 173:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 174:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_POLARITY_LOW 0x00000000U /*!< Clock to 0 when idle */ 175:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_POLARITY_HIGH (SPI_CR1_CPOL) /*!< Clock to 1 when idle */ 176:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 177:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @} 178:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 179:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 180:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_EC_BAUDRATEPRESCALER Baud Rate Prescaler 181:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @{ 182:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 183:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_BAUDRATEPRESCALER_DIV2 0x00000000U /*!< Baud 184:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_BAUDRATEPRESCALER_DIV4 (SPI_CR1_BR_0) /*!< Baud 185:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_BAUDRATEPRESCALER_DIV8 (SPI_CR1_BR_1) /*!< Baud 186:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_BAUDRATEPRESCALER_DIV16 (SPI_CR1_BR_1 | SPI_CR1_BR_0) /*!< Baud 187:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_BAUDRATEPRESCALER_DIV32 (SPI_CR1_BR_2) /*!< Baud 188:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_BAUDRATEPRESCALER_DIV64 (SPI_CR1_BR_2 | SPI_CR1_BR_0) /*!< Baud 189:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_BAUDRATEPRESCALER_DIV128 (SPI_CR1_BR_2 | SPI_CR1_BR_1) /*!< Baud 190:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_BAUDRATEPRESCALER_DIV256 (SPI_CR1_BR_2 | SPI_CR1_BR_1 | SPI_CR1_BR_0) /*!< Baud 191:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 192:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @} 193:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 194:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 195:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_EC_BIT_ORDER Transmission Bit Order 196:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @{ 197:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 198:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_LSB_FIRST (SPI_CR1_LSBFIRST) /*!< Data is transmitted/recei 199:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_MSB_FIRST 0x00000000U /*!< Data is transmitted/recei 200:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 201:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @} 202:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 203:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 204:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_EC_TRANSFER_MODE Transfer Mode 205:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @{ 206:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 207:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_FULL_DUPLEX 0x00000000U /*!< Full-Duplex mo 208:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_SIMPLEX_RX (SPI_CR1_RXONLY) /*!< Simplex Rx mod 209:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_HALF_DUPLEX_RX (SPI_CR1_BIDIMODE) /*!< Half-Duplex Rx 210:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_HALF_DUPLEX_TX (SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE) /*!< Half-Duplex Tx 211:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 212:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @} 213:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 214:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 215:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_EC_NSS_MODE Slave Select Pin Mode ARM GAS /tmp/ccLSPxIe.s page 105 216:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @{ 217:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 218:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_NSS_SOFT (SPI_CR1_SSM) /*!< NSS managed inter 219:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_NSS_HARD_INPUT 0x00000000U /*!< NSS pin used in I 220:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_NSS_HARD_OUTPUT (((uint32_t)SPI_CR2_SSOE << 16U)) /*!< NSS pin used in O 221:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 222:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @} 223:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 224:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 225:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_EC_DATAWIDTH Datawidth 226:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @{ 227:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 228:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_DATAWIDTH_4BIT (SPI_CR2_DS_0 | SPI_CR2_DS_1) 229:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_DATAWIDTH_5BIT (SPI_CR2_DS_2) 230:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_DATAWIDTH_6BIT (SPI_CR2_DS_2 | SPI_CR2_DS_0) 231:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_DATAWIDTH_7BIT (SPI_CR2_DS_2 | SPI_CR2_DS_1) 232:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_DATAWIDTH_8BIT (SPI_CR2_DS_2 | SPI_CR2_DS_1 | SPI_CR2_DS_0) 233:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_DATAWIDTH_9BIT (SPI_CR2_DS_3) 234:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_DATAWIDTH_10BIT (SPI_CR2_DS_3 | SPI_CR2_DS_0) 235:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_DATAWIDTH_11BIT (SPI_CR2_DS_3 | SPI_CR2_DS_1) 236:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_DATAWIDTH_12BIT (SPI_CR2_DS_3 | SPI_CR2_DS_1 | SPI_CR2_DS_0) 237:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_DATAWIDTH_13BIT (SPI_CR2_DS_3 | SPI_CR2_DS_2) 238:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_DATAWIDTH_14BIT (SPI_CR2_DS_3 | SPI_CR2_DS_2 | SPI_CR2_DS_0) 239:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_DATAWIDTH_15BIT (SPI_CR2_DS_3 | SPI_CR2_DS_2 | SPI_CR2_DS_1) 240:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_DATAWIDTH_16BIT (SPI_CR2_DS_3 | SPI_CR2_DS_2 | SPI_CR2_DS_1 | SPI_CR2_DS 241:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 242:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @} 243:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 244:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #if defined(USE_FULL_LL_DRIVER) 245:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 246:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_EC_CRC_CALCULATION CRC Calculation 247:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @{ 248:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 249:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_CRCCALCULATION_DISABLE 0x00000000U /*!< CRC calculation disabled 250:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_CRCCALCULATION_ENABLE (SPI_CR1_CRCEN) /*!< CRC calculation enabled 251:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 252:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @} 253:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 254:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #endif /* USE_FULL_LL_DRIVER */ 255:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 256:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_EC_CRC_LENGTH CRC Length 257:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @{ 258:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 259:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_CRC_8BIT 0x00000000U /*!< 8-bit CRC length */ 260:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_CRC_16BIT (SPI_CR1_CRCL) /*!< 16-bit CRC length */ 261:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 262:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @} 263:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 264:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 265:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_EC_RX_FIFO_TH RX FIFO Threshold 266:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @{ 267:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 268:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_RX_FIFO_TH_HALF 0x00000000U /*!< RXNE event is generated i 269:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_RX_FIFO_TH_QUARTER (SPI_CR2_FRXTH) /*!< RXNE event is generated i 270:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 271:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @} 272:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ ARM GAS /tmp/ccLSPxIe.s page 106 273:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 274:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_EC_RX_FIFO RX FIFO Level 275:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @{ 276:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 277:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_RX_FIFO_EMPTY 0x00000000U /*!< FIFO reception em 278:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_RX_FIFO_QUARTER_FULL (SPI_SR_FRLVL_0) /*!< FIFO reception 1/ 279:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_RX_FIFO_HALF_FULL (SPI_SR_FRLVL_1) /*!< FIFO reception 1/ 280:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_RX_FIFO_FULL (SPI_SR_FRLVL_1 | SPI_SR_FRLVL_0) /*!< FIFO reception fu 281:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 282:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @} 283:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 284:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 285:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_EC_TX_FIFO TX FIFO Level 286:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @{ 287:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 288:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_TX_FIFO_EMPTY 0x00000000U /*!< FIFO transmission 289:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_TX_FIFO_QUARTER_FULL (SPI_SR_FTLVL_0) /*!< FIFO transmission 290:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_TX_FIFO_HALF_FULL (SPI_SR_FTLVL_1) /*!< FIFO transmission 291:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_TX_FIFO_FULL (SPI_SR_FTLVL_1 | SPI_SR_FTLVL_0) /*!< FIFO transmission 292:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 293:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @} 294:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 295:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 296:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_EC_DMA_PARITY DMA Parity 297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @{ 298:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 299:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_DMA_PARITY_EVEN 0x00000000U /*!< Select DMA parity Even */ 300:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_DMA_PARITY_ODD 0x00000001U /*!< Select DMA parity Odd */ 301:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 302:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 303:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @} 304:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 305:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 306:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 307:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @} 308:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 309:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 310:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /* Exported macro ------------------------------------------------------------*/ 311:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_Exported_Macros SPI Exported Macros 312:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @{ 313:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_EM_WRITE_READ Common Write and read registers Macros 316:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @{ 317:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 318:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 319:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 320:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Write a value in SPI register 321:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param __INSTANCE__ SPI Instance 322:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param __REG__ Register to be written 323:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param __VALUE__ Value to be written in the register 324:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None 325:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 326:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE 327:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 328:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 329:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Read a value in SPI register ARM GAS /tmp/ccLSPxIe.s page 107 330:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param __INSTANCE__ SPI Instance 331:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param __REG__ Register to be read 332:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval Register value 333:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 334:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) 335:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 336:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @} 337:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 338:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 339:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 340:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @} 341:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 342:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 343:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /* Exported functions --------------------------------------------------------*/ 344:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_Exported_Functions SPI Exported Functions 345:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @{ 346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 347:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 348:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_EF_Configuration Configuration 349:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @{ 350:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 351:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 352:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 353:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Enable SPI peripheral 354:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR1 SPE LL_SPI_Enable 355:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 356:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None 357:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 358:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_Enable(SPI_TypeDef *SPIx) 359:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** SET_BIT(SPIx->CR1, SPI_CR1_SPE); 361:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 362:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 363:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 364:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Disable SPI peripheral 365:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @note When disabling the SPI, follow the procedure described in the Reference Manual. 366:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR1 SPE LL_SPI_Disable 367:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 368:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None 369:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_Disable(SPI_TypeDef *SPIx) 371:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE); 373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 374:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 375:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 376:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Check if SPI peripheral is enabled 377:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR1 SPE LL_SPI_IsEnabled 378:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 379:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval State of bit (1 or 0). 380:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 381:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_IsEnabled(SPI_TypeDef *SPIx) 554 .loc 4 381 26 view .LVU202 555 .LBB364: 382:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 383:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** return ((READ_BIT(SPIx->CR1, SPI_CR1_SPE) == (SPI_CR1_SPE)) ? 1UL : 0UL); 556 .loc 4 383 3 view .LVU203 ARM GAS /tmp/ccLSPxIe.s page 108 557 .loc 4 383 12 is_stmt 0 view .LVU204 558 0000 0F4B ldr r3, .L19 559 0002 1B68 ldr r3, [r3] 560 .loc 4 383 69 view .LVU205 561 0004 13F0400F tst r3, #64 562 0008 04D0 beq .L17 563 .LVL34: 564 .loc 4 383 69 view .LVU206 565 .LBE364: 566 .LBE363: 2755:Src/main.c **** { 2756:Src/main.c **** LL_SPI_Disable(SPI2); 567 .loc 1 2756 3 is_stmt 1 view .LVU207 568 .LBB365: 569 .LBI365: 370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 570 .loc 4 370 22 view .LVU208 571 .LBB366: 372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 572 .loc 4 372 3 view .LVU209 573 000a 0D4A ldr r2, .L19 574 000c 1368 ldr r3, [r2] 575 000e 23F04003 bic r3, r3, #64 576 0012 1360 str r3, [r2] 577 .LVL35: 578 .L17: 372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 579 .loc 4 372 3 is_stmt 0 view .LVU210 580 .LBE366: 581 .LBE365: 2757:Src/main.c **** } 2758:Src/main.c **** LL_SPI_SetClockPolarity(SPI2, polarity); 582 .loc 1 2758 2 is_stmt 1 view .LVU211 583 .LBB367: 584 .LBI367: 384:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 385:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 386:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 387:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Set SPI operation mode to Master or Slave 388:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @note This bit should not be changed when communication is ongoing. 389:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR1 MSTR LL_SPI_SetMode\n 390:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * CR1 SSI LL_SPI_SetMode 391:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 392:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param Mode This parameter can be one of the following values: 393:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_MODE_MASTER 394:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_MODE_SLAVE 395:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None 396:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 397:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_SetMode(SPI_TypeDef *SPIx, uint32_t Mode) 398:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 399:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** MODIFY_REG(SPIx->CR1, SPI_CR1_MSTR | SPI_CR1_SSI, Mode); 400:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 401:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 402:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 403:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Get SPI operation mode (Master or Slave) 404:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR1 MSTR LL_SPI_GetMode\n 405:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * CR1 SSI LL_SPI_GetMode ARM GAS /tmp/ccLSPxIe.s page 109 406:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 407:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval Returned value can be one of the following values: 408:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_MODE_MASTER 409:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_MODE_SLAVE 410:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 411:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_GetMode(SPI_TypeDef *SPIx) 412:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 413:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_MSTR | SPI_CR1_SSI)); 414:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 415:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 416:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 417:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Set serial protocol used 418:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation. 419:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR2 FRF LL_SPI_SetStandard 420:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 421:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param Standard This parameter can be one of the following values: 422:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_PROTOCOL_MOTOROLA 423:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_PROTOCOL_TI 424:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None 425:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 426:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_SetStandard(SPI_TypeDef *SPIx, uint32_t Standard) 427:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** MODIFY_REG(SPIx->CR2, SPI_CR2_FRF, Standard); 429:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 430:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 431:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 432:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Get serial protocol used 433:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR2 FRF LL_SPI_GetStandard 434:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 435:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval Returned value can be one of the following values: 436:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_PROTOCOL_MOTOROLA 437:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_PROTOCOL_TI 438:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 439:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_GetStandard(SPI_TypeDef *SPIx) 440:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 441:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_FRF)); 442:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 443:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 444:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 445:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Set clock phase 446:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @note This bit should not be changed when communication is ongoing. 447:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * This bit is not used in SPI TI mode. 448:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR1 CPHA LL_SPI_SetClockPhase 449:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 450:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param ClockPhase This parameter can be one of the following values: 451:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_PHASE_1EDGE 452:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_PHASE_2EDGE 453:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None 454:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 455:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_SetClockPhase(SPI_TypeDef *SPIx, uint32_t ClockPhase) 456:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 457:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** MODIFY_REG(SPIx->CR1, SPI_CR1_CPHA, ClockPhase); 458:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 459:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 460:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 461:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Get clock phase 462:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR1 CPHA LL_SPI_GetClockPhase ARM GAS /tmp/ccLSPxIe.s page 110 463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 464:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval Returned value can be one of the following values: 465:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_PHASE_1EDGE 466:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_PHASE_2EDGE 467:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 468:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_GetClockPhase(SPI_TypeDef *SPIx) 469:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 470:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPHA)); 471:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 472:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 473:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 474:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Set clock polarity 475:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @note This bit should not be changed when communication is ongoing. 476:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * This bit is not used in SPI TI mode. 477:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR1 CPOL LL_SPI_SetClockPolarity 478:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 479:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param ClockPolarity This parameter can be one of the following values: 480:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_POLARITY_LOW 481:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_POLARITY_HIGH 482:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None 483:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 484:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPolarity) 585 .loc 4 484 22 view .LVU212 586 .LBB368: 485:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 486:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** MODIFY_REG(SPIx->CR1, SPI_CR1_CPOL, ClockPolarity); 587 .loc 4 486 3 view .LVU213 588 0014 0A4B ldr r3, .L19 589 0016 1A68 ldr r2, [r3] 590 0018 22F00202 bic r2, r2, #2 591 001c 1043 orrs r0, r0, r2 592 .LVL36: 593 .loc 4 486 3 is_stmt 0 view .LVU214 594 001e 1860 str r0, [r3] 595 .LVL37: 596 .loc 4 486 3 view .LVU215 597 .LBE368: 598 .LBE367: 2759:Src/main.c **** LL_SPI_SetClockPhase(SPI2, phase); 599 .loc 1 2759 2 is_stmt 1 view .LVU216 600 .LBB369: 601 .LBI369: 455:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 602 .loc 4 455 22 view .LVU217 603 .LBB370: 457:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 604 .loc 4 457 3 view .LVU218 605 0020 1A68 ldr r2, [r3] 606 0022 22F00102 bic r2, r2, #1 607 0026 1143 orrs r1, r1, r2 608 .LVL38: 457:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 609 .loc 4 457 3 is_stmt 0 view .LVU219 610 0028 1960 str r1, [r3] 611 .LVL39: 457:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 612 .loc 4 457 3 view .LVU220 ARM GAS /tmp/ccLSPxIe.s page 111 613 .LBE370: 614 .LBE369: 2760:Src/main.c **** if (!LL_SPI_IsEnabled(SPI2)) 615 .loc 1 2760 2 is_stmt 1 view .LVU221 616 .LBB371: 617 .LBI371: 381:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 618 .loc 4 381 26 view .LVU222 619 .LBB372: 383:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 620 .loc 4 383 3 view .LVU223 383:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 621 .loc 4 383 12 is_stmt 0 view .LVU224 622 002a 1B68 ldr r3, [r3] 383:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 623 .loc 4 383 69 view .LVU225 624 002c 13F0400F tst r3, #64 625 0030 04D1 bne .L16 626 .LVL40: 383:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 627 .loc 4 383 69 view .LVU226 628 .LBE372: 629 .LBE371: 2761:Src/main.c **** { 2762:Src/main.c **** LL_SPI_Enable(SPI2); 630 .loc 1 2762 3 is_stmt 1 view .LVU227 631 .LBB373: 632 .LBI373: 358:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 633 .loc 4 358 22 view .LVU228 634 .LBB374: 360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 635 .loc 4 360 3 view .LVU229 636 0032 034A ldr r2, .L19 637 0034 1368 ldr r3, [r2] 638 0036 43F04003 orr r3, r3, #64 639 003a 1360 str r3, [r2] 640 .LVL41: 641 .L16: 360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 642 .loc 4 360 3 is_stmt 0 view .LVU230 643 .LBE374: 644 .LBE373: 2763:Src/main.c **** } 2764:Src/main.c **** } 645 .loc 1 2764 1 view .LVU231 646 003c 7047 bx lr 647 .L20: 648 003e 00BF .align 2 649 .L19: 650 0040 00380040 .word 1073756160 651 .cfi_endproc 652 .LFE1213: 654 .section .text.PA4_DAC_Set,"ax",%progbits 655 .align 1 656 .syntax unified 657 .thumb ARM GAS /tmp/ccLSPxIe.s page 112 658 .thumb_func 660 PA4_DAC_Set: 661 .LVL42: 662 .LFB1217: 2765:Src/main.c **** 2766:Src/main.c **** static void AD9833_WriteWord(uint16_t word) 2767:Src/main.c **** { 2768:Src/main.c **** uint32_t tmp32 = 0; 2769:Src/main.c **** 2770:Src/main.c **** SPI2_SetMode(LL_SPI_POLARITY_HIGH, LL_SPI_PHASE_1EDGE); 2771:Src/main.c **** 2772:Src/main.c **** HAL_GPIO_WritePin(AD9102_CS_GPIO_Port, AD9102_CS_Pin, GPIO_PIN_SET); 2773:Src/main.c **** HAL_GPIO_WritePin(DAC_LD1_CS_GPIO_Port, DAC_LD1_CS_Pin, GPIO_PIN_SET); 2774:Src/main.c **** HAL_GPIO_WritePin(DAC_TEC1_CS_GPIO_Port, DAC_TEC1_CS_Pin, GPIO_PIN_SET); 2775:Src/main.c **** 2776:Src/main.c **** HAL_GPIO_WritePin(AD9833_CS_GPIO_Port, AD9833_CS_Pin, GPIO_PIN_RESET); 2777:Src/main.c **** 2778:Src/main.c **** while((!LL_SPI_IsActiveFlag_TXE(SPI2)) && (tmp32++ < 1000)) {} 2779:Src/main.c **** LL_SPI_TransmitData16(SPI2, word); 2780:Src/main.c **** tmp32 = 0; 2781:Src/main.c **** while((!LL_SPI_IsActiveFlag_RXNE(SPI2)) && (tmp32++ < 1000)) {} 2782:Src/main.c **** (void) SPI2->DR; 2783:Src/main.c **** 2784:Src/main.c **** HAL_GPIO_WritePin(AD9833_CS_GPIO_Port, AD9833_CS_Pin, GPIO_PIN_SET); 2785:Src/main.c **** } 2786:Src/main.c **** 2787:Src/main.c **** static void AD9833_Apply(uint8_t enable, uint8_t triangle, uint32_t freq_word) 2788:Src/main.c **** { 2789:Src/main.c **** uint16_t control = 0x2000u; // B28 = 1 2790:Src/main.c **** if (triangle) 2791:Src/main.c **** { 2792:Src/main.c **** control |= 0x0002u; // MODE = 1 (triangle) 2793:Src/main.c **** } 2794:Src/main.c **** control |= 0x0100u; // RESET = 1 while updating 2795:Src/main.c **** 2796:Src/main.c **** freq_word &= 0x0FFFFFFFu; 2797:Src/main.c **** uint16_t lsw = (uint16_t)(0x4000u | (freq_word & 0x3FFFu)); // FREQ0 LSB 2798:Src/main.c **** uint16_t msw = (uint16_t)(0x4000u | ((freq_word >> 14) & 0x3FFFu)); // FREQ0 MSB 2799:Src/main.c **** 2800:Src/main.c **** AD9833_WriteWord(control); 2801:Src/main.c **** AD9833_WriteWord(lsw); 2802:Src/main.c **** AD9833_WriteWord(msw); 2803:Src/main.c **** AD9833_WriteWord(0xC000u); // PHASE0 = 0 2804:Src/main.c **** 2805:Src/main.c **** if (enable) 2806:Src/main.c **** { 2807:Src/main.c **** control &= (uint16_t)(~0x0100u); 2808:Src/main.c **** } 2809:Src/main.c **** AD9833_WriteWord(control); 2810:Src/main.c **** } 2811:Src/main.c **** 2812:Src/main.c **** static void PA4_DAC_Init(void) 2813:Src/main.c **** { 2814:Src/main.c **** GPIO_InitTypeDef GPIO_InitStruct = {0}; 2815:Src/main.c **** 2816:Src/main.c **** __HAL_RCC_DAC_CLK_ENABLE(); 2817:Src/main.c **** __HAL_RCC_GPIOA_CLK_ENABLE(); ARM GAS /tmp/ccLSPxIe.s page 113 2818:Src/main.c **** 2819:Src/main.c **** GPIO_InitStruct.Pin = GPIO_PIN_4; 2820:Src/main.c **** GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; 2821:Src/main.c **** GPIO_InitStruct.Pull = GPIO_NOPULL; 2822:Src/main.c **** HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 2823:Src/main.c **** 2824:Src/main.c **** // Keep channel disabled until a dedicated serial command enables it. 2825:Src/main.c **** DAC->CR &= ~(DAC_CR_EN1 | DAC_CR_TEN1 | DAC_CR_DMAEN1); 2826:Src/main.c **** DAC->DHR12R1 = 0u; 2827:Src/main.c **** } 2828:Src/main.c **** 2829:Src/main.c **** static void PA4_DAC_Set(uint16_t dac_code, uint8_t enable) 2830:Src/main.c **** { 663 .loc 1 2830 1 is_stmt 1 view -0 664 .cfi_startproc 665 @ args = 0, pretend = 0, frame = 0 666 @ frame_needed = 0, uses_anonymous_args = 0 667 @ link register save eliminated. 2831:Src/main.c **** if (dac_code > STM32_DAC_CODE_MAX) 668 .loc 1 2831 2 view .LVU233 669 .loc 1 2831 5 is_stmt 0 view .LVU234 670 0000 B0F5805F cmp r0, #4096 671 0004 01D3 bcc .L22 2832:Src/main.c **** { 2833:Src/main.c **** dac_code = STM32_DAC_CODE_MAX; 672 .loc 1 2833 12 view .LVU235 673 0006 40F6FF70 movw r0, #4095 674 .LVL43: 675 .L22: 2834:Src/main.c **** } 2835:Src/main.c **** 2836:Src/main.c **** DAC->DHR12R1 = dac_code; 676 .loc 1 2836 2 is_stmt 1 view .LVU236 677 .loc 1 2836 15 is_stmt 0 view .LVU237 678 000a 074B ldr r3, .L26 679 000c 9860 str r0, [r3, #8] 2837:Src/main.c **** 2838:Src/main.c **** if (enable) 680 .loc 1 2838 2 is_stmt 1 view .LVU238 681 .loc 1 2838 5 is_stmt 0 view .LVU239 682 000e 29B1 cbz r1, .L23 2839:Src/main.c **** { 2840:Src/main.c **** DAC->CR |= DAC_CR_EN1; 683 .loc 1 2840 3 is_stmt 1 view .LVU240 684 .loc 1 2840 6 is_stmt 0 view .LVU241 685 0010 1A46 mov r2, r3 686 0012 1B68 ldr r3, [r3] 687 .loc 1 2840 11 view .LVU242 688 0014 43F00103 orr r3, r3, #1 689 0018 1360 str r3, [r2] 690 001a 7047 bx lr 691 .L23: 2841:Src/main.c **** } 2842:Src/main.c **** else 2843:Src/main.c **** { 2844:Src/main.c **** DAC->CR &= ~DAC_CR_EN1; 692 .loc 1 2844 3 is_stmt 1 view .LVU243 ARM GAS /tmp/ccLSPxIe.s page 114 693 .loc 1 2844 6 is_stmt 0 view .LVU244 694 001c 024A ldr r2, .L26 695 001e 1368 ldr r3, [r2] 696 .loc 1 2844 11 view .LVU245 697 0020 23F00103 bic r3, r3, #1 698 0024 1360 str r3, [r2] 2845:Src/main.c **** } 2846:Src/main.c **** } 699 .loc 1 2846 1 view .LVU246 700 0026 7047 bx lr 701 .L27: 702 .align 2 703 .L26: 704 0028 00740040 .word 1073771520 705 .cfi_endproc 706 .LFE1217: 708 .section .text.AD9102_ResetWaveUploadState,"ax",%progbits 709 .align 1 710 .syntax unified 711 .thumb 712 .thumb_func 714 AD9102_ResetWaveUploadState: 715 .LFB1222: 2847:Src/main.c **** 2848:Src/main.c **** static void DS1809_Pulse(uint8_t uc, uint8_t dc, uint16_t count, uint16_t pulse_ms) 2849:Src/main.c **** { 2850:Src/main.c **** for (uint16_t i = 0; i < count; i++) 2851:Src/main.c **** { 2852:Src/main.c **** if (uc) 2853:Src/main.c **** { 2854:Src/main.c **** HAL_GPIO_WritePin(DS1809_UC_GPIO_Port, DS1809_UC_Pin, GPIO_PIN_RESET); 2855:Src/main.c **** } 2856:Src/main.c **** if (dc) 2857:Src/main.c **** { 2858:Src/main.c **** HAL_GPIO_WritePin(DS1809_DC_GPIO_Port, DS1809_DC_Pin, GPIO_PIN_RESET); 2859:Src/main.c **** } 2860:Src/main.c **** HAL_Delay(pulse_ms); 2861:Src/main.c **** if (uc) 2862:Src/main.c **** { 2863:Src/main.c **** HAL_GPIO_WritePin(DS1809_UC_GPIO_Port, DS1809_UC_Pin, GPIO_PIN_SET); 2864:Src/main.c **** } 2865:Src/main.c **** if (dc) 2866:Src/main.c **** { 2867:Src/main.c **** HAL_GPIO_WritePin(DS1809_DC_GPIO_Port, DS1809_DC_Pin, GPIO_PIN_SET); 2868:Src/main.c **** } 2869:Src/main.c **** HAL_Delay(pulse_ms); 2870:Src/main.c **** } 2871:Src/main.c **** } 2872:Src/main.c **** 2873:Src/main.c **** static void AD9102_WriteReg(uint16_t addr, uint16_t value) 2874:Src/main.c **** { 2875:Src/main.c **** uint32_t tmp32 = 0; 2876:Src/main.c **** uint16_t cmd = (uint16_t)(addr & 0x7FFFu); // R/W = 0 (write), 15-bit address 2877:Src/main.c **** 2878:Src/main.c **** SPI2_SetMode(LL_SPI_POLARITY_LOW, LL_SPI_PHASE_1EDGE); 2879:Src/main.c **** 2880:Src/main.c **** HAL_GPIO_WritePin(DAC_LD1_CS_GPIO_Port, DAC_LD1_CS_Pin, GPIO_PIN_SET); ARM GAS /tmp/ccLSPxIe.s page 115 2881:Src/main.c **** HAL_GPIO_WritePin(DAC_TEC1_CS_GPIO_Port, DAC_TEC1_CS_Pin, GPIO_PIN_SET); 2882:Src/main.c **** 2883:Src/main.c **** if (!LL_SPI_IsEnabled(SPI2)) 2884:Src/main.c **** { 2885:Src/main.c **** LL_SPI_Enable(SPI2); 2886:Src/main.c **** } 2887:Src/main.c **** 2888:Src/main.c **** HAL_GPIO_WritePin(AD9102_CS_GPIO_Port, AD9102_CS_Pin, GPIO_PIN_RESET); 2889:Src/main.c **** 2890:Src/main.c **** while((!LL_SPI_IsActiveFlag_TXE(SPI2)) && (tmp32++ < 1000)) {} 2891:Src/main.c **** LL_SPI_TransmitData16(SPI2, cmd); 2892:Src/main.c **** tmp32 = 0; 2893:Src/main.c **** while((!LL_SPI_IsActiveFlag_RXNE(SPI2)) && (tmp32++ < 1000)) {} 2894:Src/main.c **** (void) SPI2->DR; 2895:Src/main.c **** 2896:Src/main.c **** tmp32 = 0; 2897:Src/main.c **** while((!LL_SPI_IsActiveFlag_TXE(SPI2)) && (tmp32++ < 1000)) {} 2898:Src/main.c **** LL_SPI_TransmitData16(SPI2, value); 2899:Src/main.c **** tmp32 = 0; 2900:Src/main.c **** while((!LL_SPI_IsActiveFlag_RXNE(SPI2)) && (tmp32++ < 1000)) {} 2901:Src/main.c **** (void) SPI2->DR; 2902:Src/main.c **** 2903:Src/main.c **** HAL_GPIO_WritePin(AD9102_CS_GPIO_Port, AD9102_CS_Pin, GPIO_PIN_SET); 2904:Src/main.c **** } 2905:Src/main.c **** 2906:Src/main.c **** static uint16_t AD9102_ReadReg(uint16_t addr) 2907:Src/main.c **** { 2908:Src/main.c **** uint32_t tmp32 = 0; 2909:Src/main.c **** uint16_t cmd = (uint16_t)(0x8000u | (addr & 0x7FFFu)); // R/W = 1 (read) 2910:Src/main.c **** uint16_t value; 2911:Src/main.c **** 2912:Src/main.c **** SPI2_SetMode(LL_SPI_POLARITY_LOW, LL_SPI_PHASE_1EDGE); 2913:Src/main.c **** 2914:Src/main.c **** HAL_GPIO_WritePin(DAC_LD1_CS_GPIO_Port, DAC_LD1_CS_Pin, GPIO_PIN_SET); 2915:Src/main.c **** HAL_GPIO_WritePin(DAC_TEC1_CS_GPIO_Port, DAC_TEC1_CS_Pin, GPIO_PIN_SET); 2916:Src/main.c **** 2917:Src/main.c **** if (!LL_SPI_IsEnabled(SPI2)) 2918:Src/main.c **** { 2919:Src/main.c **** LL_SPI_Enable(SPI2); 2920:Src/main.c **** } 2921:Src/main.c **** 2922:Src/main.c **** HAL_GPIO_WritePin(AD9102_CS_GPIO_Port, AD9102_CS_Pin, GPIO_PIN_RESET); 2923:Src/main.c **** 2924:Src/main.c **** while((!LL_SPI_IsActiveFlag_TXE(SPI2)) && (tmp32++ < 1000)) {} 2925:Src/main.c **** LL_SPI_TransmitData16(SPI2, cmd); 2926:Src/main.c **** tmp32 = 0; 2927:Src/main.c **** while((!LL_SPI_IsActiveFlag_RXNE(SPI2)) && (tmp32++ < 1000)) {} 2928:Src/main.c **** (void) SPI2->DR; 2929:Src/main.c **** 2930:Src/main.c **** tmp32 = 0; 2931:Src/main.c **** while((!LL_SPI_IsActiveFlag_TXE(SPI2)) && (tmp32++ < 1000)) {} 2932:Src/main.c **** LL_SPI_TransmitData16(SPI2, 0x0000u); 2933:Src/main.c **** tmp32 = 0; 2934:Src/main.c **** while((!LL_SPI_IsActiveFlag_RXNE(SPI2)) && (tmp32++ < 1000)) {} 2935:Src/main.c **** value = LL_SPI_ReceiveData16(SPI2); 2936:Src/main.c **** 2937:Src/main.c **** HAL_GPIO_WritePin(AD9102_CS_GPIO_Port, AD9102_CS_Pin, GPIO_PIN_SET); ARM GAS /tmp/ccLSPxIe.s page 116 2938:Src/main.c **** return value; 2939:Src/main.c **** } 2940:Src/main.c **** 2941:Src/main.c **** static void AD9102_WriteRegTable(const uint16_t *values, uint16_t count) 2942:Src/main.c **** { 2943:Src/main.c **** for (uint16_t i = 0; i < count; i++) 2944:Src/main.c **** { 2945:Src/main.c **** AD9102_WriteReg(ad9102_reg_addr[i], values[i]); 2946:Src/main.c **** } 2947:Src/main.c **** } 2948:Src/main.c **** 2949:Src/main.c **** static void AD9102_ResetWaveUploadState(void) 2950:Src/main.c **** { 716 .loc 1 2950 1 is_stmt 1 view -0 717 .cfi_startproc 718 @ args = 0, pretend = 0, frame = 0 719 @ frame_needed = 0, uses_anonymous_args = 0 720 @ link register save eliminated. 2951:Src/main.c **** ad9102_wave_upload_active = 0u; 721 .loc 1 2951 2 view .LVU248 722 .loc 1 2951 28 is_stmt 0 view .LVU249 723 0000 0023 movs r3, #0 724 0002 034A ldr r2, .L29 725 0004 1370 strb r3, [r2] 2952:Src/main.c **** ad9102_wave_expected_samples = 0u; 726 .loc 1 2952 2 is_stmt 1 view .LVU250 727 .loc 1 2952 31 is_stmt 0 view .LVU251 728 0006 034A ldr r2, .L29+4 729 0008 1380 strh r3, [r2] @ movhi 2953:Src/main.c **** ad9102_wave_written_samples = 0u; 730 .loc 1 2953 2 is_stmt 1 view .LVU252 731 .loc 1 2953 30 is_stmt 0 view .LVU253 732 000a 034A ldr r2, .L29+8 733 000c 1380 strh r3, [r2] @ movhi 2954:Src/main.c **** } 734 .loc 1 2954 1 view .LVU254 735 000e 7047 bx lr 736 .L30: 737 .align 2 738 .L29: 739 0010 00000000 .word ad9102_wave_upload_active 740 0014 00000000 .word ad9102_wave_expected_samples 741 0018 00000000 .word ad9102_wave_written_samples 742 .cfi_endproc 743 .LFE1222: 745 .section .text.PID_Controller_Temp,"ax",%progbits 746 .align 1 747 .syntax unified 748 .thumb 749 .thumb_func 751 PID_Controller_Temp: 752 .LVL44: 753 .LFB1239: 2955:Src/main.c **** 2956:Src/main.c **** static void AD9102_StopOutput(void) 2957:Src/main.c **** { 2958:Src/main.c **** AD9102_WriteReg(AD9102_REG_PAT_STATUS, 0x0000u); ARM GAS /tmp/ccLSPxIe.s page 117 2959:Src/main.c **** HAL_GPIO_WritePin(AD9102_TRIG_GPIO_Port, AD9102_TRIG_Pin, GPIO_PIN_SET); 2960:Src/main.c **** } 2961:Src/main.c **** 2962:Src/main.c **** static void AD9102_StartOutput(void) 2963:Src/main.c **** { 2964:Src/main.c **** HAL_GPIO_WritePin(AD9102_TRIG_GPIO_Port, AD9102_TRIG_Pin, GPIO_PIN_SET); 2965:Src/main.c **** AD9102_WriteReg(AD9102_REG_PAT_STATUS, AD9102_PAT_STATUS_RUN); 2966:Src/main.c **** AD9102_WriteReg(AD9102_REG_RAMUPDATE, 0x0001u); 2967:Src/main.c **** for (volatile uint32_t d = 0; d < 1000; d++) {} 2968:Src/main.c **** HAL_GPIO_WritePin(AD9102_TRIG_GPIO_Port, AD9102_TRIG_Pin, GPIO_PIN_RESET); 2969:Src/main.c **** } 2970:Src/main.c **** 2971:Src/main.c **** static void AD9102_ConfigureSramPlayback(uint16_t samples, uint8_t hold) 2972:Src/main.c **** { 2973:Src/main.c **** uint16_t pat_timebase; 2974:Src/main.c **** uint32_t pat_period; 2975:Src/main.c **** 2976:Src/main.c **** if (samples < 2u) 2977:Src/main.c **** { 2978:Src/main.c **** samples = 2u; 2979:Src/main.c **** } 2980:Src/main.c **** if (samples > AD9102_SRAM_MAX_SAMPLES) 2981:Src/main.c **** { 2982:Src/main.c **** samples = AD9102_SRAM_MAX_SAMPLES; 2983:Src/main.c **** } 2984:Src/main.c **** if (hold == 0u) 2985:Src/main.c **** { 2986:Src/main.c **** hold = AD9102_SRAM_HOLD_DEFAULT; 2987:Src/main.c **** } 2988:Src/main.c **** if (hold > 0x0Fu) 2989:Src/main.c **** { 2990:Src/main.c **** hold = 0x0Fu; 2991:Src/main.c **** } 2992:Src/main.c **** 2993:Src/main.c **** pat_timebase = (uint16_t)(((uint16_t)(hold & 0x0Fu) << 8) | 2994:Src/main.c **** ((AD9102_SRAM_PAT_PERIOD_BASE_DEFAULT & 0x0Fu) << 4) | 2995:Src/main.c **** (AD9102_SRAM_START_DELAY_BASE_DEFAULT & 0x0Fu)); 2996:Src/main.c **** pat_period = (uint32_t)samples * (uint32_t)(hold & 0x0Fu); 2997:Src/main.c **** if (pat_period == 0u) 2998:Src/main.c **** { 2999:Src/main.c **** pat_period = samples; 3000:Src/main.c **** } 3001:Src/main.c **** if (pat_period > 0xFFFFu) 3002:Src/main.c **** { 3003:Src/main.c **** pat_period = 0xFFFFu; 3004:Src/main.c **** } 3005:Src/main.c **** 3006:Src/main.c **** AD9102_WriteRegTable(ad9102_example2_regval, AD9102_REG_COUNT); 3007:Src/main.c **** AD9102_StopOutput(); 3008:Src/main.c **** AD9102_WriteReg(AD9102_REG_WAV_CONFIG, AD9102_EX2_WAV_CONFIG); 3009:Src/main.c **** AD9102_WriteReg(AD9102_REG_SAW_CONFIG, AD9102_EX2_SAW_CONFIG); 3010:Src/main.c **** AD9102_WriteReg(AD9102_REG_DAC_PAT, AD9102_EX2_DAC_PAT); 3011:Src/main.c **** AD9102_WriteReg(AD9102_REG_PAT_TIMEBASE, pat_timebase); 3012:Src/main.c **** AD9102_WriteReg(AD9102_REG_PAT_PERIOD, (uint16_t)pat_period); 3013:Src/main.c **** AD9102_WriteReg(AD9102_REG_PAT_TYPE, 0x0000u); // continuous pattern repeat 3014:Src/main.c **** AD9102_WriteReg(AD9102_REG_START_DLY, AD9102_SRAM_START_DLY_DEFAULT); 3015:Src/main.c **** AD9102_WriteReg(AD9102_REG_START_ADDR, 0x0000u); ARM GAS /tmp/ccLSPxIe.s page 118 3016:Src/main.c **** AD9102_WriteReg(AD9102_REG_STOP_ADDR, (uint16_t)((samples - 1u) << 4)); 3017:Src/main.c **** AD9102_WriteReg(AD9102_REG_RAMUPDATE, 0x0001u); 3018:Src/main.c **** } 3019:Src/main.c **** 3020:Src/main.c **** static uint8_t AD9102_BeginWaveUpload(uint16_t samples) 3021:Src/main.c **** { 3022:Src/main.c **** if ((samples < 2u) || (samples > AD9102_SRAM_MAX_SAMPLES)) 3023:Src/main.c **** { 3024:Src/main.c **** return 0u; 3025:Src/main.c **** } 3026:Src/main.c **** 3027:Src/main.c **** AD9102_StopOutput(); 3028:Src/main.c **** AD9102_ResetWaveUploadState(); 3029:Src/main.c **** AD9102_ConfigureSramPlayback(samples, AD9102_SRAM_HOLD_DEFAULT); 3030:Src/main.c **** AD9102_WriteReg(AD9102_REG_PAT_STATUS, 0x0004u); // enable SRAM access 3031:Src/main.c **** 3032:Src/main.c **** ad9102_wave_expected_samples = samples; 3033:Src/main.c **** ad9102_wave_written_samples = 0u; 3034:Src/main.c **** ad9102_wave_upload_active = 1u; 3035:Src/main.c **** return 1u; 3036:Src/main.c **** } 3037:Src/main.c **** 3038:Src/main.c **** static uint8_t AD9102_WriteWaveUploadChunk(const uint16_t *samples, uint16_t chunk_count) 3039:Src/main.c **** { 3040:Src/main.c **** if (ad9102_wave_upload_active == 0u) 3041:Src/main.c **** { 3042:Src/main.c **** return 0u; 3043:Src/main.c **** } 3044:Src/main.c **** if ((chunk_count == 0u) || (chunk_count > AD9102_WAVE_MAX_CHUNK_SAMPLES)) 3045:Src/main.c **** { 3046:Src/main.c **** return 0u; 3047:Src/main.c **** } 3048:Src/main.c **** if (((uint32_t)ad9102_wave_written_samples + (uint32_t)chunk_count) > (uint32_t)ad9102_wave_expect 3049:Src/main.c **** { 3050:Src/main.c **** return 0u; 3051:Src/main.c **** } 3052:Src/main.c **** 3053:Src/main.c **** for (uint16_t i = 0; i < chunk_count; i++) 3054:Src/main.c **** { 3055:Src/main.c **** int16_t sample = (int16_t)samples[i]; 3056:Src/main.c **** uint16_t sample_u14; 3057:Src/main.c **** uint16_t word; 3058:Src/main.c **** 3059:Src/main.c **** if ((sample < AD9102_SRAM_RAMP_MIN) || (sample > AD9102_SRAM_RAMP_MAX)) 3060:Src/main.c **** { 3061:Src/main.c **** return 0u; 3062:Src/main.c **** } 3063:Src/main.c **** 3064:Src/main.c **** sample_u14 = ((uint16_t)sample) & 0x3FFFu; 3065:Src/main.c **** word = (uint16_t)(sample_u14 << 2); 3066:Src/main.c **** AD9102_WriteReg((uint16_t)(AD9102_REG_SRAM_DATA_BASE + ad9102_wave_written_samples + i), word); 3067:Src/main.c **** } 3068:Src/main.c **** 3069:Src/main.c **** ad9102_wave_written_samples = (uint16_t)(ad9102_wave_written_samples + chunk_count); 3070:Src/main.c **** return 1u; 3071:Src/main.c **** } 3072:Src/main.c **** ARM GAS /tmp/ccLSPxIe.s page 119 3073:Src/main.c **** static uint16_t AD9102_CommitWaveUpload(uint8_t *ok) 3074:Src/main.c **** { 3075:Src/main.c **** uint16_t pat_status; 3076:Src/main.c **** 3077:Src/main.c **** if (ok != NULL) 3078:Src/main.c **** { 3079:Src/main.c **** *ok = 0u; 3080:Src/main.c **** } 3081:Src/main.c **** 3082:Src/main.c **** if ((ad9102_wave_upload_active == 0u) || 3083:Src/main.c **** (ad9102_wave_expected_samples < 2u) || 3084:Src/main.c **** (ad9102_wave_written_samples != ad9102_wave_expected_samples)) 3085:Src/main.c **** { 3086:Src/main.c **** AD9102_CancelWaveUpload(); 3087:Src/main.c **** return AD9102_ReadReg(AD9102_REG_PAT_STATUS); 3088:Src/main.c **** } 3089:Src/main.c **** 3090:Src/main.c **** AD9102_WriteReg(AD9102_REG_PAT_STATUS, 0x0000u); // disable SRAM access 3091:Src/main.c **** AD9102_WriteReg(AD9102_REG_START_ADDR, 0x0000u); 3092:Src/main.c **** AD9102_WriteReg(AD9102_REG_STOP_ADDR, (uint16_t)((ad9102_wave_expected_samples - 1u) << 4)); 3093:Src/main.c **** AD9102_WriteReg(AD9102_REG_RAMUPDATE, 0x0001u); 3094:Src/main.c **** AD9102_StartOutput(); 3095:Src/main.c **** pat_status = AD9102_ReadReg(AD9102_REG_PAT_STATUS); 3096:Src/main.c **** 3097:Src/main.c **** AD9102_ResetWaveUploadState(); 3098:Src/main.c **** if (ok != NULL) 3099:Src/main.c **** { 3100:Src/main.c **** *ok = 1u; 3101:Src/main.c **** } 3102:Src/main.c **** 3103:Src/main.c **** return pat_status; 3104:Src/main.c **** } 3105:Src/main.c **** 3106:Src/main.c **** static void AD9102_CancelWaveUpload(void) 3107:Src/main.c **** { 3108:Src/main.c **** if (ad9102_wave_upload_active != 0u) 3109:Src/main.c **** { 3110:Src/main.c **** AD9102_StopOutput(); 3111:Src/main.c **** } 3112:Src/main.c **** AD9102_ResetWaveUploadState(); 3113:Src/main.c **** } 3114:Src/main.c **** 3115:Src/main.c **** static uint16_t AD9102_Apply(uint8_t saw_type, uint8_t enable, uint8_t saw_step, uint8_t pat_base, 3116:Src/main.c **** { 3117:Src/main.c **** AD9102_ResetWaveUploadState(); 3118:Src/main.c **** 3119:Src/main.c **** if (enable) 3120:Src/main.c **** { 3121:Src/main.c **** uint16_t saw_cfg; 3122:Src/main.c **** uint16_t pat_timebase; 3123:Src/main.c **** 3124:Src/main.c **** if (saw_step == 0u) 3125:Src/main.c **** { 3126:Src/main.c **** saw_step = AD9102_SAW_STEP_DEFAULT; 3127:Src/main.c **** } 3128:Src/main.c **** if (saw_step > 63u) 3129:Src/main.c **** { ARM GAS /tmp/ccLSPxIe.s page 120 3130:Src/main.c **** saw_step = 63u; 3131:Src/main.c **** } 3132:Src/main.c **** saw_cfg = (uint16_t)(((uint16_t)(saw_step & 0x3Fu) << 2) | 3133:Src/main.c **** ((uint16_t)(saw_type & 0x3u))); 3134:Src/main.c **** pat_timebase = (uint16_t)(((AD9102_PAT_TIMEBASE_HOLD_DEFAULT & 0x0Fu) << 8) | 3135:Src/main.c **** ((pat_base & 0x0Fu) << 4) | 3136:Src/main.c **** (AD9102_START_DELAY_BASE_DEFAULT & 0x0Fu)); 3137:Src/main.c **** 3138:Src/main.c **** AD9102_WriteReg(AD9102_REG_WAV_CONFIG, AD9102_EX4_WAV_CONFIG); 3139:Src/main.c **** AD9102_WriteReg(AD9102_REG_SAW_CONFIG, saw_cfg); 3140:Src/main.c **** AD9102_WriteReg(AD9102_REG_PAT_TIMEBASE, pat_timebase); 3141:Src/main.c **** AD9102_WriteReg(AD9102_REG_PAT_PERIOD, pat_period); 3142:Src/main.c **** AD9102_WriteReg(AD9102_REG_PAT_TYPE, 0x0000u); // continuous pattern repeat 3143:Src/main.c **** 3144:Src/main.c **** AD9102_StartOutput(); 3145:Src/main.c **** } 3146:Src/main.c **** else 3147:Src/main.c **** { 3148:Src/main.c **** AD9102_StopOutput(); 3149:Src/main.c **** } 3150:Src/main.c **** 3151:Src/main.c **** return AD9102_ReadReg(AD9102_REG_PAT_STATUS); 3152:Src/main.c **** } 3153:Src/main.c **** 3154:Src/main.c **** static void AD9102_LoadSramRamp(uint16_t samples, uint8_t triangle, uint16_t amplitude) 3155:Src/main.c **** { 3156:Src/main.c **** if (samples < 2u) 3157:Src/main.c **** { 3158:Src/main.c **** samples = 2u; 3159:Src/main.c **** } 3160:Src/main.c **** if (samples > AD9102_SRAM_MAX_SAMPLES) 3161:Src/main.c **** { 3162:Src/main.c **** samples = AD9102_SRAM_MAX_SAMPLES; 3163:Src/main.c **** } 3164:Src/main.c **** if (amplitude > AD9102_SRAM_AMP_DEFAULT) 3165:Src/main.c **** { 3166:Src/main.c **** amplitude = AD9102_SRAM_AMP_DEFAULT; 3167:Src/main.c **** } 3168:Src/main.c **** 3169:Src/main.c **** // Enable SRAM access. 3170:Src/main.c **** AD9102_WriteReg(AD9102_REG_PAT_STATUS, 0x0004u); 3171:Src/main.c **** 3172:Src/main.c **** for (uint16_t i = 0; i < samples; i++) 3173:Src/main.c **** { 3174:Src/main.c **** int32_t value; 3175:Src/main.c **** int32_t min_val = -(int32_t)amplitude; 3176:Src/main.c **** int32_t max_val = (int32_t)amplitude; 3177:Src/main.c **** int32_t span = max_val - min_val; 3178:Src/main.c **** if (triangle) 3179:Src/main.c **** { 3180:Src/main.c **** uint16_t half = samples / 2u; 3181:Src/main.c **** if (half == 0u) 3182:Src/main.c **** { 3183:Src/main.c **** half = 1u; 3184:Src/main.c **** } 3185:Src/main.c **** if (i < half) 3186:Src/main.c **** { ARM GAS /tmp/ccLSPxIe.s page 121 3187:Src/main.c **** uint16_t denom = (half > 1u) ? (uint16_t)(half - 1u) : 1u; 3188:Src/main.c **** if (span == 0) 3189:Src/main.c **** { 3190:Src/main.c **** value = 0; 3191:Src/main.c **** } 3192:Src/main.c **** else 3193:Src/main.c **** { 3194:Src/main.c **** value = min_val + (span * (int32_t)i) / (int32_t)denom; 3195:Src/main.c **** } 3196:Src/main.c **** } 3197:Src/main.c **** else 3198:Src/main.c **** { 3199:Src/main.c **** uint16_t tail = (uint16_t)(samples - half); 3200:Src/main.c **** uint16_t denom = (tail > 1u) ? (uint16_t)(tail - 1u) : 1u; 3201:Src/main.c **** if (span == 0) 3202:Src/main.c **** { 3203:Src/main.c **** value = 0; 3204:Src/main.c **** } 3205:Src/main.c **** else 3206:Src/main.c **** { 3207:Src/main.c **** value = max_val - (span * (int32_t)(i - half)) / (int32_t)denom; 3208:Src/main.c **** } 3209:Src/main.c **** } 3210:Src/main.c **** } 3211:Src/main.c **** else 3212:Src/main.c **** { 3213:Src/main.c **** uint16_t denom = (samples > 1u) ? (uint16_t)(samples - 1u) : 1u; 3214:Src/main.c **** if (span == 0) 3215:Src/main.c **** { 3216:Src/main.c **** value = 0; 3217:Src/main.c **** } 3218:Src/main.c **** else 3219:Src/main.c **** { 3220:Src/main.c **** value = min_val + (span * (int32_t)i) / (int32_t)denom; 3221:Src/main.c **** } 3222:Src/main.c **** } 3223:Src/main.c **** 3224:Src/main.c **** if (value < AD9102_SRAM_RAMP_MIN) 3225:Src/main.c **** { 3226:Src/main.c **** value = AD9102_SRAM_RAMP_MIN; 3227:Src/main.c **** } 3228:Src/main.c **** else if (value > AD9102_SRAM_RAMP_MAX) 3229:Src/main.c **** { 3230:Src/main.c **** value = AD9102_SRAM_RAMP_MAX; 3231:Src/main.c **** } 3232:Src/main.c **** 3233:Src/main.c **** uint16_t sample_u14 = (uint16_t)((int16_t)value) & 0x3FFFu; 3234:Src/main.c **** uint16_t word = (uint16_t)(sample_u14 << 2); 3235:Src/main.c **** AD9102_WriteReg((uint16_t)(AD9102_REG_SRAM_DATA_BASE + i), word); 3236:Src/main.c **** } 3237:Src/main.c **** 3238:Src/main.c **** // Disable SRAM access. 3239:Src/main.c **** AD9102_WriteReg(AD9102_REG_PAT_STATUS, 0x0000u); 3240:Src/main.c **** } 3241:Src/main.c **** 3242:Src/main.c **** static uint16_t AD9102_ApplySram(uint8_t enable, uint16_t samples, uint8_t hold, uint8_t triangle, 3243:Src/main.c **** { ARM GAS /tmp/ccLSPxIe.s page 122 3244:Src/main.c **** AD9102_ResetWaveUploadState(); 3245:Src/main.c **** 3246:Src/main.c **** if (samples == 0u) 3247:Src/main.c **** { 3248:Src/main.c **** samples = AD9102_SRAM_SAMPLES_DEFAULT; 3249:Src/main.c **** } 3250:Src/main.c **** if (samples < 2u) 3251:Src/main.c **** { 3252:Src/main.c **** samples = 2u; 3253:Src/main.c **** } 3254:Src/main.c **** if (samples > AD9102_SRAM_MAX_SAMPLES) 3255:Src/main.c **** { 3256:Src/main.c **** samples = AD9102_SRAM_MAX_SAMPLES; 3257:Src/main.c **** } 3258:Src/main.c **** if (hold == 0u) 3259:Src/main.c **** { 3260:Src/main.c **** hold = AD9102_SRAM_HOLD_DEFAULT; 3261:Src/main.c **** } 3262:Src/main.c **** if (hold > 0x0Fu) 3263:Src/main.c **** { 3264:Src/main.c **** hold = 0x0Fu; 3265:Src/main.c **** } 3266:Src/main.c **** 3267:Src/main.c **** if (amplitude > AD9102_SRAM_AMP_DEFAULT) 3268:Src/main.c **** { 3269:Src/main.c **** amplitude = AD9102_SRAM_AMP_DEFAULT; 3270:Src/main.c **** } 3271:Src/main.c **** 3272:Src/main.c **** AD9102_ConfigureSramPlayback(samples, hold); 3273:Src/main.c **** AD9102_LoadSramRamp(samples, triangle, amplitude); 3274:Src/main.c **** 3275:Src/main.c **** if (enable) 3276:Src/main.c **** { 3277:Src/main.c **** AD9102_StartOutput(); 3278:Src/main.c **** } 3279:Src/main.c **** else 3280:Src/main.c **** { 3281:Src/main.c **** AD9102_StopOutput(); 3282:Src/main.c **** } 3283:Src/main.c **** 3284:Src/main.c **** return AD9102_ReadReg(AD9102_REG_PAT_STATUS); 3285:Src/main.c **** } 3286:Src/main.c **** 3287:Src/main.c **** static uint8_t AD9102_CheckFlags(uint16_t pat_status, uint8_t expect_run, uint8_t saw_type, uint8_t 3288:Src/main.c **** { 3289:Src/main.c **** uint16_t spiconfig = AD9102_ReadReg(AD9102_REG_SPICONFIG); 3290:Src/main.c **** uint16_t powercfg = AD9102_ReadReg(AD9102_REG_POWERCONFIG); 3291:Src/main.c **** uint16_t clockcfg = AD9102_ReadReg(AD9102_REG_CLOCKCONFIG); 3292:Src/main.c **** uint16_t cfg_err = AD9102_ReadReg(AD9102_REG_CFG_ERROR); 3293:Src/main.c **** uint16_t pat_timebase = (uint16_t)(((AD9102_PAT_TIMEBASE_HOLD_DEFAULT & 0x0Fu) << 8) | 3294:Src/main.c **** ((pat_base & 0x0Fu) << 4) | 3295:Src/main.c **** (AD9102_START_DELAY_BASE_DEFAULT & 0x0Fu)); 3296:Src/main.c **** 3297:Src/main.c **** if (saw_step == 0u) 3298:Src/main.c **** { 3299:Src/main.c **** saw_step = AD9102_SAW_STEP_DEFAULT; 3300:Src/main.c **** } ARM GAS /tmp/ccLSPxIe.s page 123 3301:Src/main.c **** if (saw_step > 63u) 3302:Src/main.c **** { 3303:Src/main.c **** saw_step = 63u; 3304:Src/main.c **** } 3305:Src/main.c **** if (pat_period == 0u) 3306:Src/main.c **** { 3307:Src/main.c **** pat_period = AD9102_PAT_PERIOD_DEFAULT; 3308:Src/main.c **** } 3309:Src/main.c **** uint16_t expect_saw = (uint16_t)(((uint16_t)(saw_step & 0x3Fu) << 2) | 3310:Src/main.c **** ((uint16_t)(saw_type & 0x3u))); 3311:Src/main.c **** 3312:Src/main.c **** uint8_t ok = 1u; 3313:Src/main.c **** 3314:Src/main.c **** // Expect default SPI config: MSB-first, 4-wire, no double SPI, no reset. 3315:Src/main.c **** if (spiconfig != 0x0000u) 3316:Src/main.c **** { 3317:Src/main.c **** ok = 0u; 3318:Src/main.c **** } 3319:Src/main.c **** 3320:Src/main.c **** // Power blocks should not be powered down. 3321:Src/main.c **** if (powercfg & ((1u << 8) | (1u << 7) | (1u << 6) | (1u << 5) | (1u << 3))) 3322:Src/main.c **** { 3323:Src/main.c **** ok = 0u; 3324:Src/main.c **** } 3325:Src/main.c **** 3326:Src/main.c **** // Clock receiver must be enabled (cannot directly detect external clock presence). 3327:Src/main.c **** if (clockcfg & ((1u << 11) | (1u << 7) | (1u << 6) | (1u << 5))) 3328:Src/main.c **** { 3329:Src/main.c **** ok = 0u; 3330:Src/main.c **** } 3331:Src/main.c **** 3332:Src/main.c **** // Any configuration error flags indicate a bad setup. 3333:Src/main.c **** if (cfg_err & 0x003Fu) 3334:Src/main.c **** { 3335:Src/main.c **** ok = 0u; 3336:Src/main.c **** } 3337:Src/main.c **** 3338:Src/main.c **** if (expect_run && ((pat_status & AD9102_PAT_STATUS_RUN) == 0u)) 3339:Src/main.c **** { 3340:Src/main.c **** ok = 0u; 3341:Src/main.c **** } 3342:Src/main.c **** 3343:Src/main.c **** if (AD9102_ReadReg(AD9102_REG_WAV_CONFIG) != AD9102_EX4_WAV_CONFIG) 3344:Src/main.c **** { 3345:Src/main.c **** ok = 0u; 3346:Src/main.c **** } 3347:Src/main.c **** if (AD9102_ReadReg(AD9102_REG_PAT_TIMEBASE) != pat_timebase) 3348:Src/main.c **** { 3349:Src/main.c **** ok = 0u; 3350:Src/main.c **** } 3351:Src/main.c **** if (AD9102_ReadReg(AD9102_REG_PAT_PERIOD) != pat_period) 3352:Src/main.c **** { 3353:Src/main.c **** ok = 0u; 3354:Src/main.c **** } 3355:Src/main.c **** if (AD9102_ReadReg(AD9102_REG_PAT_TYPE) != 0x0000u) 3356:Src/main.c **** { 3357:Src/main.c **** ok = 0u; ARM GAS /tmp/ccLSPxIe.s page 124 3358:Src/main.c **** } 3359:Src/main.c **** if (AD9102_ReadReg(AD9102_REG_SAW_CONFIG) != expect_saw) 3360:Src/main.c **** { 3361:Src/main.c **** ok = 0u; 3362:Src/main.c **** } 3363:Src/main.c **** 3364:Src/main.c **** return (ok ? 0u : 1u); 3365:Src/main.c **** } 3366:Src/main.c **** 3367:Src/main.c **** static uint8_t AD9102_CheckFlagsSram(uint16_t pat_status, uint8_t expect_run, uint16_t samples, uin 3368:Src/main.c **** { 3369:Src/main.c **** uint16_t spiconfig = AD9102_ReadReg(AD9102_REG_SPICONFIG); 3370:Src/main.c **** uint16_t powercfg = AD9102_ReadReg(AD9102_REG_POWERCONFIG); 3371:Src/main.c **** uint16_t clockcfg = AD9102_ReadReg(AD9102_REG_CLOCKCONFIG); 3372:Src/main.c **** uint16_t cfg_err = AD9102_ReadReg(AD9102_REG_CFG_ERROR); 3373:Src/main.c **** 3374:Src/main.c **** if (samples == 0u) 3375:Src/main.c **** { 3376:Src/main.c **** samples = AD9102_SRAM_SAMPLES_DEFAULT; 3377:Src/main.c **** } 3378:Src/main.c **** if (samples < 2u) 3379:Src/main.c **** { 3380:Src/main.c **** samples = 2u; 3381:Src/main.c **** } 3382:Src/main.c **** if (samples > AD9102_SRAM_MAX_SAMPLES) 3383:Src/main.c **** { 3384:Src/main.c **** samples = AD9102_SRAM_MAX_SAMPLES; 3385:Src/main.c **** } 3386:Src/main.c **** if (hold == 0u) 3387:Src/main.c **** { 3388:Src/main.c **** hold = AD9102_SRAM_HOLD_DEFAULT; 3389:Src/main.c **** } 3390:Src/main.c **** if (hold > 0x0Fu) 3391:Src/main.c **** { 3392:Src/main.c **** hold = 0x0Fu; 3393:Src/main.c **** } 3394:Src/main.c **** 3395:Src/main.c **** uint16_t pat_timebase = (uint16_t)(((uint16_t)(hold & 0x0Fu) << 8) | 3396:Src/main.c **** ((AD9102_SRAM_PAT_PERIOD_BASE_DEFAULT & 0x0Fu) << 4) | 3397:Src/main.c **** (AD9102_SRAM_START_DELAY_BASE_DEFAULT & 0x0Fu)); 3398:Src/main.c **** uint32_t pat_period = (uint32_t)samples * (uint32_t)(hold & 0x0Fu); 3399:Src/main.c **** if (pat_period == 0u) 3400:Src/main.c **** { 3401:Src/main.c **** pat_period = samples; 3402:Src/main.c **** } 3403:Src/main.c **** if (pat_period > 0xFFFFu) 3404:Src/main.c **** { 3405:Src/main.c **** pat_period = 0xFFFFu; 3406:Src/main.c **** } 3407:Src/main.c **** 3408:Src/main.c **** uint16_t stop_addr = (uint16_t)((samples - 1u) << 4); 3409:Src/main.c **** 3410:Src/main.c **** uint8_t ok = 1u; 3411:Src/main.c **** 3412:Src/main.c **** if (spiconfig != 0x0000u) 3413:Src/main.c **** { 3414:Src/main.c **** ok = 0u; ARM GAS /tmp/ccLSPxIe.s page 125 3415:Src/main.c **** } 3416:Src/main.c **** if (powercfg & ((1u << 8) | (1u << 7) | (1u << 6) | (1u << 5) | (1u << 3))) 3417:Src/main.c **** { 3418:Src/main.c **** ok = 0u; 3419:Src/main.c **** } 3420:Src/main.c **** if (clockcfg & ((1u << 11) | (1u << 7) | (1u << 6) | (1u << 5))) 3421:Src/main.c **** { 3422:Src/main.c **** ok = 0u; 3423:Src/main.c **** } 3424:Src/main.c **** if (cfg_err & 0x003Fu) 3425:Src/main.c **** { 3426:Src/main.c **** ok = 0u; 3427:Src/main.c **** } 3428:Src/main.c **** if (expect_run && ((pat_status & AD9102_PAT_STATUS_RUN) == 0u)) 3429:Src/main.c **** { 3430:Src/main.c **** ok = 0u; 3431:Src/main.c **** } 3432:Src/main.c **** 3433:Src/main.c **** if (AD9102_ReadReg(AD9102_REG_WAV_CONFIG) != AD9102_EX2_WAV_CONFIG) 3434:Src/main.c **** { 3435:Src/main.c **** ok = 0u; 3436:Src/main.c **** } 3437:Src/main.c **** if (AD9102_ReadReg(AD9102_REG_PAT_TIMEBASE) != pat_timebase) 3438:Src/main.c **** { 3439:Src/main.c **** ok = 0u; 3440:Src/main.c **** } 3441:Src/main.c **** if (AD9102_ReadReg(AD9102_REG_PAT_PERIOD) != (uint16_t)pat_period) 3442:Src/main.c **** { 3443:Src/main.c **** ok = 0u; 3444:Src/main.c **** } 3445:Src/main.c **** if (AD9102_ReadReg(AD9102_REG_PAT_TYPE) != 0x0000u) 3446:Src/main.c **** { 3447:Src/main.c **** ok = 0u; 3448:Src/main.c **** } 3449:Src/main.c **** if (AD9102_ReadReg(AD9102_REG_START_ADDR) != 0x0000u) 3450:Src/main.c **** { 3451:Src/main.c **** ok = 0u; 3452:Src/main.c **** } 3453:Src/main.c **** if (AD9102_ReadReg(AD9102_REG_STOP_ADDR) != stop_addr) 3454:Src/main.c **** { 3455:Src/main.c **** ok = 0u; 3456:Src/main.c **** } 3457:Src/main.c **** if (AD9102_ReadReg(AD9102_REG_DAC_PAT) != AD9102_EX2_DAC_PAT) 3458:Src/main.c **** { 3459:Src/main.c **** ok = 0u; 3460:Src/main.c **** } 3461:Src/main.c **** 3462:Src/main.c **** return (ok ? 0u : 1u); 3463:Src/main.c **** } 3464:Src/main.c **** 3465:Src/main.c **** void Set_LTEC(uint8_t num, uint16_t DATA) 3466:Src/main.c **** { 3467:Src/main.c **** uint32_t tmp32; 3468:Src/main.c **** 3469:Src/main.c **** if (num == 1 || num == 3) 3470:Src/main.c **** { 3471:Src/main.c **** SPI2_SetMode(LL_SPI_POLARITY_HIGH, LL_SPI_PHASE_2EDGE); ARM GAS /tmp/ccLSPxIe.s page 126 3472:Src/main.c **** HAL_GPIO_WritePin(AD9102_CS_GPIO_Port, AD9102_CS_Pin, GPIO_PIN_SET); 3473:Src/main.c **** } 3474:Src/main.c **** 3475:Src/main.c **** switch (num) 3476:Src/main.c **** { 3477:Src/main.c **** case 1: 3478:Src/main.c **** HAL_GPIO_WritePin(DAC_LD1_CS_GPIO_Port, DAC_LD1_CS_Pin, GPIO_PIN_RESET);//Start operation with L 3479:Src/main.c **** //tmp32=0; 3480:Src/main.c **** //while(tmp32<500){tmp32++;} 3481:Src/main.c **** tmp32 = 0; 3482:Src/main.c **** while((!LL_SPI_IsActiveFlag_TXE(SPI2))&&(tmp32<=500)) {tmp32++;}//When trans. last data cycle wi 3483:Src/main.c **** LL_SPI_TransmitData16(SPI2, DATA);//Transmit word to Laser1 DAC 3484:Src/main.c **** tmp32 = 0; 3485:Src/main.c **** while((!LL_SPI_IsActiveFlag_RXNE(SPI2))&&(tmp32<=500)) {tmp32++;}//When trans. last data cycle w 3486:Src/main.c **** (void) SPI2->DR; 3487:Src/main.c **** break; 3488:Src/main.c **** case 2: 3489:Src/main.c **** //HAL_GPIO_TogglePin(OUT_11_GPIO_Port, OUT_11_Pin); //for debug purposes 3490:Src/main.c **** HAL_GPIO_WritePin(DAC_LD2_CS_GPIO_Port, DAC_LD2_CS_Pin, GPIO_PIN_RESET);//Start operation with L 3491:Src/main.c **** //tmp32=0; 3492:Src/main.c **** //while(tmp32<500){tmp32++;} 3493:Src/main.c **** tmp32 = 0; 3494:Src/main.c **** while((!LL_SPI_IsActiveFlag_TXE(SPI6))&&(tmp32<=500)) {tmp32++;}//When trans. last data cycle wi 3495:Src/main.c **** LL_SPI_TransmitData16(SPI6, DATA);//Transmit word to Laser1 DAC 3496:Src/main.c **** tmp32 = 0; 3497:Src/main.c **** while((!LL_SPI_IsActiveFlag_RXNE(SPI6))&&(tmp32<=500)) {tmp32++;}//When trans. last data cycle w 3498:Src/main.c **** (void) SPI6->DR; 3499:Src/main.c **** break; 3500:Src/main.c **** case 3: 3501:Src/main.c **** HAL_GPIO_WritePin(DAC_TEC1_CS_GPIO_Port, DAC_TEC1_CS_Pin, GPIO_PIN_RESET);//Start operation with 3502:Src/main.c **** //tmp32=0; 3503:Src/main.c **** //while(tmp32<500){tmp32++;} 3504:Src/main.c **** tmp32 = 0; 3505:Src/main.c **** while((!LL_SPI_IsActiveFlag_TXE(SPI2))&&(tmp32<=500)) {tmp32++;}//When trans. last data cycle wi 3506:Src/main.c **** LL_SPI_TransmitData16(SPI2, DATA);//Transmit word to Laser1 DAC 3507:Src/main.c **** tmp32 = 0; 3508:Src/main.c **** while((!LL_SPI_IsActiveFlag_RXNE(SPI2))&&(tmp32<=500)) {tmp32++;}//When trans. last data cycle w 3509:Src/main.c **** (void) SPI2->DR; 3510:Src/main.c **** break; 3511:Src/main.c **** case 4: 3512:Src/main.c **** HAL_GPIO_WritePin(DAC_TEC2_CS_GPIO_Port, DAC_TEC2_CS_Pin, GPIO_PIN_RESET);//Start operation with 3513:Src/main.c **** //tmp32=0; 3514:Src/main.c **** //while(tmp32<500){tmp32++;} 3515:Src/main.c **** tmp32 = 0; 3516:Src/main.c **** while((!LL_SPI_IsActiveFlag_TXE(SPI6))&&(tmp32<=500)) {tmp32++;}//When trans. last data cycle wi 3517:Src/main.c **** LL_SPI_TransmitData16(SPI6, DATA);//Transmit word to Laser1 DAC 3518:Src/main.c **** tmp32 = 0; 3519:Src/main.c **** while((!LL_SPI_IsActiveFlag_RXNE(SPI6))&&(tmp32<=500)) {tmp32++;}//When trans. last data cycle w 3520:Src/main.c **** (void) SPI6->DR; 3521:Src/main.c **** break; 3522:Src/main.c **** } 3523:Src/main.c **** HAL_GPIO_WritePin(DAC_LD1_CS_GPIO_Port, DAC_LD1_CS_Pin, GPIO_PIN_SET);//End operation with LDAC1 3524:Src/main.c **** HAL_GPIO_WritePin(DAC_LD2_CS_GPIO_Port, DAC_LD2_CS_Pin, GPIO_PIN_SET);//End operation with LDAC2 3525:Src/main.c **** HAL_GPIO_WritePin(DAC_TEC1_CS_GPIO_Port, DAC_TEC1_CS_Pin, GPIO_PIN_SET);//End operation with TEC1 3526:Src/main.c **** HAL_GPIO_WritePin(DAC_TEC2_CS_GPIO_Port, DAC_TEC2_CS_Pin, GPIO_PIN_SET);//End operation with TEC2 3527:Src/main.c **** } 3528:Src/main.c **** static uint16_t MPhD_T(uint8_t num) ARM GAS /tmp/ccLSPxIe.s page 127 3529:Src/main.c **** { 3530:Src/main.c **** uint16_t P; 3531:Src/main.c **** uint32_t tmp32; 3532:Src/main.c **** HAL_GPIO_WritePin(SPI4_CNV_GPIO_Port, SPI4_CNV_Pin, GPIO_PIN_RESET);//Prepare conversion 3533:Src/main.c **** HAL_GPIO_WritePin(SPI5_CNV_GPIO_Port, SPI5_CNV_Pin, GPIO_PIN_RESET);//Prepare conversion 3534:Src/main.c **** tmp32=0; 3535:Src/main.c **** while(tmp32<500){tmp32++;} 3536:Src/main.c **** HAL_GPIO_WritePin(SPI4_CNV_GPIO_Port, SPI4_CNV_Pin, GPIO_PIN_SET);//Stop acqusition & start conver 3537:Src/main.c **** HAL_GPIO_WritePin(SPI5_CNV_GPIO_Port, SPI5_CNV_Pin, GPIO_PIN_SET);//Stop acqusition & start conver 3538:Src/main.c **** tmp32=0; 3539:Src/main.c **** while(tmp32<500){tmp32++;} 3540:Src/main.c **** if (num==1)//MPD1 3541:Src/main.c **** { 3542:Src/main.c **** HAL_GPIO_WritePin(ADC_ThrLD1_CS_GPIO_Port, ADC_ThrLD1_CS_Pin, GPIO_PIN_SET); 3543:Src/main.c **** HAL_GPIO_WritePin(ADC_MPD1_CS_GPIO_Port, ADC_MPD1_CS_Pin, GPIO_PIN_RESET); 3544:Src/main.c **** tmp32=0; 3545:Src/main.c **** while(tmp32<500){tmp32++;} 3546:Src/main.c **** //LL_SPI_TransmitData16(SPI4, 0xFFFF);//We must to clock the CLK output for collect RX data. We c 3547:Src/main.c **** LL_SPI_Enable(SPI4);//Enable SPI for MPhD1 ADC 3548:Src/main.c **** tmp32 = 0; 3549:Src/main.c **** while(((!LL_SPI_IsActiveFlag_RXNE(SPI4))&&(tmp32<=1000))) {tmp32++;}//When rec. last data cycle w 3550:Src/main.c **** LL_SPI_Disable(SPI4);//Enable SPI for MPhD1 ADC 3551:Src/main.c **** while(tmp32<500){tmp32++;} 3552:Src/main.c **** //HAL_SPI_Receive(&hspi4, &P[0], 1, 100); 3553:Src/main.c **** HAL_GPIO_WritePin(ADC_MPD1_CS_GPIO_Port, ADC_MPD1_CS_Pin, GPIO_PIN_SET); 3554:Src/main.c **** P = LL_SPI_ReceiveData16(SPI4); 3555:Src/main.c **** } 3556:Src/main.c **** else if (num==2)//MPD2 3557:Src/main.c **** { 3558:Src/main.c **** HAL_GPIO_WritePin(ADC_ThrLD2_CS_GPIO_Port, ADC_ThrLD2_CS_Pin, GPIO_PIN_SET); 3559:Src/main.c **** HAL_GPIO_WritePin(ADC_MPD2_CS_GPIO_Port, ADC_MPD2_CS_Pin, GPIO_PIN_RESET); 3560:Src/main.c **** tmp32=0; 3561:Src/main.c **** while(tmp32<500){tmp32++;} 3562:Src/main.c **** //LL_SPI_TransmitData16(SPI5, 0xFFFF);//We must to clock the CLK output for collect RX data. We c 3563:Src/main.c **** LL_SPI_Enable(SPI5);//Enable SPI for MPhD2 ADC 3564:Src/main.c **** tmp32 = 0; 3565:Src/main.c **** while(((!LL_SPI_IsActiveFlag_RXNE(SPI5))&&(tmp32<=1000))) {tmp32++;}//When rec. last data cycle w 3566:Src/main.c **** LL_SPI_Disable(SPI5);//Enable SPI for MPhD2 ADC 3567:Src/main.c **** while(tmp32<500){tmp32++;} 3568:Src/main.c **** //HAL_SPI_Receive(&hspi4, &P[0], 1, 100); 3569:Src/main.c **** HAL_GPIO_WritePin(ADC_MPD2_CS_GPIO_Port, ADC_MPD2_CS_Pin, GPIO_PIN_SET); 3570:Src/main.c **** P = LL_SPI_ReceiveData16(SPI5); 3571:Src/main.c **** } 3572:Src/main.c **** else if (num==3)//ThrLD1 3573:Src/main.c **** { 3574:Src/main.c **** HAL_GPIO_WritePin(ADC_MPD1_CS_GPIO_Port, ADC_MPD1_CS_Pin, GPIO_PIN_SET); 3575:Src/main.c **** HAL_GPIO_WritePin(ADC_ThrLD1_CS_GPIO_Port, ADC_ThrLD1_CS_Pin, GPIO_PIN_RESET); 3576:Src/main.c **** tmp32=0; 3577:Src/main.c **** while(tmp32<500){tmp32++;} 3578:Src/main.c **** //LL_SPI_TransmitData16(SPI4, 0xFFFF);//We must to clock the CLK output for collect RX data. We c 3579:Src/main.c **** LL_SPI_Enable(SPI4);//Enable SPI for ThrLD1 ADC 3580:Src/main.c **** tmp32 = 0; 3581:Src/main.c **** while(((!LL_SPI_IsActiveFlag_RXNE(SPI4))&&(tmp32<=1000))) {tmp32++;}//When rec. last data cycle w 3582:Src/main.c **** LL_SPI_Disable(SPI4);//Enable SPI for ThrLD1 ADC 3583:Src/main.c **** while(tmp32<500){tmp32++;} 3584:Src/main.c **** //HAL_SPI_Receive(&hspi4, &P[0], 1, 100); 3585:Src/main.c **** HAL_GPIO_WritePin(ADC_ThrLD1_CS_GPIO_Port, ADC_ThrLD1_CS_Pin, GPIO_PIN_SET); ARM GAS /tmp/ccLSPxIe.s page 128 3586:Src/main.c **** P = LL_SPI_ReceiveData16(SPI4); 3587:Src/main.c **** } 3588:Src/main.c **** else if (num==4)//ThrLD2 3589:Src/main.c **** { 3590:Src/main.c **** HAL_GPIO_WritePin(ADC_MPD2_CS_GPIO_Port, ADC_MPD2_CS_Pin, GPIO_PIN_SET); 3591:Src/main.c **** HAL_GPIO_WritePin(ADC_ThrLD2_CS_GPIO_Port, ADC_ThrLD2_CS_Pin, GPIO_PIN_RESET); 3592:Src/main.c **** tmp32=0; 3593:Src/main.c **** while(tmp32<500){tmp32++;} 3594:Src/main.c **** //LL_SPI_TransmitData16(SPI5, 0xFFFF);//We must to clock the CLK output for collect RX data. We c 3595:Src/main.c **** LL_SPI_Enable(SPI5);//Enable SPI for ThrLD2 ADC 3596:Src/main.c **** tmp32 = 0; 3597:Src/main.c **** while(((!LL_SPI_IsActiveFlag_RXNE(SPI5))&&(tmp32<=1000))) {tmp32++;}//When rec. last data cycle w 3598:Src/main.c **** LL_SPI_Disable(SPI5);//Enable SPI for ThrLD2 ADC 3599:Src/main.c **** while(tmp32<500){tmp32++;} 3600:Src/main.c **** //HAL_SPI_Receive(&hspi4, &P[0], 1, 100); 3601:Src/main.c **** HAL_GPIO_WritePin(ADC_ThrLD2_CS_GPIO_Port, ADC_ThrLD2_CS_Pin, GPIO_PIN_SET); 3602:Src/main.c **** P = LL_SPI_ReceiveData16(SPI5); 3603:Src/main.c **** } 3604:Src/main.c **** /*float I_LD, Ith, I0m, T0m, Inorm, Tnorm1, Tnorm2, P, T_C, A, Pnorm; 3605:Src/main.c **** 3606:Src/main.c **** Inorm = (float) (65535) / (float) (100); 3607:Src/main.c **** Tnorm1 = (float) (65535) / (float) (50); 3608:Src/main.c **** Tnorm2 = 4; 3609:Src/main.c **** Pnorm = (float)(65535) / (float)(20); 3610:Src/main.c **** I0m = 8.1568;//@4 C - lowest temperature of system 3611:Src/main.c **** T0m = 48.6282; 3612:Src/main.c **** T_C = (float) (T_LD) / Tnorm1 + Tnorm2; 3613:Src/main.c **** 3614:Src/main.c **** Ith = I0m * expf(T_C/T0m); 3615:Src/main.c **** I_LD = (float) (C_LD) / Inorm; 3616:Src/main.c **** 3617:Src/main.c **** if (I_LD > Ith) 3618:Src/main.c **** { 3619:Src/main.c **** A = (float) (2.24276128270098e-07) * T_C * T_C * T_C - (float) (4.73392579025590e-05) * T_C * T_ 3620:Src/main.c **** P = A * (I_LD - Ith) * Pnorm; 3621:Src/main.c **** } 3622:Src/main.c **** else 3623:Src/main.c **** { 3624:Src/main.c **** P = 0; 3625:Src/main.c **** } */ 3626:Src/main.c **** return P; 3627:Src/main.c **** } 3628:Src/main.c **** /*static uint16_t Temp_LD(uint16_t T_LD_before, uint16_t T_LD, uint32_t Timer_before, uint32_t Time 3629:Src/main.c **** { 3630:Src/main.c **** uint16_t Result; 3631:Src/main.c **** // uint8_t randf; 3632:Src/main.c **** 3633:Src/main.c **** randf = 0; 3634:Src/main.c **** for (uint8_t i = 0; i < 32; i++) 3635:Src/main.c **** { 3636:Src/main.c **** randf = ((Timer>>i)&0x0001)^randf; 3637:Src/main.c **** } 3638:Src/main.c **** 3639:Src/main.c **** Result = ((float)(T_LD - T_LD_before))*((float)(1-expf(((float)(Timer_before)-(float)(Timer))/((fl 3640:Src/main.c **** 3641:Src/main.c **** return (uint16_t)(Result); 3642:Src/main.c **** }*/ ARM GAS /tmp/ccLSPxIe.s page 129 3643:Src/main.c **** static uint16_t Get_ADC(uint8_t num) 3644:Src/main.c **** { 3645:Src/main.c **** uint16_t OUT; 3646:Src/main.c **** switch (num) 3647:Src/main.c **** { 3648:Src/main.c **** case 0: 3649:Src/main.c **** HAL_ADC_Start(&hadc1); // Power on 3650:Src/main.c **** break; 3651:Src/main.c **** case 1: 3652:Src/main.c **** HAL_ADC_PollForConversion(&hadc1, 100); // Waiting for conversion 3653:Src/main.c **** OUT = HAL_ADC_GetValue(&hadc1); // Get value adc 3654:Src/main.c **** break; 3655:Src/main.c **** case 2: 3656:Src/main.c **** HAL_ADC_Stop(&hadc1); // Power off 3657:Src/main.c **** break; 3658:Src/main.c **** case 3: 3659:Src/main.c **** HAL_ADC_Start(&hadc3); // Power on 3660:Src/main.c **** break; 3661:Src/main.c **** case 4: 3662:Src/main.c **** HAL_ADC_PollForConversion(&hadc3, 100); // Waiting for conversion 3663:Src/main.c **** OUT = HAL_ADC_GetValue(&hadc3); // Get value adc 3664:Src/main.c **** break; 3665:Src/main.c **** case 5: 3666:Src/main.c **** HAL_ADC_Stop(&hadc3); // Power off 3667:Src/main.c **** break; 3668:Src/main.c **** } 3669:Src/main.c **** return OUT; 3670:Src/main.c **** } 3671:Src/main.c **** 3672:Src/main.c **** uint16_t Advanced_Controller_Temp(LDx_SetupTypeDef * LDx_curr_setup, LDx_ParamTypeDef * LDx_results 3673:Src/main.c **** { 3674:Src/main.c **** // Main idea: 3675:Src/main.c **** // I is responsible to maintaining constant temperature difference between laser and room temperat 3676:Src/main.c **** // As room temperature can be approximated as constant at current-varying time -- I should be kept 3677:Src/main.c **** // As current through laser diode heats it -- we can estimate excessive power on laser diode and t 3678:Src/main.c **** // So, equation should be look like this: 3679:Src/main.c **** // x_output = x_output_original + I(laser)*(a + (t - b)c) 3680:Src/main.c **** // t -- cycle phase 3681:Src/main.c **** // a,b,c -- constants 3682:Src/main.c **** // 3683:Src/main.c **** // How can we control laser diode temperature? 3684:Src/main.c **** // -- We can set laser to fixed current at the time we need to measure. 3685:Src/main.c **** // Then we should measure wavelength. 3686:Src/main.c **** // Calibration sequence: 3687:Src/main.c **** // 1) n 3688:Src/main.c **** 3689:Src/main.c **** 3690:Src/main.c **** 3691:Src/main.c **** int e_pid; 3692:Src/main.c **** float P_coef_current;//, I_coef_current; 3693:Src/main.c **** float e_integral; 3694:Src/main.c **** int x_output; 3695:Src/main.c **** 3696:Src/main.c **** e_pid = (int) LDx_results->LD_CURR_TEMP - (int) LDx_curr_setup->LD_TEMP; 3697:Src/main.c **** 3698:Src/main.c **** e_integral = LDx_results->e_integral; 3699:Src/main.c **** ARM GAS /tmp/ccLSPxIe.s page 130 3700:Src/main.c **** if((e_pid < 3000) && (e_pid > - 3000)){ 3701:Src/main.c **** e_integral += LDx_curr_setup->I_coef_temp * (float)(e_pid) * (float)(TO7 - TO7_PID) / (float) 100 3702:Src/main.c **** } 3703:Src/main.c **** P_coef_current = LDx_curr_setup->P_coef_temp; 3704:Src/main.c **** 3705:Src/main.c **** if (e_integral > 32000){ 3706:Src/main.c **** e_integral = 32000; 3707:Src/main.c **** } 3708:Src/main.c **** else if (e_integral < - 32000){ 3709:Src/main.c **** e_integral = -32000; 3710:Src/main.c **** } 3711:Src/main.c **** LDx_results->e_integral = e_integral; 3712:Src/main.c **** 3713:Src/main.c **** x_output = 32768 + P_coef_current * e_pid + (int)e_integral;//32768 - P_coef_current * e_pid - (in 3714:Src/main.c **** 3715:Src/main.c **** if(x_output < 1000){ 3716:Src/main.c **** x_output = 8800; 3717:Src/main.c **** } 3718:Src/main.c **** else if(x_output > 56800){ 3719:Src/main.c **** x_output = 56800; 3720:Src/main.c **** } 3721:Src/main.c **** 3722:Src/main.c **** if (num==2) 3723:Src/main.c **** TO7_PID = TO7;//Save current time only on 2nd laser 3724:Src/main.c **** 3725:Src/main.c **** return (uint16_t)x_output; 3726:Src/main.c **** } 3727:Src/main.c **** 3728:Src/main.c **** 3729:Src/main.c **** uint16_t PID_Controller_Temp(LDx_SetupTypeDef * LDx_curr_setup, LDx_ParamTypeDef * LDx_results, uin 3730:Src/main.c **** { 754 .loc 1 3730 1 is_stmt 1 view -0 755 .cfi_startproc 756 @ args = 0, pretend = 0, frame = 0 757 @ frame_needed = 0, uses_anonymous_args = 0 758 @ link register save eliminated. 759 .loc 1 3730 1 is_stmt 0 view .LVU256 760 0000 30B4 push {r4, r5} 761 .LCFI6: 762 .cfi_def_cfa_offset 8 763 .cfi_offset 4, -8 764 .cfi_offset 5, -4 3731:Src/main.c **** int e_pid; 765 .loc 1 3731 2 is_stmt 1 view .LVU257 3732:Src/main.c **** float P_coef_current;//, I_coef_current; 766 .loc 1 3732 2 view .LVU258 3733:Src/main.c **** float e_integral; 767 .loc 1 3733 2 view .LVU259 3734:Src/main.c **** int x_output; 768 .loc 1 3734 2 view .LVU260 3735:Src/main.c **** 3736:Src/main.c **** e_pid = (int) LDx_results->LD_CURR_TEMP - (int) LDx_curr_setup->LD_TEMP; 769 .loc 1 3736 2 view .LVU261 770 .loc 1 3736 28 is_stmt 0 view .LVU262 771 0002 0B88 ldrh r3, [r1] 772 .loc 1 3736 65 view .LVU263 773 0004 0488 ldrh r4, [r0] ARM GAS /tmp/ccLSPxIe.s page 131 774 .loc 1 3736 8 view .LVU264 775 0006 1B1B subs r3, r3, r4 776 .LVL45: 3737:Src/main.c **** 3738:Src/main.c **** e_integral = LDx_results->e_integral; 777 .loc 1 3738 2 is_stmt 1 view .LVU265 778 .loc 1 3738 13 is_stmt 0 view .LVU266 779 0008 D1ED017A vldr.32 s15, [r1, #4] 780 .LVL46: 3739:Src/main.c **** 3740:Src/main.c **** if((e_pid < 3000) && (e_pid > - 3000)){ 781 .loc 1 3740 2 is_stmt 1 view .LVU267 782 .loc 1 3740 20 is_stmt 0 view .LVU268 783 000c 03F6B73C addw ip, r3, #2999 784 .loc 1 3740 4 view .LVU269 785 0010 41F26E74 movw r4, #5998 786 0014 A445 cmp ip, r4 787 0016 18D8 bhi .L32 3741:Src/main.c **** e_integral += LDx_curr_setup->I_coef_temp * (float)(e_pid) * (float)(TO7 - TO7_PID) / (float) 100 788 .loc 1 3741 3 is_stmt 1 view .LVU270 789 .loc 1 3741 31 is_stmt 0 view .LVU271 790 0018 90ED027A vldr.32 s14, [r0, #8] 791 .loc 1 3741 47 view .LVU272 792 001c 06EE903A vmov s13, r3 @ int 793 0020 F8EEE66A vcvt.f32.s32 s13, s13 794 .loc 1 3741 45 view .LVU273 795 0024 27EE267A vmul.f32 s14, s14, s13 796 .loc 1 3741 76 view .LVU274 797 0028 284C ldr r4, .L42 798 002a 2468 ldr r4, [r4] 799 002c 284D ldr r5, .L42+4 800 002e 2D68 ldr r5, [r5] 801 0030 641B subs r4, r4, r5 802 .loc 1 3741 64 view .LVU275 803 0032 06EE904A vmov s13, r4 @ int 804 0036 F8EE666A vcvt.f32.u32 s13, s13 805 .loc 1 3741 62 view .LVU276 806 003a 27EE267A vmul.f32 s14, s14, s13 807 .loc 1 3741 87 view .LVU277 808 003e 9FED256A vldr.32 s12, .L42+8 809 0042 C7EE066A vdiv.f32 s13, s14, s12 810 .loc 1 3741 14 view .LVU278 811 0046 77EEA67A vadd.f32 s15, s15, s13 812 .LVL47: 813 .L32: 3742:Src/main.c **** } 3743:Src/main.c **** P_coef_current = LDx_curr_setup->P_coef_temp; 814 .loc 1 3743 2 is_stmt 1 view .LVU279 815 .loc 1 3743 17 is_stmt 0 view .LVU280 816 004a D0ED016A vldr.32 s13, [r0, #4] 817 .LVL48: 3744:Src/main.c **** 3745:Src/main.c **** if (e_integral > 32000){ 818 .loc 1 3745 2 is_stmt 1 view .LVU281 819 .loc 1 3745 5 is_stmt 0 view .LVU282 820 004e 9FED227A vldr.32 s14, .L42+12 821 0052 F4EEC77A vcmpe.f32 s15, s14 ARM GAS /tmp/ccLSPxIe.s page 132 822 0056 F1EE10FA vmrs APSR_nzcv, FPSCR 823 005a 09DC bgt .L36 3746:Src/main.c **** e_integral = 32000; 3747:Src/main.c **** } 3748:Src/main.c **** else if (e_integral < - 32000){ 824 .loc 1 3748 7 is_stmt 1 view .LVU283 825 .loc 1 3748 10 is_stmt 0 view .LVU284 826 005c 9FED1F7A vldr.32 s14, .L42+16 827 0060 F4EEC77A vcmpe.f32 s15, s14 828 0064 F1EE10FA vmrs APSR_nzcv, FPSCR 829 0068 04D5 bpl .L33 3749:Src/main.c **** e_integral = -32000; 830 .loc 1 3749 15 view .LVU285 831 006a DFED1C7A vldr.32 s15, .L42+16 832 .LVL49: 833 .loc 1 3749 15 view .LVU286 834 006e 01E0 b .L33 835 .LVL50: 836 .L36: 3746:Src/main.c **** e_integral = 32000; 837 .loc 1 3746 15 view .LVU287 838 0070 DFED197A vldr.32 s15, .L42+12 839 .LVL51: 840 .L33: 3750:Src/main.c **** } 3751:Src/main.c **** LDx_results->e_integral = e_integral; 841 .loc 1 3751 2 is_stmt 1 view .LVU288 842 .loc 1 3751 26 is_stmt 0 view .LVU289 843 0074 C1ED017A vstr.32 s15, [r1, #4] 3752:Src/main.c **** 3753:Src/main.c **** x_output = 32768 + P_coef_current * e_pid + (int)e_integral;//32768 - P_coef_current * e_pid - (in 844 .loc 1 3753 2 is_stmt 1 view .LVU290 845 .loc 1 3753 36 is_stmt 0 view .LVU291 846 0078 07EE103A vmov s14, r3 @ int 847 007c B8EEC77A vcvt.f32.s32 s14, s14 848 0080 27EE267A vmul.f32 s14, s14, s13 849 .loc 1 3753 19 view .LVU292 850 0084 DFED166A vldr.32 s13, .L42+20 851 .LVL52: 852 .loc 1 3753 19 view .LVU293 853 0088 37EE267A vadd.f32 s14, s14, s13 854 .loc 1 3753 46 view .LVU294 855 008c FDEEE77A vcvt.s32.f32 s15, s15 856 .LVL53: 857 .loc 1 3753 44 view .LVU295 858 0090 F8EEE77A vcvt.f32.s32 s15, s15 859 0094 77EE877A vadd.f32 s15, s15, s14 860 .loc 1 3753 11 view .LVU296 861 0098 FDEEE77A vcvt.s32.f32 s15, s15 862 009c 17EE900A vmov r0, s15 @ int 863 .LVL54: 3754:Src/main.c **** 3755:Src/main.c **** if(x_output < 1000){ 864 .loc 1 3755 2 is_stmt 1 view .LVU297 865 .loc 1 3755 4 is_stmt 0 view .LVU298 866 00a0 B0F57A7F cmp r0, #1000 867 00a4 06DB blt .L38 ARM GAS /tmp/ccLSPxIe.s page 133 3756:Src/main.c **** x_output = 8800; 3757:Src/main.c **** } 3758:Src/main.c **** else if(x_output > 56800){ 868 .loc 1 3758 7 is_stmt 1 view .LVU299 869 .loc 1 3758 9 is_stmt 0 view .LVU300 870 00a6 4DF6E053 movw r3, #56800 871 .LVL55: 872 .loc 1 3758 9 view .LVU301 873 00aa 9842 cmp r0, r3 874 00ac 04DD ble .L34 3759:Src/main.c **** x_output = 56800; 875 .loc 1 3759 12 view .LVU302 876 00ae 4DF6E050 movw r0, #56800 877 .LVL56: 878 .loc 1 3759 12 view .LVU303 879 00b2 01E0 b .L34 880 .LVL57: 881 .L38: 3756:Src/main.c **** x_output = 8800; 882 .loc 1 3756 12 view .LVU304 883 00b4 42F26020 movw r0, #8800 884 .LVL58: 885 .L34: 3760:Src/main.c **** } 3761:Src/main.c **** 3762:Src/main.c **** if (num==2) 886 .loc 1 3762 2 is_stmt 1 view .LVU305 887 .loc 1 3762 5 is_stmt 0 view .LVU306 888 00b8 022A cmp r2, #2 889 00ba 02D0 beq .L41 890 .LVL59: 891 .L35: 3763:Src/main.c **** TO7_PID = TO7;//Save current time only on 2nd laser 3764:Src/main.c **** 3765:Src/main.c **** return (uint16_t)x_output; 892 .loc 1 3765 2 is_stmt 1 view .LVU307 3766:Src/main.c **** } 893 .loc 1 3766 1 is_stmt 0 view .LVU308 894 00bc 80B2 uxth r0, r0 895 .LVL60: 896 .loc 1 3766 1 view .LVU309 897 00be 30BC pop {r4, r5} 898 .LCFI7: 899 .cfi_remember_state 900 .cfi_restore 5 901 .cfi_restore 4 902 .cfi_def_cfa_offset 0 903 00c0 7047 bx lr 904 .LVL61: 905 .L41: 906 .LCFI8: 907 .cfi_restore_state 3763:Src/main.c **** TO7_PID = TO7;//Save current time only on 2nd laser 908 .loc 1 3763 3 is_stmt 1 view .LVU310 3763:Src/main.c **** TO7_PID = TO7;//Save current time only on 2nd laser 909 .loc 1 3763 11 is_stmt 0 view .LVU311 910 00c2 024B ldr r3, .L42 ARM GAS /tmp/ccLSPxIe.s page 134 911 00c4 1A68 ldr r2, [r3] 912 .LVL62: 3763:Src/main.c **** TO7_PID = TO7;//Save current time only on 2nd laser 913 .loc 1 3763 11 view .LVU312 914 00c6 024B ldr r3, .L42+4 915 00c8 1A60 str r2, [r3] 916 00ca F7E7 b .L35 917 .L43: 918 .align 2 919 .L42: 920 00cc 00000000 .word TO7 921 00d0 00000000 .word TO7_PID 922 00d4 0000C842 .word 1120403456 923 00d8 0000FA46 .word 1190789120 924 00dc 0000FAC6 .word -956694528 925 00e0 00000047 .word 1191182336 926 .cfi_endproc 927 .LFE1239: 929 .section .text.AD9102_WriteReg,"ax",%progbits 930 .align 1 931 .syntax unified 932 .thumb 933 .thumb_func 935 AD9102_WriteReg: 936 .LVL63: 937 .LFB1219: 2874:Src/main.c **** uint32_t tmp32 = 0; 938 .loc 1 2874 1 is_stmt 1 view -0 939 .cfi_startproc 940 @ args = 0, pretend = 0, frame = 0 941 @ frame_needed = 0, uses_anonymous_args = 0 2874:Src/main.c **** uint32_t tmp32 = 0; 942 .loc 1 2874 1 is_stmt 0 view .LVU314 943 0000 38B5 push {r3, r4, r5, lr} 944 .LCFI9: 945 .cfi_def_cfa_offset 16 946 .cfi_offset 3, -16 947 .cfi_offset 4, -12 948 .cfi_offset 5, -8 949 .cfi_offset 14, -4 950 0002 0C46 mov r4, r1 2875:Src/main.c **** uint16_t cmd = (uint16_t)(addr & 0x7FFFu); // R/W = 0 (write), 15-bit address 951 .loc 1 2875 2 is_stmt 1 view .LVU315 952 .LVL64: 2876:Src/main.c **** 953 .loc 1 2876 2 view .LVU316 2876:Src/main.c **** 954 .loc 1 2876 11 is_stmt 0 view .LVU317 955 0004 C0F30E05 ubfx r5, r0, #0, #15 956 .LVL65: 2878:Src/main.c **** 957 .loc 1 2878 2 is_stmt 1 view .LVU318 958 0008 0021 movs r1, #0 959 .LVL66: 2878:Src/main.c **** 960 .loc 1 2878 2 is_stmt 0 view .LVU319 961 000a 0846 mov r0, r1 ARM GAS /tmp/ccLSPxIe.s page 135 962 .LVL67: 2878:Src/main.c **** 963 .loc 1 2878 2 view .LVU320 964 000c FFF7FEFF bl SPI2_SetMode 965 .LVL68: 2880:Src/main.c **** HAL_GPIO_WritePin(DAC_TEC1_CS_GPIO_Port, DAC_TEC1_CS_Pin, GPIO_PIN_SET); 966 .loc 1 2880 2 is_stmt 1 view .LVU321 967 0010 0122 movs r2, #1 968 0012 4FF48041 mov r1, #16384 969 0016 2C48 ldr r0, .L59 970 0018 FFF7FEFF bl HAL_GPIO_WritePin 971 .LVL69: 2881:Src/main.c **** 972 .loc 1 2881 2 view .LVU322 973 001c 0122 movs r2, #1 974 001e 4FF48051 mov r1, #4096 975 0022 2A48 ldr r0, .L59+4 976 0024 FFF7FEFF bl HAL_GPIO_WritePin 977 .LVL70: 2883:Src/main.c **** { 978 .loc 1 2883 2 view .LVU323 979 .LBB375: 980 .LBI375: 381:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 981 .loc 4 381 26 view .LVU324 982 .LBB376: 383:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 983 .loc 4 383 3 view .LVU325 383:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 984 .loc 4 383 12 is_stmt 0 view .LVU326 985 0028 294B ldr r3, .L59+8 986 002a 1B68 ldr r3, [r3] 383:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 987 .loc 4 383 69 view .LVU327 988 002c 13F0400F tst r3, #64 989 0030 04D1 bne .L45 990 .LVL71: 383:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 991 .loc 4 383 69 view .LVU328 992 .LBE376: 993 .LBE375: 2885:Src/main.c **** } 994 .loc 1 2885 3 is_stmt 1 view .LVU329 995 .LBB377: 996 .LBI377: 358:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 997 .loc 4 358 22 view .LVU330 998 .LBB378: 360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 999 .loc 4 360 3 view .LVU331 1000 0032 274A ldr r2, .L59+8 1001 0034 1368 ldr r3, [r2] 1002 0036 43F04003 orr r3, r3, #64 1003 003a 1360 str r3, [r2] 1004 .LVL72: 1005 .L45: 360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } ARM GAS /tmp/ccLSPxIe.s page 136 1006 .loc 4 360 3 is_stmt 0 view .LVU332 1007 .LBE378: 1008 .LBE377: 2888:Src/main.c **** 1009 .loc 1 2888 2 is_stmt 1 view .LVU333 1010 003c 0022 movs r2, #0 1011 003e 4FF48051 mov r1, #4096 1012 0042 2148 ldr r0, .L59 1013 0044 FFF7FEFF bl HAL_GPIO_WritePin 1014 .LVL73: 2890:Src/main.c **** LL_SPI_TransmitData16(SPI2, cmd); 1015 .loc 1 2890 2 view .LVU334 2875:Src/main.c **** uint16_t cmd = (uint16_t)(addr & 0x7FFFu); // R/W = 0 (write), 15-bit address 1016 .loc 1 2875 11 is_stmt 0 view .LVU335 1017 0048 0023 movs r3, #0 1018 .LVL74: 1019 .L47: 2890:Src/main.c **** LL_SPI_TransmitData16(SPI2, cmd); 1020 .loc 1 2890 63 is_stmt 1 discriminator 2 view .LVU336 2890:Src/main.c **** LL_SPI_TransmitData16(SPI2, cmd); 1021 .loc 1 2890 41 discriminator 2 view .LVU337 1022 .LBB379: 1023 .LBI379: 487:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 488:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 489:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 490:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Get clock polarity 491:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR1 CPOL LL_SPI_GetClockPolarity 492:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 493:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval Returned value can be one of the following values: 494:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_POLARITY_LOW 495:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_POLARITY_HIGH 496:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 497:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_GetClockPolarity(SPI_TypeDef *SPIx) 498:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 499:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPOL)); 500:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 501:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 502:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 503:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Set baud rate prescaler 504:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @note These bits should not be changed when communication is ongoing. SPI BaudRate = fPCLK/Pr 505:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR1 BR LL_SPI_SetBaudRatePrescaler 506:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 507:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param BaudRate This parameter can be one of the following values: 508:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2 509:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4 510:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8 511:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16 512:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32 513:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64 514:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128 515:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256 516:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None 517:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 518:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_SetBaudRatePrescaler(SPI_TypeDef *SPIx, uint32_t BaudRate) 519:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 520:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** MODIFY_REG(SPIx->CR1, SPI_CR1_BR, BaudRate); ARM GAS /tmp/ccLSPxIe.s page 137 521:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 522:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 523:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 524:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Get baud rate prescaler 525:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR1 BR LL_SPI_GetBaudRatePrescaler 526:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 527:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval Returned value can be one of the following values: 528:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2 529:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4 530:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8 531:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16 532:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32 533:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64 534:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128 535:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256 536:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 537:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_GetBaudRatePrescaler(SPI_TypeDef *SPIx) 538:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 539:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_BR)); 540:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 541:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 542:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 543:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Set transfer bit order 544:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @note This bit should not be changed when communication is ongoing. This bit is not used in S 545:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR1 LSBFIRST LL_SPI_SetTransferBitOrder 546:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 547:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param BitOrder This parameter can be one of the following values: 548:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_LSB_FIRST 549:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_MSB_FIRST 550:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None 551:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 552:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_SetTransferBitOrder(SPI_TypeDef *SPIx, uint32_t BitOrder) 553:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 554:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** MODIFY_REG(SPIx->CR1, SPI_CR1_LSBFIRST, BitOrder); 555:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 556:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 557:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 558:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Get transfer bit order 559:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR1 LSBFIRST LL_SPI_GetTransferBitOrder 560:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 561:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval Returned value can be one of the following values: 562:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_LSB_FIRST 563:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_MSB_FIRST 564:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 565:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_GetTransferBitOrder(SPI_TypeDef *SPIx) 566:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 567:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_LSBFIRST)); 568:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 569:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 570:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 571:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Set transfer direction mode 572:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @note For Half-Duplex mode, Rx Direction is set by default. 573:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * In master mode, the MOSI pin is used and in slave mode, the MISO pin is used for Half-D 574:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR1 RXONLY LL_SPI_SetTransferDirection\n 575:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * CR1 BIDIMODE LL_SPI_SetTransferDirection\n 576:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * CR1 BIDIOE LL_SPI_SetTransferDirection 577:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance ARM GAS /tmp/ccLSPxIe.s page 138 578:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param TransferDirection This parameter can be one of the following values: 579:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_FULL_DUPLEX 580:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_SIMPLEX_RX 581:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_HALF_DUPLEX_RX 582:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_HALF_DUPLEX_TX 583:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None 584:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 585:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_SetTransferDirection(SPI_TypeDef *SPIx, uint32_t TransferDirection) 586:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 587:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** MODIFY_REG(SPIx->CR1, SPI_CR1_RXONLY | SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE, TransferDirection); 588:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 589:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 590:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 591:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Get transfer direction mode 592:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR1 RXONLY LL_SPI_GetTransferDirection\n 593:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * CR1 BIDIMODE LL_SPI_GetTransferDirection\n 594:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * CR1 BIDIOE LL_SPI_GetTransferDirection 595:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 596:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval Returned value can be one of the following values: 597:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_FULL_DUPLEX 598:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_SIMPLEX_RX 599:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_HALF_DUPLEX_RX 600:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_HALF_DUPLEX_TX 601:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 602:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_GetTransferDirection(SPI_TypeDef *SPIx) 603:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 604:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_RXONLY | SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE)); 605:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 606:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 607:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 608:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Set frame data width 609:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR2 DS LL_SPI_SetDataWidth 610:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 611:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param DataWidth This parameter can be one of the following values: 612:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_DATAWIDTH_4BIT 613:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_DATAWIDTH_5BIT 614:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_DATAWIDTH_6BIT 615:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_DATAWIDTH_7BIT 616:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_DATAWIDTH_8BIT 617:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_DATAWIDTH_9BIT 618:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_DATAWIDTH_10BIT 619:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_DATAWIDTH_11BIT 620:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_DATAWIDTH_12BIT 621:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_DATAWIDTH_13BIT 622:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_DATAWIDTH_14BIT 623:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_DATAWIDTH_15BIT 624:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_DATAWIDTH_16BIT 625:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None 626:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 627:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_SetDataWidth(SPI_TypeDef *SPIx, uint32_t DataWidth) 628:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 629:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** MODIFY_REG(SPIx->CR2, SPI_CR2_DS, DataWidth); 630:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 631:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 632:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 633:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Get frame data width 634:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR2 DS LL_SPI_GetDataWidth ARM GAS /tmp/ccLSPxIe.s page 139 635:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 636:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval Returned value can be one of the following values: 637:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_DATAWIDTH_4BIT 638:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_DATAWIDTH_5BIT 639:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_DATAWIDTH_6BIT 640:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_DATAWIDTH_7BIT 641:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_DATAWIDTH_8BIT 642:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_DATAWIDTH_9BIT 643:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_DATAWIDTH_10BIT 644:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_DATAWIDTH_11BIT 645:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_DATAWIDTH_12BIT 646:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_DATAWIDTH_13BIT 647:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_DATAWIDTH_14BIT 648:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_DATAWIDTH_15BIT 649:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_DATAWIDTH_16BIT 650:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 651:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_GetDataWidth(SPI_TypeDef *SPIx) 652:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 653:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_DS)); 654:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 655:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 656:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 657:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Set threshold of RXFIFO that triggers an RXNE event 658:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR2 FRXTH LL_SPI_SetRxFIFOThreshold 659:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 660:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param Threshold This parameter can be one of the following values: 661:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_RX_FIFO_TH_HALF 662:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_RX_FIFO_TH_QUARTER 663:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None 664:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 665:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_SetRxFIFOThreshold(SPI_TypeDef *SPIx, uint32_t Threshold) 666:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 667:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** MODIFY_REG(SPIx->CR2, SPI_CR2_FRXTH, Threshold); 668:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 669:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 670:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 671:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Get threshold of RXFIFO that triggers an RXNE event 672:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR2 FRXTH LL_SPI_GetRxFIFOThreshold 673:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 674:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval Returned value can be one of the following values: 675:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_RX_FIFO_TH_HALF 676:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_RX_FIFO_TH_QUARTER 677:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 678:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_GetRxFIFOThreshold(SPI_TypeDef *SPIx) 679:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 680:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_FRXTH)); 681:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 682:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 683:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 684:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @} 685:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 686:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 687:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_EF_CRC_Management CRC Management 688:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @{ 689:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 690:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 691:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** ARM GAS /tmp/ccLSPxIe.s page 140 692:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Enable CRC 693:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation. 694:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR1 CRCEN LL_SPI_EnableCRC 695:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 696:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None 697:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 698:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_EnableCRC(SPI_TypeDef *SPIx) 699:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 700:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** SET_BIT(SPIx->CR1, SPI_CR1_CRCEN); 701:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 702:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 703:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 704:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Disable CRC 705:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation. 706:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR1 CRCEN LL_SPI_DisableCRC 707:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 708:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None 709:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 710:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_DisableCRC(SPI_TypeDef *SPIx) 711:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 712:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** CLEAR_BIT(SPIx->CR1, SPI_CR1_CRCEN); 713:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 714:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 715:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 716:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Check if CRC is enabled 717:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation. 718:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR1 CRCEN LL_SPI_IsEnabledCRC 719:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 720:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval State of bit (1 or 0). 721:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 722:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_IsEnabledCRC(SPI_TypeDef *SPIx) 723:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 724:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** return ((READ_BIT(SPIx->CR1, SPI_CR1_CRCEN) == (SPI_CR1_CRCEN)) ? 1UL : 0UL); 725:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 726:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 727:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 728:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Set CRC Length 729:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation. 730:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR1 CRCL LL_SPI_SetCRCWidth 731:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 732:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param CRCLength This parameter can be one of the following values: 733:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_CRC_8BIT 734:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_CRC_16BIT 735:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None 736:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 737:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_SetCRCWidth(SPI_TypeDef *SPIx, uint32_t CRCLength) 738:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 739:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** MODIFY_REG(SPIx->CR1, SPI_CR1_CRCL, CRCLength); 740:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 741:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 742:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 743:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Get CRC Length 744:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR1 CRCL LL_SPI_GetCRCWidth 745:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 746:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval Returned value can be one of the following values: 747:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_CRC_8BIT 748:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_CRC_16BIT ARM GAS /tmp/ccLSPxIe.s page 141 749:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 750:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_GetCRCWidth(SPI_TypeDef *SPIx) 751:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 752:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CRCL)); 753:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 754:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 755:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 756:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Set CRCNext to transfer CRC on the line 757:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @note This bit has to be written as soon as the last data is written in the SPIx_DR register. 758:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR1 CRCNEXT LL_SPI_SetCRCNext 759:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 760:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None 761:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 762:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_SetCRCNext(SPI_TypeDef *SPIx) 763:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 764:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** SET_BIT(SPIx->CR1, SPI_CR1_CRCNEXT); 765:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 766:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 767:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 768:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Set polynomial for CRC calculation 769:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CRCPR CRCPOLY LL_SPI_SetCRCPolynomial 770:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 771:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param CRCPoly This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFF 772:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None 773:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 774:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_SetCRCPolynomial(SPI_TypeDef *SPIx, uint32_t CRCPoly) 775:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 776:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** WRITE_REG(SPIx->CRCPR, (uint16_t)CRCPoly); 777:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 778:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 779:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 780:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Get polynomial for CRC calculation 781:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CRCPR CRCPOLY LL_SPI_GetCRCPolynomial 782:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 783:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF 784:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 785:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_GetCRCPolynomial(SPI_TypeDef *SPIx) 786:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 787:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** return (uint32_t)(READ_REG(SPIx->CRCPR)); 788:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 789:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 790:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 791:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Get Rx CRC 792:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll RXCRCR RXCRC LL_SPI_GetRxCRC 793:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 794:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF 795:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 796:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_GetRxCRC(SPI_TypeDef *SPIx) 797:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 798:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** return (uint32_t)(READ_REG(SPIx->RXCRCR)); 799:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 800:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 801:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 802:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Get Tx CRC 803:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll TXCRCR TXCRC LL_SPI_GetTxCRC 804:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 805:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF ARM GAS /tmp/ccLSPxIe.s page 142 806:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 807:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_GetTxCRC(SPI_TypeDef *SPIx) 808:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 809:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** return (uint32_t)(READ_REG(SPIx->TXCRCR)); 810:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 811:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 812:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 813:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @} 814:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 815:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 816:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_EF_NSS_Management Slave Select Pin Management 817:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @{ 818:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 819:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 820:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 821:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Set NSS mode 822:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @note LL_SPI_NSS_SOFT Mode is not used in SPI TI mode. 823:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR1 SSM LL_SPI_SetNSSMode\n 824:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR2 SSOE LL_SPI_SetNSSMode 825:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 826:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param NSS This parameter can be one of the following values: 827:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_NSS_SOFT 828:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_NSS_HARD_INPUT 829:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_NSS_HARD_OUTPUT 830:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None 831:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 832:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_SetNSSMode(SPI_TypeDef *SPIx, uint32_t NSS) 833:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 834:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** MODIFY_REG(SPIx->CR1, SPI_CR1_SSM, NSS); 835:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** MODIFY_REG(SPIx->CR2, SPI_CR2_SSOE, ((uint32_t)(NSS >> 16U))); 836:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 837:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 838:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 839:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Get NSS mode 840:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR1 SSM LL_SPI_GetNSSMode\n 841:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR2 SSOE LL_SPI_GetNSSMode 842:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 843:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval Returned value can be one of the following values: 844:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_NSS_SOFT 845:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_NSS_HARD_INPUT 846:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_NSS_HARD_OUTPUT 847:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 848:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_GetNSSMode(SPI_TypeDef *SPIx) 849:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 850:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** uint32_t Ssm = (READ_BIT(SPIx->CR1, SPI_CR1_SSM)); 851:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** uint32_t Ssoe = (READ_BIT(SPIx->CR2, SPI_CR2_SSOE) << 16U); 852:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** return (Ssm | Ssoe); 853:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 854:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 855:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 856:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Enable NSS pulse management 857:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @note This bit should not be changed when communication is ongoing. This bit is not used in S 858:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR2 NSSP LL_SPI_EnableNSSPulseMgt 859:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 860:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None 861:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 862:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_EnableNSSPulseMgt(SPI_TypeDef *SPIx) ARM GAS /tmp/ccLSPxIe.s page 143 863:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 864:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** SET_BIT(SPIx->CR2, SPI_CR2_NSSP); 865:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 866:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 867:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 868:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Disable NSS pulse management 869:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @note This bit should not be changed when communication is ongoing. This bit is not used in S 870:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR2 NSSP LL_SPI_DisableNSSPulseMgt 871:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 872:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None 873:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 874:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_DisableNSSPulseMgt(SPI_TypeDef *SPIx) 875:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 876:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** CLEAR_BIT(SPIx->CR2, SPI_CR2_NSSP); 877:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 878:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 879:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 880:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Check if NSS pulse is enabled 881:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @note This bit should not be changed when communication is ongoing. This bit is not used in S 882:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR2 NSSP LL_SPI_IsEnabledNSSPulse 883:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 884:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval State of bit (1 or 0). 885:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 886:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_IsEnabledNSSPulse(SPI_TypeDef *SPIx) 887:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 888:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** return ((READ_BIT(SPIx->CR2, SPI_CR2_NSSP) == (SPI_CR2_NSSP)) ? 1UL : 0UL); 889:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 890:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 891:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 892:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @} 893:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 894:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 895:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_EF_FLAG_Management FLAG Management 896:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @{ 897:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 898:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 899:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 900:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Check if Rx buffer is not empty 901:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll SR RXNE LL_SPI_IsActiveFlag_RXNE 902:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 903:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval State of bit (1 or 0). 904:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 905:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXNE(SPI_TypeDef *SPIx) 906:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** return ((READ_BIT(SPIx->SR, SPI_SR_RXNE) == (SPI_SR_RXNE)) ? 1UL : 0UL); 908:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 909:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 910:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 911:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Check if Tx buffer is empty 912:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll SR TXE LL_SPI_IsActiveFlag_TXE 913:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 914:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval State of bit (1 or 0). 915:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 916:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXE(SPI_TypeDef *SPIx) 1024 .loc 4 916 26 view .LVU338 1025 .LBB380: 917:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { ARM GAS /tmp/ccLSPxIe.s page 144 918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** return ((READ_BIT(SPIx->SR, SPI_SR_TXE) == (SPI_SR_TXE)) ? 1UL : 0UL); 1026 .loc 4 918 3 view .LVU339 1027 .loc 4 918 12 is_stmt 0 view .LVU340 1028 004a 214A ldr r2, .L59+8 1029 004c 9268 ldr r2, [r2, #8] 1030 .loc 4 918 66 view .LVU341 1031 004e 12F0020F tst r2, #2 1032 0052 05D1 bne .L46 1033 .LVL75: 1034 .loc 4 918 66 view .LVU342 1035 .LBE380: 1036 .LBE379: 2890:Src/main.c **** LL_SPI_TransmitData16(SPI2, cmd); 1037 .loc 1 2890 50 discriminator 1 view .LVU343 1038 0054 5A1C adds r2, r3, #1 1039 .LVL76: 2890:Src/main.c **** LL_SPI_TransmitData16(SPI2, cmd); 1040 .loc 1 2890 41 discriminator 1 view .LVU344 1041 0056 B3F57A7F cmp r3, #1000 1042 005a 01D2 bcs .L46 2890:Src/main.c **** LL_SPI_TransmitData16(SPI2, cmd); 1043 .loc 1 2890 50 discriminator 1 view .LVU345 1044 005c 1346 mov r3, r2 1045 005e F4E7 b .L47 1046 .LVL77: 1047 .L46: 2891:Src/main.c **** tmp32 = 0; 1048 .loc 1 2891 2 is_stmt 1 view .LVU346 1049 .LBB381: 1050 .LBI381: 919:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 920:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 921:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 922:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Get CRC error flag 923:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll SR CRCERR LL_SPI_IsActiveFlag_CRCERR 924:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 925:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval State of bit (1 or 0). 926:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 927:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_CRCERR(SPI_TypeDef *SPIx) 928:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 929:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** return ((READ_BIT(SPIx->SR, SPI_SR_CRCERR) == (SPI_SR_CRCERR)) ? 1UL : 0UL); 930:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 931:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 932:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 933:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Get mode fault error flag 934:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll SR MODF LL_SPI_IsActiveFlag_MODF 935:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 936:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval State of bit (1 or 0). 937:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 938:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_MODF(SPI_TypeDef *SPIx) 939:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 940:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** return ((READ_BIT(SPIx->SR, SPI_SR_MODF) == (SPI_SR_MODF)) ? 1UL : 0UL); 941:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 942:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 943:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 944:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Get overrun error flag 945:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll SR OVR LL_SPI_IsActiveFlag_OVR ARM GAS /tmp/ccLSPxIe.s page 145 946:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 947:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval State of bit (1 or 0). 948:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 949:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_OVR(SPI_TypeDef *SPIx) 950:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 951:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** return ((READ_BIT(SPIx->SR, SPI_SR_OVR) == (SPI_SR_OVR)) ? 1UL : 0UL); 952:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 953:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 954:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 955:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Get busy flag 956:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @note The BSY flag is cleared under any one of the following conditions: 957:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * -When the SPI is correctly disabled 958:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * -When a fault is detected in Master mode (MODF bit set to 1) 959:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * -In Master mode, when it finishes a data transmission and no new data is ready to be 960:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * sent 961:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * -In Slave mode, when the BSY flag is set to '0' for at least one SPI clock cycle between 962:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * each data transfer. 963:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll SR BSY LL_SPI_IsActiveFlag_BSY 964:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 965:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval State of bit (1 or 0). 966:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 967:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_BSY(SPI_TypeDef *SPIx) 968:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 969:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** return ((READ_BIT(SPIx->SR, SPI_SR_BSY) == (SPI_SR_BSY)) ? 1UL : 0UL); 970:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 971:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 972:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 973:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Get frame format error flag 974:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll SR FRE LL_SPI_IsActiveFlag_FRE 975:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 976:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval State of bit (1 or 0). 977:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 978:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_FRE(SPI_TypeDef *SPIx) 979:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 980:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** return ((READ_BIT(SPIx->SR, SPI_SR_FRE) == (SPI_SR_FRE)) ? 1UL : 0UL); 981:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 982:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 983:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 984:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Get FIFO reception Level 985:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll SR FRLVL LL_SPI_GetRxFIFOLevel 986:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 987:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval Returned value can be one of the following values: 988:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_RX_FIFO_EMPTY 989:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_RX_FIFO_QUARTER_FULL 990:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_RX_FIFO_HALF_FULL 991:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_RX_FIFO_FULL 992:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 993:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_GetRxFIFOLevel(SPI_TypeDef *SPIx) 994:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 995:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** return (uint32_t)(READ_BIT(SPIx->SR, SPI_SR_FRLVL)); 996:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 997:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 998:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 999:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Get FIFO Transmission Level 1000:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll SR FTLVL LL_SPI_GetTxFIFOLevel 1001:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 1002:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval Returned value can be one of the following values: ARM GAS /tmp/ccLSPxIe.s page 146 1003:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_TX_FIFO_EMPTY 1004:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_TX_FIFO_QUARTER_FULL 1005:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_TX_FIFO_HALF_FULL 1006:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_TX_FIFO_FULL 1007:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 1008:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_GetTxFIFOLevel(SPI_TypeDef *SPIx) 1009:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 1010:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** return (uint32_t)(READ_BIT(SPIx->SR, SPI_SR_FTLVL)); 1011:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1012:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 1013:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 1014:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Clear CRC error flag 1015:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll SR CRCERR LL_SPI_ClearFlag_CRCERR 1016:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 1017:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None 1018:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 1019:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_ClearFlag_CRCERR(SPI_TypeDef *SPIx) 1020:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 1021:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** CLEAR_BIT(SPIx->SR, SPI_SR_CRCERR); 1022:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1023:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 1024:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 1025:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Clear mode fault error flag 1026:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @note Clearing this flag is done by a read access to the SPIx_SR 1027:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * register followed by a write access to the SPIx_CR1 register 1028:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll SR MODF LL_SPI_ClearFlag_MODF 1029:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 1030:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None 1031:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 1032:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_ClearFlag_MODF(SPI_TypeDef *SPIx) 1033:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 1034:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __IO uint32_t tmpreg_sr; 1035:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** tmpreg_sr = SPIx->SR; 1036:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** (void) tmpreg_sr; 1037:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE); 1038:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1039:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 1040:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 1041:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Clear overrun error flag 1042:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @note Clearing this flag is done by a read access to the SPIx_DR 1043:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * register followed by a read access to the SPIx_SR register 1044:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll SR OVR LL_SPI_ClearFlag_OVR 1045:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 1046:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None 1047:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 1048:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_ClearFlag_OVR(SPI_TypeDef *SPIx) 1049:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 1050:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __IO uint32_t tmpreg; 1051:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** tmpreg = SPIx->DR; 1052:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** (void) tmpreg; 1053:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** tmpreg = SPIx->SR; 1054:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** (void) tmpreg; 1055:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1056:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 1057:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 1058:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Clear frame format error flag 1059:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @note Clearing this flag is done by reading SPIx_SR register ARM GAS /tmp/ccLSPxIe.s page 147 1060:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll SR FRE LL_SPI_ClearFlag_FRE 1061:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 1062:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None 1063:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 1064:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_ClearFlag_FRE(SPI_TypeDef *SPIx) 1065:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 1066:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __IO uint32_t tmpreg; 1067:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** tmpreg = SPIx->SR; 1068:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** (void) tmpreg; 1069:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1070:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 1071:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 1072:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @} 1073:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 1074:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 1075:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_EF_IT_Management Interrupt Management 1076:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @{ 1077:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 1078:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 1079:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 1080:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Enable error interrupt 1081:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @note This bit controls the generation of an interrupt when an error condition occurs (CRCERR 1082:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR2 ERRIE LL_SPI_EnableIT_ERR 1083:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 1084:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None 1085:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 1086:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_EnableIT_ERR(SPI_TypeDef *SPIx) 1087:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 1088:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** SET_BIT(SPIx->CR2, SPI_CR2_ERRIE); 1089:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1090:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 1091:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 1092:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Enable Rx buffer not empty interrupt 1093:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR2 RXNEIE LL_SPI_EnableIT_RXNE 1094:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 1095:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None 1096:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 1097:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_EnableIT_RXNE(SPI_TypeDef *SPIx) 1098:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 1099:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** SET_BIT(SPIx->CR2, SPI_CR2_RXNEIE); 1100:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1101:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 1102:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 1103:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Enable Tx buffer empty interrupt 1104:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR2 TXEIE LL_SPI_EnableIT_TXE 1105:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 1106:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None 1107:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 1108:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_EnableIT_TXE(SPI_TypeDef *SPIx) 1109:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 1110:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** SET_BIT(SPIx->CR2, SPI_CR2_TXEIE); 1111:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1112:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 1113:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 1114:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Disable error interrupt 1115:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @note This bit controls the generation of an interrupt when an error condition occurs (CRCERR 1116:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR2 ERRIE LL_SPI_DisableIT_ERR ARM GAS /tmp/ccLSPxIe.s page 148 1117:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 1118:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None 1119:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 1120:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_DisableIT_ERR(SPI_TypeDef *SPIx) 1121:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 1122:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** CLEAR_BIT(SPIx->CR2, SPI_CR2_ERRIE); 1123:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1124:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 1125:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 1126:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Disable Rx buffer not empty interrupt 1127:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR2 RXNEIE LL_SPI_DisableIT_RXNE 1128:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 1129:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None 1130:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 1131:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_DisableIT_RXNE(SPI_TypeDef *SPIx) 1132:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 1133:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** CLEAR_BIT(SPIx->CR2, SPI_CR2_RXNEIE); 1134:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1135:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 1136:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 1137:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Disable Tx buffer empty interrupt 1138:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR2 TXEIE LL_SPI_DisableIT_TXE 1139:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 1140:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None 1141:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 1142:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_DisableIT_TXE(SPI_TypeDef *SPIx) 1143:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 1144:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** CLEAR_BIT(SPIx->CR2, SPI_CR2_TXEIE); 1145:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1146:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 1147:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 1148:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Check if error interrupt is enabled 1149:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR2 ERRIE LL_SPI_IsEnabledIT_ERR 1150:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 1151:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval State of bit (1 or 0). 1152:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 1153:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_ERR(SPI_TypeDef *SPIx) 1154:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 1155:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** return ((READ_BIT(SPIx->CR2, SPI_CR2_ERRIE) == (SPI_CR2_ERRIE)) ? 1UL : 0UL); 1156:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1157:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 1158:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 1159:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Check if Rx buffer not empty interrupt is enabled 1160:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR2 RXNEIE LL_SPI_IsEnabledIT_RXNE 1161:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 1162:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval State of bit (1 or 0). 1163:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 1164:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_RXNE(SPI_TypeDef *SPIx) 1165:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 1166:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** return ((READ_BIT(SPIx->CR2, SPI_CR2_RXNEIE) == (SPI_CR2_RXNEIE)) ? 1UL : 0UL); 1167:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1168:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 1169:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 1170:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Check if Tx buffer empty interrupt 1171:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR2 TXEIE LL_SPI_IsEnabledIT_TXE 1172:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 1173:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval State of bit (1 or 0). ARM GAS /tmp/ccLSPxIe.s page 149 1174:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 1175:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_TXE(SPI_TypeDef *SPIx) 1176:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 1177:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** return ((READ_BIT(SPIx->CR2, SPI_CR2_TXEIE) == (SPI_CR2_TXEIE)) ? 1UL : 0UL); 1178:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1179:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 1180:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 1181:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @} 1182:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 1183:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 1184:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_EF_DMA_Management DMA Management 1185:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @{ 1186:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 1187:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 1188:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 1189:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Enable DMA Rx 1190:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR2 RXDMAEN LL_SPI_EnableDMAReq_RX 1191:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 1192:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None 1193:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 1194:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_EnableDMAReq_RX(SPI_TypeDef *SPIx) 1195:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 1196:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** SET_BIT(SPIx->CR2, SPI_CR2_RXDMAEN); 1197:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1198:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 1199:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 1200:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Disable DMA Rx 1201:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR2 RXDMAEN LL_SPI_DisableDMAReq_RX 1202:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 1203:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None 1204:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 1205:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_DisableDMAReq_RX(SPI_TypeDef *SPIx) 1206:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 1207:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** CLEAR_BIT(SPIx->CR2, SPI_CR2_RXDMAEN); 1208:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1209:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 1210:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 1211:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Check if DMA Rx is enabled 1212:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR2 RXDMAEN LL_SPI_IsEnabledDMAReq_RX 1213:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 1214:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval State of bit (1 or 0). 1215:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 1216:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_RX(SPI_TypeDef *SPIx) 1217:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 1218:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** return ((READ_BIT(SPIx->CR2, SPI_CR2_RXDMAEN) == (SPI_CR2_RXDMAEN)) ? 1UL : 0UL); 1219:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1220:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 1221:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 1222:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Enable DMA Tx 1223:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR2 TXDMAEN LL_SPI_EnableDMAReq_TX 1224:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 1225:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None 1226:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 1227:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_EnableDMAReq_TX(SPI_TypeDef *SPIx) 1228:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 1229:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** SET_BIT(SPIx->CR2, SPI_CR2_TXDMAEN); 1230:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } ARM GAS /tmp/ccLSPxIe.s page 150 1231:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 1232:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 1233:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Disable DMA Tx 1234:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR2 TXDMAEN LL_SPI_DisableDMAReq_TX 1235:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 1236:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None 1237:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 1238:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_DisableDMAReq_TX(SPI_TypeDef *SPIx) 1239:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 1240:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** CLEAR_BIT(SPIx->CR2, SPI_CR2_TXDMAEN); 1241:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1242:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 1243:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 1244:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Check if DMA Tx is enabled 1245:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR2 TXDMAEN LL_SPI_IsEnabledDMAReq_TX 1246:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 1247:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval State of bit (1 or 0). 1248:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 1249:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx) 1250:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 1251:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** return ((READ_BIT(SPIx->CR2, SPI_CR2_TXDMAEN) == (SPI_CR2_TXDMAEN)) ? 1UL : 0UL); 1252:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1253:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 1254:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 1255:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Set parity of Last DMA reception 1256:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR2 LDMARX LL_SPI_SetDMAParity_RX 1257:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 1258:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param Parity This parameter can be one of the following values: 1259:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_DMA_PARITY_ODD 1260:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_DMA_PARITY_EVEN 1261:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None 1262:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 1263:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_SetDMAParity_RX(SPI_TypeDef *SPIx, uint32_t Parity) 1264:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 1265:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** MODIFY_REG(SPIx->CR2, SPI_CR2_LDMARX, (Parity << SPI_CR2_LDMARX_Pos)); 1266:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1267:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 1268:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 1269:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Get parity configuration for Last DMA reception 1270:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR2 LDMARX LL_SPI_GetDMAParity_RX 1271:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 1272:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval Returned value can be one of the following values: 1273:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_DMA_PARITY_ODD 1274:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_DMA_PARITY_EVEN 1275:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 1276:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_GetDMAParity_RX(SPI_TypeDef *SPIx) 1277:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 1278:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_LDMARX) >> SPI_CR2_LDMARX_Pos); 1279:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1280:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 1281:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 1282:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Set parity of Last DMA transmission 1283:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR2 LDMATX LL_SPI_SetDMAParity_TX 1284:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 1285:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param Parity This parameter can be one of the following values: 1286:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_DMA_PARITY_ODD 1287:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_DMA_PARITY_EVEN ARM GAS /tmp/ccLSPxIe.s page 151 1288:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None 1289:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 1290:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_SetDMAParity_TX(SPI_TypeDef *SPIx, uint32_t Parity) 1291:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 1292:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** MODIFY_REG(SPIx->CR2, SPI_CR2_LDMATX, (Parity << SPI_CR2_LDMATX_Pos)); 1293:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1294:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 1295:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 1296:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Get parity configuration for Last DMA transmission 1297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR2 LDMATX LL_SPI_GetDMAParity_TX 1298:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 1299:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval Returned value can be one of the following values: 1300:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_DMA_PARITY_ODD 1301:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_DMA_PARITY_EVEN 1302:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 1303:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_GetDMAParity_TX(SPI_TypeDef *SPIx) 1304:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 1305:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_LDMATX) >> SPI_CR2_LDMATX_Pos); 1306:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1307:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 1308:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 1309:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Get the data register address used for DMA transfer 1310:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll DR DR LL_SPI_DMA_GetRegAddr 1311:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 1312:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval Address of data register 1313:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 1314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_DMA_GetRegAddr(SPI_TypeDef *SPIx) 1315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 1316:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** return (uint32_t) &(SPIx->DR); 1317:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1318:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 1319:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 1320:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @} 1321:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 1322:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 1323:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_EF_DATA_Management DATA Management 1324:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @{ 1325:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 1326:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 1327:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 1328:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Read 8-Bits in the data register 1329:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll DR DR LL_SPI_ReceiveData8 1330:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 1331:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval RxData Value between Min_Data=0x00 and Max_Data=0xFF 1332:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 1333:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint8_t LL_SPI_ReceiveData8(SPI_TypeDef *SPIx) 1334:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 1335:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** return (*((__IO uint8_t *)&SPIx->DR)); 1336:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1337:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 1338:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 1339:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Read 16-Bits in the data register 1340:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll DR DR LL_SPI_ReceiveData16 1341:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 1342:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval RxData Value between Min_Data=0x00 and Max_Data=0xFFFF 1343:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 1344:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint16_t LL_SPI_ReceiveData16(SPI_TypeDef *SPIx) ARM GAS /tmp/ccLSPxIe.s page 152 1345:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 1346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** return (uint16_t)(READ_REG(SPIx->DR)); 1347:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1348:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 1349:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 1350:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Write 8-Bits in the data register 1351:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll DR DR LL_SPI_TransmitData8 1352:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 1353:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param TxData Value between Min_Data=0x00 and Max_Data=0xFF 1354:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None 1355:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 1356:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_TransmitData8(SPI_TypeDef *SPIx, uint8_t TxData) 1357:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 1358:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #if defined (__GNUC__) 1359:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __IO uint8_t *spidr = ((__IO uint8_t *)&SPIx->DR); 1360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** *spidr = TxData; 1361:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #else 1362:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** *((__IO uint8_t *)&SPIx->DR) = TxData; 1363:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #endif /* __GNUC__ */ 1364:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1365:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 1366:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** 1367:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Write 16-Bits in the data register 1368:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll DR DR LL_SPI_TransmitData16 1369:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance 1370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param TxData Value between Min_Data=0x00 and Max_Data=0xFFFF 1371:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None 1372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ 1373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData) 1051 .loc 4 1373 22 view .LVU347 1052 .LBB382: 1374:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 1375:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #if defined (__GNUC__) 1376:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __IO uint16_t *spidr = ((__IO uint16_t *)&SPIx->DR); 1053 .loc 4 1376 3 view .LVU348 1377:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** *spidr = TxData; 1054 .loc 4 1377 3 view .LVU349 1055 .loc 4 1377 10 is_stmt 0 view .LVU350 1056 0060 1B4B ldr r3, .L59+8 1057 0062 9D81 strh r5, [r3, #12] @ movhi 1058 .LVL78: 1059 .loc 4 1377 10 view .LVU351 1060 .LBE382: 1061 .LBE381: 2892:Src/main.c **** while((!LL_SPI_IsActiveFlag_RXNE(SPI2)) && (tmp32++ < 1000)) {} 1062 .loc 1 2892 2 is_stmt 1 view .LVU352 2893:Src/main.c **** (void) SPI2->DR; 1063 .loc 1 2893 2 view .LVU353 2892:Src/main.c **** while((!LL_SPI_IsActiveFlag_RXNE(SPI2)) && (tmp32++ < 1000)) {} 1064 .loc 1 2892 8 is_stmt 0 view .LVU354 1065 0064 0023 movs r3, #0 1066 .LVL79: 1067 .L49: 2893:Src/main.c **** (void) SPI2->DR; 1068 .loc 1 2893 64 is_stmt 1 discriminator 2 view .LVU355 2893:Src/main.c **** (void) SPI2->DR; 1069 .loc 1 2893 42 discriminator 2 view .LVU356 ARM GAS /tmp/ccLSPxIe.s page 153 1070 .LBB383: 1071 .LBI383: 905:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 1072 .loc 4 905 26 view .LVU357 1073 .LBB384: 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1074 .loc 4 907 3 view .LVU358 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1075 .loc 4 907 12 is_stmt 0 view .LVU359 1076 0066 1A4A ldr r2, .L59+8 1077 0068 9268 ldr r2, [r2, #8] 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1078 .loc 4 907 68 view .LVU360 1079 006a 12F0010F tst r2, #1 1080 006e 05D1 bne .L48 1081 .LVL80: 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1082 .loc 4 907 68 view .LVU361 1083 .LBE384: 1084 .LBE383: 2893:Src/main.c **** (void) SPI2->DR; 1085 .loc 1 2893 51 discriminator 1 view .LVU362 1086 0070 5A1C adds r2, r3, #1 1087 .LVL81: 2893:Src/main.c **** (void) SPI2->DR; 1088 .loc 1 2893 42 discriminator 1 view .LVU363 1089 0072 B3F57A7F cmp r3, #1000 1090 0076 01D2 bcs .L48 2893:Src/main.c **** (void) SPI2->DR; 1091 .loc 1 2893 51 discriminator 1 view .LVU364 1092 0078 1346 mov r3, r2 1093 007a F4E7 b .L49 1094 .LVL82: 1095 .L48: 2894:Src/main.c **** 1096 .loc 1 2894 2 is_stmt 1 view .LVU365 1097 007c 144B ldr r3, .L59+8 1098 007e DB68 ldr r3, [r3, #12] 2896:Src/main.c **** while((!LL_SPI_IsActiveFlag_TXE(SPI2)) && (tmp32++ < 1000)) {} 1099 .loc 1 2896 2 view .LVU366 1100 .LVL83: 2897:Src/main.c **** LL_SPI_TransmitData16(SPI2, value); 1101 .loc 1 2897 2 view .LVU367 2896:Src/main.c **** while((!LL_SPI_IsActiveFlag_TXE(SPI2)) && (tmp32++ < 1000)) {} 1102 .loc 1 2896 8 is_stmt 0 view .LVU368 1103 0080 0023 movs r3, #0 1104 .LVL84: 1105 .L51: 2897:Src/main.c **** LL_SPI_TransmitData16(SPI2, value); 1106 .loc 1 2897 63 is_stmt 1 discriminator 2 view .LVU369 2897:Src/main.c **** LL_SPI_TransmitData16(SPI2, value); 1107 .loc 1 2897 41 discriminator 2 view .LVU370 1108 .LBB385: 1109 .LBI385: 916:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 1110 .loc 4 916 26 view .LVU371 1111 .LBB386: ARM GAS /tmp/ccLSPxIe.s page 154 918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1112 .loc 4 918 3 view .LVU372 918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1113 .loc 4 918 12 is_stmt 0 view .LVU373 1114 0082 134A ldr r2, .L59+8 1115 0084 9268 ldr r2, [r2, #8] 918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1116 .loc 4 918 66 view .LVU374 1117 0086 12F0020F tst r2, #2 1118 008a 05D1 bne .L50 1119 .LVL85: 918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1120 .loc 4 918 66 view .LVU375 1121 .LBE386: 1122 .LBE385: 2897:Src/main.c **** LL_SPI_TransmitData16(SPI2, value); 1123 .loc 1 2897 50 discriminator 1 view .LVU376 1124 008c 5A1C adds r2, r3, #1 1125 .LVL86: 2897:Src/main.c **** LL_SPI_TransmitData16(SPI2, value); 1126 .loc 1 2897 41 discriminator 1 view .LVU377 1127 008e B3F57A7F cmp r3, #1000 1128 0092 01D2 bcs .L50 2897:Src/main.c **** LL_SPI_TransmitData16(SPI2, value); 1129 .loc 1 2897 50 discriminator 1 view .LVU378 1130 0094 1346 mov r3, r2 1131 0096 F4E7 b .L51 1132 .LVL87: 1133 .L50: 2898:Src/main.c **** tmp32 = 0; 1134 .loc 1 2898 2 is_stmt 1 view .LVU379 1135 .LBB387: 1136 .LBI387: 1373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 1137 .loc 4 1373 22 view .LVU380 1138 .LBB388: 1376:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** *spidr = TxData; 1139 .loc 4 1376 3 view .LVU381 1140 .loc 4 1377 3 view .LVU382 1141 .loc 4 1377 10 is_stmt 0 view .LVU383 1142 0098 0D4B ldr r3, .L59+8 1143 009a 9C81 strh r4, [r3, #12] @ movhi 1144 .LVL88: 1145 .loc 4 1377 10 view .LVU384 1146 .LBE388: 1147 .LBE387: 2899:Src/main.c **** while((!LL_SPI_IsActiveFlag_RXNE(SPI2)) && (tmp32++ < 1000)) {} 1148 .loc 1 2899 2 is_stmt 1 view .LVU385 2900:Src/main.c **** (void) SPI2->DR; 1149 .loc 1 2900 2 view .LVU386 2899:Src/main.c **** while((!LL_SPI_IsActiveFlag_RXNE(SPI2)) && (tmp32++ < 1000)) {} 1150 .loc 1 2899 8 is_stmt 0 view .LVU387 1151 009c 0023 movs r3, #0 1152 .LVL89: 1153 .L53: 2900:Src/main.c **** (void) SPI2->DR; 1154 .loc 1 2900 64 is_stmt 1 discriminator 2 view .LVU388 ARM GAS /tmp/ccLSPxIe.s page 155 2900:Src/main.c **** (void) SPI2->DR; 1155 .loc 1 2900 42 discriminator 2 view .LVU389 1156 .LBB389: 1157 .LBI389: 905:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 1158 .loc 4 905 26 view .LVU390 1159 .LBB390: 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1160 .loc 4 907 3 view .LVU391 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1161 .loc 4 907 12 is_stmt 0 view .LVU392 1162 009e 0C4A ldr r2, .L59+8 1163 00a0 9268 ldr r2, [r2, #8] 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1164 .loc 4 907 68 view .LVU393 1165 00a2 12F0010F tst r2, #1 1166 00a6 05D1 bne .L52 1167 .LVL90: 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 1168 .loc 4 907 68 view .LVU394 1169 .LBE390: 1170 .LBE389: 2900:Src/main.c **** (void) SPI2->DR; 1171 .loc 1 2900 51 discriminator 1 view .LVU395 1172 00a8 5A1C adds r2, r3, #1 1173 .LVL91: 2900:Src/main.c **** (void) SPI2->DR; 1174 .loc 1 2900 42 discriminator 1 view .LVU396 1175 00aa B3F57A7F cmp r3, #1000 1176 00ae 01D2 bcs .L52 2900:Src/main.c **** (void) SPI2->DR; 1177 .loc 1 2900 51 discriminator 1 view .LVU397 1178 00b0 1346 mov r3, r2 1179 00b2 F4E7 b .L53 1180 .LVL92: 1181 .L52: 2901:Src/main.c **** 1182 .loc 1 2901 2 is_stmt 1 view .LVU398 1183 00b4 064B ldr r3, .L59+8 1184 00b6 DB68 ldr r3, [r3, #12] 2903:Src/main.c **** } 1185 .loc 1 2903 2 view .LVU399 1186 00b8 0122 movs r2, #1 1187 00ba 4FF48051 mov r1, #4096 1188 00be 0248 ldr r0, .L59 1189 00c0 FFF7FEFF bl HAL_GPIO_WritePin 1190 .LVL93: 2904:Src/main.c **** 1191 .loc 1 2904 1 is_stmt 0 view .LVU400 1192 00c4 38BD pop {r3, r4, r5, pc} 1193 .LVL94: 1194 .L60: 2904:Src/main.c **** 1195 .loc 1 2904 1 view .LVU401 1196 00c6 00BF .align 2 1197 .L59: 1198 00c8 00040240 .word 1073873920 ARM GAS /tmp/ccLSPxIe.s page 156 1199 00cc 000C0240 .word 1073875968 1200 00d0 00380040 .word 1073756160 1201 .cfi_endproc 1202 .LFE1219: 1204 .section .text.AD9102_WriteRegTable,"ax",%progbits 1205 .align 1 1206 .syntax unified 1207 .thumb 1208 .thumb_func 1210 AD9102_WriteRegTable: 1211 .LVL95: 1212 .LFB1221: 2942:Src/main.c **** for (uint16_t i = 0; i < count; i++) 1213 .loc 1 2942 1 is_stmt 1 view -0 1214 .cfi_startproc 1215 @ args = 0, pretend = 0, frame = 0 1216 @ frame_needed = 0, uses_anonymous_args = 0 2942:Src/main.c **** for (uint16_t i = 0; i < count; i++) 1217 .loc 1 2942 1 is_stmt 0 view .LVU403 1218 0000 70B5 push {r4, r5, r6, lr} 1219 .LCFI10: 1220 .cfi_def_cfa_offset 16 1221 .cfi_offset 4, -16 1222 .cfi_offset 5, -12 1223 .cfi_offset 6, -8 1224 .cfi_offset 14, -4 1225 0002 0646 mov r6, r0 1226 0004 0D46 mov r5, r1 2943:Src/main.c **** { 1227 .loc 1 2943 2 is_stmt 1 view .LVU404 1228 .LBB391: 2943:Src/main.c **** { 1229 .loc 1 2943 7 view .LVU405 1230 .LVL96: 2943:Src/main.c **** { 1231 .loc 1 2943 16 is_stmt 0 view .LVU406 1232 0006 0024 movs r4, #0 2943:Src/main.c **** { 1233 .loc 1 2943 2 view .LVU407 1234 0008 08E0 b .L62 1235 .LVL97: 1236 .L63: 2945:Src/main.c **** } 1237 .loc 1 2945 3 is_stmt 1 view .LVU408 1238 000a 36F81410 ldrh r1, [r6, r4, lsl #1] 1239 000e 054B ldr r3, .L65 1240 0010 33F81400 ldrh r0, [r3, r4, lsl #1] 1241 0014 FFF7FEFF bl AD9102_WriteReg 1242 .LVL98: 2943:Src/main.c **** { 1243 .loc 1 2943 35 discriminator 3 view .LVU409 1244 0018 0134 adds r4, r4, #1 1245 .LVL99: 2943:Src/main.c **** { 1246 .loc 1 2943 35 is_stmt 0 discriminator 3 view .LVU410 1247 001a A4B2 uxth r4, r4 1248 .LVL100: ARM GAS /tmp/ccLSPxIe.s page 157 1249 .L62: 2943:Src/main.c **** { 1250 .loc 1 2943 25 is_stmt 1 discriminator 1 view .LVU411 1251 001c AC42 cmp r4, r5 1252 001e F4D3 bcc .L63 1253 .LBE391: 2947:Src/main.c **** 1254 .loc 1 2947 1 is_stmt 0 view .LVU412 1255 0020 70BD pop {r4, r5, r6, pc} 1256 .LVL101: 1257 .L66: 2947:Src/main.c **** 1258 .loc 1 2947 1 view .LVU413 1259 0022 00BF .align 2 1260 .L65: 1261 0024 00000000 .word ad9102_reg_addr 1262 .cfi_endproc 1263 .LFE1221: 1265 .section .text.AD9102_LoadSramRamp,"ax",%progbits 1266 .align 1 1267 .syntax unified 1268 .thumb 1269 .thumb_func 1271 AD9102_LoadSramRamp: 1272 .LVL102: 1273 .LFB1231: 3155:Src/main.c **** if (samples < 2u) 1274 .loc 1 3155 1 is_stmt 1 view -0 1275 .cfi_startproc 1276 @ args = 0, pretend = 0, frame = 0 1277 @ frame_needed = 0, uses_anonymous_args = 0 3155:Src/main.c **** if (samples < 2u) 1278 .loc 1 3155 1 is_stmt 0 view .LVU415 1279 0000 F8B5 push {r3, r4, r5, r6, r7, lr} 1280 .LCFI11: 1281 .cfi_def_cfa_offset 24 1282 .cfi_offset 3, -24 1283 .cfi_offset 4, -20 1284 .cfi_offset 5, -16 1285 .cfi_offset 6, -12 1286 .cfi_offset 7, -8 1287 .cfi_offset 14, -4 1288 0002 0F46 mov r7, r1 1289 0004 1646 mov r6, r2 3156:Src/main.c **** { 1290 .loc 1 3156 2 is_stmt 1 view .LVU416 3156:Src/main.c **** { 1291 .loc 1 3156 5 is_stmt 0 view .LVU417 1292 0006 0128 cmp r0, #1 1293 0008 06D9 bls .L81 1294 000a 0546 mov r5, r0 3160:Src/main.c **** { 1295 .loc 1 3160 2 is_stmt 1 view .LVU418 3160:Src/main.c **** { 1296 .loc 1 3160 5 is_stmt 0 view .LVU419 1297 000c B0F5805F cmp r0, #4096 1298 0010 03D9 bls .L68 ARM GAS /tmp/ccLSPxIe.s page 158 3162:Src/main.c **** } 1299 .loc 1 3162 11 view .LVU420 1300 0012 4FF48055 mov r5, #4096 1301 0016 00E0 b .L68 1302 .L81: 3158:Src/main.c **** } 1303 .loc 1 3158 11 view .LVU421 1304 0018 0225 movs r5, #2 1305 .L68: 1306 .LVL103: 3164:Src/main.c **** { 1307 .loc 1 3164 2 is_stmt 1 view .LVU422 3164:Src/main.c **** { 1308 .loc 1 3164 5 is_stmt 0 view .LVU423 1309 001a B6F5005F cmp r6, #8192 1310 001e 01D3 bcc .L69 3166:Src/main.c **** } 1311 .loc 1 3166 13 view .LVU424 1312 0020 41F6FF76 movw r6, #8191 1313 .L69: 1314 .LVL104: 3170:Src/main.c **** 1315 .loc 1 3170 2 is_stmt 1 view .LVU425 1316 0024 0421 movs r1, #4 1317 .LVL105: 3170:Src/main.c **** 1318 .loc 1 3170 2 is_stmt 0 view .LVU426 1319 0026 1E20 movs r0, #30 1320 0028 FFF7FEFF bl AD9102_WriteReg 1321 .LVL106: 3172:Src/main.c **** { 1322 .loc 1 3172 2 is_stmt 1 view .LVU427 1323 .LBB392: 3172:Src/main.c **** { 1324 .loc 1 3172 7 view .LVU428 3172:Src/main.c **** { 1325 .loc 1 3172 16 is_stmt 0 view .LVU429 1326 002c 0024 movs r4, #0 3172:Src/main.c **** { 1327 .loc 1 3172 2 view .LVU430 1328 002e 2DE0 b .L70 1329 .LVL107: 1330 .L92: 1331 .LBB393: 1332 .LBB394: 3183:Src/main.c **** } 1333 .loc 1 3183 10 view .LVU431 1334 0030 0122 movs r2, #1 1335 .LVL108: 3183:Src/main.c **** } 1336 .loc 1 3183 10 view .LVU432 1337 0032 34E0 b .L72 1338 .LVL109: 1339 .L85: 1340 .LBB395: 3187:Src/main.c **** if (span == 0) 1341 .loc 1 3187 14 discriminator 2 view .LVU433 ARM GAS /tmp/ccLSPxIe.s page 159 1342 0034 0122 movs r2, #1 1343 .LVL110: 3187:Src/main.c **** if (span == 0) 1344 .loc 1 3187 14 discriminator 2 view .LVU434 1345 0036 38E0 b .L74 1346 .LVL111: 1347 .L73: 3187:Src/main.c **** if (span == 0) 1348 .loc 1 3187 14 discriminator 2 view .LVU435 1349 .LBE395: 1350 .LBB396: 3199:Src/main.c **** uint16_t denom = (tail > 1u) ? (uint16_t)(tail - 1u) : 1u; 1351 .loc 1 3199 5 is_stmt 1 view .LVU436 3199:Src/main.c **** uint16_t denom = (tail > 1u) ? (uint16_t)(tail - 1u) : 1u; 1352 .loc 1 3199 14 is_stmt 0 view .LVU437 1353 0038 A91A subs r1, r5, r2 1354 003a 89B2 uxth r1, r1 1355 .LVL112: 3200:Src/main.c **** if (span == 0) 1356 .loc 1 3200 5 is_stmt 1 view .LVU438 3200:Src/main.c **** if (span == 0) 1357 .loc 1 3200 14 is_stmt 0 view .LVU439 1358 003c 0129 cmp r1, #1 1359 003e 09D9 bls .L86 3200:Src/main.c **** if (span == 0) 1360 .loc 1 3200 14 discriminator 1 view .LVU440 1361 0040 0139 subs r1, r1, #1 1362 .LVL113: 3200:Src/main.c **** if (span == 0) 1363 .loc 1 3200 14 discriminator 1 view .LVU441 1364 0042 89B2 uxth r1, r1 1365 .LVL114: 1366 .L77: 3201:Src/main.c **** { 1367 .loc 1 3201 5 is_stmt 1 view .LVU442 3201:Src/main.c **** { 1368 .loc 1 3201 8 is_stmt 0 view .LVU443 1369 0044 ABB1 cbz r3, .L75 3207:Src/main.c **** } 1370 .loc 1 3207 6 is_stmt 1 view .LVU444 3207:Src/main.c **** } 1371 .loc 1 3207 44 is_stmt 0 view .LVU445 1372 0046 A21A subs r2, r4, r2 1373 .LVL115: 3207:Src/main.c **** } 1374 .loc 1 3207 30 view .LVU446 1375 0048 03FB02F2 mul r2, r3, r2 3207:Src/main.c **** } 1376 .loc 1 3207 53 view .LVU447 1377 004c 92FBF1F2 sdiv r2, r2, r1 3207:Src/main.c **** } 1378 .loc 1 3207 12 view .LVU448 1379 0050 831A subs r3, r0, r2 1380 .LVL116: 3207:Src/main.c **** } 1381 .loc 1 3207 12 view .LVU449 1382 0052 0BE0 b .L76 ARM GAS /tmp/ccLSPxIe.s page 160 1383 .LVL117: 1384 .L86: 3200:Src/main.c **** if (span == 0) 1385 .loc 1 3200 14 discriminator 2 view .LVU450 1386 0054 0121 movs r1, #1 1387 .LVL118: 3200:Src/main.c **** if (span == 0) 1388 .loc 1 3200 14 discriminator 2 view .LVU451 1389 0056 F5E7 b .L77 1390 .LVL119: 1391 .L71: 3200:Src/main.c **** if (span == 0) 1392 .loc 1 3200 14 discriminator 2 view .LVU452 1393 .LBE396: 1394 .LBE394: 1395 .LBB398: 3213:Src/main.c **** if (span == 0) 1396 .loc 1 3213 4 is_stmt 1 view .LVU453 3213:Src/main.c **** if (span == 0) 1397 .loc 1 3213 13 is_stmt 0 view .LVU454 1398 0058 012D cmp r5, #1 1399 005a 2ED9 bls .L87 3213:Src/main.c **** if (span == 0) 1400 .loc 1 3213 13 discriminator 1 view .LVU455 1401 005c 6A1E subs r2, r5, #1 1402 005e 92B2 uxth r2, r2 1403 .L78: 1404 .LVL120: 3214:Src/main.c **** { 1405 .loc 1 3214 4 is_stmt 1 view .LVU456 3214:Src/main.c **** { 1406 .loc 1 3214 7 is_stmt 0 view .LVU457 1407 0060 3BB1 cbz r3, .L75 3220:Src/main.c **** } 1408 .loc 1 3220 5 is_stmt 1 view .LVU458 3220:Src/main.c **** } 1409 .loc 1 3220 29 is_stmt 0 view .LVU459 1410 0062 04FB03F3 mul r3, r4, r3 1411 .LVL121: 3220:Src/main.c **** } 1412 .loc 1 3220 43 view .LVU460 1413 0066 93FBF2F3 sdiv r3, r3, r2 1414 006a 1B1A subs r3, r3, r0 1415 .LVL122: 1416 .L76: 3220:Src/main.c **** } 1417 .loc 1 3220 43 view .LVU461 1418 .LBE398: 3224:Src/main.c **** { 1419 .loc 1 3224 3 is_stmt 1 view .LVU462 3224:Src/main.c **** { 1420 .loc 1 3224 6 is_stmt 0 view .LVU463 1421 006c 13F5005F cmn r3, #8192 1422 0070 25DB blt .L88 1423 .LVL123: 1424 .L75: 3228:Src/main.c **** { ARM GAS /tmp/ccLSPxIe.s page 161 1425 .loc 1 3228 8 is_stmt 1 view .LVU464 3228:Src/main.c **** { 1426 .loc 1 3228 11 is_stmt 0 view .LVU465 1427 0072 B3F5005F cmp r3, #8192 1428 0076 24DA bge .L89 1429 .L79: 1430 .LVL124: 3233:Src/main.c **** uint16_t word = (uint16_t)(sample_u14 << 2); 1431 .loc 1 3233 3 is_stmt 1 view .LVU466 3233:Src/main.c **** uint16_t word = (uint16_t)(sample_u14 << 2); 1432 .loc 1 3233 25 is_stmt 0 view .LVU467 1433 0078 99B2 uxth r1, r3 1434 .LVL125: 3234:Src/main.c **** AD9102_WriteReg((uint16_t)(AD9102_REG_SRAM_DATA_BASE + i), word); 1435 .loc 1 3234 3 is_stmt 1 view .LVU468 3235:Src/main.c **** } 1436 .loc 1 3235 3 view .LVU469 1437 007a 8900 lsls r1, r1, #2 1438 .LVL126: 3235:Src/main.c **** } 1439 .loc 1 3235 3 is_stmt 0 view .LVU470 1440 007c 89B2 uxth r1, r1 1441 007e 04F5C040 add r0, r4, #24576 1442 .LVL127: 3235:Src/main.c **** } 1443 .loc 1 3235 3 view .LVU471 1444 0082 80B2 uxth r0, r0 1445 0084 FFF7FEFF bl AD9102_WriteReg 1446 .LVL128: 3235:Src/main.c **** } 1447 .loc 1 3235 3 view .LVU472 1448 .LBE393: 3172:Src/main.c **** { 1449 .loc 1 3172 37 is_stmt 1 discriminator 2 view .LVU473 1450 0088 0134 adds r4, r4, #1 1451 .LVL129: 3172:Src/main.c **** { 1452 .loc 1 3172 37 is_stmt 0 discriminator 2 view .LVU474 1453 008a A4B2 uxth r4, r4 1454 .LVL130: 1455 .L70: 3172:Src/main.c **** { 1456 .loc 1 3172 25 is_stmt 1 discriminator 1 view .LVU475 1457 008c A542 cmp r5, r4 1458 008e 1BD9 bls .L91 1459 .LBB401: 3174:Src/main.c **** int32_t min_val = -(int32_t)amplitude; 1460 .loc 1 3174 3 view .LVU476 3175:Src/main.c **** int32_t max_val = (int32_t)amplitude; 1461 .loc 1 3175 3 view .LVU477 3175:Src/main.c **** int32_t max_val = (int32_t)amplitude; 1462 .loc 1 3175 22 is_stmt 0 view .LVU478 1463 0090 3046 mov r0, r6 1464 .LVL131: 3176:Src/main.c **** int32_t span = max_val - min_val; 1465 .loc 1 3176 3 is_stmt 1 view .LVU479 3177:Src/main.c **** if (triangle) ARM GAS /tmp/ccLSPxIe.s page 162 1466 .loc 1 3177 3 view .LVU480 3177:Src/main.c **** if (triangle) 1467 .loc 1 3177 11 is_stmt 0 view .LVU481 1468 0092 7300 lsls r3, r6, #1 1469 .LVL132: 3178:Src/main.c **** { 1470 .loc 1 3178 3 is_stmt 1 view .LVU482 3178:Src/main.c **** { 1471 .loc 1 3178 6 is_stmt 0 view .LVU483 1472 0094 002F cmp r7, #0 1473 0096 DFD0 beq .L71 1474 .LBB399: 3180:Src/main.c **** if (half == 0u) 1475 .loc 1 3180 4 is_stmt 1 view .LVU484 3180:Src/main.c **** if (half == 0u) 1476 .loc 1 3180 13 is_stmt 0 view .LVU485 1477 0098 6A08 lsrs r2, r5, #1 1478 .LVL133: 3181:Src/main.c **** { 1479 .loc 1 3181 4 is_stmt 1 view .LVU486 3181:Src/main.c **** { 1480 .loc 1 3181 7 is_stmt 0 view .LVU487 1481 009a 012D cmp r5, #1 1482 009c C8D9 bls .L92 1483 .LVL134: 1484 .L72: 3185:Src/main.c **** { 1485 .loc 1 3185 4 is_stmt 1 view .LVU488 3185:Src/main.c **** { 1486 .loc 1 3185 7 is_stmt 0 view .LVU489 1487 009e 9442 cmp r4, r2 1488 00a0 CAD2 bcs .L73 1489 .LBB397: 3187:Src/main.c **** if (span == 0) 1490 .loc 1 3187 5 is_stmt 1 view .LVU490 3187:Src/main.c **** if (span == 0) 1491 .loc 1 3187 14 is_stmt 0 view .LVU491 1492 00a2 012A cmp r2, #1 1493 00a4 C6D9 bls .L85 3187:Src/main.c **** if (span == 0) 1494 .loc 1 3187 14 discriminator 1 view .LVU492 1495 00a6 013A subs r2, r2, #1 1496 .LVL135: 3187:Src/main.c **** if (span == 0) 1497 .loc 1 3187 14 discriminator 1 view .LVU493 1498 00a8 92B2 uxth r2, r2 1499 .LVL136: 1500 .L74: 3188:Src/main.c **** { 1501 .loc 1 3188 5 is_stmt 1 view .LVU494 3188:Src/main.c **** { 1502 .loc 1 3188 8 is_stmt 0 view .LVU495 1503 00aa 002B cmp r3, #0 1504 00ac E1D0 beq .L75 3194:Src/main.c **** } 1505 .loc 1 3194 6 is_stmt 1 view .LVU496 3194:Src/main.c **** } ARM GAS /tmp/ccLSPxIe.s page 163 1506 .loc 1 3194 30 is_stmt 0 view .LVU497 1507 00ae 04FB03F3 mul r3, r4, r3 1508 .LVL137: 3194:Src/main.c **** } 1509 .loc 1 3194 44 view .LVU498 1510 00b2 93FBF2F3 sdiv r3, r3, r2 1511 00b6 1B1A subs r3, r3, r0 1512 .LVL138: 3194:Src/main.c **** } 1513 .loc 1 3194 44 view .LVU499 1514 00b8 D8E7 b .L76 1515 .LVL139: 1516 .L87: 3194:Src/main.c **** } 1517 .loc 1 3194 44 view .LVU500 1518 .LBE397: 1519 .LBE399: 1520 .LBB400: 3213:Src/main.c **** if (span == 0) 1521 .loc 1 3213 13 discriminator 2 view .LVU501 1522 00ba 0122 movs r2, #1 1523 00bc D0E7 b .L78 1524 .LVL140: 1525 .L88: 3213:Src/main.c **** if (span == 0) 1526 .loc 1 3213 13 discriminator 2 view .LVU502 1527 .LBE400: 3226:Src/main.c **** } 1528 .loc 1 3226 10 view .LVU503 1529 00be 054B ldr r3, .L93 1530 .LVL141: 3226:Src/main.c **** } 1531 .loc 1 3226 10 view .LVU504 1532 00c0 DAE7 b .L79 1533 .LVL142: 1534 .L89: 3230:Src/main.c **** } 1535 .loc 1 3230 10 view .LVU505 1536 00c2 41F6FF73 movw r3, #8191 1537 00c6 D7E7 b .L79 1538 .LVL143: 1539 .L91: 3230:Src/main.c **** } 1540 .loc 1 3230 10 view .LVU506 1541 .LBE401: 1542 .LBE392: 3239:Src/main.c **** } 1543 .loc 1 3239 2 is_stmt 1 view .LVU507 1544 00c8 0021 movs r1, #0 1545 00ca 1E20 movs r0, #30 1546 00cc FFF7FEFF bl AD9102_WriteReg 1547 .LVL144: 3240:Src/main.c **** 1548 .loc 1 3240 1 is_stmt 0 view .LVU508 1549 00d0 F8BD pop {r3, r4, r5, r6, r7, pc} 1550 .LVL145: 1551 .L94: ARM GAS /tmp/ccLSPxIe.s page 164 3240:Src/main.c **** 1552 .loc 1 3240 1 view .LVU509 1553 00d2 00BF .align 2 1554 .L93: 1555 00d4 00E0FFFF .word -8192 1556 .cfi_endproc 1557 .LFE1231: 1559 .section .text.AD9102_WriteWaveUploadChunk,"ax",%progbits 1560 .align 1 1561 .syntax unified 1562 .thumb 1563 .thumb_func 1565 AD9102_WriteWaveUploadChunk: 1566 .LVL146: 1567 .LFB1227: 3039:Src/main.c **** if (ad9102_wave_upload_active == 0u) 1568 .loc 1 3039 1 is_stmt 1 view -0 1569 .cfi_startproc 1570 @ args = 0, pretend = 0, frame = 0 1571 @ frame_needed = 0, uses_anonymous_args = 0 3039:Src/main.c **** if (ad9102_wave_upload_active == 0u) 1572 .loc 1 3039 1 is_stmt 0 view .LVU511 1573 0000 70B5 push {r4, r5, r6, lr} 1574 .LCFI12: 1575 .cfi_def_cfa_offset 16 1576 .cfi_offset 4, -16 1577 .cfi_offset 5, -12 1578 .cfi_offset 6, -8 1579 .cfi_offset 14, -4 1580 0002 0646 mov r6, r0 3040:Src/main.c **** { 1581 .loc 1 3040 2 is_stmt 1 view .LVU512 3040:Src/main.c **** { 1582 .loc 1 3040 32 is_stmt 0 view .LVU513 1583 0004 194B ldr r3, .L104 1584 0006 1878 ldrb r0, [r3] @ zero_extendqisi2 1585 .LVL147: 3040:Src/main.c **** { 1586 .loc 1 3040 5 view .LVU514 1587 0008 58B3 cbz r0, .L96 1588 000a 0D46 mov r5, r1 3044:Src/main.c **** { 1589 .loc 1 3044 2 is_stmt 1 view .LVU515 3044:Src/main.c **** { 1590 .loc 1 3044 26 is_stmt 0 view .LVU516 1591 000c 4B1E subs r3, r1, #1 1592 000e 9BB2 uxth r3, r3 3044:Src/main.c **** { 1593 .loc 1 3044 5 view .LVU517 1594 0010 0B2B cmp r3, #11 1595 0012 25D8 bhi .L99 3048:Src/main.c **** { 1596 .loc 1 3048 2 is_stmt 1 view .LVU518 3048:Src/main.c **** { 1597 .loc 1 3048 7 is_stmt 0 view .LVU519 1598 0014 164B ldr r3, .L104+4 1599 0016 1B88 ldrh r3, [r3] ARM GAS /tmp/ccLSPxIe.s page 165 3048:Src/main.c **** { 1600 .loc 1 3048 45 view .LVU520 1601 0018 0B44 add r3, r3, r1 3048:Src/main.c **** { 1602 .loc 1 3048 72 view .LVU521 1603 001a 164A ldr r2, .L104+8 1604 001c 1288 ldrh r2, [r2] 3048:Src/main.c **** { 1605 .loc 1 3048 5 view .LVU522 1606 001e 9342 cmp r3, r2 1607 0020 20D8 bhi .L100 1608 .LBB402: 3053:Src/main.c **** { 1609 .loc 1 3053 16 view .LVU523 1610 0022 0024 movs r4, #0 1611 .LVL148: 1612 .L97: 3053:Src/main.c **** { 1613 .loc 1 3053 25 is_stmt 1 discriminator 1 view .LVU524 1614 0024 AC42 cmp r4, r5 1615 0026 15D2 bcs .L103 1616 .LBB403: 3055:Src/main.c **** uint16_t sample_u14; 1617 .loc 1 3055 3 view .LVU525 3055:Src/main.c **** uint16_t sample_u14; 1618 .loc 1 3055 36 is_stmt 0 view .LVU526 1619 0028 36F81430 ldrh r3, [r6, r4, lsl #1] 1620 .LVL149: 3056:Src/main.c **** uint16_t word; 1621 .loc 1 3056 3 is_stmt 1 view .LVU527 3057:Src/main.c **** 1622 .loc 1 3057 3 view .LVU528 3059:Src/main.c **** { 1623 .loc 1 3059 3 view .LVU529 3059:Src/main.c **** { 1624 .loc 1 3059 39 is_stmt 0 view .LVU530 1625 002c 03F50052 add r2, r3, #8192 1626 0030 92B2 uxth r2, r2 3059:Src/main.c **** { 1627 .loc 1 3059 6 view .LVU531 1628 0032 B2F5804F cmp r2, #16384 1629 0036 17D2 bcs .L101 3064:Src/main.c **** word = (uint16_t)(sample_u14 << 2); 1630 .loc 1 3064 3 is_stmt 1 view .LVU532 1631 .LVL150: 3065:Src/main.c **** AD9102_WriteReg((uint16_t)(AD9102_REG_SRAM_DATA_BASE + ad9102_wave_written_samples + i), word); 1632 .loc 1 3065 3 view .LVU533 3066:Src/main.c **** } 1633 .loc 1 3066 3 view .LVU534 3066:Src/main.c **** } 1634 .loc 1 3066 86 is_stmt 0 view .LVU535 1635 0038 0D4A ldr r2, .L104+4 1636 003a 1088 ldrh r0, [r2] 1637 003c 2044 add r0, r0, r4 1638 003e 80B2 uxth r0, r0 3066:Src/main.c **** } 1639 .loc 1 3066 3 view .LVU536 ARM GAS /tmp/ccLSPxIe.s page 166 1640 0040 9900 lsls r1, r3, #2 1641 0042 89B2 uxth r1, r1 1642 0044 00F5C040 add r0, r0, #24576 1643 0048 80B2 uxth r0, r0 1644 004a FFF7FEFF bl AD9102_WriteReg 1645 .LVL151: 3066:Src/main.c **** } 1646 .loc 1 3066 3 view .LVU537 1647 .LBE403: 3053:Src/main.c **** { 1648 .loc 1 3053 41 is_stmt 1 discriminator 2 view .LVU538 1649 004e 0134 adds r4, r4, #1 1650 .LVL152: 3053:Src/main.c **** { 1651 .loc 1 3053 41 is_stmt 0 discriminator 2 view .LVU539 1652 0050 A4B2 uxth r4, r4 1653 .LVL153: 3053:Src/main.c **** { 1654 .loc 1 3053 41 discriminator 2 view .LVU540 1655 0052 E7E7 b .L97 1656 .LVL154: 1657 .L103: 3053:Src/main.c **** { 1658 .loc 1 3053 41 discriminator 2 view .LVU541 1659 .LBE402: 3069:Src/main.c **** return 1u; 1660 .loc 1 3069 2 is_stmt 1 view .LVU542 3069:Src/main.c **** return 1u; 1661 .loc 1 3069 32 is_stmt 0 view .LVU543 1662 0054 064B ldr r3, .L104+4 1663 0056 1A88 ldrh r2, [r3] 1664 0058 1544 add r5, r5, r2 1665 .LVL155: 3069:Src/main.c **** return 1u; 1666 .loc 1 3069 30 view .LVU544 1667 005a 1D80 strh r5, [r3] @ movhi 3070:Src/main.c **** } 1668 .loc 1 3070 2 is_stmt 1 view .LVU545 3070:Src/main.c **** } 1669 .loc 1 3070 9 is_stmt 0 view .LVU546 1670 005c 0120 movs r0, #1 1671 005e 00E0 b .L96 1672 .LVL156: 1673 .L99: 3046:Src/main.c **** } 1674 .loc 1 3046 10 view .LVU547 1675 0060 0020 movs r0, #0 1676 .LVL157: 1677 .L96: 3071:Src/main.c **** 1678 .loc 1 3071 1 view .LVU548 1679 0062 70BD pop {r4, r5, r6, pc} 1680 .LVL158: 1681 .L100: 3050:Src/main.c **** } 1682 .loc 1 3050 10 view .LVU549 1683 0064 0020 movs r0, #0 ARM GAS /tmp/ccLSPxIe.s page 167 1684 0066 FCE7 b .L96 1685 .LVL159: 1686 .L101: 1687 .LBB405: 1688 .LBB404: 3061:Src/main.c **** } 1689 .loc 1 3061 11 view .LVU550 1690 0068 0020 movs r0, #0 1691 006a FAE7 b .L96 1692 .L105: 1693 .align 2 1694 .L104: 1695 006c 00000000 .word ad9102_wave_upload_active 1696 0070 00000000 .word ad9102_wave_written_samples 1697 0074 00000000 .word ad9102_wave_expected_samples 1698 .LBE404: 1699 .LBE405: 1700 .cfi_endproc 1701 .LFE1227: 1703 .section .text.AD9102_Init,"ax",%progbits 1704 .align 1 1705 .syntax unified 1706 .thumb 1707 .thumb_func 1709 AD9102_Init: 1710 .LFB1212: 2740:Src/main.c **** HAL_GPIO_WritePin(AD9102_CS_GPIO_Port, AD9102_CS_Pin, GPIO_PIN_SET); 1711 .loc 1 2740 1 is_stmt 1 view -0 1712 .cfi_startproc 1713 @ args = 0, pretend = 0, frame = 8 1714 @ frame_needed = 0, uses_anonymous_args = 0 1715 0000 00B5 push {lr} 1716 .LCFI13: 1717 .cfi_def_cfa_offset 4 1718 .cfi_offset 14, -4 1719 0002 83B0 sub sp, sp, #12 1720 .LCFI14: 1721 .cfi_def_cfa_offset 16 2741:Src/main.c **** HAL_GPIO_WritePin(AD9102_RESET_GPIO_Port, AD9102_RESET_Pin, GPIO_PIN_RESET); 1722 .loc 1 2741 2 view .LVU552 1723 0004 0122 movs r2, #1 1724 0006 4FF48051 mov r1, #4096 1725 000a 1648 ldr r0, .L110 1726 000c FFF7FEFF bl HAL_GPIO_WritePin 1727 .LVL160: 2742:Src/main.c **** for (volatile uint32_t d = 0; d < 1000; d++) {} 1728 .loc 1 2742 2 view .LVU553 1729 0010 0022 movs r2, #0 1730 0012 4021 movs r1, #64 1731 0014 1448 ldr r0, .L110+4 1732 0016 FFF7FEFF bl HAL_GPIO_WritePin 1733 .LVL161: 2743:Src/main.c **** HAL_GPIO_WritePin(AD9102_RESET_GPIO_Port, AD9102_RESET_Pin, GPIO_PIN_SET); 1734 .loc 1 2743 2 view .LVU554 1735 .LBB406: 2743:Src/main.c **** HAL_GPIO_WritePin(AD9102_RESET_GPIO_Port, AD9102_RESET_Pin, GPIO_PIN_SET); 1736 .loc 1 2743 7 view .LVU555 ARM GAS /tmp/ccLSPxIe.s page 168 2743:Src/main.c **** HAL_GPIO_WritePin(AD9102_RESET_GPIO_Port, AD9102_RESET_Pin, GPIO_PIN_SET); 1737 .loc 1 2743 25 is_stmt 0 view .LVU556 1738 001a 0023 movs r3, #0 1739 001c 0193 str r3, [sp, #4] 2743:Src/main.c **** HAL_GPIO_WritePin(AD9102_RESET_GPIO_Port, AD9102_RESET_Pin, GPIO_PIN_SET); 1740 .loc 1 2743 2 view .LVU557 1741 001e 02E0 b .L107 1742 .L108: 2743:Src/main.c **** HAL_GPIO_WritePin(AD9102_RESET_GPIO_Port, AD9102_RESET_Pin, GPIO_PIN_SET); 1743 .loc 1 2743 48 is_stmt 1 discriminator 3 view .LVU558 2743:Src/main.c **** HAL_GPIO_WritePin(AD9102_RESET_GPIO_Port, AD9102_RESET_Pin, GPIO_PIN_SET); 1744 .loc 1 2743 43 discriminator 3 view .LVU559 1745 0020 019B ldr r3, [sp, #4] 1746 0022 0133 adds r3, r3, #1 1747 0024 0193 str r3, [sp, #4] 1748 .L107: 2743:Src/main.c **** HAL_GPIO_WritePin(AD9102_RESET_GPIO_Port, AD9102_RESET_Pin, GPIO_PIN_SET); 1749 .loc 1 2743 34 discriminator 1 view .LVU560 1750 0026 019B ldr r3, [sp, #4] 1751 0028 B3F57A7F cmp r3, #1000 1752 002c F8D3 bcc .L108 1753 .LBE406: 2744:Src/main.c **** 1754 .loc 1 2744 2 view .LVU561 1755 002e 0122 movs r2, #1 1756 0030 4021 movs r1, #64 1757 0032 0D48 ldr r0, .L110+4 1758 0034 FFF7FEFF bl HAL_GPIO_WritePin 1759 .LVL162: 2746:Src/main.c **** AD9102_WriteReg(AD9102_REG_PAT_STATUS, 0x0000u); 1760 .loc 1 2746 2 view .LVU562 1761 0038 4221 movs r1, #66 1762 003a 0C48 ldr r0, .L110+8 1763 003c FFF7FEFF bl AD9102_WriteRegTable 1764 .LVL163: 2747:Src/main.c **** AD9102_WriteReg(AD9102_REG_RAMUPDATE, 0x0001u); 1765 .loc 1 2747 2 view .LVU563 1766 0040 0021 movs r1, #0 1767 0042 1E20 movs r0, #30 1768 0044 FFF7FEFF bl AD9102_WriteReg 1769 .LVL164: 2748:Src/main.c **** HAL_GPIO_WritePin(AD9102_TRIG_GPIO_Port, AD9102_TRIG_Pin, GPIO_PIN_SET); 1770 .loc 1 2748 2 view .LVU564 1771 0048 0121 movs r1, #1 1772 004a 1D20 movs r0, #29 1773 004c FFF7FEFF bl AD9102_WriteReg 1774 .LVL165: 2749:Src/main.c **** } 1775 .loc 1 2749 2 view .LVU565 1776 0050 0122 movs r2, #1 1777 0052 4FF40061 mov r1, #2048 1778 0056 0648 ldr r0, .L110+12 1779 0058 FFF7FEFF bl HAL_GPIO_WritePin 1780 .LVL166: 2750:Src/main.c **** 1781 .loc 1 2750 1 is_stmt 0 view .LVU566 1782 005c 03B0 add sp, sp, #12 ARM GAS /tmp/ccLSPxIe.s page 169 1783 .LCFI15: 1784 .cfi_def_cfa_offset 4 1785 @ sp needed 1786 005e 5DF804FB ldr pc, [sp], #4 1787 .L111: 1788 0062 00BF .align 2 1789 .L110: 1790 0064 00040240 .word 1073873920 1791 0068 00080240 .word 1073874944 1792 006c 00000000 .word ad9102_example4_regval 1793 0070 000C0240 .word 1073875968 1794 .cfi_endproc 1795 .LFE1212: 1797 .section .text.AD9102_StartOutput,"ax",%progbits 1798 .align 1 1799 .syntax unified 1800 .thumb 1801 .thumb_func 1803 AD9102_StartOutput: 1804 .LFB1224: 2963:Src/main.c **** HAL_GPIO_WritePin(AD9102_TRIG_GPIO_Port, AD9102_TRIG_Pin, GPIO_PIN_SET); 1805 .loc 1 2963 1 is_stmt 1 view -0 1806 .cfi_startproc 1807 @ args = 0, pretend = 0, frame = 8 1808 @ frame_needed = 0, uses_anonymous_args = 0 1809 0000 00B5 push {lr} 1810 .LCFI16: 1811 .cfi_def_cfa_offset 4 1812 .cfi_offset 14, -4 1813 0002 83B0 sub sp, sp, #12 1814 .LCFI17: 1815 .cfi_def_cfa_offset 16 2964:Src/main.c **** AD9102_WriteReg(AD9102_REG_PAT_STATUS, AD9102_PAT_STATUS_RUN); 1816 .loc 1 2964 2 view .LVU568 1817 0004 0122 movs r2, #1 1818 0006 4FF40061 mov r1, #2048 1819 000a 0F48 ldr r0, .L116 1820 000c FFF7FEFF bl HAL_GPIO_WritePin 1821 .LVL167: 2965:Src/main.c **** AD9102_WriteReg(AD9102_REG_RAMUPDATE, 0x0001u); 1822 .loc 1 2965 2 view .LVU569 1823 0010 0121 movs r1, #1 1824 0012 1E20 movs r0, #30 1825 0014 FFF7FEFF bl AD9102_WriteReg 1826 .LVL168: 2966:Src/main.c **** for (volatile uint32_t d = 0; d < 1000; d++) {} 1827 .loc 1 2966 2 view .LVU570 1828 0018 0121 movs r1, #1 1829 001a 1D20 movs r0, #29 1830 001c FFF7FEFF bl AD9102_WriteReg 1831 .LVL169: 2967:Src/main.c **** HAL_GPIO_WritePin(AD9102_TRIG_GPIO_Port, AD9102_TRIG_Pin, GPIO_PIN_RESET); 1832 .loc 1 2967 2 view .LVU571 1833 .LBB407: 2967:Src/main.c **** HAL_GPIO_WritePin(AD9102_TRIG_GPIO_Port, AD9102_TRIG_Pin, GPIO_PIN_RESET); 1834 .loc 1 2967 7 view .LVU572 2967:Src/main.c **** HAL_GPIO_WritePin(AD9102_TRIG_GPIO_Port, AD9102_TRIG_Pin, GPIO_PIN_RESET); ARM GAS /tmp/ccLSPxIe.s page 170 1835 .loc 1 2967 25 is_stmt 0 view .LVU573 1836 0020 0023 movs r3, #0 1837 0022 0193 str r3, [sp, #4] 2967:Src/main.c **** HAL_GPIO_WritePin(AD9102_TRIG_GPIO_Port, AD9102_TRIG_Pin, GPIO_PIN_RESET); 1838 .loc 1 2967 2 view .LVU574 1839 0024 02E0 b .L113 1840 .L114: 2967:Src/main.c **** HAL_GPIO_WritePin(AD9102_TRIG_GPIO_Port, AD9102_TRIG_Pin, GPIO_PIN_RESET); 1841 .loc 1 2967 48 is_stmt 1 discriminator 3 view .LVU575 2967:Src/main.c **** HAL_GPIO_WritePin(AD9102_TRIG_GPIO_Port, AD9102_TRIG_Pin, GPIO_PIN_RESET); 1842 .loc 1 2967 43 discriminator 3 view .LVU576 1843 0026 019B ldr r3, [sp, #4] 1844 0028 0133 adds r3, r3, #1 1845 002a 0193 str r3, [sp, #4] 1846 .L113: 2967:Src/main.c **** HAL_GPIO_WritePin(AD9102_TRIG_GPIO_Port, AD9102_TRIG_Pin, GPIO_PIN_RESET); 1847 .loc 1 2967 34 discriminator 1 view .LVU577 1848 002c 019B ldr r3, [sp, #4] 1849 002e B3F57A7F cmp r3, #1000 1850 0032 F8D3 bcc .L114 1851 .LBE407: 2968:Src/main.c **** } 1852 .loc 1 2968 2 view .LVU578 1853 0034 0022 movs r2, #0 1854 0036 4FF40061 mov r1, #2048 1855 003a 0348 ldr r0, .L116 1856 003c FFF7FEFF bl HAL_GPIO_WritePin 1857 .LVL170: 2969:Src/main.c **** 1858 .loc 1 2969 1 is_stmt 0 view .LVU579 1859 0040 03B0 add sp, sp, #12 1860 .LCFI18: 1861 .cfi_def_cfa_offset 4 1862 @ sp needed 1863 0042 5DF804FB ldr pc, [sp], #4 1864 .L117: 1865 0046 00BF .align 2 1866 .L116: 1867 0048 000C0240 .word 1073875968 1868 .cfi_endproc 1869 .LFE1224: 1871 .section .text.AD9102_StopOutput,"ax",%progbits 1872 .align 1 1873 .syntax unified 1874 .thumb 1875 .thumb_func 1877 AD9102_StopOutput: 1878 .LFB1223: 2957:Src/main.c **** AD9102_WriteReg(AD9102_REG_PAT_STATUS, 0x0000u); 1879 .loc 1 2957 1 is_stmt 1 view -0 1880 .cfi_startproc 1881 @ args = 0, pretend = 0, frame = 0 1882 @ frame_needed = 0, uses_anonymous_args = 0 1883 0000 08B5 push {r3, lr} 1884 .LCFI19: 1885 .cfi_def_cfa_offset 8 1886 .cfi_offset 3, -8 ARM GAS /tmp/ccLSPxIe.s page 171 1887 .cfi_offset 14, -4 2958:Src/main.c **** HAL_GPIO_WritePin(AD9102_TRIG_GPIO_Port, AD9102_TRIG_Pin, GPIO_PIN_SET); 1888 .loc 1 2958 2 view .LVU581 1889 0002 0021 movs r1, #0 1890 0004 1E20 movs r0, #30 1891 0006 FFF7FEFF bl AD9102_WriteReg 1892 .LVL171: 2959:Src/main.c **** } 1893 .loc 1 2959 2 view .LVU582 1894 000a 0122 movs r2, #1 1895 000c 4FF40061 mov r1, #2048 1896 0010 0148 ldr r0, .L120 1897 0012 FFF7FEFF bl HAL_GPIO_WritePin 1898 .LVL172: 2960:Src/main.c **** 1899 .loc 1 2960 1 is_stmt 0 view .LVU583 1900 0016 08BD pop {r3, pc} 1901 .L121: 1902 .align 2 1903 .L120: 1904 0018 000C0240 .word 1073875968 1905 .cfi_endproc 1906 .LFE1223: 1908 .section .text.AD9102_ConfigureSramPlayback,"ax",%progbits 1909 .align 1 1910 .syntax unified 1911 .thumb 1912 .thumb_func 1914 AD9102_ConfigureSramPlayback: 1915 .LVL173: 1916 .LFB1225: 2972:Src/main.c **** uint16_t pat_timebase; 1917 .loc 1 2972 1 is_stmt 1 view -0 1918 .cfi_startproc 1919 @ args = 0, pretend = 0, frame = 0 1920 @ frame_needed = 0, uses_anonymous_args = 0 2972:Src/main.c **** uint16_t pat_timebase; 1921 .loc 1 2972 1 is_stmt 0 view .LVU585 1922 0000 70B5 push {r4, r5, r6, lr} 1923 .LCFI20: 1924 .cfi_def_cfa_offset 16 1925 .cfi_offset 4, -16 1926 .cfi_offset 5, -12 1927 .cfi_offset 6, -8 1928 .cfi_offset 14, -4 2973:Src/main.c **** uint32_t pat_period; 1929 .loc 1 2973 2 is_stmt 1 view .LVU586 2974:Src/main.c **** 1930 .loc 1 2974 2 view .LVU587 2976:Src/main.c **** { 1931 .loc 1 2976 2 view .LVU588 2976:Src/main.c **** { 1932 .loc 1 2976 5 is_stmt 0 view .LVU589 1933 0002 0128 cmp r0, #1 1934 0004 06D9 bls .L126 1935 0006 0446 mov r4, r0 2980:Src/main.c **** { ARM GAS /tmp/ccLSPxIe.s page 172 1936 .loc 1 2980 2 is_stmt 1 view .LVU590 2980:Src/main.c **** { 1937 .loc 1 2980 5 is_stmt 0 view .LVU591 1938 0008 B0F5805F cmp r0, #4096 1939 000c 03D9 bls .L123 2982:Src/main.c **** } 1940 .loc 1 2982 11 view .LVU592 1941 000e 4FF48054 mov r4, #4096 1942 0012 00E0 b .L123 1943 .L126: 2978:Src/main.c **** } 1944 .loc 1 2978 11 view .LVU593 1945 0014 0224 movs r4, #2 1946 .L123: 1947 .LVL174: 2984:Src/main.c **** { 1948 .loc 1 2984 2 is_stmt 1 view .LVU594 2984:Src/main.c **** { 1949 .loc 1 2984 5 is_stmt 0 view .LVU595 1950 0016 19B1 cbz r1, .L128 2988:Src/main.c **** { 1951 .loc 1 2988 2 is_stmt 1 view .LVU596 2988:Src/main.c **** { 1952 .loc 1 2988 5 is_stmt 0 view .LVU597 1953 0018 0F29 cmp r1, #15 1954 001a 02D9 bls .L124 2990:Src/main.c **** } 1955 .loc 1 2990 8 view .LVU598 1956 001c 0F21 movs r1, #15 1957 .LVL175: 2990:Src/main.c **** } 1958 .loc 1 2990 8 view .LVU599 1959 001e 00E0 b .L124 1960 .LVL176: 1961 .L128: 2986:Src/main.c **** } 1962 .loc 1 2986 8 view .LVU600 1963 0020 0121 movs r1, #1 1964 .LVL177: 1965 .L124: 2993:Src/main.c **** ((AD9102_SRAM_PAT_PERIOD_BASE_DEFAULT & 0x0Fu) << 4) | 1966 .loc 1 2993 2 is_stmt 1 view .LVU601 2993:Src/main.c **** ((AD9102_SRAM_PAT_PERIOD_BASE_DEFAULT & 0x0Fu) << 4) | 1967 .loc 1 2993 54 is_stmt 0 view .LVU602 1968 0022 0D02 lsls r5, r1, #8 1969 0024 05F47065 and r5, r5, #3840 2993:Src/main.c **** ((AD9102_SRAM_PAT_PERIOD_BASE_DEFAULT & 0x0Fu) << 4) | 1970 .loc 1 2993 15 view .LVU603 1971 0028 45F01105 orr r5, r5, #17 1972 .LVL178: 2996:Src/main.c **** if (pat_period == 0u) 1973 .loc 1 2996 2 is_stmt 1 view .LVU604 2996:Src/main.c **** if (pat_period == 0u) 1974 .loc 1 2996 15 is_stmt 0 view .LVU605 1975 002c 2646 mov r6, r4 2996:Src/main.c **** if (pat_period == 0u) 1976 .loc 1 2996 35 view .LVU606 ARM GAS /tmp/ccLSPxIe.s page 173 1977 002e 01F00F01 and r1, r1, #15 1978 .LVL179: 2996:Src/main.c **** if (pat_period == 0u) 1979 .loc 1 2996 13 view .LVU607 1980 0032 04FB01F1 mul r1, r4, r1 1981 .LVL180: 2997:Src/main.c **** { 1982 .loc 1 2997 2 is_stmt 1 view .LVU608 2997:Src/main.c **** { 1983 .loc 1 2997 5 is_stmt 0 view .LVU609 1984 0036 19B1 cbz r1, .L125 3001:Src/main.c **** { 1985 .loc 1 3001 2 is_stmt 1 view .LVU610 3001:Src/main.c **** { 1986 .loc 1 3001 5 is_stmt 0 view .LVU611 1987 0038 B1F5803F cmp r1, #65536 1988 003c 35D2 bcs .L130 1989 003e 0E46 mov r6, r1 1990 .L125: 1991 .LVL181: 3006:Src/main.c **** AD9102_StopOutput(); 1992 .loc 1 3006 2 is_stmt 1 view .LVU612 1993 0040 4221 movs r1, #66 1994 0042 1B48 ldr r0, .L132 1995 0044 FFF7FEFF bl AD9102_WriteRegTable 1996 .LVL182: 3007:Src/main.c **** AD9102_WriteReg(AD9102_REG_WAV_CONFIG, AD9102_EX2_WAV_CONFIG); 1997 .loc 1 3007 2 view .LVU613 1998 0048 FFF7FEFF bl AD9102_StopOutput 1999 .LVL183: 3008:Src/main.c **** AD9102_WriteReg(AD9102_REG_SAW_CONFIG, AD9102_EX2_SAW_CONFIG); 2000 .loc 1 3008 2 view .LVU614 2001 004c 43F23001 movw r1, #12336 2002 0050 2720 movs r0, #39 2003 0052 FFF7FEFF bl AD9102_WriteReg 2004 .LVL184: 3009:Src/main.c **** AD9102_WriteReg(AD9102_REG_DAC_PAT, AD9102_EX2_DAC_PAT); 2005 .loc 1 3009 2 view .LVU615 2006 0056 4FF40071 mov r1, #512 2007 005a 3720 movs r0, #55 2008 005c FFF7FEFF bl AD9102_WriteReg 2009 .LVL185: 3010:Src/main.c **** AD9102_WriteReg(AD9102_REG_PAT_TIMEBASE, pat_timebase); 2010 .loc 1 3010 2 view .LVU616 2011 0060 40F20111 movw r1, #257 2012 0064 2B20 movs r0, #43 2013 0066 FFF7FEFF bl AD9102_WriteReg 2014 .LVL186: 3011:Src/main.c **** AD9102_WriteReg(AD9102_REG_PAT_PERIOD, (uint16_t)pat_period); 2015 .loc 1 3011 2 view .LVU617 2016 006a 2946 mov r1, r5 2017 006c 2820 movs r0, #40 2018 006e FFF7FEFF bl AD9102_WriteReg 2019 .LVL187: 3012:Src/main.c **** AD9102_WriteReg(AD9102_REG_PAT_TYPE, 0x0000u); // continuous pattern repeat 2020 .loc 1 3012 2 view .LVU618 2021 0072 B1B2 uxth r1, r6 ARM GAS /tmp/ccLSPxIe.s page 174 2022 0074 2920 movs r0, #41 2023 0076 FFF7FEFF bl AD9102_WriteReg 2024 .LVL188: 3013:Src/main.c **** AD9102_WriteReg(AD9102_REG_START_DLY, AD9102_SRAM_START_DLY_DEFAULT); 2025 .loc 1 3013 2 view .LVU619 2026 007a 0021 movs r1, #0 2027 007c 1F20 movs r0, #31 2028 007e FFF7FEFF bl AD9102_WriteReg 2029 .LVL189: 3014:Src/main.c **** AD9102_WriteReg(AD9102_REG_START_ADDR, 0x0000u); 2030 .loc 1 3014 2 view .LVU620 2031 0082 0021 movs r1, #0 2032 0084 5C20 movs r0, #92 2033 0086 FFF7FEFF bl AD9102_WriteReg 2034 .LVL190: 3015:Src/main.c **** AD9102_WriteReg(AD9102_REG_STOP_ADDR, (uint16_t)((samples - 1u) << 4)); 2035 .loc 1 3015 2 view .LVU621 2036 008a 0021 movs r1, #0 2037 008c 5D20 movs r0, #93 2038 008e FFF7FEFF bl AD9102_WriteReg 2039 .LVL191: 3016:Src/main.c **** AD9102_WriteReg(AD9102_REG_RAMUPDATE, 0x0001u); 2040 .loc 1 3016 2 view .LVU622 3016:Src/main.c **** AD9102_WriteReg(AD9102_REG_RAMUPDATE, 0x0001u); 2041 .loc 1 3016 60 is_stmt 0 view .LVU623 2042 0092 611E subs r1, r4, #1 2043 0094 89B2 uxth r1, r1 3016:Src/main.c **** AD9102_WriteReg(AD9102_REG_RAMUPDATE, 0x0001u); 2044 .loc 1 3016 2 view .LVU624 2045 0096 0901 lsls r1, r1, #4 2046 0098 89B2 uxth r1, r1 2047 009a 5E20 movs r0, #94 2048 009c FFF7FEFF bl AD9102_WriteReg 2049 .LVL192: 3017:Src/main.c **** } 2050 .loc 1 3017 2 is_stmt 1 view .LVU625 2051 00a0 0121 movs r1, #1 2052 00a2 1D20 movs r0, #29 2053 00a4 FFF7FEFF bl AD9102_WriteReg 2054 .LVL193: 3018:Src/main.c **** 2055 .loc 1 3018 1 is_stmt 0 view .LVU626 2056 00a8 70BD pop {r4, r5, r6, pc} 2057 .LVL194: 2058 .L130: 3003:Src/main.c **** } 2059 .loc 1 3003 14 view .LVU627 2060 00aa 4FF6FF76 movw r6, #65535 2061 00ae C7E7 b .L125 2062 .L133: 2063 .align 2 2064 .L132: 2065 00b0 00000000 .word ad9102_example2_regval 2066 .cfi_endproc 2067 .LFE1225: 2069 .section .text.AD9102_BeginWaveUpload,"ax",%progbits 2070 .align 1 ARM GAS /tmp/ccLSPxIe.s page 175 2071 .syntax unified 2072 .thumb 2073 .thumb_func 2075 AD9102_BeginWaveUpload: 2076 .LVL195: 2077 .LFB1226: 3021:Src/main.c **** if ((samples < 2u) || (samples > AD9102_SRAM_MAX_SAMPLES)) 2078 .loc 1 3021 1 is_stmt 1 view -0 2079 .cfi_startproc 2080 @ args = 0, pretend = 0, frame = 0 2081 @ frame_needed = 0, uses_anonymous_args = 0 3022:Src/main.c **** { 2082 .loc 1 3022 2 view .LVU629 3022:Src/main.c **** { 2083 .loc 1 3022 21 is_stmt 0 view .LVU630 2084 0000 831E subs r3, r0, #2 2085 0002 9BB2 uxth r3, r3 3022:Src/main.c **** { 2086 .loc 1 3022 5 view .LVU631 2087 0004 40F6FE72 movw r2, #4094 2088 0008 9342 cmp r3, r2 2089 000a 01D9 bls .L141 3024:Src/main.c **** } 2090 .loc 1 3024 10 view .LVU632 2091 000c 0020 movs r0, #0 2092 .LVL196: 3036:Src/main.c **** 2093 .loc 1 3036 1 view .LVU633 2094 000e 7047 bx lr 2095 .LVL197: 2096 .L141: 3021:Src/main.c **** if ((samples < 2u) || (samples > AD9102_SRAM_MAX_SAMPLES)) 2097 .loc 1 3021 1 view .LVU634 2098 0010 10B5 push {r4, lr} 2099 .LCFI21: 2100 .cfi_def_cfa_offset 8 2101 .cfi_offset 4, -8 2102 .cfi_offset 14, -4 2103 0012 0446 mov r4, r0 3027:Src/main.c **** AD9102_ResetWaveUploadState(); 2104 .loc 1 3027 2 is_stmt 1 view .LVU635 2105 0014 FFF7FEFF bl AD9102_StopOutput 2106 .LVL198: 3028:Src/main.c **** AD9102_ConfigureSramPlayback(samples, AD9102_SRAM_HOLD_DEFAULT); 2107 .loc 1 3028 2 view .LVU636 2108 0018 FFF7FEFF bl AD9102_ResetWaveUploadState 2109 .LVL199: 3029:Src/main.c **** AD9102_WriteReg(AD9102_REG_PAT_STATUS, 0x0004u); // enable SRAM access 2110 .loc 1 3029 2 view .LVU637 2111 001c 0121 movs r1, #1 2112 001e 2046 mov r0, r4 2113 0020 FFF7FEFF bl AD9102_ConfigureSramPlayback 2114 .LVL200: 3030:Src/main.c **** 2115 .loc 1 3030 2 view .LVU638 2116 0024 0421 movs r1, #4 2117 0026 1E20 movs r0, #30 ARM GAS /tmp/ccLSPxIe.s page 176 2118 0028 FFF7FEFF bl AD9102_WriteReg 2119 .LVL201: 3032:Src/main.c **** ad9102_wave_written_samples = 0u; 2120 .loc 1 3032 2 view .LVU639 3032:Src/main.c **** ad9102_wave_written_samples = 0u; 2121 .loc 1 3032 31 is_stmt 0 view .LVU640 2122 002c 044B ldr r3, .L142 2123 002e 1C80 strh r4, [r3] @ movhi 3033:Src/main.c **** ad9102_wave_upload_active = 1u; 2124 .loc 1 3033 2 is_stmt 1 view .LVU641 3033:Src/main.c **** ad9102_wave_upload_active = 1u; 2125 .loc 1 3033 30 is_stmt 0 view .LVU642 2126 0030 044B ldr r3, .L142+4 2127 0032 0022 movs r2, #0 2128 0034 1A80 strh r2, [r3] @ movhi 3034:Src/main.c **** return 1u; 2129 .loc 1 3034 2 is_stmt 1 view .LVU643 3034:Src/main.c **** return 1u; 2130 .loc 1 3034 28 is_stmt 0 view .LVU644 2131 0036 0120 movs r0, #1 2132 0038 034B ldr r3, .L142+8 2133 003a 1870 strb r0, [r3] 3035:Src/main.c **** } 2134 .loc 1 3035 2 is_stmt 1 view .LVU645 3036:Src/main.c **** 2135 .loc 1 3036 1 is_stmt 0 view .LVU646 2136 003c 10BD pop {r4, pc} 2137 .L143: 2138 003e 00BF .align 2 2139 .L142: 2140 0040 00000000 .word ad9102_wave_expected_samples 2141 0044 00000000 .word ad9102_wave_written_samples 2142 0048 00000000 .word ad9102_wave_upload_active 2143 .cfi_endproc 2144 .LFE1226: 2146 .section .text.AD9102_CancelWaveUpload,"ax",%progbits 2147 .align 1 2148 .syntax unified 2149 .thumb 2150 .thumb_func 2152 AD9102_CancelWaveUpload: 2153 .LFB1229: 3107:Src/main.c **** if (ad9102_wave_upload_active != 0u) 2154 .loc 1 3107 1 is_stmt 1 view -0 2155 .cfi_startproc 2156 @ args = 0, pretend = 0, frame = 0 2157 @ frame_needed = 0, uses_anonymous_args = 0 2158 0000 08B5 push {r3, lr} 2159 .LCFI22: 2160 .cfi_def_cfa_offset 8 2161 .cfi_offset 3, -8 2162 .cfi_offset 14, -4 3108:Src/main.c **** { 2163 .loc 1 3108 2 view .LVU648 3108:Src/main.c **** { 2164 .loc 1 3108 32 is_stmt 0 view .LVU649 2165 0002 044B ldr r3, .L148 ARM GAS /tmp/ccLSPxIe.s page 177 2166 0004 1B78 ldrb r3, [r3] @ zero_extendqisi2 3108:Src/main.c **** { 2167 .loc 1 3108 5 view .LVU650 2168 0006 13B9 cbnz r3, .L147 2169 .L145: 3112:Src/main.c **** } 2170 .loc 1 3112 2 is_stmt 1 view .LVU651 2171 0008 FFF7FEFF bl AD9102_ResetWaveUploadState 2172 .LVL202: 3113:Src/main.c **** 2173 .loc 1 3113 1 is_stmt 0 view .LVU652 2174 000c 08BD pop {r3, pc} 2175 .L147: 3110:Src/main.c **** } 2176 .loc 1 3110 3 is_stmt 1 view .LVU653 2177 000e FFF7FEFF bl AD9102_StopOutput 2178 .LVL203: 2179 0012 F9E7 b .L145 2180 .L149: 2181 .align 2 2182 .L148: 2183 0014 00000000 .word ad9102_wave_upload_active 2184 .cfi_endproc 2185 .LFE1229: 2187 .section .text.AD9102_ReadReg,"ax",%progbits 2188 .align 1 2189 .syntax unified 2190 .thumb 2191 .thumb_func 2193 AD9102_ReadReg: 2194 .LVL204: 2195 .LFB1220: 2907:Src/main.c **** uint32_t tmp32 = 0; 2196 .loc 1 2907 1 view -0 2197 .cfi_startproc 2198 @ args = 0, pretend = 0, frame = 0 2199 @ frame_needed = 0, uses_anonymous_args = 0 2907:Src/main.c **** uint32_t tmp32 = 0; 2200 .loc 1 2907 1 is_stmt 0 view .LVU655 2201 0000 10B5 push {r4, lr} 2202 .LCFI23: 2203 .cfi_def_cfa_offset 8 2204 .cfi_offset 4, -8 2205 .cfi_offset 14, -4 2908:Src/main.c **** uint16_t cmd = (uint16_t)(0x8000u | (addr & 0x7FFFu)); // R/W = 1 (read) 2206 .loc 1 2908 2 is_stmt 1 view .LVU656 2207 .LVL205: 2909:Src/main.c **** uint16_t value; 2208 .loc 1 2909 2 view .LVU657 2909:Src/main.c **** uint16_t value; 2209 .loc 1 2909 11 is_stmt 0 view .LVU658 2210 0002 40F40044 orr r4, r0, #32768 2211 .LVL206: 2910:Src/main.c **** 2212 .loc 1 2910 2 is_stmt 1 view .LVU659 2912:Src/main.c **** 2213 .loc 1 2912 2 view .LVU660 ARM GAS /tmp/ccLSPxIe.s page 178 2214 0006 0021 movs r1, #0 2215 0008 0846 mov r0, r1 2216 .LVL207: 2912:Src/main.c **** 2217 .loc 1 2912 2 is_stmt 0 view .LVU661 2218 000a FFF7FEFF bl SPI2_SetMode 2219 .LVL208: 2914:Src/main.c **** HAL_GPIO_WritePin(DAC_TEC1_CS_GPIO_Port, DAC_TEC1_CS_Pin, GPIO_PIN_SET); 2220 .loc 1 2914 2 is_stmt 1 view .LVU662 2221 000e 0122 movs r2, #1 2222 0010 4FF48041 mov r1, #16384 2223 0014 2C48 ldr r0, .L165 2224 0016 FFF7FEFF bl HAL_GPIO_WritePin 2225 .LVL209: 2915:Src/main.c **** 2226 .loc 1 2915 2 view .LVU663 2227 001a 0122 movs r2, #1 2228 001c 4FF48051 mov r1, #4096 2229 0020 2A48 ldr r0, .L165+4 2230 0022 FFF7FEFF bl HAL_GPIO_WritePin 2231 .LVL210: 2917:Src/main.c **** { 2232 .loc 1 2917 2 view .LVU664 2233 .LBB408: 2234 .LBI408: 381:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 2235 .loc 4 381 26 view .LVU665 2236 .LBB409: 383:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 2237 .loc 4 383 3 view .LVU666 383:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 2238 .loc 4 383 12 is_stmt 0 view .LVU667 2239 0026 2A4B ldr r3, .L165+8 2240 0028 1B68 ldr r3, [r3] 383:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 2241 .loc 4 383 69 view .LVU668 2242 002a 13F0400F tst r3, #64 2243 002e 04D1 bne .L151 2244 .LVL211: 383:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 2245 .loc 4 383 69 view .LVU669 2246 .LBE409: 2247 .LBE408: 2919:Src/main.c **** } 2248 .loc 1 2919 3 is_stmt 1 view .LVU670 2249 .LBB410: 2250 .LBI410: 358:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 2251 .loc 4 358 22 view .LVU671 2252 .LBB411: 360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 2253 .loc 4 360 3 view .LVU672 2254 0030 274A ldr r2, .L165+8 2255 0032 1368 ldr r3, [r2] 2256 0034 43F04003 orr r3, r3, #64 2257 0038 1360 str r3, [r2] 2258 .LVL212: ARM GAS /tmp/ccLSPxIe.s page 179 2259 .L151: 360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 2260 .loc 4 360 3 is_stmt 0 view .LVU673 2261 .LBE411: 2262 .LBE410: 2922:Src/main.c **** 2263 .loc 1 2922 2 is_stmt 1 view .LVU674 2264 003a 0022 movs r2, #0 2265 003c 4FF48051 mov r1, #4096 2266 0040 2148 ldr r0, .L165 2267 0042 FFF7FEFF bl HAL_GPIO_WritePin 2268 .LVL213: 2924:Src/main.c **** LL_SPI_TransmitData16(SPI2, cmd); 2269 .loc 1 2924 2 view .LVU675 2908:Src/main.c **** uint16_t cmd = (uint16_t)(0x8000u | (addr & 0x7FFFu)); // R/W = 1 (read) 2270 .loc 1 2908 11 is_stmt 0 view .LVU676 2271 0046 0023 movs r3, #0 2272 .LVL214: 2273 .L153: 2924:Src/main.c **** LL_SPI_TransmitData16(SPI2, cmd); 2274 .loc 1 2924 63 is_stmt 1 discriminator 2 view .LVU677 2924:Src/main.c **** LL_SPI_TransmitData16(SPI2, cmd); 2275 .loc 1 2924 41 discriminator 2 view .LVU678 2276 .LBB412: 2277 .LBI412: 916:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 2278 .loc 4 916 26 view .LVU679 2279 .LBB413: 918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 2280 .loc 4 918 3 view .LVU680 918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 2281 .loc 4 918 12 is_stmt 0 view .LVU681 2282 0048 214A ldr r2, .L165+8 2283 004a 9268 ldr r2, [r2, #8] 918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 2284 .loc 4 918 66 view .LVU682 2285 004c 12F0020F tst r2, #2 2286 0050 05D1 bne .L152 2287 .LVL215: 918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 2288 .loc 4 918 66 view .LVU683 2289 .LBE413: 2290 .LBE412: 2924:Src/main.c **** LL_SPI_TransmitData16(SPI2, cmd); 2291 .loc 1 2924 50 discriminator 1 view .LVU684 2292 0052 5A1C adds r2, r3, #1 2293 .LVL216: 2924:Src/main.c **** LL_SPI_TransmitData16(SPI2, cmd); 2294 .loc 1 2924 41 discriminator 1 view .LVU685 2295 0054 B3F57A7F cmp r3, #1000 2296 0058 01D2 bcs .L152 2924:Src/main.c **** LL_SPI_TransmitData16(SPI2, cmd); 2297 .loc 1 2924 50 discriminator 1 view .LVU686 2298 005a 1346 mov r3, r2 2299 005c F4E7 b .L153 2300 .LVL217: 2301 .L152: ARM GAS /tmp/ccLSPxIe.s page 180 2925:Src/main.c **** tmp32 = 0; 2302 .loc 1 2925 2 is_stmt 1 view .LVU687 2303 .LBB414: 2304 .LBI414: 1373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 2305 .loc 4 1373 22 view .LVU688 2306 .LBB415: 1376:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** *spidr = TxData; 2307 .loc 4 1376 3 view .LVU689 2308 .loc 4 1377 3 view .LVU690 2309 .loc 4 1377 10 is_stmt 0 view .LVU691 2310 005e 1C4B ldr r3, .L165+8 2311 0060 9C81 strh r4, [r3, #12] @ movhi 2312 .LVL218: 2313 .loc 4 1377 10 view .LVU692 2314 .LBE415: 2315 .LBE414: 2926:Src/main.c **** while((!LL_SPI_IsActiveFlag_RXNE(SPI2)) && (tmp32++ < 1000)) {} 2316 .loc 1 2926 2 is_stmt 1 view .LVU693 2927:Src/main.c **** (void) SPI2->DR; 2317 .loc 1 2927 2 view .LVU694 2926:Src/main.c **** while((!LL_SPI_IsActiveFlag_RXNE(SPI2)) && (tmp32++ < 1000)) {} 2318 .loc 1 2926 8 is_stmt 0 view .LVU695 2319 0062 0023 movs r3, #0 2320 .LVL219: 2321 .L155: 2927:Src/main.c **** (void) SPI2->DR; 2322 .loc 1 2927 64 is_stmt 1 discriminator 2 view .LVU696 2927:Src/main.c **** (void) SPI2->DR; 2323 .loc 1 2927 42 discriminator 2 view .LVU697 2324 .LBB416: 2325 .LBI416: 905:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 2326 .loc 4 905 26 view .LVU698 2327 .LBB417: 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 2328 .loc 4 907 3 view .LVU699 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 2329 .loc 4 907 12 is_stmt 0 view .LVU700 2330 0064 1A4A ldr r2, .L165+8 2331 0066 9268 ldr r2, [r2, #8] 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 2332 .loc 4 907 68 view .LVU701 2333 0068 12F0010F tst r2, #1 2334 006c 05D1 bne .L154 2335 .LVL220: 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 2336 .loc 4 907 68 view .LVU702 2337 .LBE417: 2338 .LBE416: 2927:Src/main.c **** (void) SPI2->DR; 2339 .loc 1 2927 51 discriminator 1 view .LVU703 2340 006e 5A1C adds r2, r3, #1 2341 .LVL221: 2927:Src/main.c **** (void) SPI2->DR; 2342 .loc 1 2927 42 discriminator 1 view .LVU704 2343 0070 B3F57A7F cmp r3, #1000 ARM GAS /tmp/ccLSPxIe.s page 181 2344 0074 01D2 bcs .L154 2927:Src/main.c **** (void) SPI2->DR; 2345 .loc 1 2927 51 discriminator 1 view .LVU705 2346 0076 1346 mov r3, r2 2347 0078 F4E7 b .L155 2348 .LVL222: 2349 .L154: 2928:Src/main.c **** 2350 .loc 1 2928 2 is_stmt 1 view .LVU706 2351 007a 154B ldr r3, .L165+8 2352 007c DB68 ldr r3, [r3, #12] 2930:Src/main.c **** while((!LL_SPI_IsActiveFlag_TXE(SPI2)) && (tmp32++ < 1000)) {} 2353 .loc 1 2930 2 view .LVU707 2354 .LVL223: 2931:Src/main.c **** LL_SPI_TransmitData16(SPI2, 0x0000u); 2355 .loc 1 2931 2 view .LVU708 2930:Src/main.c **** while((!LL_SPI_IsActiveFlag_TXE(SPI2)) && (tmp32++ < 1000)) {} 2356 .loc 1 2930 8 is_stmt 0 view .LVU709 2357 007e 0023 movs r3, #0 2358 .LVL224: 2359 .L157: 2931:Src/main.c **** LL_SPI_TransmitData16(SPI2, 0x0000u); 2360 .loc 1 2931 63 is_stmt 1 discriminator 2 view .LVU710 2931:Src/main.c **** LL_SPI_TransmitData16(SPI2, 0x0000u); 2361 .loc 1 2931 41 discriminator 2 view .LVU711 2362 .LBB418: 2363 .LBI418: 916:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 2364 .loc 4 916 26 view .LVU712 2365 .LBB419: 918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 2366 .loc 4 918 3 view .LVU713 918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 2367 .loc 4 918 12 is_stmt 0 view .LVU714 2368 0080 134A ldr r2, .L165+8 2369 0082 9268 ldr r2, [r2, #8] 918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 2370 .loc 4 918 66 view .LVU715 2371 0084 12F0020F tst r2, #2 2372 0088 05D1 bne .L156 2373 .LVL225: 918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 2374 .loc 4 918 66 view .LVU716 2375 .LBE419: 2376 .LBE418: 2931:Src/main.c **** LL_SPI_TransmitData16(SPI2, 0x0000u); 2377 .loc 1 2931 50 discriminator 1 view .LVU717 2378 008a 5A1C adds r2, r3, #1 2379 .LVL226: 2931:Src/main.c **** LL_SPI_TransmitData16(SPI2, 0x0000u); 2380 .loc 1 2931 41 discriminator 1 view .LVU718 2381 008c B3F57A7F cmp r3, #1000 2382 0090 01D2 bcs .L156 2931:Src/main.c **** LL_SPI_TransmitData16(SPI2, 0x0000u); 2383 .loc 1 2931 50 discriminator 1 view .LVU719 2384 0092 1346 mov r3, r2 2385 0094 F4E7 b .L157 ARM GAS /tmp/ccLSPxIe.s page 182 2386 .LVL227: 2387 .L156: 2932:Src/main.c **** tmp32 = 0; 2388 .loc 1 2932 2 is_stmt 1 view .LVU720 2389 .LBB420: 2390 .LBI420: 1373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 2391 .loc 4 1373 22 view .LVU721 2392 .LBB421: 1376:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** *spidr = TxData; 2393 .loc 4 1376 3 view .LVU722 2394 .loc 4 1377 3 view .LVU723 2395 .loc 4 1377 10 is_stmt 0 view .LVU724 2396 0096 0023 movs r3, #0 2397 0098 0D4A ldr r2, .L165+8 2398 009a 9381 strh r3, [r2, #12] @ movhi 2399 .LVL228: 2400 .loc 4 1377 10 view .LVU725 2401 .LBE421: 2402 .LBE420: 2933:Src/main.c **** while((!LL_SPI_IsActiveFlag_RXNE(SPI2)) && (tmp32++ < 1000)) {} 2403 .loc 1 2933 2 is_stmt 1 view .LVU726 2934:Src/main.c **** value = LL_SPI_ReceiveData16(SPI2); 2404 .loc 1 2934 2 view .LVU727 2405 .L159: 2934:Src/main.c **** value = LL_SPI_ReceiveData16(SPI2); 2406 .loc 1 2934 64 discriminator 2 view .LVU728 2934:Src/main.c **** value = LL_SPI_ReceiveData16(SPI2); 2407 .loc 1 2934 42 discriminator 2 view .LVU729 2408 .LBB422: 2409 .LBI422: 905:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 2410 .loc 4 905 26 view .LVU730 2411 .LBB423: 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 2412 .loc 4 907 3 view .LVU731 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 2413 .loc 4 907 12 is_stmt 0 view .LVU732 2414 009c 0C4A ldr r2, .L165+8 2415 009e 9268 ldr r2, [r2, #8] 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 2416 .loc 4 907 68 view .LVU733 2417 00a0 12F0010F tst r2, #1 2418 00a4 05D1 bne .L158 2419 .LVL229: 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 2420 .loc 4 907 68 view .LVU734 2421 .LBE423: 2422 .LBE422: 2934:Src/main.c **** value = LL_SPI_ReceiveData16(SPI2); 2423 .loc 1 2934 51 discriminator 1 view .LVU735 2424 00a6 5A1C adds r2, r3, #1 2425 .LVL230: 2934:Src/main.c **** value = LL_SPI_ReceiveData16(SPI2); 2426 .loc 1 2934 42 discriminator 1 view .LVU736 2427 00a8 B3F57A7F cmp r3, #1000 2428 00ac 01D2 bcs .L158 ARM GAS /tmp/ccLSPxIe.s page 183 2934:Src/main.c **** value = LL_SPI_ReceiveData16(SPI2); 2429 .loc 1 2934 51 discriminator 1 view .LVU737 2430 00ae 1346 mov r3, r2 2431 00b0 F4E7 b .L159 2432 .LVL231: 2433 .L158: 2935:Src/main.c **** 2434 .loc 1 2935 2 is_stmt 1 view .LVU738 2435 .LBB424: 2436 .LBI424: 1344:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 2437 .loc 4 1344 26 view .LVU739 2438 .LBB425: 1346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 2439 .loc 4 1346 3 view .LVU740 1346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 2440 .loc 4 1346 21 is_stmt 0 view .LVU741 2441 00b2 074B ldr r3, .L165+8 2442 00b4 DC68 ldr r4, [r3, #12] 2443 .LVL232: 1346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 2444 .loc 4 1346 10 view .LVU742 2445 00b6 A4B2 uxth r4, r4 2446 .LVL233: 1346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 2447 .loc 4 1346 10 view .LVU743 2448 .LBE425: 2449 .LBE424: 2937:Src/main.c **** return value; 2450 .loc 1 2937 2 is_stmt 1 view .LVU744 2451 00b8 0122 movs r2, #1 2452 00ba 4FF48051 mov r1, #4096 2453 00be 0248 ldr r0, .L165 2454 00c0 FFF7FEFF bl HAL_GPIO_WritePin 2455 .LVL234: 2938:Src/main.c **** } 2456 .loc 1 2938 2 view .LVU745 2939:Src/main.c **** 2457 .loc 1 2939 1 is_stmt 0 view .LVU746 2458 00c4 2046 mov r0, r4 2459 00c6 10BD pop {r4, pc} 2460 .LVL235: 2461 .L166: 2939:Src/main.c **** 2462 .loc 1 2939 1 view .LVU747 2463 .align 2 2464 .L165: 2465 00c8 00040240 .word 1073873920 2466 00cc 000C0240 .word 1073875968 2467 00d0 00380040 .word 1073756160 2468 .cfi_endproc 2469 .LFE1220: 2471 .section .text.AD9102_ApplySram,"ax",%progbits 2472 .align 1 2473 .syntax unified 2474 .thumb 2475 .thumb_func ARM GAS /tmp/ccLSPxIe.s page 184 2477 AD9102_ApplySram: 2478 .LVL236: 2479 .LFB1232: 3243:Src/main.c **** AD9102_ResetWaveUploadState(); 2480 .loc 1 3243 1 is_stmt 1 view -0 2481 .cfi_startproc 2482 @ args = 4, pretend = 0, frame = 0 2483 @ frame_needed = 0, uses_anonymous_args = 0 3243:Src/main.c **** AD9102_ResetWaveUploadState(); 2484 .loc 1 3243 1 is_stmt 0 view .LVU749 2485 0000 2DE9F041 push {r4, r5, r6, r7, r8, lr} 2486 .LCFI24: 2487 .cfi_def_cfa_offset 24 2488 .cfi_offset 4, -24 2489 .cfi_offset 5, -20 2490 .cfi_offset 6, -16 2491 .cfi_offset 7, -12 2492 .cfi_offset 8, -8 2493 .cfi_offset 14, -4 2494 0004 0646 mov r6, r0 2495 0006 0C46 mov r4, r1 2496 0008 1546 mov r5, r2 2497 000a 1F46 mov r7, r3 2498 000c BDF81880 ldrh r8, [sp, #24] 3244:Src/main.c **** 2499 .loc 1 3244 2 is_stmt 1 view .LVU750 2500 0010 FFF7FEFF bl AD9102_ResetWaveUploadState 2501 .LVL237: 3246:Src/main.c **** { 2502 .loc 1 3246 2 view .LVU751 3246:Src/main.c **** { 2503 .loc 1 3246 5 is_stmt 0 view .LVU752 2504 0014 1CB1 cbz r4, .L174 3250:Src/main.c **** { 2505 .loc 1 3250 2 is_stmt 1 view .LVU753 3250:Src/main.c **** { 2506 .loc 1 3250 5 is_stmt 0 view .LVU754 2507 0016 012C cmp r4, #1 2508 0018 02D8 bhi .L168 3252:Src/main.c **** } 2509 .loc 1 3252 11 view .LVU755 2510 001a 0224 movs r4, #2 2511 .LVL238: 3252:Src/main.c **** } 2512 .loc 1 3252 11 view .LVU756 2513 001c 03E0 b .L169 2514 .LVL239: 2515 .L174: 3248:Src/main.c **** } 2516 .loc 1 3248 11 view .LVU757 2517 001e 1024 movs r4, #16 2518 .LVL240: 2519 .L168: 3254:Src/main.c **** { 2520 .loc 1 3254 2 is_stmt 1 view .LVU758 3254:Src/main.c **** { 2521 .loc 1 3254 5 is_stmt 0 view .LVU759 ARM GAS /tmp/ccLSPxIe.s page 185 2522 0020 B4F5805F cmp r4, #4096 2523 0024 04D8 bhi .L176 2524 .LVL241: 2525 .L169: 3258:Src/main.c **** { 2526 .loc 1 3258 2 is_stmt 1 view .LVU760 3258:Src/main.c **** { 2527 .loc 1 3258 5 is_stmt 0 view .LVU761 2528 0026 35B1 cbz r5, .L177 3262:Src/main.c **** { 2529 .loc 1 3262 2 is_stmt 1 view .LVU762 3262:Src/main.c **** { 2530 .loc 1 3262 5 is_stmt 0 view .LVU763 2531 0028 0F2D cmp r5, #15 2532 002a 05D9 bls .L170 3264:Src/main.c **** } 2533 .loc 1 3264 8 view .LVU764 2534 002c 0F25 movs r5, #15 2535 .LVL242: 3264:Src/main.c **** } 2536 .loc 1 3264 8 view .LVU765 2537 002e 03E0 b .L170 2538 .LVL243: 2539 .L176: 3256:Src/main.c **** } 2540 .loc 1 3256 11 view .LVU766 2541 0030 4FF48054 mov r4, #4096 2542 .LVL244: 3256:Src/main.c **** } 2543 .loc 1 3256 11 view .LVU767 2544 0034 F7E7 b .L169 2545 .LVL245: 2546 .L177: 3260:Src/main.c **** } 2547 .loc 1 3260 8 view .LVU768 2548 0036 0125 movs r5, #1 2549 .LVL246: 2550 .L170: 3267:Src/main.c **** { 2551 .loc 1 3267 2 is_stmt 1 view .LVU769 3267:Src/main.c **** { 2552 .loc 1 3267 5 is_stmt 0 view .LVU770 2553 0038 B8F5005F cmp r8, #8192 2554 003c 01D3 bcc .L171 3269:Src/main.c **** } 2555 .loc 1 3269 13 view .LVU771 2556 003e 41F6FF78 movw r8, #8191 2557 .L171: 2558 .LVL247: 3272:Src/main.c **** AD9102_LoadSramRamp(samples, triangle, amplitude); 2559 .loc 1 3272 2 is_stmt 1 view .LVU772 2560 0042 2946 mov r1, r5 2561 0044 2046 mov r0, r4 2562 0046 FFF7FEFF bl AD9102_ConfigureSramPlayback 2563 .LVL248: 3273:Src/main.c **** 2564 .loc 1 3273 2 view .LVU773 ARM GAS /tmp/ccLSPxIe.s page 186 2565 004a 4246 mov r2, r8 2566 004c 3946 mov r1, r7 2567 004e 2046 mov r0, r4 2568 0050 FFF7FEFF bl AD9102_LoadSramRamp 2569 .LVL249: 3275:Src/main.c **** { 2570 .loc 1 3275 2 view .LVU774 3275:Src/main.c **** { 2571 .loc 1 3275 5 is_stmt 0 view .LVU775 2572 0054 36B1 cbz r6, .L172 3277:Src/main.c **** } 2573 .loc 1 3277 3 is_stmt 1 view .LVU776 2574 0056 FFF7FEFF bl AD9102_StartOutput 2575 .LVL250: 2576 .L173: 3284:Src/main.c **** } 2577 .loc 1 3284 2 view .LVU777 3284:Src/main.c **** } 2578 .loc 1 3284 9 is_stmt 0 view .LVU778 2579 005a 1E20 movs r0, #30 2580 005c FFF7FEFF bl AD9102_ReadReg 2581 .LVL251: 3285:Src/main.c **** 2582 .loc 1 3285 1 view .LVU779 2583 0060 BDE8F081 pop {r4, r5, r6, r7, r8, pc} 2584 .LVL252: 2585 .L172: 3281:Src/main.c **** } 2586 .loc 1 3281 3 is_stmt 1 view .LVU780 2587 0064 FFF7FEFF bl AD9102_StopOutput 2588 .LVL253: 2589 0068 F7E7 b .L173 2590 .cfi_endproc 2591 .LFE1232: 2593 .section .text.AD9102_Apply,"ax",%progbits 2594 .align 1 2595 .syntax unified 2596 .thumb 2597 .thumb_func 2599 AD9102_Apply: 2600 .LVL254: 2601 .LFB1230: 3116:Src/main.c **** AD9102_ResetWaveUploadState(); 2602 .loc 1 3116 1 view -0 2603 .cfi_startproc 2604 @ args = 4, pretend = 0, frame = 0 2605 @ frame_needed = 0, uses_anonymous_args = 0 3116:Src/main.c **** AD9102_ResetWaveUploadState(); 2606 .loc 1 3116 1 is_stmt 0 view .LVU782 2607 0000 F8B5 push {r3, r4, r5, r6, r7, lr} 2608 .LCFI25: 2609 .cfi_def_cfa_offset 24 2610 .cfi_offset 3, -24 2611 .cfi_offset 4, -20 2612 .cfi_offset 5, -16 2613 .cfi_offset 6, -12 2614 .cfi_offset 7, -8 ARM GAS /tmp/ccLSPxIe.s page 187 2615 .cfi_offset 14, -4 2616 0002 0546 mov r5, r0 2617 0004 0F46 mov r7, r1 2618 0006 1446 mov r4, r2 2619 0008 1E46 mov r6, r3 3117:Src/main.c **** 2620 .loc 1 3117 2 is_stmt 1 view .LVU783 2621 000a FFF7FEFF bl AD9102_ResetWaveUploadState 2622 .LVL255: 3119:Src/main.c **** { 2623 .loc 1 3119 2 view .LVU784 3119:Src/main.c **** { 2624 .loc 1 3119 5 is_stmt 0 view .LVU785 2625 000e 67B3 cbz r7, .L182 2626 .LBB426: 3121:Src/main.c **** uint16_t pat_timebase; 2627 .loc 1 3121 3 is_stmt 1 view .LVU786 3122:Src/main.c **** 2628 .loc 1 3122 3 view .LVU787 3124:Src/main.c **** { 2629 .loc 1 3124 3 view .LVU788 3124:Src/main.c **** { 2630 .loc 1 3124 6 is_stmt 0 view .LVU789 2631 0010 1CB1 cbz r4, .L185 3128:Src/main.c **** { 2632 .loc 1 3128 3 is_stmt 1 view .LVU790 3128:Src/main.c **** { 2633 .loc 1 3128 6 is_stmt 0 view .LVU791 2634 0012 3F2C cmp r4, #63 2635 0014 02D9 bls .L183 3130:Src/main.c **** } 2636 .loc 1 3130 13 view .LVU792 2637 0016 3F24 movs r4, #63 2638 .LVL256: 3130:Src/main.c **** } 2639 .loc 1 3130 13 view .LVU793 2640 0018 00E0 b .L183 2641 .LVL257: 2642 .L185: 3126:Src/main.c **** } 2643 .loc 1 3126 13 view .LVU794 2644 001a 0124 movs r4, #1 2645 .LVL258: 2646 .L183: 3132:Src/main.c **** ((uint16_t)(saw_type & 0x3u))); 2647 .loc 1 3132 3 is_stmt 1 view .LVU795 3133:Src/main.c **** pat_timebase = (uint16_t)(((AD9102_PAT_TIMEBASE_HOLD_DEFAULT & 0x0Fu) << 8) | 2648 .loc 1 3133 25 is_stmt 0 view .LVU796 2649 001c 05F00305 and r5, r5, #3 2650 .LVL259: 3132:Src/main.c **** ((uint16_t)(saw_type & 0x3u))); 2651 .loc 1 3132 60 view .LVU797 2652 0020 A400 lsls r4, r4, #2 2653 .LVL260: 3132:Src/main.c **** ((uint16_t)(saw_type & 0x3u))); 2654 .loc 1 3132 60 view .LVU798 2655 0022 E4B2 uxtb r4, r4 ARM GAS /tmp/ccLSPxIe.s page 188 3132:Src/main.c **** ((uint16_t)(saw_type & 0x3u))); 2656 .loc 1 3132 11 view .LVU799 2657 0024 2543 orrs r5, r5, r4 2658 .LVL261: 3134:Src/main.c **** ((pat_base & 0x0Fu) << 4) | 2659 .loc 1 3134 3 is_stmt 1 view .LVU800 3135:Src/main.c **** (AD9102_START_DELAY_BASE_DEFAULT & 0x0Fu)); 2660 .loc 1 3135 49 is_stmt 0 view .LVU801 2661 0026 3301 lsls r3, r6, #4 2662 0028 03F0F003 and r3, r3, #240 3134:Src/main.c **** ((pat_base & 0x0Fu) << 4) | 2663 .loc 1 3134 16 view .LVU802 2664 002c 40F20114 movw r4, #257 2665 0030 1C43 orrs r4, r4, r3 2666 .LVL262: 3138:Src/main.c **** AD9102_WriteReg(AD9102_REG_SAW_CONFIG, saw_cfg); 2667 .loc 1 3138 3 is_stmt 1 view .LVU803 2668 0032 43F21221 movw r1, #12818 2669 0036 2720 movs r0, #39 2670 0038 FFF7FEFF bl AD9102_WriteReg 2671 .LVL263: 3139:Src/main.c **** AD9102_WriteReg(AD9102_REG_PAT_TIMEBASE, pat_timebase); 2672 .loc 1 3139 3 view .LVU804 2673 003c 2946 mov r1, r5 2674 003e 3720 movs r0, #55 2675 0040 FFF7FEFF bl AD9102_WriteReg 2676 .LVL264: 3140:Src/main.c **** AD9102_WriteReg(AD9102_REG_PAT_PERIOD, pat_period); 2677 .loc 1 3140 3 view .LVU805 2678 0044 2146 mov r1, r4 2679 0046 2820 movs r0, #40 2680 0048 FFF7FEFF bl AD9102_WriteReg 2681 .LVL265: 3141:Src/main.c **** AD9102_WriteReg(AD9102_REG_PAT_TYPE, 0x0000u); // continuous pattern repeat 2682 .loc 1 3141 3 view .LVU806 2683 004c BDF81810 ldrh r1, [sp, #24] 2684 0050 2920 movs r0, #41 2685 0052 FFF7FEFF bl AD9102_WriteReg 2686 .LVL266: 3142:Src/main.c **** 2687 .loc 1 3142 3 view .LVU807 2688 0056 0021 movs r1, #0 2689 0058 1F20 movs r0, #31 2690 005a FFF7FEFF bl AD9102_WriteReg 2691 .LVL267: 3144:Src/main.c **** } 2692 .loc 1 3144 3 view .LVU808 2693 005e FFF7FEFF bl AD9102_StartOutput 2694 .LVL268: 2695 .L184: 3144:Src/main.c **** } 2696 .loc 1 3144 3 is_stmt 0 view .LVU809 2697 .LBE426: 3151:Src/main.c **** } 2698 .loc 1 3151 2 is_stmt 1 view .LVU810 3151:Src/main.c **** } 2699 .loc 1 3151 9 is_stmt 0 view .LVU811 ARM GAS /tmp/ccLSPxIe.s page 189 2700 0062 1E20 movs r0, #30 2701 0064 FFF7FEFF bl AD9102_ReadReg 2702 .LVL269: 3152:Src/main.c **** 2703 .loc 1 3152 1 view .LVU812 2704 0068 F8BD pop {r3, r4, r5, r6, r7, pc} 2705 .LVL270: 2706 .L182: 3148:Src/main.c **** } 2707 .loc 1 3148 3 is_stmt 1 view .LVU813 2708 006a FFF7FEFF bl AD9102_StopOutput 2709 .LVL271: 2710 006e F8E7 b .L184 2711 .cfi_endproc 2712 .LFE1230: 2714 .section .text.AD9102_CheckFlags,"ax",%progbits 2715 .align 1 2716 .syntax unified 2717 .thumb 2718 .thumb_func 2720 AD9102_CheckFlags: 2721 .LVL272: 2722 .LFB1233: 3288:Src/main.c **** uint16_t spiconfig = AD9102_ReadReg(AD9102_REG_SPICONFIG); 2723 .loc 1 3288 1 view -0 2724 .cfi_startproc 2725 @ args = 8, pretend = 0, frame = 8 2726 @ frame_needed = 0, uses_anonymous_args = 0 3288:Src/main.c **** uint16_t spiconfig = AD9102_ReadReg(AD9102_REG_SPICONFIG); 2727 .loc 1 3288 1 is_stmt 0 view .LVU815 2728 0000 2DE9F04F push {r4, r5, r6, r7, r8, r9, r10, fp, lr} 2729 .LCFI26: 2730 .cfi_def_cfa_offset 36 2731 .cfi_offset 4, -36 2732 .cfi_offset 5, -32 2733 .cfi_offset 6, -28 2734 .cfi_offset 7, -24 2735 .cfi_offset 8, -20 2736 .cfi_offset 9, -16 2737 .cfi_offset 10, -12 2738 .cfi_offset 11, -8 2739 .cfi_offset 14, -4 2740 0004 83B0 sub sp, sp, #12 2741 .LCFI27: 2742 .cfi_def_cfa_offset 48 2743 0006 0190 str r0, [sp, #4] 2744 0008 0F46 mov r7, r1 2745 000a 1546 mov r5, r2 2746 000c 1C46 mov r4, r3 2747 000e BDF834B0 ldrh fp, [sp, #52] 3289:Src/main.c **** uint16_t powercfg = AD9102_ReadReg(AD9102_REG_POWERCONFIG); 2748 .loc 1 3289 2 is_stmt 1 view .LVU816 3289:Src/main.c **** uint16_t powercfg = AD9102_ReadReg(AD9102_REG_POWERCONFIG); 2749 .loc 1 3289 23 is_stmt 0 view .LVU817 2750 0012 0020 movs r0, #0 2751 .LVL273: 3289:Src/main.c **** uint16_t powercfg = AD9102_ReadReg(AD9102_REG_POWERCONFIG); ARM GAS /tmp/ccLSPxIe.s page 190 2752 .loc 1 3289 23 view .LVU818 2753 0014 FFF7FEFF bl AD9102_ReadReg 2754 .LVL274: 3289:Src/main.c **** uint16_t powercfg = AD9102_ReadReg(AD9102_REG_POWERCONFIG); 2755 .loc 1 3289 23 view .LVU819 2756 0018 8246 mov r10, r0 2757 .LVL275: 3290:Src/main.c **** uint16_t clockcfg = AD9102_ReadReg(AD9102_REG_CLOCKCONFIG); 2758 .loc 1 3290 2 is_stmt 1 view .LVU820 3290:Src/main.c **** uint16_t clockcfg = AD9102_ReadReg(AD9102_REG_CLOCKCONFIG); 2759 .loc 1 3290 22 is_stmt 0 view .LVU821 2760 001a 0120 movs r0, #1 2761 001c FFF7FEFF bl AD9102_ReadReg 2762 .LVL276: 2763 0020 8146 mov r9, r0 2764 .LVL277: 3291:Src/main.c **** uint16_t cfg_err = AD9102_ReadReg(AD9102_REG_CFG_ERROR); 2765 .loc 1 3291 2 is_stmt 1 view .LVU822 3291:Src/main.c **** uint16_t cfg_err = AD9102_ReadReg(AD9102_REG_CFG_ERROR); 2766 .loc 1 3291 22 is_stmt 0 view .LVU823 2767 0022 0220 movs r0, #2 2768 0024 FFF7FEFF bl AD9102_ReadReg 2769 .LVL278: 2770 0028 8046 mov r8, r0 2771 .LVL279: 3292:Src/main.c **** uint16_t pat_timebase = (uint16_t)(((AD9102_PAT_TIMEBASE_HOLD_DEFAULT & 0x0Fu) << 8) | 2772 .loc 1 3292 2 is_stmt 1 view .LVU824 3292:Src/main.c **** uint16_t pat_timebase = (uint16_t)(((AD9102_PAT_TIMEBASE_HOLD_DEFAULT & 0x0Fu) << 8) | 2773 .loc 1 3292 21 is_stmt 0 view .LVU825 2774 002a 6020 movs r0, #96 2775 002c FFF7FEFF bl AD9102_ReadReg 2776 .LVL280: 3293:Src/main.c **** ((pat_base & 0x0Fu) << 4) | 2777 .loc 1 3293 2 is_stmt 1 view .LVU826 3294:Src/main.c **** (AD9102_START_DELAY_BASE_DEFAULT & 0x0Fu)); 2778 .loc 1 3294 57 is_stmt 0 view .LVU827 2779 0030 9DF83030 ldrb r3, [sp, #48] @ zero_extendqisi2 2780 0034 1B01 lsls r3, r3, #4 2781 0036 03F0F003 and r3, r3, #240 3293:Src/main.c **** ((pat_base & 0x0Fu) << 4) | 2782 .loc 1 3293 11 view .LVU828 2783 003a 40F20116 movw r6, #257 2784 003e 1E43 orrs r6, r6, r3 2785 .LVL281: 3297:Src/main.c **** { 2786 .loc 1 3297 2 is_stmt 1 view .LVU829 3297:Src/main.c **** { 2787 .loc 1 3297 5 is_stmt 0 view .LVU830 2788 0040 1CB1 cbz r4, .L201 3301:Src/main.c **** { 2789 .loc 1 3301 2 is_stmt 1 view .LVU831 3301:Src/main.c **** { 2790 .loc 1 3301 5 is_stmt 0 view .LVU832 2791 0042 3F2C cmp r4, #63 2792 0044 02D9 bls .L189 3303:Src/main.c **** } 2793 .loc 1 3303 12 view .LVU833 ARM GAS /tmp/ccLSPxIe.s page 191 2794 0046 3F24 movs r4, #63 2795 .LVL282: 3303:Src/main.c **** } 2796 .loc 1 3303 12 view .LVU834 2797 0048 00E0 b .L189 2798 .LVL283: 2799 .L201: 3299:Src/main.c **** } 2800 .loc 1 3299 12 view .LVU835 2801 004a 0124 movs r4, #1 2802 .LVL284: 2803 .L189: 3305:Src/main.c **** { 2804 .loc 1 3305 2 is_stmt 1 view .LVU836 3305:Src/main.c **** { 2805 .loc 1 3305 5 is_stmt 0 view .LVU837 2806 004c BBF1000F cmp fp, #0 2807 0050 01D1 bne .L190 3307:Src/main.c **** } 2808 .loc 1 3307 14 view .LVU838 2809 0052 4FF6FF7B movw fp, #65535 2810 .L190: 2811 .LVL285: 3309:Src/main.c **** ((uint16_t)(saw_type & 0x3u))); 2812 .loc 1 3309 2 is_stmt 1 view .LVU839 3310:Src/main.c **** 2813 .loc 1 3310 35 is_stmt 0 view .LVU840 2814 0056 05F00305 and r5, r5, #3 2815 .LVL286: 3309:Src/main.c **** ((uint16_t)(saw_type & 0x3u))); 2816 .loc 1 3309 71 view .LVU841 2817 005a A400 lsls r4, r4, #2 2818 .LVL287: 3309:Src/main.c **** ((uint16_t)(saw_type & 0x3u))); 2819 .loc 1 3309 71 view .LVU842 2820 005c E4B2 uxtb r4, r4 3309:Src/main.c **** ((uint16_t)(saw_type & 0x3u))); 2821 .loc 1 3309 11 view .LVU843 2822 005e 2543 orrs r5, r5, r4 2823 .LVL288: 3312:Src/main.c **** 2824 .loc 1 3312 2 is_stmt 1 view .LVU844 3315:Src/main.c **** { 2825 .loc 1 3315 2 view .LVU845 3315:Src/main.c **** { 2826 .loc 1 3315 5 is_stmt 0 view .LVU846 2827 0060 BAF1000F cmp r10, #0 2828 0064 36D1 bne .L204 3312:Src/main.c **** 2829 .loc 1 3312 10 view .LVU847 2830 0066 0124 movs r4, #1 2831 .L191: 2832 .LVL289: 3321:Src/main.c **** { 2833 .loc 1 3321 2 is_stmt 1 view .LVU848 3321:Src/main.c **** { 2834 .loc 1 3321 5 is_stmt 0 view .LVU849 ARM GAS /tmp/ccLSPxIe.s page 192 2835 0068 19F4F47F tst r9, #488 2836 006c 00D0 beq .L192 3323:Src/main.c **** } 2837 .loc 1 3323 6 view .LVU850 2838 006e 0024 movs r4, #0 2839 .LVL290: 2840 .L192: 3327:Src/main.c **** { 2841 .loc 1 3327 2 is_stmt 1 view .LVU851 3327:Src/main.c **** { 2842 .loc 1 3327 5 is_stmt 0 view .LVU852 2843 0070 18F40E6F tst r8, #2272 2844 0074 00D0 beq .L193 3329:Src/main.c **** } 2845 .loc 1 3329 6 view .LVU853 2846 0076 0024 movs r4, #0 2847 .LVL291: 2848 .L193: 3333:Src/main.c **** { 2849 .loc 1 3333 2 is_stmt 1 view .LVU854 3333:Src/main.c **** { 2850 .loc 1 3333 5 is_stmt 0 view .LVU855 2851 0078 10F03F0F tst r0, #63 2852 007c 00D0 beq .L194 3335:Src/main.c **** } 2853 .loc 1 3335 6 view .LVU856 2854 007e 0024 movs r4, #0 2855 .LVL292: 2856 .L194: 3338:Src/main.c **** { 2857 .loc 1 3338 2 is_stmt 1 view .LVU857 3338:Src/main.c **** { 2858 .loc 1 3338 5 is_stmt 0 view .LVU858 2859 0080 27B1 cbz r7, .L195 3338:Src/main.c **** { 2860 .loc 1 3338 17 discriminator 1 view .LVU859 2861 0082 019B ldr r3, [sp, #4] 2862 0084 13F0010F tst r3, #1 2863 0088 00D1 bne .L195 3340:Src/main.c **** } 2864 .loc 1 3340 6 view .LVU860 2865 008a 0024 movs r4, #0 2866 .LVL293: 2867 .L195: 3343:Src/main.c **** { 2868 .loc 1 3343 2 is_stmt 1 view .LVU861 3343:Src/main.c **** { 2869 .loc 1 3343 6 is_stmt 0 view .LVU862 2870 008c 2720 movs r0, #39 2871 .LVL294: 3343:Src/main.c **** { 2872 .loc 1 3343 6 view .LVU863 2873 008e FFF7FEFF bl AD9102_ReadReg 2874 .LVL295: 3343:Src/main.c **** { 2875 .loc 1 3343 5 discriminator 1 view .LVU864 2876 0092 43F21223 movw r3, #12818 ARM GAS /tmp/ccLSPxIe.s page 193 2877 0096 9842 cmp r0, r3 2878 0098 00D0 beq .L196 3345:Src/main.c **** } 2879 .loc 1 3345 6 view .LVU865 2880 009a 0024 movs r4, #0 2881 .LVL296: 2882 .L196: 3347:Src/main.c **** { 2883 .loc 1 3347 2 is_stmt 1 view .LVU866 3347:Src/main.c **** { 2884 .loc 1 3347 6 is_stmt 0 view .LVU867 2885 009c 2820 movs r0, #40 2886 009e FFF7FEFF bl AD9102_ReadReg 2887 .LVL297: 3347:Src/main.c **** { 2888 .loc 1 3347 5 discriminator 1 view .LVU868 2889 00a2 B042 cmp r0, r6 2890 00a4 00D0 beq .L197 3349:Src/main.c **** } 2891 .loc 1 3349 6 view .LVU869 2892 00a6 0024 movs r4, #0 2893 .LVL298: 2894 .L197: 3351:Src/main.c **** { 2895 .loc 1 3351 2 is_stmt 1 view .LVU870 3351:Src/main.c **** { 2896 .loc 1 3351 6 is_stmt 0 view .LVU871 2897 00a8 2920 movs r0, #41 2898 00aa FFF7FEFF bl AD9102_ReadReg 2899 .LVL299: 3351:Src/main.c **** { 2900 .loc 1 3351 5 discriminator 1 view .LVU872 2901 00ae 5845 cmp r0, fp 2902 00b0 00D0 beq .L198 3353:Src/main.c **** } 2903 .loc 1 3353 6 view .LVU873 2904 00b2 0024 movs r4, #0 2905 .LVL300: 2906 .L198: 3355:Src/main.c **** { 2907 .loc 1 3355 2 is_stmt 1 view .LVU874 3355:Src/main.c **** { 2908 .loc 1 3355 6 is_stmt 0 view .LVU875 2909 00b4 1F20 movs r0, #31 2910 00b6 FFF7FEFF bl AD9102_ReadReg 2911 .LVL301: 3355:Src/main.c **** { 2912 .loc 1 3355 5 discriminator 1 view .LVU876 2913 00ba 00B1 cbz r0, .L199 3357:Src/main.c **** } 2914 .loc 1 3357 6 view .LVU877 2915 00bc 0024 movs r4, #0 2916 .LVL302: 2917 .L199: 3359:Src/main.c **** { 2918 .loc 1 3359 2 is_stmt 1 view .LVU878 3359:Src/main.c **** { ARM GAS /tmp/ccLSPxIe.s page 194 2919 .loc 1 3359 6 is_stmt 0 view .LVU879 2920 00be 3720 movs r0, #55 2921 00c0 FFF7FEFF bl AD9102_ReadReg 2922 .LVL303: 3359:Src/main.c **** { 2923 .loc 1 3359 5 discriminator 1 view .LVU880 2924 00c4 A842 cmp r0, r5 2925 00c6 00D0 beq .L200 3361:Src/main.c **** } 2926 .loc 1 3361 6 view .LVU881 2927 00c8 0024 movs r4, #0 2928 .LVL304: 2929 .L200: 3364:Src/main.c **** } 2930 .loc 1 3364 2 is_stmt 1 view .LVU882 3365:Src/main.c **** 2931 .loc 1 3365 1 is_stmt 0 view .LVU883 2932 00ca 84F00100 eor r0, r4, #1 2933 00ce 03B0 add sp, sp, #12 2934 .LCFI28: 2935 .cfi_remember_state 2936 .cfi_def_cfa_offset 36 2937 @ sp needed 2938 00d0 BDE8F08F pop {r4, r5, r6, r7, r8, r9, r10, fp, pc} 2939 .LVL305: 2940 .L204: 2941 .LCFI29: 2942 .cfi_restore_state 3317:Src/main.c **** } 2943 .loc 1 3317 6 view .LVU884 2944 00d4 0024 movs r4, #0 2945 00d6 C7E7 b .L191 2946 .cfi_endproc 2947 .LFE1233: 2949 .section .text.AD9102_CommitWaveUpload,"ax",%progbits 2950 .align 1 2951 .syntax unified 2952 .thumb 2953 .thumb_func 2955 AD9102_CommitWaveUpload: 2956 .LVL306: 2957 .LFB1228: 3074:Src/main.c **** uint16_t pat_status; 2958 .loc 1 3074 1 is_stmt 1 view -0 2959 .cfi_startproc 2960 @ args = 0, pretend = 0, frame = 0 2961 @ frame_needed = 0, uses_anonymous_args = 0 3074:Src/main.c **** uint16_t pat_status; 2962 .loc 1 3074 1 is_stmt 0 view .LVU886 2963 0000 38B5 push {r3, r4, r5, lr} 2964 .LCFI30: 2965 .cfi_def_cfa_offset 16 2966 .cfi_offset 3, -16 2967 .cfi_offset 4, -12 2968 .cfi_offset 5, -8 2969 .cfi_offset 14, -4 3075:Src/main.c **** ARM GAS /tmp/ccLSPxIe.s page 195 2970 .loc 1 3075 2 is_stmt 1 view .LVU887 3077:Src/main.c **** { 2971 .loc 1 3077 2 view .LVU888 3077:Src/main.c **** { 2972 .loc 1 3077 5 is_stmt 0 view .LVU889 2973 0002 0546 mov r5, r0 2974 0004 08B1 cbz r0, .L216 3079:Src/main.c **** } 2975 .loc 1 3079 3 is_stmt 1 view .LVU890 3079:Src/main.c **** } 2976 .loc 1 3079 7 is_stmt 0 view .LVU891 2977 0006 0023 movs r3, #0 2978 0008 0370 strb r3, [r0] 2979 .L216: 3082:Src/main.c **** (ad9102_wave_expected_samples < 2u) || 2980 .loc 1 3082 2 is_stmt 1 view .LVU892 3082:Src/main.c **** (ad9102_wave_expected_samples < 2u) || 2981 .loc 1 3082 33 is_stmt 0 view .LVU893 2982 000a 1A4B ldr r3, .L221 2983 000c 1B78 ldrb r3, [r3] @ zero_extendqisi2 3082:Src/main.c **** (ad9102_wave_expected_samples < 2u) || 2984 .loc 1 3082 5 view .LVU894 2985 000e 3BB1 cbz r3, .L217 3083:Src/main.c **** (ad9102_wave_written_samples != ad9102_wave_expected_samples)) 2986 .loc 1 3083 36 view .LVU895 2987 0010 194B ldr r3, .L221+4 2988 0012 1B88 ldrh r3, [r3] 3082:Src/main.c **** (ad9102_wave_expected_samples < 2u) || 2989 .loc 1 3082 40 discriminator 1 view .LVU896 2990 0014 012B cmp r3, #1 2991 0016 03D9 bls .L217 3084:Src/main.c **** { 2992 .loc 1 3084 35 view .LVU897 2993 0018 184A ldr r2, .L221+8 2994 001a 1288 ldrh r2, [r2] 3083:Src/main.c **** (ad9102_wave_written_samples != ad9102_wave_expected_samples)) 2995 .loc 1 3083 42 view .LVU898 2996 001c 9342 cmp r3, r2 2997 001e 07D0 beq .L218 2998 .L217: 3086:Src/main.c **** return AD9102_ReadReg(AD9102_REG_PAT_STATUS); 2999 .loc 1 3086 3 is_stmt 1 view .LVU899 3000 0020 FFF7FEFF bl AD9102_CancelWaveUpload 3001 .LVL307: 3087:Src/main.c **** } 3002 .loc 1 3087 3 view .LVU900 3087:Src/main.c **** } 3003 .loc 1 3087 10 is_stmt 0 view .LVU901 3004 0024 1E20 movs r0, #30 3005 0026 FFF7FEFF bl AD9102_ReadReg 3006 .LVL308: 3007 002a 0446 mov r4, r0 3008 .L219: 3104:Src/main.c **** 3009 .loc 1 3104 1 view .LVU902 3010 002c 2046 mov r0, r4 3011 002e 38BD pop {r3, r4, r5, pc} ARM GAS /tmp/ccLSPxIe.s page 196 3012 .LVL309: 3013 .L218: 3090:Src/main.c **** AD9102_WriteReg(AD9102_REG_START_ADDR, 0x0000u); 3014 .loc 1 3090 2 is_stmt 1 view .LVU903 3015 0030 0021 movs r1, #0 3016 0032 1E20 movs r0, #30 3017 .LVL310: 3090:Src/main.c **** AD9102_WriteReg(AD9102_REG_START_ADDR, 0x0000u); 3018 .loc 1 3090 2 is_stmt 0 view .LVU904 3019 0034 FFF7FEFF bl AD9102_WriteReg 3020 .LVL311: 3091:Src/main.c **** AD9102_WriteReg(AD9102_REG_STOP_ADDR, (uint16_t)((ad9102_wave_expected_samples - 1u) << 4)); 3021 .loc 1 3091 2 is_stmt 1 view .LVU905 3022 0038 0021 movs r1, #0 3023 003a 5D20 movs r0, #93 3024 003c FFF7FEFF bl AD9102_WriteReg 3025 .LVL312: 3092:Src/main.c **** AD9102_WriteReg(AD9102_REG_RAMUPDATE, 0x0001u); 3026 .loc 1 3092 2 view .LVU906 3092:Src/main.c **** AD9102_WriteReg(AD9102_REG_RAMUPDATE, 0x0001u); 3027 .loc 1 3092 81 is_stmt 0 view .LVU907 3028 0040 0D4B ldr r3, .L221+4 3029 0042 1988 ldrh r1, [r3] 3030 0044 0139 subs r1, r1, #1 3031 0046 89B2 uxth r1, r1 3092:Src/main.c **** AD9102_WriteReg(AD9102_REG_RAMUPDATE, 0x0001u); 3032 .loc 1 3092 2 view .LVU908 3033 0048 0901 lsls r1, r1, #4 3034 004a 89B2 uxth r1, r1 3035 004c 5E20 movs r0, #94 3036 004e FFF7FEFF bl AD9102_WriteReg 3037 .LVL313: 3093:Src/main.c **** AD9102_StartOutput(); 3038 .loc 1 3093 2 is_stmt 1 view .LVU909 3039 0052 0121 movs r1, #1 3040 0054 1D20 movs r0, #29 3041 0056 FFF7FEFF bl AD9102_WriteReg 3042 .LVL314: 3094:Src/main.c **** pat_status = AD9102_ReadReg(AD9102_REG_PAT_STATUS); 3043 .loc 1 3094 2 view .LVU910 3044 005a FFF7FEFF bl AD9102_StartOutput 3045 .LVL315: 3095:Src/main.c **** 3046 .loc 1 3095 2 view .LVU911 3095:Src/main.c **** 3047 .loc 1 3095 15 is_stmt 0 view .LVU912 3048 005e 1E20 movs r0, #30 3049 0060 FFF7FEFF bl AD9102_ReadReg 3050 .LVL316: 3051 0064 0446 mov r4, r0 3052 .LVL317: 3097:Src/main.c **** if (ok != NULL) 3053 .loc 1 3097 2 is_stmt 1 view .LVU913 3054 0066 FFF7FEFF bl AD9102_ResetWaveUploadState 3055 .LVL318: 3098:Src/main.c **** { 3056 .loc 1 3098 2 view .LVU914 ARM GAS /tmp/ccLSPxIe.s page 197 3098:Src/main.c **** { 3057 .loc 1 3098 5 is_stmt 0 view .LVU915 3058 006a 002D cmp r5, #0 3059 006c DED0 beq .L219 3100:Src/main.c **** } 3060 .loc 1 3100 3 is_stmt 1 view .LVU916 3100:Src/main.c **** } 3061 .loc 1 3100 7 is_stmt 0 view .LVU917 3062 006e 0123 movs r3, #1 3063 0070 2B70 strb r3, [r5] 3064 0072 DBE7 b .L219 3065 .L222: 3066 .align 2 3067 .L221: 3068 0074 00000000 .word ad9102_wave_upload_active 3069 0078 00000000 .word ad9102_wave_expected_samples 3070 007c 00000000 .word ad9102_wave_written_samples 3071 .cfi_endproc 3072 .LFE1228: 3074 .section .text.AD9102_CheckFlagsSram,"ax",%progbits 3075 .align 1 3076 .syntax unified 3077 .thumb 3078 .thumb_func 3080 AD9102_CheckFlagsSram: 3081 .LVL319: 3082 .LFB1234: 3368:Src/main.c **** uint16_t spiconfig = AD9102_ReadReg(AD9102_REG_SPICONFIG); 3083 .loc 1 3368 1 is_stmt 1 view -0 3084 .cfi_startproc 3085 @ args = 0, pretend = 0, frame = 8 3086 @ frame_needed = 0, uses_anonymous_args = 0 3368:Src/main.c **** uint16_t spiconfig = AD9102_ReadReg(AD9102_REG_SPICONFIG); 3087 .loc 1 3368 1 is_stmt 0 view .LVU919 3088 0000 2DE9F04F push {r4, r5, r6, r7, r8, r9, r10, fp, lr} 3089 .LCFI31: 3090 .cfi_def_cfa_offset 36 3091 .cfi_offset 4, -36 3092 .cfi_offset 5, -32 3093 .cfi_offset 6, -28 3094 .cfi_offset 7, -24 3095 .cfi_offset 8, -20 3096 .cfi_offset 9, -16 3097 .cfi_offset 10, -12 3098 .cfi_offset 11, -8 3099 .cfi_offset 14, -4 3100 0004 83B0 sub sp, sp, #12 3101 .LCFI32: 3102 .cfi_def_cfa_offset 48 3103 0006 8346 mov fp, r0 3104 0008 0F46 mov r7, r1 3105 000a 1446 mov r4, r2 3106 000c 1D46 mov r5, r3 3369:Src/main.c **** uint16_t powercfg = AD9102_ReadReg(AD9102_REG_POWERCONFIG); 3107 .loc 1 3369 2 is_stmt 1 view .LVU920 3369:Src/main.c **** uint16_t powercfg = AD9102_ReadReg(AD9102_REG_POWERCONFIG); 3108 .loc 1 3369 23 is_stmt 0 view .LVU921 ARM GAS /tmp/ccLSPxIe.s page 198 3109 000e 0020 movs r0, #0 3110 .LVL320: 3369:Src/main.c **** uint16_t powercfg = AD9102_ReadReg(AD9102_REG_POWERCONFIG); 3111 .loc 1 3369 23 view .LVU922 3112 0010 FFF7FEFF bl AD9102_ReadReg 3113 .LVL321: 3369:Src/main.c **** uint16_t powercfg = AD9102_ReadReg(AD9102_REG_POWERCONFIG); 3114 .loc 1 3369 23 view .LVU923 3115 0014 8246 mov r10, r0 3116 .LVL322: 3370:Src/main.c **** uint16_t clockcfg = AD9102_ReadReg(AD9102_REG_CLOCKCONFIG); 3117 .loc 1 3370 2 is_stmt 1 view .LVU924 3370:Src/main.c **** uint16_t clockcfg = AD9102_ReadReg(AD9102_REG_CLOCKCONFIG); 3118 .loc 1 3370 22 is_stmt 0 view .LVU925 3119 0016 0120 movs r0, #1 3120 0018 FFF7FEFF bl AD9102_ReadReg 3121 .LVL323: 3122 001c 8146 mov r9, r0 3123 .LVL324: 3371:Src/main.c **** uint16_t cfg_err = AD9102_ReadReg(AD9102_REG_CFG_ERROR); 3124 .loc 1 3371 2 is_stmt 1 view .LVU926 3371:Src/main.c **** uint16_t cfg_err = AD9102_ReadReg(AD9102_REG_CFG_ERROR); 3125 .loc 1 3371 22 is_stmt 0 view .LVU927 3126 001e 0220 movs r0, #2 3127 0020 FFF7FEFF bl AD9102_ReadReg 3128 .LVL325: 3129 0024 8046 mov r8, r0 3130 .LVL326: 3372:Src/main.c **** 3131 .loc 1 3372 2 is_stmt 1 view .LVU928 3372:Src/main.c **** 3132 .loc 1 3372 21 is_stmt 0 view .LVU929 3133 0026 6020 movs r0, #96 3134 0028 FFF7FEFF bl AD9102_ReadReg 3135 .LVL327: 3374:Src/main.c **** { 3136 .loc 1 3374 2 is_stmt 1 view .LVU930 3374:Src/main.c **** { 3137 .loc 1 3374 5 is_stmt 0 view .LVU931 3138 002c 1CB1 cbz r4, .L240 3378:Src/main.c **** { 3139 .loc 1 3378 2 is_stmt 1 view .LVU932 3378:Src/main.c **** { 3140 .loc 1 3378 5 is_stmt 0 view .LVU933 3141 002e 012C cmp r4, #1 3142 0030 02D8 bhi .L224 3380:Src/main.c **** } 3143 .loc 1 3380 11 view .LVU934 3144 0032 0224 movs r4, #2 3145 .LVL328: 3380:Src/main.c **** } 3146 .loc 1 3380 11 view .LVU935 3147 0034 03E0 b .L225 3148 .LVL329: 3149 .L240: 3376:Src/main.c **** } 3150 .loc 1 3376 11 view .LVU936 ARM GAS /tmp/ccLSPxIe.s page 199 3151 0036 1024 movs r4, #16 3152 .LVL330: 3153 .L224: 3382:Src/main.c **** { 3154 .loc 1 3382 2 is_stmt 1 view .LVU937 3382:Src/main.c **** { 3155 .loc 1 3382 5 is_stmt 0 view .LVU938 3156 0038 B4F5805F cmp r4, #4096 3157 003c 04D8 bhi .L242 3158 .LVL331: 3159 .L225: 3386:Src/main.c **** { 3160 .loc 1 3386 2 is_stmt 1 view .LVU939 3386:Src/main.c **** { 3161 .loc 1 3386 5 is_stmt 0 view .LVU940 3162 003e 35B1 cbz r5, .L243 3390:Src/main.c **** { 3163 .loc 1 3390 2 is_stmt 1 view .LVU941 3390:Src/main.c **** { 3164 .loc 1 3390 5 is_stmt 0 view .LVU942 3165 0040 0F2D cmp r5, #15 3166 0042 05D9 bls .L226 3392:Src/main.c **** } 3167 .loc 1 3392 8 view .LVU943 3168 0044 0F25 movs r5, #15 3169 .LVL332: 3392:Src/main.c **** } 3170 .loc 1 3392 8 view .LVU944 3171 0046 03E0 b .L226 3172 .LVL333: 3173 .L242: 3384:Src/main.c **** } 3174 .loc 1 3384 11 view .LVU945 3175 0048 4FF48054 mov r4, #4096 3176 .LVL334: 3384:Src/main.c **** } 3177 .loc 1 3384 11 view .LVU946 3178 004c F7E7 b .L225 3179 .LVL335: 3180 .L243: 3388:Src/main.c **** } 3181 .loc 1 3388 8 view .LVU947 3182 004e 0125 movs r5, #1 3183 .LVL336: 3184 .L226: 3395:Src/main.c **** ((AD9102_SRAM_PAT_PERIOD_BASE_DEFAULT & 0x0Fu) << 4) | 3185 .loc 1 3395 2 is_stmt 1 view .LVU948 3395:Src/main.c **** ((AD9102_SRAM_PAT_PERIOD_BASE_DEFAULT & 0x0Fu) << 4) | 3186 .loc 1 3395 63 is_stmt 0 view .LVU949 3187 0050 2E02 lsls r6, r5, #8 3188 0052 06F47066 and r6, r6, #3840 3395:Src/main.c **** ((AD9102_SRAM_PAT_PERIOD_BASE_DEFAULT & 0x0Fu) << 4) | 3189 .loc 1 3395 11 view .LVU950 3190 0056 46F01106 orr r6, r6, #17 3191 .LVL337: 3398:Src/main.c **** if (pat_period == 0u) 3192 .loc 1 3398 2 is_stmt 1 view .LVU951 ARM GAS /tmp/ccLSPxIe.s page 200 3398:Src/main.c **** if (pat_period == 0u) 3193 .loc 1 3398 24 is_stmt 0 view .LVU952 3194 005a 0194 str r4, [sp, #4] 3398:Src/main.c **** if (pat_period == 0u) 3195 .loc 1 3398 44 view .LVU953 3196 005c 05F00F05 and r5, r5, #15 3197 .LVL338: 3398:Src/main.c **** if (pat_period == 0u) 3198 .loc 1 3398 11 view .LVU954 3199 0060 04FB05F5 mul r5, r4, r5 3200 .LVL339: 3399:Src/main.c **** { 3201 .loc 1 3399 2 is_stmt 1 view .LVU955 3399:Src/main.c **** { 3202 .loc 1 3399 5 is_stmt 0 view .LVU956 3203 0064 1DB1 cbz r5, .L227 3403:Src/main.c **** { 3204 .loc 1 3403 2 is_stmt 1 view .LVU957 3403:Src/main.c **** { 3205 .loc 1 3403 5 is_stmt 0 view .LVU958 3206 0066 B5F5803F cmp r5, #65536 3207 006a 4CD2 bcs .L245 3208 006c 0195 str r5, [sp, #4] 3209 .L227: 3210 .LVL340: 3408:Src/main.c **** 3211 .loc 1 3408 2 is_stmt 1 view .LVU959 3408:Src/main.c **** 3212 .loc 1 3408 43 is_stmt 0 view .LVU960 3213 006e 013C subs r4, r4, #1 3214 .LVL341: 3408:Src/main.c **** 3215 .loc 1 3408 43 view .LVU961 3216 0070 A4B2 uxth r4, r4 3408:Src/main.c **** 3217 .loc 1 3408 11 view .LVU962 3218 0072 2401 lsls r4, r4, #4 3219 0074 A4B2 uxth r4, r4 3220 .LVL342: 3410:Src/main.c **** 3221 .loc 1 3410 2 is_stmt 1 view .LVU963 3412:Src/main.c **** { 3222 .loc 1 3412 2 view .LVU964 3412:Src/main.c **** { 3223 .loc 1 3412 5 is_stmt 0 view .LVU965 3224 0076 BAF1000F cmp r10, #0 3225 007a 48D1 bne .L246 3410:Src/main.c **** 3226 .loc 1 3410 10 view .LVU966 3227 007c 0125 movs r5, #1 3228 .L228: 3229 .LVL343: 3416:Src/main.c **** { 3230 .loc 1 3416 2 is_stmt 1 view .LVU967 3416:Src/main.c **** { 3231 .loc 1 3416 5 is_stmt 0 view .LVU968 3232 007e 19F4F47F tst r9, #488 ARM GAS /tmp/ccLSPxIe.s page 201 3233 0082 00D0 beq .L229 3418:Src/main.c **** } 3234 .loc 1 3418 6 view .LVU969 3235 0084 0025 movs r5, #0 3236 .LVL344: 3237 .L229: 3420:Src/main.c **** { 3238 .loc 1 3420 2 is_stmt 1 view .LVU970 3420:Src/main.c **** { 3239 .loc 1 3420 5 is_stmt 0 view .LVU971 3240 0086 18F40E6F tst r8, #2272 3241 008a 00D0 beq .L230 3422:Src/main.c **** } 3242 .loc 1 3422 6 view .LVU972 3243 008c 0025 movs r5, #0 3244 .LVL345: 3245 .L230: 3424:Src/main.c **** { 3246 .loc 1 3424 2 is_stmt 1 view .LVU973 3424:Src/main.c **** { 3247 .loc 1 3424 5 is_stmt 0 view .LVU974 3248 008e 10F03F0F tst r0, #63 3249 0092 00D0 beq .L231 3426:Src/main.c **** } 3250 .loc 1 3426 6 view .LVU975 3251 0094 0025 movs r5, #0 3252 .LVL346: 3253 .L231: 3428:Src/main.c **** { 3254 .loc 1 3428 2 is_stmt 1 view .LVU976 3428:Src/main.c **** { 3255 .loc 1 3428 5 is_stmt 0 view .LVU977 3256 0096 1FB1 cbz r7, .L232 3428:Src/main.c **** { 3257 .loc 1 3428 17 discriminator 1 view .LVU978 3258 0098 1BF0010F tst fp, #1 3259 009c 00D1 bne .L232 3430:Src/main.c **** } 3260 .loc 1 3430 6 view .LVU979 3261 009e 0025 movs r5, #0 3262 .LVL347: 3263 .L232: 3433:Src/main.c **** { 3264 .loc 1 3433 2 is_stmt 1 view .LVU980 3433:Src/main.c **** { 3265 .loc 1 3433 6 is_stmt 0 view .LVU981 3266 00a0 2720 movs r0, #39 3267 .LVL348: 3433:Src/main.c **** { 3268 .loc 1 3433 6 view .LVU982 3269 00a2 FFF7FEFF bl AD9102_ReadReg 3270 .LVL349: 3433:Src/main.c **** { 3271 .loc 1 3433 5 discriminator 1 view .LVU983 3272 00a6 43F23003 movw r3, #12336 3273 00aa 9842 cmp r0, r3 3274 00ac 00D0 beq .L233 ARM GAS /tmp/ccLSPxIe.s page 202 3435:Src/main.c **** } 3275 .loc 1 3435 6 view .LVU984 3276 00ae 0025 movs r5, #0 3277 .LVL350: 3278 .L233: 3437:Src/main.c **** { 3279 .loc 1 3437 2 is_stmt 1 view .LVU985 3437:Src/main.c **** { 3280 .loc 1 3437 6 is_stmt 0 view .LVU986 3281 00b0 2820 movs r0, #40 3282 00b2 FFF7FEFF bl AD9102_ReadReg 3283 .LVL351: 3437:Src/main.c **** { 3284 .loc 1 3437 5 discriminator 1 view .LVU987 3285 00b6 B042 cmp r0, r6 3286 00b8 00D0 beq .L234 3439:Src/main.c **** } 3287 .loc 1 3439 6 view .LVU988 3288 00ba 0025 movs r5, #0 3289 .LVL352: 3290 .L234: 3441:Src/main.c **** { 3291 .loc 1 3441 2 is_stmt 1 view .LVU989 3441:Src/main.c **** { 3292 .loc 1 3441 6 is_stmt 0 view .LVU990 3293 00bc 2920 movs r0, #41 3294 00be FFF7FEFF bl AD9102_ReadReg 3295 .LVL353: 3441:Src/main.c **** { 3296 .loc 1 3441 44 discriminator 1 view .LVU991 3297 00c2 BDF80430 ldrh r3, [sp, #4] 3441:Src/main.c **** { 3298 .loc 1 3441 5 discriminator 1 view .LVU992 3299 00c6 9842 cmp r0, r3 3300 00c8 00D0 beq .L235 3443:Src/main.c **** } 3301 .loc 1 3443 6 view .LVU993 3302 00ca 0025 movs r5, #0 3303 .LVL354: 3304 .L235: 3445:Src/main.c **** { 3305 .loc 1 3445 2 is_stmt 1 view .LVU994 3445:Src/main.c **** { 3306 .loc 1 3445 6 is_stmt 0 view .LVU995 3307 00cc 1F20 movs r0, #31 3308 00ce FFF7FEFF bl AD9102_ReadReg 3309 .LVL355: 3445:Src/main.c **** { 3310 .loc 1 3445 5 discriminator 1 view .LVU996 3311 00d2 00B1 cbz r0, .L236 3447:Src/main.c **** } 3312 .loc 1 3447 6 view .LVU997 3313 00d4 0025 movs r5, #0 3314 .LVL356: 3315 .L236: 3449:Src/main.c **** { 3316 .loc 1 3449 2 is_stmt 1 view .LVU998 ARM GAS /tmp/ccLSPxIe.s page 203 3449:Src/main.c **** { 3317 .loc 1 3449 6 is_stmt 0 view .LVU999 3318 00d6 5D20 movs r0, #93 3319 00d8 FFF7FEFF bl AD9102_ReadReg 3320 .LVL357: 3449:Src/main.c **** { 3321 .loc 1 3449 5 discriminator 1 view .LVU1000 3322 00dc 00B1 cbz r0, .L237 3451:Src/main.c **** } 3323 .loc 1 3451 6 view .LVU1001 3324 00de 0025 movs r5, #0 3325 .LVL358: 3326 .L237: 3453:Src/main.c **** { 3327 .loc 1 3453 2 is_stmt 1 view .LVU1002 3453:Src/main.c **** { 3328 .loc 1 3453 6 is_stmt 0 view .LVU1003 3329 00e0 5E20 movs r0, #94 3330 00e2 FFF7FEFF bl AD9102_ReadReg 3331 .LVL359: 3453:Src/main.c **** { 3332 .loc 1 3453 5 discriminator 1 view .LVU1004 3333 00e6 A042 cmp r0, r4 3334 00e8 00D0 beq .L238 3455:Src/main.c **** } 3335 .loc 1 3455 6 view .LVU1005 3336 00ea 0025 movs r5, #0 3337 .LVL360: 3338 .L238: 3457:Src/main.c **** { 3339 .loc 1 3457 2 is_stmt 1 view .LVU1006 3457:Src/main.c **** { 3340 .loc 1 3457 6 is_stmt 0 view .LVU1007 3341 00ec 2B20 movs r0, #43 3342 00ee FFF7FEFF bl AD9102_ReadReg 3343 .LVL361: 3457:Src/main.c **** { 3344 .loc 1 3457 5 discriminator 1 view .LVU1008 3345 00f2 40F20113 movw r3, #257 3346 00f6 9842 cmp r0, r3 3347 00f8 00D0 beq .L239 3459:Src/main.c **** } 3348 .loc 1 3459 6 view .LVU1009 3349 00fa 0025 movs r5, #0 3350 .LVL362: 3351 .L239: 3462:Src/main.c **** } 3352 .loc 1 3462 2 is_stmt 1 view .LVU1010 3463:Src/main.c **** 3353 .loc 1 3463 1 is_stmt 0 view .LVU1011 3354 00fc 85F00100 eor r0, r5, #1 3355 0100 03B0 add sp, sp, #12 3356 .LCFI33: 3357 .cfi_remember_state 3358 .cfi_def_cfa_offset 36 3359 @ sp needed 3360 0102 BDE8F08F pop {r4, r5, r6, r7, r8, r9, r10, fp, pc} ARM GAS /tmp/ccLSPxIe.s page 204 3361 .LVL363: 3362 .L245: 3363 .LCFI34: 3364 .cfi_restore_state 3405:Src/main.c **** } 3365 .loc 1 3405 14 view .LVU1012 3366 0106 4FF6FF73 movw r3, #65535 3367 010a 0193 str r3, [sp, #4] 3368 010c AFE7 b .L227 3369 .LVL364: 3370 .L246: 3414:Src/main.c **** } 3371 .loc 1 3414 6 view .LVU1013 3372 010e 0025 movs r5, #0 3373 0110 B5E7 b .L228 3374 .cfi_endproc 3375 .LFE1234: 3377 .section .text.AD9833_WriteWord,"ax",%progbits 3378 .align 1 3379 .syntax unified 3380 .thumb 3381 .thumb_func 3383 AD9833_WriteWord: 3384 .LVL365: 3385 .LFB1214: 2767:Src/main.c **** uint32_t tmp32 = 0; 3386 .loc 1 2767 1 is_stmt 1 view -0 3387 .cfi_startproc 3388 @ args = 0, pretend = 0, frame = 0 3389 @ frame_needed = 0, uses_anonymous_args = 0 2767:Src/main.c **** uint32_t tmp32 = 0; 3390 .loc 1 2767 1 is_stmt 0 view .LVU1015 3391 0000 38B5 push {r3, r4, r5, lr} 3392 .LCFI35: 3393 .cfi_def_cfa_offset 16 3394 .cfi_offset 3, -16 3395 .cfi_offset 4, -12 3396 .cfi_offset 5, -8 3397 .cfi_offset 14, -4 3398 0002 0446 mov r4, r0 2768:Src/main.c **** 3399 .loc 1 2768 2 is_stmt 1 view .LVU1016 3400 .LVL366: 2770:Src/main.c **** 3401 .loc 1 2770 2 view .LVU1017 3402 0004 0021 movs r1, #0 3403 0006 0220 movs r0, #2 3404 .LVL367: 2770:Src/main.c **** 3405 .loc 1 2770 2 is_stmt 0 view .LVU1018 3406 0008 FFF7FEFF bl SPI2_SetMode 3407 .LVL368: 2772:Src/main.c **** HAL_GPIO_WritePin(DAC_LD1_CS_GPIO_Port, DAC_LD1_CS_Pin, GPIO_PIN_SET); 3408 .loc 1 2772 2 is_stmt 1 view .LVU1019 3409 000c 1E4D ldr r5, .L267 3410 000e 0122 movs r2, #1 3411 0010 4FF48051 mov r1, #4096 ARM GAS /tmp/ccLSPxIe.s page 205 3412 0014 2846 mov r0, r5 3413 0016 FFF7FEFF bl HAL_GPIO_WritePin 3414 .LVL369: 2773:Src/main.c **** HAL_GPIO_WritePin(DAC_TEC1_CS_GPIO_Port, DAC_TEC1_CS_Pin, GPIO_PIN_SET); 3415 .loc 1 2773 2 view .LVU1020 3416 001a 0122 movs r2, #1 3417 001c 4FF48041 mov r1, #16384 3418 0020 2846 mov r0, r5 3419 0022 FFF7FEFF bl HAL_GPIO_WritePin 3420 .LVL370: 2774:Src/main.c **** 3421 .loc 1 2774 2 view .LVU1021 3422 0026 05F50065 add r5, r5, #2048 3423 002a 0122 movs r2, #1 3424 002c 4FF48051 mov r1, #4096 3425 0030 2846 mov r0, r5 3426 0032 FFF7FEFF bl HAL_GPIO_WritePin 3427 .LVL371: 2776:Src/main.c **** 3428 .loc 1 2776 2 view .LVU1022 3429 0036 0022 movs r2, #0 3430 0038 4FF40051 mov r1, #8192 3431 003c 2846 mov r0, r5 3432 003e FFF7FEFF bl HAL_GPIO_WritePin 3433 .LVL372: 2778:Src/main.c **** LL_SPI_TransmitData16(SPI2, word); 3434 .loc 1 2778 2 view .LVU1023 2768:Src/main.c **** 3435 .loc 1 2768 11 is_stmt 0 view .LVU1024 3436 0042 0023 movs r3, #0 3437 .LVL373: 3438 .L261: 2778:Src/main.c **** LL_SPI_TransmitData16(SPI2, word); 3439 .loc 1 2778 63 is_stmt 1 discriminator 2 view .LVU1025 2778:Src/main.c **** LL_SPI_TransmitData16(SPI2, word); 3440 .loc 1 2778 41 discriminator 2 view .LVU1026 3441 .LBB427: 3442 .LBI427: 916:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 3443 .loc 4 916 26 view .LVU1027 3444 .LBB428: 918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 3445 .loc 4 918 3 view .LVU1028 918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 3446 .loc 4 918 12 is_stmt 0 view .LVU1029 3447 0044 114A ldr r2, .L267+4 3448 0046 9268 ldr r2, [r2, #8] 918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 3449 .loc 4 918 66 view .LVU1030 3450 0048 12F0020F tst r2, #2 3451 004c 05D1 bne .L260 3452 .LVL374: 918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 3453 .loc 4 918 66 view .LVU1031 3454 .LBE428: 3455 .LBE427: 2778:Src/main.c **** LL_SPI_TransmitData16(SPI2, word); ARM GAS /tmp/ccLSPxIe.s page 206 3456 .loc 1 2778 50 discriminator 1 view .LVU1032 3457 004e 5A1C adds r2, r3, #1 3458 .LVL375: 2778:Src/main.c **** LL_SPI_TransmitData16(SPI2, word); 3459 .loc 1 2778 41 discriminator 1 view .LVU1033 3460 0050 B3F57A7F cmp r3, #1000 3461 0054 01D2 bcs .L260 2778:Src/main.c **** LL_SPI_TransmitData16(SPI2, word); 3462 .loc 1 2778 50 discriminator 1 view .LVU1034 3463 0056 1346 mov r3, r2 3464 0058 F4E7 b .L261 3465 .LVL376: 3466 .L260: 2779:Src/main.c **** tmp32 = 0; 3467 .loc 1 2779 2 is_stmt 1 view .LVU1035 3468 .LBB429: 3469 .LBI429: 1373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 3470 .loc 4 1373 22 view .LVU1036 3471 .LBB430: 1376:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** *spidr = TxData; 3472 .loc 4 1376 3 view .LVU1037 3473 .loc 4 1377 3 view .LVU1038 3474 .loc 4 1377 10 is_stmt 0 view .LVU1039 3475 005a 0C4B ldr r3, .L267+4 3476 005c 9C81 strh r4, [r3, #12] @ movhi 3477 .LVL377: 3478 .loc 4 1377 10 view .LVU1040 3479 .LBE430: 3480 .LBE429: 2780:Src/main.c **** while((!LL_SPI_IsActiveFlag_RXNE(SPI2)) && (tmp32++ < 1000)) {} 3481 .loc 1 2780 2 is_stmt 1 view .LVU1041 2781:Src/main.c **** (void) SPI2->DR; 3482 .loc 1 2781 2 view .LVU1042 2780:Src/main.c **** while((!LL_SPI_IsActiveFlag_RXNE(SPI2)) && (tmp32++ < 1000)) {} 3483 .loc 1 2780 8 is_stmt 0 view .LVU1043 3484 005e 0023 movs r3, #0 3485 .LVL378: 3486 .L263: 2781:Src/main.c **** (void) SPI2->DR; 3487 .loc 1 2781 64 is_stmt 1 discriminator 2 view .LVU1044 2781:Src/main.c **** (void) SPI2->DR; 3488 .loc 1 2781 42 discriminator 2 view .LVU1045 3489 .LBB431: 3490 .LBI431: 905:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 3491 .loc 4 905 26 view .LVU1046 3492 .LBB432: 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 3493 .loc 4 907 3 view .LVU1047 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 3494 .loc 4 907 12 is_stmt 0 view .LVU1048 3495 0060 0A4A ldr r2, .L267+4 3496 0062 9268 ldr r2, [r2, #8] 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 3497 .loc 4 907 68 view .LVU1049 3498 0064 12F0010F tst r2, #1 ARM GAS /tmp/ccLSPxIe.s page 207 3499 0068 05D1 bne .L262 3500 .LVL379: 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 3501 .loc 4 907 68 view .LVU1050 3502 .LBE432: 3503 .LBE431: 2781:Src/main.c **** (void) SPI2->DR; 3504 .loc 1 2781 51 discriminator 1 view .LVU1051 3505 006a 5A1C adds r2, r3, #1 3506 .LVL380: 2781:Src/main.c **** (void) SPI2->DR; 3507 .loc 1 2781 42 discriminator 1 view .LVU1052 3508 006c B3F57A7F cmp r3, #1000 3509 0070 01D2 bcs .L262 2781:Src/main.c **** (void) SPI2->DR; 3510 .loc 1 2781 51 discriminator 1 view .LVU1053 3511 0072 1346 mov r3, r2 3512 0074 F4E7 b .L263 3513 .LVL381: 3514 .L262: 2782:Src/main.c **** 3515 .loc 1 2782 2 is_stmt 1 view .LVU1054 3516 0076 054B ldr r3, .L267+4 3517 0078 DB68 ldr r3, [r3, #12] 2784:Src/main.c **** } 3518 .loc 1 2784 2 view .LVU1055 3519 007a 0122 movs r2, #1 3520 007c 4FF40051 mov r1, #8192 3521 0080 0348 ldr r0, .L267+8 3522 0082 FFF7FEFF bl HAL_GPIO_WritePin 3523 .LVL382: 2785:Src/main.c **** 3524 .loc 1 2785 1 is_stmt 0 view .LVU1056 3525 0086 38BD pop {r3, r4, r5, pc} 3526 .LVL383: 3527 .L268: 2785:Src/main.c **** 3528 .loc 1 2785 1 view .LVU1057 3529 .align 2 3530 .L267: 3531 0088 00040240 .word 1073873920 3532 008c 00380040 .word 1073756160 3533 0090 000C0240 .word 1073875968 3534 .cfi_endproc 3535 .LFE1214: 3537 .section .text.AD9833_Apply,"ax",%progbits 3538 .align 1 3539 .syntax unified 3540 .thumb 3541 .thumb_func 3543 AD9833_Apply: 3544 .LVL384: 3545 .LFB1215: 2788:Src/main.c **** uint16_t control = 0x2000u; // B28 = 1 3546 .loc 1 2788 1 is_stmt 1 view -0 3547 .cfi_startproc 3548 @ args = 0, pretend = 0, frame = 0 ARM GAS /tmp/ccLSPxIe.s page 208 3549 @ frame_needed = 0, uses_anonymous_args = 0 2788:Src/main.c **** uint16_t control = 0x2000u; // B28 = 1 3550 .loc 1 2788 1 is_stmt 0 view .LVU1059 3551 0000 2DE9F041 push {r4, r5, r6, r7, r8, lr} 3552 .LCFI36: 3553 .cfi_def_cfa_offset 24 3554 .cfi_offset 4, -24 3555 .cfi_offset 5, -20 3556 .cfi_offset 6, -16 3557 .cfi_offset 7, -12 3558 .cfi_offset 8, -8 3559 .cfi_offset 14, -4 3560 0004 0546 mov r5, r0 2789:Src/main.c **** if (triangle) 3561 .loc 1 2789 2 is_stmt 1 view .LVU1060 3562 .LVL385: 2790:Src/main.c **** { 3563 .loc 1 2790 2 view .LVU1061 2790:Src/main.c **** { 3564 .loc 1 2790 5 is_stmt 0 view .LVU1062 3565 0006 F9B9 cbnz r1, .L272 2789:Src/main.c **** if (triangle) 3566 .loc 1 2789 11 view .LVU1063 3567 0008 4FF40057 mov r7, #8192 3568 .L270: 3569 .LVL386: 2794:Src/main.c **** 3570 .loc 1 2794 2 is_stmt 1 view .LVU1064 2794:Src/main.c **** 3571 .loc 1 2794 10 is_stmt 0 view .LVU1065 3572 000c 47F48078 orr r8, r7, #256 3573 .LVL387: 2796:Src/main.c **** uint16_t lsw = (uint16_t)(0x4000u | (freq_word & 0x3FFFu)); // FREQ0 LSB 3574 .loc 1 2796 2 is_stmt 1 view .LVU1066 2797:Src/main.c **** uint16_t msw = (uint16_t)(0x4000u | ((freq_word >> 14) & 0x3FFFu)); // FREQ0 MSB 3575 .loc 1 2797 2 view .LVU1067 2797:Src/main.c **** uint16_t msw = (uint16_t)(0x4000u | ((freq_word >> 14) & 0x3FFFu)); // FREQ0 MSB 3576 .loc 1 2797 49 is_stmt 0 view .LVU1068 3577 0010 C2F30D06 ubfx r6, r2, #0, #14 2797:Src/main.c **** uint16_t msw = (uint16_t)(0x4000u | ((freq_word >> 14) & 0x3FFFu)); // FREQ0 MSB 3578 .loc 1 2797 11 view .LVU1069 3579 0014 46F48046 orr r6, r6, #16384 3580 .LVL388: 2798:Src/main.c **** 3581 .loc 1 2798 2 is_stmt 1 view .LVU1070 2798:Src/main.c **** 3582 .loc 1 2798 57 is_stmt 0 view .LVU1071 3583 0018 C2F38D32 ubfx r2, r2, #14, #14 3584 .LVL389: 2798:Src/main.c **** 3585 .loc 1 2798 11 view .LVU1072 3586 001c 42F48044 orr r4, r2, #16384 3587 .LVL390: 2800:Src/main.c **** AD9833_WriteWord(lsw); 3588 .loc 1 2800 2 is_stmt 1 view .LVU1073 3589 0020 4046 mov r0, r8 3590 .LVL391: ARM GAS /tmp/ccLSPxIe.s page 209 2800:Src/main.c **** AD9833_WriteWord(lsw); 3591 .loc 1 2800 2 is_stmt 0 view .LVU1074 3592 0022 FFF7FEFF bl AD9833_WriteWord 3593 .LVL392: 2801:Src/main.c **** AD9833_WriteWord(msw); 3594 .loc 1 2801 2 is_stmt 1 view .LVU1075 3595 0026 3046 mov r0, r6 3596 0028 FFF7FEFF bl AD9833_WriteWord 3597 .LVL393: 2802:Src/main.c **** AD9833_WriteWord(0xC000u); // PHASE0 = 0 3598 .loc 1 2802 2 view .LVU1076 3599 002c 2046 mov r0, r4 3600 002e FFF7FEFF bl AD9833_WriteWord 3601 .LVL394: 2803:Src/main.c **** 3602 .loc 1 2803 2 view .LVU1077 3603 0032 4FF44040 mov r0, #49152 3604 0036 FFF7FEFF bl AD9833_WriteWord 3605 .LVL395: 2805:Src/main.c **** { 3606 .loc 1 2805 2 view .LVU1078 2805:Src/main.c **** { 3607 .loc 1 2805 5 is_stmt 0 view .LVU1079 3608 003a 05B9 cbnz r5, .L271 2794:Src/main.c **** 3609 .loc 1 2794 10 view .LVU1080 3610 003c 4746 mov r7, r8 3611 .L271: 3612 .LVL396: 2809:Src/main.c **** } 3613 .loc 1 2809 2 is_stmt 1 view .LVU1081 3614 003e 3846 mov r0, r7 3615 0040 FFF7FEFF bl AD9833_WriteWord 3616 .LVL397: 2810:Src/main.c **** 3617 .loc 1 2810 1 is_stmt 0 view .LVU1082 3618 0044 BDE8F081 pop {r4, r5, r6, r7, r8, pc} 3619 .LVL398: 3620 .L272: 2792:Src/main.c **** } 3621 .loc 1 2792 11 view .LVU1083 3622 0048 42F20207 movw r7, #8194 3623 004c DEE7 b .L270 3624 .cfi_endproc 3625 .LFE1215: 3627 .section .text.OUT_trigger,"ax",%progbits 3628 .align 1 3629 .syntax unified 3630 .thumb 3631 .thumb_func 3633 OUT_trigger: 3634 .LVL399: 3635 .LFB1211: 2684:Src/main.c **** switch (out_n) 3636 .loc 1 2684 1 is_stmt 1 view -0 3637 .cfi_startproc 3638 @ args = 0, pretend = 0, frame = 0 ARM GAS /tmp/ccLSPxIe.s page 210 3639 @ frame_needed = 0, uses_anonymous_args = 0 2684:Src/main.c **** switch (out_n) 3640 .loc 1 2684 1 is_stmt 0 view .LVU1085 3641 0000 10B5 push {r4, lr} 3642 .LCFI37: 3643 .cfi_def_cfa_offset 8 3644 .cfi_offset 4, -8 3645 .cfi_offset 14, -4 2685:Src/main.c **** { 3646 .loc 1 2685 2 is_stmt 1 view .LVU1086 3647 0002 0928 cmp r0, #9 3648 0004 13D8 bhi .L274 3649 0006 DFE800F0 tbb [pc, r0] 3650 .L277: 3651 000a 05 .byte (.L286-.L277)/2 3652 000b 13 .byte (.L285-.L277)/2 3653 000c 21 .byte (.L284-.L277)/2 3654 000d 2F .byte (.L283-.L277)/2 3655 000e 3D .byte (.L282-.L277)/2 3656 000f 4B .byte (.L281-.L277)/2 3657 0010 59 .byte (.L280-.L277)/2 3658 0011 65 .byte (.L279-.L277)/2 3659 0012 71 .byte (.L278-.L277)/2 3660 0013 7D .byte (.L276-.L277)/2 3661 .p2align 1 3662 .L286: 2688:Src/main.c **** HAL_GPIO_WritePin(OUT_0_GPIO_Port, OUT_0_Pin, GPIO_PIN_RESET); 3663 .loc 1 2688 3 view .LVU1087 3664 0014 414C ldr r4, .L289 3665 0016 0122 movs r2, #1 3666 0018 4FF48061 mov r1, #1024 3667 001c 2046 mov r0, r4 3668 .LVL400: 2688:Src/main.c **** HAL_GPIO_WritePin(OUT_0_GPIO_Port, OUT_0_Pin, GPIO_PIN_RESET); 3669 .loc 1 2688 3 is_stmt 0 view .LVU1088 3670 001e FFF7FEFF bl HAL_GPIO_WritePin 3671 .LVL401: 2689:Src/main.c **** break; 3672 .loc 1 2689 3 is_stmt 1 view .LVU1089 3673 0022 0022 movs r2, #0 3674 0024 4FF48061 mov r1, #1024 3675 0028 2046 mov r0, r4 3676 002a FFF7FEFF bl HAL_GPIO_WritePin 3677 .LVL402: 2690:Src/main.c **** 3678 .loc 1 2690 2 view .LVU1090 3679 .L274: 2737:Src/main.c **** 3680 .loc 1 2737 1 is_stmt 0 view .LVU1091 3681 002e 10BD pop {r4, pc} 3682 .LVL403: 3683 .L285: 2693:Src/main.c **** HAL_GPIO_WritePin(OUT_1_GPIO_Port, OUT_1_Pin, GPIO_PIN_RESET); 3684 .loc 1 2693 3 is_stmt 1 view .LVU1092 3685 0030 3A4C ldr r4, .L289 3686 0032 0122 movs r2, #1 3687 0034 4FF40061 mov r1, #2048 ARM GAS /tmp/ccLSPxIe.s page 211 3688 0038 2046 mov r0, r4 3689 .LVL404: 2693:Src/main.c **** HAL_GPIO_WritePin(OUT_1_GPIO_Port, OUT_1_Pin, GPIO_PIN_RESET); 3690 .loc 1 2693 3 is_stmt 0 view .LVU1093 3691 003a FFF7FEFF bl HAL_GPIO_WritePin 3692 .LVL405: 2694:Src/main.c **** break; 3693 .loc 1 2694 3 is_stmt 1 view .LVU1094 3694 003e 0022 movs r2, #0 3695 0040 4FF40061 mov r1, #2048 3696 0044 2046 mov r0, r4 3697 0046 FFF7FEFF bl HAL_GPIO_WritePin 3698 .LVL406: 2695:Src/main.c **** 3699 .loc 1 2695 2 view .LVU1095 3700 004a F0E7 b .L274 3701 .LVL407: 3702 .L284: 2698:Src/main.c **** HAL_GPIO_WritePin(OUT_2_GPIO_Port, OUT_2_Pin, GPIO_PIN_RESET); 3703 .loc 1 2698 3 view .LVU1096 3704 004c 334C ldr r4, .L289 3705 004e 0122 movs r2, #1 3706 0050 4FF48051 mov r1, #4096 3707 0054 2046 mov r0, r4 3708 .LVL408: 2698:Src/main.c **** HAL_GPIO_WritePin(OUT_2_GPIO_Port, OUT_2_Pin, GPIO_PIN_RESET); 3709 .loc 1 2698 3 is_stmt 0 view .LVU1097 3710 0056 FFF7FEFF bl HAL_GPIO_WritePin 3711 .LVL409: 2699:Src/main.c **** break; 3712 .loc 1 2699 3 is_stmt 1 view .LVU1098 3713 005a 0022 movs r2, #0 3714 005c 4FF48051 mov r1, #4096 3715 0060 2046 mov r0, r4 3716 0062 FFF7FEFF bl HAL_GPIO_WritePin 3717 .LVL410: 2700:Src/main.c **** 3718 .loc 1 2700 2 view .LVU1099 3719 0066 E2E7 b .L274 3720 .LVL411: 3721 .L283: 2703:Src/main.c **** HAL_GPIO_WritePin(OUT_3_GPIO_Port, OUT_3_Pin, GPIO_PIN_RESET); 3722 .loc 1 2703 3 view .LVU1100 3723 0068 2C4C ldr r4, .L289 3724 006a 0122 movs r2, #1 3725 006c 4FF40051 mov r1, #8192 3726 0070 2046 mov r0, r4 3727 .LVL412: 2703:Src/main.c **** HAL_GPIO_WritePin(OUT_3_GPIO_Port, OUT_3_Pin, GPIO_PIN_RESET); 3728 .loc 1 2703 3 is_stmt 0 view .LVU1101 3729 0072 FFF7FEFF bl HAL_GPIO_WritePin 3730 .LVL413: 2704:Src/main.c **** break; 3731 .loc 1 2704 3 is_stmt 1 view .LVU1102 3732 0076 0022 movs r2, #0 3733 0078 4FF40051 mov r1, #8192 3734 007c 2046 mov r0, r4 ARM GAS /tmp/ccLSPxIe.s page 212 3735 007e FFF7FEFF bl HAL_GPIO_WritePin 3736 .LVL414: 2705:Src/main.c **** 3737 .loc 1 2705 2 view .LVU1103 3738 0082 D4E7 b .L274 3739 .LVL415: 3740 .L282: 2708:Src/main.c **** HAL_GPIO_WritePin(OUT_4_GPIO_Port, OUT_4_Pin, GPIO_PIN_RESET); 3741 .loc 1 2708 3 view .LVU1104 3742 0084 254C ldr r4, .L289 3743 0086 0122 movs r2, #1 3744 0088 4FF48041 mov r1, #16384 3745 008c 2046 mov r0, r4 3746 .LVL416: 2708:Src/main.c **** HAL_GPIO_WritePin(OUT_4_GPIO_Port, OUT_4_Pin, GPIO_PIN_RESET); 3747 .loc 1 2708 3 is_stmt 0 view .LVU1105 3748 008e FFF7FEFF bl HAL_GPIO_WritePin 3749 .LVL417: 2709:Src/main.c **** break; 3750 .loc 1 2709 3 is_stmt 1 view .LVU1106 3751 0092 0022 movs r2, #0 3752 0094 4FF48041 mov r1, #16384 3753 0098 2046 mov r0, r4 3754 009a FFF7FEFF bl HAL_GPIO_WritePin 3755 .LVL418: 2710:Src/main.c **** 3756 .loc 1 2710 2 view .LVU1107 3757 009e C6E7 b .L274 3758 .LVL419: 3759 .L281: 2713:Src/main.c **** HAL_GPIO_WritePin(OUT_5_GPIO_Port, OUT_5_Pin, GPIO_PIN_RESET); 3760 .loc 1 2713 3 view .LVU1108 3761 00a0 1E4C ldr r4, .L289 3762 00a2 0122 movs r2, #1 3763 00a4 4FF40041 mov r1, #32768 3764 00a8 2046 mov r0, r4 3765 .LVL420: 2713:Src/main.c **** HAL_GPIO_WritePin(OUT_5_GPIO_Port, OUT_5_Pin, GPIO_PIN_RESET); 3766 .loc 1 2713 3 is_stmt 0 view .LVU1109 3767 00aa FFF7FEFF bl HAL_GPIO_WritePin 3768 .LVL421: 2714:Src/main.c **** break; 3769 .loc 1 2714 3 is_stmt 1 view .LVU1110 3770 00ae 0022 movs r2, #0 3771 00b0 4FF40041 mov r1, #32768 3772 00b4 2046 mov r0, r4 3773 00b6 FFF7FEFF bl HAL_GPIO_WritePin 3774 .LVL422: 2715:Src/main.c **** 3775 .loc 1 2715 2 view .LVU1111 3776 00ba B8E7 b .L274 3777 .LVL423: 3778 .L280: 2718:Src/main.c **** HAL_GPIO_WritePin(OUT_6_GPIO_Port, OUT_6_Pin, GPIO_PIN_RESET); 3779 .loc 1 2718 3 view .LVU1112 3780 00bc 184C ldr r4, .L289+4 3781 00be 0122 movs r2, #1 ARM GAS /tmp/ccLSPxIe.s page 213 3782 00c0 1021 movs r1, #16 3783 00c2 2046 mov r0, r4 3784 .LVL424: 2718:Src/main.c **** HAL_GPIO_WritePin(OUT_6_GPIO_Port, OUT_6_Pin, GPIO_PIN_RESET); 3785 .loc 1 2718 3 is_stmt 0 view .LVU1113 3786 00c4 FFF7FEFF bl HAL_GPIO_WritePin 3787 .LVL425: 2719:Src/main.c **** break; 3788 .loc 1 2719 3 is_stmt 1 view .LVU1114 3789 00c8 0022 movs r2, #0 3790 00ca 1021 movs r1, #16 3791 00cc 2046 mov r0, r4 3792 00ce FFF7FEFF bl HAL_GPIO_WritePin 3793 .LVL426: 2720:Src/main.c **** 3794 .loc 1 2720 2 view .LVU1115 3795 00d2 ACE7 b .L274 3796 .LVL427: 3797 .L279: 2723:Src/main.c **** HAL_GPIO_WritePin(OUT_7_GPIO_Port, OUT_7_Pin, GPIO_PIN_RESET); 3798 .loc 1 2723 3 view .LVU1116 3799 00d4 124C ldr r4, .L289+4 3800 00d6 0122 movs r2, #1 3801 00d8 2021 movs r1, #32 3802 00da 2046 mov r0, r4 3803 .LVL428: 2723:Src/main.c **** HAL_GPIO_WritePin(OUT_7_GPIO_Port, OUT_7_Pin, GPIO_PIN_RESET); 3804 .loc 1 2723 3 is_stmt 0 view .LVU1117 3805 00dc FFF7FEFF bl HAL_GPIO_WritePin 3806 .LVL429: 2724:Src/main.c **** break; 3807 .loc 1 2724 3 is_stmt 1 view .LVU1118 3808 00e0 0022 movs r2, #0 3809 00e2 2021 movs r1, #32 3810 00e4 2046 mov r0, r4 3811 00e6 FFF7FEFF bl HAL_GPIO_WritePin 3812 .LVL430: 2725:Src/main.c **** 3813 .loc 1 2725 2 view .LVU1119 3814 00ea A0E7 b .L274 3815 .LVL431: 3816 .L278: 2728:Src/main.c **** HAL_GPIO_WritePin(OUT_8_GPIO_Port, OUT_8_Pin, GPIO_PIN_RESET); 3817 .loc 1 2728 3 view .LVU1120 3818 00ec 0C4C ldr r4, .L289+4 3819 00ee 0122 movs r2, #1 3820 00f0 4021 movs r1, #64 3821 00f2 2046 mov r0, r4 3822 .LVL432: 2728:Src/main.c **** HAL_GPIO_WritePin(OUT_8_GPIO_Port, OUT_8_Pin, GPIO_PIN_RESET); 3823 .loc 1 2728 3 is_stmt 0 view .LVU1121 3824 00f4 FFF7FEFF bl HAL_GPIO_WritePin 3825 .LVL433: 2729:Src/main.c **** break; 3826 .loc 1 2729 3 is_stmt 1 view .LVU1122 3827 00f8 0022 movs r2, #0 3828 00fa 4021 movs r1, #64 ARM GAS /tmp/ccLSPxIe.s page 214 3829 00fc 2046 mov r0, r4 3830 00fe FFF7FEFF bl HAL_GPIO_WritePin 3831 .LVL434: 2730:Src/main.c **** 3832 .loc 1 2730 2 view .LVU1123 3833 0102 94E7 b .L274 3834 .LVL435: 3835 .L276: 2733:Src/main.c **** HAL_GPIO_WritePin(OUT_9_GPIO_Port, OUT_9_Pin, GPIO_PIN_RESET); 3836 .loc 1 2733 3 view .LVU1124 3837 0104 064C ldr r4, .L289+4 3838 0106 0122 movs r2, #1 3839 0108 8021 movs r1, #128 3840 010a 2046 mov r0, r4 3841 .LVL436: 2733:Src/main.c **** HAL_GPIO_WritePin(OUT_9_GPIO_Port, OUT_9_Pin, GPIO_PIN_RESET); 3842 .loc 1 2733 3 is_stmt 0 view .LVU1125 3843 010c FFF7FEFF bl HAL_GPIO_WritePin 3844 .LVL437: 2734:Src/main.c **** break; 3845 .loc 1 2734 3 is_stmt 1 view .LVU1126 3846 0110 0022 movs r2, #0 3847 0112 8021 movs r1, #128 3848 0114 2046 mov r0, r4 3849 0116 FFF7FEFF bl HAL_GPIO_WritePin 3850 .LVL438: 2735:Src/main.c **** } 3851 .loc 1 2735 2 view .LVU1127 2737:Src/main.c **** 3852 .loc 1 2737 1 is_stmt 0 view .LVU1128 3853 011a 88E7 b .L274 3854 .L290: 3855 .align 2 3856 .L289: 3857 011c 00180240 .word 1073879040 3858 0120 00040240 .word 1073873920 3859 .cfi_endproc 3860 .LFE1211: 3862 .section .text.MPhD_T,"ax",%progbits 3863 .align 1 3864 .syntax unified 3865 .thumb 3866 .thumb_func 3868 MPhD_T: 3869 .LVL439: 3870 .LFB1236: 3529:Src/main.c **** uint16_t P; 3871 .loc 1 3529 1 is_stmt 1 view -0 3872 .cfi_startproc 3873 @ args = 0, pretend = 0, frame = 0 3874 @ frame_needed = 0, uses_anonymous_args = 0 3529:Src/main.c **** uint16_t P; 3875 .loc 1 3529 1 is_stmt 0 view .LVU1130 3876 0000 38B5 push {r3, r4, r5, lr} 3877 .LCFI38: 3878 .cfi_def_cfa_offset 16 3879 .cfi_offset 3, -16 ARM GAS /tmp/ccLSPxIe.s page 215 3880 .cfi_offset 4, -12 3881 .cfi_offset 5, -8 3882 .cfi_offset 14, -4 3883 0002 0446 mov r4, r0 3530:Src/main.c **** uint32_t tmp32; 3884 .loc 1 3530 2 is_stmt 1 view .LVU1131 3531:Src/main.c **** HAL_GPIO_WritePin(SPI4_CNV_GPIO_Port, SPI4_CNV_Pin, GPIO_PIN_RESET);//Prepare conversion 3885 .loc 1 3531 2 view .LVU1132 3532:Src/main.c **** HAL_GPIO_WritePin(SPI5_CNV_GPIO_Port, SPI5_CNV_Pin, GPIO_PIN_RESET);//Prepare conversion 3886 .loc 1 3532 2 view .LVU1133 3887 0004 0022 movs r2, #0 3888 0006 4FF48041 mov r1, #16384 3889 000a 8148 ldr r0, .L332 3890 .LVL440: 3532:Src/main.c **** HAL_GPIO_WritePin(SPI5_CNV_GPIO_Port, SPI5_CNV_Pin, GPIO_PIN_RESET);//Prepare conversion 3891 .loc 1 3532 2 is_stmt 0 view .LVU1134 3892 000c FFF7FEFF bl HAL_GPIO_WritePin 3893 .LVL441: 3533:Src/main.c **** tmp32=0; 3894 .loc 1 3533 2 is_stmt 1 view .LVU1135 3895 0010 0022 movs r2, #0 3896 0012 4FF40071 mov r1, #512 3897 0016 7F48 ldr r0, .L332+4 3898 0018 FFF7FEFF bl HAL_GPIO_WritePin 3899 .LVL442: 3534:Src/main.c **** while(tmp32<500){tmp32++;} 3900 .loc 1 3534 2 view .LVU1136 3535:Src/main.c **** HAL_GPIO_WritePin(SPI4_CNV_GPIO_Port, SPI4_CNV_Pin, GPIO_PIN_SET);//Stop acqusition & start conver 3901 .loc 1 3535 2 view .LVU1137 3534:Src/main.c **** while(tmp32<500){tmp32++;} 3902 .loc 1 3534 7 is_stmt 0 view .LVU1138 3903 001c 0023 movs r3, #0 3535:Src/main.c **** HAL_GPIO_WritePin(SPI4_CNV_GPIO_Port, SPI4_CNV_Pin, GPIO_PIN_SET);//Stop acqusition & start conver 3904 .loc 1 3535 7 view .LVU1139 3905 001e 00E0 b .L292 3906 .LVL443: 3907 .L293: 3535:Src/main.c **** HAL_GPIO_WritePin(SPI4_CNV_GPIO_Port, SPI4_CNV_Pin, GPIO_PIN_SET);//Stop acqusition & start conver 3908 .loc 1 3535 19 is_stmt 1 discriminator 2 view .LVU1140 3535:Src/main.c **** HAL_GPIO_WritePin(SPI4_CNV_GPIO_Port, SPI4_CNV_Pin, GPIO_PIN_SET);//Stop acqusition & start conver 3909 .loc 1 3535 24 is_stmt 0 discriminator 2 view .LVU1141 3910 0020 0133 adds r3, r3, #1 3911 .LVL444: 3912 .L292: 3535:Src/main.c **** HAL_GPIO_WritePin(SPI4_CNV_GPIO_Port, SPI4_CNV_Pin, GPIO_PIN_SET);//Stop acqusition & start conver 3913 .loc 1 3535 13 is_stmt 1 discriminator 1 view .LVU1142 3914 0022 B3F5FA7F cmp r3, #500 3915 0026 FBD3 bcc .L293 3536:Src/main.c **** HAL_GPIO_WritePin(SPI5_CNV_GPIO_Port, SPI5_CNV_Pin, GPIO_PIN_SET);//Stop acqusition & start conver 3916 .loc 1 3536 2 view .LVU1143 3917 0028 0122 movs r2, #1 3918 002a 4FF48041 mov r1, #16384 3919 002e 7848 ldr r0, .L332 3920 0030 FFF7FEFF bl HAL_GPIO_WritePin 3921 .LVL445: 3537:Src/main.c **** tmp32=0; 3922 .loc 1 3537 2 view .LVU1144 ARM GAS /tmp/ccLSPxIe.s page 216 3923 0034 0122 movs r2, #1 3924 0036 4FF40071 mov r1, #512 3925 003a 7648 ldr r0, .L332+4 3926 003c FFF7FEFF bl HAL_GPIO_WritePin 3927 .LVL446: 3538:Src/main.c **** while(tmp32<500){tmp32++;} 3928 .loc 1 3538 2 view .LVU1145 3539:Src/main.c **** if (num==1)//MPD1 3929 .loc 1 3539 2 view .LVU1146 3538:Src/main.c **** while(tmp32<500){tmp32++;} 3930 .loc 1 3538 7 is_stmt 0 view .LVU1147 3931 0040 0023 movs r3, #0 3539:Src/main.c **** if (num==1)//MPD1 3932 .loc 1 3539 7 view .LVU1148 3933 0042 00E0 b .L294 3934 .LVL447: 3935 .L295: 3539:Src/main.c **** if (num==1)//MPD1 3936 .loc 1 3539 19 is_stmt 1 discriminator 2 view .LVU1149 3539:Src/main.c **** if (num==1)//MPD1 3937 .loc 1 3539 24 is_stmt 0 discriminator 2 view .LVU1150 3938 0044 0133 adds r3, r3, #1 3939 .LVL448: 3940 .L294: 3539:Src/main.c **** if (num==1)//MPD1 3941 .loc 1 3539 13 is_stmt 1 discriminator 1 view .LVU1151 3942 0046 B3F5FA7F cmp r3, #500 3943 004a FBD3 bcc .L295 3540:Src/main.c **** { 3944 .loc 1 3540 2 view .LVU1152 3945 004c 631E subs r3, r4, #1 3946 .LVL449: 3540:Src/main.c **** { 3947 .loc 1 3540 2 is_stmt 0 view .LVU1153 3948 004e 032B cmp r3, #3 3949 0050 39D8 bhi .L296 3950 0052 DFE803F0 tbb [pc, r3] 3951 .L298: 3952 0056 02 .byte (.L301-.L298)/2 3953 0057 3A .byte (.L300-.L298)/2 3954 0058 6F .byte (.L299-.L298)/2 3955 0059 A6 .byte (.L297-.L298)/2 3956 .p2align 1 3957 .L301: 3542:Src/main.c **** HAL_GPIO_WritePin(ADC_MPD1_CS_GPIO_Port, ADC_MPD1_CS_Pin, GPIO_PIN_RESET); 3958 .loc 1 3542 3 is_stmt 1 view .LVU1154 3959 005a 6D4C ldr r4, .L332 3960 .LVL450: 3542:Src/main.c **** HAL_GPIO_WritePin(ADC_MPD1_CS_GPIO_Port, ADC_MPD1_CS_Pin, GPIO_PIN_RESET); 3961 .loc 1 3542 3 is_stmt 0 view .LVU1155 3962 005c 0122 movs r2, #1 3963 005e 4FF40061 mov r1, #2048 3964 0062 2046 mov r0, r4 3965 0064 FFF7FEFF bl HAL_GPIO_WritePin 3966 .LVL451: 3543:Src/main.c **** tmp32=0; 3967 .loc 1 3543 3 is_stmt 1 view .LVU1156 ARM GAS /tmp/ccLSPxIe.s page 217 3968 0068 0022 movs r2, #0 3969 006a 4FF48061 mov r1, #1024 3970 006e 2046 mov r0, r4 3971 0070 FFF7FEFF bl HAL_GPIO_WritePin 3972 .LVL452: 3544:Src/main.c **** while(tmp32<500){tmp32++;} 3973 .loc 1 3544 3 view .LVU1157 3545:Src/main.c **** //LL_SPI_TransmitData16(SPI4, 0xFFFF);//We must to clock the CLK output for collect RX data. We c 3974 .loc 1 3545 3 view .LVU1158 3544:Src/main.c **** while(tmp32<500){tmp32++;} 3975 .loc 1 3544 8 is_stmt 0 view .LVU1159 3976 0074 0023 movs r3, #0 3545:Src/main.c **** //LL_SPI_TransmitData16(SPI4, 0xFFFF);//We must to clock the CLK output for collect RX data. We c 3977 .loc 1 3545 8 view .LVU1160 3978 0076 00E0 b .L302 3979 .LVL453: 3980 .L303: 3545:Src/main.c **** //LL_SPI_TransmitData16(SPI4, 0xFFFF);//We must to clock the CLK output for collect RX data. We c 3981 .loc 1 3545 20 is_stmt 1 discriminator 2 view .LVU1161 3545:Src/main.c **** //LL_SPI_TransmitData16(SPI4, 0xFFFF);//We must to clock the CLK output for collect RX data. We c 3982 .loc 1 3545 25 is_stmt 0 discriminator 2 view .LVU1162 3983 0078 0133 adds r3, r3, #1 3984 .LVL454: 3985 .L302: 3545:Src/main.c **** //LL_SPI_TransmitData16(SPI4, 0xFFFF);//We must to clock the CLK output for collect RX data. We c 3986 .loc 1 3545 14 is_stmt 1 discriminator 1 view .LVU1163 3987 007a B3F5FA7F cmp r3, #500 3988 007e FBD3 bcc .L303 3547:Src/main.c **** tmp32 = 0; 3989 .loc 1 3547 3 view .LVU1164 3990 .LVL455: 3991 .LBB433: 3992 .LBI433: 358:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 3993 .loc 4 358 22 view .LVU1165 3994 .LBB434: 360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 3995 .loc 4 360 3 view .LVU1166 3996 0080 654A ldr r2, .L332+8 3997 0082 1368 ldr r3, [r2] 3998 .LVL456: 360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 3999 .loc 4 360 3 is_stmt 0 view .LVU1167 4000 0084 43F04003 orr r3, r3, #64 4001 0088 1360 str r3, [r2] 4002 .LVL457: 360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 4003 .loc 4 360 3 view .LVU1168 4004 .LBE434: 4005 .LBE433: 3548:Src/main.c **** while(((!LL_SPI_IsActiveFlag_RXNE(SPI4))&&(tmp32<=1000))) {tmp32++;}//When rec. last data cycle w 4006 .loc 1 3548 3 is_stmt 1 view .LVU1169 3549:Src/main.c **** LL_SPI_Disable(SPI4);//Enable SPI for MPhD1 ADC 4007 .loc 1 3549 3 view .LVU1170 3548:Src/main.c **** while(((!LL_SPI_IsActiveFlag_RXNE(SPI4))&&(tmp32<=1000))) {tmp32++;}//When rec. last data cycle w 4008 .loc 1 3548 9 is_stmt 0 view .LVU1171 4009 008a 0023 movs r3, #0 ARM GAS /tmp/ccLSPxIe.s page 218 4010 .LVL458: 4011 .L304: 3549:Src/main.c **** LL_SPI_Disable(SPI4);//Enable SPI for MPhD1 ADC 4012 .loc 1 3549 43 is_stmt 1 discriminator 1 view .LVU1172 4013 .LBB435: 4014 .LBI435: 905:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 4015 .loc 4 905 26 view .LVU1173 4016 .LBB436: 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 4017 .loc 4 907 3 view .LVU1174 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 4018 .loc 4 907 12 is_stmt 0 view .LVU1175 4019 008c 624A ldr r2, .L332+8 4020 008e 9268 ldr r2, [r2, #8] 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 4021 .loc 4 907 68 view .LVU1176 4022 0090 12F0010F tst r2, #1 4023 0094 04D1 bne .L305 4024 .LVL459: 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 4025 .loc 4 907 68 view .LVU1177 4026 .LBE436: 4027 .LBE435: 3549:Src/main.c **** LL_SPI_Disable(SPI4);//Enable SPI for MPhD1 ADC 4028 .loc 1 3549 43 discriminator 2 view .LVU1178 4029 0096 B3F57A7F cmp r3, #1000 4030 009a 01D8 bhi .L305 3549:Src/main.c **** LL_SPI_Disable(SPI4);//Enable SPI for MPhD1 ADC 4031 .loc 1 3549 62 is_stmt 1 discriminator 3 view .LVU1179 3549:Src/main.c **** LL_SPI_Disable(SPI4);//Enable SPI for MPhD1 ADC 4032 .loc 1 3549 67 is_stmt 0 discriminator 3 view .LVU1180 4033 009c 0133 adds r3, r3, #1 4034 .LVL460: 3549:Src/main.c **** LL_SPI_Disable(SPI4);//Enable SPI for MPhD1 ADC 4035 .loc 1 3549 67 discriminator 3 view .LVU1181 4036 009e F5E7 b .L304 4037 .L305: 3550:Src/main.c **** while(tmp32<500){tmp32++;} 4038 .loc 1 3550 3 is_stmt 1 view .LVU1182 4039 .LVL461: 4040 .LBB437: 4041 .LBI437: 370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 4042 .loc 4 370 22 view .LVU1183 4043 .LBB438: 372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 4044 .loc 4 372 3 view .LVU1184 4045 00a0 5D49 ldr r1, .L332+8 4046 00a2 0A68 ldr r2, [r1] 4047 00a4 22F04002 bic r2, r2, #64 4048 00a8 0A60 str r2, [r1] 4049 .LVL462: 372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 4050 .loc 4 372 3 is_stmt 0 view .LVU1185 4051 .LBE438: 4052 .LBE437: ARM GAS /tmp/ccLSPxIe.s page 219 3551:Src/main.c **** //HAL_SPI_Receive(&hspi4, &P[0], 1, 100); 4053 .loc 1 3551 3 is_stmt 1 view .LVU1186 4054 .LBB440: 4055 .LBB439: 373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 4056 .loc 4 373 1 is_stmt 0 view .LVU1187 4057 00aa 00E0 b .L307 4058 .L308: 373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 4059 .loc 4 373 1 view .LVU1188 4060 .LBE439: 4061 .LBE440: 3551:Src/main.c **** //HAL_SPI_Receive(&hspi4, &P[0], 1, 100); 4062 .loc 1 3551 20 is_stmt 1 discriminator 2 view .LVU1189 3551:Src/main.c **** //HAL_SPI_Receive(&hspi4, &P[0], 1, 100); 4063 .loc 1 3551 25 is_stmt 0 discriminator 2 view .LVU1190 4064 00ac 0133 adds r3, r3, #1 4065 .LVL463: 4066 .L307: 3551:Src/main.c **** //HAL_SPI_Receive(&hspi4, &P[0], 1, 100); 4067 .loc 1 3551 14 is_stmt 1 discriminator 1 view .LVU1191 4068 00ae B3F5FA7F cmp r3, #500 4069 00b2 FBD3 bcc .L308 3553:Src/main.c **** P = LL_SPI_ReceiveData16(SPI4); 4070 .loc 1 3553 3 view .LVU1192 4071 00b4 0122 movs r2, #1 4072 00b6 4FF48061 mov r1, #1024 4073 00ba 5548 ldr r0, .L332 4074 00bc FFF7FEFF bl HAL_GPIO_WritePin 4075 .LVL464: 3554:Src/main.c **** } 4076 .loc 1 3554 3 view .LVU1193 4077 .LBB441: 4078 .LBI441: 1344:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 4079 .loc 4 1344 26 view .LVU1194 4080 .LBB442: 1346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 4081 .loc 4 1346 3 view .LVU1195 1346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 4082 .loc 4 1346 21 is_stmt 0 view .LVU1196 4083 00c0 554B ldr r3, .L332+8 4084 00c2 DD68 ldr r5, [r3, #12] 1346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 4085 .loc 4 1346 10 view .LVU1197 4086 00c4 ADB2 uxth r5, r5 4087 .LVL465: 4088 .L296: 1346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 4089 .loc 4 1346 10 view .LVU1198 4090 .LBE442: 4091 .LBE441: 3626:Src/main.c **** } 4092 .loc 1 3626 2 is_stmt 1 view .LVU1199 3627:Src/main.c **** /*static uint16_t Temp_LD(uint16_t T_LD_before, uint16_t T_LD, uint32_t Timer_before, uint32_t Time 4093 .loc 1 3627 1 is_stmt 0 view .LVU1200 4094 00c6 2846 mov r0, r5 ARM GAS /tmp/ccLSPxIe.s page 220 4095 00c8 38BD pop {r3, r4, r5, pc} 4096 .LVL466: 4097 .L300: 3558:Src/main.c **** HAL_GPIO_WritePin(ADC_MPD2_CS_GPIO_Port, ADC_MPD2_CS_Pin, GPIO_PIN_RESET); 4098 .loc 1 3558 3 is_stmt 1 view .LVU1201 4099 00ca 524C ldr r4, .L332+4 4100 00cc 0122 movs r2, #1 4101 00ce 4FF48061 mov r1, #1024 4102 00d2 2046 mov r0, r4 4103 00d4 FFF7FEFF bl HAL_GPIO_WritePin 4104 .LVL467: 3559:Src/main.c **** tmp32=0; 4105 .loc 1 3559 3 view .LVU1202 4106 00d8 0022 movs r2, #0 4107 00da 4021 movs r1, #64 4108 00dc 2046 mov r0, r4 4109 00de FFF7FEFF bl HAL_GPIO_WritePin 4110 .LVL468: 3560:Src/main.c **** while(tmp32<500){tmp32++;} 4111 .loc 1 3560 3 view .LVU1203 3561:Src/main.c **** //LL_SPI_TransmitData16(SPI5, 0xFFFF);//We must to clock the CLK output for collect RX data. We c 4112 .loc 1 3561 3 view .LVU1204 3560:Src/main.c **** while(tmp32<500){tmp32++;} 4113 .loc 1 3560 8 is_stmt 0 view .LVU1205 4114 00e2 0023 movs r3, #0 3561:Src/main.c **** //LL_SPI_TransmitData16(SPI5, 0xFFFF);//We must to clock the CLK output for collect RX data. We c 4115 .loc 1 3561 8 view .LVU1206 4116 00e4 00E0 b .L309 4117 .LVL469: 4118 .L310: 3561:Src/main.c **** //LL_SPI_TransmitData16(SPI5, 0xFFFF);//We must to clock the CLK output for collect RX data. We c 4119 .loc 1 3561 20 is_stmt 1 discriminator 2 view .LVU1207 3561:Src/main.c **** //LL_SPI_TransmitData16(SPI5, 0xFFFF);//We must to clock the CLK output for collect RX data. We c 4120 .loc 1 3561 25 is_stmt 0 discriminator 2 view .LVU1208 4121 00e6 0133 adds r3, r3, #1 4122 .LVL470: 4123 .L309: 3561:Src/main.c **** //LL_SPI_TransmitData16(SPI5, 0xFFFF);//We must to clock the CLK output for collect RX data. We c 4124 .loc 1 3561 14 is_stmt 1 discriminator 1 view .LVU1209 4125 00e8 B3F5FA7F cmp r3, #500 4126 00ec FBD3 bcc .L310 3563:Src/main.c **** tmp32 = 0; 4127 .loc 1 3563 3 view .LVU1210 4128 .LVL471: 4129 .LBB443: 4130 .LBI443: 358:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 4131 .loc 4 358 22 view .LVU1211 4132 .LBB444: 360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 4133 .loc 4 360 3 view .LVU1212 4134 00ee 4B4A ldr r2, .L332+12 4135 00f0 1368 ldr r3, [r2] 4136 .LVL472: 360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 4137 .loc 4 360 3 is_stmt 0 view .LVU1213 4138 00f2 43F04003 orr r3, r3, #64 ARM GAS /tmp/ccLSPxIe.s page 221 4139 00f6 1360 str r3, [r2] 4140 .LVL473: 360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 4141 .loc 4 360 3 view .LVU1214 4142 .LBE444: 4143 .LBE443: 3564:Src/main.c **** while(((!LL_SPI_IsActiveFlag_RXNE(SPI5))&&(tmp32<=1000))) {tmp32++;}//When rec. last data cycle w 4144 .loc 1 3564 3 is_stmt 1 view .LVU1215 3565:Src/main.c **** LL_SPI_Disable(SPI5);//Enable SPI for MPhD2 ADC 4145 .loc 1 3565 3 view .LVU1216 3564:Src/main.c **** while(((!LL_SPI_IsActiveFlag_RXNE(SPI5))&&(tmp32<=1000))) {tmp32++;}//When rec. last data cycle w 4146 .loc 1 3564 9 is_stmt 0 view .LVU1217 4147 00f8 0023 movs r3, #0 4148 .LVL474: 4149 .L311: 3565:Src/main.c **** LL_SPI_Disable(SPI5);//Enable SPI for MPhD2 ADC 4150 .loc 1 3565 43 is_stmt 1 discriminator 1 view .LVU1218 4151 .LBB445: 4152 .LBI445: 905:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 4153 .loc 4 905 26 view .LVU1219 4154 .LBB446: 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 4155 .loc 4 907 3 view .LVU1220 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 4156 .loc 4 907 12 is_stmt 0 view .LVU1221 4157 00fa 484A ldr r2, .L332+12 4158 00fc 9268 ldr r2, [r2, #8] 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 4159 .loc 4 907 68 view .LVU1222 4160 00fe 12F0010F tst r2, #1 4161 0102 04D1 bne .L312 4162 .LVL475: 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 4163 .loc 4 907 68 view .LVU1223 4164 .LBE446: 4165 .LBE445: 3565:Src/main.c **** LL_SPI_Disable(SPI5);//Enable SPI for MPhD2 ADC 4166 .loc 1 3565 43 discriminator 2 view .LVU1224 4167 0104 B3F57A7F cmp r3, #1000 4168 0108 01D8 bhi .L312 3565:Src/main.c **** LL_SPI_Disable(SPI5);//Enable SPI for MPhD2 ADC 4169 .loc 1 3565 62 is_stmt 1 discriminator 3 view .LVU1225 3565:Src/main.c **** LL_SPI_Disable(SPI5);//Enable SPI for MPhD2 ADC 4170 .loc 1 3565 67 is_stmt 0 discriminator 3 view .LVU1226 4171 010a 0133 adds r3, r3, #1 4172 .LVL476: 3565:Src/main.c **** LL_SPI_Disable(SPI5);//Enable SPI for MPhD2 ADC 4173 .loc 1 3565 67 discriminator 3 view .LVU1227 4174 010c F5E7 b .L311 4175 .L312: 3566:Src/main.c **** while(tmp32<500){tmp32++;} 4176 .loc 1 3566 3 is_stmt 1 view .LVU1228 4177 .LVL477: 4178 .LBB447: 4179 .LBI447: 370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { ARM GAS /tmp/ccLSPxIe.s page 222 4180 .loc 4 370 22 view .LVU1229 4181 .LBB448: 372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 4182 .loc 4 372 3 view .LVU1230 4183 010e 4349 ldr r1, .L332+12 4184 0110 0A68 ldr r2, [r1] 4185 0112 22F04002 bic r2, r2, #64 4186 0116 0A60 str r2, [r1] 4187 .LVL478: 372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 4188 .loc 4 372 3 is_stmt 0 view .LVU1231 4189 .LBE448: 4190 .LBE447: 3567:Src/main.c **** //HAL_SPI_Receive(&hspi4, &P[0], 1, 100); 4191 .loc 1 3567 3 is_stmt 1 view .LVU1232 4192 .LBB450: 4193 .LBB449: 373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 4194 .loc 4 373 1 is_stmt 0 view .LVU1233 4195 0118 00E0 b .L314 4196 .L315: 373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 4197 .loc 4 373 1 view .LVU1234 4198 .LBE449: 4199 .LBE450: 3567:Src/main.c **** //HAL_SPI_Receive(&hspi4, &P[0], 1, 100); 4200 .loc 1 3567 20 is_stmt 1 discriminator 2 view .LVU1235 3567:Src/main.c **** //HAL_SPI_Receive(&hspi4, &P[0], 1, 100); 4201 .loc 1 3567 25 is_stmt 0 discriminator 2 view .LVU1236 4202 011a 0133 adds r3, r3, #1 4203 .LVL479: 4204 .L314: 3567:Src/main.c **** //HAL_SPI_Receive(&hspi4, &P[0], 1, 100); 4205 .loc 1 3567 14 is_stmt 1 discriminator 1 view .LVU1237 4206 011c B3F5FA7F cmp r3, #500 4207 0120 FBD3 bcc .L315 3569:Src/main.c **** P = LL_SPI_ReceiveData16(SPI5); 4208 .loc 1 3569 3 view .LVU1238 4209 0122 0122 movs r2, #1 4210 0124 4021 movs r1, #64 4211 0126 3B48 ldr r0, .L332+4 4212 0128 FFF7FEFF bl HAL_GPIO_WritePin 4213 .LVL480: 3570:Src/main.c **** } 4214 .loc 1 3570 3 view .LVU1239 4215 .LBB451: 4216 .LBI451: 1344:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 4217 .loc 4 1344 26 view .LVU1240 4218 .LBB452: 1346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 4219 .loc 4 1346 3 view .LVU1241 1346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 4220 .loc 4 1346 21 is_stmt 0 view .LVU1242 4221 012c 3B4B ldr r3, .L332+12 4222 012e DD68 ldr r5, [r3, #12] 1346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } ARM GAS /tmp/ccLSPxIe.s page 223 4223 .loc 4 1346 10 view .LVU1243 4224 0130 ADB2 uxth r5, r5 4225 .LVL481: 1346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 4226 .loc 4 1346 10 view .LVU1244 4227 .LBE452: 4228 .LBE451: 4229 0132 C8E7 b .L296 4230 .LVL482: 4231 .L299: 3574:Src/main.c **** HAL_GPIO_WritePin(ADC_ThrLD1_CS_GPIO_Port, ADC_ThrLD1_CS_Pin, GPIO_PIN_RESET); 4232 .loc 1 3574 3 is_stmt 1 view .LVU1245 4233 0134 364C ldr r4, .L332 4234 0136 0122 movs r2, #1 4235 0138 4FF48061 mov r1, #1024 4236 013c 2046 mov r0, r4 4237 013e FFF7FEFF bl HAL_GPIO_WritePin 4238 .LVL483: 3575:Src/main.c **** tmp32=0; 4239 .loc 1 3575 3 view .LVU1246 4240 0142 0022 movs r2, #0 4241 0144 4FF40061 mov r1, #2048 4242 0148 2046 mov r0, r4 4243 014a FFF7FEFF bl HAL_GPIO_WritePin 4244 .LVL484: 3576:Src/main.c **** while(tmp32<500){tmp32++;} 4245 .loc 1 3576 3 view .LVU1247 3577:Src/main.c **** //LL_SPI_TransmitData16(SPI4, 0xFFFF);//We must to clock the CLK output for collect RX data. We c 4246 .loc 1 3577 3 view .LVU1248 3576:Src/main.c **** while(tmp32<500){tmp32++;} 4247 .loc 1 3576 8 is_stmt 0 view .LVU1249 4248 014e 0023 movs r3, #0 3577:Src/main.c **** //LL_SPI_TransmitData16(SPI4, 0xFFFF);//We must to clock the CLK output for collect RX data. We c 4249 .loc 1 3577 8 view .LVU1250 4250 0150 00E0 b .L316 4251 .LVL485: 4252 .L317: 3577:Src/main.c **** //LL_SPI_TransmitData16(SPI4, 0xFFFF);//We must to clock the CLK output for collect RX data. We c 4253 .loc 1 3577 20 is_stmt 1 discriminator 2 view .LVU1251 3577:Src/main.c **** //LL_SPI_TransmitData16(SPI4, 0xFFFF);//We must to clock the CLK output for collect RX data. We c 4254 .loc 1 3577 25 is_stmt 0 discriminator 2 view .LVU1252 4255 0152 0133 adds r3, r3, #1 4256 .LVL486: 4257 .L316: 3577:Src/main.c **** //LL_SPI_TransmitData16(SPI4, 0xFFFF);//We must to clock the CLK output for collect RX data. We c 4258 .loc 1 3577 14 is_stmt 1 discriminator 1 view .LVU1253 4259 0154 B3F5FA7F cmp r3, #500 4260 0158 FBD3 bcc .L317 3579:Src/main.c **** tmp32 = 0; 4261 .loc 1 3579 3 view .LVU1254 4262 .LVL487: 4263 .LBB453: 4264 .LBI453: 358:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 4265 .loc 4 358 22 view .LVU1255 4266 .LBB454: 360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } ARM GAS /tmp/ccLSPxIe.s page 224 4267 .loc 4 360 3 view .LVU1256 4268 015a 2F4A ldr r2, .L332+8 4269 015c 1368 ldr r3, [r2] 4270 .LVL488: 360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 4271 .loc 4 360 3 is_stmt 0 view .LVU1257 4272 015e 43F04003 orr r3, r3, #64 4273 0162 1360 str r3, [r2] 4274 .LVL489: 360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 4275 .loc 4 360 3 view .LVU1258 4276 .LBE454: 4277 .LBE453: 3580:Src/main.c **** while(((!LL_SPI_IsActiveFlag_RXNE(SPI4))&&(tmp32<=1000))) {tmp32++;}//When rec. last data cycle w 4278 .loc 1 3580 3 is_stmt 1 view .LVU1259 3581:Src/main.c **** LL_SPI_Disable(SPI4);//Enable SPI for ThrLD1 ADC 4279 .loc 1 3581 3 view .LVU1260 3580:Src/main.c **** while(((!LL_SPI_IsActiveFlag_RXNE(SPI4))&&(tmp32<=1000))) {tmp32++;}//When rec. last data cycle w 4280 .loc 1 3580 9 is_stmt 0 view .LVU1261 4281 0164 0023 movs r3, #0 4282 .LVL490: 4283 .L318: 3581:Src/main.c **** LL_SPI_Disable(SPI4);//Enable SPI for ThrLD1 ADC 4284 .loc 1 3581 43 is_stmt 1 discriminator 1 view .LVU1262 4285 .LBB455: 4286 .LBI455: 905:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 4287 .loc 4 905 26 view .LVU1263 4288 .LBB456: 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 4289 .loc 4 907 3 view .LVU1264 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 4290 .loc 4 907 12 is_stmt 0 view .LVU1265 4291 0166 2C4A ldr r2, .L332+8 4292 0168 9268 ldr r2, [r2, #8] 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 4293 .loc 4 907 68 view .LVU1266 4294 016a 12F0010F tst r2, #1 4295 016e 04D1 bne .L319 4296 .LVL491: 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 4297 .loc 4 907 68 view .LVU1267 4298 .LBE456: 4299 .LBE455: 3581:Src/main.c **** LL_SPI_Disable(SPI4);//Enable SPI for ThrLD1 ADC 4300 .loc 1 3581 43 discriminator 2 view .LVU1268 4301 0170 B3F57A7F cmp r3, #1000 4302 0174 01D8 bhi .L319 3581:Src/main.c **** LL_SPI_Disable(SPI4);//Enable SPI for ThrLD1 ADC 4303 .loc 1 3581 62 is_stmt 1 discriminator 3 view .LVU1269 3581:Src/main.c **** LL_SPI_Disable(SPI4);//Enable SPI for ThrLD1 ADC 4304 .loc 1 3581 67 is_stmt 0 discriminator 3 view .LVU1270 4305 0176 0133 adds r3, r3, #1 4306 .LVL492: 3581:Src/main.c **** LL_SPI_Disable(SPI4);//Enable SPI for ThrLD1 ADC 4307 .loc 1 3581 67 discriminator 3 view .LVU1271 4308 0178 F5E7 b .L318 ARM GAS /tmp/ccLSPxIe.s page 225 4309 .L319: 3582:Src/main.c **** while(tmp32<500){tmp32++;} 4310 .loc 1 3582 3 is_stmt 1 view .LVU1272 4311 .LVL493: 4312 .LBB457: 4313 .LBI457: 370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 4314 .loc 4 370 22 view .LVU1273 4315 .LBB458: 372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 4316 .loc 4 372 3 view .LVU1274 4317 017a 2749 ldr r1, .L332+8 4318 017c 0A68 ldr r2, [r1] 4319 017e 22F04002 bic r2, r2, #64 4320 0182 0A60 str r2, [r1] 4321 .LVL494: 372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 4322 .loc 4 372 3 is_stmt 0 view .LVU1275 4323 .LBE458: 4324 .LBE457: 3583:Src/main.c **** //HAL_SPI_Receive(&hspi4, &P[0], 1, 100); 4325 .loc 1 3583 3 is_stmt 1 view .LVU1276 4326 .LBB460: 4327 .LBB459: 373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 4328 .loc 4 373 1 is_stmt 0 view .LVU1277 4329 0184 00E0 b .L321 4330 .L322: 373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 4331 .loc 4 373 1 view .LVU1278 4332 .LBE459: 4333 .LBE460: 3583:Src/main.c **** //HAL_SPI_Receive(&hspi4, &P[0], 1, 100); 4334 .loc 1 3583 20 is_stmt 1 discriminator 2 view .LVU1279 3583:Src/main.c **** //HAL_SPI_Receive(&hspi4, &P[0], 1, 100); 4335 .loc 1 3583 25 is_stmt 0 discriminator 2 view .LVU1280 4336 0186 0133 adds r3, r3, #1 4337 .LVL495: 4338 .L321: 3583:Src/main.c **** //HAL_SPI_Receive(&hspi4, &P[0], 1, 100); 4339 .loc 1 3583 14 is_stmt 1 discriminator 1 view .LVU1281 4340 0188 B3F5FA7F cmp r3, #500 4341 018c FBD3 bcc .L322 3585:Src/main.c **** P = LL_SPI_ReceiveData16(SPI4); 4342 .loc 1 3585 3 view .LVU1282 4343 018e 0122 movs r2, #1 4344 0190 4FF40061 mov r1, #2048 4345 0194 1E48 ldr r0, .L332 4346 0196 FFF7FEFF bl HAL_GPIO_WritePin 4347 .LVL496: 3586:Src/main.c **** } 4348 .loc 1 3586 3 view .LVU1283 4349 .LBB461: 4350 .LBI461: 1344:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 4351 .loc 4 1344 26 view .LVU1284 4352 .LBB462: ARM GAS /tmp/ccLSPxIe.s page 226 1346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 4353 .loc 4 1346 3 view .LVU1285 1346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 4354 .loc 4 1346 21 is_stmt 0 view .LVU1286 4355 019a 1F4B ldr r3, .L332+8 4356 019c DD68 ldr r5, [r3, #12] 1346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 4357 .loc 4 1346 10 view .LVU1287 4358 019e ADB2 uxth r5, r5 4359 .LVL497: 1346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 4360 .loc 4 1346 10 view .LVU1288 4361 .LBE462: 4362 .LBE461: 4363 01a0 91E7 b .L296 4364 .LVL498: 4365 .L297: 3590:Src/main.c **** HAL_GPIO_WritePin(ADC_ThrLD2_CS_GPIO_Port, ADC_ThrLD2_CS_Pin, GPIO_PIN_RESET); 4366 .loc 1 3590 3 is_stmt 1 view .LVU1289 4367 01a2 1C4C ldr r4, .L332+4 4368 01a4 0122 movs r2, #1 4369 01a6 4021 movs r1, #64 4370 01a8 2046 mov r0, r4 4371 01aa FFF7FEFF bl HAL_GPIO_WritePin 4372 .LVL499: 3591:Src/main.c **** tmp32=0; 4373 .loc 1 3591 3 view .LVU1290 4374 01ae 0022 movs r2, #0 4375 01b0 4FF48061 mov r1, #1024 4376 01b4 2046 mov r0, r4 4377 01b6 FFF7FEFF bl HAL_GPIO_WritePin 4378 .LVL500: 3592:Src/main.c **** while(tmp32<500){tmp32++;} 4379 .loc 1 3592 3 view .LVU1291 3593:Src/main.c **** //LL_SPI_TransmitData16(SPI5, 0xFFFF);//We must to clock the CLK output for collect RX data. We c 4380 .loc 1 3593 3 view .LVU1292 3592:Src/main.c **** while(tmp32<500){tmp32++;} 4381 .loc 1 3592 8 is_stmt 0 view .LVU1293 4382 01ba 0023 movs r3, #0 3593:Src/main.c **** //LL_SPI_TransmitData16(SPI5, 0xFFFF);//We must to clock the CLK output for collect RX data. We c 4383 .loc 1 3593 8 view .LVU1294 4384 01bc 00E0 b .L323 4385 .LVL501: 4386 .L324: 3593:Src/main.c **** //LL_SPI_TransmitData16(SPI5, 0xFFFF);//We must to clock the CLK output for collect RX data. We c 4387 .loc 1 3593 20 is_stmt 1 discriminator 2 view .LVU1295 3593:Src/main.c **** //LL_SPI_TransmitData16(SPI5, 0xFFFF);//We must to clock the CLK output for collect RX data. We c 4388 .loc 1 3593 25 is_stmt 0 discriminator 2 view .LVU1296 4389 01be 0133 adds r3, r3, #1 4390 .LVL502: 4391 .L323: 3593:Src/main.c **** //LL_SPI_TransmitData16(SPI5, 0xFFFF);//We must to clock the CLK output for collect RX data. We c 4392 .loc 1 3593 14 is_stmt 1 discriminator 1 view .LVU1297 4393 01c0 B3F5FA7F cmp r3, #500 4394 01c4 FBD3 bcc .L324 3595:Src/main.c **** tmp32 = 0; 4395 .loc 1 3595 3 view .LVU1298 ARM GAS /tmp/ccLSPxIe.s page 227 4396 .LVL503: 4397 .LBB463: 4398 .LBI463: 358:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 4399 .loc 4 358 22 view .LVU1299 4400 .LBB464: 360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 4401 .loc 4 360 3 view .LVU1300 4402 01c6 154A ldr r2, .L332+12 4403 01c8 1368 ldr r3, [r2] 4404 .LVL504: 360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 4405 .loc 4 360 3 is_stmt 0 view .LVU1301 4406 01ca 43F04003 orr r3, r3, #64 4407 01ce 1360 str r3, [r2] 4408 .LVL505: 360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 4409 .loc 4 360 3 view .LVU1302 4410 .LBE464: 4411 .LBE463: 3596:Src/main.c **** while(((!LL_SPI_IsActiveFlag_RXNE(SPI5))&&(tmp32<=1000))) {tmp32++;}//When rec. last data cycle w 4412 .loc 1 3596 3 is_stmt 1 view .LVU1303 3597:Src/main.c **** LL_SPI_Disable(SPI5);//Enable SPI for ThrLD2 ADC 4413 .loc 1 3597 3 view .LVU1304 3596:Src/main.c **** while(((!LL_SPI_IsActiveFlag_RXNE(SPI5))&&(tmp32<=1000))) {tmp32++;}//When rec. last data cycle w 4414 .loc 1 3596 9 is_stmt 0 view .LVU1305 4415 01d0 0023 movs r3, #0 4416 .LVL506: 4417 .L325: 3597:Src/main.c **** LL_SPI_Disable(SPI5);//Enable SPI for ThrLD2 ADC 4418 .loc 1 3597 43 is_stmt 1 discriminator 1 view .LVU1306 4419 .LBB465: 4420 .LBI465: 905:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 4421 .loc 4 905 26 view .LVU1307 4422 .LBB466: 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 4423 .loc 4 907 3 view .LVU1308 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 4424 .loc 4 907 12 is_stmt 0 view .LVU1309 4425 01d2 124A ldr r2, .L332+12 4426 01d4 9268 ldr r2, [r2, #8] 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 4427 .loc 4 907 68 view .LVU1310 4428 01d6 12F0010F tst r2, #1 4429 01da 04D1 bne .L326 4430 .LVL507: 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 4431 .loc 4 907 68 view .LVU1311 4432 .LBE466: 4433 .LBE465: 3597:Src/main.c **** LL_SPI_Disable(SPI5);//Enable SPI for ThrLD2 ADC 4434 .loc 1 3597 43 discriminator 2 view .LVU1312 4435 01dc B3F57A7F cmp r3, #1000 4436 01e0 01D8 bhi .L326 3597:Src/main.c **** LL_SPI_Disable(SPI5);//Enable SPI for ThrLD2 ADC 4437 .loc 1 3597 62 is_stmt 1 discriminator 3 view .LVU1313 ARM GAS /tmp/ccLSPxIe.s page 228 3597:Src/main.c **** LL_SPI_Disable(SPI5);//Enable SPI for ThrLD2 ADC 4438 .loc 1 3597 67 is_stmt 0 discriminator 3 view .LVU1314 4439 01e2 0133 adds r3, r3, #1 4440 .LVL508: 3597:Src/main.c **** LL_SPI_Disable(SPI5);//Enable SPI for ThrLD2 ADC 4441 .loc 1 3597 67 discriminator 3 view .LVU1315 4442 01e4 F5E7 b .L325 4443 .L326: 3598:Src/main.c **** while(tmp32<500){tmp32++;} 4444 .loc 1 3598 3 is_stmt 1 view .LVU1316 4445 .LVL509: 4446 .LBB467: 4447 .LBI467: 370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 4448 .loc 4 370 22 view .LVU1317 4449 .LBB468: 372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 4450 .loc 4 372 3 view .LVU1318 4451 01e6 0D49 ldr r1, .L332+12 4452 01e8 0A68 ldr r2, [r1] 4453 01ea 22F04002 bic r2, r2, #64 4454 01ee 0A60 str r2, [r1] 4455 .LVL510: 372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 4456 .loc 4 372 3 is_stmt 0 view .LVU1319 4457 .LBE468: 4458 .LBE467: 3599:Src/main.c **** //HAL_SPI_Receive(&hspi4, &P[0], 1, 100); 4459 .loc 1 3599 3 is_stmt 1 view .LVU1320 4460 .LBB470: 4461 .LBB469: 373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 4462 .loc 4 373 1 is_stmt 0 view .LVU1321 4463 01f0 00E0 b .L328 4464 .L329: 373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** 4465 .loc 4 373 1 view .LVU1322 4466 .LBE469: 4467 .LBE470: 3599:Src/main.c **** //HAL_SPI_Receive(&hspi4, &P[0], 1, 100); 4468 .loc 1 3599 20 is_stmt 1 discriminator 2 view .LVU1323 3599:Src/main.c **** //HAL_SPI_Receive(&hspi4, &P[0], 1, 100); 4469 .loc 1 3599 25 is_stmt 0 discriminator 2 view .LVU1324 4470 01f2 0133 adds r3, r3, #1 4471 .LVL511: 4472 .L328: 3599:Src/main.c **** //HAL_SPI_Receive(&hspi4, &P[0], 1, 100); 4473 .loc 1 3599 14 is_stmt 1 discriminator 1 view .LVU1325 4474 01f4 B3F5FA7F cmp r3, #500 4475 01f8 FBD3 bcc .L329 3601:Src/main.c **** P = LL_SPI_ReceiveData16(SPI5); 4476 .loc 1 3601 3 view .LVU1326 4477 01fa 0122 movs r2, #1 4478 01fc 4FF48061 mov r1, #1024 4479 0200 0448 ldr r0, .L332+4 4480 0202 FFF7FEFF bl HAL_GPIO_WritePin 4481 .LVL512: ARM GAS /tmp/ccLSPxIe.s page 229 3602:Src/main.c **** } 4482 .loc 1 3602 3 view .LVU1327 4483 .LBB471: 4484 .LBI471: 1344:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 4485 .loc 4 1344 26 view .LVU1328 4486 .LBB472: 1346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 4487 .loc 4 1346 3 view .LVU1329 1346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 4488 .loc 4 1346 21 is_stmt 0 view .LVU1330 4489 0206 054B ldr r3, .L332+12 4490 0208 DD68 ldr r5, [r3, #12] 1346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 4491 .loc 4 1346 10 view .LVU1331 4492 020a ADB2 uxth r5, r5 4493 .LVL513: 1346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 4494 .loc 4 1346 10 view .LVU1332 4495 020c 5BE7 b .L296 4496 .L333: 4497 020e 00BF .align 2 4498 .L332: 4499 0210 00100240 .word 1073876992 4500 0214 00140240 .word 1073878016 4501 0218 00340140 .word 1073820672 4502 021c 00500140 .word 1073827840 4503 .LBE472: 4504 .LBE471: 4505 .cfi_endproc 4506 .LFE1236: 4508 .section .text.Stop_TIM10,"ax",%progbits 4509 .align 1 4510 .syntax unified 4511 .thumb 4512 .thumb_func 4514 Stop_TIM10: 4515 .LFB1247: 3767:Src/main.c **** uint8_t CheckChecksum(uint16_t *pbuff) 3768:Src/main.c **** { 3769:Src/main.c **** uint16_t cl_ind; 3770:Src/main.c **** 3771:Src/main.c **** switch (UART_header) 3772:Src/main.c **** { 3773:Src/main.c **** case 0x7777: 3774:Src/main.c **** cl_ind = TSK_16 - 2; 3775:Src/main.c **** break; 3776:Src/main.c **** case 0x1111: 3777:Src/main.c **** cl_ind = CL_16 - 2; 3778:Src/main.c **** break; 3779:Src/main.c **** default: 3780:Src/main.c **** return 0; 3781:Src/main.c **** break; 3782:Src/main.c **** } 3783:Src/main.c **** 3784:Src/main.c **** CS_result = CalculateChecksum(pbuff, cl_ind); 3785:Src/main.c **** ARM GAS /tmp/ccLSPxIe.s page 230 3786:Src/main.c **** return ((CS_result == COMMAND[cl_ind]) ? 1 : 0); 3787:Src/main.c **** } 3788:Src/main.c **** uint16_t CalculateChecksum(uint16_t *pbuff, uint16_t len) 3789:Src/main.c **** { 3790:Src/main.c **** short i; 3791:Src/main.c **** uint16_t cs = *pbuff; 3792:Src/main.c **** 3793:Src/main.c **** for(i = 1; i < len; i++) 3794:Src/main.c **** { 3795:Src/main.c **** cs ^= *(pbuff+i); 3796:Src/main.c **** } 3797:Src/main.c **** return cs; 3798:Src/main.c **** } 3799:Src/main.c **** 3800:Src/main.c **** /*int SD_Init(void) 3801:Src/main.c **** { 3802:Src/main.c **** int test=0; 3803:Src/main.c **** if (HAL_GPIO_ReadPin(SDMMC1_EN_GPIO_Port, SDMMC1_EN_Pin)==GPIO_PIN_RESET) 3804:Src/main.c **** { 3805:Src/main.c **** test = Mount_SD("/"); 3806:Src/main.c **** if (test == 0) //0 - suc 3807:Src/main.c **** { 3808:Src/main.c **** //Format_SD(); 3809:Src/main.c **** test = Create_File("FILE1.TXT"); // 0 -suc 3810:Src/main.c **** //Create_File("FILE2.TXT"); 3811:Src/main.c **** Write_File ("FILE1.TXT", "____OSGG main borad information. Program made by Kazakov Viktor. Part 3812:Src/main.c **** test = Unmount_SD("/"); // 0 - succ 3813:Src/main.c **** return test; 3814:Src/main.c **** } 3815:Src/main.c **** else 3816:Src/main.c **** { 3817:Src/main.c **** return 1; 3818:Src/main.c **** } 3819:Src/main.c **** } 3820:Src/main.c **** else 3821:Src/main.c **** { 3822:Src/main.c **** return 1; 3823:Src/main.c **** } 3824:Src/main.c **** }*/ 3825:Src/main.c **** 3826:Src/main.c **** int SD_SAVE(uint16_t *pbuff) 3827:Src/main.c **** { 3828:Src/main.c **** int test=0; 3829:Src/main.c **** if (HAL_GPIO_ReadPin(SDMMC1_EN_GPIO_Port, SDMMC1_EN_Pin)==GPIO_PIN_RESET) 3830:Src/main.c **** { 3831:Src/main.c **** test = Mount_SD("/"); 3832:Src/main.c **** if (test == 0) //0 - suc 3833:Src/main.c **** { 3834:Src/main.c **** //Format_SD(); 3835:Src/main.c **** test = Update_File_byte("FILE1.TXT", (uint8_t *)pbuff, DL_8); 3836:Src/main.c **** test = Unmount_SD("/"); // 0 - succ 3837:Src/main.c **** return test; 3838:Src/main.c **** } 3839:Src/main.c **** else 3840:Src/main.c **** { 3841:Src/main.c **** return 1; 3842:Src/main.c **** } ARM GAS /tmp/ccLSPxIe.s page 231 3843:Src/main.c **** } 3844:Src/main.c **** else 3845:Src/main.c **** { 3846:Src/main.c **** return 1; 3847:Src/main.c **** } 3848:Src/main.c **** } 3849:Src/main.c **** 3850:Src/main.c **** 3851:Src/main.c **** 3852:Src/main.c **** //uint32_t Get_Length(void) 3853:Src/main.c **** //{ 3854:Src/main.c **** // return SD_matr[0][0] + ((uint32_t) (SD_matr[0][1])<<16); 3855:Src/main.c **** //} 3856:Src/main.c **** 3857:Src/main.c **** int SD_READ(uint16_t *pbuff) 3858:Src/main.c **** { 3859:Src/main.c **** int test=0; 3860:Src/main.c **** if (HAL_GPIO_ReadPin(SDMMC1_EN_GPIO_Port, SDMMC1_EN_Pin)==GPIO_PIN_RESET) 3861:Src/main.c **** { 3862:Src/main.c **** test = Mount_SD("/"); 3863:Src/main.c **** if (test == 0) //0 - suc 3864:Src/main.c **** { 3865:Src/main.c **** //Format_SD(); 3866:Src/main.c **** test = Seek_Read_File ("FILE1.TXT", (uint8_t *)pbuff, DL_8, fgoto);//Read next 246 bytes 3867:Src/main.c **** fgoto+=DL_8; 3868:Src/main.c **** test = Unmount_SD("/"); // 0 - succ 3869:Src/main.c **** return test; 3870:Src/main.c **** } 3871:Src/main.c **** else 3872:Src/main.c **** { 3873:Src/main.c **** return 1; 3874:Src/main.c **** } 3875:Src/main.c **** } 3876:Src/main.c **** else 3877:Src/main.c **** { 3878:Src/main.c **** return 1; 3879:Src/main.c **** } 3880:Src/main.c **** 3881:Src/main.c **** /* for (uint16_t j = 0; j < DL_16; j++) 3882:Src/main.c **** { 3883:Src/main.c **** *(pbuff+j) = SD_matr[SD_SLIDE][j]; 3884:Src/main.c **** } 3885:Src/main.c **** if (SD_SLIDEDHR12R1 = 0u; 5137 .loc 1 2825 2 view .LVU1546 2825:Src/main.c **** DAC->DHR12R1 = 0u; 5138 .loc 1 2825 5 is_stmt 0 view .LVU1547 5139 0046 064B ldr r3, .L344+8 5140 0048 1968 ldr r1, [r3] 2825:Src/main.c **** DAC->DHR12R1 = 0u; 5141 .loc 1 2825 10 view .LVU1548 5142 004a 064A ldr r2, .L344+12 5143 004c 0A40 ands r2, r2, r1 5144 004e 1A60 str r2, [r3] 2826:Src/main.c **** } 5145 .loc 1 2826 2 is_stmt 1 view .LVU1549 2826:Src/main.c **** } 5146 .loc 1 2826 15 is_stmt 0 view .LVU1550 5147 0050 9C60 str r4, [r3, #8] 2827:Src/main.c **** 5148 .loc 1 2827 1 view .LVU1551 5149 0052 08B0 add sp, sp, #32 5150 .LCFI45: 5151 .cfi_def_cfa_offset 8 5152 @ sp needed 5153 0054 10BD pop {r4, pc} 5154 .L345: 5155 0056 00BF .align 2 5156 .L344: 5157 0058 00380240 .word 1073887232 5158 005c 00000240 .word 1073872896 5159 0060 00740040 .word 1073771520 5160 0064 FAEFFFFF .word -4102 5161 .cfi_endproc 5162 .LFE1216: 5164 .section .text.MX_SPI4_Init,"ax",%progbits 5165 .align 1 5166 .syntax unified 5167 .thumb 5168 .thumb_func 5170 MX_SPI4_Init: 5171 .LFB1192: 1439:Src/main.c **** 5172 .loc 1 1439 1 is_stmt 1 view -0 ARM GAS /tmp/ccLSPxIe.s page 248 5173 .cfi_startproc 5174 @ args = 0, pretend = 0, frame = 72 5175 @ frame_needed = 0, uses_anonymous_args = 0 5176 0000 2DE9F041 push {r4, r5, r6, r7, r8, lr} 5177 .LCFI46: 5178 .cfi_def_cfa_offset 24 5179 .cfi_offset 4, -24 5180 .cfi_offset 5, -20 5181 .cfi_offset 6, -16 5182 .cfi_offset 7, -12 5183 .cfi_offset 8, -8 5184 .cfi_offset 14, -4 5185 0004 92B0 sub sp, sp, #72 5186 .LCFI47: 5187 .cfi_def_cfa_offset 96 1445:Src/main.c **** 5188 .loc 1 1445 3 view .LVU1553 1445:Src/main.c **** 5189 .loc 1 1445 22 is_stmt 0 view .LVU1554 5190 0006 2822 movs r2, #40 5191 0008 0021 movs r1, #0 5192 000a 08A8 add r0, sp, #32 5193 000c FFF7FEFF bl memset 5194 .LVL545: 1447:Src/main.c **** 5195 .loc 1 1447 3 is_stmt 1 view .LVU1555 1447:Src/main.c **** 5196 .loc 1 1447 23 is_stmt 0 view .LVU1556 5197 0010 0024 movs r4, #0 5198 0012 0294 str r4, [sp, #8] 5199 0014 0394 str r4, [sp, #12] 5200 0016 0494 str r4, [sp, #16] 5201 0018 0594 str r4, [sp, #20] 5202 001a 0694 str r4, [sp, #24] 5203 001c 0794 str r4, [sp, #28] 1450:Src/main.c **** 5204 .loc 1 1450 3 is_stmt 1 view .LVU1557 5205 .LVL546: 5206 .LBB483: 5207 .LBI483: 316:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } 317:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 318:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** 319:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Check if AHB1 peripheral clock is enabled or not 320:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll AHB1ENR GPIOAEN LL_AHB1_GRP1_IsEnabledClock\n 321:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOBEN LL_AHB1_GRP1_IsEnabledClock\n 322:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOCEN LL_AHB1_GRP1_IsEnabledClock\n 323:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIODEN LL_AHB1_GRP1_IsEnabledClock\n 324:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOEEN LL_AHB1_GRP1_IsEnabledClock\n 325:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOFEN LL_AHB1_GRP1_IsEnabledClock\n 326:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOGEN LL_AHB1_GRP1_IsEnabledClock\n 327:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOHEN LL_AHB1_GRP1_IsEnabledClock\n 328:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOIEN LL_AHB1_GRP1_IsEnabledClock\n 329:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOJEN LL_AHB1_GRP1_IsEnabledClock\n 330:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOKEN LL_AHB1_GRP1_IsEnabledClock\n 331:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR CRCEN LL_AHB1_GRP1_IsEnabledClock\n 332:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR BKPSRAMEN LL_AHB1_GRP1_IsEnabledClock\n ARM GAS /tmp/ccLSPxIe.s page 249 333:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR DTCMRAMEN LL_AHB1_GRP1_IsEnabledClock\n 334:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR DMA1EN LL_AHB1_GRP1_IsEnabledClock\n 335:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR DMA2EN LL_AHB1_GRP1_IsEnabledClock\n 336:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR DMA2DEN LL_AHB1_GRP1_IsEnabledClock\n 337:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR ETHMACEN LL_AHB1_GRP1_IsEnabledClock\n 338:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR ETHMACTXEN LL_AHB1_GRP1_IsEnabledClock\n 339:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR ETHMACRXEN LL_AHB1_GRP1_IsEnabledClock\n 340:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR ETHMACPTPEN LL_AHB1_GRP1_IsEnabledClock\n 341:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR OTGHSEN LL_AHB1_GRP1_IsEnabledClock\n 342:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR OTGHSULPIENDEN LL_AHB1_GRP1_IsEnabledClock 343:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: 344:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA 345:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB 346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC 347:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD 348:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE 349:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF 350:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG 351:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH 352:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI 353:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*) 354:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*) 355:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRC 356:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM 357:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DTCMRAM 358:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 359:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*) 361:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*) 362:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*) 363:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*) 364:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACPTP (*) 365:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS 366:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHSULPI 367:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * 368:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. 369:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval State of Periphs (1 or 0). 370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ 371:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs) 372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { 373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** return (READ_BIT(RCC->AHB1ENR, Periphs) == Periphs); 374:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } 375:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 376:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** 377:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Disable AHB1 peripherals clock. 378:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll AHB1ENR GPIOAEN LL_AHB1_GRP1_DisableClock\n 379:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOBEN LL_AHB1_GRP1_DisableClock\n 380:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOCEN LL_AHB1_GRP1_DisableClock\n 381:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIODEN LL_AHB1_GRP1_DisableClock\n 382:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOEEN LL_AHB1_GRP1_DisableClock\n 383:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOFEN LL_AHB1_GRP1_DisableClock\n 384:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOGEN LL_AHB1_GRP1_DisableClock\n 385:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOHEN LL_AHB1_GRP1_DisableClock\n 386:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOIEN LL_AHB1_GRP1_DisableClock\n 387:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOJEN LL_AHB1_GRP1_DisableClock\n 388:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOKEN LL_AHB1_GRP1_DisableClock\n 389:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR CRCEN LL_AHB1_GRP1_DisableClock\n ARM GAS /tmp/ccLSPxIe.s page 250 390:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR BKPSRAMEN LL_AHB1_GRP1_DisableClock\n 391:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR DTCMRAMEN LL_AHB1_GRP1_DisableClock\n 392:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR DMA1EN LL_AHB1_GRP1_DisableClock\n 393:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR DMA2EN LL_AHB1_GRP1_DisableClock\n 394:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR DMA2DEN LL_AHB1_GRP1_DisableClock\n 395:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR ETHMACEN LL_AHB1_GRP1_DisableClock\n 396:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR ETHMACTXEN LL_AHB1_GRP1_DisableClock\n 397:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR ETHMACRXEN LL_AHB1_GRP1_DisableClock\n 398:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR ETHMACPTPEN LL_AHB1_GRP1_DisableClock\n 399:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR OTGHSEN LL_AHB1_GRP1_DisableClock\n 400:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR OTGHSULPIENDEN LL_AHB1_GRP1_DisableClock 401:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: 402:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA 403:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB 404:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC 405:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD 406:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE 407:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF 408:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG 409:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH 410:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI 411:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*) 412:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*) 413:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRC 414:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM 415:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DTCMRAM 416:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 417:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 418:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*) 419:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*) 420:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*) 421:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*) 422:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACPTP (*) 423:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS 424:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHSULPI 425:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * 426:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. 427:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval None 428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ 429:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs) 430:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { 431:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** CLEAR_BIT(RCC->AHB1ENR, Periphs); 432:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } 433:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 434:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** 435:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Force AHB1 peripherals reset. 436:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll AHB1RSTR GPIOARST LL_AHB1_GRP1_ForceReset\n 437:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR GPIOBRST LL_AHB1_GRP1_ForceReset\n 438:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR GPIOCRST LL_AHB1_GRP1_ForceReset\n 439:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR GPIODRST LL_AHB1_GRP1_ForceReset\n 440:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR GPIOERST LL_AHB1_GRP1_ForceReset\n 441:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR GPIOFRST LL_AHB1_GRP1_ForceReset\n 442:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR GPIOGRST LL_AHB1_GRP1_ForceReset\n 443:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR GPIOHRST LL_AHB1_GRP1_ForceReset\n 444:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR GPIOIRST LL_AHB1_GRP1_ForceReset\n 445:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR GPIOJRST LL_AHB1_GRP1_ForceReset\n 446:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR GPIOKRST LL_AHB1_GRP1_ForceReset\n ARM GAS /tmp/ccLSPxIe.s page 251 447:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR CRCRST LL_AHB1_GRP1_ForceReset\n 448:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR DMA1RST LL_AHB1_GRP1_ForceReset\n 449:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR DMA2RST LL_AHB1_GRP1_ForceReset\n 450:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR DMA2DRST LL_AHB1_GRP1_ForceReset\n 451:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR ETHMACRST LL_AHB1_GRP1_ForceReset\n 452:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR OTGHSRST LL_AHB1_GRP1_ForceReset 453:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: 454:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ALL 455:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA 456:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB 457:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC 458:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD 459:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE 460:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF 461:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG 462:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH 463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI 464:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*) 465:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*) 466:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRC 467:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 468:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 469:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*) 470:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*) 471:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS 472:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * 473:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. 474:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval None 475:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ 476:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs) 477:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { 478:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** SET_BIT(RCC->AHB1RSTR, Periphs); 479:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } 480:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 481:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** 482:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Release AHB1 peripherals reset. 483:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll AHB1RSTR GPIOARST LL_AHB1_GRP1_ReleaseReset\n 484:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR GPIOBRST LL_AHB1_GRP1_ReleaseReset\n 485:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR GPIOCRST LL_AHB1_GRP1_ReleaseReset\n 486:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR GPIODRST LL_AHB1_GRP1_ReleaseReset\n 487:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR GPIOERST LL_AHB1_GRP1_ReleaseReset\n 488:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR GPIOFRST LL_AHB1_GRP1_ReleaseReset\n 489:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR GPIOGRST LL_AHB1_GRP1_ReleaseReset\n 490:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR GPIOHRST LL_AHB1_GRP1_ReleaseReset\n 491:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR GPIOIRST LL_AHB1_GRP1_ReleaseReset\n 492:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR GPIOJRST LL_AHB1_GRP1_ReleaseReset\n 493:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR GPIOKRST LL_AHB1_GRP1_ReleaseReset\n 494:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR CRCRST LL_AHB1_GRP1_ReleaseReset\n 495:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR DMA1RST LL_AHB1_GRP1_ReleaseReset\n 496:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR DMA2RST LL_AHB1_GRP1_ReleaseReset\n 497:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR DMA2DRST LL_AHB1_GRP1_ReleaseReset\n 498:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR ETHMACRST LL_AHB1_GRP1_ReleaseReset\n 499:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR OTGHSRST LL_AHB1_GRP1_ReleaseReset 500:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: 501:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ALL 502:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA 503:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB ARM GAS /tmp/ccLSPxIe.s page 252 504:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC 505:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD 506:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE 507:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF 508:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG 509:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH 510:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI 511:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*) 512:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*) 513:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRC 514:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 515:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 516:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*) 517:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*) 518:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS 519:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * 520:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. 521:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval None 522:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ 523:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs) 524:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { 525:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** CLEAR_BIT(RCC->AHB1RSTR, Periphs); 526:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } 527:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 528:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** 529:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Enable AHB1 peripheral clocks in low-power mode 530:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll AHB1LPENR GPIOALPEN LL_AHB1_GRP1_EnableClockLowPower\n 531:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR GPIOBLPEN LL_AHB1_GRP1_EnableClockLowPower\n 532:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR GPIOCLPEN LL_AHB1_GRP1_EnableClockLowPower\n 533:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR GPIODLPEN LL_AHB1_GRP1_EnableClockLowPower\n 534:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR GPIOELPEN LL_AHB1_GRP1_EnableClockLowPower\n 535:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR GPIOFLPEN LL_AHB1_GRP1_EnableClockLowPower\n 536:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR GPIOGLPEN LL_AHB1_GRP1_EnableClockLowPower\n 537:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR GPIOHLPEN LL_AHB1_GRP1_EnableClockLowPower\n 538:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR GPIOILPEN LL_AHB1_GRP1_EnableClockLowPower\n 539:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR GPIOJLPEN LL_AHB1_GRP1_EnableClockLowPower\n 540:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR GPIOKLPEN LL_AHB1_GRP1_EnableClockLowPower\n 541:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR CRCLPEN LL_AHB1_GRP1_EnableClockLowPower\n 542:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR AXILPEN LL_AHB1_GRP1_EnableClockLowPower\n 543:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR FLITFLPEN LL_AHB1_GRP1_EnableClockLowPower\n 544:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR SRAM1LPEN LL_AHB1_GRP1_EnableClockLowPower\n 545:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR SRAM2LPEN LL_AHB1_GRP1_EnableClockLowPower\n 546:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR BKPSRAMLPEN LL_AHB1_GRP1_EnableClockLowPower\n 547:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR DTCMRAMLPEN LL_AHB1_GRP1_EnableClockLowPower\n 548:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR DMA1LPEN LL_AHB1_GRP1_EnableClockLowPower\n 549:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR DMA2LPEN LL_AHB1_GRP1_EnableClockLowPower\n 550:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR DMA2DLPEN LL_AHB1_GRP1_EnableClockLowPower\n 551:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR ETHMACLPEN LL_AHB1_GRP1_EnableClockLowPower\n 552:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR ETHMACTXLPEN LL_AHB1_GRP1_EnableClockLowPower\n 553:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR ETHMACRXLPEN LL_AHB1_GRP1_EnableClockLowPower\n 554:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR ETHMACPTPLPEN LL_AHB1_GRP1_EnableClockLowPower\n 555:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR OTGHSLPEN LL_AHB1_GRP1_EnableClockLowPower\n 556:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR OTGHSULPILPEN LL_AHB1_GRP1_EnableClockLowPower 557:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: 558:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA 559:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB 560:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC ARM GAS /tmp/ccLSPxIe.s page 253 561:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD 562:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE 563:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF 564:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG 565:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH 566:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI 567:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*) 568:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*) 569:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRC 570:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_AXI 571:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_FLITF 572:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1 573:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM2 574:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM 575:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DTCMRAM 576:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 577:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 578:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*) 579:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*) 580:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*) 581:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*) 582:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACPTP (*) 583:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS 584:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHSULPI 585:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * 586:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. 587:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval None 588:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ 589:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB1_GRP1_EnableClockLowPower(uint32_t Periphs) 590:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { 591:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __IO uint32_t tmpreg; 592:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** SET_BIT(RCC->AHB1LPENR, Periphs); 593:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Delay after an RCC peripheral clock enabling */ 594:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** tmpreg = READ_BIT(RCC->AHB1LPENR, Periphs); 595:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; 596:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } 597:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 598:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** 599:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Disable AHB1 peripheral clocks in low-power mode 600:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll AHB1LPENR GPIOALPEN LL_AHB1_GRP1_DisableClockLowPower\n 601:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR GPIOBLPEN LL_AHB1_GRP1_DisableClockLowPower\n 602:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR GPIOCLPEN LL_AHB1_GRP1_DisableClockLowPower\n 603:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR GPIODLPEN LL_AHB1_GRP1_DisableClockLowPower\n 604:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR GPIOELPEN LL_AHB1_GRP1_DisableClockLowPower\n 605:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR GPIOFLPEN LL_AHB1_GRP1_DisableClockLowPower\n 606:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR GPIOGLPEN LL_AHB1_GRP1_DisableClockLowPower\n 607:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR GPIOHLPEN LL_AHB1_GRP1_DisableClockLowPower\n 608:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR GPIOILPEN LL_AHB1_GRP1_DisableClockLowPower\n 609:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR GPIOJLPEN LL_AHB1_GRP1_DisableClockLowPower\n 610:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR GPIOKLPEN LL_AHB1_GRP1_DisableClockLowPower\n 611:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR CRCLPEN LL_AHB1_GRP1_DisableClockLowPower\n 612:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR AXILPEN LL_AHB1_GRP1_DisableClockLowPower\n 613:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR FLITFLPEN LL_AHB1_GRP1_DisableClockLowPower\n 614:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR SRAM1LPEN LL_AHB1_GRP1_DisableClockLowPower\n 615:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR SRAM2LPEN LL_AHB1_GRP1_DisableClockLowPower\n 616:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR BKPSRAMLPEN LL_AHB1_GRP1_DisableClockLowPower\n 617:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR DTCMRAMLPEN LL_AHB1_GRP1_DisableClockLowPower\n ARM GAS /tmp/ccLSPxIe.s page 254 618:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR DMA1LPEN LL_AHB1_GRP1_DisableClockLowPower\n 619:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR DMA2LPEN LL_AHB1_GRP1_DisableClockLowPower\n 620:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR DMA2DLPEN LL_AHB1_GRP1_DisableClockLowPower\n 621:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR ETHMACLPEN LL_AHB1_GRP1_DisableClockLowPower\n 622:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR ETHMACTXLPEN LL_AHB1_GRP1_DisableClockLowPower\n 623:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR ETHMACRXLPEN LL_AHB1_GRP1_DisableClockLowPower\n 624:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR ETHMACPTPLPEN LL_AHB1_GRP1_DisableClockLowPower\n 625:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR OTGHSLPEN LL_AHB1_GRP1_DisableClockLowPower\n 626:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR OTGHSULPILPEN LL_AHB1_GRP1_DisableClockLowPower 627:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: 628:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA 629:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB 630:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC 631:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD 632:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE 633:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF 634:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG 635:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH 636:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI 637:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*) 638:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*) 639:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRC 640:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_AXI 641:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_FLITF 642:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1 643:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM2 644:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM 645:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DTCMRAM 646:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 647:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 648:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*) 649:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*) 650:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*) 651:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*) 652:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACPTP (*) 653:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS 654:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHSULPI 655:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * 656:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. 657:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval None 658:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ 659:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB1_GRP1_DisableClockLowPower(uint32_t Periphs) 660:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { 661:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** CLEAR_BIT(RCC->AHB1LPENR, Periphs); 662:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } 663:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 664:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** 665:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @} 666:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ 667:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 668:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** @defgroup BUS_LL_EF_AHB2 AHB2 669:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @{ 670:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ 671:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 672:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** 673:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Enable AHB2 peripherals clock. 674:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll AHB2ENR DCMIEN LL_AHB2_GRP1_EnableClock\n ARM GAS /tmp/ccLSPxIe.s page 255 675:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2ENR JPEGEN LL_AHB2_GRP1_EnableClock\n 676:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2ENR CRYPEN LL_AHB2_GRP1_EnableClock\n 677:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2ENR AESEN LL_AHB2_GRP1_EnableClock\n 678:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2ENR HASHEN LL_AHB2_GRP1_EnableClock\n 679:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2ENR RNGEN LL_AHB2_GRP1_EnableClock\n 680:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2ENR OTGFSEN LL_AHB2_GRP1_EnableClock 681:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: 682:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*) 683:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_JPEG (*) 684:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) 685:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*) 686:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) 687:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_RNG 688:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS 689:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * 690:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. 691:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval None 692:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ 693:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB2_GRP1_EnableClock(uint32_t Periphs) 694:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { 695:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __IO uint32_t tmpreg; 696:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** SET_BIT(RCC->AHB2ENR, Periphs); 697:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Delay after an RCC peripheral clock enabling */ 698:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** tmpreg = READ_BIT(RCC->AHB2ENR, Periphs); 699:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; 700:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } 701:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 702:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** 703:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Check if AHB2 peripheral clock is enabled or not 704:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll AHB2ENR DCMIEN LL_AHB2_GRP1_IsEnabledClock\n 705:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2ENR JPEGEN LL_AHB2_GRP1_IsEnabledClock\n 706:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2ENR CRYPEN LL_AHB2_GRP1_IsEnabledClock\n 707:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2ENR AESEN LL_AHB2_GRP1_IsEnabledClock\n 708:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2ENR HASHEN LL_AHB2_GRP1_IsEnabledClock\n 709:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2ENR RNGEN LL_AHB2_GRP1_IsEnabledClock\n 710:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2ENR OTGFSEN LL_AHB2_GRP1_IsEnabledClock 711:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: 712:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*) 713:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_JPEG (*) 714:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) 715:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*) 716:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) 717:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_RNG 718:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS 719:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * 720:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. 721:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval State of Periphs (1 or 0). 722:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ 723:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE uint32_t LL_AHB2_GRP1_IsEnabledClock(uint32_t Periphs) 724:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { 725:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** return (READ_BIT(RCC->AHB2ENR, Periphs) == Periphs); 726:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } 727:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 728:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** 729:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Disable AHB2 peripherals clock. 730:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll AHB2ENR DCMIEN LL_AHB2_GRP1_DisableClock\n 731:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2ENR JPEGEN LL_AHB2_GRP1_DisableClock\n ARM GAS /tmp/ccLSPxIe.s page 256 732:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2ENR CRYPEN LL_AHB2_GRP1_DisableClock\n 733:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2ENR AESEN LL_AHB2_GRP1_DisableClock\n 734:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2ENR HASHEN LL_AHB2_GRP1_DisableClock\n 735:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2ENR RNGEN LL_AHB2_GRP1_DisableClock\n 736:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2ENR OTGFSEN LL_AHB2_GRP1_DisableClock 737:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: 738:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*) 739:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_JPEG (*) 740:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) 741:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*) 742:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) 743:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_RNG 744:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS 745:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * 746:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. 747:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval None 748:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ 749:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB2_GRP1_DisableClock(uint32_t Periphs) 750:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { 751:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** CLEAR_BIT(RCC->AHB2ENR, Periphs); 752:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } 753:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 754:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** 755:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Force AHB2 peripherals reset. 756:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll AHB2RSTR DCMIRST LL_AHB2_GRP1_ForceReset\n 757:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2RSTR JPEGRST LL_AHB2_GRP1_ForceReset\n 758:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2RSTR CRYPRST LL_AHB2_GRP1_ForceReset\n 759:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2RSTR AESRST LL_AHB2_GRP1_ForceReset\n 760:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2RSTR HASHRST LL_AHB2_GRP1_ForceReset\n 761:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2RSTR RNGRST LL_AHB2_GRP1_ForceReset\n 762:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2RSTR OTGFSRST LL_AHB2_GRP1_ForceReset 763:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: 764:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_ALL 765:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*) 766:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_JPEG (*) 767:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) 768:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*) 769:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) 770:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_RNG 771:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS 772:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * 773:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. 774:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval None 775:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ 776:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB2_GRP1_ForceReset(uint32_t Periphs) 777:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { 778:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** SET_BIT(RCC->AHB2RSTR, Periphs); 779:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } 780:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 781:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** 782:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Release AHB2 peripherals reset. 783:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll AHB2RSTR DCMIRST LL_AHB2_GRP1_ReleaseReset\n 784:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2RSTR JPEGRST LL_AHB2_GRP1_ReleaseReset\n 785:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2RSTR CRYPRST LL_AHB2_GRP1_ReleaseReset\n 786:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2RSTR AESRST LL_AHB2_GRP1_ReleaseReset\n 787:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2RSTR HASHRST LL_AHB2_GRP1_ReleaseReset\n 788:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2RSTR RNGRST LL_AHB2_GRP1_ReleaseReset\n ARM GAS /tmp/ccLSPxIe.s page 257 789:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2RSTR OTGFSRST LL_AHB2_GRP1_ReleaseReset 790:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: 791:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_ALL 792:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*) 793:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_JPEG (*) 794:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) 795:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*) 796:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) 797:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_RNG 798:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS 799:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * 800:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. 801:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval None 802:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ 803:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB2_GRP1_ReleaseReset(uint32_t Periphs) 804:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { 805:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** CLEAR_BIT(RCC->AHB2RSTR, Periphs); 806:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } 807:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 808:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** 809:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Enable AHB2 peripheral clocks in low-power mode 810:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll AHB2LPENR DCMILPEN LL_AHB2_GRP1_EnableClockLowPower\n 811:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2LPENR JPEGLPEN LL_AHB2_GRP1_EnableClockLowPower\n 812:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2LPENR CRYPLPEN LL_AHB2_GRP1_EnableClockLowPower\n 813:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2LPENR AESLPEN LL_AHB2_GRP1_EnableClockLowPower\n 814:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2LPENR HASHLPEN LL_AHB2_GRP1_EnableClockLowPower\n 815:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2LPENR RNGLPEN LL_AHB2_GRP1_EnableClockLowPower\n 816:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2LPENR OTGFSLPEN LL_AHB2_GRP1_EnableClockLowPower 817:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: 818:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*) 819:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_JPEG (*) 820:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) 821:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*) 822:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) 823:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_RNG 824:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS 825:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * 826:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. 827:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval None 828:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ 829:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB2_GRP1_EnableClockLowPower(uint32_t Periphs) 830:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { 831:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __IO uint32_t tmpreg; 832:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** SET_BIT(RCC->AHB2LPENR, Periphs); 833:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Delay after an RCC peripheral clock enabling */ 834:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** tmpreg = READ_BIT(RCC->AHB2LPENR, Periphs); 835:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; 836:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } 837:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 838:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** 839:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Disable AHB2 peripheral clocks in low-power mode 840:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll AHB2LPENR DCMILPEN LL_AHB2_GRP1_DisableClockLowPower\n 841:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2LPENR JPEGLPEN LL_AHB2_GRP1_DisableClockLowPower\n 842:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2LPENR CRYPLPEN LL_AHB2_GRP1_DisableClockLowPower\n 843:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2LPENR AESLPEN LL_AHB2_GRP1_DisableClockLowPower\n 844:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2LPENR HASHLPEN LL_AHB2_GRP1_DisableClockLowPower\n 845:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2LPENR RNGLPEN LL_AHB2_GRP1_DisableClockLowPower\n ARM GAS /tmp/ccLSPxIe.s page 258 846:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2LPENR OTGFSLPEN LL_AHB2_GRP1_DisableClockLowPower 847:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: 848:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*) 849:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_JPEG (*) 850:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) 851:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*) 852:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) 853:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_RNG 854:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS 855:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * 856:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. 857:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval None 858:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ 859:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB2_GRP1_DisableClockLowPower(uint32_t Periphs) 860:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { 861:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** CLEAR_BIT(RCC->AHB2LPENR, Periphs); 862:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } 863:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 864:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** 865:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @} 866:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ 867:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 868:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** @defgroup BUS_LL_EF_AHB3 AHB3 869:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @{ 870:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ 871:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 872:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** 873:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Enable AHB3 peripherals clock. 874:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll AHB3ENR FMCEN LL_AHB3_GRP1_EnableClock\n 875:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB3ENR QSPIEN LL_AHB3_GRP1_EnableClock 876:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: 877:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*) 878:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI 879:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * 880:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. 881:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval None 882:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ 883:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB3_GRP1_EnableClock(uint32_t Periphs) 884:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { 885:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __IO uint32_t tmpreg; 886:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** SET_BIT(RCC->AHB3ENR, Periphs); 887:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Delay after an RCC peripheral clock enabling */ 888:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** tmpreg = READ_BIT(RCC->AHB3ENR, Periphs); 889:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; 890:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } 891:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 892:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** 893:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Check if AHB3 peripheral clock is enabled or not 894:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll AHB3ENR FMCEN LL_AHB3_GRP1_IsEnabledClock\n 895:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB3ENR QSPIEN LL_AHB3_GRP1_IsEnabledClock 896:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: 897:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*) 898:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI 899:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * 900:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. 901:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval State of Periphs (1 or 0). 902:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ ARM GAS /tmp/ccLSPxIe.s page 259 903:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE uint32_t LL_AHB3_GRP1_IsEnabledClock(uint32_t Periphs) 904:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { 905:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** return (READ_BIT(RCC->AHB3ENR, Periphs) == Periphs); 906:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 908:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** 909:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Disable AHB3 peripherals clock. 910:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll AHB3ENR FMCEN LL_AHB3_GRP1_DisableClock\n 911:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB3ENR QSPIEN LL_AHB3_GRP1_DisableClock 912:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: 913:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*) 914:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI 915:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * 916:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. 917:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval None 918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ 919:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB3_GRP1_DisableClock(uint32_t Periphs) 920:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { 921:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** CLEAR_BIT(RCC->AHB3ENR, Periphs); 922:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } 923:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 924:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** 925:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Force AHB3 peripherals reset. 926:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll AHB3RSTR FMCRST LL_AHB3_GRP1_ForceReset\n 927:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB3RSTR QSPIRST LL_AHB3_GRP1_ForceReset 928:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: 929:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB3_GRP1_PERIPH_ALL 930:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*) 931:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI 932:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * 933:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. 934:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval None 935:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ 936:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB3_GRP1_ForceReset(uint32_t Periphs) 937:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { 938:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** SET_BIT(RCC->AHB3RSTR, Periphs); 939:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } 940:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 941:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** 942:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Release AHB3 peripherals reset. 943:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll AHB3RSTR FMCRST LL_AHB3_GRP1_ReleaseReset\n 944:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB3RSTR QSPIRST LL_AHB3_GRP1_ReleaseReset 945:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: 946:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_ALL 947:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*) 948:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI 949:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * 950:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. 951:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval None 952:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ 953:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB3_GRP1_ReleaseReset(uint32_t Periphs) 954:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { 955:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** CLEAR_BIT(RCC->AHB3RSTR, Periphs); 956:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } 957:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 958:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** 959:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Enable AHB3 peripheral clocks in low-power mode ARM GAS /tmp/ccLSPxIe.s page 260 960:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll AHB3LPENR FMCLPEN LL_AHB3_GRP1_EnableClockLowPower\n 961:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB3LPENR QSPILPEN LL_AHB3_GRP1_EnableClockLowPower 962:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: 963:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*) 964:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI 965:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * 966:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. 967:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval None 968:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ 969:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB3_GRP1_EnableClockLowPower(uint32_t Periphs) 970:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { 971:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __IO uint32_t tmpreg; 972:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** SET_BIT(RCC->AHB3LPENR, Periphs); 973:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Delay after an RCC peripheral clock enabling */ 974:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** tmpreg = READ_BIT(RCC->AHB3LPENR, Periphs); 975:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; 976:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } 977:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 978:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** 979:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Disable AHB3 peripheral clocks in low-power mode 980:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll AHB3LPENR FMCLPEN LL_AHB3_GRP1_DisableClockLowPower\n 981:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB3LPENR QSPILPEN LL_AHB3_GRP1_DisableClockLowPower 982:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: 983:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*) 984:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI 985:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * 986:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. 987:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval None 988:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ 989:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB3_GRP1_DisableClockLowPower(uint32_t Periphs) 990:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { 991:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** CLEAR_BIT(RCC->AHB3LPENR, Periphs); 992:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } 993:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 994:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** 995:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @} 996:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ 997:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 998:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** @defgroup BUS_LL_EF_APB1 APB1 999:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @{ 1000:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ 1001:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 1002:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** 1003:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Enable APB1 peripherals clock. 1004:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_EnableClock\n 1005:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR TIM3EN LL_APB1_GRP1_EnableClock\n 1006:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR TIM4EN LL_APB1_GRP1_EnableClock\n 1007:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR TIM5EN LL_APB1_GRP1_EnableClock\n 1008:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR TIM6EN LL_APB1_GRP1_EnableClock\n 1009:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR TIM7EN LL_APB1_GRP1_EnableClock\n 1010:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR TIM12EN LL_APB1_GRP1_EnableClock\n 1011:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR TIM13EN LL_APB1_GRP1_EnableClock\n 1012:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR TIM14EN LL_APB1_GRP1_EnableClock\n 1013:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR LPTIM1EN LL_APB1_GRP1_EnableClock\n 1014:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR WWDGEN LL_APB1_GRP1_EnableClock\n 1015:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR SPI2EN LL_APB1_GRP1_EnableClock\n 1016:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR SPI3EN LL_APB1_GRP1_EnableClock\n ARM GAS /tmp/ccLSPxIe.s page 261 1017:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR SPDIFRXEN LL_APB1_GRP1_EnableClock\n 1018:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR USART2EN LL_APB1_GRP1_EnableClock\n 1019:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR USART3EN LL_APB1_GRP1_EnableClock\n 1020:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR UART4EN LL_APB1_GRP1_EnableClock\n 1021:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR UART5EN LL_APB1_GRP1_EnableClock\n 1022:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR I2C1EN LL_APB1_GRP1_EnableClock\n 1023:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR I2C2EN LL_APB1_GRP1_EnableClock\n 1024:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR I2C3EN LL_APB1_GRP1_EnableClock\n 1025:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR I2C4EN LL_APB1_GRP1_EnableClock\n 1026:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR CAN1EN LL_APB1_GRP1_EnableClock\n 1027:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR CAN2EN LL_APB1_GRP1_EnableClock\n 1028:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR CAN3EN LL_APB1_GRP1_EnableClock\n 1029:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR CECEN LL_APB1_GRP1_EnableClock\n 1030:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR PWREN LL_APB1_GRP1_EnableClock\n 1031:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR DACEN LL_APB1_GRP1_EnableClock\n 1032:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR UART7EN LL_APB1_GRP1_EnableClock\n 1033:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR UART8EN LL_APB1_GRP1_EnableClock\n 1034:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR RTCEN LL_APB1_GRP1_EnableClock 1035:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: 1036:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 1037:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 1038:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 1039:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 1040:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 1041:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 1042:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 1043:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 1044:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 1045:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 1046:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_WWDG 1047:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 1048:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 1049:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*) 1050:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART2 1051:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART3 1052:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART4 1053:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART5 1054:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 1055:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 1056:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 1057:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C4 (*) 1058:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 1059:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*) 1060:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*) 1061:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) 1062:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_PWR 1063:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 1064:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART7 1065:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART8 1066:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*) 1067:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * 1068:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. 1069:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval None 1070:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ 1071:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs) 1072:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { 1073:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __IO uint32_t tmpreg; ARM GAS /tmp/ccLSPxIe.s page 262 1074:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** SET_BIT(RCC->APB1ENR, Periphs); 1075:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Delay after an RCC peripheral clock enabling */ 1076:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** tmpreg = READ_BIT(RCC->APB1ENR, Periphs); 1077:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; 1078:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } 1079:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 1080:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** 1081:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Check if APB1 peripheral clock is enabled or not 1082:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_IsEnabledClock\n 1083:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR TIM3EN LL_APB1_GRP1_IsEnabledClock\n 1084:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR TIM4EN LL_APB1_GRP1_IsEnabledClock\n 1085:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR TIM5EN LL_APB1_GRP1_IsEnabledClock\n 1086:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR TIM6EN LL_APB1_GRP1_IsEnabledClock\n 1087:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR TIM7EN LL_APB1_GRP1_IsEnabledClock\n 1088:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR TIM12EN LL_APB1_GRP1_IsEnabledClock\n 1089:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR TIM13EN LL_APB1_GRP1_IsEnabledClock\n 1090:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR TIM14EN LL_APB1_GRP1_IsEnabledClock\n 1091:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR LPTIM1EN LL_APB1_GRP1_IsEnabledClock\n 1092:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR WWDGEN LL_APB1_GRP1_IsEnabledClock\n 1093:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR SPI2EN LL_APB1_GRP1_IsEnabledClock\n 1094:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR SPI3EN LL_APB1_GRP1_IsEnabledClock\n 1095:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR SPDIFRXEN LL_APB1_GRP1_IsEnabledClock\n 1096:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR USART2EN LL_APB1_GRP1_IsEnabledClock\n 1097:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR USART3EN LL_APB1_GRP1_IsEnabledClock\n 1098:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR UART4EN LL_APB1_GRP1_IsEnabledClock\n 1099:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR UART5EN LL_APB1_GRP1_IsEnabledClock\n 1100:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR I2C1EN LL_APB1_GRP1_IsEnabledClock\n 1101:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR I2C2EN LL_APB1_GRP1_IsEnabledClock\n 1102:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR I2C3EN LL_APB1_GRP1_IsEnabledClock\n 1103:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR I2C4EN LL_APB1_GRP1_IsEnabledClock\n 1104:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR CAN1EN LL_APB1_GRP1_IsEnabledClock\n 1105:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR CAN2EN LL_APB1_GRP1_IsEnabledClock\n 1106:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR CAN3EN LL_APB1_GRP1_IsEnabledClock\n 1107:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR CECEN LL_APB1_GRP1_IsEnabledClock\n 1108:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR PWREN LL_APB1_GRP1_IsEnabledClock\n 1109:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR DACEN LL_APB1_GRP1_IsEnabledClock\n 1110:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR UART7EN LL_APB1_GRP1_IsEnabledClock\n 1111:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR UART8EN LL_APB1_GRP1_IsEnabledClock\n 1112:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR RTCEN LL_APB1_GRP1_IsEnabledClock 1113:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: 1114:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 1115:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 1116:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 1117:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 1118:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 1119:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 1120:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 1121:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 1122:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 1123:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 1124:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_WWDG 1125:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 1126:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 1127:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*) 1128:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART2 1129:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART3 1130:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART4 ARM GAS /tmp/ccLSPxIe.s page 263 1131:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART5 1132:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 1133:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 1134:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 1135:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C4 (*) 1136:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 1137:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*) 1138:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*) 1139:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) 1140:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_PWR 1141:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 1142:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART7 1143:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART8 1144:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*) 1145:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * 1146:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. 1147:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval State of Periphs (1 or 0). 1148:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ 1149:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs) 1150:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { 1151:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** return (READ_BIT(RCC->APB1ENR, Periphs) == Periphs); 1152:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } 1153:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 1154:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** 1155:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Disable APB1 peripherals clock. 1156:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_DisableClock\n 1157:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR TIM3EN LL_APB1_GRP1_DisableClock\n 1158:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR TIM4EN LL_APB1_GRP1_DisableClock\n 1159:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR TIM5EN LL_APB1_GRP1_DisableClock\n 1160:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR TIM6EN LL_APB1_GRP1_DisableClock\n 1161:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR TIM7EN LL_APB1_GRP1_DisableClock\n 1162:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR TIM12EN LL_APB1_GRP1_DisableClock\n 1163:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR TIM13EN LL_APB1_GRP1_DisableClock\n 1164:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR TIM14EN LL_APB1_GRP1_DisableClock\n 1165:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR LPTIM1EN LL_APB1_GRP1_DisableClock\n 1166:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR WWDGEN LL_APB1_GRP1_DisableClock\n 1167:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR SPI2EN LL_APB1_GRP1_DisableClock\n 1168:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR SPI3EN LL_APB1_GRP1_DisableClock\n 1169:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR SPDIFRXEN LL_APB1_GRP1_DisableClock\n 1170:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR USART2EN LL_APB1_GRP1_DisableClock\n 1171:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR USART3EN LL_APB1_GRP1_DisableClock\n 1172:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR UART4EN LL_APB1_GRP1_DisableClock\n 1173:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR UART5EN LL_APB1_GRP1_DisableClock\n 1174:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR I2C1EN LL_APB1_GRP1_DisableClock\n 1175:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR I2C2EN LL_APB1_GRP1_DisableClock\n 1176:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR I2C3EN LL_APB1_GRP1_DisableClock\n 1177:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR I2C4EN LL_APB1_GRP1_DisableClock\n 1178:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR CAN1EN LL_APB1_GRP1_DisableClock\n 1179:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR CAN2EN LL_APB1_GRP1_DisableClock\n 1180:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR CAN3EN LL_APB1_GRP1_DisableClock\n 1181:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR CECEN LL_APB1_GRP1_DisableClock\n 1182:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR PWREN LL_APB1_GRP1_DisableClock\n 1183:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR DACEN LL_APB1_GRP1_DisableClock\n 1184:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR UART7EN LL_APB1_GRP1_DisableClock\n 1185:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR UART8EN LL_APB1_GRP1_DisableClock\n 1186:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR RTCEN LL_APB1_GRP1_DisableClock 1187:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: ARM GAS /tmp/ccLSPxIe.s page 264 1188:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 1189:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 1190:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 1191:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 1192:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 1193:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 1194:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 1195:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 1196:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 1197:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 1198:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_WWDG 1199:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 1200:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 1201:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*) 1202:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART2 1203:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART3 1204:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART4 1205:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART5 1206:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 1207:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 1208:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 1209:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C4 (*) 1210:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 1211:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*) 1212:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*) 1213:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) 1214:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_PWR 1215:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 1216:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART7 1217:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART8 1218:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*) 1219:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * 1220:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. 1221:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval None 1222:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ 1223:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_APB1_GRP1_DisableClock(uint32_t Periphs) 1224:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { 1225:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** CLEAR_BIT(RCC->APB1ENR, Periphs); 1226:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } 1227:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 1228:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** 1229:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Force APB1 peripherals reset. 1230:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll APB1RSTR TIM2RST LL_APB1_GRP1_ForceReset\n 1231:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR TIM3RST LL_APB1_GRP1_ForceReset\n 1232:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR TIM4RST LL_APB1_GRP1_ForceReset\n 1233:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR TIM5RST LL_APB1_GRP1_ForceReset\n 1234:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR TIM6RST LL_APB1_GRP1_ForceReset\n 1235:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR TIM7RST LL_APB1_GRP1_ForceReset\n 1236:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR TIM12RST LL_APB1_GRP1_ForceReset\n 1237:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR TIM13RST LL_APB1_GRP1_ForceReset\n 1238:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR TIM14RST LL_APB1_GRP1_ForceReset\n 1239:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR LPTIM1RST LL_APB1_GRP1_ForceReset\n 1240:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR WWDGRST LL_APB1_GRP1_ForceReset\n 1241:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR SPI2RST LL_APB1_GRP1_ForceReset\n 1242:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR SPI3RST LL_APB1_GRP1_ForceReset\n 1243:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR SPDIFRXRST LL_APB1_GRP1_ForceReset\n 1244:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR USART2RST LL_APB1_GRP1_ForceReset\n ARM GAS /tmp/ccLSPxIe.s page 265 1245:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR USART3RST LL_APB1_GRP1_ForceReset\n 1246:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR UART4RST LL_APB1_GRP1_ForceReset\n 1247:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR UART5RST LL_APB1_GRP1_ForceReset\n 1248:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR I2C1RST LL_APB1_GRP1_ForceReset\n 1249:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR I2C2RST LL_APB1_GRP1_ForceReset\n 1250:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR I2C3RST LL_APB1_GRP1_ForceReset\n 1251:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR I2C4RST LL_APB1_GRP1_ForceReset\n 1252:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR CAN1RST LL_APB1_GRP1_ForceReset\n 1253:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR CAN2RST LL_APB1_GRP1_ForceReset\n 1254:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR CAN3RST LL_APB1_GRP1_ForceReset\n 1255:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR CECRST LL_APB1_GRP1_ForceReset\n 1256:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR PWRRST LL_APB1_GRP1_ForceReset\n 1257:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR DACRST LL_APB1_GRP1_ForceReset\n 1258:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR UART7RST LL_APB1_GRP1_ForceReset\n 1259:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR UART8RST LL_APB1_GRP1_ForceReset 1260:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: 1261:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 1262:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 1263:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 1264:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 1265:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 1266:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 1267:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 1268:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 1269:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 1270:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 1271:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_WWDG 1272:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 1273:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 1274:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*) 1275:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART2 1276:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART3 1277:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART4 1278:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART5 1279:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 1280:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 1281:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 1282:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C4 (*) 1283:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 1284:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*) 1285:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*) 1286:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) 1287:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_PWR 1288:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 1289:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART7 1290:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART8 1291:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * 1292:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. 1293:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval None 1294:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ 1295:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_APB1_GRP1_ForceReset(uint32_t Periphs) 1296:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { 1297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** SET_BIT(RCC->APB1RSTR, Periphs); 1298:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } 1299:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 1300:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** 1301:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Release APB1 peripherals reset. ARM GAS /tmp/ccLSPxIe.s page 266 1302:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll APB1RSTR TIM2RST LL_APB1_GRP1_ReleaseReset\n 1303:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR TIM3RST LL_APB1_GRP1_ReleaseReset\n 1304:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR TIM4RST LL_APB1_GRP1_ReleaseReset\n 1305:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR TIM5RST LL_APB1_GRP1_ReleaseReset\n 1306:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR TIM6RST LL_APB1_GRP1_ReleaseReset\n 1307:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR TIM7RST LL_APB1_GRP1_ReleaseReset\n 1308:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR TIM12RST LL_APB1_GRP1_ReleaseReset\n 1309:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR TIM13RST LL_APB1_GRP1_ReleaseReset\n 1310:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR TIM14RST LL_APB1_GRP1_ReleaseReset\n 1311:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR LPTIM1RST LL_APB1_GRP1_ReleaseReset\n 1312:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR WWDGRST LL_APB1_GRP1_ReleaseReset\n 1313:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR SPI2RST LL_APB1_GRP1_ReleaseReset\n 1314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR SPI3RST LL_APB1_GRP1_ReleaseReset\n 1315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR SPDIFRXRST LL_APB1_GRP1_ReleaseReset\n 1316:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR USART2RST LL_APB1_GRP1_ReleaseReset\n 1317:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR USART3RST LL_APB1_GRP1_ReleaseReset\n 1318:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR UART4RST LL_APB1_GRP1_ReleaseReset\n 1319:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR UART5RST LL_APB1_GRP1_ReleaseReset\n 1320:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR I2C1RST LL_APB1_GRP1_ReleaseReset\n 1321:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR I2C2RST LL_APB1_GRP1_ReleaseReset\n 1322:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR I2C3RST LL_APB1_GRP1_ReleaseReset\n 1323:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR I2C4RST LL_APB1_GRP1_ReleaseReset\n 1324:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR CAN1RST LL_APB1_GRP1_ReleaseReset\n 1325:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR CAN2RST LL_APB1_GRP1_ReleaseReset\n 1326:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR CAN3RST LL_APB1_GRP1_ReleaseReset\n 1327:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR CECRST LL_APB1_GRP1_ReleaseReset\n 1328:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR PWRRST LL_APB1_GRP1_ReleaseReset\n 1329:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR DACRST LL_APB1_GRP1_ReleaseReset\n 1330:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR UART7RST LL_APB1_GRP1_ReleaseReset\n 1331:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR UART8RST LL_APB1_GRP1_ReleaseReset 1332:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: 1333:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 1334:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 1335:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 1336:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 1337:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 1338:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 1339:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 1340:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 1341:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 1342:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 1343:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_WWDG 1344:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 1345:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 1346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*) 1347:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART2 1348:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART3 1349:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART4 1350:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART5 1351:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 1352:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 1353:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 1354:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C4 (*) 1355:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 1356:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*) 1357:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*) 1358:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) ARM GAS /tmp/ccLSPxIe.s page 267 1359:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_PWR 1360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 1361:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART7 1362:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART8 1363:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * 1364:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. 1365:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval None 1366:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ 1367:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_APB1_GRP1_ReleaseReset(uint32_t Periphs) 1368:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { 1369:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** CLEAR_BIT(RCC->APB1RSTR, Periphs); 1370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } 1371:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 1372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** 1373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Enable APB1 peripheral clocks in low-power mode 1374:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll APB1LPENR TIM2LPEN LL_APB1_GRP1_EnableClockLowPower\n 1375:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR TIM3LPEN LL_APB1_GRP1_EnableClockLowPower\n 1376:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR TIM4LPEN LL_APB1_GRP1_EnableClockLowPower\n 1377:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR TIM5LPEN LL_APB1_GRP1_EnableClockLowPower\n 1378:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR TIM6LPEN LL_APB1_GRP1_EnableClockLowPower\n 1379:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR TIM7LPEN LL_APB1_GRP1_EnableClockLowPower\n 1380:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR TIM12LPEN LL_APB1_GRP1_EnableClockLowPower\n 1381:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR TIM13LPEN LL_APB1_GRP1_EnableClockLowPower\n 1382:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR TIM14LPEN LL_APB1_GRP1_EnableClockLowPower\n 1383:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR LPTIM1LPEN LL_APB1_GRP1_EnableClockLowPower\n 1384:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR WWDGLPEN LL_APB1_GRP1_EnableClockLowPower\n 1385:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR SPI2LPEN LL_APB1_GRP1_EnableClockLowPower\n 1386:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR SPI3LPEN LL_APB1_GRP1_EnableClockLowPower\n 1387:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR SPDIFRXLPEN LL_APB1_GRP1_EnableClockLowPower\n 1388:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR USART2LPEN LL_APB1_GRP1_EnableClockLowPower\n 1389:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR USART3LPEN LL_APB1_GRP1_EnableClockLowPower\n 1390:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR UART4LPEN LL_APB1_GRP1_EnableClockLowPower\n 1391:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR UART5LPEN LL_APB1_GRP1_EnableClockLowPower\n 1392:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR I2C1LPEN LL_APB1_GRP1_EnableClockLowPower\n 1393:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR I2C2LPEN LL_APB1_GRP1_EnableClockLowPower\n 1394:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR I2C3LPEN LL_APB1_GRP1_EnableClockLowPower\n 1395:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR I2C4LPEN LL_APB1_GRP1_EnableClockLowPower\n 1396:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR CAN1LPEN LL_APB1_GRP1_EnableClockLowPower\n 1397:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR CAN2LPEN LL_APB1_GRP1_EnableClockLowPower\n 1398:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR CAN3LPEN LL_APB1_GRP1_EnableClockLowPower\n 1399:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR CECLPEN LL_APB1_GRP1_EnableClockLowPower\n 1400:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR PWRLPEN LL_APB1_GRP1_EnableClockLowPower\n 1401:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR DACLPEN LL_APB1_GRP1_EnableClockLowPower\n 1402:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR UART7LPEN LL_APB1_GRP1_EnableClockLowPower\n 1403:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR UART8LPEN LL_APB1_GRP1_EnableClockLowPower\n 1404:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR RTCLPEN LL_APB1_GRP1_EnableClockLowPower 1405:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: 1406:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 1407:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 1408:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 1409:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 1410:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 1411:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 1412:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 1413:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 1414:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 1415:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 ARM GAS /tmp/ccLSPxIe.s page 268 1416:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_WWDG 1417:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 1418:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 1419:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*) 1420:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART2 1421:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART3 1422:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART4 1423:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART5 1424:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 1425:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 1426:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 1427:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C4 (*) 1428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 1429:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*) 1430:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*) 1431:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) 1432:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_PWR 1433:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 1434:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART7 1435:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART8 1436:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*) 1437:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * 1438:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. 1439:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval None 1440:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ 1441:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_APB1_GRP1_EnableClockLowPower(uint32_t Periphs) 1442:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { 1443:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __IO uint32_t tmpreg; 1444:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** SET_BIT(RCC->APB1LPENR, Periphs); 1445:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Delay after an RCC peripheral clock enabling */ 1446:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** tmpreg = READ_BIT(RCC->APB1LPENR, Periphs); 1447:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; 1448:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } 1449:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 1450:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** 1451:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Disable APB1 peripheral clocks in low-power mode 1452:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll APB1LPENR TIM2LPEN LL_APB1_GRP1_DisableClockLowPower\n 1453:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR TIM3LPEN LL_APB1_GRP1_DisableClockLowPower\n 1454:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR TIM4LPEN LL_APB1_GRP1_DisableClockLowPower\n 1455:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR TIM5LPEN LL_APB1_GRP1_DisableClockLowPower\n 1456:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR TIM6LPEN LL_APB1_GRP1_DisableClockLowPower\n 1457:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR TIM7LPEN LL_APB1_GRP1_DisableClockLowPower\n 1458:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR TIM12LPEN LL_APB1_GRP1_DisableClockLowPower\n 1459:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR TIM13LPEN LL_APB1_GRP1_DisableClockLowPower\n 1460:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR TIM14LPEN LL_APB1_GRP1_DisableClockLowPower\n 1461:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR LPTIM1LPEN LL_APB1_GRP1_DisableClockLowPower\n 1462:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR WWDGLPEN LL_APB1_GRP1_DisableClockLowPower\n 1463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR SPI2LPEN LL_APB1_GRP1_DisableClockLowPower\n 1464:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR SPI3LPEN LL_APB1_GRP1_DisableClockLowPower\n 1465:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR SPDIFRXLPEN LL_APB1_GRP1_DisableClockLowPower\n 1466:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR USART2LPEN LL_APB1_GRP1_DisableClockLowPower\n 1467:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR USART3LPEN LL_APB1_GRP1_DisableClockLowPower\n 1468:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR UART4LPEN LL_APB1_GRP1_DisableClockLowPower\n 1469:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR UART5LPEN LL_APB1_GRP1_DisableClockLowPower\n 1470:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR I2C1LPEN LL_APB1_GRP1_DisableClockLowPower\n 1471:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR I2C2LPEN LL_APB1_GRP1_DisableClockLowPower\n 1472:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR I2C3LPEN LL_APB1_GRP1_DisableClockLowPower\n ARM GAS /tmp/ccLSPxIe.s page 269 1473:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR I2C4LPEN LL_APB1_GRP1_DisableClockLowPower\n 1474:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR CAN1LPEN LL_APB1_GRP1_DisableClockLowPower\n 1475:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR CAN2LPEN LL_APB1_GRP1_DisableClockLowPower\n 1476:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR CAN3LPEN LL_APB1_GRP1_DisableClockLowPower\n 1477:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR CECLPEN LL_APB1_GRP1_DisableClockLowPower\n 1478:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR PWRLPEN LL_APB1_GRP1_DisableClockLowPower\n 1479:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR DACLPEN LL_APB1_GRP1_DisableClockLowPower\n 1480:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR UART7LPEN LL_APB1_GRP1_DisableClockLowPower\n 1481:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR UART8LPEN LL_APB1_GRP1_DisableClockLowPower\n 1482:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR RTCLPEN LL_APB1_GRP1_DisableClockLowPower 1483:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: 1484:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 1485:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 1486:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 1487:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 1488:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 1489:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 1490:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 1491:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 1492:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 1493:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 1494:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_WWDG 1495:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 1496:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 1497:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*) 1498:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART2 1499:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART3 1500:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART4 1501:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART5 1502:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 1503:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 1504:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 1505:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C4 (*) 1506:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 1507:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*) 1508:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*) 1509:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) 1510:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_PWR 1511:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 1512:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART7 1513:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART8 1514:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*) 1515:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * 1516:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. 1517:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval None 1518:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ 1519:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_APB1_GRP1_DisableClockLowPower(uint32_t Periphs) 1520:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { 1521:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** CLEAR_BIT(RCC->APB1LPENR, Periphs); 1522:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } 1523:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 1524:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** 1525:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @} 1526:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ 1527:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 1528:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** @defgroup BUS_LL_EF_APB2 APB2 1529:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @{ ARM GAS /tmp/ccLSPxIe.s page 270 1530:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ 1531:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** 1532:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** 1533:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Enable APB2 peripherals clock. 1534:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll APB2ENR TIM1EN LL_APB2_GRP1_EnableClock\n 1535:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR TIM8EN LL_APB2_GRP1_EnableClock\n 1536:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR USART1EN LL_APB2_GRP1_EnableClock\n 1537:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR USART6EN LL_APB2_GRP1_EnableClock\n 1538:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR ADC1EN LL_APB2_GRP1_EnableClock\n 1539:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR ADC2EN LL_APB2_GRP1_EnableClock\n 1540:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR ADC3EN LL_APB2_GRP1_EnableClock\n 1541:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR SDMMC1EN LL_APB2_GRP1_EnableClock\n 1542:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR SDMMC2EN LL_APB2_GRP1_EnableClock\n 1543:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR SPI1EN LL_APB2_GRP1_EnableClock\n 1544:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR SPI4EN LL_APB2_GRP1_EnableClock\n 1545:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR SYSCFGEN LL_APB2_GRP1_EnableClock\n 1546:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR TIM9EN LL_APB2_GRP1_EnableClock\n 1547:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR TIM10EN LL_APB2_GRP1_EnableClock\n 1548:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR TIM11EN LL_APB2_GRP1_EnableClock\n 1549:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR SPI5EN LL_APB2_GRP1_EnableClock\n 1550:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR SPI6EN LL_APB2_GRP1_EnableClock\n 1551:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR SAI1EN LL_APB2_GRP1_EnableClock\n 1552:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR SAI2EN LL_APB2_GRP1_EnableClock\n 1553:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR LTDCEN LL_APB2_GRP1_EnableClock\n 1554:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR DSIEN LL_APB2_GRP1_EnableClock\n 1555:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR DFSDM1EN LL_APB2_GRP1_EnableClock\n 1556:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR MDIOEN LL_APB2_GRP1_EnableClock\n 1557:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR OTGPHYCEN LL_APB2_GRP1_EnableClock 1558:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: 1559:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 1560:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 1561:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_USART1 1562:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_USART6 1563:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_ADC1 1564:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_ADC2 1565:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_ADC3 1566:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1 1567:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC2 (*) 1568:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 1569:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 1570:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG 1571:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_TIM9 1572:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_TIM10 1573:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_TIM11 1574:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 1575:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*) 1576:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 1577:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 1578:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*) 1579:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*) 1580:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*) 1581:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_MDIO (*) 1582:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_OTGPHYC (*) 1583:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * 1584:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. 1585:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval None 1586:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ ARM GAS /tmp/ccLSPxIe.s page 271 1587:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_APB2_GRP1_EnableClock(uint32_t Periphs) 5208 .loc 3 1587 22 view .LVU1558 5209 .LBB484: 1588:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { 1589:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __IO uint32_t tmpreg; 5210 .loc 3 1589 3 view .LVU1559 1590:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** SET_BIT(RCC->APB2ENR, Periphs); 5211 .loc 3 1590 3 view .LVU1560 5212 001e 2A4B ldr r3, .L348 5213 0020 5A6C ldr r2, [r3, #68] 5214 0022 42F40052 orr r2, r2, #8192 5215 0026 5A64 str r2, [r3, #68] 1591:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Delay after an RCC peripheral clock enabling */ 1592:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** tmpreg = READ_BIT(RCC->APB2ENR, Periphs); 5216 .loc 3 1592 3 view .LVU1561 5217 .loc 3 1592 12 is_stmt 0 view .LVU1562 5218 0028 5A6C ldr r2, [r3, #68] 5219 002a 02F40052 and r2, r2, #8192 5220 .loc 3 1592 10 view .LVU1563 5221 002e 0192 str r2, [sp, #4] 1593:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; 5222 .loc 3 1593 3 is_stmt 1 view .LVU1564 5223 0030 019A ldr r2, [sp, #4] 5224 .LVL547: 5225 .loc 3 1593 3 is_stmt 0 view .LVU1565 5226 .LBE484: 5227 .LBE483: 1452:Src/main.c **** /**SPI4 GPIO Configuration 5228 .loc 1 1452 3 is_stmt 1 view .LVU1566 5229 .LBB485: 5230 .LBI485: 309:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { 5231 .loc 3 309 22 view .LVU1567 5232 .LBB486: 311:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** SET_BIT(RCC->AHB1ENR, Periphs); 5233 .loc 3 311 3 view .LVU1568 312:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Delay after an RCC peripheral clock enabling */ 5234 .loc 3 312 3 view .LVU1569 5235 0032 1A6B ldr r2, [r3, #48] 5236 0034 42F01002 orr r2, r2, #16 5237 0038 1A63 str r2, [r3, #48] 314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; 5238 .loc 3 314 3 view .LVU1570 314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; 5239 .loc 3 314 12 is_stmt 0 view .LVU1571 5240 003a 1B6B ldr r3, [r3, #48] 5241 003c 03F01003 and r3, r3, #16 314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; 5242 .loc 3 314 10 view .LVU1572 5243 0040 0093 str r3, [sp] 315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } 5244 .loc 3 315 3 is_stmt 1 view .LVU1573 5245 0042 009B ldr r3, [sp] 5246 .LVL548: 315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } 5247 .loc 3 315 3 is_stmt 0 view .LVU1574 5248 .LBE486: ARM GAS /tmp/ccLSPxIe.s page 272 5249 .LBE485: 1457:Src/main.c **** GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE; 5250 .loc 1 1457 3 is_stmt 1 view .LVU1575 1457:Src/main.c **** GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE; 5251 .loc 1 1457 23 is_stmt 0 view .LVU1576 5252 0044 4FF48053 mov r3, #4096 5253 0048 0293 str r3, [sp, #8] 1458:Src/main.c **** GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH; 5254 .loc 1 1458 3 is_stmt 1 view .LVU1577 1458:Src/main.c **** GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH; 5255 .loc 1 1458 24 is_stmt 0 view .LVU1578 5256 004a 0225 movs r5, #2 5257 004c 0395 str r5, [sp, #12] 1459:Src/main.c **** GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; 5258 .loc 1 1459 3 is_stmt 1 view .LVU1579 1459:Src/main.c **** GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; 5259 .loc 1 1459 25 is_stmt 0 view .LVU1580 5260 004e 4FF00308 mov r8, #3 5261 0052 CDF81080 str r8, [sp, #16] 1460:Src/main.c **** GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; 5262 .loc 1 1460 3 is_stmt 1 view .LVU1581 1461:Src/main.c **** GPIO_InitStruct.Alternate = LL_GPIO_AF_5; 5263 .loc 1 1461 3 view .LVU1582 1462:Src/main.c **** LL_GPIO_Init(GPIOE, &GPIO_InitStruct); 5264 .loc 1 1462 3 view .LVU1583 1462:Src/main.c **** LL_GPIO_Init(GPIOE, &GPIO_InitStruct); 5265 .loc 1 1462 29 is_stmt 0 view .LVU1584 5266 0056 0527 movs r7, #5 5267 0058 0797 str r7, [sp, #28] 1463:Src/main.c **** 5268 .loc 1 1463 3 is_stmt 1 view .LVU1585 5269 005a 1C4E ldr r6, .L348+4 5270 005c 02A9 add r1, sp, #8 5271 005e 3046 mov r0, r6 5272 0060 FFF7FEFF bl LL_GPIO_Init 5273 .LVL549: 1465:Src/main.c **** GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE; 5274 .loc 1 1465 3 view .LVU1586 1465:Src/main.c **** GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE; 5275 .loc 1 1465 23 is_stmt 0 view .LVU1587 5276 0064 4FF40053 mov r3, #8192 5277 0068 0293 str r3, [sp, #8] 1466:Src/main.c **** GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH; 5278 .loc 1 1466 3 is_stmt 1 view .LVU1588 1466:Src/main.c **** GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH; 5279 .loc 1 1466 24 is_stmt 0 view .LVU1589 5280 006a 0395 str r5, [sp, #12] 1467:Src/main.c **** GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; 5281 .loc 1 1467 3 is_stmt 1 view .LVU1590 1467:Src/main.c **** GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; 5282 .loc 1 1467 25 is_stmt 0 view .LVU1591 5283 006c CDF81080 str r8, [sp, #16] 1468:Src/main.c **** GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; 5284 .loc 1 1468 3 is_stmt 1 view .LVU1592 1468:Src/main.c **** GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; 5285 .loc 1 1468 30 is_stmt 0 view .LVU1593 5286 0070 0594 str r4, [sp, #20] ARM GAS /tmp/ccLSPxIe.s page 273 1469:Src/main.c **** GPIO_InitStruct.Alternate = LL_GPIO_AF_5; 5287 .loc 1 1469 3 is_stmt 1 view .LVU1594 1469:Src/main.c **** GPIO_InitStruct.Alternate = LL_GPIO_AF_5; 5288 .loc 1 1469 24 is_stmt 0 view .LVU1595 5289 0072 0694 str r4, [sp, #24] 1470:Src/main.c **** LL_GPIO_Init(GPIOE, &GPIO_InitStruct); 5290 .loc 1 1470 3 is_stmt 1 view .LVU1596 1470:Src/main.c **** LL_GPIO_Init(GPIOE, &GPIO_InitStruct); 5291 .loc 1 1470 29 is_stmt 0 view .LVU1597 5292 0074 0797 str r7, [sp, #28] 1471:Src/main.c **** 5293 .loc 1 1471 3 is_stmt 1 view .LVU1598 5294 0076 02A9 add r1, sp, #8 5295 0078 3046 mov r0, r6 5296 007a FFF7FEFF bl LL_GPIO_Init 5297 .LVL550: 1477:Src/main.c **** SPI_InitStruct.Mode = LL_SPI_MODE_MASTER; 5298 .loc 1 1477 3 view .LVU1599 1477:Src/main.c **** SPI_InitStruct.Mode = LL_SPI_MODE_MASTER; 5299 .loc 1 1477 36 is_stmt 0 view .LVU1600 5300 007e 4FF48063 mov r3, #1024 5301 0082 0893 str r3, [sp, #32] 1478:Src/main.c **** SPI_InitStruct.DataWidth = LL_SPI_DATAWIDTH_16BIT; 5302 .loc 1 1478 3 is_stmt 1 view .LVU1601 1478:Src/main.c **** SPI_InitStruct.DataWidth = LL_SPI_DATAWIDTH_16BIT; 5303 .loc 1 1478 23 is_stmt 0 view .LVU1602 5304 0084 4FF48273 mov r3, #260 5305 0088 0993 str r3, [sp, #36] 1479:Src/main.c **** SPI_InitStruct.ClockPolarity = LL_SPI_POLARITY_HIGH; 5306 .loc 1 1479 3 is_stmt 1 view .LVU1603 1479:Src/main.c **** SPI_InitStruct.ClockPolarity = LL_SPI_POLARITY_HIGH; 5307 .loc 1 1479 28 is_stmt 0 view .LVU1604 5308 008a 4FF47063 mov r3, #3840 5309 008e 0A93 str r3, [sp, #40] 1480:Src/main.c **** SPI_InitStruct.ClockPhase = LL_SPI_PHASE_1EDGE; 5310 .loc 1 1480 3 is_stmt 1 view .LVU1605 1480:Src/main.c **** SPI_InitStruct.ClockPhase = LL_SPI_PHASE_1EDGE; 5311 .loc 1 1480 32 is_stmt 0 view .LVU1606 5312 0090 0B95 str r5, [sp, #44] 1481:Src/main.c **** SPI_InitStruct.NSS = LL_SPI_NSS_SOFT; 5313 .loc 1 1481 3 is_stmt 1 view .LVU1607 1481:Src/main.c **** SPI_InitStruct.NSS = LL_SPI_NSS_SOFT; 5314 .loc 1 1481 29 is_stmt 0 view .LVU1608 5315 0092 0C94 str r4, [sp, #48] 1482:Src/main.c **** SPI_InitStruct.BaudRate = LL_SPI_BAUDRATEPRESCALER_DIV16; 5316 .loc 1 1482 3 is_stmt 1 view .LVU1609 1482:Src/main.c **** SPI_InitStruct.BaudRate = LL_SPI_BAUDRATEPRESCALER_DIV16; 5317 .loc 1 1482 22 is_stmt 0 view .LVU1610 5318 0094 4FF40073 mov r3, #512 5319 0098 0D93 str r3, [sp, #52] 1483:Src/main.c **** SPI_InitStruct.BitOrder = LL_SPI_MSB_FIRST; 5320 .loc 1 1483 3 is_stmt 1 view .LVU1611 1483:Src/main.c **** SPI_InitStruct.BitOrder = LL_SPI_MSB_FIRST; 5321 .loc 1 1483 27 is_stmt 0 view .LVU1612 5322 009a 1823 movs r3, #24 5323 009c 0E93 str r3, [sp, #56] 1484:Src/main.c **** SPI_InitStruct.CRCCalculation = LL_SPI_CRCCALCULATION_DISABLE; ARM GAS /tmp/ccLSPxIe.s page 274 5324 .loc 1 1484 3 is_stmt 1 view .LVU1613 1484:Src/main.c **** SPI_InitStruct.CRCCalculation = LL_SPI_CRCCALCULATION_DISABLE; 5325 .loc 1 1484 27 is_stmt 0 view .LVU1614 5326 009e 0F94 str r4, [sp, #60] 1485:Src/main.c **** SPI_InitStruct.CRCPoly = 7; 5327 .loc 1 1485 3 is_stmt 1 view .LVU1615 1485:Src/main.c **** SPI_InitStruct.CRCPoly = 7; 5328 .loc 1 1485 33 is_stmt 0 view .LVU1616 5329 00a0 1094 str r4, [sp, #64] 1486:Src/main.c **** LL_SPI_Init(SPI4, &SPI_InitStruct); 5330 .loc 1 1486 3 is_stmt 1 view .LVU1617 1486:Src/main.c **** LL_SPI_Init(SPI4, &SPI_InitStruct); 5331 .loc 1 1486 26 is_stmt 0 view .LVU1618 5332 00a2 0723 movs r3, #7 5333 00a4 1193 str r3, [sp, #68] 1487:Src/main.c **** LL_SPI_SetStandard(SPI4, LL_SPI_PROTOCOL_MOTOROLA); 5334 .loc 1 1487 3 is_stmt 1 view .LVU1619 5335 00a6 0A4C ldr r4, .L348+8 5336 00a8 08A9 add r1, sp, #32 5337 00aa 2046 mov r0, r4 5338 00ac FFF7FEFF bl LL_SPI_Init 5339 .LVL551: 1488:Src/main.c **** LL_SPI_DisableNSSPulseMgt(SPI4); 5340 .loc 1 1488 3 view .LVU1620 5341 .LBB487: 5342 .LBI487: 426:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 5343 .loc 4 426 22 view .LVU1621 5344 .LBB488: 428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 5345 .loc 4 428 3 view .LVU1622 5346 00b0 6368 ldr r3, [r4, #4] 5347 00b2 23F01003 bic r3, r3, #16 5348 00b6 6360 str r3, [r4, #4] 5349 .LVL552: 428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 5350 .loc 4 428 3 is_stmt 0 view .LVU1623 5351 .LBE488: 5352 .LBE487: 1489:Src/main.c **** /* USER CODE BEGIN SPI4_Init 2 */ 5353 .loc 1 1489 3 is_stmt 1 view .LVU1624 5354 .LBB489: 5355 .LBI489: 874:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 5356 .loc 4 874 22 view .LVU1625 5357 .LBB490: 876:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 5358 .loc 4 876 3 view .LVU1626 5359 00b8 6368 ldr r3, [r4, #4] 5360 00ba 23F00803 bic r3, r3, #8 5361 00be 6360 str r3, [r4, #4] 5362 .LVL553: 876:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 5363 .loc 4 876 3 is_stmt 0 view .LVU1627 5364 .LBE490: 5365 .LBE489: 1494:Src/main.c **** ARM GAS /tmp/ccLSPxIe.s page 275 5366 .loc 1 1494 1 view .LVU1628 5367 00c0 12B0 add sp, sp, #72 5368 .LCFI48: 5369 .cfi_def_cfa_offset 24 5370 @ sp needed 5371 00c2 BDE8F081 pop {r4, r5, r6, r7, r8, pc} 5372 .L349: 5373 00c6 00BF .align 2 5374 .L348: 5375 00c8 00380240 .word 1073887232 5376 00cc 00100240 .word 1073876992 5377 00d0 00340140 .word 1073820672 5378 .cfi_endproc 5379 .LFE1192: 5381 .section .text.MX_SPI2_Init,"ax",%progbits 5382 .align 1 5383 .syntax unified 5384 .thumb 5385 .thumb_func 5387 MX_SPI2_Init: 5388 .LFB1191: 1367:Src/main.c **** 5389 .loc 1 1367 1 is_stmt 1 view -0 5390 .cfi_startproc 5391 @ args = 0, pretend = 0, frame = 72 5392 @ frame_needed = 0, uses_anonymous_args = 0 5393 0000 2DE9F041 push {r4, r5, r6, r7, r8, lr} 5394 .LCFI49: 5395 .cfi_def_cfa_offset 24 5396 .cfi_offset 4, -24 5397 .cfi_offset 5, -20 5398 .cfi_offset 6, -16 5399 .cfi_offset 7, -12 5400 .cfi_offset 8, -8 5401 .cfi_offset 14, -4 5402 0004 92B0 sub sp, sp, #72 5403 .LCFI50: 5404 .cfi_def_cfa_offset 96 1373:Src/main.c **** 5405 .loc 1 1373 3 view .LVU1630 1373:Src/main.c **** 5406 .loc 1 1373 22 is_stmt 0 view .LVU1631 5407 0006 2822 movs r2, #40 5408 0008 0021 movs r1, #0 5409 000a 08A8 add r0, sp, #32 5410 000c FFF7FEFF bl memset 5411 .LVL554: 1375:Src/main.c **** 5412 .loc 1 1375 3 is_stmt 1 view .LVU1632 1375:Src/main.c **** 5413 .loc 1 1375 23 is_stmt 0 view .LVU1633 5414 0010 0024 movs r4, #0 5415 0012 0294 str r4, [sp, #8] 5416 0014 0394 str r4, [sp, #12] 5417 0016 0494 str r4, [sp, #16] 5418 0018 0594 str r4, [sp, #20] 5419 001a 0694 str r4, [sp, #24] ARM GAS /tmp/ccLSPxIe.s page 276 5420 001c 0794 str r4, [sp, #28] 1378:Src/main.c **** 5421 .loc 1 1378 3 is_stmt 1 view .LVU1634 5422 .LVL555: 5423 .LBB491: 5424 .LBI491: 1071:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { 5425 .loc 3 1071 22 view .LVU1635 5426 .LBB492: 1073:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** SET_BIT(RCC->APB1ENR, Periphs); 5427 .loc 3 1073 3 view .LVU1636 1074:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Delay after an RCC peripheral clock enabling */ 5428 .loc 3 1074 3 view .LVU1637 5429 001e 2F4B ldr r3, .L352 5430 0020 1A6C ldr r2, [r3, #64] 5431 0022 42F48042 orr r2, r2, #16384 5432 0026 1A64 str r2, [r3, #64] 1076:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; 5433 .loc 3 1076 3 view .LVU1638 1076:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; 5434 .loc 3 1076 12 is_stmt 0 view .LVU1639 5435 0028 1A6C ldr r2, [r3, #64] 5436 002a 02F48042 and r2, r2, #16384 1076:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; 5437 .loc 3 1076 10 view .LVU1640 5438 002e 0192 str r2, [sp, #4] 1077:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } 5439 .loc 3 1077 3 is_stmt 1 view .LVU1641 5440 0030 019A ldr r2, [sp, #4] 5441 .LVL556: 1077:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } 5442 .loc 3 1077 3 is_stmt 0 view .LVU1642 5443 .LBE492: 5444 .LBE491: 1380:Src/main.c **** /**SPI2 GPIO Configuration 5445 .loc 1 1380 3 is_stmt 1 view .LVU1643 5446 .LBB493: 5447 .LBI493: 309:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { 5448 .loc 3 309 22 view .LVU1644 5449 .LBB494: 311:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** SET_BIT(RCC->AHB1ENR, Periphs); 5450 .loc 3 311 3 view .LVU1645 312:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Delay after an RCC peripheral clock enabling */ 5451 .loc 3 312 3 view .LVU1646 5452 0032 1A6B ldr r2, [r3, #48] 5453 0034 42F00202 orr r2, r2, #2 5454 0038 1A63 str r2, [r3, #48] 314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; 5455 .loc 3 314 3 view .LVU1647 314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; 5456 .loc 3 314 12 is_stmt 0 view .LVU1648 5457 003a 1B6B ldr r3, [r3, #48] 5458 003c 03F00203 and r3, r3, #2 314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; 5459 .loc 3 314 10 view .LVU1649 5460 0040 0093 str r3, [sp] ARM GAS /tmp/ccLSPxIe.s page 277 315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } 5461 .loc 3 315 3 is_stmt 1 view .LVU1650 5462 0042 009B ldr r3, [sp] 5463 .LVL557: 315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } 5464 .loc 3 315 3 is_stmt 0 view .LVU1651 5465 .LBE494: 5466 .LBE493: 1386:Src/main.c **** GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE; 5467 .loc 1 1386 3 is_stmt 1 view .LVU1652 1386:Src/main.c **** GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE; 5468 .loc 1 1386 23 is_stmt 0 view .LVU1653 5469 0044 4FF40053 mov r3, #8192 5470 0048 0293 str r3, [sp, #8] 1387:Src/main.c **** GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH; 5471 .loc 1 1387 3 is_stmt 1 view .LVU1654 1387:Src/main.c **** GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH; 5472 .loc 1 1387 24 is_stmt 0 view .LVU1655 5473 004a 4FF00208 mov r8, #2 5474 004e CDF80C80 str r8, [sp, #12] 1388:Src/main.c **** GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; 5475 .loc 1 1388 3 is_stmt 1 view .LVU1656 1388:Src/main.c **** GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; 5476 .loc 1 1388 25 is_stmt 0 view .LVU1657 5477 0052 0327 movs r7, #3 5478 0054 0497 str r7, [sp, #16] 1389:Src/main.c **** GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; 5479 .loc 1 1389 3 is_stmt 1 view .LVU1658 1390:Src/main.c **** GPIO_InitStruct.Alternate = LL_GPIO_AF_5; 5480 .loc 1 1390 3 view .LVU1659 1391:Src/main.c **** LL_GPIO_Init(GPIOB, &GPIO_InitStruct); 5481 .loc 1 1391 3 view .LVU1660 1391:Src/main.c **** LL_GPIO_Init(GPIOB, &GPIO_InitStruct); 5482 .loc 1 1391 29 is_stmt 0 view .LVU1661 5483 0056 0526 movs r6, #5 5484 0058 0796 str r6, [sp, #28] 1392:Src/main.c **** 5485 .loc 1 1392 3 is_stmt 1 view .LVU1662 5486 005a 214D ldr r5, .L352+4 5487 005c 02A9 add r1, sp, #8 5488 005e 2846 mov r0, r5 5489 0060 FFF7FEFF bl LL_GPIO_Init 5490 .LVL558: 1394:Src/main.c **** GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE; 5491 .loc 1 1394 3 view .LVU1663 1394:Src/main.c **** GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE; 5492 .loc 1 1394 23 is_stmt 0 view .LVU1664 5493 0064 4FF48043 mov r3, #16384 5494 0068 0293 str r3, [sp, #8] 1395:Src/main.c **** GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH; 5495 .loc 1 1395 3 is_stmt 1 view .LVU1665 1395:Src/main.c **** GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH; 5496 .loc 1 1395 24 is_stmt 0 view .LVU1666 5497 006a CDF80C80 str r8, [sp, #12] 1396:Src/main.c **** GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; 5498 .loc 1 1396 3 is_stmt 1 view .LVU1667 1396:Src/main.c **** GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; ARM GAS /tmp/ccLSPxIe.s page 278 5499 .loc 1 1396 25 is_stmt 0 view .LVU1668 5500 006e 0497 str r7, [sp, #16] 1397:Src/main.c **** GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; 5501 .loc 1 1397 3 is_stmt 1 view .LVU1669 1397:Src/main.c **** GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; 5502 .loc 1 1397 30 is_stmt 0 view .LVU1670 5503 0070 0594 str r4, [sp, #20] 1398:Src/main.c **** GPIO_InitStruct.Alternate = LL_GPIO_AF_5; 5504 .loc 1 1398 3 is_stmt 1 view .LVU1671 1398:Src/main.c **** GPIO_InitStruct.Alternate = LL_GPIO_AF_5; 5505 .loc 1 1398 24 is_stmt 0 view .LVU1672 5506 0072 0694 str r4, [sp, #24] 1399:Src/main.c **** LL_GPIO_Init(GPIOB, &GPIO_InitStruct); 5507 .loc 1 1399 3 is_stmt 1 view .LVU1673 1399:Src/main.c **** LL_GPIO_Init(GPIOB, &GPIO_InitStruct); 5508 .loc 1 1399 29 is_stmt 0 view .LVU1674 5509 0074 0796 str r6, [sp, #28] 1400:Src/main.c **** 5510 .loc 1 1400 3 is_stmt 1 view .LVU1675 5511 0076 02A9 add r1, sp, #8 5512 0078 2846 mov r0, r5 5513 007a FFF7FEFF bl LL_GPIO_Init 5514 .LVL559: 1402:Src/main.c **** GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE; 5515 .loc 1 1402 3 view .LVU1676 1402:Src/main.c **** GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE; 5516 .loc 1 1402 23 is_stmt 0 view .LVU1677 5517 007e 4FF40043 mov r3, #32768 5518 0082 0293 str r3, [sp, #8] 1403:Src/main.c **** GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH; 5519 .loc 1 1403 3 is_stmt 1 view .LVU1678 1403:Src/main.c **** GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH; 5520 .loc 1 1403 24 is_stmt 0 view .LVU1679 5521 0084 CDF80C80 str r8, [sp, #12] 1404:Src/main.c **** GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; 5522 .loc 1 1404 3 is_stmt 1 view .LVU1680 1404:Src/main.c **** GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; 5523 .loc 1 1404 25 is_stmt 0 view .LVU1681 5524 0088 0497 str r7, [sp, #16] 1405:Src/main.c **** GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; 5525 .loc 1 1405 3 is_stmt 1 view .LVU1682 1405:Src/main.c **** GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; 5526 .loc 1 1405 30 is_stmt 0 view .LVU1683 5527 008a 0594 str r4, [sp, #20] 1406:Src/main.c **** GPIO_InitStruct.Alternate = LL_GPIO_AF_5; 5528 .loc 1 1406 3 is_stmt 1 view .LVU1684 1406:Src/main.c **** GPIO_InitStruct.Alternate = LL_GPIO_AF_5; 5529 .loc 1 1406 24 is_stmt 0 view .LVU1685 5530 008c 0694 str r4, [sp, #24] 1407:Src/main.c **** LL_GPIO_Init(GPIOB, &GPIO_InitStruct); 5531 .loc 1 1407 3 is_stmt 1 view .LVU1686 1407:Src/main.c **** LL_GPIO_Init(GPIOB, &GPIO_InitStruct); 5532 .loc 1 1407 29 is_stmt 0 view .LVU1687 5533 008e 0796 str r6, [sp, #28] 1408:Src/main.c **** 5534 .loc 1 1408 3 is_stmt 1 view .LVU1688 5535 0090 02A9 add r1, sp, #8 ARM GAS /tmp/ccLSPxIe.s page 279 5536 0092 2846 mov r0, r5 5537 0094 FFF7FEFF bl LL_GPIO_Init 5538 .LVL560: 1414:Src/main.c **** SPI_InitStruct.Mode = LL_SPI_MODE_MASTER; 5539 .loc 1 1414 3 view .LVU1689 1414:Src/main.c **** SPI_InitStruct.Mode = LL_SPI_MODE_MASTER; 5540 .loc 1 1414 36 is_stmt 0 view .LVU1690 5541 0098 0894 str r4, [sp, #32] 1415:Src/main.c **** SPI_InitStruct.DataWidth = LL_SPI_DATAWIDTH_16BIT; 5542 .loc 1 1415 3 is_stmt 1 view .LVU1691 1415:Src/main.c **** SPI_InitStruct.DataWidth = LL_SPI_DATAWIDTH_16BIT; 5543 .loc 1 1415 23 is_stmt 0 view .LVU1692 5544 009a 4FF48273 mov r3, #260 5545 009e 0993 str r3, [sp, #36] 1416:Src/main.c **** SPI_InitStruct.ClockPolarity = LL_SPI_POLARITY_LOW; 5546 .loc 1 1416 3 is_stmt 1 view .LVU1693 1416:Src/main.c **** SPI_InitStruct.ClockPolarity = LL_SPI_POLARITY_LOW; 5547 .loc 1 1416 28 is_stmt 0 view .LVU1694 5548 00a0 4FF47063 mov r3, #3840 5549 00a4 0A93 str r3, [sp, #40] 1417:Src/main.c **** SPI_InitStruct.ClockPhase = LL_SPI_PHASE_1EDGE; 5550 .loc 1 1417 3 is_stmt 1 view .LVU1695 1417:Src/main.c **** SPI_InitStruct.ClockPhase = LL_SPI_PHASE_1EDGE; 5551 .loc 1 1417 32 is_stmt 0 view .LVU1696 5552 00a6 0B94 str r4, [sp, #44] 1418:Src/main.c **** SPI_InitStruct.NSS = LL_SPI_NSS_SOFT; 5553 .loc 1 1418 3 is_stmt 1 view .LVU1697 1418:Src/main.c **** SPI_InitStruct.NSS = LL_SPI_NSS_SOFT; 5554 .loc 1 1418 29 is_stmt 0 view .LVU1698 5555 00a8 0C94 str r4, [sp, #48] 1419:Src/main.c **** SPI_InitStruct.BaudRate = LL_SPI_BAUDRATEPRESCALER_DIV8; 5556 .loc 1 1419 3 is_stmt 1 view .LVU1699 1419:Src/main.c **** SPI_InitStruct.BaudRate = LL_SPI_BAUDRATEPRESCALER_DIV8; 5557 .loc 1 1419 22 is_stmt 0 view .LVU1700 5558 00aa 4FF40073 mov r3, #512 5559 00ae 0D93 str r3, [sp, #52] 1420:Src/main.c **** SPI_InitStruct.BitOrder = LL_SPI_MSB_FIRST; 5560 .loc 1 1420 3 is_stmt 1 view .LVU1701 1420:Src/main.c **** SPI_InitStruct.BitOrder = LL_SPI_MSB_FIRST; 5561 .loc 1 1420 27 is_stmt 0 view .LVU1702 5562 00b0 1023 movs r3, #16 5563 00b2 0E93 str r3, [sp, #56] 1421:Src/main.c **** SPI_InitStruct.CRCCalculation = LL_SPI_CRCCALCULATION_DISABLE; 5564 .loc 1 1421 3 is_stmt 1 view .LVU1703 1421:Src/main.c **** SPI_InitStruct.CRCCalculation = LL_SPI_CRCCALCULATION_DISABLE; 5565 .loc 1 1421 27 is_stmt 0 view .LVU1704 5566 00b4 0F94 str r4, [sp, #60] 1422:Src/main.c **** SPI_InitStruct.CRCPoly = 7; 5567 .loc 1 1422 3 is_stmt 1 view .LVU1705 1422:Src/main.c **** SPI_InitStruct.CRCPoly = 7; 5568 .loc 1 1422 33 is_stmt 0 view .LVU1706 5569 00b6 1094 str r4, [sp, #64] 1423:Src/main.c **** LL_SPI_Init(SPI2, &SPI_InitStruct); 5570 .loc 1 1423 3 is_stmt 1 view .LVU1707 1423:Src/main.c **** LL_SPI_Init(SPI2, &SPI_InitStruct); 5571 .loc 1 1423 26 is_stmt 0 view .LVU1708 5572 00b8 0723 movs r3, #7 ARM GAS /tmp/ccLSPxIe.s page 280 5573 00ba 1193 str r3, [sp, #68] 1424:Src/main.c **** LL_SPI_SetStandard(SPI2, LL_SPI_PROTOCOL_MOTOROLA); 5574 .loc 1 1424 3 is_stmt 1 view .LVU1709 5575 00bc 094C ldr r4, .L352+8 5576 00be 08A9 add r1, sp, #32 5577 00c0 2046 mov r0, r4 5578 00c2 FFF7FEFF bl LL_SPI_Init 5579 .LVL561: 1425:Src/main.c **** LL_SPI_DisableNSSPulseMgt(SPI2); 5580 .loc 1 1425 3 view .LVU1710 5581 .LBB495: 5582 .LBI495: 426:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 5583 .loc 4 426 22 view .LVU1711 5584 .LBB496: 428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 5585 .loc 4 428 3 view .LVU1712 5586 00c6 6368 ldr r3, [r4, #4] 5587 00c8 23F01003 bic r3, r3, #16 5588 00cc 6360 str r3, [r4, #4] 5589 .LVL562: 428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 5590 .loc 4 428 3 is_stmt 0 view .LVU1713 5591 .LBE496: 5592 .LBE495: 1426:Src/main.c **** /* USER CODE BEGIN SPI2_Init 2 */ 5593 .loc 1 1426 3 is_stmt 1 view .LVU1714 5594 .LBB497: 5595 .LBI497: 874:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 5596 .loc 4 874 22 view .LVU1715 5597 .LBB498: 876:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 5598 .loc 4 876 3 view .LVU1716 5599 00ce 6368 ldr r3, [r4, #4] 5600 00d0 23F00803 bic r3, r3, #8 5601 00d4 6360 str r3, [r4, #4] 5602 .LVL563: 876:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 5603 .loc 4 876 3 is_stmt 0 view .LVU1717 5604 .LBE498: 5605 .LBE497: 1431:Src/main.c **** 5606 .loc 1 1431 1 view .LVU1718 5607 00d6 12B0 add sp, sp, #72 5608 .LCFI51: 5609 .cfi_def_cfa_offset 24 5610 @ sp needed 5611 00d8 BDE8F081 pop {r4, r5, r6, r7, r8, pc} 5612 .L353: 5613 .align 2 5614 .L352: 5615 00dc 00380240 .word 1073887232 5616 00e0 00040240 .word 1073873920 5617 00e4 00380040 .word 1073756160 5618 .cfi_endproc 5619 .LFE1191: ARM GAS /tmp/ccLSPxIe.s page 281 5621 .section .text.MX_SPI5_Init,"ax",%progbits 5622 .align 1 5623 .syntax unified 5624 .thumb 5625 .thumb_func 5627 MX_SPI5_Init: 5628 .LFB1193: 1502:Src/main.c **** 5629 .loc 1 1502 1 is_stmt 1 view -0 5630 .cfi_startproc 5631 @ args = 0, pretend = 0, frame = 72 5632 @ frame_needed = 0, uses_anonymous_args = 0 5633 0000 2DE9F041 push {r4, r5, r6, r7, r8, lr} 5634 .LCFI52: 5635 .cfi_def_cfa_offset 24 5636 .cfi_offset 4, -24 5637 .cfi_offset 5, -20 5638 .cfi_offset 6, -16 5639 .cfi_offset 7, -12 5640 .cfi_offset 8, -8 5641 .cfi_offset 14, -4 5642 0004 92B0 sub sp, sp, #72 5643 .LCFI53: 5644 .cfi_def_cfa_offset 96 1508:Src/main.c **** 5645 .loc 1 1508 3 view .LVU1720 1508:Src/main.c **** 5646 .loc 1 1508 22 is_stmt 0 view .LVU1721 5647 0006 2822 movs r2, #40 5648 0008 0021 movs r1, #0 5649 000a 08A8 add r0, sp, #32 5650 000c FFF7FEFF bl memset 5651 .LVL564: 1510:Src/main.c **** 5652 .loc 1 1510 3 is_stmt 1 view .LVU1722 1510:Src/main.c **** 5653 .loc 1 1510 23 is_stmt 0 view .LVU1723 5654 0010 0024 movs r4, #0 5655 0012 0294 str r4, [sp, #8] 5656 0014 0394 str r4, [sp, #12] 5657 0016 0494 str r4, [sp, #16] 5658 0018 0594 str r4, [sp, #20] 5659 001a 0694 str r4, [sp, #24] 5660 001c 0794 str r4, [sp, #28] 1513:Src/main.c **** 5661 .loc 1 1513 3 is_stmt 1 view .LVU1724 5662 .LVL565: 5663 .LBB499: 5664 .LBI499: 1587:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { 5665 .loc 3 1587 22 view .LVU1725 5666 .LBB500: 1589:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** SET_BIT(RCC->APB2ENR, Periphs); 5667 .loc 3 1589 3 view .LVU1726 1590:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Delay after an RCC peripheral clock enabling */ 5668 .loc 3 1590 3 view .LVU1727 5669 001e 294B ldr r3, .L356 ARM GAS /tmp/ccLSPxIe.s page 282 5670 0020 5A6C ldr r2, [r3, #68] 5671 0022 42F48012 orr r2, r2, #1048576 5672 0026 5A64 str r2, [r3, #68] 1592:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; 5673 .loc 3 1592 3 view .LVU1728 1592:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; 5674 .loc 3 1592 12 is_stmt 0 view .LVU1729 5675 0028 5A6C ldr r2, [r3, #68] 5676 002a 02F48012 and r2, r2, #1048576 1592:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; 5677 .loc 3 1592 10 view .LVU1730 5678 002e 0192 str r2, [sp, #4] 5679 .loc 3 1593 3 is_stmt 1 view .LVU1731 5680 0030 019A ldr r2, [sp, #4] 5681 .LVL566: 5682 .loc 3 1593 3 is_stmt 0 view .LVU1732 5683 .LBE500: 5684 .LBE499: 1515:Src/main.c **** /**SPI5 GPIO Configuration 5685 .loc 1 1515 3 is_stmt 1 view .LVU1733 5686 .LBB501: 5687 .LBI501: 309:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { 5688 .loc 3 309 22 view .LVU1734 5689 .LBB502: 311:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** SET_BIT(RCC->AHB1ENR, Periphs); 5690 .loc 3 311 3 view .LVU1735 312:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Delay after an RCC peripheral clock enabling */ 5691 .loc 3 312 3 view .LVU1736 5692 0032 1A6B ldr r2, [r3, #48] 5693 0034 42F02002 orr r2, r2, #32 5694 0038 1A63 str r2, [r3, #48] 314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; 5695 .loc 3 314 3 view .LVU1737 314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; 5696 .loc 3 314 12 is_stmt 0 view .LVU1738 5697 003a 1B6B ldr r3, [r3, #48] 5698 003c 03F02003 and r3, r3, #32 314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; 5699 .loc 3 314 10 view .LVU1739 5700 0040 0093 str r3, [sp] 315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } 5701 .loc 3 315 3 is_stmt 1 view .LVU1740 5702 0042 009B ldr r3, [sp] 5703 .LVL567: 315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } 5704 .loc 3 315 3 is_stmt 0 view .LVU1741 5705 .LBE502: 5706 .LBE501: 1520:Src/main.c **** GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE; 5707 .loc 1 1520 3 is_stmt 1 view .LVU1742 1520:Src/main.c **** GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE; 5708 .loc 1 1520 23 is_stmt 0 view .LVU1743 5709 0044 8023 movs r3, #128 5710 0046 0293 str r3, [sp, #8] 1521:Src/main.c **** GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH; 5711 .loc 1 1521 3 is_stmt 1 view .LVU1744 ARM GAS /tmp/ccLSPxIe.s page 283 1521:Src/main.c **** GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH; 5712 .loc 1 1521 24 is_stmt 0 view .LVU1745 5713 0048 0225 movs r5, #2 5714 004a 0395 str r5, [sp, #12] 1522:Src/main.c **** GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; 5715 .loc 1 1522 3 is_stmt 1 view .LVU1746 1522:Src/main.c **** GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; 5716 .loc 1 1522 25 is_stmt 0 view .LVU1747 5717 004c 4FF00308 mov r8, #3 5718 0050 CDF81080 str r8, [sp, #16] 1523:Src/main.c **** GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; 5719 .loc 1 1523 3 is_stmt 1 view .LVU1748 1524:Src/main.c **** GPIO_InitStruct.Alternate = LL_GPIO_AF_5; 5720 .loc 1 1524 3 view .LVU1749 1525:Src/main.c **** LL_GPIO_Init(GPIOF, &GPIO_InitStruct); 5721 .loc 1 1525 3 view .LVU1750 1525:Src/main.c **** LL_GPIO_Init(GPIOF, &GPIO_InitStruct); 5722 .loc 1 1525 29 is_stmt 0 view .LVU1751 5723 0054 0527 movs r7, #5 5724 0056 0797 str r7, [sp, #28] 1526:Src/main.c **** 5725 .loc 1 1526 3 is_stmt 1 view .LVU1752 5726 0058 1B4E ldr r6, .L356+4 5727 005a 02A9 add r1, sp, #8 5728 005c 3046 mov r0, r6 5729 005e FFF7FEFF bl LL_GPIO_Init 5730 .LVL568: 1528:Src/main.c **** GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE; 5731 .loc 1 1528 3 view .LVU1753 1528:Src/main.c **** GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE; 5732 .loc 1 1528 23 is_stmt 0 view .LVU1754 5733 0062 4FF48073 mov r3, #256 5734 0066 0293 str r3, [sp, #8] 1529:Src/main.c **** GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH; 5735 .loc 1 1529 3 is_stmt 1 view .LVU1755 1529:Src/main.c **** GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH; 5736 .loc 1 1529 24 is_stmt 0 view .LVU1756 5737 0068 0395 str r5, [sp, #12] 1530:Src/main.c **** GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; 5738 .loc 1 1530 3 is_stmt 1 view .LVU1757 1530:Src/main.c **** GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; 5739 .loc 1 1530 25 is_stmt 0 view .LVU1758 5740 006a CDF81080 str r8, [sp, #16] 1531:Src/main.c **** GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; 5741 .loc 1 1531 3 is_stmt 1 view .LVU1759 1531:Src/main.c **** GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; 5742 .loc 1 1531 30 is_stmt 0 view .LVU1760 5743 006e 0594 str r4, [sp, #20] 1532:Src/main.c **** GPIO_InitStruct.Alternate = LL_GPIO_AF_5; 5744 .loc 1 1532 3 is_stmt 1 view .LVU1761 1532:Src/main.c **** GPIO_InitStruct.Alternate = LL_GPIO_AF_5; 5745 .loc 1 1532 24 is_stmt 0 view .LVU1762 5746 0070 0694 str r4, [sp, #24] 1533:Src/main.c **** LL_GPIO_Init(GPIOF, &GPIO_InitStruct); 5747 .loc 1 1533 3 is_stmt 1 view .LVU1763 1533:Src/main.c **** LL_GPIO_Init(GPIOF, &GPIO_InitStruct); 5748 .loc 1 1533 29 is_stmt 0 view .LVU1764 ARM GAS /tmp/ccLSPxIe.s page 284 5749 0072 0797 str r7, [sp, #28] 1534:Src/main.c **** 5750 .loc 1 1534 3 is_stmt 1 view .LVU1765 5751 0074 02A9 add r1, sp, #8 5752 0076 3046 mov r0, r6 5753 0078 FFF7FEFF bl LL_GPIO_Init 5754 .LVL569: 1540:Src/main.c **** SPI_InitStruct.Mode = LL_SPI_MODE_MASTER; 5755 .loc 1 1540 3 view .LVU1766 1540:Src/main.c **** SPI_InitStruct.Mode = LL_SPI_MODE_MASTER; 5756 .loc 1 1540 36 is_stmt 0 view .LVU1767 5757 007c 4FF48063 mov r3, #1024 5758 0080 0893 str r3, [sp, #32] 1541:Src/main.c **** SPI_InitStruct.DataWidth = LL_SPI_DATAWIDTH_16BIT; 5759 .loc 1 1541 3 is_stmt 1 view .LVU1768 1541:Src/main.c **** SPI_InitStruct.DataWidth = LL_SPI_DATAWIDTH_16BIT; 5760 .loc 1 1541 23 is_stmt 0 view .LVU1769 5761 0082 4FF48273 mov r3, #260 5762 0086 0993 str r3, [sp, #36] 1542:Src/main.c **** SPI_InitStruct.ClockPolarity = LL_SPI_POLARITY_HIGH; 5763 .loc 1 1542 3 is_stmt 1 view .LVU1770 1542:Src/main.c **** SPI_InitStruct.ClockPolarity = LL_SPI_POLARITY_HIGH; 5764 .loc 1 1542 28 is_stmt 0 view .LVU1771 5765 0088 4FF47063 mov r3, #3840 5766 008c 0A93 str r3, [sp, #40] 1543:Src/main.c **** SPI_InitStruct.ClockPhase = LL_SPI_PHASE_1EDGE; 5767 .loc 1 1543 3 is_stmt 1 view .LVU1772 1543:Src/main.c **** SPI_InitStruct.ClockPhase = LL_SPI_PHASE_1EDGE; 5768 .loc 1 1543 32 is_stmt 0 view .LVU1773 5769 008e 0B95 str r5, [sp, #44] 1544:Src/main.c **** SPI_InitStruct.NSS = LL_SPI_NSS_SOFT; 5770 .loc 1 1544 3 is_stmt 1 view .LVU1774 1544:Src/main.c **** SPI_InitStruct.NSS = LL_SPI_NSS_SOFT; 5771 .loc 1 1544 29 is_stmt 0 view .LVU1775 5772 0090 0C94 str r4, [sp, #48] 1545:Src/main.c **** SPI_InitStruct.BaudRate = LL_SPI_BAUDRATEPRESCALER_DIV16; 5773 .loc 1 1545 3 is_stmt 1 view .LVU1776 1545:Src/main.c **** SPI_InitStruct.BaudRate = LL_SPI_BAUDRATEPRESCALER_DIV16; 5774 .loc 1 1545 22 is_stmt 0 view .LVU1777 5775 0092 4FF40073 mov r3, #512 5776 0096 0D93 str r3, [sp, #52] 1546:Src/main.c **** SPI_InitStruct.BitOrder = LL_SPI_MSB_FIRST; 5777 .loc 1 1546 3 is_stmt 1 view .LVU1778 1546:Src/main.c **** SPI_InitStruct.BitOrder = LL_SPI_MSB_FIRST; 5778 .loc 1 1546 27 is_stmt 0 view .LVU1779 5779 0098 1823 movs r3, #24 5780 009a 0E93 str r3, [sp, #56] 1547:Src/main.c **** SPI_InitStruct.CRCCalculation = LL_SPI_CRCCALCULATION_DISABLE; 5781 .loc 1 1547 3 is_stmt 1 view .LVU1780 1547:Src/main.c **** SPI_InitStruct.CRCCalculation = LL_SPI_CRCCALCULATION_DISABLE; 5782 .loc 1 1547 27 is_stmt 0 view .LVU1781 5783 009c 0F94 str r4, [sp, #60] 1548:Src/main.c **** SPI_InitStruct.CRCPoly = 7; 5784 .loc 1 1548 3 is_stmt 1 view .LVU1782 1548:Src/main.c **** SPI_InitStruct.CRCPoly = 7; 5785 .loc 1 1548 33 is_stmt 0 view .LVU1783 5786 009e 1094 str r4, [sp, #64] ARM GAS /tmp/ccLSPxIe.s page 285 1549:Src/main.c **** LL_SPI_Init(SPI5, &SPI_InitStruct); 5787 .loc 1 1549 3 is_stmt 1 view .LVU1784 1549:Src/main.c **** LL_SPI_Init(SPI5, &SPI_InitStruct); 5788 .loc 1 1549 26 is_stmt 0 view .LVU1785 5789 00a0 0723 movs r3, #7 5790 00a2 1193 str r3, [sp, #68] 1550:Src/main.c **** LL_SPI_SetStandard(SPI5, LL_SPI_PROTOCOL_MOTOROLA); 5791 .loc 1 1550 3 is_stmt 1 view .LVU1786 5792 00a4 094C ldr r4, .L356+8 5793 00a6 08A9 add r1, sp, #32 5794 00a8 2046 mov r0, r4 5795 00aa FFF7FEFF bl LL_SPI_Init 5796 .LVL570: 1551:Src/main.c **** LL_SPI_DisableNSSPulseMgt(SPI5); 5797 .loc 1 1551 3 view .LVU1787 5798 .LBB503: 5799 .LBI503: 426:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 5800 .loc 4 426 22 view .LVU1788 5801 .LBB504: 428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 5802 .loc 4 428 3 view .LVU1789 5803 00ae 6368 ldr r3, [r4, #4] 5804 00b0 23F01003 bic r3, r3, #16 5805 00b4 6360 str r3, [r4, #4] 5806 .LVL571: 428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 5807 .loc 4 428 3 is_stmt 0 view .LVU1790 5808 .LBE504: 5809 .LBE503: 1552:Src/main.c **** /* USER CODE BEGIN SPI5_Init 2 */ 5810 .loc 1 1552 3 is_stmt 1 view .LVU1791 5811 .LBB505: 5812 .LBI505: 874:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 5813 .loc 4 874 22 view .LVU1792 5814 .LBB506: 876:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 5815 .loc 4 876 3 view .LVU1793 5816 00b6 6368 ldr r3, [r4, #4] 5817 00b8 23F00803 bic r3, r3, #8 5818 00bc 6360 str r3, [r4, #4] 5819 .LVL572: 876:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 5820 .loc 4 876 3 is_stmt 0 view .LVU1794 5821 .LBE506: 5822 .LBE505: 1557:Src/main.c **** 5823 .loc 1 1557 1 view .LVU1795 5824 00be 12B0 add sp, sp, #72 5825 .LCFI54: 5826 .cfi_def_cfa_offset 24 5827 @ sp needed 5828 00c0 BDE8F081 pop {r4, r5, r6, r7, r8, pc} 5829 .L357: 5830 .align 2 5831 .L356: ARM GAS /tmp/ccLSPxIe.s page 286 5832 00c4 00380240 .word 1073887232 5833 00c8 00140240 .word 1073878016 5834 00cc 00500140 .word 1073827840 5835 .cfi_endproc 5836 .LFE1193: 5838 .section .text.MX_SPI6_Init,"ax",%progbits 5839 .align 1 5840 .syntax unified 5841 .thumb 5842 .thumb_func 5844 MX_SPI6_Init: 5845 .LFB1194: 1565:Src/main.c **** 5846 .loc 1 1565 1 is_stmt 1 view -0 5847 .cfi_startproc 5848 @ args = 0, pretend = 0, frame = 72 5849 @ frame_needed = 0, uses_anonymous_args = 0 5850 0000 2DE9F041 push {r4, r5, r6, r7, r8, lr} 5851 .LCFI55: 5852 .cfi_def_cfa_offset 24 5853 .cfi_offset 4, -24 5854 .cfi_offset 5, -20 5855 .cfi_offset 6, -16 5856 .cfi_offset 7, -12 5857 .cfi_offset 8, -8 5858 .cfi_offset 14, -4 5859 0004 92B0 sub sp, sp, #72 5860 .LCFI56: 5861 .cfi_def_cfa_offset 96 1571:Src/main.c **** 5862 .loc 1 1571 3 view .LVU1797 1571:Src/main.c **** 5863 .loc 1 1571 22 is_stmt 0 view .LVU1798 5864 0006 2822 movs r2, #40 5865 0008 0021 movs r1, #0 5866 000a 08A8 add r0, sp, #32 5867 000c FFF7FEFF bl memset 5868 .LVL573: 1573:Src/main.c **** 5869 .loc 1 1573 3 is_stmt 1 view .LVU1799 1573:Src/main.c **** 5870 .loc 1 1573 23 is_stmt 0 view .LVU1800 5871 0010 0024 movs r4, #0 5872 0012 0294 str r4, [sp, #8] 5873 0014 0394 str r4, [sp, #12] 5874 0016 0494 str r4, [sp, #16] 5875 0018 0594 str r4, [sp, #20] 5876 001a 0694 str r4, [sp, #24] 5877 001c 0794 str r4, [sp, #28] 1576:Src/main.c **** 5878 .loc 1 1576 3 is_stmt 1 view .LVU1801 5879 .LVL574: 5880 .LBB507: 5881 .LBI507: 1587:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { 5882 .loc 3 1587 22 view .LVU1802 5883 .LBB508: ARM GAS /tmp/ccLSPxIe.s page 287 1589:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** SET_BIT(RCC->APB2ENR, Periphs); 5884 .loc 3 1589 3 view .LVU1803 1590:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Delay after an RCC peripheral clock enabling */ 5885 .loc 3 1590 3 view .LVU1804 5886 001e 294B ldr r3, .L360 5887 0020 5A6C ldr r2, [r3, #68] 5888 0022 42F40012 orr r2, r2, #2097152 5889 0026 5A64 str r2, [r3, #68] 1592:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; 5890 .loc 3 1592 3 view .LVU1805 1592:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; 5891 .loc 3 1592 12 is_stmt 0 view .LVU1806 5892 0028 5A6C ldr r2, [r3, #68] 5893 002a 02F40012 and r2, r2, #2097152 1592:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; 5894 .loc 3 1592 10 view .LVU1807 5895 002e 0192 str r2, [sp, #4] 5896 .loc 3 1593 3 is_stmt 1 view .LVU1808 5897 0030 019A ldr r2, [sp, #4] 5898 .LVL575: 5899 .loc 3 1593 3 is_stmt 0 view .LVU1809 5900 .LBE508: 5901 .LBE507: 1578:Src/main.c **** /**SPI6 GPIO Configuration 5902 .loc 1 1578 3 is_stmt 1 view .LVU1810 5903 .LBB509: 5904 .LBI509: 309:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { 5905 .loc 3 309 22 view .LVU1811 5906 .LBB510: 311:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** SET_BIT(RCC->AHB1ENR, Periphs); 5907 .loc 3 311 3 view .LVU1812 312:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Delay after an RCC peripheral clock enabling */ 5908 .loc 3 312 3 view .LVU1813 5909 0032 1A6B ldr r2, [r3, #48] 5910 0034 42F00102 orr r2, r2, #1 5911 0038 1A63 str r2, [r3, #48] 314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; 5912 .loc 3 314 3 view .LVU1814 314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; 5913 .loc 3 314 12 is_stmt 0 view .LVU1815 5914 003a 1B6B ldr r3, [r3, #48] 5915 003c 03F00103 and r3, r3, #1 314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; 5916 .loc 3 314 10 view .LVU1816 5917 0040 0093 str r3, [sp] 315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } 5918 .loc 3 315 3 is_stmt 1 view .LVU1817 5919 0042 009B ldr r3, [sp] 5920 .LVL576: 315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } 5921 .loc 3 315 3 is_stmt 0 view .LVU1818 5922 .LBE510: 5923 .LBE509: 1583:Src/main.c **** GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE; 5924 .loc 1 1583 3 is_stmt 1 view .LVU1819 1583:Src/main.c **** GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE; ARM GAS /tmp/ccLSPxIe.s page 288 5925 .loc 1 1583 23 is_stmt 0 view .LVU1820 5926 0044 2023 movs r3, #32 5927 0046 0293 str r3, [sp, #8] 1584:Src/main.c **** GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH; 5928 .loc 1 1584 3 is_stmt 1 view .LVU1821 1584:Src/main.c **** GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH; 5929 .loc 1 1584 24 is_stmt 0 view .LVU1822 5930 0048 0225 movs r5, #2 5931 004a 0395 str r5, [sp, #12] 1585:Src/main.c **** GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; 5932 .loc 1 1585 3 is_stmt 1 view .LVU1823 1585:Src/main.c **** GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; 5933 .loc 1 1585 25 is_stmt 0 view .LVU1824 5934 004c 4FF00308 mov r8, #3 5935 0050 CDF81080 str r8, [sp, #16] 1586:Src/main.c **** GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; 5936 .loc 1 1586 3 is_stmt 1 view .LVU1825 1587:Src/main.c **** GPIO_InitStruct.Alternate = LL_GPIO_AF_8; 5937 .loc 1 1587 3 view .LVU1826 1588:Src/main.c **** LL_GPIO_Init(GPIOA, &GPIO_InitStruct); 5938 .loc 1 1588 3 view .LVU1827 1588:Src/main.c **** LL_GPIO_Init(GPIOA, &GPIO_InitStruct); 5939 .loc 1 1588 29 is_stmt 0 view .LVU1828 5940 0054 0827 movs r7, #8 5941 0056 0797 str r7, [sp, #28] 1589:Src/main.c **** 5942 .loc 1 1589 3 is_stmt 1 view .LVU1829 5943 0058 1B4E ldr r6, .L360+4 5944 005a 0DEB0701 add r1, sp, r7 5945 005e 3046 mov r0, r6 5946 0060 FFF7FEFF bl LL_GPIO_Init 5947 .LVL577: 1591:Src/main.c **** GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE; 5948 .loc 1 1591 3 view .LVU1830 1591:Src/main.c **** GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE; 5949 .loc 1 1591 23 is_stmt 0 view .LVU1831 5950 0064 8023 movs r3, #128 5951 0066 0293 str r3, [sp, #8] 1592:Src/main.c **** GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH; 5952 .loc 1 1592 3 is_stmt 1 view .LVU1832 1592:Src/main.c **** GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH; 5953 .loc 1 1592 24 is_stmt 0 view .LVU1833 5954 0068 0395 str r5, [sp, #12] 1593:Src/main.c **** GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; 5955 .loc 1 1593 3 is_stmt 1 view .LVU1834 1593:Src/main.c **** GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; 5956 .loc 1 1593 25 is_stmt 0 view .LVU1835 5957 006a CDF81080 str r8, [sp, #16] 1594:Src/main.c **** GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; 5958 .loc 1 1594 3 is_stmt 1 view .LVU1836 1594:Src/main.c **** GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; 5959 .loc 1 1594 30 is_stmt 0 view .LVU1837 5960 006e 0594 str r4, [sp, #20] 1595:Src/main.c **** GPIO_InitStruct.Alternate = LL_GPIO_AF_8; 5961 .loc 1 1595 3 is_stmt 1 view .LVU1838 1595:Src/main.c **** GPIO_InitStruct.Alternate = LL_GPIO_AF_8; 5962 .loc 1 1595 24 is_stmt 0 view .LVU1839 ARM GAS /tmp/ccLSPxIe.s page 289 5963 0070 0694 str r4, [sp, #24] 1596:Src/main.c **** LL_GPIO_Init(GPIOA, &GPIO_InitStruct); 5964 .loc 1 1596 3 is_stmt 1 view .LVU1840 1596:Src/main.c **** LL_GPIO_Init(GPIOA, &GPIO_InitStruct); 5965 .loc 1 1596 29 is_stmt 0 view .LVU1841 5966 0072 0797 str r7, [sp, #28] 1597:Src/main.c **** 5967 .loc 1 1597 3 is_stmt 1 view .LVU1842 5968 0074 0DEB0701 add r1, sp, r7 5969 0078 3046 mov r0, r6 5970 007a FFF7FEFF bl LL_GPIO_Init 5971 .LVL578: 1603:Src/main.c **** SPI_InitStruct.Mode = LL_SPI_MODE_MASTER; 5972 .loc 1 1603 3 view .LVU1843 1603:Src/main.c **** SPI_InitStruct.Mode = LL_SPI_MODE_MASTER; 5973 .loc 1 1603 36 is_stmt 0 view .LVU1844 5974 007e 0894 str r4, [sp, #32] 1604:Src/main.c **** SPI_InitStruct.DataWidth = LL_SPI_DATAWIDTH_16BIT; 5975 .loc 1 1604 3 is_stmt 1 view .LVU1845 1604:Src/main.c **** SPI_InitStruct.DataWidth = LL_SPI_DATAWIDTH_16BIT; 5976 .loc 1 1604 23 is_stmt 0 view .LVU1846 5977 0080 4FF48273 mov r3, #260 5978 0084 0993 str r3, [sp, #36] 1605:Src/main.c **** SPI_InitStruct.ClockPolarity = LL_SPI_POLARITY_HIGH; 5979 .loc 1 1605 3 is_stmt 1 view .LVU1847 1605:Src/main.c **** SPI_InitStruct.ClockPolarity = LL_SPI_POLARITY_HIGH; 5980 .loc 1 1605 28 is_stmt 0 view .LVU1848 5981 0086 4FF47063 mov r3, #3840 5982 008a 0A93 str r3, [sp, #40] 1606:Src/main.c **** SPI_InitStruct.ClockPhase = LL_SPI_PHASE_2EDGE; 5983 .loc 1 1606 3 is_stmt 1 view .LVU1849 1606:Src/main.c **** SPI_InitStruct.ClockPhase = LL_SPI_PHASE_2EDGE; 5984 .loc 1 1606 32 is_stmt 0 view .LVU1850 5985 008c 0B95 str r5, [sp, #44] 1607:Src/main.c **** SPI_InitStruct.NSS = LL_SPI_NSS_SOFT; 5986 .loc 1 1607 3 is_stmt 1 view .LVU1851 1607:Src/main.c **** SPI_InitStruct.NSS = LL_SPI_NSS_SOFT; 5987 .loc 1 1607 29 is_stmt 0 view .LVU1852 5988 008e 0123 movs r3, #1 5989 0090 0C93 str r3, [sp, #48] 1608:Src/main.c **** SPI_InitStruct.BaudRate = LL_SPI_BAUDRATEPRESCALER_DIV16; 5990 .loc 1 1608 3 is_stmt 1 view .LVU1853 1608:Src/main.c **** SPI_InitStruct.BaudRate = LL_SPI_BAUDRATEPRESCALER_DIV16; 5991 .loc 1 1608 22 is_stmt 0 view .LVU1854 5992 0092 4FF40073 mov r3, #512 5993 0096 0D93 str r3, [sp, #52] 1609:Src/main.c **** SPI_InitStruct.BitOrder = LL_SPI_MSB_FIRST; 5994 .loc 1 1609 3 is_stmt 1 view .LVU1855 1609:Src/main.c **** SPI_InitStruct.BitOrder = LL_SPI_MSB_FIRST; 5995 .loc 1 1609 27 is_stmt 0 view .LVU1856 5996 0098 1823 movs r3, #24 5997 009a 0E93 str r3, [sp, #56] 1610:Src/main.c **** SPI_InitStruct.CRCCalculation = LL_SPI_CRCCALCULATION_DISABLE; 5998 .loc 1 1610 3 is_stmt 1 view .LVU1857 1610:Src/main.c **** SPI_InitStruct.CRCCalculation = LL_SPI_CRCCALCULATION_DISABLE; 5999 .loc 1 1610 27 is_stmt 0 view .LVU1858 6000 009c 0F94 str r4, [sp, #60] ARM GAS /tmp/ccLSPxIe.s page 290 1611:Src/main.c **** SPI_InitStruct.CRCPoly = 7; 6001 .loc 1 1611 3 is_stmt 1 view .LVU1859 1611:Src/main.c **** SPI_InitStruct.CRCPoly = 7; 6002 .loc 1 1611 33 is_stmt 0 view .LVU1860 6003 009e 1094 str r4, [sp, #64] 1612:Src/main.c **** LL_SPI_Init(SPI6, &SPI_InitStruct); 6004 .loc 1 1612 3 is_stmt 1 view .LVU1861 1612:Src/main.c **** LL_SPI_Init(SPI6, &SPI_InitStruct); 6005 .loc 1 1612 26 is_stmt 0 view .LVU1862 6006 00a0 0723 movs r3, #7 6007 00a2 1193 str r3, [sp, #68] 1613:Src/main.c **** LL_SPI_SetStandard(SPI6, LL_SPI_PROTOCOL_MOTOROLA); 6008 .loc 1 1613 3 is_stmt 1 view .LVU1863 6009 00a4 094C ldr r4, .L360+8 6010 00a6 08A9 add r1, sp, #32 6011 00a8 2046 mov r0, r4 6012 00aa FFF7FEFF bl LL_SPI_Init 6013 .LVL579: 1614:Src/main.c **** LL_SPI_DisableNSSPulseMgt(SPI6); 6014 .loc 1 1614 3 view .LVU1864 6015 .LBB511: 6016 .LBI511: 426:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 6017 .loc 4 426 22 view .LVU1865 6018 .LBB512: 428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 6019 .loc 4 428 3 view .LVU1866 6020 00ae 6368 ldr r3, [r4, #4] 6021 00b0 23F01003 bic r3, r3, #16 6022 00b4 6360 str r3, [r4, #4] 6023 .LVL580: 428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 6024 .loc 4 428 3 is_stmt 0 view .LVU1867 6025 .LBE512: 6026 .LBE511: 1615:Src/main.c **** /* USER CODE BEGIN SPI6_Init 2 */ 6027 .loc 1 1615 3 is_stmt 1 view .LVU1868 6028 .LBB513: 6029 .LBI513: 874:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 6030 .loc 4 874 22 view .LVU1869 6031 .LBB514: 876:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 6032 .loc 4 876 3 view .LVU1870 6033 00b6 6368 ldr r3, [r4, #4] 6034 00b8 23F00803 bic r3, r3, #8 6035 00bc 6360 str r3, [r4, #4] 6036 .LVL581: 876:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 6037 .loc 4 876 3 is_stmt 0 view .LVU1871 6038 .LBE514: 6039 .LBE513: 1620:Src/main.c **** 6040 .loc 1 1620 1 view .LVU1872 6041 00be 12B0 add sp, sp, #72 6042 .LCFI57: 6043 .cfi_def_cfa_offset 24 ARM GAS /tmp/ccLSPxIe.s page 291 6044 @ sp needed 6045 00c0 BDE8F081 pop {r4, r5, r6, r7, r8, pc} 6046 .L361: 6047 .align 2 6048 .L360: 6049 00c4 00380240 .word 1073887232 6050 00c8 00000240 .word 1073872896 6051 00cc 00540140 .word 1073828864 6052 .cfi_endproc 6053 .LFE1194: 6055 .section .text.MX_TIM2_Init,"ax",%progbits 6056 .align 1 6057 .syntax unified 6058 .thumb 6059 .thumb_func 6061 MX_TIM2_Init: 6062 .LFB1195: 1628:Src/main.c **** 6063 .loc 1 1628 1 is_stmt 1 view -0 6064 .cfi_startproc 6065 @ args = 0, pretend = 0, frame = 24 6066 @ frame_needed = 0, uses_anonymous_args = 0 6067 0000 10B5 push {r4, lr} 6068 .LCFI58: 6069 .cfi_def_cfa_offset 8 6070 .cfi_offset 4, -8 6071 .cfi_offset 14, -4 6072 0002 86B0 sub sp, sp, #24 6073 .LCFI59: 6074 .cfi_def_cfa_offset 32 1634:Src/main.c **** 6075 .loc 1 1634 3 view .LVU1874 1634:Src/main.c **** 6076 .loc 1 1634 22 is_stmt 0 view .LVU1875 6077 0004 0024 movs r4, #0 6078 0006 0194 str r4, [sp, #4] 6079 0008 0294 str r4, [sp, #8] 6080 000a 0394 str r4, [sp, #12] 6081 000c 0494 str r4, [sp, #16] 6082 000e 0594 str r4, [sp, #20] 1637:Src/main.c **** 6083 .loc 1 1637 3 is_stmt 1 view .LVU1876 6084 .LVL582: 6085 .LBB515: 6086 .LBI515: 1071:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { 6087 .loc 3 1071 22 view .LVU1877 6088 .LBB516: 1073:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** SET_BIT(RCC->APB1ENR, Periphs); 6089 .loc 3 1073 3 view .LVU1878 1074:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Delay after an RCC peripheral clock enabling */ 6090 .loc 3 1074 3 view .LVU1879 6091 0010 1D4B ldr r3, .L364 6092 0012 1A6C ldr r2, [r3, #64] 6093 0014 42F00102 orr r2, r2, #1 6094 0018 1A64 str r2, [r3, #64] 1076:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; ARM GAS /tmp/ccLSPxIe.s page 292 6095 .loc 3 1076 3 view .LVU1880 1076:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; 6096 .loc 3 1076 12 is_stmt 0 view .LVU1881 6097 001a 1B6C ldr r3, [r3, #64] 6098 001c 03F00103 and r3, r3, #1 1076:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; 6099 .loc 3 1076 10 view .LVU1882 6100 0020 0093 str r3, [sp] 1077:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } 6101 .loc 3 1077 3 is_stmt 1 view .LVU1883 6102 0022 009B ldr r3, [sp] 6103 .LVL583: 1077:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } 6104 .loc 3 1077 3 is_stmt 0 view .LVU1884 6105 .LBE516: 6106 .LBE515: 1640:Src/main.c **** NVIC_EnableIRQ(TIM2_IRQn); 6107 .loc 1 1640 3 is_stmt 1 view .LVU1885 6108 .LBB517: 6109 .LBI517: 1884:Drivers/CMSIS/Include/core_cm7.h **** { 6110 .loc 2 1884 26 view .LVU1886 6111 .LBB518: 1886:Drivers/CMSIS/Include/core_cm7.h **** } 6112 .loc 2 1886 3 view .LVU1887 1886:Drivers/CMSIS/Include/core_cm7.h **** } 6113 .loc 2 1886 26 is_stmt 0 view .LVU1888 6114 0024 194B ldr r3, .L364+4 6115 0026 D868 ldr r0, [r3, #12] 6116 .LBE518: 6117 .LBE517: 1640:Src/main.c **** NVIC_EnableIRQ(TIM2_IRQn); 6118 .loc 1 1640 3 discriminator 1 view .LVU1889 6119 0028 2246 mov r2, r4 6120 002a 2146 mov r1, r4 6121 002c C0F30220 ubfx r0, r0, #8, #3 6122 0030 FFF7FEFF bl NVIC_EncodePriority 6123 .LVL584: 6124 .LBB519: 6125 .LBI519: 2024:Drivers/CMSIS/Include/core_cm7.h **** { 6126 .loc 2 2024 22 is_stmt 1 view .LVU1890 6127 .LBB520: 2026:Drivers/CMSIS/Include/core_cm7.h **** { 6128 .loc 2 2026 3 view .LVU1891 2028:Drivers/CMSIS/Include/core_cm7.h **** } 6129 .loc 2 2028 5 view .LVU1892 2028:Drivers/CMSIS/Include/core_cm7.h **** } 6130 .loc 2 2028 49 is_stmt 0 view .LVU1893 6131 0034 0001 lsls r0, r0, #4 6132 .LVL585: 2028:Drivers/CMSIS/Include/core_cm7.h **** } 6133 .loc 2 2028 49 view .LVU1894 6134 0036 C0B2 uxtb r0, r0 2028:Drivers/CMSIS/Include/core_cm7.h **** } 6135 .loc 2 2028 47 view .LVU1895 6136 0038 154B ldr r3, .L364+8 ARM GAS /tmp/ccLSPxIe.s page 293 6137 003a 83F81C03 strb r0, [r3, #796] 6138 .LVL586: 2028:Drivers/CMSIS/Include/core_cm7.h **** } 6139 .loc 2 2028 47 view .LVU1896 6140 .LBE520: 6141 .LBE519: 1641:Src/main.c **** 6142 .loc 1 1641 3 is_stmt 1 view .LVU1897 6143 .LBB521: 6144 .LBI521: 1896:Drivers/CMSIS/Include/core_cm7.h **** { 6145 .loc 2 1896 22 view .LVU1898 6146 .LBB522: 1898:Drivers/CMSIS/Include/core_cm7.h **** { 6147 .loc 2 1898 3 view .LVU1899 1900:Drivers/CMSIS/Include/core_cm7.h **** } 6148 .loc 2 1900 5 view .LVU1900 1900:Drivers/CMSIS/Include/core_cm7.h **** } 6149 .loc 2 1900 43 is_stmt 0 view .LVU1901 6150 003e 4FF08052 mov r2, #268435456 6151 0042 1A60 str r2, [r3] 6152 .LVL587: 1900:Drivers/CMSIS/Include/core_cm7.h **** } 6153 .loc 2 1900 43 view .LVU1902 6154 .LBE522: 6155 .LBE521: 1646:Src/main.c **** TIM_InitStruct.CounterMode = LL_TIM_COUNTERMODE_UP; 6156 .loc 1 1646 3 is_stmt 1 view .LVU1903 1646:Src/main.c **** TIM_InitStruct.CounterMode = LL_TIM_COUNTERMODE_UP; 6157 .loc 1 1646 28 is_stmt 0 view .LVU1904 6158 0044 4FF47A73 mov r3, #1000 6159 0048 ADF80430 strh r3, [sp, #4] @ movhi 1647:Src/main.c **** TIM_InitStruct.Autoreload = 840000; 6160 .loc 1 1647 3 is_stmt 1 view .LVU1905 1647:Src/main.c **** TIM_InitStruct.Autoreload = 840000; 6161 .loc 1 1647 30 is_stmt 0 view .LVU1906 6162 004c 0294 str r4, [sp, #8] 1648:Src/main.c **** TIM_InitStruct.ClockDivision = LL_TIM_CLOCKDIVISION_DIV1; 6163 .loc 1 1648 3 is_stmt 1 view .LVU1907 1648:Src/main.c **** TIM_InitStruct.ClockDivision = LL_TIM_CLOCKDIVISION_DIV1; 6164 .loc 1 1648 29 is_stmt 0 view .LVU1908 6165 004e 114B ldr r3, .L364+12 6166 0050 0393 str r3, [sp, #12] 1649:Src/main.c **** LL_TIM_Init(TIM2, &TIM_InitStruct); 6167 .loc 1 1649 3 is_stmt 1 view .LVU1909 1649:Src/main.c **** LL_TIM_Init(TIM2, &TIM_InitStruct); 6168 .loc 1 1649 32 is_stmt 0 view .LVU1910 6169 0052 0494 str r4, [sp, #16] 1650:Src/main.c **** LL_TIM_DisableARRPreload(TIM2); 6170 .loc 1 1650 3 is_stmt 1 view .LVU1911 6171 0054 01A9 add r1, sp, #4 6172 0056 4FF08040 mov r0, #1073741824 6173 005a FFF7FEFF bl LL_TIM_Init 6174 .LVL588: 1651:Src/main.c **** LL_TIM_SetClockSource(TIM2, LL_TIM_CLOCKSOURCE_INTERNAL); 6175 .loc 1 1651 3 view .LVU1912 6176 .LBB523: ARM GAS /tmp/ccLSPxIe.s page 294 6177 .LBI523: 6178 .file 5 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h" 1:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 2:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** ****************************************************************************** 3:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @file stm32f7xx_ll_tim.h 4:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @author MCD Application Team 5:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Header file of TIM LL module. 6:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** ****************************************************************************** 7:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @attention 8:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * 9:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * Copyright (c) 2017 STMicroelectronics. 10:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * All rights reserved. 11:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * 12:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * This software is licensed under terms that can be found in the LICENSE file 13:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * in the root directory of this software component. 14:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * If no LICENSE file comes with this software, it is provided AS-IS. 15:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * 16:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** ****************************************************************************** 17:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 18:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 19:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /* Define to prevent recursive inclusion -------------------------------------*/ 20:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #ifndef __STM32F7xx_LL_TIM_H 21:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define __STM32F7xx_LL_TIM_H 22:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 23:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #ifdef __cplusplus 24:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** extern "C" { 25:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #endif 26:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 27:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /* Includes ------------------------------------------------------------------*/ 28:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #include "stm32f7xx.h" 29:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 30:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @addtogroup STM32F7xx_LL_Driver 31:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ 32:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 33:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 34:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #if defined (TIM1) || defined (TIM8) || defined (TIM2) || defined (TIM3) || defined (TIM4) || defi 35:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 36:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL TIM 37:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ 38:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 39:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 40:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /* Private types -------------------------------------------------------------*/ 41:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /* Private variables ---------------------------------------------------------*/ 42:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_Private_Variables TIM Private Variables 43:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ 44:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 45:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** static const uint8_t OFFSET_TAB_CCMRx[] = 46:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 47:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 0x00U, /* 0: TIMx_CH1 */ 48:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 0x00U, /* 1: TIMx_CH1N */ 49:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 0x00U, /* 2: TIMx_CH2 */ 50:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 0x00U, /* 3: TIMx_CH2N */ 51:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 0x04U, /* 4: TIMx_CH3 */ 52:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 0x04U, /* 5: TIMx_CH3N */ 53:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 0x04U, /* 6: TIMx_CH4 */ 54:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 0x3CU, /* 7: TIMx_CH5 */ 55:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 0x3CU /* 8: TIMx_CH6 */ ARM GAS /tmp/ccLSPxIe.s page 295 56:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }; 57:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 58:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** static const uint8_t SHIFT_TAB_OCxx[] = 59:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 60:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 0U, /* 0: OC1M, OC1FE, OC1PE */ 61:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 0U, /* 1: - NA */ 62:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 8U, /* 2: OC2M, OC2FE, OC2PE */ 63:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 0U, /* 3: - NA */ 64:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 0U, /* 4: OC3M, OC3FE, OC3PE */ 65:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 0U, /* 5: - NA */ 66:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 8U, /* 6: OC4M, OC4FE, OC4PE */ 67:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 0U, /* 7: OC5M, OC5FE, OC5PE */ 68:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 8U /* 8: OC6M, OC6FE, OC6PE */ 69:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }; 70:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 71:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** static const uint8_t SHIFT_TAB_ICxx[] = 72:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 73:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 0U, /* 0: CC1S, IC1PSC, IC1F */ 74:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 0U, /* 1: - NA */ 75:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 8U, /* 2: CC2S, IC2PSC, IC2F */ 76:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 0U, /* 3: - NA */ 77:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 0U, /* 4: CC3S, IC3PSC, IC3F */ 78:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 0U, /* 5: - NA */ 79:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 8U, /* 6: CC4S, IC4PSC, IC4F */ 80:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 0U, /* 7: - NA */ 81:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 0U /* 8: - NA */ 82:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }; 83:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 84:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** static const uint8_t SHIFT_TAB_CCxP[] = 85:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 86:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 0U, /* 0: CC1P */ 87:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 2U, /* 1: CC1NP */ 88:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 4U, /* 2: CC2P */ 89:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 6U, /* 3: CC2NP */ 90:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 8U, /* 4: CC3P */ 91:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 10U, /* 5: CC3NP */ 92:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 12U, /* 6: CC4P */ 93:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 16U, /* 7: CC5P */ 94:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 20U /* 8: CC6P */ 95:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }; 96:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 97:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** static const uint8_t SHIFT_TAB_OISx[] = 98:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 99:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 0U, /* 0: OIS1 */ 100:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1U, /* 1: OIS1N */ 101:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 2U, /* 2: OIS2 */ 102:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3U, /* 3: OIS2N */ 103:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 4U, /* 4: OIS3 */ 104:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 5U, /* 5: OIS3N */ 105:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 6U, /* 6: OIS4 */ 106:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 8U, /* 7: OIS5 */ 107:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 10U /* 8: OIS6 */ 108:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }; 109:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 110:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} 111:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 112:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** ARM GAS /tmp/ccLSPxIe.s page 296 113:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /* Private constants ---------------------------------------------------------*/ 114:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_Private_Constants TIM Private Constants 115:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ 116:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 117:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 118:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #if defined(TIM_BREAK_INPUT_SUPPORT) 119:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /* Defines used for the bit position in the register and perform offsets */ 120:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define TIM_POSITION_BRK_SOURCE (POSITION_VAL(Source) & 0x1FUL) 121:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 122:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /* Generic bit definitions for TIMx_AF1 register */ 123:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define TIMx_AF1_BKINP TIM1_AF1_BKINP /*!< BRK BKIN input polarity */ 124:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #endif /* TIM_BREAK_INPUT_SUPPORT */ 125:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 126:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /* Remap mask definitions */ 127:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define TIMx_OR_RMP_SHIFT 16U 128:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define TIMx_OR_RMP_MASK 0x0000FFFFU 129:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define TIM2_OR_RMP_MASK (TIM2_OR_ITR1_RMP << TIMx_OR_RMP_SHIFT) 130:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define TIM5_OR_RMP_MASK (TIM5_OR_TI4_RMP << TIMx_OR_RMP_SHIFT) 131:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define TIM11_OR_RMP_MASK (TIM11_OR_TI1_RMP << TIMx_OR_RMP_SHIFT) 132:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 133:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /* Mask used to set the TDG[x:0] of the DTG bits of the TIMx_BDTR register */ 134:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define DT_DELAY_1 ((uint8_t)0x7F) 135:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define DT_DELAY_2 ((uint8_t)0x3F) 136:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define DT_DELAY_3 ((uint8_t)0x1F) 137:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define DT_DELAY_4 ((uint8_t)0x1F) 138:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 139:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /* Mask used to set the DTG[7:5] bits of the DTG bits of the TIMx_BDTR register */ 140:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define DT_RANGE_1 ((uint8_t)0x00) 141:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define DT_RANGE_2 ((uint8_t)0x80) 142:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define DT_RANGE_3 ((uint8_t)0xC0) 143:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define DT_RANGE_4 ((uint8_t)0xE0) 144:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 145:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 146:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 147:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} 148:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 149:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 150:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /* Private macros ------------------------------------------------------------*/ 151:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_Private_Macros TIM Private Macros 152:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ 153:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 154:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @brief Convert channel id into channel index. 155:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param __CHANNEL__ This parameter can be one of the following values: 156:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 157:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1N 158:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 159:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2N 160:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 161:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3N 162:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 163:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH5 164:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH6 165:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval none 166:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 167:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define TIM_GET_CHANNEL_INDEX( __CHANNEL__) \ 168:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** (((__CHANNEL__) == LL_TIM_CHANNEL_CH1) ? 0U :\ 169:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** ((__CHANNEL__) == LL_TIM_CHANNEL_CH1N) ? 1U :\ ARM GAS /tmp/ccLSPxIe.s page 297 170:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** ((__CHANNEL__) == LL_TIM_CHANNEL_CH2) ? 2U :\ 171:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** ((__CHANNEL__) == LL_TIM_CHANNEL_CH2N) ? 3U :\ 172:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** ((__CHANNEL__) == LL_TIM_CHANNEL_CH3) ? 4U :\ 173:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** ((__CHANNEL__) == LL_TIM_CHANNEL_CH3N) ? 5U :\ 174:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** ((__CHANNEL__) == LL_TIM_CHANNEL_CH4) ? 6U :\ 175:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** ((__CHANNEL__) == LL_TIM_CHANNEL_CH5) ? 7U : 8U) 176:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 177:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @brief Calculate the deadtime sampling period(in ps). 178:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param __TIMCLK__ timer input clock frequency (in Hz). 179:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param __CKD__ This parameter can be one of the following values: 180:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CLOCKDIVISION_DIV1 181:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CLOCKDIVISION_DIV2 182:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CLOCKDIVISION_DIV4 183:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval none 184:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 185:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define TIM_CALC_DTS(__TIMCLK__, __CKD__) \ 186:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** (((__CKD__) == LL_TIM_CLOCKDIVISION_DIV1) ? ((uint64_t)1000000000000U/(__TIMCLK__)) : \ 187:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** ((__CKD__) == LL_TIM_CLOCKDIVISION_DIV2) ? ((uint64_t)1000000000000U/((__TIMCLK__) >> 1U)) : \ 188:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** ((uint64_t)1000000000000U/((__TIMCLK__) >> 2U))) 189:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 190:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} 191:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 192:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 193:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 194:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /* Exported types ------------------------------------------------------------*/ 195:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #if defined(USE_FULL_LL_DRIVER) 196:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_ES_INIT TIM Exported Init structure 197:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ 198:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 199:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 200:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 201:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief TIM Time Base configuration structure definition. 202:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 203:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** typedef struct 204:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 205:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint16_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock. 206:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a number between Min_Data=0x0000 and Max_D 207:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 208:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary function 209:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_SetPrescaler().*/ 210:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 211:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t CounterMode; /*!< Specifies the counter mode. 212:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_COUNTERMODE. 213:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 214:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary function 215:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_SetCounterMode().*/ 216:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 217:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t Autoreload; /*!< Specifies the auto reload value to be loaded into the active 218:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** Auto-Reload Register at the next update event. 219:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter must be a number between Min_Data=0x0000 and Max_ 220:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** Some timer instances may support 32 bits counters. In that case 221:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** be a number between 0x0000 and 0xFFFFFFFF. 222:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 223:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary function 224:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_SetAutoReload().*/ 225:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 226:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t ClockDivision; /*!< Specifies the clock division. ARM GAS /tmp/ccLSPxIe.s page 298 227:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_CLOCKDIVISION. 228:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 229:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary function 230:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_SetClockDivision().*/ 231:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 232:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downc 233:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** reaches zero, an update event is generated and counting restarts 234:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** from the RCR value (N). 235:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This means in PWM mode that (N+1) corresponds to: 236:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** - the number of PWM periods in edge-aligned mode 237:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** - the number of half PWM period in center-aligned mode 238:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** GP timers: this parameter must be a number between Min_Data = 0x 239:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** Max_Data = 0xFF. 240:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** Advanced timers: this parameter must be a number between Min_Dat 241:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** Max_Data = 0xFFFF. 242:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 243:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary function 244:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_SetRepetitionCounter().*/ 245:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } LL_TIM_InitTypeDef; 246:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 247:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 248:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief TIM Output Compare configuration structure definition. 249:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 250:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** typedef struct 251:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 252:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t OCMode; /*!< Specifies the output mode. 253:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_OCMODE. 254:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 255:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary function 256:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_OC_SetMode().*/ 257:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 258:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t OCState; /*!< Specifies the TIM Output Compare state. 259:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_OCSTATE. 260:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 261:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary functions 262:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/ 263:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 264:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t OCNState; /*!< Specifies the TIM complementary Output Compare state. 265:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_OCSTATE. 266:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 267:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary functions 268:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/ 269:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 270:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t CompareValue; /*!< Specifies the Compare value to be loaded into the Capture Compare Re 271:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a number between Min_Data=0x0000 and Max_Data= 272:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 273:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary function 274:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** LL_TIM_OC_SetCompareCHx (x=1..6).*/ 275:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 276:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t OCPolarity; /*!< Specifies the output polarity. 277:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY. 278:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 279:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary function 280:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_OC_SetPolarity().*/ 281:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 282:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t OCNPolarity; /*!< Specifies the complementary output polarity. 283:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY. ARM GAS /tmp/ccLSPxIe.s page 299 284:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 285:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary function 286:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_OC_SetPolarity().*/ 287:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 288:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 289:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. 290:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE. 291:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 292:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary function 293:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_OC_SetIdleState().*/ 294:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 295:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. 296:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE. 297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 298:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary function 299:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_OC_SetIdleState().*/ 300:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } LL_TIM_OC_InitTypeDef; 301:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 302:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 303:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief TIM Input Capture configuration structure definition. 304:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 305:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 306:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** typedef struct 307:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 308:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 309:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t ICPolarity; /*!< Specifies the active edge of the input signal. 310:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY. 311:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 312:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary function 313:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_IC_SetPolarity().*/ 314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t ICActiveInput; /*!< Specifies the input. 316:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT. 317:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 318:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary function 319:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_IC_SetActiveInput().*/ 320:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 321:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler. 322:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_ICPSC. 323:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 324:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary function 325:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_IC_SetPrescaler().*/ 326:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 327:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t ICFilter; /*!< Specifies the input capture filter. 328:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_IC_FILTER. 329:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 330:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary function 331:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_IC_SetFilter().*/ 332:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } LL_TIM_IC_InitTypeDef; 333:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 334:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 335:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 336:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief TIM Encoder interface configuration structure definition. 337:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 338:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** typedef struct 339:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 340:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t EncoderMode; /*!< Specifies the encoder resolution (x2 or x4). ARM GAS /tmp/ccLSPxIe.s page 300 341:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_ENCODERMODE. 342:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 343:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary function 344:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_SetEncoderMode().*/ 345:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input. 347:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY. 348:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 349:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary function 350:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_IC_SetPolarity().*/ 351:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 352:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t IC1ActiveInput; /*!< Specifies the TI1 input source 353:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT. 354:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 355:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary function 356:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_IC_SetActiveInput().*/ 357:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 358:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value. 359:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_ICPSC. 360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 361:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary function 362:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_IC_SetPrescaler().*/ 363:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 364:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t IC1Filter; /*!< Specifies the TI1 input filter. 365:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_IC_FILTER. 366:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 367:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary function 368:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_IC_SetFilter().*/ 369:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t IC2Polarity; /*!< Specifies the active edge of TI2 input. 371:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY. 372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary function 374:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_IC_SetPolarity().*/ 375:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 376:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t IC2ActiveInput; /*!< Specifies the TI2 input source 377:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT. 378:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 379:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary function 380:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_IC_SetActiveInput().*/ 381:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 382:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t IC2Prescaler; /*!< Specifies the TI2 input prescaler value. 383:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_ICPSC. 384:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 385:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary function 386:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_IC_SetPrescaler().*/ 387:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 388:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t IC2Filter; /*!< Specifies the TI2 input filter. 389:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_IC_FILTER. 390:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 391:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary function 392:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_IC_SetFilter().*/ 393:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 394:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } LL_TIM_ENCODER_InitTypeDef; 395:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 396:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 397:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief TIM Hall sensor interface configuration structure definition. ARM GAS /tmp/ccLSPxIe.s page 301 398:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 399:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** typedef struct 400:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 401:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 402:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input. 403:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY. 404:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 405:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary function 406:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_IC_SetPolarity().*/ 407:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 408:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value. 409:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** Prescaler must be set to get a maximum counter period longer th 410:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** time interval between 2 consecutive changes on the Hall inputs. 411:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_ICPSC. 412:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 413:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary function 414:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_IC_SetPrescaler().*/ 415:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 416:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t IC1Filter; /*!< Specifies the TI1 input filter. 417:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of 418:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref TIM_LL_EC_IC_FILTER. 419:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 420:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary function 421:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_IC_SetFilter().*/ 422:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 423:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t CommutationDelay; /*!< Specifies the compare value to be loaded into the Capture Compa 424:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** A positive pulse (TRGO event) is generated with a programmable 425:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** a change occurs on the Hall inputs. 426:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a number between Min_Data = 0x0000 and Ma 427:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary function 429:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_OC_SetCompareCH2().*/ 430:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } LL_TIM_HALLSENSOR_InitTypeDef; 431:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 432:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 433:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief BDTR (Break and Dead Time) structure definition 434:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 435:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** typedef struct 436:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 437:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t OSSRState; /*!< Specifies the Off-State selection used in Run mode. 438:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_OSSR 439:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 440:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary functio 441:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_SetOffStates() 442:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 443:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @note This bit-field cannot be modified as long as LOCK level 444:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** programmed. */ 445:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 446:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t OSSIState; /*!< Specifies the Off-State used in Idle state. 447:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_OSSI 448:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 449:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary functio 450:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_SetOffStates() 451:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 452:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @note This bit-field cannot be modified as long as LOCK level 453:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** programmed. */ 454:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** ARM GAS /tmp/ccLSPxIe.s page 302 455:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t LockLevel; /*!< Specifies the LOCK level parameters. 456:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_LOCKLEVEL 457:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 458:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @note The LOCK bits can be written only once after the reset. 459:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** register has been written, their content is frozen until the 460:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 461:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint8_t DeadTime; /*!< Specifies the delay time between the switching-off and the 462:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** switching-on of the outputs. 463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a number between Min_Data = 0x00 and Ma 464:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 465:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary functio 466:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_OC_SetDeadTime() 467:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 468:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @note This bit-field can not be modified as long as LOCK leve 469:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** programmed. */ 470:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 471:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint16_t BreakState; /*!< Specifies whether the TIM Break input is enabled or not. 472:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_BREAK_ENABLE 473:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 474:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary functio 475:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_EnableBRK() or @ref LL_TIM_DisableBRK() 476:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 477:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @note This bit-field can not be modified as long as LOCK leve 478:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** programmed. */ 479:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 480:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t BreakPolarity; /*!< Specifies the TIM Break Input pin polarity. 481:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_BREAK_POLARIT 482:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 483:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary functio 484:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_ConfigBRK() 485:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 486:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @note This bit-field can not be modified as long as LOCK leve 487:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** programmed. */ 488:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 489:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t BreakFilter; /*!< Specifies the TIM Break Filter. 490:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_BREAK_FILTER 491:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 492:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary functio 493:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_ConfigBRK() 494:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 495:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @note This bit-field can not be modified as long as LOCK leve 496:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** programmed. */ 497:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 498:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t Break2State; /*!< Specifies whether the TIM Break2 input is enabled or not. 499:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_BREAK2_ENABLE 500:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 501:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary functio 502:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_EnableBRK2() or @ref LL_TIM_DisableBRK2() 503:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 504:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @note This bit-field can not be modified as long as LOCK leve 505:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** programmed. */ 506:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 507:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t Break2Polarity; /*!< Specifies the TIM Break2 Input pin polarity. 508:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_BREAK2_POLARI 509:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 510:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary functio 511:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_ConfigBRK2() ARM GAS /tmp/ccLSPxIe.s page 303 512:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 513:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @note This bit-field can not be modified as long as LOCK leve 514:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** programmed. */ 515:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 516:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t Break2Filter; /*!< Specifies the TIM Break2 Filter. 517:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_BREAK2_FILTER 518:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 519:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary functio 520:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_ConfigBRK2() 521:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 522:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @note This bit-field can not be modified as long as LOCK leve 523:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** programmed. */ 524:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 525:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t AutomaticOutput; /*!< Specifies whether the TIM Automatic Output feature is enabled 526:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_AUTOMATICOUTP 527:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 528:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary functio 529:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_EnableAutomaticOutput() or @ref LL_TIM_DisableAut 530:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 531:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @note This bit-field can not be modified as long as LOCK leve 532:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** programmed. */ 533:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } LL_TIM_BDTR_InitTypeDef; 534:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 535:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 536:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} 537:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 538:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #endif /* USE_FULL_LL_DRIVER */ 539:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 540:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /* Exported constants --------------------------------------------------------*/ 541:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_Exported_Constants TIM Exported Constants 542:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ 543:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 544:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 545:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EC_GET_FLAG Get Flags Defines 546:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Flags defines which can be used with LL_TIM_ReadReg function. 547:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ 548:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 549:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_SR_UIF TIM_SR_UIF /*!< Update interrupt flag */ 550:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_SR_CC1IF TIM_SR_CC1IF /*!< Capture/compare 1 interrup 551:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_SR_CC2IF TIM_SR_CC2IF /*!< Capture/compare 2 interrup 552:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_SR_CC3IF TIM_SR_CC3IF /*!< Capture/compare 3 interrup 553:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_SR_CC4IF TIM_SR_CC4IF /*!< Capture/compare 4 interrup 554:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_SR_CC5IF TIM_SR_CC5IF /*!< Capture/compare 5 interrup 555:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_SR_CC6IF TIM_SR_CC6IF /*!< Capture/compare 6 interrup 556:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_SR_COMIF TIM_SR_COMIF /*!< COM interrupt flag */ 557:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_SR_TIF TIM_SR_TIF /*!< Trigger interrupt flag */ 558:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_SR_BIF TIM_SR_BIF /*!< Break interrupt flag */ 559:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_SR_B2IF TIM_SR_B2IF /*!< Second break interrupt fla 560:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_SR_CC1OF TIM_SR_CC1OF /*!< Capture/Compare 1 overcapt 561:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_SR_CC2OF TIM_SR_CC2OF /*!< Capture/Compare 2 overcapt 562:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_SR_CC3OF TIM_SR_CC3OF /*!< Capture/Compare 3 overcapt 563:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_SR_CC4OF TIM_SR_CC4OF /*!< Capture/Compare 4 overcapt 564:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_SR_SBIF TIM_SR_SBIF /*!< System Break interrupt fla 565:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 566:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} 567:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 568:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** ARM GAS /tmp/ccLSPxIe.s page 304 569:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #if defined(USE_FULL_LL_DRIVER) 570:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EC_BREAK_ENABLE Break Enable 571:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ 572:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 573:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_BREAK_DISABLE 0x00000000U /*!< Break function disabled */ 574:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_BREAK_ENABLE TIM_BDTR_BKE /*!< Break function enabled */ 575:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 576:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} 577:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 578:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 579:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EC_BREAK2_ENABLE Break2 Enable 580:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ 581:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 582:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_BREAK2_DISABLE 0x00000000U /*!< Break2 function disabled */ 583:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_BREAK2_ENABLE TIM_BDTR_BK2E /*!< Break2 function enabled */ 584:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 585:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} 586:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 587:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 588:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EC_AUTOMATICOUTPUT_ENABLE Automatic output enable 589:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ 590:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 591:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U /*!< MOE can be set only by 592:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /*!< MOE can be set by softw 593:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 594:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} 595:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 596:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #endif /* USE_FULL_LL_DRIVER */ 597:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 598:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EC_IT IT Defines 599:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief IT defines which can be used with LL_TIM_ReadReg and LL_TIM_WriteReg functions. 600:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ 601:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 602:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_DIER_UIE TIM_DIER_UIE /*!< Update interrupt enable */ 603:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_DIER_CC1IE TIM_DIER_CC1IE /*!< Capture/compare 1 interrup 604:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_DIER_CC2IE TIM_DIER_CC2IE /*!< Capture/compare 2 interrup 605:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_DIER_CC3IE TIM_DIER_CC3IE /*!< Capture/compare 3 interrup 606:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_DIER_CC4IE TIM_DIER_CC4IE /*!< Capture/compare 4 interrup 607:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_DIER_COMIE TIM_DIER_COMIE /*!< COM interrupt enable */ 608:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_DIER_TIE TIM_DIER_TIE /*!< Trigger interrupt enable * 609:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_DIER_BIE TIM_DIER_BIE /*!< Break interrupt enable */ 610:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 611:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} 612:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 613:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 614:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EC_UPDATESOURCE Update Source 615:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ 616:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 617:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_UPDATESOURCE_REGULAR 0x00000000U /*!< Counter overflow/underflow 618:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_UPDATESOURCE_COUNTER TIM_CR1_URS /*!< Only counter overflow/unde 619:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 620:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} 621:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 622:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 623:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EC_ONEPULSEMODE One Pulse Mode 624:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ 625:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ ARM GAS /tmp/ccLSPxIe.s page 305 626:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_ONEPULSEMODE_SINGLE TIM_CR1_OPM /*!< Counter stops counting at 627:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_ONEPULSEMODE_REPETITIVE 0x00000000U /*!< Counter is not stopped at 628:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 629:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} 630:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 631:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 632:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EC_COUNTERMODE Counter Mode 633:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ 634:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 635:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_COUNTERMODE_UP 0x00000000U /*!< Counter used as upcounter 636:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_COUNTERMODE_DOWN TIM_CR1_DIR /*!< Counter used as downcounte 637:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_COUNTERMODE_CENTER_DOWN TIM_CR1_CMS_0 /*!< The counter counts up and 638:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_COUNTERMODE_CENTER_UP TIM_CR1_CMS_1 /*!< The counter counts up and 639:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_COUNTERMODE_CENTER_UP_DOWN TIM_CR1_CMS /*!< The counter counts up and 640:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 641:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} 642:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 643:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 644:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EC_CLOCKDIVISION Clock Division 645:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ 646:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 647:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_CLOCKDIVISION_DIV1 0x00000000U /*!< tDTS=tCK_INT */ 648:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0 /*!< tDTS=2*tCK_INT */ 649:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1 /*!< tDTS=4*tCK_INT */ 650:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 651:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} 652:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 653:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 654:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EC_COUNTERDIRECTION Counter Direction 655:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ 656:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 657:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_COUNTERDIRECTION_UP 0x00000000U /*!< Timer counter counts up */ 658:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_COUNTERDIRECTION_DOWN TIM_CR1_DIR /*!< Timer counter counts down 659:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 660:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} 661:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 662:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 663:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EC_CCUPDATESOURCE Capture Compare Update Source 664:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ 665:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 666:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_CCUPDATESOURCE_COMG_ONLY 0x00000000U /*!< Capture/compare control bi 667:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI TIM_CR2_CCUS /*!< Capture/compare control bi 668:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 669:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} 670:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 671:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 672:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EC_CCDMAREQUEST Capture Compare DMA Request 673:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ 674:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 675:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_CCDMAREQUEST_CC 0x00000000U /*!< CCx DMA request sent when 676:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_CCDMAREQUEST_UPDATE TIM_CR2_CCDS /*!< CCx DMA requests sent when 677:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 678:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} 679:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 680:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 681:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EC_LOCKLEVEL Lock Level 682:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ ARM GAS /tmp/ccLSPxIe.s page 306 683:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 684:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_LOCKLEVEL_OFF 0x00000000U /*!< LOCK OFF - No bit is write 685:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0 /*!< LOCK Level 1 */ 686:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1 /*!< LOCK Level 2 */ 687:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_LOCKLEVEL_3 TIM_BDTR_LOCK /*!< LOCK Level 3 */ 688:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 689:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} 690:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 691:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 692:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EC_CHANNEL Channel 693:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ 694:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 695:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_CHANNEL_CH1 TIM_CCER_CC1E /*!< Timer input/output channel 1 696:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_CHANNEL_CH1N TIM_CCER_CC1NE /*!< Timer complementary output ch 697:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_CHANNEL_CH2 TIM_CCER_CC2E /*!< Timer input/output channel 2 698:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_CHANNEL_CH2N TIM_CCER_CC2NE /*!< Timer complementary output ch 699:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_CHANNEL_CH3 TIM_CCER_CC3E /*!< Timer input/output channel 3 700:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_CHANNEL_CH3N TIM_CCER_CC3NE /*!< Timer complementary output ch 701:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_CHANNEL_CH4 TIM_CCER_CC4E /*!< Timer input/output channel 4 702:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_CHANNEL_CH5 TIM_CCER_CC5E /*!< Timer output channel 5 */ 703:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_CHANNEL_CH6 TIM_CCER_CC6E /*!< Timer output channel 6 */ 704:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 705:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} 706:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 707:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 708:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #if defined(USE_FULL_LL_DRIVER) 709:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EC_OCSTATE Output Configuration State 710:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ 711:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 712:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_OCSTATE_DISABLE 0x00000000U /*!< OCx is not active */ 713:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_OCSTATE_ENABLE TIM_CCER_CC1E /*!< OCx signal is output on 714:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 715:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} 716:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 717:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #endif /* USE_FULL_LL_DRIVER */ 718:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 719:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** Legacy definitions for compatibility purpose 720:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @cond 0 721:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 722:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_OCMODE_ASSYMETRIC_PWM1 LL_TIM_OCMODE_ASYMMETRIC_PWM1 723:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_OCMODE_ASSYMETRIC_PWM2 LL_TIM_OCMODE_ASYMMETRIC_PWM2 724:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 725:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @endcond 726:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 727:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 728:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EC_OCMODE Output Configuration Mode 729:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ 730:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 731:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_OCMODE_FROZEN 0x00000000U 732:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0 733:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1 734:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) 735:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_OCMODE_FORCED_INACTIVE TIM_CCMR1_OC1M_2 736:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0) 737:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1) 738:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1 739:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_OCMODE_RETRIG_OPM1 TIM_CCMR1_OC1M_3 ARM GAS /tmp/ccLSPxIe.s page 307 740:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_OCMODE_RETRIG_OPM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0) 741:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_OCMODE_COMBINED_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2) 742:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_OCMODE_COMBINED_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1 743:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_OCMODE_ASYMMETRIC_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1 744:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_OCMODE_ASYMMETRIC_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M) 745:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 746:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} 747:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 748:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 749:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EC_OCPOLARITY Output Configuration Polarity 750:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ 751:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 752:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_OCPOLARITY_HIGH 0x00000000U /*!< OCxactive high*/ 753:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_OCPOLARITY_LOW TIM_CCER_CC1P /*!< OCxactive low*/ 754:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 755:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} 756:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 757:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 758:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EC_OCIDLESTATE Output Configuration Idle State 759:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ 760:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 761:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_OCIDLESTATE_LOW 0x00000000U /*!__REG__, (__VAL 1185:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1186:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 1187:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Read a value in TIM register. 1188:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param __INSTANCE__ TIM Instance 1189:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param __REG__ Register to be read 1190:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval Register value 1191:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1192:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__) 1193:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 1194:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} 1195:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ ARM GAS /tmp/ccLSPxIe.s page 315 1196:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1197:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 1198:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief HELPER macro retrieving the UIFCPY flag from the counter value. 1199:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note ex: @ref __LL_TIM_GETFLAG_UIFCPY (@ref LL_TIM_GetCounter ()); 1200:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Relevant only if UIF flag remapping has been enabled (UIF status bit is copied 1201:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * to TIMx_CNT register bit 31) 1202:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param __CNT__ Counter value 1203:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval UIF status bit 1204:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1205:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define __LL_TIM_GETFLAG_UIFCPY(__CNT__) \ 1206:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** (READ_BIT((__CNT__), TIM_CNT_UIFCPY) >> TIM_CNT_UIFCPY_Pos) 1207:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1208:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 1209:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief HELPER macro calculating DTG[0:7] in the TIMx_BDTR register to achieve the requested de 1210:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note ex: @ref __LL_TIM_CALC_DEADTIME (80000000, @ref LL_TIM_GetClockDivision (), 120); 1211:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param __TIMCLK__ timer input clock frequency (in Hz) 1212:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param __CKD__ This parameter can be one of the following values: 1213:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CLOCKDIVISION_DIV1 1214:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CLOCKDIVISION_DIV2 1215:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CLOCKDIVISION_DIV4 1216:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param __DT__ deadtime duration (in ns) 1217:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval DTG[0:7] 1218:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1219:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define __LL_TIM_CALC_DEADTIME(__TIMCLK__, __CKD__, __DT__) \ 1220:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** ( (((uint64_t)((__DT__)*1000U)) < ((DT_DELAY_1+1U) * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? 1221:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** (uint8_t)(((uint64_t)((__DT__)*1000U) / TIM_CALC_DTS((__TIMCLK__), (__CKD__))) & DT_DELAY_1) : 1222:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** (((uint64_t)((__DT__)*1000U)) < ((64U + (DT_DELAY_2+1U)) * 2U * TIM_CALC_DTS((__TIMCLK__), (__C 1223:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** (uint8_t)(DT_RANGE_2 | ((uint8_t)((uint8_t)((((uint64_t)((__DT__)*1000U))/ TIM_CALC_DTS((__TIMC 1224:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** (__CKD__))) >> 1U) - (uint8_t) 64) & DT_DELAY_2)) 1225:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_3+1U)) * 8U * TIM_CALC_DTS((__TIMCLK__), (__C 1226:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** (uint8_t)(DT_RANGE_3 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMC 1227:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** (__CKD__))) >> 3U) - (uint8_t) 32) & DT_DELAY_3)) 1228:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_4+1U)) * 16U * TIM_CALC_DTS((__TIMCLK__), (__ 1229:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** (uint8_t)(DT_RANGE_4 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMC 1230:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** (__CKD__))) >> 4U) - (uint8_t) 32) & DT_DELAY_4)) 1231:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 0U) 1232:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1233:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 1234:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief HELPER macro calculating the prescaler value to achieve the required counter clock freq 1235:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note ex: @ref __LL_TIM_CALC_PSC (80000000, 1000000); 1236:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param __TIMCLK__ timer input clock frequency (in Hz) 1237:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param __CNTCLK__ counter clock frequency (in Hz) 1238:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval Prescaler value (between Min_Data=0 and Max_Data=65535) 1239:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1240:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define __LL_TIM_CALC_PSC(__TIMCLK__, __CNTCLK__) \ 1241:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** (((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)((((__TIMCLK__) + (__CNTCLK__)/2U)/(__CNTCLK__)) - 1U 1242:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1243:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 1244:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief HELPER macro calculating the auto-reload value to achieve the required output signal fr 1245:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note ex: @ref __LL_TIM_CALC_ARR (1000000, @ref LL_TIM_GetPrescaler (), 10000); 1246:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param __TIMCLK__ timer input clock frequency (in Hz) 1247:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param __PSC__ prescaler 1248:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param __FREQ__ output signal frequency (in Hz) 1249:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535) 1250:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1251:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define __LL_TIM_CALC_ARR(__TIMCLK__, __PSC__, __FREQ__) \ 1252:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** ((((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? (((__TIMCLK__)/((__FREQ__) * ((__PSC__) + 1U)) ARM GAS /tmp/ccLSPxIe.s page 316 1253:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1254:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 1255:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief HELPER macro calculating the compare value required to achieve the required timer outpu 1256:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * active/inactive delay. 1257:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note ex: @ref __LL_TIM_CALC_DELAY (1000000, @ref LL_TIM_GetPrescaler (), 10); 1258:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param __TIMCLK__ timer input clock frequency (in Hz) 1259:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param __PSC__ prescaler 1260:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param __DELAY__ timer output compare active/inactive delay (in us) 1261:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval Compare value (between Min_Data=0 and Max_Data=65535) 1262:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1263:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define __LL_TIM_CALC_DELAY(__TIMCLK__, __PSC__, __DELAY__) \ 1264:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** ((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__)) \ 1265:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** / ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U)))) 1266:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1267:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 1268:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief HELPER macro calculating the auto-reload value to achieve the required pulse duration 1269:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * (when the timer operates in one pulse mode). 1270:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note ex: @ref __LL_TIM_CALC_PULSE (1000000, @ref LL_TIM_GetPrescaler (), 10, 20); 1271:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param __TIMCLK__ timer input clock frequency (in Hz) 1272:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param __PSC__ prescaler 1273:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param __DELAY__ timer output compare active/inactive delay (in us) 1274:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param __PULSE__ pulse duration (in us) 1275:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535) 1276:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1277:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define __LL_TIM_CALC_PULSE(__TIMCLK__, __PSC__, __DELAY__, __PULSE__) \ 1278:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** ((uint32_t)(__LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__PULSE__)) \ 1279:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + __LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__DELAY__)))) 1280:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1281:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 1282:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief HELPER macro retrieving the ratio of the input capture prescaler 1283:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note ex: @ref __LL_TIM_GET_ICPSC_RATIO (@ref LL_TIM_IC_GetPrescaler ()); 1284:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param __ICPSC__ This parameter can be one of the following values: 1285:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ICPSC_DIV1 1286:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ICPSC_DIV2 1287:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ICPSC_DIV4 1288:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ICPSC_DIV8 1289:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval Input capture prescaler ratio (1, 2, 4 or 8) 1290:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1291:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define __LL_TIM_GET_ICPSC_RATIO(__ICPSC__) \ 1292:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** ((uint32_t)(0x01U << (((__ICPSC__) >> 16U) >> TIM_CCMR1_IC1PSC_Pos))) 1293:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1294:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1295:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 1296:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} 1297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1298:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1299:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /* Exported functions --------------------------------------------------------*/ 1300:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_Exported_Functions TIM Exported Functions 1301:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ 1302:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1303:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1304:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EF_Time_Base Time Base configuration 1305:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ 1306:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1307:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 1308:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Enable timer counter. 1309:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR1 CEN LL_TIM_EnableCounter ARM GAS /tmp/ccLSPxIe.s page 317 1310:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 1311:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 1312:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1313:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_EnableCounter(TIM_TypeDef *TIMx) 1314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 1315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** SET_BIT(TIMx->CR1, TIM_CR1_CEN); 1316:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 1317:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1318:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 1319:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Disable timer counter. 1320:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR1 CEN LL_TIM_DisableCounter 1321:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 1322:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 1323:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1324:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_DisableCounter(TIM_TypeDef *TIMx) 1325:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 1326:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** CLEAR_BIT(TIMx->CR1, TIM_CR1_CEN); 1327:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 1328:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1329:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 1330:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Indicates whether the timer counter is enabled. 1331:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR1 CEN LL_TIM_IsEnabledCounter 1332:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 1333:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval State of bit (1 or 0). 1334:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1335:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsEnabledCounter(const TIM_TypeDef *TIMx) 1336:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 1337:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return ((READ_BIT(TIMx->CR1, TIM_CR1_CEN) == (TIM_CR1_CEN)) ? 1UL : 0UL); 1338:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 1339:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1340:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 1341:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Enable update event generation. 1342:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR1 UDIS LL_TIM_EnableUpdateEvent 1343:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 1344:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 1345:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_EnableUpdateEvent(TIM_TypeDef *TIMx) 1347:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 1348:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** CLEAR_BIT(TIMx->CR1, TIM_CR1_UDIS); 1349:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 1350:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1351:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 1352:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Disable update event generation. 1353:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR1 UDIS LL_TIM_DisableUpdateEvent 1354:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 1355:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 1356:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1357:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_DisableUpdateEvent(TIM_TypeDef *TIMx) 1358:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 1359:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** SET_BIT(TIMx->CR1, TIM_CR1_UDIS); 1360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 1361:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1362:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 1363:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Indicates whether update event generation is enabled. 1364:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR1 UDIS LL_TIM_IsEnabledUpdateEvent 1365:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 1366:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval Inverted state of bit (0 or 1). ARM GAS /tmp/ccLSPxIe.s page 318 1367:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1368:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsEnabledUpdateEvent(const TIM_TypeDef *TIMx) 1369:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 1370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return ((READ_BIT(TIMx->CR1, TIM_CR1_UDIS) == (uint32_t)RESET) ? 1UL : 0UL); 1371:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 1372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 1374:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Set update event source 1375:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Update event source set to LL_TIM_UPDATESOURCE_REGULAR: any of the following events 1376:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * generate an update interrupt or DMA request if enabled: 1377:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * - Counter overflow/underflow 1378:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * - Setting the UG bit 1379:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * - Update generation through the slave mode controller 1380:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Update event source set to LL_TIM_UPDATESOURCE_COUNTER: only counter 1381:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * overflow/underflow generates an update interrupt or DMA request if enabled. 1382:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR1 URS LL_TIM_SetUpdateSource 1383:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 1384:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param UpdateSource This parameter can be one of the following values: 1385:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_UPDATESOURCE_REGULAR 1386:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_UPDATESOURCE_COUNTER 1387:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 1388:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1389:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_SetUpdateSource(TIM_TypeDef *TIMx, uint32_t UpdateSource) 1390:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 1391:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(TIMx->CR1, TIM_CR1_URS, UpdateSource); 1392:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 1393:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1394:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 1395:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Get actual event update source 1396:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR1 URS LL_TIM_GetUpdateSource 1397:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 1398:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval Returned value can be one of the following values: 1399:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_UPDATESOURCE_REGULAR 1400:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_UPDATESOURCE_COUNTER 1401:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1402:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_GetUpdateSource(const TIM_TypeDef *TIMx) 1403:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 1404:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_URS)); 1405:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 1406:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1407:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 1408:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Set one pulse mode (one shot v.s. repetitive). 1409:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR1 OPM LL_TIM_SetOnePulseMode 1410:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 1411:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param OnePulseMode This parameter can be one of the following values: 1412:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ONEPULSEMODE_SINGLE 1413:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE 1414:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 1415:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1416:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_SetOnePulseMode(TIM_TypeDef *TIMx, uint32_t OnePulseMode) 1417:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 1418:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(TIMx->CR1, TIM_CR1_OPM, OnePulseMode); 1419:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 1420:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1421:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 1422:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Get actual one pulse mode. 1423:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR1 OPM LL_TIM_GetOnePulseMode ARM GAS /tmp/ccLSPxIe.s page 319 1424:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 1425:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval Returned value can be one of the following values: 1426:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ONEPULSEMODE_SINGLE 1427:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE 1428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1429:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_GetOnePulseMode(const TIM_TypeDef *TIMx) 1430:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 1431:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_OPM)); 1432:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 1433:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1434:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 1435:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Set the timer counter counting mode. 1436:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to 1437:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * check whether or not the counter mode selection feature is supported 1438:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * by a timer instance. 1439:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) 1440:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * requires a timer reset to avoid unexpected direction 1441:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * due to DIR bit readonly in center aligned mode. 1442:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR1 DIR LL_TIM_SetCounterMode\n 1443:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CR1 CMS LL_TIM_SetCounterMode 1444:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 1445:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param CounterMode This parameter can be one of the following values: 1446:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_COUNTERMODE_UP 1447:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_COUNTERMODE_DOWN 1448:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP 1449:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN 1450:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN 1451:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 1452:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1453:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_SetCounterMode(TIM_TypeDef *TIMx, uint32_t CounterMode) 1454:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 1455:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(TIMx->CR1, (TIM_CR1_DIR | TIM_CR1_CMS), CounterMode); 1456:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 1457:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1458:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 1459:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Get actual counter mode. 1460:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to 1461:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * check whether or not the counter mode selection feature is supported 1462:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * by a timer instance. 1463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR1 DIR LL_TIM_GetCounterMode\n 1464:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CR1 CMS LL_TIM_GetCounterMode 1465:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 1466:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval Returned value can be one of the following values: 1467:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_COUNTERMODE_UP 1468:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_COUNTERMODE_DOWN 1469:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP 1470:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN 1471:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN 1472:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1473:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_GetCounterMode(const TIM_TypeDef *TIMx) 1474:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 1475:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t counter_mode; 1476:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1477:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** counter_mode = (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CMS)); 1478:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1479:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** if (counter_mode == 0U) 1480:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { ARM GAS /tmp/ccLSPxIe.s page 320 1481:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** counter_mode = (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR)); 1482:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 1483:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1484:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return counter_mode; 1485:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 1486:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1487:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 1488:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Enable auto-reload (ARR) preload. 1489:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR1 ARPE LL_TIM_EnableARRPreload 1490:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 1491:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 1492:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1493:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_EnableARRPreload(TIM_TypeDef *TIMx) 1494:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 1495:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** SET_BIT(TIMx->CR1, TIM_CR1_ARPE); 1496:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 1497:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1498:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 1499:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Disable auto-reload (ARR) preload. 1500:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR1 ARPE LL_TIM_DisableARRPreload 1501:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 1502:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 1503:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1504:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_DisableARRPreload(TIM_TypeDef *TIMx) 6179 .loc 5 1504 22 view .LVU1913 6180 .LBB524: 1505:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 1506:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** CLEAR_BIT(TIMx->CR1, TIM_CR1_ARPE); 6181 .loc 5 1506 3 view .LVU1914 6182 005e 4FF08043 mov r3, #1073741824 6183 0062 1A68 ldr r2, [r3] 6184 0064 22F08002 bic r2, r2, #128 6185 0068 1A60 str r2, [r3] 6186 .LVL589: 6187 .loc 5 1506 3 is_stmt 0 view .LVU1915 6188 .LBE524: 6189 .LBE523: 1652:Src/main.c **** LL_TIM_SetTriggerOutput(TIM2, LL_TIM_TRGO_RESET); 6190 .loc 1 1652 3 is_stmt 1 view .LVU1916 6191 .LBB525: 6192 .LBI525: 1507:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 1508:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1509:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 1510:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Indicates whether auto-reload (ARR) preload is enabled. 1511:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR1 ARPE LL_TIM_IsEnabledARRPreload 1512:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 1513:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval State of bit (1 or 0). 1514:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1515:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsEnabledARRPreload(const TIM_TypeDef *TIMx) 1516:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 1517:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return ((READ_BIT(TIMx->CR1, TIM_CR1_ARPE) == (TIM_CR1_ARPE)) ? 1UL : 0UL); 1518:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 1519:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1520:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 1521:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Set the division ratio between the timer clock and the sampling clock used by the dead 1522:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * (when supported) and the digital filters. ARM GAS /tmp/ccLSPxIe.s page 321 1523:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check 1524:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * whether or not the clock division feature is supported by the timer 1525:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * instance. 1526:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR1 CKD LL_TIM_SetClockDivision 1527:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 1528:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param ClockDivision This parameter can be one of the following values: 1529:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CLOCKDIVISION_DIV1 1530:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CLOCKDIVISION_DIV2 1531:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CLOCKDIVISION_DIV4 1532:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 1533:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1534:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_SetClockDivision(TIM_TypeDef *TIMx, uint32_t ClockDivision) 1535:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 1536:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(TIMx->CR1, TIM_CR1_CKD, ClockDivision); 1537:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 1538:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1539:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 1540:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Get the actual division ratio between the timer clock and the sampling clock used by t 1541:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * generators (when supported) and the digital filters. 1542:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check 1543:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * whether or not the clock division feature is supported by the timer 1544:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * instance. 1545:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR1 CKD LL_TIM_GetClockDivision 1546:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 1547:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval Returned value can be one of the following values: 1548:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CLOCKDIVISION_DIV1 1549:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CLOCKDIVISION_DIV2 1550:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CLOCKDIVISION_DIV4 1551:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1552:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_GetClockDivision(const TIM_TypeDef *TIMx) 1553:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 1554:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CKD)); 1555:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 1556:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1557:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 1558:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Set the counter value. 1559:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check 1560:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * whether or not a timer instance supports a 32 bits counter. 1561:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CNT CNT LL_TIM_SetCounter 1562:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 1563:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Counter Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF) 1564:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 1565:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1566:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_SetCounter(TIM_TypeDef *TIMx, uint32_t Counter) 1567:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 1568:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** WRITE_REG(TIMx->CNT, Counter); 1569:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 1570:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1571:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 1572:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Get the counter value. 1573:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check 1574:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * whether or not a timer instance supports a 32 bits counter. 1575:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CNT CNT LL_TIM_GetCounter 1576:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 1577:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF) 1578:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1579:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_GetCounter(const TIM_TypeDef *TIMx) ARM GAS /tmp/ccLSPxIe.s page 322 1580:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 1581:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return (uint32_t)(READ_REG(TIMx->CNT)); 1582:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 1583:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1584:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 1585:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Get the current direction of the counter 1586:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR1 DIR LL_TIM_GetDirection 1587:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 1588:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval Returned value can be one of the following values: 1589:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_COUNTERDIRECTION_UP 1590:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_COUNTERDIRECTION_DOWN 1591:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1592:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_GetDirection(const TIM_TypeDef *TIMx) 1593:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 1594:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR)); 1595:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 1596:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1597:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 1598:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Set the prescaler value. 1599:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note The counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1). 1600:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note The prescaler can be changed on the fly as this control register is buffered. The new 1601:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * prescaler ratio is taken into account at the next update event. 1602:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Helper macro @ref __LL_TIM_CALC_PSC can be used to calculate the Prescaler parameter 1603:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll PSC PSC LL_TIM_SetPrescaler 1604:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 1605:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Prescaler between Min_Data=0 and Max_Data=65535 1606:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 1607:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1608:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Prescaler) 1609:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 1610:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** WRITE_REG(TIMx->PSC, Prescaler); 1611:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 1612:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1613:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 1614:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Get the prescaler value. 1615:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll PSC PSC LL_TIM_GetPrescaler 1616:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 1617:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval Prescaler value between Min_Data=0 and Max_Data=65535 1618:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1619:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_GetPrescaler(const TIM_TypeDef *TIMx) 1620:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 1621:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return (uint32_t)(READ_REG(TIMx->PSC)); 1622:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 1623:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1624:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 1625:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Set the auto-reload value. 1626:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note The counter is blocked while the auto-reload value is null. 1627:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check 1628:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * whether or not a timer instance supports a 32 bits counter. 1629:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Helper macro @ref __LL_TIM_CALC_ARR can be used to calculate the AutoReload parameter 1630:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll ARR ARR LL_TIM_SetAutoReload 1631:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 1632:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param AutoReload between Min_Data=0 and Max_Data=65535 1633:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 1634:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1635:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_SetAutoReload(TIM_TypeDef *TIMx, uint32_t AutoReload) 1636:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { ARM GAS /tmp/ccLSPxIe.s page 323 1637:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** WRITE_REG(TIMx->ARR, AutoReload); 1638:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 1639:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1640:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 1641:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Get the auto-reload value. 1642:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll ARR ARR LL_TIM_GetAutoReload 1643:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check 1644:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * whether or not a timer instance supports a 32 bits counter. 1645:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 1646:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval Auto-reload value 1647:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1648:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_GetAutoReload(const TIM_TypeDef *TIMx) 1649:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 1650:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return (uint32_t)(READ_REG(TIMx->ARR)); 1651:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 1652:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1653:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 1654:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Set the repetition counter value. 1655:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note For advanced timer instances RepetitionCounter can be up to 65535. 1656:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check 1657:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * whether or not a timer instance supports a repetition counter. 1658:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll RCR REP LL_TIM_SetRepetitionCounter 1659:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 1660:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param RepetitionCounter between Min_Data=0 and Max_Data=255 or 65535 for advanced timer. 1661:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 1662:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1663:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_SetRepetitionCounter(TIM_TypeDef *TIMx, uint32_t RepetitionCounter) 1664:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 1665:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** WRITE_REG(TIMx->RCR, RepetitionCounter); 1666:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 1667:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1668:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 1669:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Get the repetition counter value. 1670:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check 1671:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * whether or not a timer instance supports a repetition counter. 1672:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll RCR REP LL_TIM_GetRepetitionCounter 1673:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 1674:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval Repetition counter value 1675:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1676:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_GetRepetitionCounter(const TIM_TypeDef *TIMx) 1677:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 1678:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return (uint32_t)(READ_REG(TIMx->RCR)); 1679:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 1680:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1681:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 1682:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Force a continuous copy of the update interrupt flag (UIF) into the timer counter regis 1683:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note This allows both the counter value and a potential roll-over condition signalled by the U 1684:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * in an atomic way. 1685:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR1 UIFREMAP LL_TIM_EnableUIFRemap 1686:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 1687:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 1688:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1689:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_EnableUIFRemap(TIM_TypeDef *TIMx) 1690:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 1691:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** SET_BIT(TIMx->CR1, TIM_CR1_UIFREMAP); 1692:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 1693:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** ARM GAS /tmp/ccLSPxIe.s page 324 1694:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 1695:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Disable update interrupt flag (UIF) remapping. 1696:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR1 UIFREMAP LL_TIM_DisableUIFRemap 1697:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 1698:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 1699:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1700:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_DisableUIFRemap(TIM_TypeDef *TIMx) 1701:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 1702:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** CLEAR_BIT(TIMx->CR1, TIM_CR1_UIFREMAP); 1703:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 1704:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1705:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 1706:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Indicate whether update interrupt flag (UIF) copy is set. 1707:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Counter Counter value 1708:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval State of bit (1 or 0). 1709:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1710:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsActiveUIFCPY(const uint32_t Counter) 1711:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 1712:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return (((Counter & TIM_CNT_UIFCPY) == (TIM_CNT_UIFCPY)) ? 1UL : 0UL); 1713:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 1714:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1715:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 1716:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} 1717:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1718:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1719:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EF_Capture_Compare Capture Compare configuration 1720:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ 1721:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1722:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 1723:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Enable the capture/compare control bits (CCxE, CCxNE and OCxM) preload. 1724:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note CCxE, CCxNE and OCxM bits are preloaded, after having been written, 1725:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * they are updated only when a commutation event (COM) occurs. 1726:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Only on channels that have a complementary output. 1727:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check 1728:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * whether or not a timer instance is able to generate a commutation event. 1729:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR2 CCPC LL_TIM_CC_EnablePreload 1730:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 1731:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 1732:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1733:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_CC_EnablePreload(TIM_TypeDef *TIMx) 1734:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 1735:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** SET_BIT(TIMx->CR2, TIM_CR2_CCPC); 1736:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 1737:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1738:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 1739:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Disable the capture/compare control bits (CCxE, CCxNE and OCxM) preload. 1740:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check 1741:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * whether or not a timer instance is able to generate a commutation event. 1742:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR2 CCPC LL_TIM_CC_DisablePreload 1743:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 1744:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 1745:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1746:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_CC_DisablePreload(TIM_TypeDef *TIMx) 1747:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 1748:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** CLEAR_BIT(TIMx->CR2, TIM_CR2_CCPC); 1749:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 1750:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** ARM GAS /tmp/ccLSPxIe.s page 325 1751:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 1752:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Indicates whether the capture/compare control bits (CCxE, CCxNE and OCxM) preload is en 1753:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR2 CCPC LL_TIM_CC_IsEnabledPreload 1754:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 1755:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval State of bit (1 or 0). 1756:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1757:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledPreload(const TIM_TypeDef *TIMx) 1758:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 1759:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return ((READ_BIT(TIMx->CR2, TIM_CR2_CCPC) == (TIM_CR2_CCPC)) ? 1UL : 0UL); 1760:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 1761:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1762:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 1763:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Set the updated source of the capture/compare control bits (CCxE, CCxNE and OCxM). 1764:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check 1765:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * whether or not a timer instance is able to generate a commutation event. 1766:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR2 CCUS LL_TIM_CC_SetUpdate 1767:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 1768:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param CCUpdateSource This parameter can be one of the following values: 1769:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CCUPDATESOURCE_COMG_ONLY 1770:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI 1771:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 1772:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1773:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_CC_SetUpdate(TIM_TypeDef *TIMx, uint32_t CCUpdateSource) 1774:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 1775:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(TIMx->CR2, TIM_CR2_CCUS, CCUpdateSource); 1776:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 1777:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1778:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 1779:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Set the trigger of the capture/compare DMA request. 1780:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR2 CCDS LL_TIM_CC_SetDMAReqTrigger 1781:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 1782:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param DMAReqTrigger This parameter can be one of the following values: 1783:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CCDMAREQUEST_CC 1784:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CCDMAREQUEST_UPDATE 1785:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 1786:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1787:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_CC_SetDMAReqTrigger(TIM_TypeDef *TIMx, uint32_t DMAReqTrigger) 1788:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 1789:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(TIMx->CR2, TIM_CR2_CCDS, DMAReqTrigger); 1790:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 1791:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1792:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 1793:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Get actual trigger of the capture/compare DMA request. 1794:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR2 CCDS LL_TIM_CC_GetDMAReqTrigger 1795:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 1796:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval Returned value can be one of the following values: 1797:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CCDMAREQUEST_CC 1798:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CCDMAREQUEST_UPDATE 1799:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1800:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_CC_GetDMAReqTrigger(const TIM_TypeDef *TIMx) 1801:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 1802:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return (uint32_t)(READ_BIT(TIMx->CR2, TIM_CR2_CCDS)); 1803:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 1804:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1805:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 1806:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Set the lock level to freeze the 1807:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * configuration of several capture/compare parameters. ARM GAS /tmp/ccLSPxIe.s page 326 1808:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not 1809:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * the lock mechanism is supported by a timer instance. 1810:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll BDTR LOCK LL_TIM_CC_SetLockLevel 1811:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 1812:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param LockLevel This parameter can be one of the following values: 1813:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_LOCKLEVEL_OFF 1814:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_LOCKLEVEL_1 1815:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_LOCKLEVEL_2 1816:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_LOCKLEVEL_3 1817:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 1818:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1819:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_CC_SetLockLevel(TIM_TypeDef *TIMx, uint32_t LockLevel) 1820:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 1821:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(TIMx->BDTR, TIM_BDTR_LOCK, LockLevel); 1822:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 1823:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1824:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 1825:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Enable capture/compare channels. 1826:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCER CC1E LL_TIM_CC_EnableChannel\n 1827:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC1NE LL_TIM_CC_EnableChannel\n 1828:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC2E LL_TIM_CC_EnableChannel\n 1829:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC2NE LL_TIM_CC_EnableChannel\n 1830:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC3E LL_TIM_CC_EnableChannel\n 1831:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC3NE LL_TIM_CC_EnableChannel\n 1832:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC4E LL_TIM_CC_EnableChannel\n 1833:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC5E LL_TIM_CC_EnableChannel\n 1834:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC6E LL_TIM_CC_EnableChannel 1835:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 1836:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Channels This parameter can be a combination of the following values: 1837:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 1838:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1N 1839:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 1840:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2N 1841:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 1842:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3N 1843:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 1844:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH5 1845:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH6 1846:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 1847:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1848:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_CC_EnableChannel(TIM_TypeDef *TIMx, uint32_t Channels) 1849:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 1850:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** SET_BIT(TIMx->CCER, Channels); 1851:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 1852:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1853:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 1854:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Disable capture/compare channels. 1855:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCER CC1E LL_TIM_CC_DisableChannel\n 1856:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC1NE LL_TIM_CC_DisableChannel\n 1857:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC2E LL_TIM_CC_DisableChannel\n 1858:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC2NE LL_TIM_CC_DisableChannel\n 1859:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC3E LL_TIM_CC_DisableChannel\n 1860:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC3NE LL_TIM_CC_DisableChannel\n 1861:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC4E LL_TIM_CC_DisableChannel\n 1862:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC5E LL_TIM_CC_DisableChannel\n 1863:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC6E LL_TIM_CC_DisableChannel 1864:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance ARM GAS /tmp/ccLSPxIe.s page 327 1865:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Channels This parameter can be a combination of the following values: 1866:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 1867:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1N 1868:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 1869:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2N 1870:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 1871:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3N 1872:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 1873:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH5 1874:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH6 1875:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 1876:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1877:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_CC_DisableChannel(TIM_TypeDef *TIMx, uint32_t Channels) 1878:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 1879:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** CLEAR_BIT(TIMx->CCER, Channels); 1880:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 1881:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1882:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 1883:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Indicate whether channel(s) is(are) enabled. 1884:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCER CC1E LL_TIM_CC_IsEnabledChannel\n 1885:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC1NE LL_TIM_CC_IsEnabledChannel\n 1886:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC2E LL_TIM_CC_IsEnabledChannel\n 1887:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC2NE LL_TIM_CC_IsEnabledChannel\n 1888:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC3E LL_TIM_CC_IsEnabledChannel\n 1889:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC3NE LL_TIM_CC_IsEnabledChannel\n 1890:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC4E LL_TIM_CC_IsEnabledChannel\n 1891:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC5E LL_TIM_CC_IsEnabledChannel\n 1892:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC6E LL_TIM_CC_IsEnabledChannel 1893:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 1894:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Channels This parameter can be a combination of the following values: 1895:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 1896:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1N 1897:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 1898:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2N 1899:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 1900:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3N 1901:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 1902:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH5 1903:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH6 1904:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval State of bit (1 or 0). 1905:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1906:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledChannel(const TIM_TypeDef *TIMx, uint32_t Channels) 1907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 1908:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return ((READ_BIT(TIMx->CCER, Channels) == (Channels)) ? 1UL : 0UL); 1909:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 1910:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1911:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 1912:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} 1913:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1914:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1915:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EF_Output_Channel Output channel configuration 1916:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ 1917:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 1919:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Configure an output channel. 1920:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCMR1 CC1S LL_TIM_OC_ConfigOutput\n 1921:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR1 CC2S LL_TIM_OC_ConfigOutput\n ARM GAS /tmp/ccLSPxIe.s page 328 1922:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 CC3S LL_TIM_OC_ConfigOutput\n 1923:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 CC4S LL_TIM_OC_ConfigOutput\n 1924:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR3 CC5S LL_TIM_OC_ConfigOutput\n 1925:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR3 CC6S LL_TIM_OC_ConfigOutput\n 1926:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC1P LL_TIM_OC_ConfigOutput\n 1927:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC2P LL_TIM_OC_ConfigOutput\n 1928:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC3P LL_TIM_OC_ConfigOutput\n 1929:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC4P LL_TIM_OC_ConfigOutput\n 1930:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC5P LL_TIM_OC_ConfigOutput\n 1931:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC6P LL_TIM_OC_ConfigOutput\n 1932:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CR2 OIS1 LL_TIM_OC_ConfigOutput\n 1933:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CR2 OIS2 LL_TIM_OC_ConfigOutput\n 1934:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CR2 OIS3 LL_TIM_OC_ConfigOutput\n 1935:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CR2 OIS4 LL_TIM_OC_ConfigOutput\n 1936:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CR2 OIS5 LL_TIM_OC_ConfigOutput\n 1937:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CR2 OIS6 LL_TIM_OC_ConfigOutput 1938:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 1939:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Channel This parameter can be one of the following values: 1940:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 1941:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 1942:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 1943:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 1944:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH5 1945:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH6 1946:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Configuration This parameter must be a combination of all the following values: 1947:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCPOLARITY_HIGH or @ref LL_TIM_OCPOLARITY_LOW 1948:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCIDLESTATE_LOW or @ref LL_TIM_OCIDLESTATE_HIGH 1949:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 1950:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1951:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configura 1952:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 1953:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 1954:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iC 1955:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** CLEAR_BIT(*pReg, (TIM_CCMR1_CC1S << SHIFT_TAB_OCxx[iChannel])); 1956:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]), 1957:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** (Configuration & TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]); 1958:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]), 1959:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** (Configuration & TIM_CR2_OIS1) << SHIFT_TAB_OISx[iChannel]); 1960:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 1961:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1962:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 1963:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Define the behavior of the output reference signal OCxREF from which 1964:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * OCx and OCxN (when relevant) are derived. 1965:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCMR1 OC1M LL_TIM_OC_SetMode\n 1966:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR1 OC2M LL_TIM_OC_SetMode\n 1967:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 OC3M LL_TIM_OC_SetMode\n 1968:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 OC4M LL_TIM_OC_SetMode\n 1969:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR3 OC5M LL_TIM_OC_SetMode\n 1970:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR3 OC6M LL_TIM_OC_SetMode 1971:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 1972:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Channel This parameter can be one of the following values: 1973:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 1974:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 1975:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 1976:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 1977:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH5 1978:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH6 ARM GAS /tmp/ccLSPxIe.s page 329 1979:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Mode This parameter can be one of the following values: 1980:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_FROZEN 1981:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_ACTIVE 1982:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_INACTIVE 1983:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_TOGGLE 1984:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE 1985:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE 1986:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_PWM1 1987:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_PWM2 1988:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_RETRIG_OPM1 1989:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_RETRIG_OPM2 1990:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_COMBINED_PWM1 1991:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_COMBINED_PWM2 1992:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_ASYMMETRIC_PWM1 1993:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_ASYMMETRIC_PWM2 1994:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 1995:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 1996:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Mode) 1997:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 1998:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 1999:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iC 2000:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel]), Mode << SHIFT 2001:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 2002:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 2003:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 2004:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Get the output compare mode of an output channel. 2005:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCMR1 OC1M LL_TIM_OC_GetMode\n 2006:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR1 OC2M LL_TIM_OC_GetMode\n 2007:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 OC3M LL_TIM_OC_GetMode\n 2008:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 OC4M LL_TIM_OC_GetMode\n 2009:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR3 OC5M LL_TIM_OC_GetMode\n 2010:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR3 OC6M LL_TIM_OC_GetMode 2011:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 2012:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Channel This parameter can be one of the following values: 2013:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 2014:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 2015:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 2016:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 2017:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH5 2018:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH6 2019:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval Returned value can be one of the following values: 2020:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_FROZEN 2021:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_ACTIVE 2022:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_INACTIVE 2023:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_TOGGLE 2024:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE 2025:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE 2026:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_PWM1 2027:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_PWM2 2028:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_RETRIG_OPM1 2029:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_RETRIG_OPM2 2030:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_COMBINED_PWM1 2031:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_COMBINED_PWM2 2032:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_ASYMMETRIC_PWM1 2033:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_ASYMMETRIC_PWM2 2034:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 2035:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_OC_GetMode(const TIM_TypeDef *TIMx, uint32_t Channel) ARM GAS /tmp/ccLSPxIe.s page 330 2036:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 2037:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 2038:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CC 2039:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return (READ_BIT(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel])) >> SHIFT 2040:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 2041:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 2042:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 2043:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Set the polarity of an output channel. 2044:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCER CC1P LL_TIM_OC_SetPolarity\n 2045:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC1NP LL_TIM_OC_SetPolarity\n 2046:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC2P LL_TIM_OC_SetPolarity\n 2047:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC2NP LL_TIM_OC_SetPolarity\n 2048:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC3P LL_TIM_OC_SetPolarity\n 2049:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC3NP LL_TIM_OC_SetPolarity\n 2050:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC4P LL_TIM_OC_SetPolarity\n 2051:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC5P LL_TIM_OC_SetPolarity\n 2052:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC6P LL_TIM_OC_SetPolarity 2053:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 2054:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Channel This parameter can be one of the following values: 2055:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 2056:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1N 2057:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 2058:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2N 2059:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 2060:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3N 2061:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 2062:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH5 2063:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH6 2064:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Polarity This parameter can be one of the following values: 2065:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCPOLARITY_HIGH 2066:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCPOLARITY_LOW 2067:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 2068:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 2069:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_OC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Polarity) 2070:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 2071:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 2072:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]), Polarity << SHIFT_TAB_CCxP[i 2073:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 2074:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 2075:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 2076:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Get the polarity of an output channel. 2077:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCER CC1P LL_TIM_OC_GetPolarity\n 2078:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC1NP LL_TIM_OC_GetPolarity\n 2079:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC2P LL_TIM_OC_GetPolarity\n 2080:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC2NP LL_TIM_OC_GetPolarity\n 2081:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC3P LL_TIM_OC_GetPolarity\n 2082:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC3NP LL_TIM_OC_GetPolarity\n 2083:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC4P LL_TIM_OC_GetPolarity\n 2084:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC5P LL_TIM_OC_GetPolarity\n 2085:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC6P LL_TIM_OC_GetPolarity 2086:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 2087:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Channel This parameter can be one of the following values: 2088:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 2089:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1N 2090:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 2091:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2N 2092:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 ARM GAS /tmp/ccLSPxIe.s page 331 2093:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3N 2094:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 2095:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH5 2096:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH6 2097:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval Returned value can be one of the following values: 2098:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCPOLARITY_HIGH 2099:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCPOLARITY_LOW 2100:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 2101:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity(const TIM_TypeDef *TIMx, uint32_t Channel) 2102:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 2103:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 2104:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return (READ_BIT(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel])) >> SHIFT_TAB_CCxP[iChan 2105:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 2106:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 2107:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 2108:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Set the IDLE state of an output channel 2109:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note This function is significant only for the timer instances 2110:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * supporting the break feature. Macro IS_TIM_BREAK_INSTANCE(TIMx) 2111:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * can be used to check whether or not a timer instance provides 2112:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * a break input. 2113:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR2 OIS1 LL_TIM_OC_SetIdleState\n 2114:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CR2 OIS2N LL_TIM_OC_SetIdleState\n 2115:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CR2 OIS2 LL_TIM_OC_SetIdleState\n 2116:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CR2 OIS2N LL_TIM_OC_SetIdleState\n 2117:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CR2 OIS3 LL_TIM_OC_SetIdleState\n 2118:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CR2 OIS3N LL_TIM_OC_SetIdleState\n 2119:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CR2 OIS4 LL_TIM_OC_SetIdleState\n 2120:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CR2 OIS5 LL_TIM_OC_SetIdleState\n 2121:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CR2 OIS6 LL_TIM_OC_SetIdleState 2122:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 2123:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Channel This parameter can be one of the following values: 2124:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 2125:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1N 2126:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 2127:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2N 2128:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 2129:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3N 2130:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 2131:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH5 2132:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH6 2133:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param IdleState This parameter can be one of the following values: 2134:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCIDLESTATE_LOW 2135:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCIDLESTATE_HIGH 2136:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 2137:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 2138:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_OC_SetIdleState(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t IdleState 2139:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 2140:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 2141:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]), IdleState << SHIFT_TAB_OISx[iC 2142:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 2143:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 2144:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 2145:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Get the IDLE state of an output channel 2146:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR2 OIS1 LL_TIM_OC_GetIdleState\n 2147:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CR2 OIS2N LL_TIM_OC_GetIdleState\n 2148:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CR2 OIS2 LL_TIM_OC_GetIdleState\n 2149:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CR2 OIS2N LL_TIM_OC_GetIdleState\n ARM GAS /tmp/ccLSPxIe.s page 332 2150:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CR2 OIS3 LL_TIM_OC_GetIdleState\n 2151:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CR2 OIS3N LL_TIM_OC_GetIdleState\n 2152:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CR2 OIS4 LL_TIM_OC_GetIdleState\n 2153:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CR2 OIS5 LL_TIM_OC_GetIdleState\n 2154:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CR2 OIS6 LL_TIM_OC_GetIdleState 2155:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 2156:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Channel This parameter can be one of the following values: 2157:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 2158:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1N 2159:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 2160:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2N 2161:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 2162:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3N 2163:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 2164:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH5 2165:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH6 2166:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval Returned value can be one of the following values: 2167:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCIDLESTATE_LOW 2168:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCIDLESTATE_HIGH 2169:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 2170:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_OC_GetIdleState(const TIM_TypeDef *TIMx, uint32_t Channel) 2171:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 2172:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 2173:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return (READ_BIT(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel])) >> SHIFT_TAB_OISx[iChanne 2174:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 2175:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 2176:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 2177:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Enable fast mode for the output channel. 2178:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Acts only if the channel is configured in PWM1 or PWM2 mode. 2179:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCMR1 OC1FE LL_TIM_OC_EnableFast\n 2180:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR1 OC2FE LL_TIM_OC_EnableFast\n 2181:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 OC3FE LL_TIM_OC_EnableFast\n 2182:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 OC4FE LL_TIM_OC_EnableFast\n 2183:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR3 OC5FE LL_TIM_OC_EnableFast\n 2184:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR3 OC6FE LL_TIM_OC_EnableFast 2185:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 2186:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Channel This parameter can be one of the following values: 2187:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 2188:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 2189:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 2190:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 2191:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH5 2192:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH6 2193:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 2194:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 2195:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_OC_EnableFast(TIM_TypeDef *TIMx, uint32_t Channel) 2196:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 2197:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 2198:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iC 2199:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** SET_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel])); 2200:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 2201:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 2202:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 2203:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 2204:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Disable fast mode for the output channel. 2205:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCMR1 OC1FE LL_TIM_OC_DisableFast\n 2206:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR1 OC2FE LL_TIM_OC_DisableFast\n ARM GAS /tmp/ccLSPxIe.s page 333 2207:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 OC3FE LL_TIM_OC_DisableFast\n 2208:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 OC4FE LL_TIM_OC_DisableFast\n 2209:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR3 OC5FE LL_TIM_OC_DisableFast\n 2210:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR3 OC6FE LL_TIM_OC_DisableFast 2211:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 2212:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Channel This parameter can be one of the following values: 2213:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 2214:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 2215:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 2216:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 2217:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH5 2218:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH6 2219:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 2220:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 2221:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_OC_DisableFast(TIM_TypeDef *TIMx, uint32_t Channel) 2222:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 2223:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 2224:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iC 2225:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** CLEAR_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel])); 2226:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 2227:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 2228:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 2229:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 2230:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Indicates whether fast mode is enabled for the output channel. 2231:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCMR1 OC1FE LL_TIM_OC_IsEnabledFast\n 2232:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR1 OC2FE LL_TIM_OC_IsEnabledFast\n 2233:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 OC3FE LL_TIM_OC_IsEnabledFast\n 2234:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 OC4FE LL_TIM_OC_IsEnabledFast\n 2235:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR3 OC5FE LL_TIM_OC_IsEnabledFast\n 2236:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR3 OC6FE LL_TIM_OC_IsEnabledFast 2237:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 2238:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Channel This parameter can be one of the following values: 2239:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 2240:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 2241:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 2242:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 2243:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH5 2244:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH6 2245:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval State of bit (1 or 0). 2246:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 2247:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(const TIM_TypeDef *TIMx, uint32_t Channel) 2248:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 2249:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 2250:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CC 2251:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t bitfield = TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]; 2252:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL); 2253:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 2254:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 2255:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 2256:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Enable compare register (TIMx_CCRx) preload for the output channel. 2257:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCMR1 OC1PE LL_TIM_OC_EnablePreload\n 2258:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR1 OC2PE LL_TIM_OC_EnablePreload\n 2259:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 OC3PE LL_TIM_OC_EnablePreload\n 2260:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 OC4PE LL_TIM_OC_EnablePreload\n 2261:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR3 OC5PE LL_TIM_OC_EnablePreload\n 2262:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR3 OC6PE LL_TIM_OC_EnablePreload 2263:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance ARM GAS /tmp/ccLSPxIe.s page 334 2264:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Channel This parameter can be one of the following values: 2265:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 2266:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 2267:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 2268:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 2269:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH5 2270:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH6 2271:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 2272:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 2273:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_OC_EnablePreload(TIM_TypeDef *TIMx, uint32_t Channel) 2274:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 2275:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 2276:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iC 2277:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** SET_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel])); 2278:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 2279:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 2280:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 2281:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Disable compare register (TIMx_CCRx) preload for the output channel. 2282:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCMR1 OC1PE LL_TIM_OC_DisablePreload\n 2283:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR1 OC2PE LL_TIM_OC_DisablePreload\n 2284:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 OC3PE LL_TIM_OC_DisablePreload\n 2285:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 OC4PE LL_TIM_OC_DisablePreload\n 2286:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR3 OC5PE LL_TIM_OC_DisablePreload\n 2287:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR3 OC6PE LL_TIM_OC_DisablePreload 2288:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 2289:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Channel This parameter can be one of the following values: 2290:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 2291:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 2292:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 2293:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 2294:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH5 2295:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH6 2296:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 2297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 2298:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_OC_DisablePreload(TIM_TypeDef *TIMx, uint32_t Channel) 2299:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 2300:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 2301:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iC 2302:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** CLEAR_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel])); 2303:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 2304:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 2305:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 2306:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Indicates whether compare register (TIMx_CCRx) preload is enabled for the output channe 2307:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCMR1 OC1PE LL_TIM_OC_IsEnabledPreload\n 2308:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR1 OC2PE LL_TIM_OC_IsEnabledPreload\n 2309:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 OC3PE LL_TIM_OC_IsEnabledPreload\n 2310:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 OC4PE LL_TIM_OC_IsEnabledPreload\n 2311:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR3 OC5PE LL_TIM_OC_IsEnabledPreload\n 2312:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR3 OC6PE LL_TIM_OC_IsEnabledPreload 2313:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 2314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Channel This parameter can be one of the following values: 2315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 2316:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 2317:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 2318:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 2319:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH5 2320:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH6 ARM GAS /tmp/ccLSPxIe.s page 335 2321:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval State of bit (1 or 0). 2322:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 2323:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(const TIM_TypeDef *TIMx, uint32_t Channel) 2324:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 2325:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 2326:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CC 2327:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t bitfield = TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]; 2328:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL); 2329:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 2330:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 2331:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 2332:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Enable clearing the output channel on an external event. 2333:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note This function can only be used in Output compare and PWM modes. It does not work in Force 2334:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether 2335:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * or not a timer instance can clear the OCxREF signal on an external event. 2336:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCMR1 OC1CE LL_TIM_OC_EnableClear\n 2337:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR1 OC2CE LL_TIM_OC_EnableClear\n 2338:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 OC3CE LL_TIM_OC_EnableClear\n 2339:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 OC4CE LL_TIM_OC_EnableClear\n 2340:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR3 OC5CE LL_TIM_OC_EnableClear\n 2341:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR3 OC6CE LL_TIM_OC_EnableClear 2342:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 2343:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Channel This parameter can be one of the following values: 2344:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 2345:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 2346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 2347:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 2348:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH5 2349:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH6 2350:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 2351:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 2352:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_OC_EnableClear(TIM_TypeDef *TIMx, uint32_t Channel) 2353:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 2354:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 2355:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iC 2356:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** SET_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel])); 2357:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 2358:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 2359:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 2360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Disable clearing the output channel on an external event. 2361:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether 2362:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * or not a timer instance can clear the OCxREF signal on an external event. 2363:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCMR1 OC1CE LL_TIM_OC_DisableClear\n 2364:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR1 OC2CE LL_TIM_OC_DisableClear\n 2365:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 OC3CE LL_TIM_OC_DisableClear\n 2366:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 OC4CE LL_TIM_OC_DisableClear\n 2367:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR3 OC5CE LL_TIM_OC_DisableClear\n 2368:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR3 OC6CE LL_TIM_OC_DisableClear 2369:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 2370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Channel This parameter can be one of the following values: 2371:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 2372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 2373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 2374:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 2375:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH5 2376:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH6 2377:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None ARM GAS /tmp/ccLSPxIe.s page 336 2378:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 2379:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_OC_DisableClear(TIM_TypeDef *TIMx, uint32_t Channel) 2380:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 2381:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 2382:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iC 2383:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** CLEAR_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel])); 2384:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 2385:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 2386:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 2387:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Indicates clearing the output channel on an external event is enabled for the output ch 2388:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note This function enables clearing the output channel on an external event. 2389:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note This function can only be used in Output compare and PWM modes. It does not work in Force 2390:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether 2391:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * or not a timer instance can clear the OCxREF signal on an external event. 2392:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCMR1 OC1CE LL_TIM_OC_IsEnabledClear\n 2393:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR1 OC2CE LL_TIM_OC_IsEnabledClear\n 2394:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 OC3CE LL_TIM_OC_IsEnabledClear\n 2395:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 OC4CE LL_TIM_OC_IsEnabledClear\n 2396:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR3 OC5CE LL_TIM_OC_IsEnabledClear\n 2397:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR3 OC6CE LL_TIM_OC_IsEnabledClear 2398:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 2399:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Channel This parameter can be one of the following values: 2400:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 2401:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 2402:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 2403:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 2404:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH5 2405:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH6 2406:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval State of bit (1 or 0). 2407:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 2408:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(const TIM_TypeDef *TIMx, uint32_t Channel) 2409:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 2410:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 2411:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CC 2412:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t bitfield = TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]; 2413:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL); 2414:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 2415:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 2416:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 2417:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Set the dead-time delay (delay inserted between the rising edge of the OCxREF signal an 2418:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * the Ocx and OCxN signals). 2419:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not 2420:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * dead-time insertion feature is supported by a timer instance. 2421:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Helper macro @ref __LL_TIM_CALC_DEADTIME can be used to calculate the DeadTime parameter 2422:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll BDTR DTG LL_TIM_OC_SetDeadTime 2423:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 2424:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param DeadTime between Min_Data=0 and Max_Data=255 2425:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 2426:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 2427:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_OC_SetDeadTime(TIM_TypeDef *TIMx, uint32_t DeadTime) 2428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 2429:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(TIMx->BDTR, TIM_BDTR_DTG, DeadTime); 2430:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 2431:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 2432:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 2433:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Set compare value for output channel 1 (TIMx_CCR1). 2434:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF. ARM GAS /tmp/ccLSPxIe.s page 337 2435:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check 2436:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * whether or not a timer instance supports a 32 bits counter. 2437:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not 2438:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * output channel 1 is supported by a timer instance. 2439:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCR1 CCR1 LL_TIM_OC_SetCompareCH1 2440:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 2441:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param CompareValue between Min_Data=0 and Max_Data=65535 2442:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 2443:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 2444:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_OC_SetCompareCH1(TIM_TypeDef *TIMx, uint32_t CompareValue) 2445:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 2446:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** WRITE_REG(TIMx->CCR1, CompareValue); 2447:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 2448:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 2449:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 2450:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Set compare value for output channel 2 (TIMx_CCR2). 2451:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF. 2452:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check 2453:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * whether or not a timer instance supports a 32 bits counter. 2454:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not 2455:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * output channel 2 is supported by a timer instance. 2456:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCR2 CCR2 LL_TIM_OC_SetCompareCH2 2457:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 2458:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param CompareValue between Min_Data=0 and Max_Data=65535 2459:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 2460:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 2461:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_OC_SetCompareCH2(TIM_TypeDef *TIMx, uint32_t CompareValue) 2462:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 2463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** WRITE_REG(TIMx->CCR2, CompareValue); 2464:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 2465:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 2466:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 2467:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Set compare value for output channel 3 (TIMx_CCR3). 2468:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF. 2469:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check 2470:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * whether or not a timer instance supports a 32 bits counter. 2471:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not 2472:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * output channel is supported by a timer instance. 2473:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCR3 CCR3 LL_TIM_OC_SetCompareCH3 2474:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 2475:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param CompareValue between Min_Data=0 and Max_Data=65535 2476:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 2477:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 2478:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_OC_SetCompareCH3(TIM_TypeDef *TIMx, uint32_t CompareValue) 2479:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 2480:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** WRITE_REG(TIMx->CCR3, CompareValue); 2481:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 2482:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 2483:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 2484:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Set compare value for output channel 4 (TIMx_CCR4). 2485:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF. 2486:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check 2487:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * whether or not a timer instance supports a 32 bits counter. 2488:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not 2489:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * output channel 4 is supported by a timer instance. 2490:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCR4 CCR4 LL_TIM_OC_SetCompareCH4 2491:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance ARM GAS /tmp/ccLSPxIe.s page 338 2492:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param CompareValue between Min_Data=0 and Max_Data=65535 2493:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 2494:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 2495:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_OC_SetCompareCH4(TIM_TypeDef *TIMx, uint32_t CompareValue) 2496:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 2497:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** WRITE_REG(TIMx->CCR4, CompareValue); 2498:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 2499:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 2500:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 2501:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Set compare value for output channel 5 (TIMx_CCR5). 2502:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not 2503:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * output channel 5 is supported by a timer instance. 2504:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCR5 CCR5 LL_TIM_OC_SetCompareCH5 2505:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 2506:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param CompareValue between Min_Data=0 and Max_Data=65535 2507:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 2508:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 2509:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_OC_SetCompareCH5(TIM_TypeDef *TIMx, uint32_t CompareValue) 2510:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 2511:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(TIMx->CCR5, TIM_CCR5_CCR5, CompareValue); 2512:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 2513:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 2514:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 2515:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Set compare value for output channel 6 (TIMx_CCR6). 2516:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not 2517:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * output channel 6 is supported by a timer instance. 2518:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCR6 CCR6 LL_TIM_OC_SetCompareCH6 2519:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 2520:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param CompareValue between Min_Data=0 and Max_Data=65535 2521:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 2522:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 2523:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_OC_SetCompareCH6(TIM_TypeDef *TIMx, uint32_t CompareValue) 2524:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 2525:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** WRITE_REG(TIMx->CCR6, CompareValue); 2526:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 2527:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 2528:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 2529:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Get compare value (TIMx_CCR1) set for output channel 1. 2530:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFF 2531:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check 2532:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * whether or not a timer instance supports a 32 bits counter. 2533:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not 2534:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * output channel 1 is supported by a timer instance. 2535:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCR1 CCR1 LL_TIM_OC_GetCompareCH1 2536:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 2537:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval CompareValue (between Min_Data=0 and Max_Data=65535) 2538:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 2539:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH1(const TIM_TypeDef *TIMx) 2540:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 2541:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return (uint32_t)(READ_REG(TIMx->CCR1)); 2542:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 2543:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 2544:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 2545:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Get compare value (TIMx_CCR2) set for output channel 2. 2546:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFF 2547:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check 2548:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * whether or not a timer instance supports a 32 bits counter. ARM GAS /tmp/ccLSPxIe.s page 339 2549:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not 2550:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * output channel 2 is supported by a timer instance. 2551:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCR2 CCR2 LL_TIM_OC_GetCompareCH2 2552:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 2553:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval CompareValue (between Min_Data=0 and Max_Data=65535) 2554:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 2555:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH2(const TIM_TypeDef *TIMx) 2556:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 2557:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return (uint32_t)(READ_REG(TIMx->CCR2)); 2558:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 2559:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 2560:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 2561:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Get compare value (TIMx_CCR3) set for output channel 3. 2562:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFF 2563:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check 2564:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * whether or not a timer instance supports a 32 bits counter. 2565:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not 2566:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * output channel 3 is supported by a timer instance. 2567:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCR3 CCR3 LL_TIM_OC_GetCompareCH3 2568:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 2569:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval CompareValue (between Min_Data=0 and Max_Data=65535) 2570:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 2571:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH3(const TIM_TypeDef *TIMx) 2572:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 2573:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return (uint32_t)(READ_REG(TIMx->CCR3)); 2574:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 2575:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 2576:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 2577:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Get compare value (TIMx_CCR4) set for output channel 4. 2578:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFF 2579:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check 2580:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * whether or not a timer instance supports a 32 bits counter. 2581:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not 2582:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * output channel 4 is supported by a timer instance. 2583:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCR4 CCR4 LL_TIM_OC_GetCompareCH4 2584:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 2585:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval CompareValue (between Min_Data=0 and Max_Data=65535) 2586:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 2587:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH4(const TIM_TypeDef *TIMx) 2588:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 2589:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return (uint32_t)(READ_REG(TIMx->CCR4)); 2590:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 2591:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 2592:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 2593:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Get compare value (TIMx_CCR5) set for output channel 5. 2594:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not 2595:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * output channel 5 is supported by a timer instance. 2596:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCR5 CCR5 LL_TIM_OC_GetCompareCH5 2597:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 2598:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval CompareValue (between Min_Data=0 and Max_Data=65535) 2599:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 2600:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH5(const TIM_TypeDef *TIMx) 2601:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 2602:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return (uint32_t)(READ_BIT(TIMx->CCR5, TIM_CCR5_CCR5)); 2603:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 2604:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 2605:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** ARM GAS /tmp/ccLSPxIe.s page 340 2606:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Get compare value (TIMx_CCR6) set for output channel 6. 2607:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not 2608:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * output channel 6 is supported by a timer instance. 2609:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCR6 CCR6 LL_TIM_OC_GetCompareCH6 2610:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 2611:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval CompareValue (between Min_Data=0 and Max_Data=65535) 2612:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 2613:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH6(const TIM_TypeDef *TIMx) 2614:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 2615:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return (uint32_t)(READ_REG(TIMx->CCR6)); 2616:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 2617:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 2618:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 2619:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Select on which reference signal the OC5REF is combined to. 2620:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_COMBINED3PHASEPWM_INSTANCE(TIMx) can be used to check 2621:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * whether or not a timer instance supports the combined 3-phase PWM mode. 2622:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCR5 GC5C3 LL_TIM_SetCH5CombinedChannels\n 2623:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCR5 GC5C2 LL_TIM_SetCH5CombinedChannels\n 2624:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCR5 GC5C1 LL_TIM_SetCH5CombinedChannels 2625:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 2626:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param GroupCH5 This parameter can be a combination of the following values: 2627:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_GROUPCH5_NONE 2628:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_GROUPCH5_OC1REFC 2629:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_GROUPCH5_OC2REFC 2630:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_GROUPCH5_OC3REFC 2631:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 2632:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 2633:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_SetCH5CombinedChannels(TIM_TypeDef *TIMx, uint32_t GroupCH5) 2634:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 2635:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(TIMx->CCR5, (TIM_CCR5_GC5C3 | TIM_CCR5_GC5C2 | TIM_CCR5_GC5C1), GroupCH5); 2636:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 2637:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 2638:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 2639:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} 2640:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 2641:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 2642:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EF_Input_Channel Input channel configuration 2643:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ 2644:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 2645:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 2646:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Configure input channel. 2647:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCMR1 CC1S LL_TIM_IC_Config\n 2648:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR1 IC1PSC LL_TIM_IC_Config\n 2649:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR1 IC1F LL_TIM_IC_Config\n 2650:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR1 CC2S LL_TIM_IC_Config\n 2651:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR1 IC2PSC LL_TIM_IC_Config\n 2652:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR1 IC2F LL_TIM_IC_Config\n 2653:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 CC3S LL_TIM_IC_Config\n 2654:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 IC3PSC LL_TIM_IC_Config\n 2655:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 IC3F LL_TIM_IC_Config\n 2656:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 CC4S LL_TIM_IC_Config\n 2657:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 IC4PSC LL_TIM_IC_Config\n 2658:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 IC4F LL_TIM_IC_Config\n 2659:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC1P LL_TIM_IC_Config\n 2660:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC1NP LL_TIM_IC_Config\n 2661:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC2P LL_TIM_IC_Config\n 2662:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC2NP LL_TIM_IC_Config\n ARM GAS /tmp/ccLSPxIe.s page 341 2663:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC3P LL_TIM_IC_Config\n 2664:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC3NP LL_TIM_IC_Config\n 2665:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC4P LL_TIM_IC_Config\n 2666:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC4NP LL_TIM_IC_Config 2667:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 2668:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Channel This parameter can be one of the following values: 2669:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 2670:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 2671:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 2672:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 2673:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Configuration This parameter must be a combination of all the following values: 2674:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI or @ref LL_TIM_ACTIVEINPUT_INDIRECTTI or @ref LL_ 2675:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ICPSC_DIV1 or ... or @ref LL_TIM_ICPSC_DIV8 2676:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV1 or ... or @ref LL_TIM_IC_FILTER_FDIV32_N8 2677:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_POLARITY_RISING or @ref LL_TIM_IC_POLARITY_FALLING or @ref LL_TIM_I 2678:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 2679:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 2680:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration) 2681:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 2682:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 2683:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iC 2684:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChanne 2685:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** ((Configuration >> 16U) & (TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S)) 2686:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** << SHIFT_TAB_ICxx[iChannel]); 2687:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]), 2688:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** (Configuration & (TIM_CCER_CC1NP | TIM_CCER_CC1P)) << SHIFT_TAB_CCxP[iChannel]); 2689:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 2690:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 2691:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 2692:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Set the active input. 2693:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCMR1 CC1S LL_TIM_IC_SetActiveInput\n 2694:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR1 CC2S LL_TIM_IC_SetActiveInput\n 2695:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 CC3S LL_TIM_IC_SetActiveInput\n 2696:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 CC4S LL_TIM_IC_SetActiveInput 2697:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 2698:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Channel This parameter can be one of the following values: 2699:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 2700:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 2701:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 2702:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 2703:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param ICActiveInput This parameter can be one of the following values: 2704:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI 2705:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI 2706:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ACTIVEINPUT_TRC 2707:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 2708:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 2709:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_IC_SetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICActiv 2710:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 2711:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 2712:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iC 2713:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), (ICActiveInput >> 16U) << SHIFT 2714:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 2715:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 2716:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 2717:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Get the current active input. 2718:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCMR1 CC1S LL_TIM_IC_GetActiveInput\n 2719:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR1 CC2S LL_TIM_IC_GetActiveInput\n ARM GAS /tmp/ccLSPxIe.s page 342 2720:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 CC3S LL_TIM_IC_GetActiveInput\n 2721:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 CC4S LL_TIM_IC_GetActiveInput 2722:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 2723:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Channel This parameter can be one of the following values: 2724:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 2725:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 2726:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 2727:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 2728:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval Returned value can be one of the following values: 2729:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI 2730:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI 2731:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ACTIVEINPUT_TRC 2732:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 2733:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(const TIM_TypeDef *TIMx, uint32_t Channel) 2734:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 2735:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 2736:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CC 2737:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return ((READ_BIT(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChann 2738:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 2739:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 2740:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 2741:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Set the prescaler of input channel. 2742:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCMR1 IC1PSC LL_TIM_IC_SetPrescaler\n 2743:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR1 IC2PSC LL_TIM_IC_SetPrescaler\n 2744:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 IC3PSC LL_TIM_IC_SetPrescaler\n 2745:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 IC4PSC LL_TIM_IC_SetPrescaler 2746:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 2747:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Channel This parameter can be one of the following values: 2748:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 2749:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 2750:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 2751:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 2752:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param ICPrescaler This parameter can be one of the following values: 2753:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ICPSC_DIV1 2754:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ICPSC_DIV2 2755:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ICPSC_DIV4 2756:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ICPSC_DIV8 2757:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 2758:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 2759:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_IC_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPrescal 2760:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 2761:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 2762:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iC 2763:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel]), (ICPrescaler >> 16U) << SHIFT 2764:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 2765:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 2766:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 2767:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Get the current prescaler value acting on an input channel. 2768:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCMR1 IC1PSC LL_TIM_IC_GetPrescaler\n 2769:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR1 IC2PSC LL_TIM_IC_GetPrescaler\n 2770:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 IC3PSC LL_TIM_IC_GetPrescaler\n 2771:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 IC4PSC LL_TIM_IC_GetPrescaler 2772:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 2773:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Channel This parameter can be one of the following values: 2774:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 2775:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 2776:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 ARM GAS /tmp/ccLSPxIe.s page 343 2777:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 2778:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval Returned value can be one of the following values: 2779:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ICPSC_DIV1 2780:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ICPSC_DIV2 2781:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ICPSC_DIV4 2782:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ICPSC_DIV8 2783:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 2784:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(const TIM_TypeDef *TIMx, uint32_t Channel) 2785:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 2786:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 2787:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CC 2788:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iCha 2789:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 2790:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 2791:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 2792:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Set the input filter duration. 2793:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCMR1 IC1F LL_TIM_IC_SetFilter\n 2794:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR1 IC2F LL_TIM_IC_SetFilter\n 2795:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 IC3F LL_TIM_IC_SetFilter\n 2796:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 IC4F LL_TIM_IC_SetFilter 2797:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 2798:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Channel This parameter can be one of the following values: 2799:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 2800:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 2801:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 2802:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 2803:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param ICFilter This parameter can be one of the following values: 2804:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV1 2805:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV1_N2 2806:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV1_N4 2807:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV1_N8 2808:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV2_N6 2809:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV2_N8 2810:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV4_N6 2811:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV4_N8 2812:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV8_N6 2813:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV8_N8 2814:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV16_N5 2815:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV16_N6 2816:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV16_N8 2817:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV32_N5 2818:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV32_N6 2819:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV32_N8 2820:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 2821:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 2822:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_IC_SetFilter(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICFilter) 2823:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 2824:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 2825:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iC 2826:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel]), (ICFilter >> 16U) << SHIFT_TAB_ 2827:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 2828:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 2829:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 2830:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Get the input filter duration. 2831:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCMR1 IC1F LL_TIM_IC_GetFilter\n 2832:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR1 IC2F LL_TIM_IC_GetFilter\n 2833:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 IC3F LL_TIM_IC_GetFilter\n ARM GAS /tmp/ccLSPxIe.s page 344 2834:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 IC4F LL_TIM_IC_GetFilter 2835:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 2836:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Channel This parameter can be one of the following values: 2837:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 2838:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 2839:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 2840:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 2841:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval Returned value can be one of the following values: 2842:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV1 2843:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV1_N2 2844:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV1_N4 2845:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV1_N8 2846:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV2_N6 2847:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV2_N8 2848:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV4_N6 2849:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV4_N8 2850:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV8_N6 2851:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV8_N8 2852:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV16_N5 2853:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV16_N6 2854:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV16_N8 2855:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV32_N5 2856:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV32_N6 2857:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV32_N8 2858:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 2859:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IC_GetFilter(const TIM_TypeDef *TIMx, uint32_t Channel) 2860:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 2861:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 2862:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CC 2863:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChann 2864:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 2865:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 2866:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 2867:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Set the input channel polarity. 2868:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCER CC1P LL_TIM_IC_SetPolarity\n 2869:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC1NP LL_TIM_IC_SetPolarity\n 2870:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC2P LL_TIM_IC_SetPolarity\n 2871:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC2NP LL_TIM_IC_SetPolarity\n 2872:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC3P LL_TIM_IC_SetPolarity\n 2873:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC3NP LL_TIM_IC_SetPolarity\n 2874:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC4P LL_TIM_IC_SetPolarity\n 2875:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC4NP LL_TIM_IC_SetPolarity 2876:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 2877:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Channel This parameter can be one of the following values: 2878:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 2879:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 2880:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 2881:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 2882:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param ICPolarity This parameter can be one of the following values: 2883:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_POLARITY_RISING 2884:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_POLARITY_FALLING 2885:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE 2886:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 2887:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 2888:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_IC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPolarity 2889:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 2890:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); ARM GAS /tmp/ccLSPxIe.s page 345 2891:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]), 2892:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** ICPolarity << SHIFT_TAB_CCxP[iChannel]); 2893:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 2894:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 2895:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 2896:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Get the current input channel polarity. 2897:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCER CC1P LL_TIM_IC_GetPolarity\n 2898:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC1NP LL_TIM_IC_GetPolarity\n 2899:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC2P LL_TIM_IC_GetPolarity\n 2900:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC2NP LL_TIM_IC_GetPolarity\n 2901:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC3P LL_TIM_IC_GetPolarity\n 2902:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC3NP LL_TIM_IC_GetPolarity\n 2903:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC4P LL_TIM_IC_GetPolarity\n 2904:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC4NP LL_TIM_IC_GetPolarity 2905:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 2906:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Channel This parameter can be one of the following values: 2907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 2908:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 2909:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 2910:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 2911:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval Returned value can be one of the following values: 2912:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_POLARITY_RISING 2913:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_POLARITY_FALLING 2914:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE 2915:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 2916:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IC_GetPolarity(const TIM_TypeDef *TIMx, uint32_t Channel) 2917:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 2918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 2919:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return (READ_BIT(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel])) >> 2920:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** SHIFT_TAB_CCxP[iChannel]); 2921:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 2922:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 2923:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 2924:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Connect the TIMx_CH1, CH2 and CH3 pins to the TI1 input (XOR combination). 2925:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not 2926:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * a timer instance provides an XOR input. 2927:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR2 TI1S LL_TIM_IC_EnableXORCombination 2928:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 2929:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 2930:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 2931:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_IC_EnableXORCombination(TIM_TypeDef *TIMx) 2932:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 2933:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** SET_BIT(TIMx->CR2, TIM_CR2_TI1S); 2934:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 2935:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 2936:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 2937:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Disconnect the TIMx_CH1, CH2 and CH3 pins from the TI1 input. 2938:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not 2939:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * a timer instance provides an XOR input. 2940:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR2 TI1S LL_TIM_IC_DisableXORCombination 2941:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 2942:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 2943:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 2944:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_IC_DisableXORCombination(TIM_TypeDef *TIMx) 2945:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 2946:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** CLEAR_BIT(TIMx->CR2, TIM_CR2_TI1S); 2947:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } ARM GAS /tmp/ccLSPxIe.s page 346 2948:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 2949:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 2950:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Indicates whether the TIMx_CH1, CH2 and CH3 pins are connectected to the TI1 input. 2951:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not 2952:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * a timer instance provides an XOR input. 2953:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR2 TI1S LL_TIM_IC_IsEnabledXORCombination 2954:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 2955:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval State of bit (1 or 0). 2956:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 2957:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IC_IsEnabledXORCombination(const TIM_TypeDef *TIMx) 2958:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 2959:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return ((READ_BIT(TIMx->CR2, TIM_CR2_TI1S) == (TIM_CR2_TI1S)) ? 1UL : 0UL); 2960:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 2961:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 2962:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 2963:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Get captured value for input channel 1. 2964:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xF 2965:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check 2966:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * whether or not a timer instance supports a 32 bits counter. 2967:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not 2968:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * input channel 1 is supported by a timer instance. 2969:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCR1 CCR1 LL_TIM_IC_GetCaptureCH1 2970:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 2971:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval CapturedValue (between Min_Data=0 and Max_Data=65535) 2972:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 2973:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH1(const TIM_TypeDef *TIMx) 2974:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 2975:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return (uint32_t)(READ_REG(TIMx->CCR1)); 2976:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 2977:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 2978:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 2979:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Get captured value for input channel 2. 2980:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xF 2981:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check 2982:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * whether or not a timer instance supports a 32 bits counter. 2983:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not 2984:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * input channel 2 is supported by a timer instance. 2985:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCR2 CCR2 LL_TIM_IC_GetCaptureCH2 2986:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 2987:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval CapturedValue (between Min_Data=0 and Max_Data=65535) 2988:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 2989:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH2(const TIM_TypeDef *TIMx) 2990:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 2991:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return (uint32_t)(READ_REG(TIMx->CCR2)); 2992:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 2993:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 2994:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 2995:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Get captured value for input channel 3. 2996:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xF 2997:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check 2998:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * whether or not a timer instance supports a 32 bits counter. 2999:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not 3000:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * input channel 3 is supported by a timer instance. 3001:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCR3 CCR3 LL_TIM_IC_GetCaptureCH3 3002:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3003:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval CapturedValue (between Min_Data=0 and Max_Data=65535) 3004:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ ARM GAS /tmp/ccLSPxIe.s page 347 3005:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH3(const TIM_TypeDef *TIMx) 3006:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3007:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return (uint32_t)(READ_REG(TIMx->CCR3)); 3008:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3009:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3010:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3011:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Get captured value for input channel 4. 3012:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xF 3013:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check 3014:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * whether or not a timer instance supports a 32 bits counter. 3015:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not 3016:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * input channel 4 is supported by a timer instance. 3017:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCR4 CCR4 LL_TIM_IC_GetCaptureCH4 3018:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3019:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval CapturedValue (between Min_Data=0 and Max_Data=65535) 3020:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3021:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH4(const TIM_TypeDef *TIMx) 3022:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3023:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return (uint32_t)(READ_REG(TIMx->CCR4)); 3024:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3025:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3026:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3027:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} 3028:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3029:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3030:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EF_Clock_Selection Counter clock selection 3031:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ 3032:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3033:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3034:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Enable external clock mode 2. 3035:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note When external clock mode 2 is enabled the counter is clocked by any active edge on the ET 3036:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check 3037:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * whether or not a timer instance supports external clock mode2. 3038:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SMCR ECE LL_TIM_EnableExternalClock 3039:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3040:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 3041:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3042:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_EnableExternalClock(TIM_TypeDef *TIMx) 3043:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3044:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** SET_BIT(TIMx->SMCR, TIM_SMCR_ECE); 3045:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3046:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3047:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3048:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Disable external clock mode 2. 3049:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check 3050:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * whether or not a timer instance supports external clock mode2. 3051:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SMCR ECE LL_TIM_DisableExternalClock 3052:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3053:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 3054:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3055:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_DisableExternalClock(TIM_TypeDef *TIMx) 3056:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3057:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** CLEAR_BIT(TIMx->SMCR, TIM_SMCR_ECE); 3058:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3059:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3060:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3061:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Indicate whether external clock mode 2 is enabled. ARM GAS /tmp/ccLSPxIe.s page 348 3062:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check 3063:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * whether or not a timer instance supports external clock mode2. 3064:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SMCR ECE LL_TIM_IsEnabledExternalClock 3065:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3066:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval State of bit (1 or 0). 3067:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3068:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsEnabledExternalClock(const TIM_TypeDef *TIMx) 3069:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3070:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return ((READ_BIT(TIMx->SMCR, TIM_SMCR_ECE) == (TIM_SMCR_ECE)) ? 1UL : 0UL); 3071:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3072:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3073:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3074:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Set the clock source of the counter clock. 3075:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note when selected clock source is external clock mode 1, the timer input 3076:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * the external clock is applied is selected by calling the @ref LL_TIM_SetTriggerInput() 3077:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * function. This timer input must be configured by calling 3078:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * the @ref LL_TIM_IC_Config() function. 3079:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(TIMx) can be used to check 3080:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * whether or not a timer instance supports external clock mode1. 3081:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check 3082:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * whether or not a timer instance supports external clock mode2. 3083:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SMCR SMS LL_TIM_SetClockSource\n 3084:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * SMCR ECE LL_TIM_SetClockSource 3085:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3086:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param ClockSource This parameter can be one of the following values: 3087:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CLOCKSOURCE_INTERNAL 3088:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE1 3089:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE2 3090:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 3091:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3092:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_SetClockSource(TIM_TypeDef *TIMx, uint32_t ClockSource) 6193 .loc 5 3092 22 view .LVU1917 6194 .LBB526: 3093:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3094:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS | TIM_SMCR_ECE, ClockSource); 6195 .loc 5 3094 3 view .LVU1918 6196 006a 9968 ldr r1, [r3, #8] 6197 006c 0A4A ldr r2, .L364+16 6198 006e 0A40 ands r2, r2, r1 6199 0070 9A60 str r2, [r3, #8] 6200 .LVL590: 6201 .loc 5 3094 3 is_stmt 0 view .LVU1919 6202 .LBE526: 6203 .LBE525: 1653:Src/main.c **** LL_TIM_DisableMasterSlaveMode(TIM2); 6204 .loc 1 1653 3 is_stmt 1 view .LVU1920 6205 .LBB527: 6206 .LBI527: 3095:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3096:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3097:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3098:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Set the encoder interface mode. 3099:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx) can be used to check 3100:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * whether or not a timer instance supports the encoder mode. 3101:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SMCR SMS LL_TIM_SetEncoderMode 3102:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3103:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param EncoderMode This parameter can be one of the following values: ARM GAS /tmp/ccLSPxIe.s page 349 3104:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ENCODERMODE_X2_TI1 3105:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ENCODERMODE_X2_TI2 3106:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ENCODERMODE_X4_TI12 3107:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 3108:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3109:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_SetEncoderMode(TIM_TypeDef *TIMx, uint32_t EncoderMode) 3110:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3111:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, EncoderMode); 3112:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3113:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3114:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3115:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} 3116:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3117:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3118:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EF_Timer_Synchronization Timer synchronisation configuration 3119:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ 3120:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3121:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3122:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Set the trigger output (TRGO) used for timer synchronization . 3123:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_MASTER_INSTANCE(TIMx) can be used to check 3124:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * whether or not a timer instance can operate as a master timer. 3125:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR2 MMS LL_TIM_SetTriggerOutput 3126:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3127:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TimerSynchronization This parameter can be one of the following values: 3128:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TRGO_RESET 3129:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TRGO_ENABLE 3130:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TRGO_UPDATE 3131:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TRGO_CC1IF 3132:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TRGO_OC1REF 3133:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TRGO_OC2REF 3134:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TRGO_OC3REF 3135:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TRGO_OC4REF 3136:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 3137:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3138:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_SetTriggerOutput(TIM_TypeDef *TIMx, uint32_t TimerSynchronization) 6207 .loc 5 3138 22 view .LVU1921 6208 .LBB528: 3139:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3140:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(TIMx->CR2, TIM_CR2_MMS, TimerSynchronization); 6209 .loc 5 3140 3 view .LVU1922 6210 0072 5A68 ldr r2, [r3, #4] 6211 0074 22F07002 bic r2, r2, #112 6212 0078 5A60 str r2, [r3, #4] 6213 .LVL591: 6214 .loc 5 3140 3 is_stmt 0 view .LVU1923 6215 .LBE528: 6216 .LBE527: 1654:Src/main.c **** /* USER CODE BEGIN TIM2_Init 2 */ 6217 .loc 1 1654 3 is_stmt 1 view .LVU1924 6218 .LBB529: 6219 .LBI529: 3141:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3142:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3143:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3144:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Set the trigger output 2 (TRGO2) used for ADC synchronization . 3145:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_TRGO2_INSTANCE(TIMx) can be used to check 3146:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * whether or not a timer instance can be used for ADC synchronization. ARM GAS /tmp/ccLSPxIe.s page 350 3147:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR2 MMS2 LL_TIM_SetTriggerOutput2 3148:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer Instance 3149:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param ADCSynchronization This parameter can be one of the following values: 3150:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TRGO2_RESET 3151:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TRGO2_ENABLE 3152:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TRGO2_UPDATE 3153:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TRGO2_CC1F 3154:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TRGO2_OC1 3155:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TRGO2_OC2 3156:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TRGO2_OC3 3157:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TRGO2_OC4 3158:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TRGO2_OC5 3159:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TRGO2_OC6 3160:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TRGO2_OC4_RISINGFALLING 3161:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TRGO2_OC6_RISINGFALLING 3162:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TRGO2_OC4_RISING_OC6_RISING 3163:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TRGO2_OC4_RISING_OC6_FALLING 3164:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TRGO2_OC5_RISING_OC6_RISING 3165:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TRGO2_OC5_RISING_OC6_FALLING 3166:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 3167:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3168:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_SetTriggerOutput2(TIM_TypeDef *TIMx, uint32_t ADCSynchronization) 3169:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3170:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(TIMx->CR2, TIM_CR2_MMS2, ADCSynchronization); 3171:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3172:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3173:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3174:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Set the synchronization mode of a slave timer. 3175:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not 3176:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * a timer instance can operate as a slave timer. 3177:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SMCR SMS LL_TIM_SetSlaveMode 3178:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3179:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param SlaveMode This parameter can be one of the following values: 3180:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_SLAVEMODE_DISABLED 3181:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_SLAVEMODE_RESET 3182:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_SLAVEMODE_GATED 3183:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_SLAVEMODE_TRIGGER 3184:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_SLAVEMODE_COMBINED_RESETTRIGGER 3185:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 3186:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3187:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_SetSlaveMode(TIM_TypeDef *TIMx, uint32_t SlaveMode) 3188:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3189:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, SlaveMode); 3190:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3191:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3192:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3193:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Set the selects the trigger input to be used to synchronize the counter. 3194:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not 3195:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * a timer instance can operate as a slave timer. 3196:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SMCR TS LL_TIM_SetTriggerInput 3197:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3198:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TriggerInput This parameter can be one of the following values: 3199:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TS_ITR0 3200:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TS_ITR1 3201:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TS_ITR2 3202:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TS_ITR3 3203:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TS_TI1F_ED ARM GAS /tmp/ccLSPxIe.s page 351 3204:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TS_TI1FP1 3205:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TS_TI2FP2 3206:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TS_ETRF 3207:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 3208:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3209:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_SetTriggerInput(TIM_TypeDef *TIMx, uint32_t TriggerInput) 3210:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3211:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(TIMx->SMCR, TIM_SMCR_TS, TriggerInput); 3212:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3213:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3214:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3215:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Enable the Master/Slave mode. 3216:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not 3217:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * a timer instance can operate as a slave timer. 3218:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SMCR MSM LL_TIM_EnableMasterSlaveMode 3219:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3220:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 3221:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3222:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_EnableMasterSlaveMode(TIM_TypeDef *TIMx) 3223:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3224:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** SET_BIT(TIMx->SMCR, TIM_SMCR_MSM); 3225:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3226:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3227:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3228:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Disable the Master/Slave mode. 3229:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not 3230:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * a timer instance can operate as a slave timer. 3231:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SMCR MSM LL_TIM_DisableMasterSlaveMode 3232:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3233:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 3234:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3235:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_DisableMasterSlaveMode(TIM_TypeDef *TIMx) 6220 .loc 5 3235 22 view .LVU1925 6221 .LBB530: 3236:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3237:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** CLEAR_BIT(TIMx->SMCR, TIM_SMCR_MSM); 6222 .loc 5 3237 3 view .LVU1926 6223 007a 9A68 ldr r2, [r3, #8] 6224 007c 22F08002 bic r2, r2, #128 6225 0080 9A60 str r2, [r3, #8] 6226 .LVL592: 6227 .loc 5 3237 3 is_stmt 0 view .LVU1927 6228 .LBE530: 6229 .LBE529: 1659:Src/main.c **** 6230 .loc 1 1659 1 view .LVU1928 6231 0082 06B0 add sp, sp, #24 6232 .LCFI60: 6233 .cfi_def_cfa_offset 8 6234 @ sp needed 6235 0084 10BD pop {r4, pc} 6236 .L365: 6237 0086 00BF .align 2 6238 .L364: 6239 0088 00380240 .word 1073887232 6240 008c 00ED00E0 .word -536810240 6241 0090 00E100E0 .word -536813312 ARM GAS /tmp/ccLSPxIe.s page 352 6242 0094 40D10C00 .word 840000 6243 0098 F8BFFEFF .word -81928 6244 .cfi_endproc 6245 .LFE1195: 6247 .section .text.MX_TIM5_Init,"ax",%progbits 6248 .align 1 6249 .syntax unified 6250 .thumb 6251 .thumb_func 6253 MX_TIM5_Init: 6254 .LFB1197: 1726:Src/main.c **** 6255 .loc 1 1726 1 is_stmt 1 view -0 6256 .cfi_startproc 6257 @ args = 0, pretend = 0, frame = 24 6258 @ frame_needed = 0, uses_anonymous_args = 0 6259 0000 10B5 push {r4, lr} 6260 .LCFI61: 6261 .cfi_def_cfa_offset 8 6262 .cfi_offset 4, -8 6263 .cfi_offset 14, -4 6264 0002 86B0 sub sp, sp, #24 6265 .LCFI62: 6266 .cfi_def_cfa_offset 32 1732:Src/main.c **** 6267 .loc 1 1732 3 view .LVU1930 1732:Src/main.c **** 6268 .loc 1 1732 22 is_stmt 0 view .LVU1931 6269 0004 0024 movs r4, #0 6270 0006 0194 str r4, [sp, #4] 6271 0008 0294 str r4, [sp, #8] 6272 000a 0394 str r4, [sp, #12] 6273 000c 0494 str r4, [sp, #16] 6274 000e 0594 str r4, [sp, #20] 1735:Src/main.c **** 6275 .loc 1 1735 3 is_stmt 1 view .LVU1932 6276 .LVL593: 6277 .LBB531: 6278 .LBI531: 1071:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { 6279 .loc 3 1071 22 view .LVU1933 6280 .LBB532: 1073:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** SET_BIT(RCC->APB1ENR, Periphs); 6281 .loc 3 1073 3 view .LVU1934 1074:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Delay after an RCC peripheral clock enabling */ 6282 .loc 3 1074 3 view .LVU1935 6283 0010 1C4B ldr r3, .L368 6284 0012 1A6C ldr r2, [r3, #64] 6285 0014 42F00802 orr r2, r2, #8 6286 0018 1A64 str r2, [r3, #64] 1076:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; 6287 .loc 3 1076 3 view .LVU1936 1076:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; 6288 .loc 3 1076 12 is_stmt 0 view .LVU1937 6289 001a 1B6C ldr r3, [r3, #64] 6290 001c 03F00803 and r3, r3, #8 1076:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; ARM GAS /tmp/ccLSPxIe.s page 353 6291 .loc 3 1076 10 view .LVU1938 6292 0020 0093 str r3, [sp] 1077:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } 6293 .loc 3 1077 3 is_stmt 1 view .LVU1939 6294 0022 009B ldr r3, [sp] 6295 .LVL594: 1077:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } 6296 .loc 3 1077 3 is_stmt 0 view .LVU1940 6297 .LBE532: 6298 .LBE531: 1738:Src/main.c **** NVIC_EnableIRQ(TIM5_IRQn); 6299 .loc 1 1738 3 is_stmt 1 view .LVU1941 6300 .LBB533: 6301 .LBI533: 1884:Drivers/CMSIS/Include/core_cm7.h **** { 6302 .loc 2 1884 26 view .LVU1942 6303 .LBB534: 1886:Drivers/CMSIS/Include/core_cm7.h **** } 6304 .loc 2 1886 3 view .LVU1943 1886:Drivers/CMSIS/Include/core_cm7.h **** } 6305 .loc 2 1886 26 is_stmt 0 view .LVU1944 6306 0024 184B ldr r3, .L368+4 6307 0026 D868 ldr r0, [r3, #12] 6308 .LBE534: 6309 .LBE533: 1738:Src/main.c **** NVIC_EnableIRQ(TIM5_IRQn); 6310 .loc 1 1738 3 discriminator 1 view .LVU1945 6311 0028 2246 mov r2, r4 6312 002a 2146 mov r1, r4 6313 002c C0F30220 ubfx r0, r0, #8, #3 6314 0030 FFF7FEFF bl NVIC_EncodePriority 6315 .LVL595: 6316 .LBB535: 6317 .LBI535: 2024:Drivers/CMSIS/Include/core_cm7.h **** { 6318 .loc 2 2024 22 is_stmt 1 view .LVU1946 6319 .LBB536: 2026:Drivers/CMSIS/Include/core_cm7.h **** { 6320 .loc 2 2026 3 view .LVU1947 2028:Drivers/CMSIS/Include/core_cm7.h **** } 6321 .loc 2 2028 5 view .LVU1948 2028:Drivers/CMSIS/Include/core_cm7.h **** } 6322 .loc 2 2028 49 is_stmt 0 view .LVU1949 6323 0034 0001 lsls r0, r0, #4 6324 .LVL596: 2028:Drivers/CMSIS/Include/core_cm7.h **** } 6325 .loc 2 2028 49 view .LVU1950 6326 0036 C0B2 uxtb r0, r0 2028:Drivers/CMSIS/Include/core_cm7.h **** } 6327 .loc 2 2028 47 view .LVU1951 6328 0038 144B ldr r3, .L368+8 6329 003a 83F83203 strb r0, [r3, #818] 6330 .LVL597: 2028:Drivers/CMSIS/Include/core_cm7.h **** } 6331 .loc 2 2028 47 view .LVU1952 6332 .LBE536: 6333 .LBE535: ARM GAS /tmp/ccLSPxIe.s page 354 1739:Src/main.c **** 6334 .loc 1 1739 3 is_stmt 1 view .LVU1953 6335 .LBB537: 6336 .LBI537: 1896:Drivers/CMSIS/Include/core_cm7.h **** { 6337 .loc 2 1896 22 view .LVU1954 6338 .LBB538: 1898:Drivers/CMSIS/Include/core_cm7.h **** { 6339 .loc 2 1898 3 view .LVU1955 1900:Drivers/CMSIS/Include/core_cm7.h **** } 6340 .loc 2 1900 5 view .LVU1956 1900:Drivers/CMSIS/Include/core_cm7.h **** } 6341 .loc 2 1900 43 is_stmt 0 view .LVU1957 6342 003e 4FF48022 mov r2, #262144 6343 0042 5A60 str r2, [r3, #4] 6344 .LVL598: 1900:Drivers/CMSIS/Include/core_cm7.h **** } 6345 .loc 2 1900 43 view .LVU1958 6346 .LBE538: 6347 .LBE537: 1744:Src/main.c **** TIM_InitStruct.CounterMode = LL_TIM_COUNTERMODE_UP; 6348 .loc 1 1744 3 is_stmt 1 view .LVU1959 1744:Src/main.c **** TIM_InitStruct.CounterMode = LL_TIM_COUNTERMODE_UP; 6349 .loc 1 1744 28 is_stmt 0 view .LVU1960 6350 0044 42F21073 movw r3, #10000 6351 0048 ADF80430 strh r3, [sp, #4] @ movhi 1745:Src/main.c **** TIM_InitStruct.Autoreload = 560; 6352 .loc 1 1745 3 is_stmt 1 view .LVU1961 1745:Src/main.c **** TIM_InitStruct.Autoreload = 560; 6353 .loc 1 1745 30 is_stmt 0 view .LVU1962 6354 004c 0294 str r4, [sp, #8] 1746:Src/main.c **** TIM_InitStruct.ClockDivision = LL_TIM_CLOCKDIVISION_DIV1; 6355 .loc 1 1746 3 is_stmt 1 view .LVU1963 1746:Src/main.c **** TIM_InitStruct.ClockDivision = LL_TIM_CLOCKDIVISION_DIV1; 6356 .loc 1 1746 29 is_stmt 0 view .LVU1964 6357 004e 4FF40C73 mov r3, #560 6358 0052 0393 str r3, [sp, #12] 1747:Src/main.c **** LL_TIM_Init(TIM5, &TIM_InitStruct); 6359 .loc 1 1747 3 is_stmt 1 view .LVU1965 1747:Src/main.c **** LL_TIM_Init(TIM5, &TIM_InitStruct); 6360 .loc 1 1747 32 is_stmt 0 view .LVU1966 6361 0054 0494 str r4, [sp, #16] 1748:Src/main.c **** LL_TIM_DisableARRPreload(TIM5); 6362 .loc 1 1748 3 is_stmt 1 view .LVU1967 6363 0056 0E4C ldr r4, .L368+12 6364 0058 01A9 add r1, sp, #4 6365 005a 2046 mov r0, r4 6366 005c FFF7FEFF bl LL_TIM_Init 6367 .LVL599: 1749:Src/main.c **** LL_TIM_SetClockSource(TIM5, LL_TIM_CLOCKSOURCE_INTERNAL); 6368 .loc 1 1749 3 view .LVU1968 6369 .LBB539: 6370 .LBI539: 1504:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 6371 .loc 5 1504 22 view .LVU1969 6372 .LBB540: 1506:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } ARM GAS /tmp/ccLSPxIe.s page 355 6373 .loc 5 1506 3 view .LVU1970 6374 0060 2368 ldr r3, [r4] 6375 0062 23F08003 bic r3, r3, #128 6376 0066 2360 str r3, [r4] 6377 .LVL600: 1506:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 6378 .loc 5 1506 3 is_stmt 0 view .LVU1971 6379 .LBE540: 6380 .LBE539: 1750:Src/main.c **** LL_TIM_SetTriggerOutput(TIM5, LL_TIM_TRGO_RESET); 6381 .loc 1 1750 3 is_stmt 1 view .LVU1972 6382 .LBB541: 6383 .LBI541: 3092:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 6384 .loc 5 3092 22 view .LVU1973 6385 .LBB542: 3094:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 6386 .loc 5 3094 3 view .LVU1974 6387 0068 A268 ldr r2, [r4, #8] 6388 006a 0A4B ldr r3, .L368+16 6389 006c 1340 ands r3, r3, r2 6390 006e A360 str r3, [r4, #8] 6391 .LVL601: 3094:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 6392 .loc 5 3094 3 is_stmt 0 view .LVU1975 6393 .LBE542: 6394 .LBE541: 1751:Src/main.c **** LL_TIM_DisableMasterSlaveMode(TIM5); 6395 .loc 1 1751 3 is_stmt 1 view .LVU1976 6396 .LBB543: 6397 .LBI543: 3138:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 6398 .loc 5 3138 22 view .LVU1977 6399 .LBB544: 3140:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 6400 .loc 5 3140 3 view .LVU1978 6401 0070 6368 ldr r3, [r4, #4] 6402 0072 23F07003 bic r3, r3, #112 6403 0076 6360 str r3, [r4, #4] 6404 .LVL602: 3140:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 6405 .loc 5 3140 3 is_stmt 0 view .LVU1979 6406 .LBE544: 6407 .LBE543: 1752:Src/main.c **** /* USER CODE BEGIN TIM5_Init 2 */ 6408 .loc 1 1752 3 is_stmt 1 view .LVU1980 6409 .LBB545: 6410 .LBI545: 3235:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 6411 .loc 5 3235 22 view .LVU1981 6412 .LBB546: 6413 .loc 5 3237 3 view .LVU1982 6414 0078 A368 ldr r3, [r4, #8] 6415 007a 23F08003 bic r3, r3, #128 6416 007e A360 str r3, [r4, #8] 6417 .LVL603: 6418 .loc 5 3237 3 is_stmt 0 view .LVU1983 ARM GAS /tmp/ccLSPxIe.s page 356 6419 .LBE546: 6420 .LBE545: 1757:Src/main.c **** 6421 .loc 1 1757 1 view .LVU1984 6422 0080 06B0 add sp, sp, #24 6423 .LCFI63: 6424 .cfi_def_cfa_offset 8 6425 @ sp needed 6426 0082 10BD pop {r4, pc} 6427 .L369: 6428 .align 2 6429 .L368: 6430 0084 00380240 .word 1073887232 6431 0088 00ED00E0 .word -536810240 6432 008c 00E100E0 .word -536813312 6433 0090 000C0040 .word 1073744896 6434 0094 F8BFFEFF .word -81928 6435 .cfi_endproc 6436 .LFE1197: 6438 .section .text.MX_TIM7_Init,"ax",%progbits 6439 .align 1 6440 .syntax unified 6441 .thumb 6442 .thumb_func 6444 MX_TIM7_Init: 6445 .LFB1199: 1802:Src/main.c **** 6446 .loc 1 1802 1 is_stmt 1 view -0 6447 .cfi_startproc 6448 @ args = 0, pretend = 0, frame = 24 6449 @ frame_needed = 0, uses_anonymous_args = 0 6450 0000 10B5 push {r4, lr} 6451 .LCFI64: 6452 .cfi_def_cfa_offset 8 6453 .cfi_offset 4, -8 6454 .cfi_offset 14, -4 6455 0002 86B0 sub sp, sp, #24 6456 .LCFI65: 6457 .cfi_def_cfa_offset 32 1808:Src/main.c **** 6458 .loc 1 1808 3 view .LVU1986 1808:Src/main.c **** 6459 .loc 1 1808 22 is_stmt 0 view .LVU1987 6460 0004 0024 movs r4, #0 6461 0006 0194 str r4, [sp, #4] 6462 0008 0294 str r4, [sp, #8] 6463 000a 0394 str r4, [sp, #12] 6464 000c 0494 str r4, [sp, #16] 6465 000e 0594 str r4, [sp, #20] 1811:Src/main.c **** 6466 .loc 1 1811 3 is_stmt 1 view .LVU1988 6467 .LVL604: 6468 .LBB547: 6469 .LBI547: 1071:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { 6470 .loc 3 1071 22 view .LVU1989 6471 .LBB548: ARM GAS /tmp/ccLSPxIe.s page 357 1073:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** SET_BIT(RCC->APB1ENR, Periphs); 6472 .loc 3 1073 3 view .LVU1990 1074:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Delay after an RCC peripheral clock enabling */ 6473 .loc 3 1074 3 view .LVU1991 6474 0010 1A4B ldr r3, .L372 6475 0012 1A6C ldr r2, [r3, #64] 6476 0014 42F02002 orr r2, r2, #32 6477 0018 1A64 str r2, [r3, #64] 1076:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; 6478 .loc 3 1076 3 view .LVU1992 1076:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; 6479 .loc 3 1076 12 is_stmt 0 view .LVU1993 6480 001a 1B6C ldr r3, [r3, #64] 6481 001c 03F02003 and r3, r3, #32 1076:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; 6482 .loc 3 1076 10 view .LVU1994 6483 0020 0093 str r3, [sp] 1077:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } 6484 .loc 3 1077 3 is_stmt 1 view .LVU1995 6485 0022 009B ldr r3, [sp] 6486 .LVL605: 1077:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } 6487 .loc 3 1077 3 is_stmt 0 view .LVU1996 6488 .LBE548: 6489 .LBE547: 1814:Src/main.c **** NVIC_EnableIRQ(TIM7_IRQn); 6490 .loc 1 1814 3 is_stmt 1 view .LVU1997 6491 .LBB549: 6492 .LBI549: 1884:Drivers/CMSIS/Include/core_cm7.h **** { 6493 .loc 2 1884 26 view .LVU1998 6494 .LBB550: 1886:Drivers/CMSIS/Include/core_cm7.h **** } 6495 .loc 2 1886 3 view .LVU1999 1886:Drivers/CMSIS/Include/core_cm7.h **** } 6496 .loc 2 1886 26 is_stmt 0 view .LVU2000 6497 0024 164B ldr r3, .L372+4 6498 0026 D868 ldr r0, [r3, #12] 6499 .LBE550: 6500 .LBE549: 1814:Src/main.c **** NVIC_EnableIRQ(TIM7_IRQn); 6501 .loc 1 1814 3 discriminator 1 view .LVU2001 6502 0028 2246 mov r2, r4 6503 002a 2146 mov r1, r4 6504 002c C0F30220 ubfx r0, r0, #8, #3 6505 0030 FFF7FEFF bl NVIC_EncodePriority 6506 .LVL606: 6507 .LBB551: 6508 .LBI551: 2024:Drivers/CMSIS/Include/core_cm7.h **** { 6509 .loc 2 2024 22 is_stmt 1 view .LVU2002 6510 .LBB552: 2026:Drivers/CMSIS/Include/core_cm7.h **** { 6511 .loc 2 2026 3 view .LVU2003 2028:Drivers/CMSIS/Include/core_cm7.h **** } 6512 .loc 2 2028 5 view .LVU2004 2028:Drivers/CMSIS/Include/core_cm7.h **** } ARM GAS /tmp/ccLSPxIe.s page 358 6513 .loc 2 2028 49 is_stmt 0 view .LVU2005 6514 0034 0001 lsls r0, r0, #4 6515 .LVL607: 2028:Drivers/CMSIS/Include/core_cm7.h **** } 6516 .loc 2 2028 49 view .LVU2006 6517 0036 C0B2 uxtb r0, r0 2028:Drivers/CMSIS/Include/core_cm7.h **** } 6518 .loc 2 2028 47 view .LVU2007 6519 0038 124B ldr r3, .L372+8 6520 003a 83F83703 strb r0, [r3, #823] 6521 .LVL608: 2028:Drivers/CMSIS/Include/core_cm7.h **** } 6522 .loc 2 2028 47 view .LVU2008 6523 .LBE552: 6524 .LBE551: 1815:Src/main.c **** 6525 .loc 1 1815 3 is_stmt 1 view .LVU2009 6526 .LBB553: 6527 .LBI553: 1896:Drivers/CMSIS/Include/core_cm7.h **** { 6528 .loc 2 1896 22 view .LVU2010 6529 .LBB554: 1898:Drivers/CMSIS/Include/core_cm7.h **** { 6530 .loc 2 1898 3 view .LVU2011 1900:Drivers/CMSIS/Include/core_cm7.h **** } 6531 .loc 2 1900 5 view .LVU2012 1900:Drivers/CMSIS/Include/core_cm7.h **** } 6532 .loc 2 1900 43 is_stmt 0 view .LVU2013 6533 003e 4FF40002 mov r2, #8388608 6534 0042 5A60 str r2, [r3, #4] 6535 .LVL609: 1900:Drivers/CMSIS/Include/core_cm7.h **** } 6536 .loc 2 1900 43 view .LVU2014 6537 .LBE554: 6538 .LBE553: 1820:Src/main.c **** TIM_InitStruct.CounterMode = LL_TIM_COUNTERMODE_UP; 6539 .loc 1 1820 3 is_stmt 1 view .LVU2015 1820:Src/main.c **** TIM_InitStruct.CounterMode = LL_TIM_COUNTERMODE_UP; 6540 .loc 1 1820 28 is_stmt 0 view .LVU2016 6541 0044 40F29733 movw r3, #919 6542 0048 ADF80430 strh r3, [sp, #4] @ movhi 1821:Src/main.c **** TIM_InitStruct.Autoreload = 99; 6543 .loc 1 1821 3 is_stmt 1 view .LVU2017 1821:Src/main.c **** TIM_InitStruct.Autoreload = 99; 6544 .loc 1 1821 30 is_stmt 0 view .LVU2018 6545 004c 0294 str r4, [sp, #8] 1822:Src/main.c **** LL_TIM_Init(TIM7, &TIM_InitStruct); 6546 .loc 1 1822 3 is_stmt 1 view .LVU2019 1822:Src/main.c **** LL_TIM_Init(TIM7, &TIM_InitStruct); 6547 .loc 1 1822 29 is_stmt 0 view .LVU2020 6548 004e 6323 movs r3, #99 6549 0050 0393 str r3, [sp, #12] 1823:Src/main.c **** LL_TIM_DisableARRPreload(TIM7); 6550 .loc 1 1823 3 is_stmt 1 view .LVU2021 6551 0052 0D4C ldr r4, .L372+12 6552 0054 01A9 add r1, sp, #4 6553 0056 2046 mov r0, r4 ARM GAS /tmp/ccLSPxIe.s page 359 6554 0058 FFF7FEFF bl LL_TIM_Init 6555 .LVL610: 1824:Src/main.c **** LL_TIM_SetTriggerOutput(TIM7, LL_TIM_TRGO_ENABLE); 6556 .loc 1 1824 3 view .LVU2022 6557 .LBB555: 6558 .LBI555: 1504:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 6559 .loc 5 1504 22 view .LVU2023 6560 .LBB556: 1506:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 6561 .loc 5 1506 3 view .LVU2024 6562 005c 2368 ldr r3, [r4] 6563 005e 23F08003 bic r3, r3, #128 6564 0062 2360 str r3, [r4] 6565 .LVL611: 1506:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 6566 .loc 5 1506 3 is_stmt 0 view .LVU2025 6567 .LBE556: 6568 .LBE555: 1825:Src/main.c **** LL_TIM_DisableMasterSlaveMode(TIM7); 6569 .loc 1 1825 3 is_stmt 1 view .LVU2026 6570 .LBB557: 6571 .LBI557: 3138:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 6572 .loc 5 3138 22 view .LVU2027 6573 .LBB558: 3140:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 6574 .loc 5 3140 3 view .LVU2028 6575 0064 6368 ldr r3, [r4, #4] 6576 0066 23F07003 bic r3, r3, #112 6577 006a 43F01003 orr r3, r3, #16 6578 006e 6360 str r3, [r4, #4] 6579 .LVL612: 3140:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 6580 .loc 5 3140 3 is_stmt 0 view .LVU2029 6581 .LBE558: 6582 .LBE557: 1826:Src/main.c **** /* USER CODE BEGIN TIM7_Init 2 */ 6583 .loc 1 1826 3 is_stmt 1 view .LVU2030 6584 .LBB559: 6585 .LBI559: 3235:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 6586 .loc 5 3235 22 view .LVU2031 6587 .LBB560: 6588 .loc 5 3237 3 view .LVU2032 6589 0070 A368 ldr r3, [r4, #8] 6590 0072 23F08003 bic r3, r3, #128 6591 0076 A360 str r3, [r4, #8] 6592 .LVL613: 6593 .loc 5 3237 3 is_stmt 0 view .LVU2033 6594 .LBE560: 6595 .LBE559: 1831:Src/main.c **** 6596 .loc 1 1831 1 view .LVU2034 6597 0078 06B0 add sp, sp, #24 6598 .LCFI66: 6599 .cfi_def_cfa_offset 8 ARM GAS /tmp/ccLSPxIe.s page 360 6600 @ sp needed 6601 007a 10BD pop {r4, pc} 6602 .L373: 6603 .align 2 6604 .L372: 6605 007c 00380240 .word 1073887232 6606 0080 00ED00E0 .word -536810240 6607 0084 00E100E0 .word -536813312 6608 0088 00140040 .word 1073746944 6609 .cfi_endproc 6610 .LFE1199: 6612 .section .text.MX_TIM6_Init,"ax",%progbits 6613 .align 1 6614 .syntax unified 6615 .thumb 6616 .thumb_func 6618 MX_TIM6_Init: 6619 .LFB1198: 1765:Src/main.c **** 6620 .loc 1 1765 1 is_stmt 1 view -0 6621 .cfi_startproc 6622 @ args = 0, pretend = 0, frame = 24 6623 @ frame_needed = 0, uses_anonymous_args = 0 6624 0000 10B5 push {r4, lr} 6625 .LCFI67: 6626 .cfi_def_cfa_offset 8 6627 .cfi_offset 4, -8 6628 .cfi_offset 14, -4 6629 0002 86B0 sub sp, sp, #24 6630 .LCFI68: 6631 .cfi_def_cfa_offset 32 1771:Src/main.c **** 6632 .loc 1 1771 3 view .LVU2036 1771:Src/main.c **** 6633 .loc 1 1771 22 is_stmt 0 view .LVU2037 6634 0004 0024 movs r4, #0 6635 0006 0194 str r4, [sp, #4] 6636 0008 0294 str r4, [sp, #8] 6637 000a 0394 str r4, [sp, #12] 6638 000c 0494 str r4, [sp, #16] 6639 000e 0594 str r4, [sp, #20] 1774:Src/main.c **** 6640 .loc 1 1774 3 is_stmt 1 view .LVU2038 6641 .LVL614: 6642 .LBB561: 6643 .LBI561: 1071:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { 6644 .loc 3 1071 22 view .LVU2039 6645 .LBB562: 1073:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** SET_BIT(RCC->APB1ENR, Periphs); 6646 .loc 3 1073 3 view .LVU2040 1074:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Delay after an RCC peripheral clock enabling */ 6647 .loc 3 1074 3 view .LVU2041 6648 0010 1A4B ldr r3, .L376 6649 0012 1A6C ldr r2, [r3, #64] 6650 0014 42F01002 orr r2, r2, #16 6651 0018 1A64 str r2, [r3, #64] ARM GAS /tmp/ccLSPxIe.s page 361 1076:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; 6652 .loc 3 1076 3 view .LVU2042 1076:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; 6653 .loc 3 1076 12 is_stmt 0 view .LVU2043 6654 001a 1B6C ldr r3, [r3, #64] 6655 001c 03F01003 and r3, r3, #16 1076:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; 6656 .loc 3 1076 10 view .LVU2044 6657 0020 0093 str r3, [sp] 1077:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } 6658 .loc 3 1077 3 is_stmt 1 view .LVU2045 6659 0022 009B ldr r3, [sp] 6660 .LVL615: 1077:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } 6661 .loc 3 1077 3 is_stmt 0 view .LVU2046 6662 .LBE562: 6663 .LBE561: 1777:Src/main.c **** NVIC_EnableIRQ(TIM6_DAC_IRQn); 6664 .loc 1 1777 3 is_stmt 1 view .LVU2047 6665 .LBB563: 6666 .LBI563: 1884:Drivers/CMSIS/Include/core_cm7.h **** { 6667 .loc 2 1884 26 view .LVU2048 6668 .LBB564: 1886:Drivers/CMSIS/Include/core_cm7.h **** } 6669 .loc 2 1886 3 view .LVU2049 1886:Drivers/CMSIS/Include/core_cm7.h **** } 6670 .loc 2 1886 26 is_stmt 0 view .LVU2050 6671 0024 164B ldr r3, .L376+4 6672 0026 D868 ldr r0, [r3, #12] 6673 .LBE564: 6674 .LBE563: 1777:Src/main.c **** NVIC_EnableIRQ(TIM6_DAC_IRQn); 6675 .loc 1 1777 3 discriminator 1 view .LVU2051 6676 0028 2246 mov r2, r4 6677 002a 2146 mov r1, r4 6678 002c C0F30220 ubfx r0, r0, #8, #3 6679 0030 FFF7FEFF bl NVIC_EncodePriority 6680 .LVL616: 6681 .LBB565: 6682 .LBI565: 2024:Drivers/CMSIS/Include/core_cm7.h **** { 6683 .loc 2 2024 22 is_stmt 1 view .LVU2052 6684 .LBB566: 2026:Drivers/CMSIS/Include/core_cm7.h **** { 6685 .loc 2 2026 3 view .LVU2053 2028:Drivers/CMSIS/Include/core_cm7.h **** } 6686 .loc 2 2028 5 view .LVU2054 2028:Drivers/CMSIS/Include/core_cm7.h **** } 6687 .loc 2 2028 49 is_stmt 0 view .LVU2055 6688 0034 0001 lsls r0, r0, #4 6689 .LVL617: 2028:Drivers/CMSIS/Include/core_cm7.h **** } 6690 .loc 2 2028 49 view .LVU2056 6691 0036 C0B2 uxtb r0, r0 2028:Drivers/CMSIS/Include/core_cm7.h **** } 6692 .loc 2 2028 47 view .LVU2057 ARM GAS /tmp/ccLSPxIe.s page 362 6693 0038 124B ldr r3, .L376+8 6694 003a 83F83603 strb r0, [r3, #822] 6695 .LVL618: 2028:Drivers/CMSIS/Include/core_cm7.h **** } 6696 .loc 2 2028 47 view .LVU2058 6697 .LBE566: 6698 .LBE565: 1778:Src/main.c **** 6699 .loc 1 1778 3 is_stmt 1 view .LVU2059 6700 .LBB567: 6701 .LBI567: 1896:Drivers/CMSIS/Include/core_cm7.h **** { 6702 .loc 2 1896 22 view .LVU2060 6703 .LBB568: 1898:Drivers/CMSIS/Include/core_cm7.h **** { 6704 .loc 2 1898 3 view .LVU2061 1900:Drivers/CMSIS/Include/core_cm7.h **** } 6705 .loc 2 1900 5 view .LVU2062 1900:Drivers/CMSIS/Include/core_cm7.h **** } 6706 .loc 2 1900 43 is_stmt 0 view .LVU2063 6707 003e 4FF48002 mov r2, #4194304 6708 0042 5A60 str r2, [r3, #4] 6709 .LVL619: 1900:Drivers/CMSIS/Include/core_cm7.h **** } 6710 .loc 2 1900 43 view .LVU2064 6711 .LBE568: 6712 .LBE567: 1783:Src/main.c **** TIM_InitStruct.CounterMode = LL_TIM_COUNTERMODE_UP; 6713 .loc 1 1783 3 is_stmt 1 view .LVU2065 1783:Src/main.c **** TIM_InitStruct.CounterMode = LL_TIM_COUNTERMODE_UP; 6714 .loc 1 1783 28 is_stmt 0 view .LVU2066 6715 0044 4BF2AF33 movw r3, #45999 6716 0048 ADF80430 strh r3, [sp, #4] @ movhi 1784:Src/main.c **** TIM_InitStruct.Autoreload = 19; 6717 .loc 1 1784 3 is_stmt 1 view .LVU2067 1784:Src/main.c **** TIM_InitStruct.Autoreload = 19; 6718 .loc 1 1784 30 is_stmt 0 view .LVU2068 6719 004c 0294 str r4, [sp, #8] 1785:Src/main.c **** LL_TIM_Init(TIM6, &TIM_InitStruct); 6720 .loc 1 1785 3 is_stmt 1 view .LVU2069 1785:Src/main.c **** LL_TIM_Init(TIM6, &TIM_InitStruct); 6721 .loc 1 1785 29 is_stmt 0 view .LVU2070 6722 004e 1323 movs r3, #19 6723 0050 0393 str r3, [sp, #12] 1786:Src/main.c **** LL_TIM_DisableARRPreload(TIM6); 6724 .loc 1 1786 3 is_stmt 1 view .LVU2071 6725 0052 0D4C ldr r4, .L376+12 6726 0054 01A9 add r1, sp, #4 6727 0056 2046 mov r0, r4 6728 0058 FFF7FEFF bl LL_TIM_Init 6729 .LVL620: 1787:Src/main.c **** LL_TIM_SetTriggerOutput(TIM6, LL_TIM_TRGO_ENABLE); 6730 .loc 1 1787 3 view .LVU2072 6731 .LBB569: 6732 .LBI569: 1504:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 6733 .loc 5 1504 22 view .LVU2073 ARM GAS /tmp/ccLSPxIe.s page 363 6734 .LBB570: 1506:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 6735 .loc 5 1506 3 view .LVU2074 6736 005c 2368 ldr r3, [r4] 6737 005e 23F08003 bic r3, r3, #128 6738 0062 2360 str r3, [r4] 6739 .LVL621: 1506:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 6740 .loc 5 1506 3 is_stmt 0 view .LVU2075 6741 .LBE570: 6742 .LBE569: 1788:Src/main.c **** LL_TIM_DisableMasterSlaveMode(TIM6); 6743 .loc 1 1788 3 is_stmt 1 view .LVU2076 6744 .LBB571: 6745 .LBI571: 3138:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 6746 .loc 5 3138 22 view .LVU2077 6747 .LBB572: 3140:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 6748 .loc 5 3140 3 view .LVU2078 6749 0064 6368 ldr r3, [r4, #4] 6750 0066 23F07003 bic r3, r3, #112 6751 006a 43F01003 orr r3, r3, #16 6752 006e 6360 str r3, [r4, #4] 6753 .LVL622: 3140:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 6754 .loc 5 3140 3 is_stmt 0 view .LVU2079 6755 .LBE572: 6756 .LBE571: 1789:Src/main.c **** /* USER CODE BEGIN TIM6_Init 2 */ 6757 .loc 1 1789 3 is_stmt 1 view .LVU2080 6758 .LBB573: 6759 .LBI573: 3235:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 6760 .loc 5 3235 22 view .LVU2081 6761 .LBB574: 6762 .loc 5 3237 3 view .LVU2082 6763 0070 A368 ldr r3, [r4, #8] 6764 0072 23F08003 bic r3, r3, #128 6765 0076 A360 str r3, [r4, #8] 6766 .LVL623: 6767 .loc 5 3237 3 is_stmt 0 view .LVU2083 6768 .LBE574: 6769 .LBE573: 1794:Src/main.c **** 6770 .loc 1 1794 1 view .LVU2084 6771 0078 06B0 add sp, sp, #24 6772 .LCFI69: 6773 .cfi_def_cfa_offset 8 6774 @ sp needed 6775 007a 10BD pop {r4, pc} 6776 .L377: 6777 .align 2 6778 .L376: 6779 007c 00380240 .word 1073887232 6780 0080 00ED00E0 .word -536810240 6781 0084 00E100E0 .word -536813312 ARM GAS /tmp/ccLSPxIe.s page 364 6782 0088 00100040 .word 1073745920 6783 .cfi_endproc 6784 .LFE1198: 6786 .section .rodata.Init_params.str1.4,"aMS",%progbits,1 6787 .align 2 6788 .LC0: 6789 0000 2F00 .ascii "/\000" 6790 0002 0000 .align 2 6791 .LC1: 6792 0004 434F4D4D .ascii "COMMAND.TXT\000" 6792 414E442E 6792 54585400 6793 .section .text.Init_params,"ax",%progbits 6794 .align 1 6795 .syntax unified 6796 .thumb 6797 .thumb_func 6799 Init_params: 6800 .LFB1208: 2341:Src/main.c **** TO6 = 0; 6801 .loc 1 2341 1 is_stmt 1 view -0 6802 .cfi_startproc 6803 @ args = 0, pretend = 0, frame = 0 6804 @ frame_needed = 0, uses_anonymous_args = 0 6805 0000 2DE9F843 push {r3, r4, r5, r6, r7, r8, r9, lr} 6806 .LCFI70: 6807 .cfi_def_cfa_offset 32 6808 .cfi_offset 3, -32 6809 .cfi_offset 4, -28 6810 .cfi_offset 5, -24 6811 .cfi_offset 6, -20 6812 .cfi_offset 7, -16 6813 .cfi_offset 8, -12 6814 .cfi_offset 9, -8 6815 .cfi_offset 14, -4 2342:Src/main.c **** TO7 = 0; 6816 .loc 1 2342 2 view .LVU2086 2342:Src/main.c **** TO7 = 0; 6817 .loc 1 2342 6 is_stmt 0 view .LVU2087 6818 0004 0023 movs r3, #0 6819 0006 A34A ldr r2, .L390 6820 0008 1360 str r3, [r2] 2343:Src/main.c **** TO7_before = 0; 6821 .loc 1 2343 2 is_stmt 1 view .LVU2088 2343:Src/main.c **** TO7_before = 0; 6822 .loc 1 2343 6 is_stmt 0 view .LVU2089 6823 000a A34A ldr r2, .L390+4 6824 000c 1360 str r3, [r2] 2344:Src/main.c **** TO6_before = 0; 6825 .loc 1 2344 2 is_stmt 1 view .LVU2090 2344:Src/main.c **** TO6_before = 0; 6826 .loc 1 2344 13 is_stmt 0 view .LVU2091 6827 000e A34A ldr r2, .L390+8 6828 0010 1360 str r3, [r2] 2345:Src/main.c **** TO6_uart = 0; 6829 .loc 1 2345 2 is_stmt 1 view .LVU2092 2345:Src/main.c **** TO6_uart = 0; ARM GAS /tmp/ccLSPxIe.s page 365 6830 .loc 1 2345 13 is_stmt 0 view .LVU2093 6831 0012 A34A ldr r2, .L390+12 6832 0014 1360 str r3, [r2] 2346:Src/main.c **** flg_tmt = 0; 6833 .loc 1 2346 2 is_stmt 1 view .LVU2094 2346:Src/main.c **** flg_tmt = 0; 6834 .loc 1 2346 11 is_stmt 0 view .LVU2095 6835 0016 A34A ldr r2, .L390+16 6836 0018 1360 str r3, [r2] 2347:Src/main.c **** UART_rec_incr = 0; 6837 .loc 1 2347 2 is_stmt 1 view .LVU2096 2347:Src/main.c **** UART_rec_incr = 0; 6838 .loc 1 2347 10 is_stmt 0 view .LVU2097 6839 001a A34A ldr r2, .L390+20 6840 001c 1370 strb r3, [r2] 2348:Src/main.c **** fgoto = 0; 6841 .loc 1 2348 2 is_stmt 1 view .LVU2098 2348:Src/main.c **** fgoto = 0; 6842 .loc 1 2348 16 is_stmt 0 view .LVU2099 6843 001e A34A ldr r2, .L390+24 6844 0020 1380 strh r3, [r2] @ movhi 2349:Src/main.c **** sizeoffile = 0; 6845 .loc 1 2349 2 is_stmt 1 view .LVU2100 2349:Src/main.c **** sizeoffile = 0; 6846 .loc 1 2349 8 is_stmt 0 view .LVU2101 6847 0022 A34A ldr r2, .L390+28 6848 0024 1360 str r3, [r2] 2350:Src/main.c **** u_tx_flg = 0; 6849 .loc 1 2350 2 is_stmt 1 view .LVU2102 2350:Src/main.c **** u_tx_flg = 0; 6850 .loc 1 2350 13 is_stmt 0 view .LVU2103 6851 0026 A34A ldr r2, .L390+32 6852 0028 1360 str r3, [r2] 2351:Src/main.c **** u_rx_flg = 0; 6853 .loc 1 2351 2 is_stmt 1 view .LVU2104 2351:Src/main.c **** u_rx_flg = 0; 6854 .loc 1 2351 11 is_stmt 0 view .LVU2105 6855 002a A34A ldr r2, .L390+36 6856 002c 1370 strb r3, [r2] 2352:Src/main.c **** //State_Data[0]=0; 6857 .loc 1 2352 2 is_stmt 1 view .LVU2106 2352:Src/main.c **** //State_Data[0]=0; 6858 .loc 1 2352 11 is_stmt 0 view .LVU2107 6859 002e A34A ldr r2, .L390+40 6860 0030 1370 strb r3, [r2] 2355:Src/main.c **** { 6861 .loc 1 2355 2 is_stmt 1 view .LVU2108 6862 .LBB575: 2355:Src/main.c **** { 6863 .loc 1 2355 7 view .LVU2109 6864 .LVL624: 2355:Src/main.c **** { 6865 .loc 1 2355 2 is_stmt 0 view .LVU2110 6866 0032 05E0 b .L379 6867 .LVL625: 6868 .L380: 2357:Src/main.c **** } ARM GAS /tmp/ccLSPxIe.s page 366 6869 .loc 1 2357 3 is_stmt 1 view .LVU2111 2357:Src/main.c **** } 6870 .loc 1 2357 16 is_stmt 0 view .LVU2112 6871 0034 A24A ldr r2, .L390+44 6872 0036 0021 movs r1, #0 6873 0038 22F81310 strh r1, [r2, r3, lsl #1] @ movhi 2355:Src/main.c **** { 6874 .loc 1 2355 31 is_stmt 1 discriminator 3 view .LVU2113 6875 003c 0133 adds r3, r3, #1 6876 .LVL626: 2355:Src/main.c **** { 6877 .loc 1 2355 31 is_stmt 0 discriminator 3 view .LVU2114 6878 003e 9BB2 uxth r3, r3 6879 .LVL627: 6880 .L379: 2355:Src/main.c **** { 6881 .loc 1 2355 22 is_stmt 1 discriminator 1 view .LVU2115 6882 0040 0E2B cmp r3, #14 6883 0042 F7D9 bls .L380 6884 .LBE575: 2359:Src/main.c **** 6885 .loc 1 2359 2 view .LVU2116 2359:Src/main.c **** 6886 .loc 1 2359 14 is_stmt 0 view .LVU2117 6887 0044 9E4B ldr r3, .L390+44 6888 .LVL628: 2359:Src/main.c **** 6889 .loc 1 2359 14 view .LVU2118 6890 0046 41F21112 movw r2, #4369 6891 004a 1A80 strh r2, [r3] @ movhi 2362:Src/main.c **** Def_setup.LD1_EN = 0; 6892 .loc 1 2362 2 is_stmt 1 view .LVU2119 2362:Src/main.c **** Def_setup.LD1_EN = 0; 6893 .loc 1 2362 21 is_stmt 0 view .LVU2120 6894 004c 9D4B ldr r3, .L390+48 6895 004e 0022 movs r2, #0 6896 0050 DA81 strh r2, [r3, #14] @ movhi 2363:Src/main.c **** Def_setup.LD2_EN = 0; 6897 .loc 1 2363 2 is_stmt 1 view .LVU2121 2363:Src/main.c **** Def_setup.LD2_EN = 0; 6898 .loc 1 2363 19 is_stmt 0 view .LVU2122 6899 0052 DA70 strb r2, [r3, #3] 2364:Src/main.c **** Def_setup.MES_ID = 0; 6900 .loc 1 2364 2 is_stmt 1 view .LVU2123 2364:Src/main.c **** Def_setup.MES_ID = 0; 6901 .loc 1 2364 19 is_stmt 0 view .LVU2124 6902 0054 1A71 strb r2, [r3, #4] 2365:Src/main.c **** Def_setup.PI1_RD = 0; 6903 .loc 1 2365 2 is_stmt 1 view .LVU2125 2365:Src/main.c **** Def_setup.PI1_RD = 0; 6904 .loc 1 2365 19 is_stmt 0 view .LVU2126 6905 0056 1A82 strh r2, [r3, #16] @ movhi 2366:Src/main.c **** Def_setup.PI2_RD = 0; 6906 .loc 1 2366 2 is_stmt 1 view .LVU2127 2366:Src/main.c **** Def_setup.PI2_RD = 0; 6907 .loc 1 2366 19 is_stmt 0 view .LVU2128 6908 0058 1A73 strb r2, [r3, #12] ARM GAS /tmp/ccLSPxIe.s page 367 2367:Src/main.c **** Def_setup.REF1_EN = 0; 6909 .loc 1 2367 2 is_stmt 1 view .LVU2129 2367:Src/main.c **** Def_setup.REF1_EN = 0; 6910 .loc 1 2367 19 is_stmt 0 view .LVU2130 6911 005a 5A73 strb r2, [r3, #13] 2368:Src/main.c **** Def_setup.REF2_EN = 0; 6912 .loc 1 2368 2 is_stmt 1 view .LVU2131 2368:Src/main.c **** Def_setup.REF2_EN = 0; 6913 .loc 1 2368 20 is_stmt 0 view .LVU2132 6914 005c 5A71 strb r2, [r3, #5] 2369:Src/main.c **** Def_setup.SD_EN = 0; 6915 .loc 1 2369 2 is_stmt 1 view .LVU2133 2369:Src/main.c **** Def_setup.SD_EN = 0; 6916 .loc 1 2369 20 is_stmt 0 view .LVU2134 6917 005e 9A71 strb r2, [r3, #6] 2370:Src/main.c **** Def_setup.TEC1_EN = 0; 6918 .loc 1 2370 2 is_stmt 1 view .LVU2135 2370:Src/main.c **** Def_setup.TEC1_EN = 0; 6919 .loc 1 2370 18 is_stmt 0 view .LVU2136 6920 0060 DA72 strb r2, [r3, #11] 2371:Src/main.c **** Def_setup.TEC2_EN = 0; 6921 .loc 1 2371 2 is_stmt 1 view .LVU2137 2371:Src/main.c **** Def_setup.TEC2_EN = 0; 6922 .loc 1 2371 20 is_stmt 0 view .LVU2138 6923 0062 DA71 strb r2, [r3, #7] 2372:Src/main.c **** Def_setup.TS1_EN = 0; 6924 .loc 1 2372 2 is_stmt 1 view .LVU2139 2372:Src/main.c **** Def_setup.TS1_EN = 0; 6925 .loc 1 2372 20 is_stmt 0 view .LVU2140 6926 0064 1A72 strb r2, [r3, #8] 2373:Src/main.c **** Def_setup.TS2_EN = 0; 6927 .loc 1 2373 2 is_stmt 1 view .LVU2141 2373:Src/main.c **** Def_setup.TS2_EN = 0; 6928 .loc 1 2373 19 is_stmt 0 view .LVU2142 6929 0066 5A72 strb r2, [r3, #9] 2374:Src/main.c **** Def_setup.U5V1_EN = 0; 6930 .loc 1 2374 2 is_stmt 1 view .LVU2143 2374:Src/main.c **** Def_setup.U5V1_EN = 0; 6931 .loc 1 2374 19 is_stmt 0 view .LVU2144 6932 0068 9A72 strb r2, [r3, #10] 2375:Src/main.c **** Def_setup.U5V2_EN = 0; 6933 .loc 1 2375 2 is_stmt 1 view .LVU2145 2375:Src/main.c **** Def_setup.U5V2_EN = 0; 6934 .loc 1 2375 20 is_stmt 0 view .LVU2146 6935 006a 5A70 strb r2, [r3, #1] 2376:Src/main.c **** Def_setup.WORK_EN = 0; 6936 .loc 1 2376 2 is_stmt 1 view .LVU2147 2376:Src/main.c **** Def_setup.WORK_EN = 0; 6937 .loc 1 2376 20 is_stmt 0 view .LVU2148 6938 006c 9A70 strb r2, [r3, #2] 2377:Src/main.c **** 6939 .loc 1 2377 2 is_stmt 1 view .LVU2149 2377:Src/main.c **** 6940 .loc 1 2377 20 is_stmt 0 view .LVU2150 6941 006e 1A70 strb r2, [r3] 2379:Src/main.c **** LD2_def_setup.LD_TEMP = 0; 6942 .loc 1 2379 2 is_stmt 1 view .LVU2151 ARM GAS /tmp/ccLSPxIe.s page 368 2379:Src/main.c **** LD2_def_setup.LD_TEMP = 0; 6943 .loc 1 2379 24 is_stmt 0 view .LVU2152 6944 0070 954D ldr r5, .L390+52 6945 0072 2A80 strh r2, [r5] @ movhi 2380:Src/main.c **** LD1_def_setup.P_coef_temp = 0; 6946 .loc 1 2380 2 is_stmt 1 view .LVU2153 2380:Src/main.c **** LD1_def_setup.P_coef_temp = 0; 6947 .loc 1 2380 24 is_stmt 0 view .LVU2154 6948 0074 954C ldr r4, .L390+56 6949 0076 2280 strh r2, [r4] @ movhi 2381:Src/main.c **** LD2_def_setup.P_coef_temp = 0; 6950 .loc 1 2381 2 is_stmt 1 view .LVU2155 2381:Src/main.c **** LD2_def_setup.P_coef_temp = 0; 6951 .loc 1 2381 28 is_stmt 0 view .LVU2156 6952 0078 0022 movs r2, #0 6953 007a 6A60 str r2, [r5, #4] @ float 2382:Src/main.c **** LD1_def_setup.I_coef_temp = 0; 6954 .loc 1 2382 2 is_stmt 1 view .LVU2157 2382:Src/main.c **** LD1_def_setup.I_coef_temp = 0; 6955 .loc 1 2382 28 is_stmt 0 view .LVU2158 6956 007c 6260 str r2, [r4, #4] @ float 2383:Src/main.c **** LD2_def_setup.I_coef_temp = 0; 6957 .loc 1 2383 2 is_stmt 1 view .LVU2159 2383:Src/main.c **** LD2_def_setup.I_coef_temp = 0; 6958 .loc 1 2383 28 is_stmt 0 view .LVU2160 6959 007e AA60 str r2, [r5, #8] @ float 2384:Src/main.c **** 6960 .loc 1 2384 2 is_stmt 1 view .LVU2161 2384:Src/main.c **** 6961 .loc 1 2384 28 is_stmt 0 view .LVU2162 6962 0080 A260 str r2, [r4, #8] @ float 2387:Src/main.c **** LD1_curr_setup = LD1_def_setup; 6963 .loc 1 2387 2 is_stmt 1 view .LVU2163 2387:Src/main.c **** LD1_curr_setup = LD1_def_setup; 6964 .loc 1 2387 13 is_stmt 0 view .LVU2164 6965 0082 934E ldr r6, .L390+60 6966 0084 9C46 mov ip, r3 6967 0086 BCE80F00 ldmia ip!, {r0, r1, r2, r3} 6968 008a 0FC6 stmia r6!, {r0, r1, r2, r3} 6969 008c DCF80030 ldr r3, [ip] 6970 0090 3380 strh r3, [r6] @ movhi 2388:Src/main.c **** LD2_curr_setup = LD2_def_setup; 6971 .loc 1 2388 2 is_stmt 1 view .LVU2165 2388:Src/main.c **** LD2_curr_setup = LD2_def_setup; 6972 .loc 1 2388 17 is_stmt 0 view .LVU2166 6973 0092 904E ldr r6, .L390+64 6974 0094 95E80F00 ldm r5, {r0, r1, r2, r3} 6975 0098 86E80F00 stm r6, {r0, r1, r2, r3} 2389:Src/main.c **** 6976 .loc 1 2389 2 is_stmt 1 view .LVU2167 2389:Src/main.c **** 6977 .loc 1 2389 17 is_stmt 0 view .LVU2168 6978 009c 8E4D ldr r5, .L390+68 6979 009e 94E80F00 ldm r4, {r0, r1, r2, r3} 6980 00a2 85E80F00 stm r5, {r0, r1, r2, r3} 2394:Src/main.c **** LL_TIM_EnableCounter(TIM6); 6981 .loc 1 2394 2 is_stmt 1 view .LVU2169 ARM GAS /tmp/ccLSPxIe.s page 369 6982 .LVL629: 6983 .LBB576: 6984 .LBI576: 3238:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3239:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3240:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3241:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Indicates whether the Master/Slave mode is enabled. 3242:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not 3243:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * a timer instance can operate as a slave timer. 3244:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SMCR MSM LL_TIM_IsEnabledMasterSlaveMode 3245:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3246:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval State of bit (1 or 0). 3247:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3248:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsEnabledMasterSlaveMode(const TIM_TypeDef *TIMx) 3249:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3250:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return ((READ_BIT(TIMx->SMCR, TIM_SMCR_MSM) == (TIM_SMCR_MSM)) ? 1UL : 0UL); 3251:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3252:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3253:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3254:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Configure the external trigger (ETR) input. 3255:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_ETR_INSTANCE(TIMx) can be used to check whether or not 3256:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * a timer instance provides an external trigger input. 3257:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SMCR ETP LL_TIM_ConfigETR\n 3258:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * SMCR ETPS LL_TIM_ConfigETR\n 3259:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * SMCR ETF LL_TIM_ConfigETR 3260:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3261:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param ETRPolarity This parameter can be one of the following values: 3262:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ETR_POLARITY_NONINVERTED 3263:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ETR_POLARITY_INVERTED 3264:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param ETRPrescaler This parameter can be one of the following values: 3265:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ETR_PRESCALER_DIV1 3266:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ETR_PRESCALER_DIV2 3267:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ETR_PRESCALER_DIV4 3268:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ETR_PRESCALER_DIV8 3269:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param ETRFilter This parameter can be one of the following values: 3270:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ETR_FILTER_FDIV1 3271:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N2 3272:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N4 3273:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N8 3274:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ETR_FILTER_FDIV2_N6 3275:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ETR_FILTER_FDIV2_N8 3276:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ETR_FILTER_FDIV4_N6 3277:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ETR_FILTER_FDIV4_N8 3278:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ETR_FILTER_FDIV8_N6 3279:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ETR_FILTER_FDIV8_N8 3280:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N5 3281:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N6 3282:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N8 3283:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N5 3284:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N6 3285:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N8 3286:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 3287:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3288:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_ConfigETR(TIM_TypeDef *TIMx, uint32_t ETRPolarity, uint32_t ETRPrescale 3289:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t ETRFilter) 3290:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3291:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(TIMx->SMCR, TIM_SMCR_ETP | TIM_SMCR_ETPS | TIM_SMCR_ETF, ETRPolarity | ETRPrescaler | ARM GAS /tmp/ccLSPxIe.s page 370 3292:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3293:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3294:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3295:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} 3296:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3298:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EF_Break_Function Break function configuration 3299:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ 3300:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3301:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3302:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Enable the break function. 3303:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not 3304:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * a timer instance provides a break input. 3305:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll BDTR BKE LL_TIM_EnableBRK 3306:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3307:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 3308:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3309:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_EnableBRK(TIM_TypeDef *TIMx) 3310:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3311:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** SET_BIT(TIMx->BDTR, TIM_BDTR_BKE); 3312:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3313:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Disable the break function. 3316:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll BDTR BKE LL_TIM_DisableBRK 3317:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3318:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not 3319:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * a timer instance provides a break input. 3320:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 3321:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3322:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_DisableBRK(TIM_TypeDef *TIMx) 3323:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3324:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BKE); 3325:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3326:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3327:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3328:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Configure the break input. 3329:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not 3330:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * a timer instance provides a break input. 3331:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll BDTR BKP LL_TIM_ConfigBRK\n 3332:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * BDTR BKF LL_TIM_ConfigBRK 3333:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3334:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param BreakPolarity This parameter can be one of the following values: 3335:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK_POLARITY_LOW 3336:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK_POLARITY_HIGH 3337:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param BreakFilter This parameter can be one of the following values: 3338:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK_FILTER_FDIV1 3339:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N2 3340:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N4 3341:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N8 3342:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N6 3343:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N8 3344:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N6 3345:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N8 3346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N6 3347:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N8 3348:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N5 ARM GAS /tmp/ccLSPxIe.s page 371 3349:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N6 3350:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N8 3351:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N5 3352:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N6 3353:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N8 3354:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 3355:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3356:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_ConfigBRK(TIM_TypeDef *TIMx, uint32_t BreakPolarity, 3357:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t BreakFilter) 3358:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3359:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(TIMx->BDTR, TIM_BDTR_BKP | TIM_BDTR_BKF, BreakPolarity | BreakFilter); 3360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3361:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3362:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3363:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Enable the break 2 function. 3364:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not 3365:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * a timer instance provides a second break input. 3366:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll BDTR BK2E LL_TIM_EnableBRK2 3367:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3368:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 3369:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_EnableBRK2(TIM_TypeDef *TIMx) 3371:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** SET_BIT(TIMx->BDTR, TIM_BDTR_BK2E); 3373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3374:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3375:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3376:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Disable the break 2 function. 3377:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not 3378:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * a timer instance provides a second break input. 3379:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll BDTR BK2E LL_TIM_DisableBRK2 3380:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3381:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 3382:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3383:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_DisableBRK2(TIM_TypeDef *TIMx) 3384:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3385:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BK2E); 3386:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3387:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3388:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3389:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Configure the break 2 input. 3390:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not 3391:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * a timer instance provides a second break input. 3392:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll BDTR BK2P LL_TIM_ConfigBRK2\n 3393:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * BDTR BK2F LL_TIM_ConfigBRK2 3394:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3395:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Break2Polarity This parameter can be one of the following values: 3396:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK2_POLARITY_LOW 3397:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK2_POLARITY_HIGH 3398:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Break2Filter This parameter can be one of the following values: 3399:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1 3400:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N2 3401:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N4 3402:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N8 3403:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N6 3404:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N8 3405:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N6 ARM GAS /tmp/ccLSPxIe.s page 372 3406:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N8 3407:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N6 3408:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N8 3409:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N5 3410:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N6 3411:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N8 3412:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N5 3413:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N6 3414:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N8 3415:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 3416:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3417:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_ConfigBRK2(TIM_TypeDef *TIMx, uint32_t Break2Polarity, uint32_t Break2F 3418:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3419:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(TIMx->BDTR, TIM_BDTR_BK2P | TIM_BDTR_BK2F, Break2Polarity | Break2Filter); 3420:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3421:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3422:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3423:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Select the outputs off state (enabled v.s. disabled) in Idle and Run modes. 3424:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not 3425:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * a timer instance provides a break input. 3426:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll BDTR OSSI LL_TIM_SetOffStates\n 3427:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * BDTR OSSR LL_TIM_SetOffStates 3428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3429:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param OffStateIdle This parameter can be one of the following values: 3430:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OSSI_DISABLE 3431:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OSSI_ENABLE 3432:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param OffStateRun This parameter can be one of the following values: 3433:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OSSR_DISABLE 3434:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OSSR_ENABLE 3435:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 3436:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3437:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_SetOffStates(TIM_TypeDef *TIMx, uint32_t OffStateIdle, uint32_t OffStat 3438:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3439:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(TIMx->BDTR, TIM_BDTR_OSSI | TIM_BDTR_OSSR, OffStateIdle | OffStateRun); 3440:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3441:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3442:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3443:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Enable automatic output (MOE can be set by software or automatically when a break input 3444:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not 3445:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * a timer instance provides a break input. 3446:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll BDTR AOE LL_TIM_EnableAutomaticOutput 3447:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3448:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 3449:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3450:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_EnableAutomaticOutput(TIM_TypeDef *TIMx) 3451:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3452:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** SET_BIT(TIMx->BDTR, TIM_BDTR_AOE); 3453:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3454:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3455:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3456:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Disable automatic output (MOE can be set only by software). 3457:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not 3458:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * a timer instance provides a break input. 3459:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll BDTR AOE LL_TIM_DisableAutomaticOutput 3460:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3461:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 3462:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ ARM GAS /tmp/ccLSPxIe.s page 373 3463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_DisableAutomaticOutput(TIM_TypeDef *TIMx) 3464:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3465:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** CLEAR_BIT(TIMx->BDTR, TIM_BDTR_AOE); 3466:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3467:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3468:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3469:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Indicate whether automatic output is enabled. 3470:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not 3471:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * a timer instance provides a break input. 3472:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll BDTR AOE LL_TIM_IsEnabledAutomaticOutput 3473:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3474:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval State of bit (1 or 0). 3475:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3476:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsEnabledAutomaticOutput(const TIM_TypeDef *TIMx) 3477:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3478:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return ((READ_BIT(TIMx->BDTR, TIM_BDTR_AOE) == (TIM_BDTR_AOE)) ? 1UL : 0UL); 3479:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3480:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3481:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3482:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Enable the outputs (set the MOE bit in TIMx_BDTR register). 3483:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by 3484:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * software and is reset in case of break or break2 event 3485:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not 3486:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * a timer instance provides a break input. 3487:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll BDTR MOE LL_TIM_EnableAllOutputs 3488:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3489:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 3490:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3491:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_EnableAllOutputs(TIM_TypeDef *TIMx) 3492:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3493:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** SET_BIT(TIMx->BDTR, TIM_BDTR_MOE); 3494:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3495:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3496:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3497:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Disable the outputs (reset the MOE bit in TIMx_BDTR register). 3498:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by 3499:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * software and is reset in case of break or break2 event. 3500:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not 3501:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * a timer instance provides a break input. 3502:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll BDTR MOE LL_TIM_DisableAllOutputs 3503:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3504:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 3505:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3506:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_DisableAllOutputs(TIM_TypeDef *TIMx) 3507:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3508:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** CLEAR_BIT(TIMx->BDTR, TIM_BDTR_MOE); 3509:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3510:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3511:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3512:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Indicates whether outputs are enabled. 3513:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not 3514:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * a timer instance provides a break input. 3515:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll BDTR MOE LL_TIM_IsEnabledAllOutputs 3516:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3517:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval State of bit (1 or 0). 3518:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3519:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsEnabledAllOutputs(const TIM_TypeDef *TIMx) ARM GAS /tmp/ccLSPxIe.s page 374 3520:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3521:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return ((READ_BIT(TIMx->BDTR, TIM_BDTR_MOE) == (TIM_BDTR_MOE)) ? 1UL : 0UL); 3522:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3523:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3524:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #if defined(TIM_BREAK_INPUT_SUPPORT) 3525:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3526:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Enable the signals connected to the designated timer break input. 3527:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether 3528:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * or not a timer instance allows for break input selection. 3529:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll AF1 BKINE LL_TIM_EnableBreakInputSource\n 3530:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * AF1 BKDFBKE LL_TIM_EnableBreakInputSource\n 3531:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * AF2 BK2INE LL_TIM_EnableBreakInputSource\n 3532:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * AF2 BK2DFBKE LL_TIM_EnableBreakInputSource 3533:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3534:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param BreakInput This parameter can be one of the following values: 3535:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK_INPUT_BKIN 3536:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK_INPUT_BKIN2 3537:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Source This parameter can be one of the following values: 3538:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BKIN_SOURCE_BKIN 3539:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BKIN_SOURCE_DF1BK 3540:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 3541:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3542:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_EnableBreakInputSource(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t 3543:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3544:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput)); 3545:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** SET_BIT(*pReg, Source); 3546:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3547:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3548:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3549:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Disable the signals connected to the designated timer break input. 3550:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether 3551:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * or not a timer instance allows for break input selection. 3552:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll AF1 BKINE LL_TIM_DisableBreakInputSource\n 3553:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * AF1 BKDFBKE LL_TIM_DisableBreakInputSource\n 3554:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * AF2 BK2INE LL_TIM_DisableBreakInputSource\n 3555:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * AF2 BK2DFBKE LL_TIM_DisableBreakInputSource 3556:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3557:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param BreakInput This parameter can be one of the following values: 3558:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK_INPUT_BKIN 3559:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK_INPUT_BKIN2 3560:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Source This parameter can be one of the following values: 3561:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BKIN_SOURCE_BKIN 3562:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BKIN_SOURCE_DF1BK 3563:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 3564:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3565:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_DisableBreakInputSource(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_ 3566:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3567:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput)); 3568:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** CLEAR_BIT(*pReg, Source); 3569:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3570:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3571:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3572:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Set the polarity of the break signal for the timer break input. 3573:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether 3574:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * or not a timer instance allows for break input selection. 3575:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll AF1 BKINP LL_TIM_SetBreakInputSourcePolarity\n 3576:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * AF1 BKDFBKP LL_TIM_SetBreakInputSourcePolarity\n ARM GAS /tmp/ccLSPxIe.s page 375 3577:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * AF2 BK2INP LL_TIM_SetBreakInputSourcePolarity\n 3578:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * AF2 BK2DFBKP LL_TIM_SetBreakInputSourcePolarity 3579:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3580:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param BreakInput This parameter can be one of the following values: 3581:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK_INPUT_BKIN 3582:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK_INPUT_BKIN2 3583:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Source This parameter can be one of the following values: 3584:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BKIN_SOURCE_BKIN 3585:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BKIN_SOURCE_DF1BK 3586:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Polarity This parameter can be one of the following values: 3587:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BKIN_POLARITY_LOW 3588:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BKIN_POLARITY_HIGH 3589:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 3590:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3591:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_SetBreakInputSourcePolarity(TIM_TypeDef *TIMx, uint32_t BreakInput, uin 3592:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t Polarity) 3593:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3594:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput)); 3595:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(*pReg, (TIMx_AF1_BKINP << TIM_POSITION_BRK_SOURCE), (Polarity << TIM_POSITION_BRK_SOUR 3596:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3597:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #endif /* TIM_BREAK_INPUT_SUPPORT */ 3598:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3599:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} 3600:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3601:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3602:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EF_DMA_Burst_Mode DMA burst mode configuration 3603:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ 3604:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3605:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3606:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Configures the timer DMA burst feature. 3607:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_DMABURST_INSTANCE(TIMx) can be used to check whether or 3608:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * not a timer instance supports the DMA burst mode. 3609:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll DCR DBL LL_TIM_ConfigDMABurst\n 3610:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * DCR DBA LL_TIM_ConfigDMABurst 3611:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3612:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param DMABurstBaseAddress This parameter can be one of the following values: 3613:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_BASEADDR_CR1 3614:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_BASEADDR_CR2 3615:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_BASEADDR_SMCR 3616:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_BASEADDR_DIER 3617:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_BASEADDR_SR 3618:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_BASEADDR_EGR 3619:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR1 3620:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR2 3621:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_BASEADDR_CCER 3622:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_BASEADDR_CNT 3623:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_BASEADDR_PSC 3624:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_BASEADDR_ARR 3625:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_BASEADDR_RCR 3626:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR1 3627:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR2 3628:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR3 3629:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR4 3630:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_BASEADDR_BDTR 3631:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_BASEADDR_OR 3632:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR3 3633:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR5 ARM GAS /tmp/ccLSPxIe.s page 376 3634:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR6 3635:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_BASEADDR_AF1 (*) 3636:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_BASEADDR_AF2 (*) 3637:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * (*) value not defined in all devices 3638:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param DMABurstLength This parameter can be one of the following values: 3639:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_LENGTH_1TRANSFER 3640:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_LENGTH_2TRANSFERS 3641:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_LENGTH_3TRANSFERS 3642:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_LENGTH_4TRANSFERS 3643:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_LENGTH_5TRANSFERS 3644:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_LENGTH_6TRANSFERS 3645:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_LENGTH_7TRANSFERS 3646:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_LENGTH_8TRANSFERS 3647:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_LENGTH_9TRANSFERS 3648:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_LENGTH_10TRANSFERS 3649:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_LENGTH_11TRANSFERS 3650:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_LENGTH_12TRANSFERS 3651:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_LENGTH_13TRANSFERS 3652:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_LENGTH_14TRANSFERS 3653:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_LENGTH_15TRANSFERS 3654:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_LENGTH_16TRANSFERS 3655:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_LENGTH_17TRANSFERS 3656:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_LENGTH_18TRANSFERS 3657:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 3658:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3659:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_ConfigDMABurst(TIM_TypeDef *TIMx, uint32_t DMABurstBaseAddress, uint32_ 3660:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3661:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(TIMx->DCR, (TIM_DCR_DBL | TIM_DCR_DBA), (DMABurstBaseAddress | DMABurstLength)); 3662:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3663:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3664:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3665:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} 3666:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3667:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3668:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EF_Timer_Inputs_Remapping Timer input remapping 3669:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ 3670:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3671:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3672:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Remap TIM inputs (input channel, internal/external triggers). 3673:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_REMAP_INSTANCE(TIMx) can be used to check whether or not 3674:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * a some timer inputs can be remapped. 3675:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll TIM2_OR ITR1_RMP LL_TIM_SetRemap\n 3676:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * TIM5_OR TI4_RMP LL_TIM_SetRemap\n 3677:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * TIM11_OR TI1_RMP LL_TIM_SetRemap 3678:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3679:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Remap Remap param depends on the TIMx. Description available only 3680:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * in CHM version of the User Manual (not in .pdf). 3681:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * Otherwise see Reference Manual description of OR registers. 3682:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * 3683:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * Below description summarizes "Timer Instance" and "Remap" param combinations: 3684:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * 3685:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * TIM2: one of the following values 3686:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * 3687:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * ITR1_RMP can be one of the following values 3688:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TIM2_ITR1_RMP_TIM8_TRGO 3689:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TIM2_ITR1_RMP_ETH_PTP 3690:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TIM2_ITR1_RMP_OTG_FS_SOF ARM GAS /tmp/ccLSPxIe.s page 377 3691:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TIM2_ITR1_RMP_OTG_HS_SOF 3692:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * 3693:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * TIM5: one of the following values 3694:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * 3695:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TIM5_TI4_RMP_GPIO 3696:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TIM5_TI4_RMP_LSI 3697:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TIM5_TI4_RMP_LSE 3698:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TIM5_TI4_RMP_RTC 3699:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * 3700:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * TIM11: one of the following values 3701:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * 3702:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TIM11_TI1_RMP_GPIO 3703:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TIM11_TI1_RMP_SPDIFRX 3704:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TIM11_TI1_RMP_HSE 3705:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TIM11_TI1_RMP_MCO1 3706:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * 3707:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 3708:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3709:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_SetRemap(TIM_TypeDef *TIMx, uint32_t Remap) 3710:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3711:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(TIMx->OR, (Remap >> TIMx_OR_RMP_SHIFT), (Remap & TIMx_OR_RMP_MASK)); 3712:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3713:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3714:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3715:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} 3716:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3717:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3718:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EF_FLAG_Management FLAG-Management 3719:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ 3720:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3721:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3722:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Clear the update interrupt flag (UIF). 3723:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SR UIF LL_TIM_ClearFlag_UPDATE 3724:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3725:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 3726:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3727:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_ClearFlag_UPDATE(TIM_TypeDef *TIMx) 3728:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3729:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** WRITE_REG(TIMx->SR, ~(TIM_SR_UIF)); 3730:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3731:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3732:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3733:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Indicate whether update interrupt flag (UIF) is set (update interrupt is pending). 3734:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SR UIF LL_TIM_IsActiveFlag_UPDATE 3735:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3736:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval State of bit (1 or 0). 3737:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3738:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_UPDATE(const TIM_TypeDef *TIMx) 3739:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3740:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return ((READ_BIT(TIMx->SR, TIM_SR_UIF) == (TIM_SR_UIF)) ? 1UL : 0UL); 3741:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3742:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3743:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3744:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Clear the Capture/Compare 1 interrupt flag (CC1F). 3745:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SR CC1IF LL_TIM_ClearFlag_CC1 3746:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3747:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None ARM GAS /tmp/ccLSPxIe.s page 378 3748:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3749:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_ClearFlag_CC1(TIM_TypeDef *TIMx) 3750:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3751:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** WRITE_REG(TIMx->SR, ~(TIM_SR_CC1IF)); 3752:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3753:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3754:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3755:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Indicate whether Capture/Compare 1 interrupt flag (CC1F) is set (Capture/Compare 1 inte 3756:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SR CC1IF LL_TIM_IsActiveFlag_CC1 3757:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3758:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval State of bit (1 or 0). 3759:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3760:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1(const TIM_TypeDef *TIMx) 3761:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3762:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return ((READ_BIT(TIMx->SR, TIM_SR_CC1IF) == (TIM_SR_CC1IF)) ? 1UL : 0UL); 3763:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3764:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3765:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3766:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Clear the Capture/Compare 2 interrupt flag (CC2F). 3767:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SR CC2IF LL_TIM_ClearFlag_CC2 3768:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3769:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 3770:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3771:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_ClearFlag_CC2(TIM_TypeDef *TIMx) 3772:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3773:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** WRITE_REG(TIMx->SR, ~(TIM_SR_CC2IF)); 3774:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3775:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3776:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3777:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Indicate whether Capture/Compare 2 interrupt flag (CC2F) is set (Capture/Compare 2 inte 3778:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SR CC2IF LL_TIM_IsActiveFlag_CC2 3779:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3780:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval State of bit (1 or 0). 3781:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3782:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2(const TIM_TypeDef *TIMx) 3783:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3784:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return ((READ_BIT(TIMx->SR, TIM_SR_CC2IF) == (TIM_SR_CC2IF)) ? 1UL : 0UL); 3785:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3786:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3787:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3788:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Clear the Capture/Compare 3 interrupt flag (CC3F). 3789:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SR CC3IF LL_TIM_ClearFlag_CC3 3790:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3791:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 3792:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3793:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_ClearFlag_CC3(TIM_TypeDef *TIMx) 3794:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3795:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** WRITE_REG(TIMx->SR, ~(TIM_SR_CC3IF)); 3796:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3797:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3798:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3799:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Indicate whether Capture/Compare 3 interrupt flag (CC3F) is set (Capture/Compare 3 inte 3800:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SR CC3IF LL_TIM_IsActiveFlag_CC3 3801:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3802:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval State of bit (1 or 0). 3803:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3804:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3(const TIM_TypeDef *TIMx) ARM GAS /tmp/ccLSPxIe.s page 379 3805:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3806:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return ((READ_BIT(TIMx->SR, TIM_SR_CC3IF) == (TIM_SR_CC3IF)) ? 1UL : 0UL); 3807:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3808:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3809:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3810:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Clear the Capture/Compare 4 interrupt flag (CC4F). 3811:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SR CC4IF LL_TIM_ClearFlag_CC4 3812:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3813:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 3814:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3815:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_ClearFlag_CC4(TIM_TypeDef *TIMx) 3816:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3817:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** WRITE_REG(TIMx->SR, ~(TIM_SR_CC4IF)); 3818:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3819:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3820:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3821:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Indicate whether Capture/Compare 4 interrupt flag (CC4F) is set (Capture/Compare 4 inte 3822:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SR CC4IF LL_TIM_IsActiveFlag_CC4 3823:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3824:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval State of bit (1 or 0). 3825:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3826:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4(const TIM_TypeDef *TIMx) 3827:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3828:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return ((READ_BIT(TIMx->SR, TIM_SR_CC4IF) == (TIM_SR_CC4IF)) ? 1UL : 0UL); 3829:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3830:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3831:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3832:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Clear the Capture/Compare 5 interrupt flag (CC5F). 3833:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SR CC5IF LL_TIM_ClearFlag_CC5 3834:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3835:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 3836:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3837:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_ClearFlag_CC5(TIM_TypeDef *TIMx) 3838:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3839:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** WRITE_REG(TIMx->SR, ~(TIM_SR_CC5IF)); 3840:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3841:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3842:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3843:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Indicate whether Capture/Compare 5 interrupt flag (CC5F) is set (Capture/Compare 5 inte 3844:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SR CC5IF LL_TIM_IsActiveFlag_CC5 3845:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3846:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval State of bit (1 or 0). 3847:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3848:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC5(const TIM_TypeDef *TIMx) 3849:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3850:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return ((READ_BIT(TIMx->SR, TIM_SR_CC5IF) == (TIM_SR_CC5IF)) ? 1UL : 0UL); 3851:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3852:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3853:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3854:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Clear the Capture/Compare 6 interrupt flag (CC6F). 3855:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SR CC6IF LL_TIM_ClearFlag_CC6 3856:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3857:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 3858:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3859:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_ClearFlag_CC6(TIM_TypeDef *TIMx) 3860:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3861:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** WRITE_REG(TIMx->SR, ~(TIM_SR_CC6IF)); ARM GAS /tmp/ccLSPxIe.s page 380 3862:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3863:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3864:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3865:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Indicate whether Capture/Compare 6 interrupt flag (CC6F) is set (Capture/Compare 6 inte 3866:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SR CC6IF LL_TIM_IsActiveFlag_CC6 3867:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3868:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval State of bit (1 or 0). 3869:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3870:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC6(const TIM_TypeDef *TIMx) 3871:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3872:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return ((READ_BIT(TIMx->SR, TIM_SR_CC6IF) == (TIM_SR_CC6IF)) ? 1UL : 0UL); 3873:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3874:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3875:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3876:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Clear the commutation interrupt flag (COMIF). 3877:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SR COMIF LL_TIM_ClearFlag_COM 3878:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3879:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 3880:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3881:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_ClearFlag_COM(TIM_TypeDef *TIMx) 3882:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3883:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** WRITE_REG(TIMx->SR, ~(TIM_SR_COMIF)); 3884:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3885:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3886:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3887:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Indicate whether commutation interrupt flag (COMIF) is set (commutation interrupt is pe 3888:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SR COMIF LL_TIM_IsActiveFlag_COM 3889:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3890:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval State of bit (1 or 0). 3891:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3892:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_COM(const TIM_TypeDef *TIMx) 3893:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3894:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return ((READ_BIT(TIMx->SR, TIM_SR_COMIF) == (TIM_SR_COMIF)) ? 1UL : 0UL); 3895:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3896:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3897:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3898:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Clear the trigger interrupt flag (TIF). 3899:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SR TIF LL_TIM_ClearFlag_TRIG 3900:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3901:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 3902:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3903:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_ClearFlag_TRIG(TIM_TypeDef *TIMx) 3904:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3905:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** WRITE_REG(TIMx->SR, ~(TIM_SR_TIF)); 3906:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3908:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3909:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Indicate whether trigger interrupt flag (TIF) is set (trigger interrupt is pending). 3910:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SR TIF LL_TIM_IsActiveFlag_TRIG 3911:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3912:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval State of bit (1 or 0). 3913:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3914:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_TRIG(const TIM_TypeDef *TIMx) 3915:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3916:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return ((READ_BIT(TIMx->SR, TIM_SR_TIF) == (TIM_SR_TIF)) ? 1UL : 0UL); 3917:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** ARM GAS /tmp/ccLSPxIe.s page 381 3919:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3920:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Clear the break interrupt flag (BIF). 3921:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SR BIF LL_TIM_ClearFlag_BRK 3922:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3923:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 3924:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3925:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_ClearFlag_BRK(TIM_TypeDef *TIMx) 3926:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3927:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** WRITE_REG(TIMx->SR, ~(TIM_SR_BIF)); 3928:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3929:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3930:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3931:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Indicate whether break interrupt flag (BIF) is set (break interrupt is pending). 3932:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SR BIF LL_TIM_IsActiveFlag_BRK 3933:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3934:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval State of bit (1 or 0). 3935:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3936:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK(const TIM_TypeDef *TIMx) 3937:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3938:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return ((READ_BIT(TIMx->SR, TIM_SR_BIF) == (TIM_SR_BIF)) ? 1UL : 0UL); 3939:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3940:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3941:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3942:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Clear the break 2 interrupt flag (B2IF). 3943:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SR B2IF LL_TIM_ClearFlag_BRK2 3944:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3945:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 3946:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3947:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_ClearFlag_BRK2(TIM_TypeDef *TIMx) 3948:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3949:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** WRITE_REG(TIMx->SR, ~(TIM_SR_B2IF)); 3950:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3951:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3952:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3953:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Indicate whether break 2 interrupt flag (B2IF) is set (break 2 interrupt is pending). 3954:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SR B2IF LL_TIM_IsActiveFlag_BRK2 3955:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3956:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval State of bit (1 or 0). 3957:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3958:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK2(const TIM_TypeDef *TIMx) 3959:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3960:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return ((READ_BIT(TIMx->SR, TIM_SR_B2IF) == (TIM_SR_B2IF)) ? 1UL : 0UL); 3961:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3962:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3963:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3964:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Clear the Capture/Compare 1 over-capture interrupt flag (CC1OF). 3965:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SR CC1OF LL_TIM_ClearFlag_CC1OVR 3966:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3967:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 3968:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3969:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_ClearFlag_CC1OVR(TIM_TypeDef *TIMx) 3970:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3971:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** WRITE_REG(TIMx->SR, ~(TIM_SR_CC1OF)); 3972:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3973:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3974:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3975:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Indicate whether Capture/Compare 1 over-capture interrupt flag (CC1OF) is set ARM GAS /tmp/ccLSPxIe.s page 382 3976:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * (Capture/Compare 1 interrupt is pending). 3977:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SR CC1OF LL_TIM_IsActiveFlag_CC1OVR 3978:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3979:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval State of bit (1 or 0). 3980:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3981:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1OVR(const TIM_TypeDef *TIMx) 3982:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3983:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return ((READ_BIT(TIMx->SR, TIM_SR_CC1OF) == (TIM_SR_CC1OF)) ? 1UL : 0UL); 3984:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3985:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3986:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3987:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Clear the Capture/Compare 2 over-capture interrupt flag (CC2OF). 3988:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SR CC2OF LL_TIM_ClearFlag_CC2OVR 3989:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 3990:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 3991:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 3992:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_ClearFlag_CC2OVR(TIM_TypeDef *TIMx) 3993:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 3994:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** WRITE_REG(TIMx->SR, ~(TIM_SR_CC2OF)); 3995:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 3996:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3997:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 3998:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Indicate whether Capture/Compare 2 over-capture interrupt flag (CC2OF) is set 3999:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * (Capture/Compare 2 over-capture interrupt is pending). 4000:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SR CC2OF LL_TIM_IsActiveFlag_CC2OVR 4001:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 4002:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval State of bit (1 or 0). 4003:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 4004:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2OVR(const TIM_TypeDef *TIMx) 4005:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 4006:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return ((READ_BIT(TIMx->SR, TIM_SR_CC2OF) == (TIM_SR_CC2OF)) ? 1UL : 0UL); 4007:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 4008:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 4009:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 4010:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Clear the Capture/Compare 3 over-capture interrupt flag (CC3OF). 4011:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SR CC3OF LL_TIM_ClearFlag_CC3OVR 4012:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 4013:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 4014:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 4015:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_ClearFlag_CC3OVR(TIM_TypeDef *TIMx) 4016:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 4017:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** WRITE_REG(TIMx->SR, ~(TIM_SR_CC3OF)); 4018:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 4019:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 4020:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 4021:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Indicate whether Capture/Compare 3 over-capture interrupt flag (CC3OF) is set 4022:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * (Capture/Compare 3 over-capture interrupt is pending). 4023:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SR CC3OF LL_TIM_IsActiveFlag_CC3OVR 4024:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 4025:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval State of bit (1 or 0). 4026:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 4027:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3OVR(const TIM_TypeDef *TIMx) 4028:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 4029:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return ((READ_BIT(TIMx->SR, TIM_SR_CC3OF) == (TIM_SR_CC3OF)) ? 1UL : 0UL); 4030:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 4031:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 4032:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** ARM GAS /tmp/ccLSPxIe.s page 383 4033:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Clear the Capture/Compare 4 over-capture interrupt flag (CC4OF). 4034:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SR CC4OF LL_TIM_ClearFlag_CC4OVR 4035:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 4036:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 4037:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 4038:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_ClearFlag_CC4OVR(TIM_TypeDef *TIMx) 4039:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 4040:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** WRITE_REG(TIMx->SR, ~(TIM_SR_CC4OF)); 4041:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 4042:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 4043:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 4044:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Indicate whether Capture/Compare 4 over-capture interrupt flag (CC4OF) is set 4045:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * (Capture/Compare 4 over-capture interrupt is pending). 4046:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SR CC4OF LL_TIM_IsActiveFlag_CC4OVR 4047:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 4048:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval State of bit (1 or 0). 4049:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 4050:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4OVR(const TIM_TypeDef *TIMx) 4051:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 4052:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return ((READ_BIT(TIMx->SR, TIM_SR_CC4OF) == (TIM_SR_CC4OF)) ? 1UL : 0UL); 4053:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 4054:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 4055:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 4056:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Clear the system break interrupt flag (SBIF). 4057:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SR SBIF LL_TIM_ClearFlag_SYSBRK 4058:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 4059:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 4060:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 4061:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_ClearFlag_SYSBRK(TIM_TypeDef *TIMx) 4062:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 4063:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** WRITE_REG(TIMx->SR, ~(TIM_SR_SBIF)); 4064:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 4065:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 4066:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 4067:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Indicate whether system break interrupt flag (SBIF) is set (system break interrupt is p 4068:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SR SBIF LL_TIM_IsActiveFlag_SYSBRK 4069:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 4070:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval State of bit (1 or 0). 4071:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 4072:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_SYSBRK(const TIM_TypeDef *TIMx) 4073:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 4074:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return ((READ_BIT(TIMx->SR, TIM_SR_SBIF) == (TIM_SR_SBIF)) ? 1UL : 0UL); 4075:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 4076:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 4077:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 4078:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} 4079:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 4080:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 4081:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EF_IT_Management IT-Management 4082:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ 4083:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ 4084:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** 4085:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Enable update interrupt (UIE). 4086:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll DIER UIE LL_TIM_EnableIT_UPDATE 4087:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance 4088:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None 4089:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ ARM GAS /tmp/ccLSPxIe.s page 384 4090:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_EnableIT_UPDATE(TIM_TypeDef *TIMx) 6985 .loc 5 4090 22 view .LVU2170 6986 .LBB577: 4091:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 4092:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** SET_BIT(TIMx->DIER, TIM_DIER_UIE); 6987 .loc 5 4092 3 view .LVU2171 6988 00a6 8D4B ldr r3, .L390+72 6989 00a8 DA68 ldr r2, [r3, #12] 6990 00aa 42F00102 orr r2, r2, #1 6991 00ae DA60 str r2, [r3, #12] 6992 .LVL630: 6993 .loc 5 4092 3 is_stmt 0 view .LVU2172 6994 .LBE577: 6995 .LBE576: 2395:Src/main.c **** LL_TIM_EnableIT_UPDATE(TIM7); 6996 .loc 1 2395 2 is_stmt 1 view .LVU2173 6997 .LBB578: 6998 .LBI578: 1313:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 6999 .loc 5 1313 22 view .LVU2174 7000 .LBB579: 1315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 7001 .loc 5 1315 3 view .LVU2175 7002 00b0 1A68 ldr r2, [r3] 7003 00b2 42F00102 orr r2, r2, #1 7004 00b6 1A60 str r2, [r3] 7005 .LVL631: 1315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 7006 .loc 5 1315 3 is_stmt 0 view .LVU2176 7007 .LBE579: 7008 .LBE578: 2396:Src/main.c **** LL_TIM_EnableCounter(TIM7); 7009 .loc 1 2396 2 is_stmt 1 view .LVU2177 7010 .LBB580: 7011 .LBI580: 4090:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 7012 .loc 5 4090 22 view .LVU2178 7013 .LBB581: 7014 .loc 5 4092 3 view .LVU2179 7015 00b8 03F58063 add r3, r3, #1024 7016 00bc DA68 ldr r2, [r3, #12] 7017 00be 42F00102 orr r2, r2, #1 7018 00c2 DA60 str r2, [r3, #12] 7019 .LVL632: 7020 .loc 5 4092 3 is_stmt 0 view .LVU2180 7021 .LBE581: 7022 .LBE580: 2397:Src/main.c **** //HAL_TIM_Base_Start_IT(&htim6); 7023 .loc 1 2397 2 is_stmt 1 view .LVU2181 7024 .LBB582: 7025 .LBI582: 1313:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { 7026 .loc 5 1313 22 view .LVU2182 7027 .LBB583: 1315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 7028 .loc 5 1315 3 view .LVU2183 7029 00c4 1A68 ldr r2, [r3] ARM GAS /tmp/ccLSPxIe.s page 385 7030 00c6 42F00102 orr r2, r2, #1 7031 00ca 1A60 str r2, [r3] 7032 .LVL633: 1315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } 7033 .loc 5 1315 3 is_stmt 0 view .LVU2184 7034 .LBE583: 7035 .LBE582: 2404:Src/main.c **** LL_DMA_ClearFlag_TC7(DMA2); 7036 .loc 1 2404 3 is_stmt 1 view .LVU2185 7037 .LBB584: 7038 .LBI584: 7039 .file 6 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h" 1:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 2:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** ****************************************************************************** 3:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @file stm32f7xx_ll_dma.h 4:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @author MCD Application Team 5:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Header file of DMA LL module. 6:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** ****************************************************************************** 7:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @attention 8:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * 9:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * Copyright (c) 2017 STMicroelectronics. 10:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * All rights reserved. 11:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * 12:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * This software is licensed under terms that can be found in the LICENSE file in 13:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * the root directory of this software component. 14:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * If no LICENSE file comes with this software, it is provided AS-IS. 15:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * 16:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** ****************************************************************************** 17:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 18:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 19:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /* Define to prevent recursive inclusion -------------------------------------*/ 20:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #ifndef __STM32F7xx_LL_DMA_H 21:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define __STM32F7xx_LL_DMA_H 22:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 23:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #ifdef __cplusplus 24:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** extern "C" { 25:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #endif 26:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 27:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /* Includes ------------------------------------------------------------------*/ 28:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #include "stm32f7xx.h" 29:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 30:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @addtogroup STM32F7xx_LL_Driver 31:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @{ 32:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 33:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 34:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #if defined (DMA1) || defined (DMA2) 35:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 36:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL DMA 37:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @{ 38:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 39:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 40:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /* Private types -------------------------------------------------------------*/ 41:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /* Private variables ---------------------------------------------------------*/ 42:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_Private_Variables DMA Private Variables 43:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @{ 44:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 45:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /* Array used to get the DMA stream register offset versus stream index LL_DMA_STREAM_x */ ARM GAS /tmp/ccLSPxIe.s page 386 46:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** static const uint8_t STREAM_OFFSET_TAB[] = 47:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 48:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** (uint8_t)(DMA1_Stream0_BASE - DMA1_BASE), 49:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** (uint8_t)(DMA1_Stream1_BASE - DMA1_BASE), 50:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** (uint8_t)(DMA1_Stream2_BASE - DMA1_BASE), 51:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** (uint8_t)(DMA1_Stream3_BASE - DMA1_BASE), 52:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** (uint8_t)(DMA1_Stream4_BASE - DMA1_BASE), 53:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** (uint8_t)(DMA1_Stream5_BASE - DMA1_BASE), 54:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** (uint8_t)(DMA1_Stream6_BASE - DMA1_BASE), 55:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** (uint8_t)(DMA1_Stream7_BASE - DMA1_BASE) 56:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }; 57:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 58:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 59:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @} 60:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 61:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 62:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /* Private constants ---------------------------------------------------------*/ 63:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_Private_Constants DMA Private Constants 64:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @{ 65:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 66:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #if defined(DMA_SxCR_CHSEL_3) 67:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define DMA_CHANNEL_SELECTION_8_15 68:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #endif /* DMA_SxCR_CHSEL_3 */ 69:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 70:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @} 71:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 72:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 73:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 74:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /* Private macros ------------------------------------------------------------*/ 75:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /* Exported types ------------------------------------------------------------*/ 76:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #if defined(USE_FULL_LL_DRIVER) 77:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_ES_INIT DMA Exported Init structure 78:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @{ 79:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 80:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** typedef struct 81:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 82:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** uint32_t PeriphOrM2MSrcAddress; /*!< Specifies the peripheral base address for DMA transfer 83:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** or as Source base address in case of memory to memory trans 84:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 85:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** This parameter must be a value between Min_Data = 0 and Max 86:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 87:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** uint32_t MemoryOrM2MDstAddress; /*!< Specifies the memory base address for DMA transfer 88:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** or as Destination base address in case of memory to memory 89:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 90:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** This parameter must be a value between Min_Data = 0 and Max 91:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 92:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** uint32_t Direction; /*!< Specifies if the data will be transferred from memory to pe 93:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** from memory to memory or from peripheral to memory. 94:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** This parameter can be a value of @ref DMA_LL_EC_DIRECTION 95:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 96:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** This feature can be modified afterwards using unitary funct 97:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 98:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** uint32_t Mode; /*!< Specifies the normal or circular operation mode. 99:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** This parameter can be a value of @ref DMA_LL_EC_MODE 100:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** @note The circular buffer mode cannot be used if the memory 101:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** data transfer direction is configured on the selected 102:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** ARM GAS /tmp/ccLSPxIe.s page 387 103:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** This feature can be modified afterwards using unitary funct 104:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 105:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** uint32_t PeriphOrM2MSrcIncMode; /*!< Specifies whether the Peripheral address or Source address 106:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** is incremented or not. 107:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** This parameter can be a value of @ref DMA_LL_EC_PERIPH 108:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 109:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** This feature can be modified afterwards using unitary funct 110:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 111:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** uint32_t MemoryOrM2MDstIncMode; /*!< Specifies whether the Memory address or Destination address 112:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** is incremented or not. 113:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** This parameter can be a value of @ref DMA_LL_EC_MEMORY 114:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 115:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** This feature can be modified afterwards using unitary funct 116:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 117:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** uint32_t PeriphOrM2MSrcDataSize; /*!< Specifies the Peripheral data size alignment or Source data 118:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** in case of memory to memory transfer direction. 119:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** This parameter can be a value of @ref DMA_LL_EC_PDATAALIGN 120:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 121:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** This feature can be modified afterwards using unitary funct 122:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 123:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** uint32_t MemoryOrM2MDstDataSize; /*!< Specifies the Memory data size alignment or Destination dat 124:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** in case of memory to memory transfer direction. 125:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** This parameter can be a value of @ref DMA_LL_EC_MDATAALIGN 126:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 127:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** This feature can be modified afterwards using unitary funct 128:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 129:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** uint32_t NbData; /*!< Specifies the number of data to transfer, in data unit. 130:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** The data unit is equal to the source buffer configuration s 131:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** or MemorySize parameters depending in the transfer directio 132:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** This parameter must be a value between Min_Data = 0 and Max 133:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 134:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** This feature can be modified afterwards using unitary funct 135:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 136:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** uint32_t Channel; /*!< Specifies the peripheral channel. 137:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** This parameter can be a value of @ref DMA_LL_EC_CHANNEL 138:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 139:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** This feature can be modified afterwards using unitary funct 140:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 141:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** uint32_t Priority; /*!< Specifies the channel priority level. 142:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** This parameter can be a value of @ref DMA_LL_EC_PRIORITY 143:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 144:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** This feature can be modified afterwards using unitary funct 145:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 146:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** uint32_t FIFOMode; /*!< Specifies if the FIFO mode or Direct mode will be used for 147:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** This parameter can be a value of @ref DMA_LL_FIFOMODE 148:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** @note The Direct mode (FIFO mode disabled) cannot be used i 149:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** memory-to-memory data transfer is configured on the selecte 150:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 151:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** This feature can be modified afterwards using unitary funct 152:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 153:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** uint32_t FIFOThreshold; /*!< Specifies the FIFO threshold level. 154:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** This parameter can be a value of @ref DMA_LL_EC_FIFOTHRESHO 155:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 156:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** This feature can be modified afterwards using unitary funct 157:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 158:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** uint32_t MemBurst; /*!< Specifies the Burst transfer configuration for the memory t 159:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** It specifies the amount of data to be transferred in a sing ARM GAS /tmp/ccLSPxIe.s page 388 160:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** transaction. 161:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** This parameter can be a value of @ref DMA_LL_EC_MBURST 162:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** @note The burst mode is possible only if the address Increm 163:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 164:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** This feature can be modified afterwards using unitary funct 165:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 166:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** uint32_t PeriphBurst; /*!< Specifies the Burst transfer configuration for the peripher 167:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** It specifies the amount of data to be transferred in a sing 168:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** transaction. 169:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** This parameter can be a value of @ref DMA_LL_EC_PBURST 170:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** @note The burst mode is possible only if the address Increm 171:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 172:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** This feature can be modified afterwards using unitary funct 173:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 174:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } LL_DMA_InitTypeDef; 175:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 176:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @} 177:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 178:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #endif /*USE_FULL_LL_DRIVER*/ 179:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /* Exported constants --------------------------------------------------------*/ 180:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_Exported_Constants DMA Exported Constants 181:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @{ 182:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 183:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 184:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_EC_STREAM STREAM 185:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @{ 186:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 187:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_STREAM_0 0x00000000U 188:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_STREAM_1 0x00000001U 189:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_STREAM_2 0x00000002U 190:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_STREAM_3 0x00000003U 191:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_STREAM_4 0x00000004U 192:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_STREAM_5 0x00000005U 193:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_STREAM_6 0x00000006U 194:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_STREAM_7 0x00000007U 195:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_STREAM_ALL 0xFFFF0000U 196:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 197:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @} 198:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 199:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 200:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_EC_DIRECTION DIRECTION 201:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @{ 202:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 203:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_DIRECTION_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direc 204:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_DIRECTION_MEMORY_TO_PERIPH DMA_SxCR_DIR_0 /*!< Memory to peripheral direc 205:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_DIRECTION_MEMORY_TO_MEMORY DMA_SxCR_DIR_1 /*!< Memory to memory direction 206:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 207:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @} 208:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 209:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 210:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_EC_MODE MODE 211:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @{ 212:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 213:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_MODE_NORMAL 0x00000000U /*!< Normal Mode 214:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_MODE_CIRCULAR DMA_SxCR_CIRC /*!< Circular Mode 215:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_MODE_PFCTRL DMA_SxCR_PFCTRL /*!< Peripheral flow control mo 216:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** ARM GAS /tmp/ccLSPxIe.s page 389 217:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @} 218:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 219:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 220:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_EC_DOUBLEBUFFER_MODE DOUBLE BUFFER MODE 221:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @{ 222:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 223:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_DOUBLEBUFFER_MODE_DISABLE 0x00000000U /*!< Disable double buffering m 224:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_DOUBLEBUFFER_MODE_ENABLE DMA_SxCR_DBM /*!< Enable double buffering mo 225:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 226:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @} 227:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 228:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 229:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_EC_PERIPH PERIPH 230:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @{ 231:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 232:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_PERIPH_NOINCREMENT 0x00000000U /*!< Peripheral increment mode 233:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_PERIPH_INCREMENT DMA_SxCR_PINC /*!< Peripheral increment mode 234:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 235:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @} 236:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 237:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 238:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_EC_MEMORY MEMORY 239:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @{ 240:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 241:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_MEMORY_NOINCREMENT 0x00000000U /*!< Memory increment mode Disa 242:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_MEMORY_INCREMENT DMA_SxCR_MINC /*!< Memory increment mode Enab 243:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 244:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @} 245:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 246:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 247:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_EC_PDATAALIGN PDATAALIGN 248:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @{ 249:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 250:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_PDATAALIGN_BYTE 0x00000000U /*!< Peripheral data alignment 251:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_PDATAALIGN_HALFWORD DMA_SxCR_PSIZE_0 /*!< Peripheral data alignment 252:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_PDATAALIGN_WORD DMA_SxCR_PSIZE_1 /*!< Peripheral data alignment 253:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 254:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @} 255:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 256:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 257:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_EC_MDATAALIGN MDATAALIGN 258:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @{ 259:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 260:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_MDATAALIGN_BYTE 0x00000000U /*!< Memory data alignment : By 261:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_MDATAALIGN_HALFWORD DMA_SxCR_MSIZE_0 /*!< Memory data alignment : Ha 262:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_MDATAALIGN_WORD DMA_SxCR_MSIZE_1 /*!< Memory data alignment : Wo 263:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 264:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @} 265:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 266:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 267:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_EC_OFFSETSIZE OFFSETSIZE 268:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @{ 269:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 270:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_OFFSETSIZE_PSIZE 0x00000000U /*!< Peripheral increment offse 271:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_OFFSETSIZE_FIXEDTO4 DMA_SxCR_PINCOS /*!< Peripheral increment offse 272:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 273:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @} ARM GAS /tmp/ccLSPxIe.s page 390 274:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 275:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 276:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_EC_PRIORITY PRIORITY 277:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @{ 278:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 279:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_PRIORITY_LOW 0x00000000U /*!< Priority level : Low 280:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_PRIORITY_MEDIUM DMA_SxCR_PL_0 /*!< Priority level : Medium 281:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_PRIORITY_HIGH DMA_SxCR_PL_1 /*!< Priority level : High 282:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_PRIORITY_VERYHIGH DMA_SxCR_PL /*!< Priority level : Very_High 283:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 284:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @} 285:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 286:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 287:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_EC_CHANNEL CHANNEL 288:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @{ 289:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 290:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_CHANNEL_0 0x00000000U 291:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_CHANNEL_1 DMA_SxCR_CHSEL_0 292:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_CHANNEL_2 DMA_SxCR_CHSEL_1 293:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_CHANNEL_3 (DMA_SxCR_CHSEL_0 | DMA_SxCR_CHSEL_1) 294:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_CHANNEL_4 DMA_SxCR_CHSEL_2 295:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_CHANNEL_5 (DMA_SxCR_CHSEL_2 | DMA_SxCR_CHSEL_0) 296:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_CHANNEL_6 (DMA_SxCR_CHSEL_2 | DMA_SxCR_CHSEL_1) 297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_CHANNEL_7 (DMA_SxCR_CHSEL_2 | DMA_SxCR_CHSEL_1 | DMA_SxCR_CHSEL_0) 298:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #if defined(DMA_CHANNEL_SELECTION_8_15) 299:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_CHANNEL_8 DMA_SxCR_CHSEL_3 300:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_CHANNEL_9 (DMA_SxCR_CHSEL_3 | DMA_SxCR_CHSEL_0) 301:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_CHANNEL_10 (DMA_SxCR_CHSEL_3 | DMA_SxCR_CHSEL_1) 302:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_CHANNEL_11 (DMA_SxCR_CHSEL_3 | DMA_SxCR_CHSEL_1 | DMA_SxCR_CHSEL_0) 303:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_CHANNEL_12 (DMA_SxCR_CHSEL_3 | DMA_SxCR_CHSEL_2) 304:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_CHANNEL_13 (DMA_SxCR_CHSEL_3 | DMA_SxCR_CHSEL_2 | DMA_SxCR_CHSEL_0) 305:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_CHANNEL_14 (DMA_SxCR_CHSEL_3 | DMA_SxCR_CHSEL_2 | DMA_SxCR_CHSEL_1) 306:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_CHANNEL_15 DMA_SxCR_CHSEL 307:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #endif /* DMA_CHANNEL_SELECTION_8_15 */ 308:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 309:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @} 310:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 311:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 312:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_EC_MBURST MBURST 313:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @{ 314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_MBURST_SINGLE 0x00000000U /*!< Memory burst 316:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_MBURST_INC4 DMA_SxCR_MBURST_0 /*!< Memory burst 317:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_MBURST_INC8 DMA_SxCR_MBURST_1 /*!< Memory burst 318:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_MBURST_INC16 (DMA_SxCR_MBURST_0 | DMA_SxCR_MBURST_1) /*!< Memory burst 319:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 320:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @} 321:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 322:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 323:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_EC_PBURST PBURST 324:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @{ 325:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 326:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_PBURST_SINGLE 0x00000000U /*!< Peripheral b 327:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_PBURST_INC4 DMA_SxCR_PBURST_0 /*!< Peripheral b 328:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_PBURST_INC8 DMA_SxCR_PBURST_1 /*!< Peripheral b 329:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_PBURST_INC16 (DMA_SxCR_PBURST_0 | DMA_SxCR_PBURST_1) /*!< Peripheral b 330:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** ARM GAS /tmp/ccLSPxIe.s page 391 331:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @} 332:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 333:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 334:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_FIFOMODE DMA_LL_FIFOMODE 335:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @{ 336:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 337:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_FIFOMODE_DISABLE 0x00000000U /*!< FIFO mode di 338:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_FIFOMODE_ENABLE DMA_SxFCR_DMDIS /*!< FIFO mode en 339:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 340:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @} 341:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 342:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 343:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_EC_FIFOSTATUS_0 FIFOSTATUS 0 344:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @{ 345:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_FIFOSTATUS_0_25 0x00000000U /*!< 0 < fifo_lev 347:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_FIFOSTATUS_25_50 DMA_SxFCR_FS_0 /*!< 1/4 < fifo_l 348:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_FIFOSTATUS_50_75 DMA_SxFCR_FS_1 /*!< 1/2 < fifo_l 349:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_FIFOSTATUS_75_100 (DMA_SxFCR_FS_1 | DMA_SxFCR_FS_0) /*!< 3/4 < fifo_l 350:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_FIFOSTATUS_EMPTY DMA_SxFCR_FS_2 /*!< FIFO is empt 351:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_FIFOSTATUS_FULL (DMA_SxFCR_FS_2 | DMA_SxFCR_FS_0) /*!< FIFO is full 352:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 353:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @} 354:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 355:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 356:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_EC_FIFOTHRESHOLD FIFOTHRESHOLD 357:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @{ 358:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 359:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_FIFOTHRESHOLD_1_4 0x00000000U /*!< FIFO thresho 360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_FIFOTHRESHOLD_1_2 DMA_SxFCR_FTH_0 /*!< FIFO thresho 361:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_FIFOTHRESHOLD_3_4 DMA_SxFCR_FTH_1 /*!< FIFO thresho 362:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_FIFOTHRESHOLD_FULL DMA_SxFCR_FTH /*!< FIFO thresho 363:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 364:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @} 365:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 366:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 367:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_EC_CURRENTTARGETMEM CURRENTTARGETMEM 368:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @{ 369:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_CURRENTTARGETMEM0 0x00000000U /*!< Set CurrentT 371:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_CURRENTTARGETMEM1 DMA_SxCR_CT /*!< Set CurrentT 372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @} 374:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 375:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 376:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 377:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @} 378:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 379:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 380:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /* Exported macro ------------------------------------------------------------*/ 381:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_Exported_Macros DMA Exported Macros 382:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @{ 383:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 384:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 385:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_EM_WRITE_READ Common Write and read registers macros 386:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @{ 387:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ ARM GAS /tmp/ccLSPxIe.s page 392 388:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 389:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Write a value in DMA register 390:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param __INSTANCE__ DMA Instance 391:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param __REG__ Register to be written 392:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param __VALUE__ Value to be written in the register 393:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 394:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 395:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE 396:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 397:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 398:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Read a value in DMA register 399:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param __INSTANCE__ DMA Instance 400:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param __REG__ Register to be read 401:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval Register value 402:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 403:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) 404:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 405:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @} 406:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 407:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 408:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_EM_CONVERT_DMAxCHANNELy Convert DMAxStreamy 409:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @{ 410:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 411:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 412:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Convert DMAx_Streamy into DMAx 413:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param __STREAM_INSTANCE__ DMAx_Streamy 414:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval DMAx 415:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 416:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define __LL_DMA_GET_INSTANCE(__STREAM_INSTANCE__) \ 417:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** (((uint32_t)(__STREAM_INSTANCE__) > ((uint32_t)DMA1_Stream7)) ? DMA2 : DMA1) 418:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 419:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 420:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Convert DMAx_Streamy into LL_DMA_STREAM_y 421:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param __STREAM_INSTANCE__ DMAx_Streamy 422:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval LL_DMA_CHANNEL_y 423:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 424:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define __LL_DMA_GET_STREAM(__STREAM_INSTANCE__) \ 425:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** (((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream0)) ? LL_DMA_STREAM_0 : \ 426:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream0)) ? LL_DMA_STREAM_0 : \ 427:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream1)) ? LL_DMA_STREAM_1 : \ 428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream1)) ? LL_DMA_STREAM_1 : \ 429:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream2)) ? LL_DMA_STREAM_2 : \ 430:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream2)) ? LL_DMA_STREAM_2 : \ 431:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream3)) ? LL_DMA_STREAM_3 : \ 432:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream3)) ? LL_DMA_STREAM_3 : \ 433:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream4)) ? LL_DMA_STREAM_4 : \ 434:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream4)) ? LL_DMA_STREAM_4 : \ 435:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream5)) ? LL_DMA_STREAM_5 : \ 436:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream5)) ? LL_DMA_STREAM_5 : \ 437:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream6)) ? LL_DMA_STREAM_6 : \ 438:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream6)) ? LL_DMA_STREAM_6 : \ 439:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** LL_DMA_STREAM_7) 440:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 441:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 442:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Convert DMA Instance DMAx and LL_DMA_STREAM_y into DMAx_Streamy 443:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param __DMA_INSTANCE__ DMAx 444:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param __STREAM__ LL_DMA_STREAM_y ARM GAS /tmp/ccLSPxIe.s page 393 445:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval DMAx_Streamy 446:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 447:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define __LL_DMA_GET_STREAM_INSTANCE(__DMA_INSTANCE__, __STREAM__) \ 448:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** ((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DM 449:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DM 450:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DM 451:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DM 452:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DM 453:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DM 454:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DM 455:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DM 456:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DM 457:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DM 458:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DM 459:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DM 460:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DM 461:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DM 462:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DM 463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** DMA2_Stream7) 464:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 465:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 466:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @} 467:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 468:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 469:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 470:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @} 471:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 472:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 473:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 474:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /* Exported functions --------------------------------------------------------*/ 475:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_Exported_Functions DMA Exported Functions 476:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @{ 477:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 478:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 479:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_EF_Configuration Configuration 480:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @{ 481:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 482:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 483:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Enable DMA stream. 484:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR EN LL_DMA_EnableStream 485:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 486:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: 487:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 488:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 489:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 490:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 491:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 492:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 493:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 494:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 495:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 496:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 497:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_EnableStream(DMA_TypeDef *DMAx, uint32_t Stream) 498:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 499:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA 500:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 501:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** ARM GAS /tmp/ccLSPxIe.s page 394 502:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 503:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Disable DMA stream. 504:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR EN LL_DMA_DisableStream 505:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 506:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: 507:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 508:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 509:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 510:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 511:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 512:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 513:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 514:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 515:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 516:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 517:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_DisableStream(DMA_TypeDef *DMAx, uint32_t Stream) 7040 .loc 6 517 22 view .LVU2186 7041 .LBB585: 518:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 519:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, D 7042 .loc 6 519 3 view .LVU2187 7043 00cc 03F51433 add r3, r3, #151552 7044 00d0 D3F8B820 ldr r2, [r3, #184] 7045 00d4 22F00102 bic r2, r2, #1 7046 00d8 C3F8B820 str r2, [r3, #184] 7047 .LVL634: 7048 .loc 6 519 3 is_stmt 0 view .LVU2188 7049 .LBE585: 7050 .LBE584: 2405:Src/main.c **** LL_DMA_ClearFlag_TE7(DMA2); 7051 .loc 1 2405 3 is_stmt 1 view .LVU2189 7052 .LBB586: 7053 .LBI586: 520:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 521:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 522:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 523:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Check if DMA stream is enabled or disabled. 524:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR EN LL_DMA_IsEnabledStream 525:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 526:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: 527:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 528:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 529:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 530:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 531:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 532:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 533:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 534:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 535:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). 536:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 537:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsEnabledStream(DMA_TypeDef *DMAx, uint32_t Stream) 538:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 539:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))- 540:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 541:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 542:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 543:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Configure all parameters linked to DMA transfer. ARM GAS /tmp/ccLSPxIe.s page 395 544:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR DIR LL_DMA_ConfigTransfer\n 545:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * CR CIRC LL_DMA_ConfigTransfer\n 546:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * CR PINC LL_DMA_ConfigTransfer\n 547:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * CR MINC LL_DMA_ConfigTransfer\n 548:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * CR PSIZE LL_DMA_ConfigTransfer\n 549:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * CR MSIZE LL_DMA_ConfigTransfer\n 550:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * CR PL LL_DMA_ConfigTransfer\n 551:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * CR PFCTRL LL_DMA_ConfigTransfer 552:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 553:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: 554:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 555:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 556:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 557:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 558:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 559:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 560:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 561:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 562:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Configuration This parameter must be a combination of all the following values: 563:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY or @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH o 564:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_MODE_NORMAL or @ref LL_DMA_MODE_CIRCULAR or @ref LL_DMA_MODE_PFCTRL 565:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_PERIPH_INCREMENT or @ref LL_DMA_PERIPH_NOINCREMENT 566:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_MEMORY_INCREMENT or @ref LL_DMA_MEMORY_NOINCREMENT 567:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_PDATAALIGN_BYTE or @ref LL_DMA_PDATAALIGN_HALFWORD or @ref LL_DMA_PDAT 568:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_MDATAALIGN_BYTE or @ref LL_DMA_MDATAALIGN_HALFWORD or @ref LL_DMA_MDAT 569:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_PRIORITY_LOW or @ref LL_DMA_PRIORITY_MEDIUM or @ref LL_DMA_PRIORITY_HI 570:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** *@retval None 571:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 572:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ConfigTransfer(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Configurati 573:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 574:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** MODIFY_REG(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, 575:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** DMA_SxCR_DIR | DMA_SxCR_CIRC | DMA_SxCR_PINC | DMA_SxCR_MINC | DMA_SxCR_PSIZE | DMA_Sx 576:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** Configuration); 577:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 578:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 579:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 580:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Set Data transfer direction (read from peripheral or from memory). 581:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR DIR LL_DMA_SetDataTransferDirection 582:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 583:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: 584:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 585:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 586:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 587:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 588:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 589:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 590:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 591:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 592:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Direction This parameter can be one of the following values: 593:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY 594:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH 595:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY 596:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 597:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 598:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_SetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t 599:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 600:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, D ARM GAS /tmp/ccLSPxIe.s page 396 601:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 602:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 603:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 604:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Data transfer direction (read from peripheral or from memory). 605:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR DIR LL_DMA_GetDataTransferDirection 606:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 607:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: 608:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 609:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 610:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 611:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 612:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 613:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 614:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 615:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 616:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval Returned value can be one of the following values: 617:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY 618:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH 619:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY 620:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 621:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Stream) 622:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 623:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))- 624:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 625:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 626:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 627:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Set DMA mode normal, circular or peripheral flow control. 628:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR CIRC LL_DMA_SetMode\n 629:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * CR PFCTRL LL_DMA_SetMode 630:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 631:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: 632:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 633:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 634:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 635:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 636:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 637:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 638:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 639:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 640:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Mode This parameter can be one of the following values: 641:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_MODE_NORMAL 642:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_MODE_CIRCULAR 643:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_MODE_PFCTRL 644:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 645:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 646:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_SetMode(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Mode) 647:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 648:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, D 649:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 650:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 651:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 652:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get DMA mode normal, circular or peripheral flow control. 653:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR CIRC LL_DMA_GetMode\n 654:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * CR PFCTRL LL_DMA_GetMode 655:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 656:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: 657:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 ARM GAS /tmp/ccLSPxIe.s page 397 658:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 659:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 660:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 661:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 662:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 663:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 664:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 665:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval Returned value can be one of the following values: 666:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_MODE_NORMAL 667:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_MODE_CIRCULAR 668:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_MODE_PFCTRL 669:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 670:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_GetMode(DMA_TypeDef *DMAx, uint32_t Stream) 671:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 672:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))- 673:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 674:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 675:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 676:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Set Peripheral increment mode. 677:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR PINC LL_DMA_SetPeriphIncMode 678:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 679:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: 680:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 681:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 682:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 683:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 684:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 685:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 686:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 687:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 688:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param IncrementMode This parameter can be one of the following values: 689:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_PERIPH_NOINCREMENT 690:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_PERIPH_INCREMENT 691:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 692:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 693:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_SetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Increment 694:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 695:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, D 696:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 697:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 698:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 699:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Peripheral increment mode. 700:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR PINC LL_DMA_GetPeriphIncMode 701:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 702:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: 703:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 704:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 705:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 706:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 707:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 708:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 709:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 710:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 711:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval Returned value can be one of the following values: 712:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_PERIPH_NOINCREMENT 713:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_PERIPH_INCREMENT 714:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ ARM GAS /tmp/ccLSPxIe.s page 398 715:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_GetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Stream) 716:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 717:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))- 718:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 719:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 720:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 721:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Set Memory increment mode. 722:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR MINC LL_DMA_SetMemoryIncMode 723:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 724:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: 725:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 726:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 727:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 728:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 729:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 730:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 731:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 732:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 733:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param IncrementMode This parameter can be one of the following values: 734:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_MEMORY_NOINCREMENT 735:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_MEMORY_INCREMENT 736:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 737:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 738:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_SetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Increment 739:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 740:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, D 741:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 742:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 743:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 744:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Memory increment mode. 745:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR MINC LL_DMA_GetMemoryIncMode 746:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 747:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: 748:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 749:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 750:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 751:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 752:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 753:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 754:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 755:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 756:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval Returned value can be one of the following values: 757:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_MEMORY_NOINCREMENT 758:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_MEMORY_INCREMENT 759:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 760:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Stream) 761:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 762:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))- 763:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 764:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 765:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 766:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Set Peripheral size. 767:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR PSIZE LL_DMA_SetPeriphSize 768:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 769:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: 770:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 771:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 ARM GAS /tmp/ccLSPxIe.s page 399 772:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 773:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 774:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 775:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 776:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 777:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 778:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Size This parameter can be one of the following values: 779:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_PDATAALIGN_BYTE 780:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_PDATAALIGN_HALFWORD 781:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_PDATAALIGN_WORD 782:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 783:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 784:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_SetPeriphSize(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Size) 785:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 786:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, D 787:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 788:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 789:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 790:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Peripheral size. 791:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR PSIZE LL_DMA_GetPeriphSize 792:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 793:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: 794:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 795:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 796:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 797:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 798:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 799:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 800:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 801:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 802:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval Returned value can be one of the following values: 803:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_PDATAALIGN_BYTE 804:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_PDATAALIGN_HALFWORD 805:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_PDATAALIGN_WORD 806:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 807:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_GetPeriphSize(DMA_TypeDef *DMAx, uint32_t Stream) 808:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 809:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))- 810:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 811:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 812:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 813:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Set Memory size. 814:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR MSIZE LL_DMA_SetMemorySize 815:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 816:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: 817:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 818:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 819:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 820:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 821:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 822:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 823:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 824:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 825:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Size This parameter can be one of the following values: 826:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_MDATAALIGN_BYTE 827:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_MDATAALIGN_HALFWORD 828:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_MDATAALIGN_WORD ARM GAS /tmp/ccLSPxIe.s page 400 829:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 830:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 831:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_SetMemorySize(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Size) 832:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 833:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, D 834:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 835:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 836:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 837:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Memory size. 838:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR MSIZE LL_DMA_GetMemorySize 839:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 840:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: 841:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 842:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 843:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 844:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 845:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 846:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 847:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 848:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 849:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval Returned value can be one of the following values: 850:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_MDATAALIGN_BYTE 851:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_MDATAALIGN_HALFWORD 852:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_MDATAALIGN_WORD 853:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 854:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_GetMemorySize(DMA_TypeDef *DMAx, uint32_t Stream) 855:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 856:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))- 857:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 858:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 859:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 860:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Set Peripheral increment offset size. 861:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR PINCOS LL_DMA_SetIncOffsetSize 862:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 863:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: 864:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 865:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 866:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 867:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 868:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 869:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 870:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 871:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 872:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param OffsetSize This parameter can be one of the following values: 873:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_OFFSETSIZE_PSIZE 874:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_OFFSETSIZE_FIXEDTO4 875:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 876:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 877:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_SetIncOffsetSize(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t OffsetSiz 878:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 879:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, D 880:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 881:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 882:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 883:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Peripheral increment offset size. 884:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR PINCOS LL_DMA_GetIncOffsetSize 885:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance ARM GAS /tmp/ccLSPxIe.s page 401 886:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: 887:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 888:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 889:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 890:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 891:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 892:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 893:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 894:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 895:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval Returned value can be one of the following values: 896:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_OFFSETSIZE_PSIZE 897:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_OFFSETSIZE_FIXEDTO4 898:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 899:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_GetIncOffsetSize(DMA_TypeDef *DMAx, uint32_t Stream) 900:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 901:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))- 902:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 903:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 904:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 905:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Set Stream priority level. 906:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR PL LL_DMA_SetStreamPriorityLevel 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 908:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: 909:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 910:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 911:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 912:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 913:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 914:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 915:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 916:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 917:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Priority This parameter can be one of the following values: 918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_PRIORITY_LOW 919:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_PRIORITY_MEDIUM 920:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_PRIORITY_HIGH 921:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_PRIORITY_VERYHIGH 922:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 923:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 924:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_SetStreamPriorityLevel(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Pr 925:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 926:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, D 927:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 928:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 929:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 930:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream priority level. 931:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR PL LL_DMA_GetStreamPriorityLevel 932:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 933:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: 934:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 935:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 936:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 937:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 938:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 939:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 940:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 941:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 942:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval Returned value can be one of the following values: ARM GAS /tmp/ccLSPxIe.s page 402 943:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_PRIORITY_LOW 944:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_PRIORITY_MEDIUM 945:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_PRIORITY_HIGH 946:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_PRIORITY_VERYHIGH 947:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 948:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_GetStreamPriorityLevel(DMA_TypeDef *DMAx, uint32_t Stream) 949:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 950:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))- 951:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 952:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 953:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 954:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Set Number of data to transfer. 955:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll NDTR NDT LL_DMA_SetDataLength 956:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @note This action has no effect if 957:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * stream is enabled. 958:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 959:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: 960:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 961:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 962:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 963:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 964:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 965:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 966:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 967:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 968:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param NbData Between 0 to 0xFFFFFFFF 969:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 970:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 971:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_SetDataLength(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t NbData) 972:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 973:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->NDTR, 974:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 975:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 976:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 977:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Number of data to transfer. 978:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll NDTR NDT LL_DMA_GetDataLength 979:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @note Once the stream is enabled, the return value indicate the 980:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * remaining bytes to be transmitted. 981:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 982:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: 983:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 984:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 985:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 986:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 987:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 988:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 989:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 990:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 991:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval Between 0 to 0xFFFFFFFF 992:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 993:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_GetDataLength(DMA_TypeDef* DMAx, uint32_t Stream) 994:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 995:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))- 996:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 997:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 998:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 999:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Select Channel number associated to the Stream. ARM GAS /tmp/ccLSPxIe.s page 403 1000:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR CHSEL LL_DMA_SetChannelSelection 1001:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 1002:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: 1003:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 1004:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 1005:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 1006:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 1007:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 1008:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 1009:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 1010:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 1011:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Channel This parameter can be one of the following values: 1012:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_0 1013:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_1 1014:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_2 1015:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_3 1016:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_4 1017:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_5 1018:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_6 1019:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_7 1020:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_8 (*) 1021:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_9 (*) 1022:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_10 (*) 1023:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_11 (*) 1024:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_12 (*) 1025:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_13 (*) 1026:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_14 (*) 1027:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_15 (*) 1028:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * 1029:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * (*) value not defined in all devices. 1030:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 1031:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1032:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_SetChannelSelection(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Channe 1033:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1034:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, D 1035:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1036:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1037:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1038:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get the Channel number associated to the Stream. 1039:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR CHSEL LL_DMA_GetChannelSelection 1040:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 1041:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: 1042:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 1043:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 1044:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 1045:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 1046:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 1047:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 1048:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 1049:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 1050:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval Returned value can be one of the following values: 1051:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_0 1052:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_1 1053:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_2 1054:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_3 1055:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_4 1056:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_5 ARM GAS /tmp/ccLSPxIe.s page 404 1057:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_6 1058:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_7 1059:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_8 (*) 1060:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_9 (*) 1061:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_10 (*) 1062:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_11 (*) 1063:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_12 (*) 1064:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_13 (*) 1065:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_14 (*) 1066:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_15 (*) 1067:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * 1068:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * (*) value not defined in all devices. 1069:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1070:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_GetChannelSelection(DMA_TypeDef *DMAx, uint32_t Stream) 1071:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1072:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))- 1073:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1074:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1075:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1076:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Set Memory burst transfer configuration. 1077:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR MBURST LL_DMA_SetMemoryBurstxfer 1078:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 1079:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: 1080:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 1081:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 1082:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 1083:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 1084:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 1085:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 1086:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 1087:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 1088:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Mburst This parameter can be one of the following values: 1089:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_MBURST_SINGLE 1090:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_MBURST_INC4 1091:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_MBURST_INC8 1092:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_MBURST_INC16 1093:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 1094:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1095:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_SetMemoryBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Mburst) 1096:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1097:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, D 1098:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1099:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1100:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1101:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Memory burst transfer configuration. 1102:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR MBURST LL_DMA_GetMemoryBurstxfer 1103:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 1104:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: 1105:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 1106:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 1107:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 1108:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 1109:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 1110:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 1111:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 1112:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 1113:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval Returned value can be one of the following values: ARM GAS /tmp/ccLSPxIe.s page 405 1114:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_MBURST_SINGLE 1115:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_MBURST_INC4 1116:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_MBURST_INC8 1117:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_MBURST_INC16 1118:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1119:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_GetMemoryBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream) 1120:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1121:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))- 1122:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1123:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1124:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1125:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Set Peripheral burst transfer configuration. 1126:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR PBURST LL_DMA_SetPeriphBurstxfer 1127:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 1128:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: 1129:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 1130:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 1131:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 1132:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 1133:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 1134:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 1135:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 1136:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 1137:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Pburst This parameter can be one of the following values: 1138:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_PBURST_SINGLE 1139:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_PBURST_INC4 1140:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_PBURST_INC8 1141:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_PBURST_INC16 1142:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 1143:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1144:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_SetPeriphBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Pburst) 1145:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1146:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, D 1147:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1148:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1149:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1150:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Peripheral burst transfer configuration. 1151:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR PBURST LL_DMA_GetPeriphBurstxfer 1152:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 1153:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: 1154:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 1155:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 1156:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 1157:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 1158:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 1159:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 1160:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 1161:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 1162:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval Returned value can be one of the following values: 1163:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_PBURST_SINGLE 1164:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_PBURST_INC4 1165:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_PBURST_INC8 1166:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_PBURST_INC16 1167:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1168:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_GetPeriphBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream) 1169:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1170:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))- ARM GAS /tmp/ccLSPxIe.s page 406 1171:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1172:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1173:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1174:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Set Current target (only in double buffer mode) to Memory 1 or Memory 0. 1175:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR CT LL_DMA_SetCurrentTargetMem 1176:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 1177:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: 1178:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 1179:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 1180:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 1181:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 1182:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 1183:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 1184:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 1185:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 1186:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param CurrentMemory This parameter can be one of the following values: 1187:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CURRENTTARGETMEM0 1188:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CURRENTTARGETMEM1 1189:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 1190:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1191:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_SetCurrentTargetMem(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Curren 1192:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1193:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, 1194:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1195:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1196:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1197:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Set Current target (only in double buffer mode) to Memory 1 or Memory 0. 1198:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR CT LL_DMA_GetCurrentTargetMem 1199:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 1200:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: 1201:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 1202:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 1203:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 1204:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 1205:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 1206:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 1207:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 1208:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 1209:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval Returned value can be one of the following values: 1210:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CURRENTTARGETMEM0 1211:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CURRENTTARGETMEM1 1212:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1213:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_GetCurrentTargetMem(DMA_TypeDef *DMAx, uint32_t Stream) 1214:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1215:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))- 1216:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1217:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1218:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1219:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Enable the double buffer mode. 1220:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR DBM LL_DMA_EnableDoubleBufferMode 1221:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 1222:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: 1223:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 1224:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 1225:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 1226:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 1227:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 ARM GAS /tmp/ccLSPxIe.s page 407 1228:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 1229:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 1230:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 1231:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 1232:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1233:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_EnableDoubleBufferMode(DMA_TypeDef *DMAx, uint32_t Stream) 1234:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1235:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA 1236:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1237:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1238:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1239:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Disable the double buffer mode. 1240:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR DBM LL_DMA_DisableDoubleBufferMode 1241:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 1242:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: 1243:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 1244:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 1245:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 1246:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 1247:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 1248:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 1249:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 1250:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 1251:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 1252:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1253:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_DisableDoubleBufferMode(DMA_TypeDef *DMAx, uint32_t Stream) 1254:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1255:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, D 1256:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1257:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1258:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1259:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get FIFO status. 1260:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll FCR FS LL_DMA_GetFIFOStatus 1261:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 1262:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: 1263:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 1264:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 1265:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 1266:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 1267:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 1268:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 1269:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 1270:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 1271:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval Returned value can be one of the following values: 1272:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_FIFOSTATUS_0_25 1273:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_FIFOSTATUS_25_50 1274:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_FIFOSTATUS_50_75 1275:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_FIFOSTATUS_75_100 1276:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_FIFOSTATUS_EMPTY 1277:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_FIFOSTATUS_FULL 1278:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1279:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_GetFIFOStatus(DMA_TypeDef *DMAx, uint32_t Stream) 1280:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1281:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))- 1282:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1283:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1284:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** ARM GAS /tmp/ccLSPxIe.s page 408 1285:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Disable Fifo mode. 1286:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll FCR DMDIS LL_DMA_DisableFifoMode 1287:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 1288:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: 1289:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 1290:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 1291:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 1292:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 1293:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 1294:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 1295:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 1296:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 1297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 1298:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1299:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_DisableFifoMode(DMA_TypeDef *DMAx, uint32_t Stream) 1300:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1301:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, 1302:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1303:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1304:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1305:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Enable Fifo mode. 1306:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll FCR DMDIS LL_DMA_EnableFifoMode 1307:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 1308:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: 1309:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 1310:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 1311:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 1312:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 1313:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 1314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 1315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 1316:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 1317:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 1318:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1319:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_EnableFifoMode(DMA_TypeDef *DMAx, uint32_t Stream) 1320:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1321:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DM 1322:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1323:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1324:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1325:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Select FIFO threshold. 1326:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll FCR FTH LL_DMA_SetFIFOThreshold 1327:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 1328:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: 1329:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 1330:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 1331:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 1332:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 1333:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 1334:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 1335:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 1336:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 1337:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Threshold This parameter can be one of the following values: 1338:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_FIFOTHRESHOLD_1_4 1339:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_FIFOTHRESHOLD_1_2 1340:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_FIFOTHRESHOLD_3_4 1341:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_FIFOTHRESHOLD_FULL ARM GAS /tmp/ccLSPxIe.s page 409 1342:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 1343:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1344:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_SetFIFOThreshold(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Threshold 1345:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, 1347:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1348:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1349:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1350:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get FIFO threshold. 1351:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll FCR FTH LL_DMA_GetFIFOThreshold 1352:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 1353:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: 1354:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 1355:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 1356:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 1357:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 1358:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 1359:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 1360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 1361:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 1362:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval Returned value can be one of the following values: 1363:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_FIFOTHRESHOLD_1_4 1364:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_FIFOTHRESHOLD_1_2 1365:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_FIFOTHRESHOLD_3_4 1366:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_FIFOTHRESHOLD_FULL 1367:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1368:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_GetFIFOThreshold(DMA_TypeDef *DMAx, uint32_t Stream) 1369:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))- 1371:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1374:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Configure the FIFO . 1375:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll FCR FTH LL_DMA_ConfigFifo\n 1376:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * FCR DMDIS LL_DMA_ConfigFifo 1377:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 1378:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: 1379:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 1380:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 1381:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 1382:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 1383:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 1384:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 1385:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 1386:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 1387:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param FifoMode This parameter can be one of the following values: 1388:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_FIFOMODE_ENABLE 1389:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_FIFOMODE_DISABLE 1390:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param FifoThreshold This parameter can be one of the following values: 1391:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_FIFOTHRESHOLD_1_4 1392:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_FIFOTHRESHOLD_1_2 1393:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_FIFOTHRESHOLD_3_4 1394:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_FIFOTHRESHOLD_FULL 1395:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 1396:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1397:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ConfigFifo(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t FifoMode, uint3 1398:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { ARM GAS /tmp/ccLSPxIe.s page 410 1399:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, 1400:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1401:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1402:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1403:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Configure the Source and Destination addresses. 1404:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @note This API must not be called when the DMA stream is enabled. 1405:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll M0AR M0A LL_DMA_ConfigAddresses\n 1406:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * PAR PA LL_DMA_ConfigAddresses 1407:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 1408:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: 1409:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 1410:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 1411:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 1412:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 1413:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 1414:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 1415:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 1416:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 1417:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param SrcAddress Between 0 to 0xFFFFFFFF 1418:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DstAddress Between 0 to 0xFFFFFFFF 1419:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Direction This parameter can be one of the following values: 1420:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY 1421:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH 1422:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY 1423:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 1424:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1425:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ConfigAddresses(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t SrcAddress 1426:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1427:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /* Direction Memory to Periph */ 1428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** if (Direction == LL_DMA_DIRECTION_MEMORY_TO_PERIPH) 1429:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1430:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR 1431:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR, 1432:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1433:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /* Direction Periph to Memory and Memory to Memory */ 1434:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** else 1435:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1436:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR, 1437:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR 1438:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1439:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1440:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1441:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1442:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Set the Memory address. 1443:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll M0AR M0A LL_DMA_SetMemoryAddress 1444:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMO 1445:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @note This API must not be called when the DMA channel is enabled. 1446:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 1447:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: 1448:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 1449:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 1450:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 1451:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 1452:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 1453:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 1454:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 1455:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 ARM GAS /tmp/ccLSPxIe.s page 411 1456:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param MemoryAddress Between 0 to 0xFFFFFFFF 1457:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 1458:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1459:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_SetMemoryAddress(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t MemoryAdd 1460:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1461:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR, 1462:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1464:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1465:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Set the Peripheral address. 1466:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll PAR PA LL_DMA_SetPeriphAddress 1467:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMO 1468:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @note This API must not be called when the DMA channel is enabled. 1469:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 1470:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: 1471:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 1472:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 1473:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 1474:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 1475:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 1476:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 1477:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 1478:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 1479:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param PeriphAddress Between 0 to 0xFFFFFFFF 1480:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 1481:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1482:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_SetPeriphAddress(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t PeriphAdd 1483:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1484:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR, P 1485:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1486:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1487:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1488:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get the Memory address. 1489:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll M0AR M0A LL_DMA_GetMemoryAddress 1490:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMO 1491:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 1492:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: 1493:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 1494:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 1495:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 1496:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 1497:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 1498:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 1499:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 1500:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 1501:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval Between 0 to 0xFFFFFFFF 1502:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1503:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress(DMA_TypeDef* DMAx, uint32_t Stream) 1504:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1505:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))- 1506:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1507:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1508:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1509:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get the Peripheral address. 1510:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll PAR PA LL_DMA_GetPeriphAddress 1511:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMO 1512:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance ARM GAS /tmp/ccLSPxIe.s page 412 1513:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: 1514:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 1515:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 1516:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 1517:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 1518:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 1519:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 1520:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 1521:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 1522:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval Between 0 to 0xFFFFFFFF 1523:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1524:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress(DMA_TypeDef* DMAx, uint32_t Stream) 1525:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1526:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_REG(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream]))) 1527:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1528:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1529:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1530:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Set the Memory to Memory Source address. 1531:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll PAR PA LL_DMA_SetM2MSrcAddress 1532:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only. 1533:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @note This API must not be called when the DMA channel is enabled. 1534:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 1535:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: 1536:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 1537:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 1538:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 1539:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 1540:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 1541:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 1542:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 1543:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 1544:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param MemoryAddress Between 0 to 0xFFFFFFFF 1545:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 1546:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1547:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_SetM2MSrcAddress(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t MemoryAdd 1548:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1549:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR, M 1550:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1551:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1552:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1553:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Set the Memory to Memory Destination address. 1554:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll M0AR M0A LL_DMA_SetM2MDstAddress 1555:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only. 1556:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @note This API must not be called when the DMA channel is enabled. 1557:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 1558:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: 1559:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 1560:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 1561:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 1562:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 1563:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 1564:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 1565:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 1566:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 1567:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param MemoryAddress Between 0 to 0xFFFFFFFF 1568:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 1569:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ ARM GAS /tmp/ccLSPxIe.s page 413 1570:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_SetM2MDstAddress(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t MemoryAdd 1571:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1572:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR 1573:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1574:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1575:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1576:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get the Memory to Memory Source address. 1577:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll PAR PA LL_DMA_GetM2MSrcAddress 1578:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only. 1579:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 1580:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: 1581:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 1582:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 1583:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 1584:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 1585:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 1586:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 1587:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 1588:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 1589:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval Between 0 to 0xFFFFFFFF 1590:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1591:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress(DMA_TypeDef* DMAx, uint32_t Stream) 1592:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1593:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_REG(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])) 1594:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1595:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1596:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1597:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get the Memory to Memory Destination address. 1598:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll M0AR M0A LL_DMA_GetM2MDstAddress 1599:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only. 1600:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 1601:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: 1602:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 1603:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 1604:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 1605:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 1606:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 1607:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 1608:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 1609:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 1610:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval Between 0 to 0xFFFFFFFF 1611:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1612:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(DMA_TypeDef* DMAx, uint32_t Stream) 1613:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1614:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))-> 1615:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1616:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1617:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1618:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Set Memory 1 address (used in case of Double buffer mode). 1619:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll M1AR M1A LL_DMA_SetMemory1Address 1620:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 1621:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: 1622:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 1623:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 1624:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 1625:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 1626:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 ARM GAS /tmp/ccLSPxIe.s page 414 1627:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 1628:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 1629:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 1630:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Address Between 0 to 0xFFFFFFFF 1631:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 1632:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1633:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_SetMemory1Address(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Address) 1634:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1635:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M1AR, 1636:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1637:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1638:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1639:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Memory 1 address (used in case of Double buffer mode). 1640:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll M1AR M1A LL_DMA_GetMemory1Address 1641:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 1642:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: 1643:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 1644:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 1645:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 1646:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 1647:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 1648:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 1649:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 1650:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 1651:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval Between 0 to 0xFFFFFFFF 1652:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1653:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_GetMemory1Address(DMA_TypeDef *DMAx, uint32_t Stream) 1654:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1655:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M1AR); 1656:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1657:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1658:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1659:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @} 1660:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1661:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1662:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_EF_FLAG_Management FLAG_Management 1663:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @{ 1664:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1665:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1666:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1667:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 0 half transfer flag. 1668:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LISR HTIF0 LL_DMA_IsActiveFlag_HT0 1669:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 1670:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). 1671:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1672:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT0(DMA_TypeDef *DMAx) 1673:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1674:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->LISR ,DMA_LISR_HTIF0)==(DMA_LISR_HTIF0)); 1675:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1676:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1677:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1678:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 1 half transfer flag. 1679:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LISR HTIF1 LL_DMA_IsActiveFlag_HT1 1680:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 1681:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). 1682:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1683:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT1(DMA_TypeDef *DMAx) ARM GAS /tmp/ccLSPxIe.s page 415 1684:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1685:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->LISR ,DMA_LISR_HTIF1)==(DMA_LISR_HTIF1)); 1686:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1687:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1688:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1689:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 2 half transfer flag. 1690:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LISR HTIF2 LL_DMA_IsActiveFlag_HT2 1691:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 1692:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). 1693:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1694:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT2(DMA_TypeDef *DMAx) 1695:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1696:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->LISR ,DMA_LISR_HTIF2)==(DMA_LISR_HTIF2)); 1697:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1698:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1699:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1700:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 3 half transfer flag. 1701:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LISR HTIF3 LL_DMA_IsActiveFlag_HT3 1702:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 1703:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). 1704:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1705:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT3(DMA_TypeDef *DMAx) 1706:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1707:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->LISR ,DMA_LISR_HTIF3)==(DMA_LISR_HTIF3)); 1708:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1709:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1710:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1711:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 4 half transfer flag. 1712:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HISR HTIF4 LL_DMA_IsActiveFlag_HT4 1713:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 1714:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). 1715:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1716:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT4(DMA_TypeDef *DMAx) 1717:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1718:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->HISR ,DMA_HISR_HTIF4)==(DMA_HISR_HTIF4)); 1719:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1720:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1721:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1722:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 5 half transfer flag. 1723:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HISR HTIF0 LL_DMA_IsActiveFlag_HT5 1724:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 1725:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). 1726:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1727:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT5(DMA_TypeDef *DMAx) 1728:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1729:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->HISR ,DMA_HISR_HTIF5)==(DMA_HISR_HTIF5)); 1730:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1731:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1732:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1733:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 6 half transfer flag. 1734:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HISR HTIF6 LL_DMA_IsActiveFlag_HT6 1735:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 1736:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). 1737:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1738:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT6(DMA_TypeDef *DMAx) 1739:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1740:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->HISR ,DMA_HISR_HTIF6)==(DMA_HISR_HTIF6)); ARM GAS /tmp/ccLSPxIe.s page 416 1741:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1742:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1743:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1744:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 7 half transfer flag. 1745:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HISR HTIF7 LL_DMA_IsActiveFlag_HT7 1746:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 1747:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). 1748:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1749:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT7(DMA_TypeDef *DMAx) 1750:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1751:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->HISR ,DMA_HISR_HTIF7)==(DMA_HISR_HTIF7)); 1752:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1753:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1754:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1755:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 0 transfer complete flag. 1756:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LISR TCIF0 LL_DMA_IsActiveFlag_TC0 1757:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 1758:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). 1759:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1760:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC0(DMA_TypeDef *DMAx) 1761:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1762:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->LISR ,DMA_LISR_TCIF0)==(DMA_LISR_TCIF0)); 1763:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1764:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1765:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1766:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 1 transfer complete flag. 1767:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LISR TCIF1 LL_DMA_IsActiveFlag_TC1 1768:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 1769:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). 1770:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1771:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC1(DMA_TypeDef *DMAx) 1772:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1773:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->LISR ,DMA_LISR_TCIF1)==(DMA_LISR_TCIF1)); 1774:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1775:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1776:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1777:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 2 transfer complete flag. 1778:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LISR TCIF2 LL_DMA_IsActiveFlag_TC2 1779:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 1780:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). 1781:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1782:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC2(DMA_TypeDef *DMAx) 1783:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1784:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->LISR ,DMA_LISR_TCIF2)==(DMA_LISR_TCIF2)); 1785:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1786:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1787:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1788:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 3 transfer complete flag. 1789:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LISR TCIF3 LL_DMA_IsActiveFlag_TC3 1790:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 1791:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). 1792:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1793:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC3(DMA_TypeDef *DMAx) 1794:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1795:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->LISR ,DMA_LISR_TCIF3)==(DMA_LISR_TCIF3)); 1796:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1797:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** ARM GAS /tmp/ccLSPxIe.s page 417 1798:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1799:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 4 transfer complete flag. 1800:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HISR TCIF4 LL_DMA_IsActiveFlag_TC4 1801:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 1802:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). 1803:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1804:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC4(DMA_TypeDef *DMAx) 1805:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1806:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->HISR ,DMA_HISR_TCIF4)==(DMA_HISR_TCIF4)); 1807:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1808:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1809:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1810:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 5 transfer complete flag. 1811:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HISR TCIF0 LL_DMA_IsActiveFlag_TC5 1812:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 1813:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). 1814:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1815:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC5(DMA_TypeDef *DMAx) 1816:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1817:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->HISR ,DMA_HISR_TCIF5)==(DMA_HISR_TCIF5)); 1818:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1819:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1820:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1821:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 6 transfer complete flag. 1822:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HISR TCIF6 LL_DMA_IsActiveFlag_TC6 1823:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 1824:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). 1825:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1826:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC6(DMA_TypeDef *DMAx) 1827:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1828:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->HISR ,DMA_HISR_TCIF6)==(DMA_HISR_TCIF6)); 1829:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1830:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1831:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1832:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 7 transfer complete flag. 1833:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HISR TCIF7 LL_DMA_IsActiveFlag_TC7 1834:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 1835:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). 1836:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1837:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC7(DMA_TypeDef *DMAx) 1838:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1839:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->HISR ,DMA_HISR_TCIF7)==(DMA_HISR_TCIF7)); 1840:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1841:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1842:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1843:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 0 transfer error flag. 1844:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LISR TEIF0 LL_DMA_IsActiveFlag_TE0 1845:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 1846:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). 1847:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1848:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE0(DMA_TypeDef *DMAx) 1849:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1850:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->LISR ,DMA_LISR_TEIF0)==(DMA_LISR_TEIF0)); 1851:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1852:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1853:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1854:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 1 transfer error flag. ARM GAS /tmp/ccLSPxIe.s page 418 1855:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LISR TEIF1 LL_DMA_IsActiveFlag_TE1 1856:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 1857:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). 1858:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1859:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE1(DMA_TypeDef *DMAx) 1860:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1861:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->LISR ,DMA_LISR_TEIF1)==(DMA_LISR_TEIF1)); 1862:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1863:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1864:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1865:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 2 transfer error flag. 1866:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LISR TEIF2 LL_DMA_IsActiveFlag_TE2 1867:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 1868:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). 1869:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1870:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE2(DMA_TypeDef *DMAx) 1871:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1872:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->LISR ,DMA_LISR_TEIF2)==(DMA_LISR_TEIF2)); 1873:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1874:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1875:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1876:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 3 transfer error flag. 1877:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LISR TEIF3 LL_DMA_IsActiveFlag_TE3 1878:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 1879:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). 1880:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1881:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE3(DMA_TypeDef *DMAx) 1882:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1883:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->LISR ,DMA_LISR_TEIF3)==(DMA_LISR_TEIF3)); 1884:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1885:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1886:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1887:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 4 transfer error flag. 1888:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HISR TEIF4 LL_DMA_IsActiveFlag_TE4 1889:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 1890:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). 1891:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1892:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE4(DMA_TypeDef *DMAx) 1893:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1894:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->HISR ,DMA_HISR_TEIF4)==(DMA_HISR_TEIF4)); 1895:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1896:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1897:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1898:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 5 transfer error flag. 1899:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HISR TEIF0 LL_DMA_IsActiveFlag_TE5 1900:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 1901:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). 1902:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1903:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE5(DMA_TypeDef *DMAx) 1904:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1905:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->HISR ,DMA_HISR_TEIF5)==(DMA_HISR_TEIF5)); 1906:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1908:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1909:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 6 transfer error flag. 1910:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HISR TEIF6 LL_DMA_IsActiveFlag_TE6 1911:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance ARM GAS /tmp/ccLSPxIe.s page 419 1912:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). 1913:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1914:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE6(DMA_TypeDef *DMAx) 1915:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1916:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->HISR ,DMA_HISR_TEIF6)==(DMA_HISR_TEIF6)); 1917:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1919:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1920:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 7 transfer error flag. 1921:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HISR TEIF7 LL_DMA_IsActiveFlag_TE7 1922:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 1923:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). 1924:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1925:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE7(DMA_TypeDef *DMAx) 1926:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1927:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->HISR ,DMA_HISR_TEIF7)==(DMA_HISR_TEIF7)); 1928:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1929:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1930:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1931:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 0 direct mode error flag. 1932:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LISR DMEIF0 LL_DMA_IsActiveFlag_DME0 1933:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 1934:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). 1935:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1936:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME0(DMA_TypeDef *DMAx) 1937:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1938:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->LISR ,DMA_LISR_DMEIF0)==(DMA_LISR_DMEIF0)); 1939:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1940:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1941:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1942:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 1 direct mode error flag. 1943:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LISR DMEIF1 LL_DMA_IsActiveFlag_DME1 1944:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 1945:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). 1946:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1947:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME1(DMA_TypeDef *DMAx) 1948:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1949:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->LISR ,DMA_LISR_DMEIF1)==(DMA_LISR_DMEIF1)); 1950:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1951:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1952:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1953:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 2 direct mode error flag. 1954:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LISR DMEIF2 LL_DMA_IsActiveFlag_DME2 1955:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 1956:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). 1957:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1958:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME2(DMA_TypeDef *DMAx) 1959:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1960:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->LISR ,DMA_LISR_DMEIF2)==(DMA_LISR_DMEIF2)); 1961:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1962:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1963:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1964:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 3 direct mode error flag. 1965:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LISR DMEIF3 LL_DMA_IsActiveFlag_DME3 1966:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 1967:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). 1968:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ ARM GAS /tmp/ccLSPxIe.s page 420 1969:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME3(DMA_TypeDef *DMAx) 1970:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1971:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->LISR ,DMA_LISR_DMEIF3)==(DMA_LISR_DMEIF3)); 1972:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1973:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1974:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1975:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 4 direct mode error flag. 1976:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HISR DMEIF4 LL_DMA_IsActiveFlag_DME4 1977:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 1978:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). 1979:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1980:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME4(DMA_TypeDef *DMAx) 1981:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1982:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->HISR ,DMA_HISR_DMEIF4)==(DMA_HISR_DMEIF4)); 1983:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1984:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1985:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1986:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 5 direct mode error flag. 1987:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HISR DMEIF0 LL_DMA_IsActiveFlag_DME5 1988:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 1989:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). 1990:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 1991:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME5(DMA_TypeDef *DMAx) 1992:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 1993:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->HISR ,DMA_HISR_DMEIF5)==(DMA_HISR_DMEIF5)); 1994:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 1995:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 1996:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 1997:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 6 direct mode error flag. 1998:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HISR DMEIF6 LL_DMA_IsActiveFlag_DME6 1999:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 2000:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). 2001:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 2002:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME6(DMA_TypeDef *DMAx) 2003:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 2004:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->HISR ,DMA_HISR_DMEIF6)==(DMA_HISR_DMEIF6)); 2005:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 2006:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 2007:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 2008:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 7 direct mode error flag. 2009:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HISR DMEIF7 LL_DMA_IsActiveFlag_DME7 2010:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 2011:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). 2012:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 2013:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME7(DMA_TypeDef *DMAx) 2014:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 2015:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->HISR ,DMA_HISR_DMEIF7)==(DMA_HISR_DMEIF7)); 2016:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 2017:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 2018:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 2019:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 0 FIFO error flag. 2020:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LISR FEIF0 LL_DMA_IsActiveFlag_FE0 2021:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 2022:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). 2023:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 2024:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE0(DMA_TypeDef *DMAx) 2025:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { ARM GAS /tmp/ccLSPxIe.s page 421 2026:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->LISR ,DMA_LISR_FEIF0)==(DMA_LISR_FEIF0)); 2027:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 2028:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 2029:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 2030:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 1 FIFO error flag. 2031:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LISR FEIF1 LL_DMA_IsActiveFlag_FE1 2032:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 2033:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). 2034:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 2035:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE1(DMA_TypeDef *DMAx) 2036:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 2037:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->LISR ,DMA_LISR_FEIF1)==(DMA_LISR_FEIF1)); 2038:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 2039:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 2040:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 2041:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 2 FIFO error flag. 2042:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LISR FEIF2 LL_DMA_IsActiveFlag_FE2 2043:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 2044:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). 2045:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 2046:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE2(DMA_TypeDef *DMAx) 2047:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 2048:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->LISR ,DMA_LISR_FEIF2)==(DMA_LISR_FEIF2)); 2049:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 2050:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 2051:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 2052:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 3 FIFO error flag. 2053:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LISR FEIF3 LL_DMA_IsActiveFlag_FE3 2054:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 2055:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). 2056:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 2057:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE3(DMA_TypeDef *DMAx) 2058:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 2059:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->LISR ,DMA_LISR_FEIF3)==(DMA_LISR_FEIF3)); 2060:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 2061:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 2062:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 2063:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 4 FIFO error flag. 2064:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HISR FEIF4 LL_DMA_IsActiveFlag_FE4 2065:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 2066:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). 2067:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 2068:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE4(DMA_TypeDef *DMAx) 2069:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 2070:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->HISR ,DMA_HISR_FEIF4)==(DMA_HISR_FEIF4)); 2071:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 2072:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 2073:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 2074:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 5 FIFO error flag. 2075:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HISR FEIF0 LL_DMA_IsActiveFlag_FE5 2076:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 2077:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). 2078:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 2079:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE5(DMA_TypeDef *DMAx) 2080:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 2081:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->HISR ,DMA_HISR_FEIF5)==(DMA_HISR_FEIF5)); 2082:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } ARM GAS /tmp/ccLSPxIe.s page 422 2083:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 2084:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 2085:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 6 FIFO error flag. 2086:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HISR FEIF6 LL_DMA_IsActiveFlag_FE6 2087:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 2088:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). 2089:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 2090:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE6(DMA_TypeDef *DMAx) 2091:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 2092:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->HISR ,DMA_HISR_FEIF6)==(DMA_HISR_FEIF6)); 2093:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 2094:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 2095:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 2096:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 7 FIFO error flag. 2097:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HISR FEIF7 LL_DMA_IsActiveFlag_FE7 2098:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 2099:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). 2100:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 2101:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE7(DMA_TypeDef *DMAx) 2102:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 2103:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->HISR ,DMA_HISR_FEIF7)==(DMA_HISR_FEIF7)); 2104:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 2105:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 2106:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 2107:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Clear Stream 0 half transfer flag. 2108:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LIFCR CHTIF0 LL_DMA_ClearFlag_HT0 2109:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 2110:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 2111:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 2112:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_HT0(DMA_TypeDef *DMAx) 2113:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 2114:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CHTIF0); 2115:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 2116:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 2117:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 2118:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Clear Stream 1 half transfer flag. 2119:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LIFCR CHTIF1 LL_DMA_ClearFlag_HT1 2120:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 2121:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 2122:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 2123:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_HT1(DMA_TypeDef *DMAx) 2124:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 2125:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CHTIF1); 2126:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 2127:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 2128:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 2129:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Clear Stream 2 half transfer flag. 2130:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LIFCR CHTIF2 LL_DMA_ClearFlag_HT2 2131:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 2132:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 2133:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 2134:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_HT2(DMA_TypeDef *DMAx) 2135:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 2136:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CHTIF2); 2137:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 2138:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 2139:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** ARM GAS /tmp/ccLSPxIe.s page 423 2140:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Clear Stream 3 half transfer flag. 2141:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LIFCR CHTIF3 LL_DMA_ClearFlag_HT3 2142:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 2143:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 2144:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 2145:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_HT3(DMA_TypeDef *DMAx) 2146:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 2147:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CHTIF3); 2148:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 2149:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 2150:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 2151:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Clear Stream 4 half transfer flag. 2152:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HIFCR CHTIF4 LL_DMA_ClearFlag_HT4 2153:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 2154:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 2155:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 2156:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_HT4(DMA_TypeDef *DMAx) 2157:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 2158:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CHTIF4); 2159:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 2160:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 2161:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 2162:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Clear Stream 5 half transfer flag. 2163:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HIFCR CHTIF5 LL_DMA_ClearFlag_HT5 2164:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 2165:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 2166:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 2167:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_HT5(DMA_TypeDef *DMAx) 2168:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 2169:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CHTIF5); 2170:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 2171:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 2172:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 2173:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Clear Stream 6 half transfer flag. 2174:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HIFCR CHTIF6 LL_DMA_ClearFlag_HT6 2175:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 2176:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 2177:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 2178:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_HT6(DMA_TypeDef *DMAx) 2179:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 2180:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CHTIF6); 2181:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 2182:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 2183:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 2184:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Clear Stream 7 half transfer flag. 2185:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HIFCR CHTIF7 LL_DMA_ClearFlag_HT7 2186:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 2187:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 2188:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 2189:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_HT7(DMA_TypeDef *DMAx) 2190:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 2191:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CHTIF7); 2192:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 2193:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 2194:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 2195:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Clear Stream 0 transfer complete flag. 2196:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LIFCR CTCIF0 LL_DMA_ClearFlag_TC0 ARM GAS /tmp/ccLSPxIe.s page 424 2197:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 2198:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 2199:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 2200:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_TC0(DMA_TypeDef *DMAx) 2201:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 2202:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTCIF0); 2203:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 2204:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 2205:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 2206:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Clear Stream 1 transfer complete flag. 2207:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LIFCR CTCIF1 LL_DMA_ClearFlag_TC1 2208:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 2209:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 2210:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 2211:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_TC1(DMA_TypeDef *DMAx) 2212:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 2213:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTCIF1); 2214:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 2215:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 2216:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 2217:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Clear Stream 2 transfer complete flag. 2218:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LIFCR CTCIF2 LL_DMA_ClearFlag_TC2 2219:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 2220:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 2221:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 2222:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_TC2(DMA_TypeDef *DMAx) 2223:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 2224:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTCIF2); 2225:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 2226:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 2227:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 2228:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Clear Stream 3 transfer complete flag. 2229:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LIFCR CTCIF3 LL_DMA_ClearFlag_TC3 2230:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 2231:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 2232:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 2233:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_TC3(DMA_TypeDef *DMAx) 2234:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 2235:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTCIF3); 2236:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 2237:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 2238:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 2239:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Clear Stream 4 transfer complete flag. 2240:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HIFCR CTCIF4 LL_DMA_ClearFlag_TC4 2241:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 2242:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 2243:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 2244:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_TC4(DMA_TypeDef *DMAx) 2245:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 2246:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTCIF4); 2247:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 2248:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 2249:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 2250:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Clear Stream 5 transfer complete flag. 2251:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HIFCR CTCIF5 LL_DMA_ClearFlag_TC5 2252:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 2253:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None ARM GAS /tmp/ccLSPxIe.s page 425 2254:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 2255:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_TC5(DMA_TypeDef *DMAx) 2256:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 2257:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTCIF5); 2258:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 2259:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 2260:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 2261:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Clear Stream 6 transfer complete flag. 2262:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HIFCR CTCIF6 LL_DMA_ClearFlag_TC6 2263:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 2264:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 2265:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 2266:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_TC6(DMA_TypeDef *DMAx) 2267:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 2268:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTCIF6); 2269:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 2270:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 2271:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 2272:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Clear Stream 7 transfer complete flag. 2273:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HIFCR CTCIF7 LL_DMA_ClearFlag_TC7 2274:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 2275:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 2276:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 2277:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_TC7(DMA_TypeDef *DMAx) 7054 .loc 6 2277 22 view .LVU2190 7055 .LBB587: 2278:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 2279:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTCIF7); 7056 .loc 6 2279 3 view .LVU2191 7057 00dc 4FF00062 mov r2, #134217728 7058 00e0 DA60 str r2, [r3, #12] 7059 .LVL635: 7060 .loc 6 2279 3 is_stmt 0 view .LVU2192 7061 .LBE587: 7062 .LBE586: 2406:Src/main.c **** LL_USART_EnableDMAReq_TX(USART1); 7063 .loc 1 2406 3 is_stmt 1 view .LVU2193 7064 .LBB588: 7065 .LBI588: 2280:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 2281:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 2282:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 2283:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Clear Stream 0 transfer error flag. 2284:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LIFCR CTEIF0 LL_DMA_ClearFlag_TE0 2285:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 2286:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 2287:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 2288:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_TE0(DMA_TypeDef *DMAx) 2289:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 2290:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTEIF0); 2291:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 2292:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 2293:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 2294:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Clear Stream 1 transfer error flag. 2295:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LIFCR CTEIF1 LL_DMA_ClearFlag_TE1 2296:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 2297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None ARM GAS /tmp/ccLSPxIe.s page 426 2298:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 2299:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_TE1(DMA_TypeDef *DMAx) 2300:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 2301:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTEIF1); 2302:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 2303:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 2304:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 2305:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Clear Stream 2 transfer error flag. 2306:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LIFCR CTEIF2 LL_DMA_ClearFlag_TE2 2307:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 2308:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 2309:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 2310:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_TE2(DMA_TypeDef *DMAx) 2311:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 2312:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTEIF2); 2313:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 2314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 2315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 2316:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Clear Stream 3 transfer error flag. 2317:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LIFCR CTEIF3 LL_DMA_ClearFlag_TE3 2318:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 2319:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 2320:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 2321:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_TE3(DMA_TypeDef *DMAx) 2322:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 2323:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTEIF3); 2324:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 2325:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 2326:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 2327:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Clear Stream 4 transfer error flag. 2328:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HIFCR CTEIF4 LL_DMA_ClearFlag_TE4 2329:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 2330:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 2331:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 2332:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_TE4(DMA_TypeDef *DMAx) 2333:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 2334:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTEIF4); 2335:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 2336:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 2337:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 2338:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Clear Stream 5 transfer error flag. 2339:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HIFCR CTEIF5 LL_DMA_ClearFlag_TE5 2340:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 2341:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 2342:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 2343:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_TE5(DMA_TypeDef *DMAx) 2344:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 2345:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTEIF5); 2346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 2347:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 2348:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 2349:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Clear Stream 6 transfer error flag. 2350:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HIFCR CTEIF6 LL_DMA_ClearFlag_TE6 2351:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 2352:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 2353:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 2354:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_TE6(DMA_TypeDef *DMAx) ARM GAS /tmp/ccLSPxIe.s page 427 2355:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 2356:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTEIF6); 2357:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 2358:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 2359:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 2360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Clear Stream 7 transfer error flag. 2361:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HIFCR CTEIF7 LL_DMA_ClearFlag_TE7 2362:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 2363:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 2364:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 2365:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_TE7(DMA_TypeDef *DMAx) 7066 .loc 6 2365 22 view .LVU2194 7067 .LBB589: 2366:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 2367:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTEIF7); 7068 .loc 6 2367 3 view .LVU2195 7069 00e2 4FF00072 mov r2, #33554432 7070 00e6 DA60 str r2, [r3, #12] 7071 .LVL636: 7072 .loc 6 2367 3 is_stmt 0 view .LVU2196 7073 .LBE589: 7074 .LBE588: 2407:Src/main.c **** LL_DMA_EnableIT_TC(DMA2, LL_DMA_STREAM_7); 7075 .loc 1 2407 3 is_stmt 1 view .LVU2197 7076 .LBB590: 7077 .LBI590: 7078 .file 7 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h" 1:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ****************************************************************************** 3:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @file stm32f7xx_ll_usart.h 4:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @author MCD Application Team 5:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Header file of USART LL module. 6:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ****************************************************************************** 7:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @attention 8:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * 9:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Copyright (c) 2017 STMicroelectronics. 10:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * All rights reserved. 11:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * 12:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * This software is licensed under terms that can be found in the LICENSE file 13:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * in the root directory of this software component. 14:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * If no LICENSE file comes with this software, it is provided AS-IS. 15:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * 16:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ****************************************************************************** 17:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 18:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 19:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* Define to prevent recursive inclusion -------------------------------------*/ 20:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #ifndef STM32F7xx_LL_USART_H 21:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define STM32F7xx_LL_USART_H 22:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 23:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #ifdef __cplusplus 24:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** extern "C" { 25:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif 26:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 27:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* Includes ------------------------------------------------------------------*/ 28:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #include "stm32f7xx.h" 29:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 30:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @addtogroup STM32F7xx_LL_Driver ARM GAS /tmp/ccLSPxIe.s page 428 31:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ 32:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 33:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 34:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART1) || defined(USART2) || defined(USART3) || defined(USART6) \ 35:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** || defined(UART4) || defined(UART5) || defined(UART7) || defined(UART8) 36:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 37:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL USART 38:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ 39:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 40:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 41:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* Private types -------------------------------------------------------------*/ 42:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* Private variables ---------------------------------------------------------*/ 43:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 44:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* Private constants ---------------------------------------------------------*/ 45:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_Private_Constants USART Private Constants 46:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ 47:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 48:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 49:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} 50:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 51:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* Private macros ------------------------------------------------------------*/ 52:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USE_FULL_LL_DRIVER) 53:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_Private_Macros USART Private Macros 54:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ 55:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 56:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 57:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} 58:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 59:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /*USE_FULL_LL_DRIVER*/ 60:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 61:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* Exported types ------------------------------------------------------------*/ 62:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USE_FULL_LL_DRIVER) 63:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_ES_INIT USART Exported Init structures 64:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ 65:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 66:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 67:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 68:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief LL USART Init Structure definition 69:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 70:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** typedef struct 71:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 72:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 73:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** uint32_t BaudRate; /*!< This field defines expected Usart communication baud rat 74:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 75:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** This feature can be modified afterwards using unitary 76:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** function @ref LL_USART_SetBaudRate().*/ 77:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 78:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** uint32_t DataWidth; /*!< Specifies the number of data bits transmitted or receive 79:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** This parameter can be a value of @ref USART_LL_EC_DATAWI 80:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 81:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** This feature can be modified afterwards using unitary 82:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** function @ref LL_USART_SetDataWidth().*/ 83:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 84:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** uint32_t StopBits; /*!< Specifies the number of stop bits transmitted. 85:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** This parameter can be a value of @ref USART_LL_EC_STOPBI 86:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 87:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** This feature can be modified afterwards using unitary ARM GAS /tmp/ccLSPxIe.s page 429 88:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** function @ref LL_USART_SetStopBitsLength().*/ 89:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 90:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** uint32_t Parity; /*!< Specifies the parity mode. 91:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** This parameter can be a value of @ref USART_LL_EC_PARITY 92:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 93:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** This feature can be modified afterwards using unitary 94:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** function @ref LL_USART_SetParity().*/ 95:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 96:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** uint32_t TransferDirection; /*!< Specifies whether the Receive and/or Transmit mode is en 97:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** This parameter can be a value of @ref USART_LL_EC_DIRECT 98:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 99:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** This feature can be modified afterwards using unitary 100:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** function @ref LL_USART_SetTransferDirection().*/ 101:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 102:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** uint32_t HardwareFlowControl; /*!< Specifies whether the hardware flow control mode is enab 103:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** This parameter can be a value of @ref USART_LL_EC_HWCONT 104:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 105:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** This feature can be modified afterwards using unitary 106:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** function @ref LL_USART_SetHWFlowCtrl().*/ 107:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 108:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** uint32_t OverSampling; /*!< Specifies whether USART oversampling mode is 16 or 8. 109:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** This parameter can be a value of @ref USART_LL_EC_OVERSA 110:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 111:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** This feature can be modified afterwards using unitary 112:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** function @ref LL_USART_SetOverSampling().*/ 113:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 114:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } LL_USART_InitTypeDef; 115:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 116:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 117:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief LL USART Clock Init Structure definition 118:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 119:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** typedef struct 120:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 121:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** uint32_t ClockOutput; /*!< Specifies whether the USART clock is enabled or disabled 122:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** This parameter can be a value of @ref USART_LL_EC_CLOCK. 123:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 124:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** USART HW configuration can be modified afterwards using 125:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** @ref LL_USART_EnableSCLKOutput() or @ref LL_USART_Disabl 126:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** For more details, refer to description of this function. 127:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 128:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** uint32_t ClockPolarity; /*!< Specifies the steady state of the serial clock. 129:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** This parameter can be a value of @ref USART_LL_EC_POLARI 130:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 131:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** USART HW configuration can be modified afterwards using 132:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** functions @ref LL_USART_SetClockPolarity(). 133:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** For more details, refer to description of this function. 134:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 135:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** uint32_t ClockPhase; /*!< Specifies the clock transition on which the bit capture 136:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** This parameter can be a value of @ref USART_LL_EC_PHASE. 137:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 138:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** USART HW configuration can be modified afterwards using 139:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** functions @ref LL_USART_SetClockPhase(). 140:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** For more details, refer to description of this function. 141:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 142:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** uint32_t LastBitClockPulse; /*!< Specifies whether the clock pulse corresponding to the l 143:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** data bit (MSB) has to be output on the SCLK pin in synch 144:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** This parameter can be a value of @ref USART_LL_EC_LASTCL ARM GAS /tmp/ccLSPxIe.s page 430 145:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 146:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** USART HW configuration can be modified afterwards using 147:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** functions @ref LL_USART_SetLastClkPulseOutput(). 148:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** For more details, refer to description of this function. 149:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 150:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } LL_USART_ClockInitTypeDef; 151:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 152:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 153:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} 154:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 155:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USE_FULL_LL_DRIVER */ 156:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 157:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* Exported constants --------------------------------------------------------*/ 158:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_Exported_Constants USART Exported Constants 159:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ 160:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 161:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 162:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_CLEAR_FLAG Clear Flags Defines 163:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Flags defines which can be used with LL_USART_WriteReg function 164:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ 165:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 166:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ICR_PECF USART_ICR_PECF /*!< Parity error cle 167:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ICR_FECF USART_ICR_FECF /*!< Framing error cl 168:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ICR_NCF USART_ICR_NCF /*!< Noise error dete 169:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ICR_ORECF USART_ICR_ORECF /*!< Overrun error cl 170:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ICR_IDLECF USART_ICR_IDLECF /*!< Idle line detect 171:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ICR_TCCF USART_ICR_TCCF /*!< Transmission com 172:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_TCBGT_SUPPORT) 173:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ICR_TCBGTCF USART_ICR_TCBGTCF /*!< Transmission com 174:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_TCBGT_SUPPORT */ 175:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ICR_LBDCF USART_ICR_LBDCF /*!< LIN break detect 176:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ICR_CTSCF USART_ICR_CTSCF /*!< CTS clear flag * 177:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ICR_RTOCF USART_ICR_RTOCF /*!< Receiver timeout 178:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ICR_EOBCF USART_ICR_EOBCF /*!< End of block cle 179:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ICR_CMCF USART_ICR_CMCF /*!< Character match 180:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_CR1_UESM) 181:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_CR3_WUFIE) 182:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ICR_WUCF USART_ICR_WUCF /*!< Wakeup from Stop 183:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_CR3_WUFIE */ 184:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_CR1_UESM */ 185:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 186:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} 187:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 188:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 189:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_GET_FLAG Get Flags Defines 190:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Flags defines which can be used with LL_USART_ReadReg function 191:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ 192:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 193:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_PE USART_ISR_PE /*!< Parity error fla 194:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_FE USART_ISR_FE /*!< Framing error fl 195:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_NE USART_ISR_NE /*!< Noise detected f 196:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_ORE USART_ISR_ORE /*!< Overrun error fl 197:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_IDLE USART_ISR_IDLE /*!< Idle line detect 198:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_RXNE USART_ISR_RXNE /*!< Read data regist 199:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_TC USART_ISR_TC /*!< Transmission com 200:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_TXE USART_ISR_TXE /*!< Transmit data re 201:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_LBDF USART_ISR_LBDF /*!< LIN break detect ARM GAS /tmp/ccLSPxIe.s page 431 202:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_CTSIF USART_ISR_CTSIF /*!< CTS interrupt fl 203:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_CTS USART_ISR_CTS /*!< CTS flag */ 204:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_RTOF USART_ISR_RTOF /*!< Receiver timeout 205:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_EOBF USART_ISR_EOBF /*!< End of block fla 206:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_ABRE USART_ISR_ABRE /*!< Auto baud rate e 207:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_ABRF USART_ISR_ABRF /*!< Auto baud rate f 208:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_BUSY USART_ISR_BUSY /*!< Busy flag */ 209:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_CMF USART_ISR_CMF /*!< Character match 210:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_SBKF USART_ISR_SBKF /*!< Send break flag 211:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_RWU USART_ISR_RWU /*!< Receiver wakeup 212:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_CR1_UESM) 213:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_CR3_WUFIE) 214:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_WUF USART_ISR_WUF /*!< Wakeup from Stop 215:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_CR3_WUFIE */ 216:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_CR1_UESM */ 217:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_TEACK USART_ISR_TEACK /*!< Transmit enable 218:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_ISR_REACK) 219:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_REACK USART_ISR_REACK /*!< Receive enable a 220:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_ISR_REACK */ 221:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_TCBGT_SUPPORT) 222:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_TCBGT USART_ISR_TCBGT /*!< Transmission com 223:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_TCBGT_SUPPORT */ 224:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 225:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} 226:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 227:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 228:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_IT IT Defines 229:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief IT defines which can be used with LL_USART_ReadReg and LL_USART_WriteReg functions 230:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ 231:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 232:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_CR1_IDLEIE USART_CR1_IDLEIE /*!< IDLE interrupt e 233:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_CR1_RXNEIE USART_CR1_RXNEIE /*!< Read data regist 234:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_CR1_TCIE USART_CR1_TCIE /*!< Transmission com 235:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_CR1_TXEIE USART_CR1_TXEIE /*!< Transmit data re 236:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_CR1_PEIE USART_CR1_PEIE /*!< Parity error */ 237:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_CR1_CMIE USART_CR1_CMIE /*!< Character match 238:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_CR1_RTOIE USART_CR1_RTOIE /*!< Receiver timeout 239:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_CR1_EOBIE USART_CR1_EOBIE /*!< End of Block int 240:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_CR2_LBDIE USART_CR2_LBDIE /*!< LIN break detect 241:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_CR3_EIE USART_CR3_EIE /*!< Error interrupt 242:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_CR3_CTSIE USART_CR3_CTSIE /*!< CTS interrupt en 243:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_CR1_UESM) 244:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_CR3_WUFIE) 245:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_CR3_WUFIE USART_CR3_WUFIE /*!< Wakeup from Stop 246:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_CR3_WUFIE */ 247:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_CR1_UESM */ 248:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_TCBGT_SUPPORT) 249:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_CR3_TCBGTIE USART_CR3_TCBGTIE /*!< Transmission com 250:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_TCBGT_SUPPORT */ 251:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 252:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} 253:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 254:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 255:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_DIRECTION Communication Direction 256:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ 257:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 258:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_DIRECTION_NONE 0x00000000U /*!< Transmitter ARM GAS /tmp/ccLSPxIe.s page 432 259:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_DIRECTION_RX USART_CR1_RE /*!< Transmitter 260:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_DIRECTION_TX USART_CR1_TE /*!< Transmitter 261:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_DIRECTION_TX_RX (USART_CR1_TE |USART_CR1_RE) /*!< Transmitter 262:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 263:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} 264:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 265:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 266:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_PARITY Parity Control 267:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ 268:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 269:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_PARITY_NONE 0x00000000U /*!< Parity co 270:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_PARITY_EVEN USART_CR1_PCE /*!< Parity co 271:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS) /*!< Parity co 272:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 273:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} 274:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 275:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 276:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_WAKEUP Wakeup 277:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ 278:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 279:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_WAKEUP_IDLELINE 0x00000000U /*!< USART wake up from Mute 280:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_WAKEUP_ADDRESSMARK USART_CR1_WAKE /*!< USART wake up from Mute 281:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 282:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} 283:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 284:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 285:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_DATAWIDTH Datawidth 286:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ 287:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 288:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_DATAWIDTH_7B USART_CR1_M1 /*!< 7 bits word length : S 289:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_DATAWIDTH_8B 0x00000000U /*!< 8 bits word length : S 290:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_DATAWIDTH_9B USART_CR1_M0 /*!< 9 bits word length : S 291:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 292:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} 293:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 294:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 295:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_OVERSAMPLING Oversampling 296:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ 297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 298:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_OVERSAMPLING_16 0x00000000U /*!< Oversampling by 16 */ 299:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_OVERSAMPLING_8 USART_CR1_OVER8 /*!< Oversampling by 8 */ 300:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 301:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} 302:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 303:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 304:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USE_FULL_LL_DRIVER) 305:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_CLOCK Clock Signal 306:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ 307:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 308:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 309:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_CLOCK_DISABLE 0x00000000U /*!< Clock signal not provid 310:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_CLOCK_ENABLE USART_CR2_CLKEN /*!< Clock signal provided * 311:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 312:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} 313:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /*USE_FULL_LL_DRIVER*/ 315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ARM GAS /tmp/ccLSPxIe.s page 433 316:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_LASTCLKPULSE Last Clock Pulse 317:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ 318:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 319:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_LASTCLKPULSE_NO_OUTPUT 0x00000000U /*!< The clock pulse of the l 320:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_LASTCLKPULSE_OUTPUT USART_CR2_LBCL /*!< The clock pulse of the l 321:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 322:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} 323:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 324:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 325:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_PHASE Clock Phase 326:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ 327:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 328:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_PHASE_1EDGE 0x00000000U /*!< The first clock transiti 329:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_PHASE_2EDGE USART_CR2_CPHA /*!< The second clock transit 330:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 331:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} 332:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 333:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 334:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_POLARITY Clock Polarity 335:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ 336:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 337:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_POLARITY_LOW 0x00000000U /*!< Steady low value on SCLK 338:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_POLARITY_HIGH USART_CR2_CPOL /*!< Steady high value on SCL 339:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 340:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} 341:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 342:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 343:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_STOPBITS Stop Bits 344:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ 345:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_STOPBITS_0_5 USART_CR2_STOP_0 /*!< 0.5 347:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_STOPBITS_1 0x00000000U /*!< 1 s 348:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_STOPBITS_1_5 (USART_CR2_STOP_0 | USART_CR2_STOP_1) /*!< 1.5 349:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_STOPBITS_2 USART_CR2_STOP_1 /*!< 2 s 350:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 351:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} 352:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 353:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 354:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_TXRX TX RX Pins Swap 355:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ 356:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 357:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_TXRX_STANDARD 0x00000000U /*!< TX/RX pins are used as d 358:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_TXRX_SWAPPED (USART_CR2_SWAP) /*!< TX and RX pins functions 359:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} 361:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 362:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 363:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_RXPIN_LEVEL RX Pin Active Level Inversion 364:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ 365:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 366:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_RXPIN_LEVEL_STANDARD 0x00000000U /*!< RX pin signal works usin 367:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_RXPIN_LEVEL_INVERTED (USART_CR2_RXINV) /*!< RX pin signal values are 368:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 369:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} 370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 371:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_TXPIN_LEVEL TX Pin Active Level Inversion ARM GAS /tmp/ccLSPxIe.s page 434 373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ 374:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 375:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_TXPIN_LEVEL_STANDARD 0x00000000U /*!< TX pin signal works usin 376:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_TXPIN_LEVEL_INVERTED (USART_CR2_TXINV) /*!< TX pin signal values are 377:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 378:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} 379:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 380:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 381:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_BINARY_LOGIC Binary Data Inversion 382:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ 383:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 384:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_BINARY_LOGIC_POSITIVE 0x00000000U /*!< Logical data from the da 385:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_BINARY_LOGIC_NEGATIVE USART_CR2_DATAINV /*!< Logical data from the da 386:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 387:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} 388:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 389:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 390:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_BITORDER Bit Order 391:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ 392:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 393:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_BITORDER_LSBFIRST 0x00000000U /*!< data is transmitted/rece 394:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_BITORDER_MSBFIRST USART_CR2_MSBFIRST /*!< data is transmitted/rece 395:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 396:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} 397:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 398:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 399:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_AUTOBAUD_DETECT_ON Autobaud Detection 400:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ 401:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 402:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_AUTOBAUD_DETECT_ON_STARTBIT 0x00000000U /*!< Me 403:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_AUTOBAUD_DETECT_ON_FALLINGEDGE USART_CR2_ABRMODE_0 /*!< Fa 404:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME USART_CR2_ABRMODE_1 /*!< 0x 405:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_AUTOBAUD_DETECT_ON_55_FRAME (USART_CR2_ABRMODE_1 | USART_CR2_ABRMODE_0) /*!< 0x 406:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 407:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} 408:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 409:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 410:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_ADDRESS_DETECT Address Length Detection 411:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ 412:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 413:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ADDRESS_DETECT_4B 0x00000000U /*!< 4-bit address detection 414:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ADDRESS_DETECT_7B USART_CR2_ADDM7 /*!< 7-bit address detection 415:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 416:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} 417:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 418:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 419:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_HWCONTROL Hardware Control 420:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ 421:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 422:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_HWCONTROL_NONE 0x00000000U /*!< CTS and R 423:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_HWCONTROL_RTS USART_CR3_RTSE /*!< RTS outpu 424:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_HWCONTROL_CTS USART_CR3_CTSE /*!< CTS mode 425:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_HWCONTROL_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE) /*!< CTS and R 426:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 427:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} 428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 429:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ARM GAS /tmp/ccLSPxIe.s page 435 430:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_CR1_UESM) 431:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_CR3_WUS) 432:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_WAKEUP_ON Wakeup Activation 433:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ 434:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 435:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_WAKEUP_ON_ADDRESS 0x00000000U /*!< Wake u 436:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_WAKEUP_ON_STARTBIT USART_CR3_WUS_1 /*!< Wake u 437:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_WAKEUP_ON_RXNE (USART_CR3_WUS_0 | USART_CR3_WUS_1) /*!< Wake u 438:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 439:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} 440:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 441:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 442:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_CR3_WUS */ 443:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_CR1_UESM */ 444:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_IRDA_POWER IrDA Power 445:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ 446:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 447:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_IRDA_POWER_NORMAL 0x00000000U /*!< IrDA normal power mode * 448:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_IRDA_POWER_LOW USART_CR3_IRLP /*!< IrDA low power mode */ 449:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 450:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} 451:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 452:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 453:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_LINBREAK_DETECT LIN Break Detection Length 454:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ 455:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 456:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_LINBREAK_DETECT_10B 0x00000000U /*!< 10-bit break detection m 457:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_LINBREAK_DETECT_11B USART_CR2_LBDL /*!< 11-bit break detection m 458:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 459:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} 460:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 461:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 462:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_DE_POLARITY Driver Enable Polarity 463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ 464:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 465:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_DE_POLARITY_HIGH 0x00000000U /*!< DE signal is active high 466:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_DE_POLARITY_LOW USART_CR3_DEP /*!< DE signal is active low 467:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 468:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} 469:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 470:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 471:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_DMA_REG_DATA DMA Register Data 472:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ 473:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 474:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_DMA_REG_DATA_TRANSMIT 0x00000000U /*!< Get address of data regis 475:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_DMA_REG_DATA_RECEIVE 0x00000001U /*!< Get address of data regis 476:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 477:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} 478:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 479:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 480:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 481:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} 482:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 483:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 484:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* Exported macro ------------------------------------------------------------*/ 485:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_Exported_Macros USART Exported Macros 486:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ ARM GAS /tmp/ccLSPxIe.s page 436 487:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 488:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 489:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EM_WRITE_READ Common Write and read registers Macros 490:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ 491:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 492:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 493:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 494:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Write a value in USART register 495:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param __INSTANCE__ USART Instance 496:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param __REG__ Register to be written 497:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param __VALUE__ Value to be written in the register 498:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 499:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 500:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VAL 501:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 502:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 503:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Read a value in USART register 504:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param __INSTANCE__ USART Instance 505:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param __REG__ Register to be read 506:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Register value 507:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 508:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) 509:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 510:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} 511:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 512:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 513:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EM_Exported_Macros_Helper Exported_Macros_Helper 514:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ 515:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 516:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 517:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 518:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Compute USARTDIV value according to Peripheral Clock and 519:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * expected Baud Rate in 8 bits sampling mode (32 bits value of USARTDIV is returned) 520:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param __PERIPHCLK__ Peripheral Clock frequency used for USART instance 521:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param __BAUDRATE__ Baud rate value to achieve 522:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval USARTDIV value to be used for BRR register filling in OverSampling_8 case 523:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 524:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define __LL_USART_DIV_SAMPLING8(__PERIPHCLK__, __BAUDRATE__) ((((__PERIPHCLK__)*2U)\ 525:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + ((__BAUDRATE__)/2U))/(__BAUDRATE_ 526:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 527:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 528:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Compute USARTDIV value according to Peripheral Clock and 529:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * expected Baud Rate in 16 bits sampling mode (32 bits value of USARTDIV is returned) 530:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param __PERIPHCLK__ Peripheral Clock frequency used for USART instance 531:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param __BAUDRATE__ Baud rate value to achieve 532:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval USARTDIV value to be used for BRR register filling in OverSampling_16 case 533:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 534:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define __LL_USART_DIV_SAMPLING16(__PERIPHCLK__, __BAUDRATE__) (((__PERIPHCLK__) + ((__BAUDRATE__)/ 535:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 536:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 537:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} 538:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 539:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 540:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 541:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} 542:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 543:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ARM GAS /tmp/ccLSPxIe.s page 437 544:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* Exported functions --------------------------------------------------------*/ 545:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 546:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_Exported_Functions USART Exported Functions 547:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ 548:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 549:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 550:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EF_Configuration Configuration functions 551:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ 552:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 553:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 554:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 555:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief USART Enable 556:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 UE LL_USART_Enable 557:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 558:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 559:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 560:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_Enable(USART_TypeDef *USARTx) 561:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 562:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** SET_BIT(USARTx->CR1, USART_CR1_UE); 563:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 564:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 565:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 566:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief USART Disable (all USART prescalers and outputs are disabled) 567:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note When USART is disabled, USART prescalers and outputs are stopped immediately, 568:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * and current operations are discarded. The configuration of the USART is kept, but all t 569:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * flags, in the USARTx_ISR are set to their default values. 570:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 UE LL_USART_Disable 571:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 572:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 573:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 574:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_Disable(USART_TypeDef *USARTx) 575:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 576:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** CLEAR_BIT(USARTx->CR1, USART_CR1_UE); 577:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 578:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 579:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 580:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Indicate if USART is enabled 581:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 UE LL_USART_IsEnabled 582:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 583:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). 584:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 585:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabled(const USART_TypeDef *USARTx) 586:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 587:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->CR1, USART_CR1_UE) == (USART_CR1_UE)) ? 1UL : 0UL); 588:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 589:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 590:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_CR1_UESM) 591:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 592:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief USART enabled in STOP Mode. 593:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note When this function is enabled, USART is able to wake up the MCU from Stop mode, provide 594:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * USART clock selection is HSI or LSE in RCC. 595:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not 596:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Wake-up from Stop mode feature is supported by the USARTx instance. 597:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 UESM LL_USART_EnableInStopMode 598:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 599:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 600:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ ARM GAS /tmp/ccLSPxIe.s page 438 601:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableInStopMode(USART_TypeDef *USARTx) 602:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 603:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_UESM); 604:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 605:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 606:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 607:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief USART disabled in STOP Mode. 608:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note When this function is disabled, USART is not able to wake up the MCU from Stop mode 609:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not 610:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Wake-up from Stop mode feature is supported by the USARTx instance. 611:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 UESM LL_USART_DisableInStopMode 612:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 613:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 614:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 615:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableInStopMode(USART_TypeDef *USARTx) 616:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 617:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_UESM); 618:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 619:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 620:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 621:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Indicate if USART is enabled in STOP Mode (able to wake up MCU from Stop mode or not) 622:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not 623:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Wake-up from Stop mode feature is supported by the USARTx instance. 624:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 UESM LL_USART_IsEnabledInStopMode 625:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 626:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). 627:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 628:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledInStopMode(const USART_TypeDef *USARTx) 629:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 630:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->CR1, USART_CR1_UESM) == (USART_CR1_UESM)) ? 1UL : 0UL); 631:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 632:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 633:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_CR3_UCESM) 634:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 635:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief USART Clock enabled in STOP Mode 636:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note When this function is called, USART Clock is enabled while in STOP mode 637:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 UCESM LL_USART_EnableClockInStopMode 638:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 639:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 640:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 641:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableClockInStopMode(USART_TypeDef *USARTx) 642:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 643:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_UCESM); 644:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 645:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 646:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 647:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief USART clock disabled in STOP Mode 648:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note When this function is called, USART Clock is disabled while in STOP mode 649:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 UCESM LL_USART_DisableClockInStopMode 650:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 651:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 652:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 653:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableClockInStopMode(USART_TypeDef *USARTx) 654:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 655:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_UCESM); 656:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 657:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ARM GAS /tmp/ccLSPxIe.s page 439 658:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 659:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Indicate if USART clock is enabled in STOP Mode 660:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 UCESM LL_USART_IsClockEnabledInStopMode 661:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 662:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). 663:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 664:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsClockEnabledInStopMode(const USART_TypeDef *USARTx) 665:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 666:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return (READ_BIT(USARTx->CR3, USART_CR3_UCESM) == (USART_CR3_UCESM)); 667:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 668:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 669:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_CR3_UCESM */ 670:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_CR1_UESM*/ 671:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 672:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Receiver Enable (Receiver is enabled and begins searching for a start bit) 673:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 RE LL_USART_EnableDirectionRx 674:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 675:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 676:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 677:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableDirectionRx(USART_TypeDef *USARTx) 678:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 679:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_RE); 680:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 681:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 682:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 683:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Receiver Disable 684:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 RE LL_USART_DisableDirectionRx 685:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 686:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 687:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 688:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableDirectionRx(USART_TypeDef *USARTx) 689:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 690:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_RE); 691:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 692:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 693:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 694:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Transmitter Enable 695:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 TE LL_USART_EnableDirectionTx 696:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 697:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 698:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 699:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableDirectionTx(USART_TypeDef *USARTx) 700:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 701:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_TE); 702:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 703:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 704:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 705:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Transmitter Disable 706:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 TE LL_USART_DisableDirectionTx 707:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 708:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 709:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 710:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableDirectionTx(USART_TypeDef *USARTx) 711:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 712:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_TE); 713:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 714:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ARM GAS /tmp/ccLSPxIe.s page 440 715:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 716:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Configure simultaneously enabled/disabled states 717:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * of Transmitter and Receiver 718:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 RE LL_USART_SetTransferDirection\n 719:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR1 TE LL_USART_SetTransferDirection 720:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 721:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param TransferDirection This parameter can be one of the following values: 722:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_DIRECTION_NONE 723:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_DIRECTION_RX 724:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_DIRECTION_TX 725:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_DIRECTION_TX_RX 726:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 727:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 728:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetTransferDirection(USART_TypeDef *USARTx, uint32_t TransferDirectio 729:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 730:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_MODIFY_REG(USARTx->CR1, USART_CR1_RE | USART_CR1_TE, TransferDirection); 731:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 732:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 733:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 734:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Return enabled/disabled states of Transmitter and Receiver 735:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 RE LL_USART_GetTransferDirection\n 736:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR1 TE LL_USART_GetTransferDirection 737:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 738:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Returned value can be one of the following values: 739:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_DIRECTION_NONE 740:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_DIRECTION_RX 741:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_DIRECTION_TX 742:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_DIRECTION_TX_RX 743:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 744:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetTransferDirection(const USART_TypeDef *USARTx) 745:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 746:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_RE | USART_CR1_TE)); 747:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 748:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 749:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 750:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Configure Parity (enabled/disabled and parity mode if enabled). 751:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note This function selects if hardware parity control (generation and detection) is enabled 752:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * When the parity control is enabled (Odd or Even), computed parity bit is inserted at th 753:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * (9th or 8th bit depending on data width) and parity is checked on the received data. 754:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 PS LL_USART_SetParity\n 755:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR1 PCE LL_USART_SetParity 756:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 757:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param Parity This parameter can be one of the following values: 758:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_PARITY_NONE 759:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_PARITY_EVEN 760:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_PARITY_ODD 761:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 762:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 763:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetParity(USART_TypeDef *USARTx, uint32_t Parity) 764:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 765:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** MODIFY_REG(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE, Parity); 766:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 767:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 768:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 769:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Return Parity configuration (enabled/disabled and parity mode if enabled) 770:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 PS LL_USART_GetParity\n 771:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR1 PCE LL_USART_GetParity ARM GAS /tmp/ccLSPxIe.s page 441 772:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 773:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Returned value can be one of the following values: 774:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_PARITY_NONE 775:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_PARITY_EVEN 776:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_PARITY_ODD 777:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 778:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetParity(const USART_TypeDef *USARTx) 779:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 780:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE)); 781:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 782:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 783:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 784:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Set Receiver Wake Up method from Mute mode. 785:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 WAKE LL_USART_SetWakeUpMethod 786:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 787:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param Method This parameter can be one of the following values: 788:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_WAKEUP_IDLELINE 789:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_WAKEUP_ADDRESSMARK 790:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 791:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 792:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetWakeUpMethod(USART_TypeDef *USARTx, uint32_t Method) 793:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 794:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** MODIFY_REG(USARTx->CR1, USART_CR1_WAKE, Method); 795:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 796:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 797:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 798:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Return Receiver Wake Up method from Mute mode 799:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 WAKE LL_USART_GetWakeUpMethod 800:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 801:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Returned value can be one of the following values: 802:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_WAKEUP_IDLELINE 803:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_WAKEUP_ADDRESSMARK 804:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 805:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetWakeUpMethod(const USART_TypeDef *USARTx) 806:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 807:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_WAKE)); 808:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 809:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 810:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 811:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Set Word length (i.e. nb of data bits, excluding start and stop bits) 812:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 M0 LL_USART_SetDataWidth\n 813:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR1 M1 LL_USART_SetDataWidth 814:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 815:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param DataWidth This parameter can be one of the following values: 816:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_DATAWIDTH_7B 817:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_DATAWIDTH_8B 818:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_DATAWIDTH_9B 819:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 820:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 821:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetDataWidth(USART_TypeDef *USARTx, uint32_t DataWidth) 822:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 823:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** MODIFY_REG(USARTx->CR1, USART_CR1_M, DataWidth); 824:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 825:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 826:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 827:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Return Word length (i.e. nb of data bits, excluding start and stop bits) 828:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 M0 LL_USART_GetDataWidth\n ARM GAS /tmp/ccLSPxIe.s page 442 829:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR1 M1 LL_USART_GetDataWidth 830:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 831:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Returned value can be one of the following values: 832:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_DATAWIDTH_7B 833:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_DATAWIDTH_8B 834:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_DATAWIDTH_9B 835:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 836:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetDataWidth(const USART_TypeDef *USARTx) 837:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 838:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_M)); 839:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 840:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 841:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 842:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Allow switch between Mute Mode and Active mode 843:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 MME LL_USART_EnableMuteMode 844:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 845:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 846:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 847:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableMuteMode(USART_TypeDef *USARTx) 848:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 849:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_MME); 850:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 851:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 852:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 853:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Prevent Mute Mode use. Set Receiver in active mode permanently. 854:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 MME LL_USART_DisableMuteMode 855:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 856:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 857:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 858:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableMuteMode(USART_TypeDef *USARTx) 859:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 860:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_MME); 861:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 862:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 863:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 864:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Indicate if switch between Mute Mode and Active mode is allowed 865:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 MME LL_USART_IsEnabledMuteMode 866:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 867:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). 868:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 869:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledMuteMode(const USART_TypeDef *USARTx) 870:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 871:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->CR1, USART_CR1_MME) == (USART_CR1_MME)) ? 1UL : 0UL); 872:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 873:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 874:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 875:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Set Oversampling to 8-bit or 16-bit mode 876:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 OVER8 LL_USART_SetOverSampling 877:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 878:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param OverSampling This parameter can be one of the following values: 879:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_OVERSAMPLING_16 880:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_OVERSAMPLING_8 881:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 882:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 883:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetOverSampling(USART_TypeDef *USARTx, uint32_t OverSampling) 884:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 885:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** MODIFY_REG(USARTx->CR1, USART_CR1_OVER8, OverSampling); ARM GAS /tmp/ccLSPxIe.s page 443 886:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 887:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 888:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 889:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Return Oversampling mode 890:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 OVER8 LL_USART_GetOverSampling 891:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 892:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Returned value can be one of the following values: 893:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_OVERSAMPLING_16 894:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_OVERSAMPLING_8 895:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 896:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetOverSampling(const USART_TypeDef *USARTx) 897:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 898:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_OVER8)); 899:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 900:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 901:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 902:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Configure if Clock pulse of the last data bit is output to the SCLK pin or not 903:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not 904:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Synchronous mode is supported by the USARTx instance. 905:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 LBCL LL_USART_SetLastClkPulseOutput 906:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param LastBitClockPulse This parameter can be one of the following values: 908:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT 909:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_LASTCLKPULSE_OUTPUT 910:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 911:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 912:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetLastClkPulseOutput(USART_TypeDef *USARTx, uint32_t LastBitClockPul 913:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 914:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** MODIFY_REG(USARTx->CR2, USART_CR2_LBCL, LastBitClockPulse); 915:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 916:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 917:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Retrieve Clock pulse of the last data bit output configuration 919:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * (Last bit Clock pulse output to the SCLK pin or not) 920:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not 921:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Synchronous mode is supported by the USARTx instance. 922:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 LBCL LL_USART_GetLastClkPulseOutput 923:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 924:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Returned value can be one of the following values: 925:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT 926:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_LASTCLKPULSE_OUTPUT 927:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 928:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetLastClkPulseOutput(const USART_TypeDef *USARTx) 929:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 930:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_LBCL)); 931:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 932:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 933:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 934:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Select the phase of the clock output on the SCLK pin in synchronous mode 935:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not 936:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Synchronous mode is supported by the USARTx instance. 937:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 CPHA LL_USART_SetClockPhase 938:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 939:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param ClockPhase This parameter can be one of the following values: 940:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_PHASE_1EDGE 941:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_PHASE_2EDGE 942:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None ARM GAS /tmp/ccLSPxIe.s page 444 943:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 944:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetClockPhase(USART_TypeDef *USARTx, uint32_t ClockPhase) 945:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 946:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** MODIFY_REG(USARTx->CR2, USART_CR2_CPHA, ClockPhase); 947:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 948:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 949:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 950:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Return phase of the clock output on the SCLK pin in synchronous mode 951:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not 952:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Synchronous mode is supported by the USARTx instance. 953:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 CPHA LL_USART_GetClockPhase 954:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 955:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Returned value can be one of the following values: 956:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_PHASE_1EDGE 957:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_PHASE_2EDGE 958:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 959:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetClockPhase(const USART_TypeDef *USARTx) 960:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 961:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_CPHA)); 962:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 963:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 964:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 965:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Select the polarity of the clock output on the SCLK pin in synchronous mode 966:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not 967:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Synchronous mode is supported by the USARTx instance. 968:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 CPOL LL_USART_SetClockPolarity 969:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 970:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param ClockPolarity This parameter can be one of the following values: 971:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_POLARITY_LOW 972:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_POLARITY_HIGH 973:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 974:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 975:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetClockPolarity(USART_TypeDef *USARTx, uint32_t ClockPolarity) 976:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 977:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** MODIFY_REG(USARTx->CR2, USART_CR2_CPOL, ClockPolarity); 978:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 979:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 980:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 981:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Return polarity of the clock output on the SCLK pin in synchronous mode 982:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not 983:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Synchronous mode is supported by the USARTx instance. 984:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 CPOL LL_USART_GetClockPolarity 985:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 986:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Returned value can be one of the following values: 987:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_POLARITY_LOW 988:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_POLARITY_HIGH 989:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 990:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetClockPolarity(const USART_TypeDef *USARTx) 991:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 992:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_CPOL)); 993:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 994:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 995:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 996:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Configure Clock signal format (Phase Polarity and choice about output of last bit clock 997:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not 998:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Synchronous mode is supported by the USARTx instance. 999:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Call of this function is equivalent to following function call sequence : ARM GAS /tmp/ccLSPxIe.s page 445 1000:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Clock Phase configuration using @ref LL_USART_SetClockPhase() function 1001:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Clock Polarity configuration using @ref LL_USART_SetClockPolarity() function 1002:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Output of Last bit Clock pulse configuration using @ref LL_USART_SetLastClkPulseOutpu 1003:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 CPHA LL_USART_ConfigClock\n 1004:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR2 CPOL LL_USART_ConfigClock\n 1005:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR2 LBCL LL_USART_ConfigClock 1006:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1007:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param Phase This parameter can be one of the following values: 1008:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_PHASE_1EDGE 1009:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_PHASE_2EDGE 1010:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param Polarity This parameter can be one of the following values: 1011:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_POLARITY_LOW 1012:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_POLARITY_HIGH 1013:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param LBCPOutput This parameter can be one of the following values: 1014:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT 1015:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_LASTCLKPULSE_OUTPUT 1016:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 1017:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1018:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_ConfigClock(USART_TypeDef *USARTx, uint32_t Phase, uint32_t Polarity, 1019:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1020:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** MODIFY_REG(USARTx->CR2, USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_LBCL, Phase | Polarity | LBCP 1021:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1022:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1023:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1024:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Enable Clock output on SCLK pin 1025:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not 1026:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Synchronous mode is supported by the USARTx instance. 1027:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 CLKEN LL_USART_EnableSCLKOutput 1028:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1029:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 1030:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1031:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableSCLKOutput(USART_TypeDef *USARTx) 1032:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1033:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** SET_BIT(USARTx->CR2, USART_CR2_CLKEN); 1034:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1035:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1036:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1037:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Disable Clock output on SCLK pin 1038:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not 1039:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Synchronous mode is supported by the USARTx instance. 1040:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 CLKEN LL_USART_DisableSCLKOutput 1041:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1042:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 1043:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1044:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableSCLKOutput(USART_TypeDef *USARTx) 1045:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1046:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** CLEAR_BIT(USARTx->CR2, USART_CR2_CLKEN); 1047:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1048:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1049:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1050:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Indicate if Clock output on SCLK pin is enabled 1051:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not 1052:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Synchronous mode is supported by the USARTx instance. 1053:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 CLKEN LL_USART_IsEnabledSCLKOutput 1054:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1055:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). 1056:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ ARM GAS /tmp/ccLSPxIe.s page 446 1057:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledSCLKOutput(const USART_TypeDef *USARTx) 1058:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1059:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->CR2, USART_CR2_CLKEN) == (USART_CR2_CLKEN)) ? 1UL : 0UL); 1060:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1061:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1062:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1063:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Set the length of the stop bits 1064:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 STOP LL_USART_SetStopBitsLength 1065:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1066:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param StopBits This parameter can be one of the following values: 1067:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_STOPBITS_0_5 1068:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_STOPBITS_1 1069:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_STOPBITS_1_5 1070:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_STOPBITS_2 1071:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 1072:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1073:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetStopBitsLength(USART_TypeDef *USARTx, uint32_t StopBits) 1074:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1075:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** MODIFY_REG(USARTx->CR2, USART_CR2_STOP, StopBits); 1076:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1077:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1078:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1079:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Retrieve the length of the stop bits 1080:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 STOP LL_USART_GetStopBitsLength 1081:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1082:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Returned value can be one of the following values: 1083:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_STOPBITS_0_5 1084:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_STOPBITS_1 1085:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_STOPBITS_1_5 1086:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_STOPBITS_2 1087:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1088:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetStopBitsLength(const USART_TypeDef *USARTx) 1089:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1090:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_STOP)); 1091:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1092:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1093:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1094:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Configure Character frame format (Datawidth, Parity control, Stop Bits) 1095:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Call of this function is equivalent to following function call sequence : 1096:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Data Width configuration using @ref LL_USART_SetDataWidth() function 1097:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Parity Control and mode configuration using @ref LL_USART_SetParity() function 1098:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Stop bits configuration using @ref LL_USART_SetStopBitsLength() function 1099:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 PS LL_USART_ConfigCharacter\n 1100:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR1 PCE LL_USART_ConfigCharacter\n 1101:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR1 M0 LL_USART_ConfigCharacter\n 1102:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR1 M1 LL_USART_ConfigCharacter\n 1103:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR2 STOP LL_USART_ConfigCharacter 1104:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1105:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param DataWidth This parameter can be one of the following values: 1106:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_DATAWIDTH_7B 1107:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_DATAWIDTH_8B 1108:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_DATAWIDTH_9B 1109:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param Parity This parameter can be one of the following values: 1110:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_PARITY_NONE 1111:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_PARITY_EVEN 1112:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_PARITY_ODD 1113:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param StopBits This parameter can be one of the following values: ARM GAS /tmp/ccLSPxIe.s page 447 1114:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_STOPBITS_0_5 1115:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_STOPBITS_1 1116:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_STOPBITS_1_5 1117:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_STOPBITS_2 1118:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 1119:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1120:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_ConfigCharacter(USART_TypeDef *USARTx, uint32_t DataWidth, uint32_t P 1121:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** uint32_t StopBits) 1122:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1123:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** MODIFY_REG(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE | USART_CR1_M, Parity | DataWidth); 1124:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** MODIFY_REG(USARTx->CR2, USART_CR2_STOP, StopBits); 1125:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1126:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1127:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1128:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Configure TX/RX pins swapping setting. 1129:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 SWAP LL_USART_SetTXRXSwap 1130:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1131:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param SwapConfig This parameter can be one of the following values: 1132:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_TXRX_STANDARD 1133:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_TXRX_SWAPPED 1134:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 1135:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1136:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetTXRXSwap(USART_TypeDef *USARTx, uint32_t SwapConfig) 1137:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1138:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** MODIFY_REG(USARTx->CR2, USART_CR2_SWAP, SwapConfig); 1139:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1140:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1141:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1142:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Retrieve TX/RX pins swapping configuration. 1143:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 SWAP LL_USART_GetTXRXSwap 1144:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1145:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Returned value can be one of the following values: 1146:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_TXRX_STANDARD 1147:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_TXRX_SWAPPED 1148:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1149:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetTXRXSwap(const USART_TypeDef *USARTx) 1150:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1151:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_SWAP)); 1152:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1153:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1154:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1155:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Configure RX pin active level logic 1156:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 RXINV LL_USART_SetRXPinLevel 1157:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1158:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param PinInvMethod This parameter can be one of the following values: 1159:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_RXPIN_LEVEL_STANDARD 1160:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_RXPIN_LEVEL_INVERTED 1161:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 1162:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1163:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetRXPinLevel(USART_TypeDef *USARTx, uint32_t PinInvMethod) 1164:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1165:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** MODIFY_REG(USARTx->CR2, USART_CR2_RXINV, PinInvMethod); 1166:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1167:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1168:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1169:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Retrieve RX pin active level logic configuration 1170:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 RXINV LL_USART_GetRXPinLevel ARM GAS /tmp/ccLSPxIe.s page 448 1171:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1172:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Returned value can be one of the following values: 1173:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_RXPIN_LEVEL_STANDARD 1174:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_RXPIN_LEVEL_INVERTED 1175:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1176:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetRXPinLevel(const USART_TypeDef *USARTx) 1177:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1178:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_RXINV)); 1179:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1180:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1181:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1182:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Configure TX pin active level logic 1183:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 TXINV LL_USART_SetTXPinLevel 1184:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1185:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param PinInvMethod This parameter can be one of the following values: 1186:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_TXPIN_LEVEL_STANDARD 1187:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_TXPIN_LEVEL_INVERTED 1188:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 1189:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1190:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetTXPinLevel(USART_TypeDef *USARTx, uint32_t PinInvMethod) 1191:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1192:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** MODIFY_REG(USARTx->CR2, USART_CR2_TXINV, PinInvMethod); 1193:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1194:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1195:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1196:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Retrieve TX pin active level logic configuration 1197:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 TXINV LL_USART_GetTXPinLevel 1198:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1199:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Returned value can be one of the following values: 1200:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_TXPIN_LEVEL_STANDARD 1201:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_TXPIN_LEVEL_INVERTED 1202:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1203:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetTXPinLevel(const USART_TypeDef *USARTx) 1204:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1205:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_TXINV)); 1206:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1207:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1208:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1209:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Configure Binary data logic. 1210:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Allow to define how Logical data from the data register are send/received : 1211:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * either in positive/direct logic (1=H, 0=L) or in negative/inverse logic (1=L, 0=H) 1212:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 DATAINV LL_USART_SetBinaryDataLogic 1213:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1214:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param DataLogic This parameter can be one of the following values: 1215:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_BINARY_LOGIC_POSITIVE 1216:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_BINARY_LOGIC_NEGATIVE 1217:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 1218:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1219:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetBinaryDataLogic(USART_TypeDef *USARTx, uint32_t DataLogic) 1220:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1221:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** MODIFY_REG(USARTx->CR2, USART_CR2_DATAINV, DataLogic); 1222:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1223:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1224:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1225:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Retrieve Binary data configuration 1226:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 DATAINV LL_USART_GetBinaryDataLogic 1227:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance ARM GAS /tmp/ccLSPxIe.s page 449 1228:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Returned value can be one of the following values: 1229:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_BINARY_LOGIC_POSITIVE 1230:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_BINARY_LOGIC_NEGATIVE 1231:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1232:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetBinaryDataLogic(const USART_TypeDef *USARTx) 1233:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1234:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_DATAINV)); 1235:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1236:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1237:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1238:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Configure transfer bit order (either Less or Most Significant Bit First) 1239:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note MSB First means data is transmitted/received with the MSB first, following the start bi 1240:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * LSB First means data is transmitted/received with data bit 0 first, following the start 1241:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 MSBFIRST LL_USART_SetTransferBitOrder 1242:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1243:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param BitOrder This parameter can be one of the following values: 1244:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_BITORDER_LSBFIRST 1245:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_BITORDER_MSBFIRST 1246:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 1247:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1248:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetTransferBitOrder(USART_TypeDef *USARTx, uint32_t BitOrder) 1249:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1250:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** MODIFY_REG(USARTx->CR2, USART_CR2_MSBFIRST, BitOrder); 1251:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1252:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1253:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1254:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Return transfer bit order (either Less or Most Significant Bit First) 1255:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note MSB First means data is transmitted/received with the MSB first, following the start bi 1256:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * LSB First means data is transmitted/received with data bit 0 first, following the start 1257:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 MSBFIRST LL_USART_GetTransferBitOrder 1258:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1259:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Returned value can be one of the following values: 1260:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_BITORDER_LSBFIRST 1261:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_BITORDER_MSBFIRST 1262:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1263:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetTransferBitOrder(const USART_TypeDef *USARTx) 1264:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1265:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_MSBFIRST)); 1266:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1267:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1268:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1269:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Enable Auto Baud-Rate Detection 1270:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or 1271:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Auto Baud Rate detection feature is supported by the USARTx instance. 1272:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 ABREN LL_USART_EnableAutoBaudRate 1273:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1274:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 1275:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1276:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableAutoBaudRate(USART_TypeDef *USARTx) 1277:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1278:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** SET_BIT(USARTx->CR2, USART_CR2_ABREN); 1279:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1280:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1281:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1282:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Disable Auto Baud-Rate Detection 1283:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or 1284:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Auto Baud Rate detection feature is supported by the USARTx instance. ARM GAS /tmp/ccLSPxIe.s page 450 1285:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 ABREN LL_USART_DisableAutoBaudRate 1286:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1287:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 1288:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1289:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableAutoBaudRate(USART_TypeDef *USARTx) 1290:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1291:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** CLEAR_BIT(USARTx->CR2, USART_CR2_ABREN); 1292:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1293:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1294:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1295:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Indicate if Auto Baud-Rate Detection mechanism is enabled 1296:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or 1297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Auto Baud Rate detection feature is supported by the USARTx instance. 1298:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 ABREN LL_USART_IsEnabledAutoBaud 1299:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1300:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). 1301:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1302:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledAutoBaud(const USART_TypeDef *USARTx) 1303:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1304:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->CR2, USART_CR2_ABREN) == (USART_CR2_ABREN)) ? 1UL : 0UL); 1305:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1306:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1307:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1308:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Set Auto Baud-Rate mode bits 1309:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or 1310:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Auto Baud Rate detection feature is supported by the USARTx instance. 1311:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 ABRMODE LL_USART_SetAutoBaudRateMode 1312:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1313:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param AutoBaudRateMode This parameter can be one of the following values: 1314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_STARTBIT 1315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_FALLINGEDGE 1316:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME 1317:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_55_FRAME 1318:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 1319:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1320:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetAutoBaudRateMode(USART_TypeDef *USARTx, uint32_t AutoBaudRateMode) 1321:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1322:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** MODIFY_REG(USARTx->CR2, USART_CR2_ABRMODE, AutoBaudRateMode); 1323:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1324:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1325:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1326:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Return Auto Baud-Rate mode 1327:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or 1328:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Auto Baud Rate detection feature is supported by the USARTx instance. 1329:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 ABRMODE LL_USART_GetAutoBaudRateMode 1330:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1331:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Returned value can be one of the following values: 1332:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_STARTBIT 1333:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_FALLINGEDGE 1334:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME 1335:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_55_FRAME 1336:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1337:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetAutoBaudRateMode(const USART_TypeDef *USARTx) 1338:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1339:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_ABRMODE)); 1340:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1341:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ARM GAS /tmp/ccLSPxIe.s page 451 1342:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1343:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Enable Receiver Timeout 1344:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 RTOEN LL_USART_EnableRxTimeout 1345:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 1347:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1348:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableRxTimeout(USART_TypeDef *USARTx) 1349:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1350:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** SET_BIT(USARTx->CR2, USART_CR2_RTOEN); 1351:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1352:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1353:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1354:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Disable Receiver Timeout 1355:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 RTOEN LL_USART_DisableRxTimeout 1356:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1357:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 1358:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1359:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableRxTimeout(USART_TypeDef *USARTx) 1360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1361:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** CLEAR_BIT(USARTx->CR2, USART_CR2_RTOEN); 1362:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1363:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1364:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1365:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Indicate if Receiver Timeout feature is enabled 1366:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 RTOEN LL_USART_IsEnabledRxTimeout 1367:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1368:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). 1369:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledRxTimeout(const USART_TypeDef *USARTx) 1371:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->CR2, USART_CR2_RTOEN) == (USART_CR2_RTOEN)) ? 1UL : 0UL); 1373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1374:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1375:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1376:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Set Address of the USART node. 1377:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note This is used in multiprocessor communication during Mute mode or Stop mode, 1378:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * for wake up with address mark detection. 1379:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note 4bits address node is used when 4-bit Address Detection is selected in ADDM7. 1380:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * (b7-b4 should be set to 0) 1381:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * 8bits address node is used when 7-bit Address Detection is selected in ADDM7. 1382:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * (This is used in multiprocessor communication during Mute mode or Stop mode, 1383:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * for wake up with 7-bit address mark detection. 1384:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * The MSB of the character sent by the transmitter should be equal to 1. 1385:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * It may also be used for character detection during normal reception, 1386:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Mute mode inactive (for example, end of block detection in ModBus protocol). 1387:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * In this case, the whole received character (8-bit) is compared to the ADD[7:0] 1388:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * value and CMF flag is set on match) 1389:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 ADD LL_USART_ConfigNodeAddress\n 1390:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR2 ADDM7 LL_USART_ConfigNodeAddress 1391:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1392:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param AddressLen This parameter can be one of the following values: 1393:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_ADDRESS_DETECT_4B 1394:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_ADDRESS_DETECT_7B 1395:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param NodeAddress 4 or 7 bit Address of the USART node. 1396:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 1397:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1398:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_ConfigNodeAddress(USART_TypeDef *USARTx, uint32_t AddressLen, uint32_ ARM GAS /tmp/ccLSPxIe.s page 452 1399:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1400:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** MODIFY_REG(USARTx->CR2, USART_CR2_ADD | USART_CR2_ADDM7, 1401:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** (uint32_t)(AddressLen | (NodeAddress << USART_CR2_ADD_Pos))); 1402:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1403:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1404:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1405:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Return 8 bit Address of the USART node as set in ADD field of CR2. 1406:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note If 4-bit Address Detection is selected in ADDM7, 1407:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * only 4bits (b3-b0) of returned value are relevant (b31-b4 are not relevant) 1408:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * If 7-bit Address Detection is selected in ADDM7, 1409:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * only 8bits (b7-b0) of returned value are relevant (b31-b8 are not relevant) 1410:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 ADD LL_USART_GetNodeAddress 1411:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1412:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Address of the USART node (Value between Min_Data=0 and Max_Data=255) 1413:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1414:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetNodeAddress(const USART_TypeDef *USARTx) 1415:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1416:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_ADD) >> USART_CR2_ADD_Pos); 1417:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1418:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1419:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1420:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Return Length of Node Address used in Address Detection mode (7-bit or 4-bit) 1421:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 ADDM7 LL_USART_GetNodeAddressLen 1422:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1423:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Returned value can be one of the following values: 1424:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_ADDRESS_DETECT_4B 1425:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_ADDRESS_DETECT_7B 1426:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1427:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetNodeAddressLen(const USART_TypeDef *USARTx) 1428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1429:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_ADDM7)); 1430:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1431:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1432:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1433:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Enable RTS HW Flow Control 1434:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not 1435:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Hardware Flow control feature is supported by the USARTx instance. 1436:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 RTSE LL_USART_EnableRTSHWFlowCtrl 1437:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1438:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 1439:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1440:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableRTSHWFlowCtrl(USART_TypeDef *USARTx) 1441:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1442:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** SET_BIT(USARTx->CR3, USART_CR3_RTSE); 1443:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1444:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1445:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1446:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Disable RTS HW Flow Control 1447:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not 1448:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Hardware Flow control feature is supported by the USARTx instance. 1449:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 RTSE LL_USART_DisableRTSHWFlowCtrl 1450:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1451:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 1452:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1453:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableRTSHWFlowCtrl(USART_TypeDef *USARTx) 1454:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1455:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** CLEAR_BIT(USARTx->CR3, USART_CR3_RTSE); ARM GAS /tmp/ccLSPxIe.s page 453 1456:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1457:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1458:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1459:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Enable CTS HW Flow Control 1460:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not 1461:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Hardware Flow control feature is supported by the USARTx instance. 1462:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 CTSE LL_USART_EnableCTSHWFlowCtrl 1463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1464:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 1465:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1466:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableCTSHWFlowCtrl(USART_TypeDef *USARTx) 1467:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1468:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** SET_BIT(USARTx->CR3, USART_CR3_CTSE); 1469:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1470:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1471:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1472:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Disable CTS HW Flow Control 1473:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not 1474:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Hardware Flow control feature is supported by the USARTx instance. 1475:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 CTSE LL_USART_DisableCTSHWFlowCtrl 1476:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1477:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 1478:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1479:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableCTSHWFlowCtrl(USART_TypeDef *USARTx) 1480:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1481:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** CLEAR_BIT(USARTx->CR3, USART_CR3_CTSE); 1482:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1483:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1484:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1485:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Configure HW Flow Control mode (both CTS and RTS) 1486:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not 1487:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Hardware Flow control feature is supported by the USARTx instance. 1488:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 RTSE LL_USART_SetHWFlowCtrl\n 1489:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR3 CTSE LL_USART_SetHWFlowCtrl 1490:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1491:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param HardwareFlowControl This parameter can be one of the following values: 1492:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_HWCONTROL_NONE 1493:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_HWCONTROL_RTS 1494:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_HWCONTROL_CTS 1495:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_HWCONTROL_RTS_CTS 1496:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 1497:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1498:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetHWFlowCtrl(USART_TypeDef *USARTx, uint32_t HardwareFlowControl) 1499:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1500:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** MODIFY_REG(USARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE, HardwareFlowControl); 1501:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1502:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1503:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1504:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Return HW Flow Control configuration (both CTS and RTS) 1505:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not 1506:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Hardware Flow control feature is supported by the USARTx instance. 1507:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 RTSE LL_USART_GetHWFlowCtrl\n 1508:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR3 CTSE LL_USART_GetHWFlowCtrl 1509:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1510:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Returned value can be one of the following values: 1511:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_HWCONTROL_NONE 1512:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_HWCONTROL_RTS ARM GAS /tmp/ccLSPxIe.s page 454 1513:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_HWCONTROL_CTS 1514:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_HWCONTROL_RTS_CTS 1515:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1516:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetHWFlowCtrl(const USART_TypeDef *USARTx) 1517:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1518:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE)); 1519:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1520:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1521:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1522:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Enable One bit sampling method 1523:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 ONEBIT LL_USART_EnableOneBitSamp 1524:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1525:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 1526:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1527:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableOneBitSamp(USART_TypeDef *USARTx) 1528:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1529:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** SET_BIT(USARTx->CR3, USART_CR3_ONEBIT); 1530:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1531:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1532:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1533:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Disable One bit sampling method 1534:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 ONEBIT LL_USART_DisableOneBitSamp 1535:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1536:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 1537:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1538:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableOneBitSamp(USART_TypeDef *USARTx) 1539:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1540:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** CLEAR_BIT(USARTx->CR3, USART_CR3_ONEBIT); 1541:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1542:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1543:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1544:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Indicate if One bit sampling method is enabled 1545:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 ONEBIT LL_USART_IsEnabledOneBitSamp 1546:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1547:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). 1548:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1549:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledOneBitSamp(const USART_TypeDef *USARTx) 1550:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1551:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->CR3, USART_CR3_ONEBIT) == (USART_CR3_ONEBIT)) ? 1UL : 0UL); 1552:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1553:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1554:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1555:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Enable Overrun detection 1556:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 OVRDIS LL_USART_EnableOverrunDetect 1557:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1558:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 1559:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1560:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableOverrunDetect(USART_TypeDef *USARTx) 1561:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1562:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** CLEAR_BIT(USARTx->CR3, USART_CR3_OVRDIS); 1563:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1564:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1565:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1566:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Disable Overrun detection 1567:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 OVRDIS LL_USART_DisableOverrunDetect 1568:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1569:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None ARM GAS /tmp/ccLSPxIe.s page 455 1570:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1571:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableOverrunDetect(USART_TypeDef *USARTx) 1572:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1573:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** SET_BIT(USARTx->CR3, USART_CR3_OVRDIS); 1574:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1575:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1576:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1577:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Indicate if Overrun detection is enabled 1578:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 OVRDIS LL_USART_IsEnabledOverrunDetect 1579:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1580:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). 1581:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1582:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledOverrunDetect(const USART_TypeDef *USARTx) 1583:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1584:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->CR3, USART_CR3_OVRDIS) != USART_CR3_OVRDIS) ? 1UL : 0UL); 1585:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1586:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1587:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_CR1_UESM) 1588:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_CR3_WUS) 1589:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1590:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Select event type for Wake UP Interrupt Flag (WUS[1:0] bits) 1591:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not 1592:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Wake-up from Stop mode feature is supported by the USARTx instance. 1593:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 WUS LL_USART_SetWKUPType 1594:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1595:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param Type This parameter can be one of the following values: 1596:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_WAKEUP_ON_ADDRESS 1597:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_WAKEUP_ON_STARTBIT 1598:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_WAKEUP_ON_RXNE 1599:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 1600:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1601:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetWKUPType(USART_TypeDef *USARTx, uint32_t Type) 1602:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1603:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** MODIFY_REG(USARTx->CR3, USART_CR3_WUS, Type); 1604:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1605:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1606:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1607:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Return event type for Wake UP Interrupt Flag (WUS[1:0] bits) 1608:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not 1609:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Wake-up from Stop mode feature is supported by the USARTx instance. 1610:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 WUS LL_USART_GetWKUPType 1611:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1612:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Returned value can be one of the following values: 1613:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_WAKEUP_ON_ADDRESS 1614:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_WAKEUP_ON_STARTBIT 1615:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_WAKEUP_ON_RXNE 1616:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1617:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetWKUPType(const USART_TypeDef *USARTx) 1618:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1619:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_WUS)); 1620:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1621:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1622:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_CR3_WUS */ 1623:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_CR1_UESM */ 1624:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1625:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Configure USART BRR register for achieving expected Baud Rate value. 1626:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Compute and set USARTDIV value in BRR Register (full BRR content) ARM GAS /tmp/ccLSPxIe.s page 456 1627:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * according to used Peripheral Clock, Oversampling mode, and expected Baud Rate values 1628:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Peripheral clock and Baud rate values provided as function parameters should be valid 1629:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * (Baud rate value != 0) 1630:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note In case of oversampling by 16 and 8, BRR content must be greater than or equal to 16d. 1631:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll BRR BRR LL_USART_SetBaudRate 1632:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1633:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param PeriphClk Peripheral Clock 1634:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param OverSampling This parameter can be one of the following values: 1635:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_OVERSAMPLING_16 1636:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_OVERSAMPLING_8 1637:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param BaudRate Baud Rate 1638:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 1639:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1640:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetBaudRate(USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t OverS 1641:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** uint32_t BaudRate) 1642:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1643:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** uint32_t usartdiv; 1644:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** uint32_t brrtemp; 1645:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1646:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** if (OverSampling == LL_USART_OVERSAMPLING_8) 1647:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1648:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** usartdiv = (uint16_t)(__LL_USART_DIV_SAMPLING8(PeriphClk, BaudRate)); 1649:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** brrtemp = usartdiv & 0xFFF0U; 1650:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U); 1651:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** USARTx->BRR = brrtemp; 1652:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1653:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** else 1654:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1655:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** USARTx->BRR = (uint16_t)(__LL_USART_DIV_SAMPLING16(PeriphClk, BaudRate)); 1656:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1657:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1658:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1659:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1660:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Return current Baud Rate value, according to USARTDIV present in BRR register 1661:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * (full BRR content), and to used Peripheral Clock and Oversampling mode values 1662:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note In case of non-initialized or invalid value stored in BRR register, value 0 will be ret 1663:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note In case of oversampling by 16 and 8, BRR content must be greater than or equal to 16d. 1664:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll BRR BRR LL_USART_GetBaudRate 1665:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1666:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param PeriphClk Peripheral Clock 1667:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param OverSampling This parameter can be one of the following values: 1668:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_OVERSAMPLING_16 1669:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_OVERSAMPLING_8 1670:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Baud Rate 1671:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1672:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetBaudRate(const USART_TypeDef *USARTx, uint32_t PeriphClk, uint 1673:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1674:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** uint32_t usartdiv; 1675:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** uint32_t brrresult = 0x0U; 1676:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1677:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** usartdiv = USARTx->BRR; 1678:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1679:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** if (usartdiv == 0U) 1680:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1681:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* Do not perform a division by 0 */ 1682:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1683:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** else if (OverSampling == LL_USART_OVERSAMPLING_8) ARM GAS /tmp/ccLSPxIe.s page 457 1684:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1685:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** usartdiv = (uint16_t)((usartdiv & 0xFFF0U) | ((usartdiv & 0x0007U) << 1U)) ; 1686:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** if (usartdiv != 0U) 1687:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1688:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** brrresult = (PeriphClk * 2U) / usartdiv; 1689:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1690:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1691:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** else 1692:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1693:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** if ((usartdiv & 0xFFFFU) != 0U) 1694:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1695:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** brrresult = PeriphClk / usartdiv; 1696:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1697:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1698:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return (brrresult); 1699:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1700:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1701:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1702:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Set Receiver Time Out Value (expressed in nb of bits duration) 1703:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll RTOR RTO LL_USART_SetRxTimeout 1704:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1705:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param Timeout Value between Min_Data=0x00 and Max_Data=0x00FFFFFF 1706:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 1707:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1708:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetRxTimeout(USART_TypeDef *USARTx, uint32_t Timeout) 1709:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1710:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** MODIFY_REG(USARTx->RTOR, USART_RTOR_RTO, Timeout); 1711:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1712:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1713:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1714:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Get Receiver Time Out Value (expressed in nb of bits duration) 1715:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll RTOR RTO LL_USART_GetRxTimeout 1716:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1717:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Value between Min_Data=0x00 and Max_Data=0x00FFFFFF 1718:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1719:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetRxTimeout(const USART_TypeDef *USARTx) 1720:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1721:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return (uint32_t)(READ_BIT(USARTx->RTOR, USART_RTOR_RTO)); 1722:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1723:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1724:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1725:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Set Block Length value in reception 1726:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll RTOR BLEN LL_USART_SetBlockLength 1727:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1728:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param BlockLength Value between Min_Data=0x00 and Max_Data=0xFF 1729:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 1730:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1731:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetBlockLength(USART_TypeDef *USARTx, uint32_t BlockLength) 1732:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1733:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** MODIFY_REG(USARTx->RTOR, USART_RTOR_BLEN, BlockLength << USART_RTOR_BLEN_Pos); 1734:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1735:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1736:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1737:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Get Block Length value in reception 1738:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll RTOR BLEN LL_USART_GetBlockLength 1739:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1740:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Value between Min_Data=0x00 and Max_Data=0xFF ARM GAS /tmp/ccLSPxIe.s page 458 1741:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1742:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetBlockLength(const USART_TypeDef *USARTx) 1743:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1744:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return (uint32_t)(READ_BIT(USARTx->RTOR, USART_RTOR_BLEN) >> USART_RTOR_BLEN_Pos); 1745:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1746:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1747:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1748:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} 1749:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1750:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1751:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EF_Configuration_IRDA Configuration functions related to Irda feature 1752:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ 1753:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1754:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1755:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1756:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Enable IrDA mode 1757:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not 1758:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * IrDA feature is supported by the USARTx instance. 1759:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 IREN LL_USART_EnableIrda 1760:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1761:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 1762:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1763:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableIrda(USART_TypeDef *USARTx) 1764:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1765:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** SET_BIT(USARTx->CR3, USART_CR3_IREN); 1766:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1767:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1768:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1769:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Disable IrDA mode 1770:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not 1771:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * IrDA feature is supported by the USARTx instance. 1772:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 IREN LL_USART_DisableIrda 1773:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1774:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 1775:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1776:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableIrda(USART_TypeDef *USARTx) 1777:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1778:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** CLEAR_BIT(USARTx->CR3, USART_CR3_IREN); 1779:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1780:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1781:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1782:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Indicate if IrDA mode is enabled 1783:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not 1784:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * IrDA feature is supported by the USARTx instance. 1785:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 IREN LL_USART_IsEnabledIrda 1786:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1787:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). 1788:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1789:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledIrda(const USART_TypeDef *USARTx) 1790:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1791:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->CR3, USART_CR3_IREN) == (USART_CR3_IREN)) ? 1UL : 0UL); 1792:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1793:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1794:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1795:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Configure IrDA Power Mode (Normal or Low Power) 1796:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not 1797:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * IrDA feature is supported by the USARTx instance. ARM GAS /tmp/ccLSPxIe.s page 459 1798:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 IRLP LL_USART_SetIrdaPowerMode 1799:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1800:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param PowerMode This parameter can be one of the following values: 1801:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_IRDA_POWER_NORMAL 1802:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_IRDA_POWER_LOW 1803:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 1804:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1805:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetIrdaPowerMode(USART_TypeDef *USARTx, uint32_t PowerMode) 1806:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1807:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** MODIFY_REG(USARTx->CR3, USART_CR3_IRLP, PowerMode); 1808:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1809:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1810:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1811:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Retrieve IrDA Power Mode configuration (Normal or Low Power) 1812:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not 1813:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * IrDA feature is supported by the USARTx instance. 1814:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 IRLP LL_USART_GetIrdaPowerMode 1815:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1816:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Returned value can be one of the following values: 1817:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_IRDA_POWER_NORMAL 1818:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_PHASE_2EDGE 1819:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1820:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetIrdaPowerMode(const USART_TypeDef *USARTx) 1821:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1822:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_IRLP)); 1823:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1824:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1825:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1826:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Set Irda prescaler value, used for dividing the USART clock source 1827:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * to achieve the Irda Low Power frequency (8 bits value) 1828:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not 1829:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * IrDA feature is supported by the USARTx instance. 1830:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll GTPR PSC LL_USART_SetIrdaPrescaler 1831:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1832:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param PrescalerValue Value between Min_Data=0x00 and Max_Data=0xFF 1833:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 1834:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1835:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetIrdaPrescaler(USART_TypeDef *USARTx, uint32_t PrescalerValue) 1836:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1837:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** MODIFY_REG(USARTx->GTPR, USART_GTPR_PSC, (uint16_t)PrescalerValue); 1838:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1839:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1840:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1841:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Return Irda prescaler value, used for dividing the USART clock source 1842:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * to achieve the Irda Low Power frequency (8 bits value) 1843:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not 1844:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * IrDA feature is supported by the USARTx instance. 1845:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll GTPR PSC LL_USART_GetIrdaPrescaler 1846:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1847:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Irda prescaler value (Value between Min_Data=0x00 and Max_Data=0xFF) 1848:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1849:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetIrdaPrescaler(const USART_TypeDef *USARTx) 1850:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1851:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_PSC)); 1852:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1853:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1854:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** ARM GAS /tmp/ccLSPxIe.s page 460 1855:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} 1856:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1857:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1858:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EF_Configuration_Smartcard Configuration functions related to Smartcard feat 1859:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ 1860:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1861:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1862:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1863:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Enable Smartcard NACK transmission 1864:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not 1865:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Smartcard feature is supported by the USARTx instance. 1866:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 NACK LL_USART_EnableSmartcardNACK 1867:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1868:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 1869:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1870:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableSmartcardNACK(USART_TypeDef *USARTx) 1871:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1872:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** SET_BIT(USARTx->CR3, USART_CR3_NACK); 1873:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1874:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1875:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1876:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Disable Smartcard NACK transmission 1877:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not 1878:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Smartcard feature is supported by the USARTx instance. 1879:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 NACK LL_USART_DisableSmartcardNACK 1880:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1881:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 1882:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1883:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableSmartcardNACK(USART_TypeDef *USARTx) 1884:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1885:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** CLEAR_BIT(USARTx->CR3, USART_CR3_NACK); 1886:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1887:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1888:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1889:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Indicate if Smartcard NACK transmission is enabled 1890:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not 1891:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Smartcard feature is supported by the USARTx instance. 1892:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 NACK LL_USART_IsEnabledSmartcardNACK 1893:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1894:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). 1895:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1896:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcardNACK(const USART_TypeDef *USARTx) 1897:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1898:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->CR3, USART_CR3_NACK) == (USART_CR3_NACK)) ? 1UL : 0UL); 1899:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1900:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1901:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1902:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Enable Smartcard mode 1903:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not 1904:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Smartcard feature is supported by the USARTx instance. 1905:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 SCEN LL_USART_EnableSmartcard 1906:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 1908:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1909:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableSmartcard(USART_TypeDef *USARTx) 1910:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1911:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** SET_BIT(USARTx->CR3, USART_CR3_SCEN); ARM GAS /tmp/ccLSPxIe.s page 461 1912:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1913:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1914:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1915:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Disable Smartcard mode 1916:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not 1917:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Smartcard feature is supported by the USARTx instance. 1918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 SCEN LL_USART_DisableSmartcard 1919:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1920:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 1921:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1922:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableSmartcard(USART_TypeDef *USARTx) 1923:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1924:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** CLEAR_BIT(USARTx->CR3, USART_CR3_SCEN); 1925:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1926:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1927:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1928:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Indicate if Smartcard mode is enabled 1929:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not 1930:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Smartcard feature is supported by the USARTx instance. 1931:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 SCEN LL_USART_IsEnabledSmartcard 1932:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1933:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). 1934:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1935:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcard(const USART_TypeDef *USARTx) 1936:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1937:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->CR3, USART_CR3_SCEN) == (USART_CR3_SCEN)) ? 1UL : 0UL); 1938:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1939:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1940:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1941:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Set Smartcard Auto-Retry Count value (SCARCNT[2:0] bits) 1942:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not 1943:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Smartcard feature is supported by the USARTx instance. 1944:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note This bit-field specifies the number of retries in transmit and receive, in Smartcard mo 1945:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * In transmission mode, it specifies the number of automatic retransmission retries, befo 1946:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * generating a transmission error (FE bit set). 1947:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * In reception mode, it specifies the number or erroneous reception trials, before genera 1948:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * reception error (RXNE and PE bits set) 1949:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 SCARCNT LL_USART_SetSmartcardAutoRetryCount 1950:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1951:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param AutoRetryCount Value between Min_Data=0 and Max_Data=7 1952:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 1953:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1954:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetSmartcardAutoRetryCount(USART_TypeDef *USARTx, uint32_t AutoRetryC 1955:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1956:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** MODIFY_REG(USARTx->CR3, USART_CR3_SCARCNT, AutoRetryCount << USART_CR3_SCARCNT_Pos); 1957:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1958:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1959:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1960:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Return Smartcard Auto-Retry Count value (SCARCNT[2:0] bits) 1961:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not 1962:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Smartcard feature is supported by the USARTx instance. 1963:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 SCARCNT LL_USART_GetSmartcardAutoRetryCount 1964:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1965:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Smartcard Auto-Retry Count value (Value between Min_Data=0 and Max_Data=7) 1966:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1967:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetSmartcardAutoRetryCount(const USART_TypeDef *USARTx) 1968:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { ARM GAS /tmp/ccLSPxIe.s page 462 1969:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_SCARCNT) >> USART_CR3_SCARCNT_Pos); 1970:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1971:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1972:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1973:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Set Smartcard prescaler value, used for dividing the USART clock 1974:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * source to provide the SMARTCARD Clock (5 bits value) 1975:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not 1976:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Smartcard feature is supported by the USARTx instance. 1977:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll GTPR PSC LL_USART_SetSmartcardPrescaler 1978:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1979:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param PrescalerValue Value between Min_Data=0 and Max_Data=31 1980:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 1981:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1982:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetSmartcardPrescaler(USART_TypeDef *USARTx, uint32_t PrescalerValue) 1983:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1984:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** MODIFY_REG(USARTx->GTPR, USART_GTPR_PSC, (uint16_t)PrescalerValue); 1985:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 1986:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 1987:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 1988:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Return Smartcard prescaler value, used for dividing the USART clock 1989:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * source to provide the SMARTCARD Clock (5 bits value) 1990:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not 1991:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Smartcard feature is supported by the USARTx instance. 1992:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll GTPR PSC LL_USART_GetSmartcardPrescaler 1993:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 1994:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Smartcard prescaler value (Value between Min_Data=0 and Max_Data=31) 1995:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 1996:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetSmartcardPrescaler(const USART_TypeDef *USARTx) 1997:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 1998:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_PSC)); 1999:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2000:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2001:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2002:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Set Smartcard Guard time value, expressed in nb of baud clocks periods 2003:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * (GT[7:0] bits : Guard time value) 2004:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not 2005:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Smartcard feature is supported by the USARTx instance. 2006:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll GTPR GT LL_USART_SetSmartcardGuardTime 2007:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2008:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param GuardTime Value between Min_Data=0x00 and Max_Data=0xFF 2009:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 2010:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2011:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetSmartcardGuardTime(USART_TypeDef *USARTx, uint32_t GuardTime) 2012:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2013:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** MODIFY_REG(USARTx->GTPR, USART_GTPR_GT, (uint16_t)(GuardTime << USART_GTPR_GT_Pos)); 2014:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2015:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2016:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2017:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Return Smartcard Guard time value, expressed in nb of baud clocks periods 2018:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * (GT[7:0] bits : Guard time value) 2019:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not 2020:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Smartcard feature is supported by the USARTx instance. 2021:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll GTPR GT LL_USART_GetSmartcardGuardTime 2022:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2023:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Smartcard Guard time value (Value between Min_Data=0x00 and Max_Data=0xFF) 2024:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2025:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetSmartcardGuardTime(const USART_TypeDef *USARTx) ARM GAS /tmp/ccLSPxIe.s page 463 2026:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2027:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_GT) >> USART_GTPR_GT_Pos); 2028:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2029:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2030:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2031:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} 2032:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2033:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2034:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EF_Configuration_HalfDuplex Configuration functions related to Half Duplex f 2035:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ 2036:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2037:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2038:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2039:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Enable Single Wire Half-Duplex mode 2040:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not 2041:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Half-Duplex mode is supported by the USARTx instance. 2042:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 HDSEL LL_USART_EnableHalfDuplex 2043:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2044:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 2045:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2046:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableHalfDuplex(USART_TypeDef *USARTx) 2047:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2048:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** SET_BIT(USARTx->CR3, USART_CR3_HDSEL); 2049:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2050:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2051:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2052:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Disable Single Wire Half-Duplex mode 2053:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not 2054:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Half-Duplex mode is supported by the USARTx instance. 2055:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 HDSEL LL_USART_DisableHalfDuplex 2056:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2057:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 2058:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2059:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableHalfDuplex(USART_TypeDef *USARTx) 2060:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2061:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** CLEAR_BIT(USARTx->CR3, USART_CR3_HDSEL); 2062:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2063:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2064:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2065:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Indicate if Single Wire Half-Duplex mode is enabled 2066:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not 2067:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Half-Duplex mode is supported by the USARTx instance. 2068:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 HDSEL LL_USART_IsEnabledHalfDuplex 2069:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2070:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). 2071:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2072:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledHalfDuplex(const USART_TypeDef *USARTx) 2073:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2074:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->CR3, USART_CR3_HDSEL) == (USART_CR3_HDSEL)) ? 1UL : 0UL); 2075:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2076:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2077:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2078:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} 2079:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2080:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2081:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EF_Configuration_LIN Configuration functions related to LIN feature 2082:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ ARM GAS /tmp/ccLSPxIe.s page 464 2083:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2084:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2085:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2086:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Set LIN Break Detection Length 2087:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not 2088:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * LIN feature is supported by the USARTx instance. 2089:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 LBDL LL_USART_SetLINBrkDetectionLen 2090:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2091:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param LINBDLength This parameter can be one of the following values: 2092:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_LINBREAK_DETECT_10B 2093:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_LINBREAK_DETECT_11B 2094:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 2095:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2096:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetLINBrkDetectionLen(USART_TypeDef *USARTx, uint32_t LINBDLength) 2097:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2098:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** MODIFY_REG(USARTx->CR2, USART_CR2_LBDL, LINBDLength); 2099:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2100:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2101:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2102:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Return LIN Break Detection Length 2103:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not 2104:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * LIN feature is supported by the USARTx instance. 2105:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 LBDL LL_USART_GetLINBrkDetectionLen 2106:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2107:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Returned value can be one of the following values: 2108:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_LINBREAK_DETECT_10B 2109:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_LINBREAK_DETECT_11B 2110:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2111:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetLINBrkDetectionLen(const USART_TypeDef *USARTx) 2112:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2113:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_LBDL)); 2114:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2115:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2116:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2117:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Enable LIN mode 2118:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not 2119:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * LIN feature is supported by the USARTx instance. 2120:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 LINEN LL_USART_EnableLIN 2121:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2122:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 2123:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2124:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableLIN(USART_TypeDef *USARTx) 2125:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2126:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** SET_BIT(USARTx->CR2, USART_CR2_LINEN); 2127:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2128:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2129:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2130:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Disable LIN mode 2131:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not 2132:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * LIN feature is supported by the USARTx instance. 2133:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 LINEN LL_USART_DisableLIN 2134:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2135:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 2136:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2137:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableLIN(USART_TypeDef *USARTx) 2138:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2139:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** CLEAR_BIT(USARTx->CR2, USART_CR2_LINEN); ARM GAS /tmp/ccLSPxIe.s page 465 2140:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2141:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2142:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2143:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Indicate if LIN mode is enabled 2144:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not 2145:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * LIN feature is supported by the USARTx instance. 2146:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 LINEN LL_USART_IsEnabledLIN 2147:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2148:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). 2149:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2150:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledLIN(const USART_TypeDef *USARTx) 2151:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2152:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->CR2, USART_CR2_LINEN) == (USART_CR2_LINEN)) ? 1UL : 0UL); 2153:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2154:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2155:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2156:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} 2157:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2158:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2159:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EF_Configuration_DE Configuration functions related to Driver Enable feature 2160:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ 2161:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2162:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2163:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2164:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Set DEDT (Driver Enable De-Assertion Time), Time value expressed on 5 bits ([4:0] bits) 2165:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not 2166:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Driver Enable feature is supported by the USARTx instance. 2167:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 DEDT LL_USART_SetDEDeassertionTime 2168:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2169:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param Time Value between Min_Data=0 and Max_Data=31 2170:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 2171:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2172:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetDEDeassertionTime(USART_TypeDef *USARTx, uint32_t Time) 2173:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2174:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** MODIFY_REG(USARTx->CR1, USART_CR1_DEDT, Time << USART_CR1_DEDT_Pos); 2175:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2176:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2177:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2178:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Return DEDT (Driver Enable De-Assertion Time) 2179:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not 2180:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Driver Enable feature is supported by the USARTx instance. 2181:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 DEDT LL_USART_GetDEDeassertionTime 2182:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2183:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Time value expressed on 5 bits ([4:0] bits) : Value between Min_Data=0 and Max_Data=31 2184:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2185:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetDEDeassertionTime(const USART_TypeDef *USARTx) 2186:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2187:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_DEDT) >> USART_CR1_DEDT_Pos); 2188:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2189:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2190:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2191:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Set DEAT (Driver Enable Assertion Time), Time value expressed on 5 bits ([4:0] bits). 2192:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not 2193:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Driver Enable feature is supported by the USARTx instance. 2194:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 DEAT LL_USART_SetDEAssertionTime 2195:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2196:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param Time Value between Min_Data=0 and Max_Data=31 ARM GAS /tmp/ccLSPxIe.s page 466 2197:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 2198:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2199:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetDEAssertionTime(USART_TypeDef *USARTx, uint32_t Time) 2200:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2201:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** MODIFY_REG(USARTx->CR1, USART_CR1_DEAT, Time << USART_CR1_DEAT_Pos); 2202:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2203:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2204:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2205:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Return DEAT (Driver Enable Assertion Time) 2206:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not 2207:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Driver Enable feature is supported by the USARTx instance. 2208:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 DEAT LL_USART_GetDEAssertionTime 2209:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2210:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Time value expressed on 5 bits ([4:0] bits) : Value between Min_Data=0 and Max_Data=31 2211:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2212:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetDEAssertionTime(const USART_TypeDef *USARTx) 2213:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2214:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_DEAT) >> USART_CR1_DEAT_Pos); 2215:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2216:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2217:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2218:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Enable Driver Enable (DE) Mode 2219:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not 2220:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Driver Enable feature is supported by the USARTx instance. 2221:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 DEM LL_USART_EnableDEMode 2222:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2223:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 2224:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2225:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableDEMode(USART_TypeDef *USARTx) 2226:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2227:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** SET_BIT(USARTx->CR3, USART_CR3_DEM); 2228:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2229:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2230:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2231:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Disable Driver Enable (DE) Mode 2232:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not 2233:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Driver Enable feature is supported by the USARTx instance. 2234:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 DEM LL_USART_DisableDEMode 2235:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2236:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 2237:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2238:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableDEMode(USART_TypeDef *USARTx) 2239:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2240:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** CLEAR_BIT(USARTx->CR3, USART_CR3_DEM); 2241:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2242:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2243:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2244:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Indicate if Driver Enable (DE) Mode is enabled 2245:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not 2246:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Driver Enable feature is supported by the USARTx instance. 2247:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 DEM LL_USART_IsEnabledDEMode 2248:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2249:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). 2250:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2251:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledDEMode(const USART_TypeDef *USARTx) 2252:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2253:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->CR3, USART_CR3_DEM) == (USART_CR3_DEM)) ? 1UL : 0UL); ARM GAS /tmp/ccLSPxIe.s page 467 2254:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2255:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2256:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2257:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Select Driver Enable Polarity 2258:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not 2259:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Driver Enable feature is supported by the USARTx instance. 2260:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 DEP LL_USART_SetDESignalPolarity 2261:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2262:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param Polarity This parameter can be one of the following values: 2263:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_DE_POLARITY_HIGH 2264:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_DE_POLARITY_LOW 2265:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 2266:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2267:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetDESignalPolarity(USART_TypeDef *USARTx, uint32_t Polarity) 2268:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2269:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** MODIFY_REG(USARTx->CR3, USART_CR3_DEP, Polarity); 2270:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2271:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2272:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2273:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Return Driver Enable Polarity 2274:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not 2275:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Driver Enable feature is supported by the USARTx instance. 2276:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 DEP LL_USART_GetDESignalPolarity 2277:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2278:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Returned value can be one of the following values: 2279:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_DE_POLARITY_HIGH 2280:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_DE_POLARITY_LOW 2281:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2282:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetDESignalPolarity(const USART_TypeDef *USARTx) 2283:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2284:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_DEP)); 2285:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2286:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2287:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2288:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} 2289:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2290:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2291:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EF_AdvancedConfiguration Advanced Configurations services 2292:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ 2293:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2294:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2295:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2296:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Perform basic configuration of USART for enabling use in Asynchronous Mode (UART) 2297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note In UART mode, the following bits must be kept cleared: 2298:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - LINEN bit in the USART_CR2 register, 2299:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - CLKEN bit in the USART_CR2 register, 2300:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - SCEN bit in the USART_CR3 register, 2301:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - IREN bit in the USART_CR3 register, 2302:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - HDSEL bit in the USART_CR3 register. 2303:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Call of this function is equivalent to following function call sequence : 2304:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function 2305:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function 2306:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function 2307:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function 2308:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function 2309:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Other remaining configurations items related to Asynchronous Mode 2310:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * (as Baud Rate, Word length, Parity, ...) should be set using ARM GAS /tmp/ccLSPxIe.s page 468 2311:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * dedicated functions 2312:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 LINEN LL_USART_ConfigAsyncMode\n 2313:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR2 CLKEN LL_USART_ConfigAsyncMode\n 2314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR3 SCEN LL_USART_ConfigAsyncMode\n 2315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR3 IREN LL_USART_ConfigAsyncMode\n 2316:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR3 HDSEL LL_USART_ConfigAsyncMode 2317:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2318:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 2319:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2320:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_ConfigAsyncMode(USART_TypeDef *USARTx) 2321:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2322:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* In Asynchronous mode, the following bits must be kept cleared: 2323:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** - LINEN, CLKEN bits in the USART_CR2 register, 2324:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** - SCEN, IREN and HDSEL bits in the USART_CR3 register. 2325:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2326:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); 2327:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN | USART_CR3_HDSEL)); 2328:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2329:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2330:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2331:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Perform basic configuration of USART for enabling use in Synchronous Mode 2332:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note In Synchronous mode, the following bits must be kept cleared: 2333:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - LINEN bit in the USART_CR2 register, 2334:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - SCEN bit in the USART_CR3 register, 2335:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - IREN bit in the USART_CR3 register, 2336:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - HDSEL bit in the USART_CR3 register. 2337:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * This function also sets the USART in Synchronous mode. 2338:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not 2339:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Synchronous mode is supported by the USARTx instance. 2340:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Call of this function is equivalent to following function call sequence : 2341:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function 2342:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function 2343:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function 2344:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function 2345:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Set CLKEN in CR2 using @ref LL_USART_EnableSCLKOutput() function 2346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Other remaining configurations items related to Synchronous Mode 2347:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * (as Baud Rate, Word length, Parity, Clock Polarity, ...) should be set using 2348:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * dedicated functions 2349:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 LINEN LL_USART_ConfigSyncMode\n 2350:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR2 CLKEN LL_USART_ConfigSyncMode\n 2351:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR3 SCEN LL_USART_ConfigSyncMode\n 2352:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR3 IREN LL_USART_ConfigSyncMode\n 2353:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR3 HDSEL LL_USART_ConfigSyncMode 2354:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2355:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 2356:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2357:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_ConfigSyncMode(USART_TypeDef *USARTx) 2358:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2359:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* In Synchronous mode, the following bits must be kept cleared: 2360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** - LINEN bit in the USART_CR2 register, 2361:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** - SCEN, IREN and HDSEL bits in the USART_CR3 register. 2362:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2363:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN)); 2364:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN | USART_CR3_HDSEL)); 2365:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* set the UART/USART in Synchronous mode */ 2366:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** SET_BIT(USARTx->CR2, USART_CR2_CLKEN); 2367:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } ARM GAS /tmp/ccLSPxIe.s page 469 2368:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2369:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Perform basic configuration of USART for enabling use in LIN Mode 2371:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note In LIN mode, the following bits must be kept cleared: 2372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - STOP and CLKEN bits in the USART_CR2 register, 2373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - SCEN bit in the USART_CR3 register, 2374:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - IREN bit in the USART_CR3 register, 2375:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - HDSEL bit in the USART_CR3 register. 2376:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * This function also set the UART/USART in LIN mode. 2377:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not 2378:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * LIN feature is supported by the USARTx instance. 2379:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Call of this function is equivalent to following function call sequence : 2380:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function 2381:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Clear STOP in CR2 using @ref LL_USART_SetStopBitsLength() function 2382:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function 2383:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function 2384:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function 2385:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Set LINEN in CR2 using @ref LL_USART_EnableLIN() function 2386:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Other remaining configurations items related to LIN Mode 2387:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * (as Baud Rate, Word length, LIN Break Detection Length, ...) should be set using 2388:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * dedicated functions 2389:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 CLKEN LL_USART_ConfigLINMode\n 2390:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR2 STOP LL_USART_ConfigLINMode\n 2391:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR2 LINEN LL_USART_ConfigLINMode\n 2392:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR3 IREN LL_USART_ConfigLINMode\n 2393:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR3 SCEN LL_USART_ConfigLINMode\n 2394:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR3 HDSEL LL_USART_ConfigLINMode 2395:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2396:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 2397:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2398:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_ConfigLINMode(USART_TypeDef *USARTx) 2399:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2400:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* In LIN mode, the following bits must be kept cleared: 2401:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** - STOP and CLKEN bits in the USART_CR2 register, 2402:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** - IREN, SCEN and HDSEL bits in the USART_CR3 register. 2403:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2404:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** CLEAR_BIT(USARTx->CR2, (USART_CR2_CLKEN | USART_CR2_STOP)); 2405:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** CLEAR_BIT(USARTx->CR3, (USART_CR3_IREN | USART_CR3_SCEN | USART_CR3_HDSEL)); 2406:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* Set the UART/USART in LIN mode */ 2407:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** SET_BIT(USARTx->CR2, USART_CR2_LINEN); 2408:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2409:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2410:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2411:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Perform basic configuration of USART for enabling use in Half Duplex Mode 2412:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note In Half Duplex mode, the following bits must be kept cleared: 2413:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - LINEN bit in the USART_CR2 register, 2414:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - CLKEN bit in the USART_CR2 register, 2415:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - SCEN bit in the USART_CR3 register, 2416:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - IREN bit in the USART_CR3 register, 2417:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * This function also sets the UART/USART in Half Duplex mode. 2418:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not 2419:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Half-Duplex mode is supported by the USARTx instance. 2420:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Call of this function is equivalent to following function call sequence : 2421:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function 2422:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function 2423:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function 2424:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function ARM GAS /tmp/ccLSPxIe.s page 470 2425:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Set HDSEL in CR3 using @ref LL_USART_EnableHalfDuplex() function 2426:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Other remaining configurations items related to Half Duplex Mode 2427:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * (as Baud Rate, Word length, Parity, ...) should be set using 2428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * dedicated functions 2429:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 LINEN LL_USART_ConfigHalfDuplexMode\n 2430:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR2 CLKEN LL_USART_ConfigHalfDuplexMode\n 2431:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR3 HDSEL LL_USART_ConfigHalfDuplexMode\n 2432:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR3 SCEN LL_USART_ConfigHalfDuplexMode\n 2433:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR3 IREN LL_USART_ConfigHalfDuplexMode 2434:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2435:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 2436:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2437:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_ConfigHalfDuplexMode(USART_TypeDef *USARTx) 2438:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2439:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* In Half Duplex mode, the following bits must be kept cleared: 2440:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** - LINEN and CLKEN bits in the USART_CR2 register, 2441:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** - SCEN and IREN bits in the USART_CR3 register. 2442:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2443:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); 2444:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN)); 2445:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* set the UART/USART in Half Duplex mode */ 2446:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** SET_BIT(USARTx->CR3, USART_CR3_HDSEL); 2447:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2448:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2449:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2450:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Perform basic configuration of USART for enabling use in Smartcard Mode 2451:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note In Smartcard mode, the following bits must be kept cleared: 2452:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - LINEN bit in the USART_CR2 register, 2453:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - IREN bit in the USART_CR3 register, 2454:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - HDSEL bit in the USART_CR3 register. 2455:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * This function also configures Stop bits to 1.5 bits and 2456:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * sets the USART in Smartcard mode (SCEN bit). 2457:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Clock Output is also enabled (CLKEN). 2458:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not 2459:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Smartcard feature is supported by the USARTx instance. 2460:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Call of this function is equivalent to following function call sequence : 2461:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function 2462:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function 2463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function 2464:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Configure STOP in CR2 using @ref LL_USART_SetStopBitsLength() function 2465:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Set CLKEN in CR2 using @ref LL_USART_EnableSCLKOutput() function 2466:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Set SCEN in CR3 using @ref LL_USART_EnableSmartcard() function 2467:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Other remaining configurations items related to Smartcard Mode 2468:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * (as Baud Rate, Word length, Parity, ...) should be set using 2469:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * dedicated functions 2470:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 LINEN LL_USART_ConfigSmartcardMode\n 2471:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR2 STOP LL_USART_ConfigSmartcardMode\n 2472:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR2 CLKEN LL_USART_ConfigSmartcardMode\n 2473:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR3 HDSEL LL_USART_ConfigSmartcardMode\n 2474:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR3 SCEN LL_USART_ConfigSmartcardMode 2475:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2476:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 2477:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2478:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_ConfigSmartcardMode(USART_TypeDef *USARTx) 2479:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2480:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* In Smartcard mode, the following bits must be kept cleared: 2481:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** - LINEN bit in the USART_CR2 register, ARM GAS /tmp/ccLSPxIe.s page 471 2482:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** - IREN and HDSEL bits in the USART_CR3 register. 2483:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2484:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN)); 2485:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** CLEAR_BIT(USARTx->CR3, (USART_CR3_IREN | USART_CR3_HDSEL)); 2486:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* Configure Stop bits to 1.5 bits */ 2487:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* Synchronous mode is activated by default */ 2488:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** SET_BIT(USARTx->CR2, (USART_CR2_STOP_0 | USART_CR2_STOP_1 | USART_CR2_CLKEN)); 2489:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* set the UART/USART in Smartcard mode */ 2490:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** SET_BIT(USARTx->CR3, USART_CR3_SCEN); 2491:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2492:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2493:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2494:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Perform basic configuration of USART for enabling use in Irda Mode 2495:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note In IRDA mode, the following bits must be kept cleared: 2496:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - LINEN bit in the USART_CR2 register, 2497:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - STOP and CLKEN bits in the USART_CR2 register, 2498:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - SCEN bit in the USART_CR3 register, 2499:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - HDSEL bit in the USART_CR3 register. 2500:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * This function also sets the UART/USART in IRDA mode (IREN bit). 2501:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not 2502:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * IrDA feature is supported by the USARTx instance. 2503:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Call of this function is equivalent to following function call sequence : 2504:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function 2505:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function 2506:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function 2507:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function 2508:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Configure STOP in CR2 using @ref LL_USART_SetStopBitsLength() function 2509:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Set IREN in CR3 using @ref LL_USART_EnableIrda() function 2510:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Other remaining configurations items related to Irda Mode 2511:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * (as Baud Rate, Word length, Power mode, ...) should be set using 2512:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * dedicated functions 2513:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 LINEN LL_USART_ConfigIrdaMode\n 2514:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR2 CLKEN LL_USART_ConfigIrdaMode\n 2515:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR2 STOP LL_USART_ConfigIrdaMode\n 2516:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR3 SCEN LL_USART_ConfigIrdaMode\n 2517:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR3 HDSEL LL_USART_ConfigIrdaMode\n 2518:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR3 IREN LL_USART_ConfigIrdaMode 2519:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2520:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 2521:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2522:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_ConfigIrdaMode(USART_TypeDef *USARTx) 2523:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2524:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* In IRDA mode, the following bits must be kept cleared: 2525:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** - LINEN, STOP and CLKEN bits in the USART_CR2 register, 2526:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** - SCEN and HDSEL bits in the USART_CR3 register. 2527:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2528:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN | USART_CR2_STOP)); 2529:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL)); 2530:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* set the UART/USART in IRDA mode */ 2531:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** SET_BIT(USARTx->CR3, USART_CR3_IREN); 2532:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2533:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2534:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2535:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Perform basic configuration of USART for enabling use in Multi processor Mode 2536:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * (several USARTs connected in a network, one of the USARTs can be the master, 2537:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * its TX output connected to the RX inputs of the other slaves USARTs). 2538:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note In MultiProcessor mode, the following bits must be kept cleared: ARM GAS /tmp/ccLSPxIe.s page 472 2539:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - LINEN bit in the USART_CR2 register, 2540:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - CLKEN bit in the USART_CR2 register, 2541:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - SCEN bit in the USART_CR3 register, 2542:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - IREN bit in the USART_CR3 register, 2543:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - HDSEL bit in the USART_CR3 register. 2544:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Call of this function is equivalent to following function call sequence : 2545:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function 2546:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function 2547:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function 2548:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function 2549:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function 2550:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Other remaining configurations items related to Multi processor Mode 2551:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * (as Baud Rate, Wake Up Method, Node address, ...) should be set using 2552:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * dedicated functions 2553:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 LINEN LL_USART_ConfigMultiProcessMode\n 2554:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR2 CLKEN LL_USART_ConfigMultiProcessMode\n 2555:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR3 SCEN LL_USART_ConfigMultiProcessMode\n 2556:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR3 HDSEL LL_USART_ConfigMultiProcessMode\n 2557:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR3 IREN LL_USART_ConfigMultiProcessMode 2558:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2559:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 2560:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2561:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_ConfigMultiProcessMode(USART_TypeDef *USARTx) 2562:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2563:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* In Multi Processor mode, the following bits must be kept cleared: 2564:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** - LINEN and CLKEN bits in the USART_CR2 register, 2565:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** - IREN, SCEN and HDSEL bits in the USART_CR3 register. 2566:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2567:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); 2568:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN)); 2569:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2570:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2571:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2572:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} 2573:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2574:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2575:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EF_FLAG_Management FLAG_Management 2576:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ 2577:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2578:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2579:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2580:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if the USART Parity Error Flag is set or not 2581:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll ISR PE LL_USART_IsActiveFlag_PE 2582:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2583:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). 2584:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2585:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_PE(const USART_TypeDef *USARTx) 2586:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2587:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->ISR, USART_ISR_PE) == (USART_ISR_PE)) ? 1UL : 0UL); 2588:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2589:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2590:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2591:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if the USART Framing Error Flag is set or not 2592:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll ISR FE LL_USART_IsActiveFlag_FE 2593:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2594:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). 2595:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ ARM GAS /tmp/ccLSPxIe.s page 473 2596:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_FE(const USART_TypeDef *USARTx) 2597:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2598:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->ISR, USART_ISR_FE) == (USART_ISR_FE)) ? 1UL : 0UL); 2599:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2600:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2601:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2602:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if the USART Noise error detected Flag is set or not 2603:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll ISR NE LL_USART_IsActiveFlag_NE 2604:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2605:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). 2606:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2607:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_NE(const USART_TypeDef *USARTx) 2608:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2609:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->ISR, USART_ISR_NE) == (USART_ISR_NE)) ? 1UL : 0UL); 2610:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2611:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2612:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2613:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if the USART OverRun Error Flag is set or not 2614:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll ISR ORE LL_USART_IsActiveFlag_ORE 2615:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2616:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). 2617:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2618:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ORE(const USART_TypeDef *USARTx) 2619:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2620:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->ISR, USART_ISR_ORE) == (USART_ISR_ORE)) ? 1UL : 0UL); 2621:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2622:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2623:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2624:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if the USART IDLE line detected Flag is set or not 2625:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll ISR IDLE LL_USART_IsActiveFlag_IDLE 2626:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2627:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). 2628:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2629:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_IDLE(const USART_TypeDef *USARTx) 2630:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2631:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->ISR, USART_ISR_IDLE) == (USART_ISR_IDLE)) ? 1UL : 0UL); 2632:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2633:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2634:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2635:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if the USART Read Data Register Not Empty Flag is set or not 2636:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll ISR RXNE LL_USART_IsActiveFlag_RXNE 2637:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2638:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). 2639:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2640:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXNE(const USART_TypeDef *USARTx) 2641:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2642:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->ISR, USART_ISR_RXNE) == (USART_ISR_RXNE)) ? 1UL : 0UL); 2643:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2644:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2645:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2646:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if the USART Transmission Complete Flag is set or not 2647:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll ISR TC LL_USART_IsActiveFlag_TC 2648:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2649:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). 2650:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2651:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TC(const USART_TypeDef *USARTx) 2652:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { ARM GAS /tmp/ccLSPxIe.s page 474 2653:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->ISR, USART_ISR_TC) == (USART_ISR_TC)) ? 1UL : 0UL); 2654:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2655:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2656:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2657:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if the USART Transmit Data Register Empty Flag is set or not 2658:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll ISR TXE LL_USART_IsActiveFlag_TXE 2659:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2660:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). 2661:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2662:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXE(const USART_TypeDef *USARTx) 2663:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2664:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->ISR, USART_ISR_TXE) == (USART_ISR_TXE)) ? 1UL : 0UL); 2665:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2666:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2667:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2668:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if the USART LIN Break Detection Flag is set or not 2669:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not 2670:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * LIN feature is supported by the USARTx instance. 2671:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll ISR LBDF LL_USART_IsActiveFlag_LBD 2672:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2673:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). 2674:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2675:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_LBD(const USART_TypeDef *USARTx) 2676:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2677:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->ISR, USART_ISR_LBDF) == (USART_ISR_LBDF)) ? 1UL : 0UL); 2678:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2679:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2680:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2681:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if the USART CTS interrupt Flag is set or not 2682:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not 2683:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Hardware Flow control feature is supported by the USARTx instance. 2684:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll ISR CTSIF LL_USART_IsActiveFlag_nCTS 2685:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2686:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). 2687:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2688:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_nCTS(const USART_TypeDef *USARTx) 2689:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2690:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->ISR, USART_ISR_CTSIF) == (USART_ISR_CTSIF)) ? 1UL : 0UL); 2691:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2692:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2693:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2694:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if the USART CTS Flag is set or not 2695:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not 2696:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Hardware Flow control feature is supported by the USARTx instance. 2697:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll ISR CTS LL_USART_IsActiveFlag_CTS 2698:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2699:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). 2700:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2701:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_CTS(const USART_TypeDef *USARTx) 2702:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2703:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->ISR, USART_ISR_CTS) == (USART_ISR_CTS)) ? 1UL : 0UL); 2704:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2705:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2706:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2707:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if the USART Receiver Time Out Flag is set or not 2708:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll ISR RTOF LL_USART_IsActiveFlag_RTO 2709:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance ARM GAS /tmp/ccLSPxIe.s page 475 2710:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). 2711:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2712:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RTO(const USART_TypeDef *USARTx) 2713:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2714:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->ISR, USART_ISR_RTOF) == (USART_ISR_RTOF)) ? 1UL : 0UL); 2715:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2716:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2717:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2718:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if the USART End Of Block Flag is set or not 2719:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not 2720:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Smartcard feature is supported by the USARTx instance. 2721:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll ISR EOBF LL_USART_IsActiveFlag_EOB 2722:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2723:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). 2724:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2725:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_EOB(const USART_TypeDef *USARTx) 2726:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2727:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->ISR, USART_ISR_EOBF) == (USART_ISR_EOBF)) ? 1UL : 0UL); 2728:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2729:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2730:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2731:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if the USART Auto-Baud Rate Error Flag is set or not 2732:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or 2733:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Auto Baud Rate detection feature is supported by the USARTx instance. 2734:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll ISR ABRE LL_USART_IsActiveFlag_ABRE 2735:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2736:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). 2737:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2738:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ABRE(const USART_TypeDef *USARTx) 2739:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2740:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->ISR, USART_ISR_ABRE) == (USART_ISR_ABRE)) ? 1UL : 0UL); 2741:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2742:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2743:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2744:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if the USART Auto-Baud Rate Flag is set or not 2745:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or 2746:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Auto Baud Rate detection feature is supported by the USARTx instance. 2747:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll ISR ABRF LL_USART_IsActiveFlag_ABR 2748:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2749:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). 2750:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2751:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ABR(const USART_TypeDef *USARTx) 2752:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2753:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->ISR, USART_ISR_ABRF) == (USART_ISR_ABRF)) ? 1UL : 0UL); 2754:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2755:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2756:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2757:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if the USART Busy Flag is set or not 2758:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll ISR BUSY LL_USART_IsActiveFlag_BUSY 2759:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2760:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). 2761:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2762:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_BUSY(const USART_TypeDef *USARTx) 2763:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2764:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->ISR, USART_ISR_BUSY) == (USART_ISR_BUSY)) ? 1UL : 0UL); 2765:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2766:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ARM GAS /tmp/ccLSPxIe.s page 476 2767:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2768:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if the USART Character Match Flag is set or not 2769:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll ISR CMF LL_USART_IsActiveFlag_CM 2770:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2771:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). 2772:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2773:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_CM(const USART_TypeDef *USARTx) 2774:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2775:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->ISR, USART_ISR_CMF) == (USART_ISR_CMF)) ? 1UL : 0UL); 2776:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2777:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2778:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2779:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if the USART Send Break Flag is set or not 2780:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll ISR SBKF LL_USART_IsActiveFlag_SBK 2781:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2782:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). 2783:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2784:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_SBK(const USART_TypeDef *USARTx) 2785:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2786:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->ISR, USART_ISR_SBKF) == (USART_ISR_SBKF)) ? 1UL : 0UL); 2787:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2788:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2789:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2790:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if the USART Receive Wake Up from mute mode Flag is set or not 2791:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll ISR RWU LL_USART_IsActiveFlag_RWU 2792:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2793:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). 2794:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2795:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RWU(const USART_TypeDef *USARTx) 2796:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2797:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->ISR, USART_ISR_RWU) == (USART_ISR_RWU)) ? 1UL : 0UL); 2798:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2799:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2800:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_CR1_UESM) 2801:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_CR3_WUFIE) 2802:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2803:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if the USART Wake Up from stop mode Flag is set or not 2804:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not 2805:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Wake-up from Stop mode feature is supported by the USARTx instance. 2806:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll ISR WUF LL_USART_IsActiveFlag_WKUP 2807:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2808:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). 2809:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2810:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_WKUP(const USART_TypeDef *USARTx) 2811:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2812:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->ISR, USART_ISR_WUF) == (USART_ISR_WUF)) ? 1UL : 0UL); 2813:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2814:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2815:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_CR3_WUFIE */ 2816:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_CR1_UESM */ 2817:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2818:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if the USART Transmit Enable Acknowledge Flag is set or not 2819:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll ISR TEACK LL_USART_IsActiveFlag_TEACK 2820:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2821:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). 2822:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2823:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TEACK(const USART_TypeDef *USARTx) ARM GAS /tmp/ccLSPxIe.s page 477 2824:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2825:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->ISR, USART_ISR_TEACK) == (USART_ISR_TEACK)) ? 1UL : 0UL); 2826:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2827:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2828:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_ISR_REACK) 2829:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2830:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if the USART Receive Enable Acknowledge Flag is set or not 2831:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll ISR REACK LL_USART_IsActiveFlag_REACK 2832:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2833:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). 2834:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2835:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_REACK(const USART_TypeDef *USARTx) 2836:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2837:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->ISR, USART_ISR_REACK) == (USART_ISR_REACK)) ? 1UL : 0UL); 2838:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2839:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2840:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_ISR_REACK */ 2841:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_TCBGT_SUPPORT) 2842:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* Function available only on devices supporting Transmit Complete before Guard Time feature */ 2843:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2844:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if the Smartcard Transmission Complete Before Guard Time Flag is set or not 2845:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll ISR TCBGT LL_USART_IsActiveFlag_TCBGT 2846:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2847:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). 2848:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2849:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TCBGT(const USART_TypeDef *USARTx) 2850:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2851:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->ISR, USART_ISR_TCBGT) == (USART_ISR_TCBGT)) ? 1UL : 0UL); 2852:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2853:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2854:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_TCBGT_SUPPORT */ 2855:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2856:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Clear Parity Error Flag 2857:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll ICR PECF LL_USART_ClearFlag_PE 2858:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2859:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 2860:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2861:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_ClearFlag_PE(USART_TypeDef *USARTx) 2862:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2863:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** WRITE_REG(USARTx->ICR, USART_ICR_PECF); 2864:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2865:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2866:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2867:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Clear Framing Error Flag 2868:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll ICR FECF LL_USART_ClearFlag_FE 2869:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2870:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 2871:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2872:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_ClearFlag_FE(USART_TypeDef *USARTx) 2873:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2874:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** WRITE_REG(USARTx->ICR, USART_ICR_FECF); 2875:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2876:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2877:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2878:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Clear Noise Error detected Flag 2879:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll ICR NCF LL_USART_ClearFlag_NE 2880:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance ARM GAS /tmp/ccLSPxIe.s page 478 2881:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 2882:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2883:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_ClearFlag_NE(USART_TypeDef *USARTx) 2884:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2885:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** WRITE_REG(USARTx->ICR, USART_ICR_NCF); 2886:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2887:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2888:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2889:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Clear OverRun Error Flag 2890:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll ICR ORECF LL_USART_ClearFlag_ORE 2891:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2892:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 2893:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2894:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_ClearFlag_ORE(USART_TypeDef *USARTx) 2895:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2896:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** WRITE_REG(USARTx->ICR, USART_ICR_ORECF); 2897:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2898:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2899:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2900:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Clear IDLE line detected Flag 2901:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll ICR IDLECF LL_USART_ClearFlag_IDLE 2902:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2903:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 2904:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2905:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_ClearFlag_IDLE(USART_TypeDef *USARTx) 2906:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** WRITE_REG(USARTx->ICR, USART_ICR_IDLECF); 2908:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2909:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2910:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2911:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Clear Transmission Complete Flag 2912:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll ICR TCCF LL_USART_ClearFlag_TC 2913:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2914:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 2915:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2916:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_ClearFlag_TC(USART_TypeDef *USARTx) 2917:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** WRITE_REG(USARTx->ICR, USART_ICR_TCCF); 2919:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2920:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2921:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_TCBGT_SUPPORT) 2922:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* Function available only on devices supporting Transmit Complete before Guard Time feature */ 2923:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2924:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Clear Smartcard Transmission Complete Before Guard Time Flag 2925:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll ICR TCBGTCF LL_USART_ClearFlag_TCBGT 2926:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2927:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 2928:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2929:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_ClearFlag_TCBGT(USART_TypeDef *USARTx) 2930:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2931:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** WRITE_REG(USARTx->ICR, USART_ICR_TCBGTCF); 2932:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2933:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_TCBGT_SUPPORT */ 2934:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2935:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2936:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Clear LIN Break Detection Flag 2937:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not ARM GAS /tmp/ccLSPxIe.s page 479 2938:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * LIN feature is supported by the USARTx instance. 2939:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll ICR LBDCF LL_USART_ClearFlag_LBD 2940:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2941:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 2942:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2943:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_ClearFlag_LBD(USART_TypeDef *USARTx) 2944:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2945:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** WRITE_REG(USARTx->ICR, USART_ICR_LBDCF); 2946:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2947:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2948:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2949:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Clear CTS Interrupt Flag 2950:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not 2951:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Hardware Flow control feature is supported by the USARTx instance. 2952:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll ICR CTSCF LL_USART_ClearFlag_nCTS 2953:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2954:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 2955:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2956:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_ClearFlag_nCTS(USART_TypeDef *USARTx) 2957:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2958:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** WRITE_REG(USARTx->ICR, USART_ICR_CTSCF); 2959:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2960:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2961:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2962:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Clear Receiver Time Out Flag 2963:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll ICR RTOCF LL_USART_ClearFlag_RTO 2964:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2965:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 2966:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2967:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_ClearFlag_RTO(USART_TypeDef *USARTx) 2968:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2969:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** WRITE_REG(USARTx->ICR, USART_ICR_RTOCF); 2970:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2971:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2972:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2973:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Clear End Of Block Flag 2974:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not 2975:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Smartcard feature is supported by the USARTx instance. 2976:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll ICR EOBCF LL_USART_ClearFlag_EOB 2977:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2978:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 2979:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2980:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_ClearFlag_EOB(USART_TypeDef *USARTx) 2981:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2982:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** WRITE_REG(USARTx->ICR, USART_ICR_EOBCF); 2983:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 2984:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2985:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2986:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Clear Character Match Flag 2987:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll ICR CMCF LL_USART_ClearFlag_CM 2988:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 2989:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 2990:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 2991:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_ClearFlag_CM(USART_TypeDef *USARTx) 2992:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 2993:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** WRITE_REG(USARTx->ICR, USART_ICR_CMCF); 2994:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } ARM GAS /tmp/ccLSPxIe.s page 480 2995:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 2996:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_CR1_UESM) 2997:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_CR3_WUFIE) 2998:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 2999:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Clear Wake Up from stop mode Flag 3000:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not 3001:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Wake-up from Stop mode feature is supported by the USARTx instance. 3002:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll ICR WUCF LL_USART_ClearFlag_WKUP 3003:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 3004:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 3005:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3006:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_ClearFlag_WKUP(USART_TypeDef *USARTx) 3007:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 3008:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** WRITE_REG(USARTx->ICR, USART_ICR_WUCF); 3009:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 3010:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3011:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_CR3_WUFIE */ 3012:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_CR1_UESM */ 3013:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 3014:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} 3015:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3016:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3017:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EF_IT_Management IT_Management 3018:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ 3019:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3020:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3021:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 3022:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Enable IDLE Interrupt 3023:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 IDLEIE LL_USART_EnableIT_IDLE 3024:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 3025:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 3026:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3027:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableIT_IDLE(USART_TypeDef *USARTx) 3028:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 3029:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_IDLEIE); 3030:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 3031:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3032:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 3033:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Enable RX Not Empty Interrupt 3034:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 RXNEIE LL_USART_EnableIT_RXNE 3035:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 3036:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 3037:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3038:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableIT_RXNE(USART_TypeDef *USARTx) 3039:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 3040:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_RXNEIE); 3041:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 3042:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3043:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 3044:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Enable Transmission Complete Interrupt 3045:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 TCIE LL_USART_EnableIT_TC 3046:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 3047:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 3048:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3049:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableIT_TC(USART_TypeDef *USARTx) 3050:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 3051:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_TCIE); ARM GAS /tmp/ccLSPxIe.s page 481 3052:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 3053:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3054:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 3055:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Enable TX Empty Interrupt 3056:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 TXEIE LL_USART_EnableIT_TXE 3057:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 3058:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 3059:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3060:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableIT_TXE(USART_TypeDef *USARTx) 3061:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 3062:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_TXEIE); 3063:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 3064:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3065:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 3066:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Enable Parity Error Interrupt 3067:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 PEIE LL_USART_EnableIT_PE 3068:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 3069:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 3070:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3071:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableIT_PE(USART_TypeDef *USARTx) 3072:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 3073:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_PEIE); 3074:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 3075:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3076:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 3077:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Enable Character Match Interrupt 3078:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 CMIE LL_USART_EnableIT_CM 3079:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 3080:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 3081:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3082:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableIT_CM(USART_TypeDef *USARTx) 3083:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 3084:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_CMIE); 3085:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 3086:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3087:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 3088:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Enable Receiver Timeout Interrupt 3089:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 RTOIE LL_USART_EnableIT_RTO 3090:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 3091:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 3092:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3093:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableIT_RTO(USART_TypeDef *USARTx) 3094:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 3095:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_RTOIE); 3096:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 3097:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3098:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 3099:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Enable End Of Block Interrupt 3100:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not 3101:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Smartcard feature is supported by the USARTx instance. 3102:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 EOBIE LL_USART_EnableIT_EOB 3103:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 3104:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 3105:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3106:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableIT_EOB(USART_TypeDef *USARTx) 3107:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 3108:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_EOBIE); ARM GAS /tmp/ccLSPxIe.s page 482 3109:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 3110:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3111:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 3112:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Enable LIN Break Detection Interrupt 3113:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not 3114:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * LIN feature is supported by the USARTx instance. 3115:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 LBDIE LL_USART_EnableIT_LBD 3116:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 3117:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 3118:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3119:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableIT_LBD(USART_TypeDef *USARTx) 3120:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 3121:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** SET_BIT(USARTx->CR2, USART_CR2_LBDIE); 3122:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 3123:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3124:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 3125:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Enable Error Interrupt 3126:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a fram 3127:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the USARTx_ISR register). 3128:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * 0: Interrupt is inhibited 3129:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * 1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the USARTx_ISR register. 3130:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 EIE LL_USART_EnableIT_ERROR 3131:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 3132:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 3133:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3134:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableIT_ERROR(USART_TypeDef *USARTx) 3135:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 3136:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_EIE); 3137:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 3138:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3139:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 3140:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Enable CTS Interrupt 3141:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not 3142:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Hardware Flow control feature is supported by the USARTx instance. 3143:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 CTSIE LL_USART_EnableIT_CTS 3144:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 3145:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 3146:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3147:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableIT_CTS(USART_TypeDef *USARTx) 3148:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 3149:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_CTSIE); 3150:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 3151:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3152:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_CR1_UESM) 3153:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_CR3_WUFIE) 3154:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 3155:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Enable Wake Up from Stop Mode Interrupt 3156:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not 3157:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Wake-up from Stop mode feature is supported by the USARTx instance. 3158:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 WUFIE LL_USART_EnableIT_WKUP 3159:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 3160:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 3161:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3162:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableIT_WKUP(USART_TypeDef *USARTx) 3163:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 3164:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_WUFIE); 3165:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } ARM GAS /tmp/ccLSPxIe.s page 483 3166:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3167:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_CR3_WUFIE */ 3168:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_CR1_UESM */ 3169:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_TCBGT_SUPPORT) 3170:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* Function available only on devices supporting Transmit Complete before Guard Time feature */ 3171:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 3172:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Enable Smartcard Transmission Complete Before Guard Time Interrupt 3173:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not 3174:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Smartcard feature is supported by the USARTx instance. 3175:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 TCBGTIE LL_USART_EnableIT_TCBGT 3176:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 3177:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 3178:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3179:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableIT_TCBGT(USART_TypeDef *USARTx) 3180:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 3181:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_TCBGTIE); 3182:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 3183:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_TCBGT_SUPPORT */ 3184:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3185:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 3186:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Disable IDLE Interrupt 3187:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 IDLEIE LL_USART_DisableIT_IDLE 3188:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 3189:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 3190:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3191:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableIT_IDLE(USART_TypeDef *USARTx) 3192:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 3193:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_IDLEIE); 3194:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 3195:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3196:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 3197:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Disable RX Not Empty Interrupt 3198:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 RXNEIE LL_USART_DisableIT_RXNE 3199:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 3200:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 3201:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3202:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableIT_RXNE(USART_TypeDef *USARTx) 3203:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 3204:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_RXNEIE); 3205:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 3206:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3207:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 3208:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Disable Transmission Complete Interrupt 3209:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 TCIE LL_USART_DisableIT_TC 3210:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 3211:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 3212:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3213:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableIT_TC(USART_TypeDef *USARTx) 3214:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 3215:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_TCIE); 3216:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 3217:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3218:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 3219:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Disable TX Empty Interrupt 3220:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 TXEIE LL_USART_DisableIT_TXE 3221:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 3222:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None ARM GAS /tmp/ccLSPxIe.s page 484 3223:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3224:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableIT_TXE(USART_TypeDef *USARTx) 3225:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 3226:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_TXEIE); 3227:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 3228:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3229:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 3230:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Disable Parity Error Interrupt 3231:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 PEIE LL_USART_DisableIT_PE 3232:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 3233:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 3234:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3235:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableIT_PE(USART_TypeDef *USARTx) 3236:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 3237:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_PEIE); 3238:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 3239:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3240:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 3241:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Disable Character Match Interrupt 3242:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 CMIE LL_USART_DisableIT_CM 3243:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 3244:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 3245:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3246:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableIT_CM(USART_TypeDef *USARTx) 3247:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 3248:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_CMIE); 3249:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 3250:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3251:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 3252:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Disable Receiver Timeout Interrupt 3253:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 RTOIE LL_USART_DisableIT_RTO 3254:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 3255:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 3256:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3257:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableIT_RTO(USART_TypeDef *USARTx) 3258:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 3259:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_RTOIE); 3260:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 3261:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3262:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 3263:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Disable End Of Block Interrupt 3264:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not 3265:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Smartcard feature is supported by the USARTx instance. 3266:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 EOBIE LL_USART_DisableIT_EOB 3267:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 3268:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 3269:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3270:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableIT_EOB(USART_TypeDef *USARTx) 3271:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 3272:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_EOBIE); 3273:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 3274:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3275:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 3276:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Disable LIN Break Detection Interrupt 3277:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not 3278:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * LIN feature is supported by the USARTx instance. 3279:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 LBDIE LL_USART_DisableIT_LBD ARM GAS /tmp/ccLSPxIe.s page 485 3280:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 3281:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 3282:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3283:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableIT_LBD(USART_TypeDef *USARTx) 3284:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 3285:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** CLEAR_BIT(USARTx->CR2, USART_CR2_LBDIE); 3286:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 3287:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3288:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 3289:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Disable Error Interrupt 3290:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a fram 3291:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the USARTx_ISR register). 3292:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * 0: Interrupt is inhibited 3293:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * 1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the USARTx_ISR register. 3294:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 EIE LL_USART_DisableIT_ERROR 3295:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 3296:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 3297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3298:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableIT_ERROR(USART_TypeDef *USARTx) 3299:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 3300:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_EIE); 3301:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 3302:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3303:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 3304:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Disable CTS Interrupt 3305:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not 3306:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Hardware Flow control feature is supported by the USARTx instance. 3307:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 CTSIE LL_USART_DisableIT_CTS 3308:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 3309:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 3310:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3311:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableIT_CTS(USART_TypeDef *USARTx) 3312:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 3313:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_CTSIE); 3314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 3315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3316:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_CR1_UESM) 3317:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_CR3_WUFIE) 3318:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 3319:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Disable Wake Up from Stop Mode Interrupt 3320:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not 3321:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Wake-up from Stop mode feature is supported by the USARTx instance. 3322:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 WUFIE LL_USART_DisableIT_WKUP 3323:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 3324:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 3325:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3326:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableIT_WKUP(USART_TypeDef *USARTx) 3327:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 3328:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_WUFIE); 3329:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 3330:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3331:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_CR3_WUFIE */ 3332:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_CR1_UESM */ 3333:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_TCBGT_SUPPORT) 3334:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* Function available only on devices supporting Transmit Complete before Guard Time feature */ 3335:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 3336:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Disable Smartcard Transmission Complete Before Guard Time Interrupt ARM GAS /tmp/ccLSPxIe.s page 486 3337:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not 3338:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Smartcard feature is supported by the USARTx instance. 3339:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 TCBGTIE LL_USART_DisableIT_TCBGT 3340:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 3341:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 3342:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3343:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableIT_TCBGT(USART_TypeDef *USARTx) 3344:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 3345:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_TCBGTIE); 3346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 3347:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_TCBGT_SUPPORT */ 3348:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3349:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 3350:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if the USART IDLE Interrupt source is enabled or disabled. 3351:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 IDLEIE LL_USART_IsEnabledIT_IDLE 3352:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 3353:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). 3354:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3355:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_IDLE(const USART_TypeDef *USARTx) 3356:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 3357:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->CR1, USART_CR1_IDLEIE) == (USART_CR1_IDLEIE)) ? 1UL : 0UL); 3358:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 3359:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 3361:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if the USART RX Not Empty Interrupt is enabled or disabled. 3362:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 RXNEIE LL_USART_IsEnabledIT_RXNE 3363:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 3364:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). 3365:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3366:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXNE(const USART_TypeDef *USARTx) 3367:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 3368:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->CR1, USART_CR1_RXNEIE) == (USART_CR1_RXNEIE)) ? 1U : 0U); 3369:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 3370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3371:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 3372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if the USART Transmission Complete Interrupt is enabled or disabled. 3373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 TCIE LL_USART_IsEnabledIT_TC 3374:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 3375:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). 3376:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3377:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TC(const USART_TypeDef *USARTx) 3378:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 3379:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->CR1, USART_CR1_TCIE) == (USART_CR1_TCIE)) ? 1UL : 0UL); 3380:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 3381:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3382:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 3383:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if the USART TX Empty Interrupt is enabled or disabled. 3384:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 TXEIE LL_USART_IsEnabledIT_TXE 3385:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 3386:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). 3387:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3388:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXE(const USART_TypeDef *USARTx) 3389:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 3390:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->CR1, USART_CR1_TXEIE) == (USART_CR1_TXEIE)) ? 1U : 0U); 3391:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 3392:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3393:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** ARM GAS /tmp/ccLSPxIe.s page 487 3394:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if the USART Parity Error Interrupt is enabled or disabled. 3395:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 PEIE LL_USART_IsEnabledIT_PE 3396:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 3397:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). 3398:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3399:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_PE(const USART_TypeDef *USARTx) 3400:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 3401:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->CR1, USART_CR1_PEIE) == (USART_CR1_PEIE)) ? 1UL : 0UL); 3402:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 3403:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3404:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 3405:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if the USART Character Match Interrupt is enabled or disabled. 3406:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 CMIE LL_USART_IsEnabledIT_CM 3407:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 3408:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). 3409:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3410:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_CM(const USART_TypeDef *USARTx) 3411:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 3412:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->CR1, USART_CR1_CMIE) == (USART_CR1_CMIE)) ? 1UL : 0UL); 3413:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 3414:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3415:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 3416:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if the USART Receiver Timeout Interrupt is enabled or disabled. 3417:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 RTOIE LL_USART_IsEnabledIT_RTO 3418:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 3419:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). 3420:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3421:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RTO(const USART_TypeDef *USARTx) 3422:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 3423:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->CR1, USART_CR1_RTOIE) == (USART_CR1_RTOIE)) ? 1UL : 0UL); 3424:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 3425:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3426:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 3427:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if the USART End Of Block Interrupt is enabled or disabled. 3428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not 3429:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Smartcard feature is supported by the USARTx instance. 3430:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 EOBIE LL_USART_IsEnabledIT_EOB 3431:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 3432:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). 3433:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3434:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_EOB(const USART_TypeDef *USARTx) 3435:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 3436:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->CR1, USART_CR1_EOBIE) == (USART_CR1_EOBIE)) ? 1UL : 0UL); 3437:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 3438:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3439:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 3440:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if the USART LIN Break Detection Interrupt is enabled or disabled. 3441:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not 3442:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * LIN feature is supported by the USARTx instance. 3443:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 LBDIE LL_USART_IsEnabledIT_LBD 3444:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 3445:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). 3446:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3447:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_LBD(const USART_TypeDef *USARTx) 3448:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 3449:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->CR2, USART_CR2_LBDIE) == (USART_CR2_LBDIE)) ? 1UL : 0UL); 3450:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } ARM GAS /tmp/ccLSPxIe.s page 488 3451:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3452:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 3453:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if the USART Error Interrupt is enabled or disabled. 3454:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 EIE LL_USART_IsEnabledIT_ERROR 3455:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 3456:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). 3457:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3458:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_ERROR(const USART_TypeDef *USARTx) 3459:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 3460:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->CR3, USART_CR3_EIE) == (USART_CR3_EIE)) ? 1UL : 0UL); 3461:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 3462:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 3464:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if the USART CTS Interrupt is enabled or disabled. 3465:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not 3466:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Hardware Flow control feature is supported by the USARTx instance. 3467:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 CTSIE LL_USART_IsEnabledIT_CTS 3468:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 3469:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). 3470:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3471:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_CTS(const USART_TypeDef *USARTx) 3472:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 3473:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->CR3, USART_CR3_CTSIE) == (USART_CR3_CTSIE)) ? 1UL : 0UL); 3474:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 3475:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3476:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_CR1_UESM) 3477:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_CR3_WUFIE) 3478:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 3479:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if the USART Wake Up from Stop Mode Interrupt is enabled or disabled. 3480:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not 3481:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Wake-up from Stop mode feature is supported by the USARTx instance. 3482:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 WUFIE LL_USART_IsEnabledIT_WKUP 3483:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 3484:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). 3485:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3486:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_WKUP(const USART_TypeDef *USARTx) 3487:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 3488:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->CR3, USART_CR3_WUFIE) == (USART_CR3_WUFIE)) ? 1UL : 0UL); 3489:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 3490:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3491:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_CR3_WUFIE */ 3492:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_CR1_UESM */ 3493:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_TCBGT_SUPPORT) 3494:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* Function available only on devices supporting Transmit Complete before Guard Time feature */ 3495:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 3496:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if the Smartcard Transmission Complete Before Guard Time Interrupt is enabled or 3497:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not 3498:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Smartcard feature is supported by the USARTx instance. 3499:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 TCBGTIE LL_USART_IsEnabledIT_TCBGT 3500:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 3501:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). 3502:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3503:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TCBGT(const USART_TypeDef *USARTx) 3504:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 3505:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->CR3, USART_CR3_TCBGTIE) == (USART_CR3_TCBGTIE)) ? 1UL : 0UL); 3506:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 3507:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_TCBGT_SUPPORT */ ARM GAS /tmp/ccLSPxIe.s page 489 3508:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3509:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 3510:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} 3511:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3512:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3513:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EF_DMA_Management DMA_Management 3514:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ 3515:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3516:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3517:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 3518:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Enable DMA Mode for reception 3519:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 DMAR LL_USART_EnableDMAReq_RX 3520:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 3521:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 3522:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3523:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableDMAReq_RX(USART_TypeDef *USARTx) 3524:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 3525:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_DMAR); 3526:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 3527:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3528:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 3529:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Disable DMA Mode for reception 3530:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 DMAR LL_USART_DisableDMAReq_RX 3531:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 3532:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 3533:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3534:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableDMAReq_RX(USART_TypeDef *USARTx) 3535:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 3536:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_DMAR); 3537:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 3538:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3539:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 3540:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if DMA Mode is enabled for reception 3541:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 DMAR LL_USART_IsEnabledDMAReq_RX 3542:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 3543:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). 3544:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3545:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_RX(const USART_TypeDef *USARTx) 3546:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 3547:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->CR3, USART_CR3_DMAR) == (USART_CR3_DMAR)) ? 1UL : 0UL); 3548:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 3549:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3550:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 3551:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Enable DMA Mode for transmission 3552:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 DMAT LL_USART_EnableDMAReq_TX 3553:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 3554:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 3555:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3556:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableDMAReq_TX(USART_TypeDef *USARTx) 7079 .loc 7 3556 22 view .LVU2198 7080 .L381: 3557:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 3558:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_DMAT); 7081 .loc 7 3558 3 discriminator 1 view .LVU2199 7082 .LBB591: 7083 .loc 7 3558 3 discriminator 1 view .LVU2200 7084 .loc 7 3558 3 discriminator 1 view .LVU2201 ARM GAS /tmp/ccLSPxIe.s page 490 7085 .loc 7 3558 3 discriminator 1 view .LVU2202 7086 .LBB592: 7087 .LBI592: 7088 .file 8 "Drivers/CMSIS/Include/cmsis_gcc.h" 1:Drivers/CMSIS/Include/cmsis_gcc.h **** /**************************************************************************//** 2:Drivers/CMSIS/Include/cmsis_gcc.h **** * @file cmsis_gcc.h 3:Drivers/CMSIS/Include/cmsis_gcc.h **** * @brief CMSIS compiler GCC header file 4:Drivers/CMSIS/Include/cmsis_gcc.h **** * @version V5.0.4 5:Drivers/CMSIS/Include/cmsis_gcc.h **** * @date 09. April 2018 6:Drivers/CMSIS/Include/cmsis_gcc.h **** ******************************************************************************/ 7:Drivers/CMSIS/Include/cmsis_gcc.h **** /* 8:Drivers/CMSIS/Include/cmsis_gcc.h **** * Copyright (c) 2009-2018 Arm Limited. All rights reserved. 9:Drivers/CMSIS/Include/cmsis_gcc.h **** * 10:Drivers/CMSIS/Include/cmsis_gcc.h **** * SPDX-License-Identifier: Apache-2.0 11:Drivers/CMSIS/Include/cmsis_gcc.h **** * 12:Drivers/CMSIS/Include/cmsis_gcc.h **** * Licensed under the Apache License, Version 2.0 (the License); you may 13:Drivers/CMSIS/Include/cmsis_gcc.h **** * not use this file except in compliance with the License. 14:Drivers/CMSIS/Include/cmsis_gcc.h **** * You may obtain a copy of the License at 15:Drivers/CMSIS/Include/cmsis_gcc.h **** * 16:Drivers/CMSIS/Include/cmsis_gcc.h **** * www.apache.org/licenses/LICENSE-2.0 17:Drivers/CMSIS/Include/cmsis_gcc.h **** * 18:Drivers/CMSIS/Include/cmsis_gcc.h **** * Unless required by applicable law or agreed to in writing, software 19:Drivers/CMSIS/Include/cmsis_gcc.h **** * distributed under the License is distributed on an AS IS BASIS, WITHOUT 20:Drivers/CMSIS/Include/cmsis_gcc.h **** * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 21:Drivers/CMSIS/Include/cmsis_gcc.h **** * See the License for the specific language governing permissions and 22:Drivers/CMSIS/Include/cmsis_gcc.h **** * limitations under the License. 23:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 24:Drivers/CMSIS/Include/cmsis_gcc.h **** 25:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __CMSIS_GCC_H 26:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_H 27:Drivers/CMSIS/Include/cmsis_gcc.h **** 28:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ignore some GCC warnings */ 29:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push 30:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wsign-conversion" 31:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wconversion" 32:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wunused-parameter" 33:Drivers/CMSIS/Include/cmsis_gcc.h **** 34:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Fallback for __has_builtin */ 35:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __has_builtin 36:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __has_builtin(x) (0) 37:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 38:Drivers/CMSIS/Include/cmsis_gcc.h **** 39:Drivers/CMSIS/Include/cmsis_gcc.h **** /* CMSIS compiler specific defines */ 40:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __ASM 41:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __ASM __asm 42:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 43:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __INLINE 44:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __INLINE inline 45:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 46:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __STATIC_INLINE 47:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __STATIC_INLINE static inline 48:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 49:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __STATIC_FORCEINLINE 50:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline 51:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 52:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __NO_RETURN 53:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __NO_RETURN __attribute__((__noreturn__)) ARM GAS /tmp/ccLSPxIe.s page 491 54:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 55:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __USED 56:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __USED __attribute__((used)) 57:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 58:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __WEAK 59:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __WEAK __attribute__((weak)) 60:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 61:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PACKED 62:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PACKED __attribute__((packed, aligned(1))) 63:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 64:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PACKED_STRUCT 65:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) 66:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 67:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PACKED_UNION 68:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PACKED_UNION union __attribute__((packed, aligned(1))) 69:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 70:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT32 /* deprecated */ 71:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push 72:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" 73:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" 74:Drivers/CMSIS/Include/cmsis_gcc.h **** struct __attribute__((packed)) T_UINT32 { uint32_t v; }; 75:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop 76:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) 77:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 78:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT16_WRITE 79:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push 80:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" 81:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" 82:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; 83:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop 84:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))- 85:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 86:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT16_READ 87:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push 88:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" 89:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" 90:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; 91:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop 92:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(add 93:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 94:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT32_WRITE 95:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push 96:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" 97:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" 98:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; 99:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop 100:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))- 101:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 102:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT32_READ 103:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push 104:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" 105:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" 106:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; 107:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop 108:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(add 109:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 110:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __ALIGNED ARM GAS /tmp/ccLSPxIe.s page 492 111:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __ALIGNED(x) __attribute__((aligned(x))) 112:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 113:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __RESTRICT 114:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __RESTRICT __restrict 115:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 116:Drivers/CMSIS/Include/cmsis_gcc.h **** 117:Drivers/CMSIS/Include/cmsis_gcc.h **** 118:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ########################### Core Function Access ########################### */ 119:Drivers/CMSIS/Include/cmsis_gcc.h **** /** \ingroup CMSIS_Core_FunctionInterface 120:Drivers/CMSIS/Include/cmsis_gcc.h **** \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions 121:Drivers/CMSIS/Include/cmsis_gcc.h **** @{ 122:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 123:Drivers/CMSIS/Include/cmsis_gcc.h **** 124:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 125:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Enable IRQ Interrupts 126:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Enables IRQ interrupts by clearing the I-bit in the CPSR. 127:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes. 128:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 129:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __enable_irq(void) 130:Drivers/CMSIS/Include/cmsis_gcc.h **** { 131:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsie i" : : : "memory"); 132:Drivers/CMSIS/Include/cmsis_gcc.h **** } 133:Drivers/CMSIS/Include/cmsis_gcc.h **** 134:Drivers/CMSIS/Include/cmsis_gcc.h **** 135:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 136:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Disable IRQ Interrupts 137:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Disables IRQ interrupts by setting the I-bit in the CPSR. 138:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes. 139:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 140:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __disable_irq(void) 141:Drivers/CMSIS/Include/cmsis_gcc.h **** { 142:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsid i" : : : "memory"); 143:Drivers/CMSIS/Include/cmsis_gcc.h **** } 144:Drivers/CMSIS/Include/cmsis_gcc.h **** 145:Drivers/CMSIS/Include/cmsis_gcc.h **** 146:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 147:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Control Register 148:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the Control Register. 149:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Control Register value 150:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 151:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_CONTROL(void) 152:Drivers/CMSIS/Include/cmsis_gcc.h **** { 153:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 154:Drivers/CMSIS/Include/cmsis_gcc.h **** 155:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, control" : "=r" (result) ); 156:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 157:Drivers/CMSIS/Include/cmsis_gcc.h **** } 158:Drivers/CMSIS/Include/cmsis_gcc.h **** 159:Drivers/CMSIS/Include/cmsis_gcc.h **** 160:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) 161:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 162:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Control Register (non-secure) 163:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the non-secure Control Register when in secure mode. 164:Drivers/CMSIS/Include/cmsis_gcc.h **** \return non-secure Control Register value 165:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 166:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) 167:Drivers/CMSIS/Include/cmsis_gcc.h **** { ARM GAS /tmp/ccLSPxIe.s page 493 168:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 169:Drivers/CMSIS/Include/cmsis_gcc.h **** 170:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); 171:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 172:Drivers/CMSIS/Include/cmsis_gcc.h **** } 173:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 174:Drivers/CMSIS/Include/cmsis_gcc.h **** 175:Drivers/CMSIS/Include/cmsis_gcc.h **** 176:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 177:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Control Register 178:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Writes the given value to the Control Register. 179:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] control Control Register value to set 180:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 181:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) 182:Drivers/CMSIS/Include/cmsis_gcc.h **** { 183:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); 184:Drivers/CMSIS/Include/cmsis_gcc.h **** } 185:Drivers/CMSIS/Include/cmsis_gcc.h **** 186:Drivers/CMSIS/Include/cmsis_gcc.h **** 187:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) 188:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 189:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Control Register (non-secure) 190:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Writes the given value to the non-secure Control Register when in secure state. 191:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] control Control Register value to set 192:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 193:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) 194:Drivers/CMSIS/Include/cmsis_gcc.h **** { 195:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); 196:Drivers/CMSIS/Include/cmsis_gcc.h **** } 197:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 198:Drivers/CMSIS/Include/cmsis_gcc.h **** 199:Drivers/CMSIS/Include/cmsis_gcc.h **** 200:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 201:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get IPSR Register 202:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the IPSR Register. 203:Drivers/CMSIS/Include/cmsis_gcc.h **** \return IPSR Register value 204:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 205:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_IPSR(void) 206:Drivers/CMSIS/Include/cmsis_gcc.h **** { 207:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 208:Drivers/CMSIS/Include/cmsis_gcc.h **** 209:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); 210:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 211:Drivers/CMSIS/Include/cmsis_gcc.h **** } 212:Drivers/CMSIS/Include/cmsis_gcc.h **** 213:Drivers/CMSIS/Include/cmsis_gcc.h **** 214:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 215:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get APSR Register 216:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the APSR Register. 217:Drivers/CMSIS/Include/cmsis_gcc.h **** \return APSR Register value 218:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 219:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_APSR(void) 220:Drivers/CMSIS/Include/cmsis_gcc.h **** { 221:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 222:Drivers/CMSIS/Include/cmsis_gcc.h **** 223:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, apsr" : "=r" (result) ); 224:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); ARM GAS /tmp/ccLSPxIe.s page 494 225:Drivers/CMSIS/Include/cmsis_gcc.h **** } 226:Drivers/CMSIS/Include/cmsis_gcc.h **** 227:Drivers/CMSIS/Include/cmsis_gcc.h **** 228:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 229:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get xPSR Register 230:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the xPSR Register. 231:Drivers/CMSIS/Include/cmsis_gcc.h **** \return xPSR Register value 232:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 233:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_xPSR(void) 234:Drivers/CMSIS/Include/cmsis_gcc.h **** { 235:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 236:Drivers/CMSIS/Include/cmsis_gcc.h **** 237:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); 238:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 239:Drivers/CMSIS/Include/cmsis_gcc.h **** } 240:Drivers/CMSIS/Include/cmsis_gcc.h **** 241:Drivers/CMSIS/Include/cmsis_gcc.h **** 242:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 243:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Process Stack Pointer 244:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Process Stack Pointer (PSP). 245:Drivers/CMSIS/Include/cmsis_gcc.h **** \return PSP Register value 246:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 247:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_PSP(void) 248:Drivers/CMSIS/Include/cmsis_gcc.h **** { 249:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 250:Drivers/CMSIS/Include/cmsis_gcc.h **** 251:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, psp" : "=r" (result) ); 252:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 253:Drivers/CMSIS/Include/cmsis_gcc.h **** } 254:Drivers/CMSIS/Include/cmsis_gcc.h **** 255:Drivers/CMSIS/Include/cmsis_gcc.h **** 256:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) 257:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 258:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Process Stack Pointer (non-secure) 259:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure s 260:Drivers/CMSIS/Include/cmsis_gcc.h **** \return PSP Register value 261:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 262:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) 263:Drivers/CMSIS/Include/cmsis_gcc.h **** { 264:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 265:Drivers/CMSIS/Include/cmsis_gcc.h **** 266:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); 267:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 268:Drivers/CMSIS/Include/cmsis_gcc.h **** } 269:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 270:Drivers/CMSIS/Include/cmsis_gcc.h **** 271:Drivers/CMSIS/Include/cmsis_gcc.h **** 272:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 273:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Process Stack Pointer 274:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Process Stack Pointer (PSP). 275:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfProcStack Process Stack Pointer value to set 276:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 277:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) 278:Drivers/CMSIS/Include/cmsis_gcc.h **** { 279:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); 280:Drivers/CMSIS/Include/cmsis_gcc.h **** } 281:Drivers/CMSIS/Include/cmsis_gcc.h **** ARM GAS /tmp/ccLSPxIe.s page 495 282:Drivers/CMSIS/Include/cmsis_gcc.h **** 283:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) 284:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 285:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Process Stack Pointer (non-secure) 286:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure sta 287:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfProcStack Process Stack Pointer value to set 288:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 289:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) 290:Drivers/CMSIS/Include/cmsis_gcc.h **** { 291:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); 292:Drivers/CMSIS/Include/cmsis_gcc.h **** } 293:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 294:Drivers/CMSIS/Include/cmsis_gcc.h **** 295:Drivers/CMSIS/Include/cmsis_gcc.h **** 296:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 297:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Main Stack Pointer 298:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Main Stack Pointer (MSP). 299:Drivers/CMSIS/Include/cmsis_gcc.h **** \return MSP Register value 300:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 301:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_MSP(void) 302:Drivers/CMSIS/Include/cmsis_gcc.h **** { 303:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 304:Drivers/CMSIS/Include/cmsis_gcc.h **** 305:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, msp" : "=r" (result) ); 306:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 307:Drivers/CMSIS/Include/cmsis_gcc.h **** } 308:Drivers/CMSIS/Include/cmsis_gcc.h **** 309:Drivers/CMSIS/Include/cmsis_gcc.h **** 310:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) 311:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 312:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Main Stack Pointer (non-secure) 313:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure stat 314:Drivers/CMSIS/Include/cmsis_gcc.h **** \return MSP Register value 315:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 316:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) 317:Drivers/CMSIS/Include/cmsis_gcc.h **** { 318:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 319:Drivers/CMSIS/Include/cmsis_gcc.h **** 320:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); 321:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 322:Drivers/CMSIS/Include/cmsis_gcc.h **** } 323:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 324:Drivers/CMSIS/Include/cmsis_gcc.h **** 325:Drivers/CMSIS/Include/cmsis_gcc.h **** 326:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 327:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Main Stack Pointer 328:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Main Stack Pointer (MSP). 329:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfMainStack Main Stack Pointer value to set 330:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 331:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) 332:Drivers/CMSIS/Include/cmsis_gcc.h **** { 333:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); 334:Drivers/CMSIS/Include/cmsis_gcc.h **** } 335:Drivers/CMSIS/Include/cmsis_gcc.h **** 336:Drivers/CMSIS/Include/cmsis_gcc.h **** 337:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) 338:Drivers/CMSIS/Include/cmsis_gcc.h **** /** ARM GAS /tmp/ccLSPxIe.s page 496 339:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Main Stack Pointer (non-secure) 340:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. 341:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfMainStack Main Stack Pointer value to set 342:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 343:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) 344:Drivers/CMSIS/Include/cmsis_gcc.h **** { 345:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); 346:Drivers/CMSIS/Include/cmsis_gcc.h **** } 347:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 348:Drivers/CMSIS/Include/cmsis_gcc.h **** 349:Drivers/CMSIS/Include/cmsis_gcc.h **** 350:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) 351:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 352:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Stack Pointer (non-secure) 353:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. 354:Drivers/CMSIS/Include/cmsis_gcc.h **** \return SP Register value 355:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 356:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) 357:Drivers/CMSIS/Include/cmsis_gcc.h **** { 358:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 359:Drivers/CMSIS/Include/cmsis_gcc.h **** 360:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); 361:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 362:Drivers/CMSIS/Include/cmsis_gcc.h **** } 363:Drivers/CMSIS/Include/cmsis_gcc.h **** 364:Drivers/CMSIS/Include/cmsis_gcc.h **** 365:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 366:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Stack Pointer (non-secure) 367:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. 368:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfStack Stack Pointer value to set 369:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 370:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) 371:Drivers/CMSIS/Include/cmsis_gcc.h **** { 372:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); 373:Drivers/CMSIS/Include/cmsis_gcc.h **** } 374:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 375:Drivers/CMSIS/Include/cmsis_gcc.h **** 376:Drivers/CMSIS/Include/cmsis_gcc.h **** 377:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 378:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Priority Mask 379:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current state of the priority mask bit from the Priority Mask Register. 380:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Priority Mask value 381:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 382:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) 383:Drivers/CMSIS/Include/cmsis_gcc.h **** { 384:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 385:Drivers/CMSIS/Include/cmsis_gcc.h **** 386:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); 387:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 388:Drivers/CMSIS/Include/cmsis_gcc.h **** } 389:Drivers/CMSIS/Include/cmsis_gcc.h **** 390:Drivers/CMSIS/Include/cmsis_gcc.h **** 391:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) 392:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 393:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Priority Mask (non-secure) 394:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current state of the non-secure priority mask bit from the Priority Mask Reg 395:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Priority Mask value ARM GAS /tmp/ccLSPxIe.s page 497 396:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 397:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) 398:Drivers/CMSIS/Include/cmsis_gcc.h **** { 399:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 400:Drivers/CMSIS/Include/cmsis_gcc.h **** 401:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, primask_ns" : "=r" (result) :: "memory"); 402:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 403:Drivers/CMSIS/Include/cmsis_gcc.h **** } 404:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 405:Drivers/CMSIS/Include/cmsis_gcc.h **** 406:Drivers/CMSIS/Include/cmsis_gcc.h **** 407:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 408:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Priority Mask 409:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Priority Mask Register. 410:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] priMask Priority Mask 411:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 412:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) 413:Drivers/CMSIS/Include/cmsis_gcc.h **** { 414:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); 415:Drivers/CMSIS/Include/cmsis_gcc.h **** } 416:Drivers/CMSIS/Include/cmsis_gcc.h **** 417:Drivers/CMSIS/Include/cmsis_gcc.h **** 418:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) 419:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 420:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Priority Mask (non-secure) 421:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Priority Mask Register when in secure state. 422:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] priMask Priority Mask 423:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 424:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) 425:Drivers/CMSIS/Include/cmsis_gcc.h **** { 426:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); 427:Drivers/CMSIS/Include/cmsis_gcc.h **** } 428:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 429:Drivers/CMSIS/Include/cmsis_gcc.h **** 430:Drivers/CMSIS/Include/cmsis_gcc.h **** 431:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ 432:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ 433:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) 434:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 435:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Enable FIQ 436:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Enables FIQ interrupts by clearing the F-bit in the CPSR. 437:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes. 438:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 439:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __enable_fault_irq(void) 440:Drivers/CMSIS/Include/cmsis_gcc.h **** { 441:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsie f" : : : "memory"); 442:Drivers/CMSIS/Include/cmsis_gcc.h **** } 443:Drivers/CMSIS/Include/cmsis_gcc.h **** 444:Drivers/CMSIS/Include/cmsis_gcc.h **** 445:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 446:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Disable FIQ 447:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Disables FIQ interrupts by setting the F-bit in the CPSR. 448:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes. 449:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 450:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __disable_fault_irq(void) 451:Drivers/CMSIS/Include/cmsis_gcc.h **** { 452:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsid f" : : : "memory"); ARM GAS /tmp/ccLSPxIe.s page 498 453:Drivers/CMSIS/Include/cmsis_gcc.h **** } 454:Drivers/CMSIS/Include/cmsis_gcc.h **** 455:Drivers/CMSIS/Include/cmsis_gcc.h **** 456:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 457:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Base Priority 458:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Base Priority register. 459:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Base Priority register value 460:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 461:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) 462:Drivers/CMSIS/Include/cmsis_gcc.h **** { 463:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 464:Drivers/CMSIS/Include/cmsis_gcc.h **** 465:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, basepri" : "=r" (result) ); 466:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 467:Drivers/CMSIS/Include/cmsis_gcc.h **** } 468:Drivers/CMSIS/Include/cmsis_gcc.h **** 469:Drivers/CMSIS/Include/cmsis_gcc.h **** 470:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) 471:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 472:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Base Priority (non-secure) 473:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Base Priority register when in secure state. 474:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Base Priority register value 475:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 476:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) 477:Drivers/CMSIS/Include/cmsis_gcc.h **** { 478:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 479:Drivers/CMSIS/Include/cmsis_gcc.h **** 480:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); 481:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 482:Drivers/CMSIS/Include/cmsis_gcc.h **** } 483:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 484:Drivers/CMSIS/Include/cmsis_gcc.h **** 485:Drivers/CMSIS/Include/cmsis_gcc.h **** 486:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 487:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Base Priority 488:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Base Priority register. 489:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] basePri Base Priority value to set 490:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 491:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) 492:Drivers/CMSIS/Include/cmsis_gcc.h **** { 493:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); 494:Drivers/CMSIS/Include/cmsis_gcc.h **** } 495:Drivers/CMSIS/Include/cmsis_gcc.h **** 496:Drivers/CMSIS/Include/cmsis_gcc.h **** 497:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) 498:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 499:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Base Priority (non-secure) 500:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Base Priority register when in secure state. 501:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] basePri Base Priority value to set 502:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 503:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) 504:Drivers/CMSIS/Include/cmsis_gcc.h **** { 505:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); 506:Drivers/CMSIS/Include/cmsis_gcc.h **** } 507:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 508:Drivers/CMSIS/Include/cmsis_gcc.h **** 509:Drivers/CMSIS/Include/cmsis_gcc.h **** ARM GAS /tmp/ccLSPxIe.s page 499 510:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 511:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Base Priority with condition 512:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Base Priority register only if BASEPRI masking is disable 513:Drivers/CMSIS/Include/cmsis_gcc.h **** or the new value increases the BASEPRI priority level. 514:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] basePri Base Priority value to set 515:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 516:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) 517:Drivers/CMSIS/Include/cmsis_gcc.h **** { 518:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); 519:Drivers/CMSIS/Include/cmsis_gcc.h **** } 520:Drivers/CMSIS/Include/cmsis_gcc.h **** 521:Drivers/CMSIS/Include/cmsis_gcc.h **** 522:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 523:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Fault Mask 524:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Fault Mask register. 525:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Fault Mask register value 526:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 527:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) 528:Drivers/CMSIS/Include/cmsis_gcc.h **** { 529:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 530:Drivers/CMSIS/Include/cmsis_gcc.h **** 531:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); 532:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 533:Drivers/CMSIS/Include/cmsis_gcc.h **** } 534:Drivers/CMSIS/Include/cmsis_gcc.h **** 535:Drivers/CMSIS/Include/cmsis_gcc.h **** 536:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) 537:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 538:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Fault Mask (non-secure) 539:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Fault Mask register when in secure state. 540:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Fault Mask register value 541:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 542:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) 543:Drivers/CMSIS/Include/cmsis_gcc.h **** { 544:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 545:Drivers/CMSIS/Include/cmsis_gcc.h **** 546:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); 547:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 548:Drivers/CMSIS/Include/cmsis_gcc.h **** } 549:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 550:Drivers/CMSIS/Include/cmsis_gcc.h **** 551:Drivers/CMSIS/Include/cmsis_gcc.h **** 552:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 553:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Fault Mask 554:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Fault Mask register. 555:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] faultMask Fault Mask value to set 556:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 557:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) 558:Drivers/CMSIS/Include/cmsis_gcc.h **** { 559:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); 560:Drivers/CMSIS/Include/cmsis_gcc.h **** } 561:Drivers/CMSIS/Include/cmsis_gcc.h **** 562:Drivers/CMSIS/Include/cmsis_gcc.h **** 563:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) 564:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 565:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Fault Mask (non-secure) 566:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Fault Mask register when in secure state. ARM GAS /tmp/ccLSPxIe.s page 500 567:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] faultMask Fault Mask value to set 568:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 569:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) 570:Drivers/CMSIS/Include/cmsis_gcc.h **** { 571:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); 572:Drivers/CMSIS/Include/cmsis_gcc.h **** } 573:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 574:Drivers/CMSIS/Include/cmsis_gcc.h **** 575:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ 576:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ 577:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ 578:Drivers/CMSIS/Include/cmsis_gcc.h **** 579:Drivers/CMSIS/Include/cmsis_gcc.h **** 580:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ 581:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) 582:Drivers/CMSIS/Include/cmsis_gcc.h **** 583:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 584:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Process Stack Pointer Limit 585:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure 586:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence zero is returned always in non-secure 587:Drivers/CMSIS/Include/cmsis_gcc.h **** mode. 588:Drivers/CMSIS/Include/cmsis_gcc.h **** 589:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). 590:Drivers/CMSIS/Include/cmsis_gcc.h **** \return PSPLIM Register value 591:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 592:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) 593:Drivers/CMSIS/Include/cmsis_gcc.h **** { 594:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ 595:Drivers/CMSIS/Include/cmsis_gcc.h **** (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) 596:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure PSPLIM is RAZ/WI 597:Drivers/CMSIS/Include/cmsis_gcc.h **** return 0U; 598:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 599:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 600:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, psplim" : "=r" (result) ); 601:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; 602:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 603:Drivers/CMSIS/Include/cmsis_gcc.h **** } 604:Drivers/CMSIS/Include/cmsis_gcc.h **** 605:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) 606:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 607:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Process Stack Pointer Limit (non-secure) 608:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure 609:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence zero is returned always. 610:Drivers/CMSIS/Include/cmsis_gcc.h **** 611:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in 612:Drivers/CMSIS/Include/cmsis_gcc.h **** \return PSPLIM Register value 613:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 614:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) 615:Drivers/CMSIS/Include/cmsis_gcc.h **** { 616:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) 617:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure PSPLIM is RAZ/WI 618:Drivers/CMSIS/Include/cmsis_gcc.h **** return 0U; 619:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 620:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 621:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); 622:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; 623:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif ARM GAS /tmp/ccLSPxIe.s page 501 624:Drivers/CMSIS/Include/cmsis_gcc.h **** } 625:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 626:Drivers/CMSIS/Include/cmsis_gcc.h **** 627:Drivers/CMSIS/Include/cmsis_gcc.h **** 628:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 629:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Process Stack Pointer Limit 630:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure 631:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence the write is silently ignored in non-secure 632:Drivers/CMSIS/Include/cmsis_gcc.h **** mode. 633:Drivers/CMSIS/Include/cmsis_gcc.h **** 634:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). 635:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set 636:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 637:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) 638:Drivers/CMSIS/Include/cmsis_gcc.h **** { 639:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ 640:Drivers/CMSIS/Include/cmsis_gcc.h **** (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) 641:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure PSPLIM is RAZ/WI 642:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)ProcStackPtrLimit; 643:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 644:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); 645:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 646:Drivers/CMSIS/Include/cmsis_gcc.h **** } 647:Drivers/CMSIS/Include/cmsis_gcc.h **** 648:Drivers/CMSIS/Include/cmsis_gcc.h **** 649:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) 650:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 651:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Process Stack Pointer (non-secure) 652:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure 653:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence the write is silently ignored. 654:Drivers/CMSIS/Include/cmsis_gcc.h **** 655:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in s 656:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set 657:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 658:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) 659:Drivers/CMSIS/Include/cmsis_gcc.h **** { 660:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) 661:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure PSPLIM is RAZ/WI 662:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)ProcStackPtrLimit; 663:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 664:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); 665:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 666:Drivers/CMSIS/Include/cmsis_gcc.h **** } 667:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 668:Drivers/CMSIS/Include/cmsis_gcc.h **** 669:Drivers/CMSIS/Include/cmsis_gcc.h **** 670:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 671:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Main Stack Pointer Limit 672:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure 673:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence zero is returned always in non-secure 674:Drivers/CMSIS/Include/cmsis_gcc.h **** mode. 675:Drivers/CMSIS/Include/cmsis_gcc.h **** 676:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). 677:Drivers/CMSIS/Include/cmsis_gcc.h **** \return MSPLIM Register value 678:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 679:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) 680:Drivers/CMSIS/Include/cmsis_gcc.h **** { ARM GAS /tmp/ccLSPxIe.s page 502 681:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ 682:Drivers/CMSIS/Include/cmsis_gcc.h **** (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) 683:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure MSPLIM is RAZ/WI 684:Drivers/CMSIS/Include/cmsis_gcc.h **** return 0U; 685:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 686:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 687:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, msplim" : "=r" (result) ); 688:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; 689:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 690:Drivers/CMSIS/Include/cmsis_gcc.h **** } 691:Drivers/CMSIS/Include/cmsis_gcc.h **** 692:Drivers/CMSIS/Include/cmsis_gcc.h **** 693:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) 694:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 695:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Main Stack Pointer Limit (non-secure) 696:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure 697:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence zero is returned always. 698:Drivers/CMSIS/Include/cmsis_gcc.h **** 699:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in sec 700:Drivers/CMSIS/Include/cmsis_gcc.h **** \return MSPLIM Register value 701:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 702:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) 703:Drivers/CMSIS/Include/cmsis_gcc.h **** { 704:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) 705:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure MSPLIM is RAZ/WI 706:Drivers/CMSIS/Include/cmsis_gcc.h **** return 0U; 707:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 708:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 709:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); 710:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; 711:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 712:Drivers/CMSIS/Include/cmsis_gcc.h **** } 713:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 714:Drivers/CMSIS/Include/cmsis_gcc.h **** 715:Drivers/CMSIS/Include/cmsis_gcc.h **** 716:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 717:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Main Stack Pointer Limit 718:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure 719:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence the write is silently ignored in non-secure 720:Drivers/CMSIS/Include/cmsis_gcc.h **** mode. 721:Drivers/CMSIS/Include/cmsis_gcc.h **** 722:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). 723:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set 724:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 725:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) 726:Drivers/CMSIS/Include/cmsis_gcc.h **** { 727:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ 728:Drivers/CMSIS/Include/cmsis_gcc.h **** (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) 729:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure MSPLIM is RAZ/WI 730:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)MainStackPtrLimit; 731:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 732:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); 733:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 734:Drivers/CMSIS/Include/cmsis_gcc.h **** } 735:Drivers/CMSIS/Include/cmsis_gcc.h **** 736:Drivers/CMSIS/Include/cmsis_gcc.h **** 737:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) ARM GAS /tmp/ccLSPxIe.s page 503 738:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 739:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Main Stack Pointer Limit (non-secure) 740:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure 741:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence the write is silently ignored. 742:Drivers/CMSIS/Include/cmsis_gcc.h **** 743:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secu 744:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] MainStackPtrLimit Main Stack Pointer value to set 745:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 746:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) 747:Drivers/CMSIS/Include/cmsis_gcc.h **** { 748:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) 749:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure MSPLIM is RAZ/WI 750:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)MainStackPtrLimit; 751:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 752:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); 753:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 754:Drivers/CMSIS/Include/cmsis_gcc.h **** } 755:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 756:Drivers/CMSIS/Include/cmsis_gcc.h **** 757:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ 758:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ 759:Drivers/CMSIS/Include/cmsis_gcc.h **** 760:Drivers/CMSIS/Include/cmsis_gcc.h **** 761:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 762:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get FPSCR 763:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Floating Point Status/Control register. 764:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Floating Point Status/Control register value 765:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 766:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_FPSCR(void) 767:Drivers/CMSIS/Include/cmsis_gcc.h **** { 768:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ 769:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) 770:Drivers/CMSIS/Include/cmsis_gcc.h **** #if __has_builtin(__builtin_arm_get_fpscr) 771:Drivers/CMSIS/Include/cmsis_gcc.h **** // Re-enable using built-in when GCC has been fixed 772:Drivers/CMSIS/Include/cmsis_gcc.h **** // || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) 773:Drivers/CMSIS/Include/cmsis_gcc.h **** /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ 774:Drivers/CMSIS/Include/cmsis_gcc.h **** return __builtin_arm_get_fpscr(); 775:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 776:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 777:Drivers/CMSIS/Include/cmsis_gcc.h **** 778:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); 779:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 780:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 781:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 782:Drivers/CMSIS/Include/cmsis_gcc.h **** return(0U); 783:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 784:Drivers/CMSIS/Include/cmsis_gcc.h **** } 785:Drivers/CMSIS/Include/cmsis_gcc.h **** 786:Drivers/CMSIS/Include/cmsis_gcc.h **** 787:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 788:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set FPSCR 789:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Floating Point Status/Control register. 790:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] fpscr Floating Point Status/Control value to set 791:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 792:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) 793:Drivers/CMSIS/Include/cmsis_gcc.h **** { 794:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ ARM GAS /tmp/ccLSPxIe.s page 504 795:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) 796:Drivers/CMSIS/Include/cmsis_gcc.h **** #if __has_builtin(__builtin_arm_set_fpscr) 797:Drivers/CMSIS/Include/cmsis_gcc.h **** // Re-enable using built-in when GCC has been fixed 798:Drivers/CMSIS/Include/cmsis_gcc.h **** // || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) 799:Drivers/CMSIS/Include/cmsis_gcc.h **** /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ 800:Drivers/CMSIS/Include/cmsis_gcc.h **** __builtin_arm_set_fpscr(fpscr); 801:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 802:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory"); 803:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 804:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 805:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)fpscr; 806:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 807:Drivers/CMSIS/Include/cmsis_gcc.h **** } 808:Drivers/CMSIS/Include/cmsis_gcc.h **** 809:Drivers/CMSIS/Include/cmsis_gcc.h **** 810:Drivers/CMSIS/Include/cmsis_gcc.h **** /*@} end of CMSIS_Core_RegAccFunctions */ 811:Drivers/CMSIS/Include/cmsis_gcc.h **** 812:Drivers/CMSIS/Include/cmsis_gcc.h **** 813:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ########################## Core Instruction Access ######################### */ 814:Drivers/CMSIS/Include/cmsis_gcc.h **** /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface 815:Drivers/CMSIS/Include/cmsis_gcc.h **** Access to dedicated instructions 816:Drivers/CMSIS/Include/cmsis_gcc.h **** @{ 817:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 818:Drivers/CMSIS/Include/cmsis_gcc.h **** 819:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Define macros for porting to both thumb1 and thumb2. 820:Drivers/CMSIS/Include/cmsis_gcc.h **** * For thumb1, use low register (r0-r7), specified by constraint "l" 821:Drivers/CMSIS/Include/cmsis_gcc.h **** * Otherwise, use general registers, specified by constraint "r" */ 822:Drivers/CMSIS/Include/cmsis_gcc.h **** #if defined (__thumb__) && !defined (__thumb2__) 823:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_OUT_REG(r) "=l" (r) 824:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_RW_REG(r) "+l" (r) 825:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_USE_REG(r) "l" (r) 826:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 827:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_OUT_REG(r) "=r" (r) 828:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_RW_REG(r) "+r" (r) 829:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_USE_REG(r) "r" (r) 830:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 831:Drivers/CMSIS/Include/cmsis_gcc.h **** 832:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 833:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief No Operation 834:Drivers/CMSIS/Include/cmsis_gcc.h **** \details No Operation does nothing. This instruction can be used for code alignment purposes. 835:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 836:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __NOP() __ASM volatile ("nop") 837:Drivers/CMSIS/Include/cmsis_gcc.h **** 838:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 839:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Wait For Interrupt 840:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Wait For Interrupt is a hint instruction that suspends execution until one of a number o 841:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 842:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __WFI() __ASM volatile ("wfi") 843:Drivers/CMSIS/Include/cmsis_gcc.h **** 844:Drivers/CMSIS/Include/cmsis_gcc.h **** 845:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 846:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Wait For Event 847:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Wait For Event is a hint instruction that permits the processor to enter 848:Drivers/CMSIS/Include/cmsis_gcc.h **** a low-power state until one of a number of events occurs. 849:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 850:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __WFE() __ASM volatile ("wfe") 851:Drivers/CMSIS/Include/cmsis_gcc.h **** ARM GAS /tmp/ccLSPxIe.s page 505 852:Drivers/CMSIS/Include/cmsis_gcc.h **** 853:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 854:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Send Event 855:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. 856:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 857:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __SEV() __ASM volatile ("sev") 858:Drivers/CMSIS/Include/cmsis_gcc.h **** 859:Drivers/CMSIS/Include/cmsis_gcc.h **** 860:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 861:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Instruction Synchronization Barrier 862:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Instruction Synchronization Barrier flushes the pipeline in the processor, 863:Drivers/CMSIS/Include/cmsis_gcc.h **** so that all instructions following the ISB are fetched from cache or memory, 864:Drivers/CMSIS/Include/cmsis_gcc.h **** after the instruction has been completed. 865:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 866:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __ISB(void) 867:Drivers/CMSIS/Include/cmsis_gcc.h **** { 868:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("isb 0xF":::"memory"); 869:Drivers/CMSIS/Include/cmsis_gcc.h **** } 870:Drivers/CMSIS/Include/cmsis_gcc.h **** 871:Drivers/CMSIS/Include/cmsis_gcc.h **** 872:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 873:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Data Synchronization Barrier 874:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Acts as a special kind of Data Memory Barrier. 875:Drivers/CMSIS/Include/cmsis_gcc.h **** It completes when all explicit memory accesses before this instruction complete. 876:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 877:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __DSB(void) 878:Drivers/CMSIS/Include/cmsis_gcc.h **** { 879:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("dsb 0xF":::"memory"); 880:Drivers/CMSIS/Include/cmsis_gcc.h **** } 881:Drivers/CMSIS/Include/cmsis_gcc.h **** 882:Drivers/CMSIS/Include/cmsis_gcc.h **** 883:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 884:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Data Memory Barrier 885:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Ensures the apparent order of the explicit memory operations before 886:Drivers/CMSIS/Include/cmsis_gcc.h **** and after the instruction, without ensuring their completion. 887:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 888:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __DMB(void) 889:Drivers/CMSIS/Include/cmsis_gcc.h **** { 890:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("dmb 0xF":::"memory"); 891:Drivers/CMSIS/Include/cmsis_gcc.h **** } 892:Drivers/CMSIS/Include/cmsis_gcc.h **** 893:Drivers/CMSIS/Include/cmsis_gcc.h **** 894:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 895:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Reverse byte order (32 bit) 896:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x785 897:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to reverse 898:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Reversed value 899:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 900:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __REV(uint32_t value) 901:Drivers/CMSIS/Include/cmsis_gcc.h **** { 902:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) 903:Drivers/CMSIS/Include/cmsis_gcc.h **** return __builtin_bswap32(value); 904:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 905:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 906:Drivers/CMSIS/Include/cmsis_gcc.h **** 907:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); 908:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; ARM GAS /tmp/ccLSPxIe.s page 506 909:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 910:Drivers/CMSIS/Include/cmsis_gcc.h **** } 911:Drivers/CMSIS/Include/cmsis_gcc.h **** 912:Drivers/CMSIS/Include/cmsis_gcc.h **** 913:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 914:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Reverse byte order (16 bit) 915:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 916:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to reverse 917:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Reversed value 918:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 919:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __REV16(uint32_t value) 920:Drivers/CMSIS/Include/cmsis_gcc.h **** { 921:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 922:Drivers/CMSIS/Include/cmsis_gcc.h **** 923:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); 924:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; 925:Drivers/CMSIS/Include/cmsis_gcc.h **** } 926:Drivers/CMSIS/Include/cmsis_gcc.h **** 927:Drivers/CMSIS/Include/cmsis_gcc.h **** 928:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 929:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Reverse byte order (16 bit) 930:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For exam 931:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to reverse 932:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Reversed value 933:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 934:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE int16_t __REVSH(int16_t value) 935:Drivers/CMSIS/Include/cmsis_gcc.h **** { 936:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) 937:Drivers/CMSIS/Include/cmsis_gcc.h **** return (int16_t)__builtin_bswap16(value); 938:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 939:Drivers/CMSIS/Include/cmsis_gcc.h **** int16_t result; 940:Drivers/CMSIS/Include/cmsis_gcc.h **** 941:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); 942:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; 943:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 944:Drivers/CMSIS/Include/cmsis_gcc.h **** } 945:Drivers/CMSIS/Include/cmsis_gcc.h **** 946:Drivers/CMSIS/Include/cmsis_gcc.h **** 947:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 948:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Rotate Right in unsigned value (32 bit) 949:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Rotate Right (immediate) provides the value of the contents of a register rotated by a v 950:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] op1 Value to rotate 951:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] op2 Number of Bits to rotate 952:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Rotated value 953:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 954:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) 955:Drivers/CMSIS/Include/cmsis_gcc.h **** { 956:Drivers/CMSIS/Include/cmsis_gcc.h **** op2 %= 32U; 957:Drivers/CMSIS/Include/cmsis_gcc.h **** if (op2 == 0U) 958:Drivers/CMSIS/Include/cmsis_gcc.h **** { 959:Drivers/CMSIS/Include/cmsis_gcc.h **** return op1; 960:Drivers/CMSIS/Include/cmsis_gcc.h **** } 961:Drivers/CMSIS/Include/cmsis_gcc.h **** return (op1 >> op2) | (op1 << (32U - op2)); 962:Drivers/CMSIS/Include/cmsis_gcc.h **** } 963:Drivers/CMSIS/Include/cmsis_gcc.h **** 964:Drivers/CMSIS/Include/cmsis_gcc.h **** 965:Drivers/CMSIS/Include/cmsis_gcc.h **** /** ARM GAS /tmp/ccLSPxIe.s page 507 966:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Breakpoint 967:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Causes the processor to enter Debug state. 968:Drivers/CMSIS/Include/cmsis_gcc.h **** Debug tools can use this to investigate system state when the instruction at a particula 969:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value is ignored by the processor. 970:Drivers/CMSIS/Include/cmsis_gcc.h **** If required, a debugger can use it to store additional information about the break 971:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 972:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __BKPT(value) __ASM volatile ("bkpt "#value) 973:Drivers/CMSIS/Include/cmsis_gcc.h **** 974:Drivers/CMSIS/Include/cmsis_gcc.h **** 975:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 976:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Reverse bit order of value 977:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Reverses the bit order of the given value. 978:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to reverse 979:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Reversed value 980:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 981:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value) 982:Drivers/CMSIS/Include/cmsis_gcc.h **** { 983:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 984:Drivers/CMSIS/Include/cmsis_gcc.h **** 985:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ 986:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ 987:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) 988:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 989:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 990:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ 991:Drivers/CMSIS/Include/cmsis_gcc.h **** 992:Drivers/CMSIS/Include/cmsis_gcc.h **** result = value; /* r will be reversed bits of v; first get LSB of v */ 993:Drivers/CMSIS/Include/cmsis_gcc.h **** for (value >>= 1U; value != 0U; value >>= 1U) 994:Drivers/CMSIS/Include/cmsis_gcc.h **** { 995:Drivers/CMSIS/Include/cmsis_gcc.h **** result <<= 1U; 996:Drivers/CMSIS/Include/cmsis_gcc.h **** result |= value & 1U; 997:Drivers/CMSIS/Include/cmsis_gcc.h **** s--; 998:Drivers/CMSIS/Include/cmsis_gcc.h **** } 999:Drivers/CMSIS/Include/cmsis_gcc.h **** result <<= s; /* shift when v's highest bits are zero */ 1000:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 1001:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; 1002:Drivers/CMSIS/Include/cmsis_gcc.h **** } 1003:Drivers/CMSIS/Include/cmsis_gcc.h **** 1004:Drivers/CMSIS/Include/cmsis_gcc.h **** 1005:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 1006:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Count leading zeros 1007:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Counts the number of leading zeros of a data value. 1008:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to count the leading zeros 1009:Drivers/CMSIS/Include/cmsis_gcc.h **** \return number of leading zeros in value 1010:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 1011:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CLZ (uint8_t)__builtin_clz 1012:Drivers/CMSIS/Include/cmsis_gcc.h **** 1013:Drivers/CMSIS/Include/cmsis_gcc.h **** 1014:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ 1015:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ 1016:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ 1017:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) 1018:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 1019:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief LDR Exclusive (8 bit) 1020:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Executes a exclusive LDR instruction for 8 bit value. 1021:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ptr Pointer to data 1022:Drivers/CMSIS/Include/cmsis_gcc.h **** \return value of type uint8_t at (*ptr) ARM GAS /tmp/ccLSPxIe.s page 508 1023:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 1024:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr) 1025:Drivers/CMSIS/Include/cmsis_gcc.h **** { 1026:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 1027:Drivers/CMSIS/Include/cmsis_gcc.h **** 1028:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) 1029:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); 1030:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 1031:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not 1032:Drivers/CMSIS/Include/cmsis_gcc.h **** accepted by assembler. So has to use following less efficient pattern. 1033:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 1034:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); 1035:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 1036:Drivers/CMSIS/Include/cmsis_gcc.h **** return ((uint8_t) result); /* Add explicit type cast here */ 1037:Drivers/CMSIS/Include/cmsis_gcc.h **** } 1038:Drivers/CMSIS/Include/cmsis_gcc.h **** 1039:Drivers/CMSIS/Include/cmsis_gcc.h **** 1040:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 1041:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief LDR Exclusive (16 bit) 1042:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Executes a exclusive LDR instruction for 16 bit values. 1043:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ptr Pointer to data 1044:Drivers/CMSIS/Include/cmsis_gcc.h **** \return value of type uint16_t at (*ptr) 1045:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 1046:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr) 1047:Drivers/CMSIS/Include/cmsis_gcc.h **** { 1048:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 1049:Drivers/CMSIS/Include/cmsis_gcc.h **** 1050:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) 1051:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); 1052:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 1053:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not 1054:Drivers/CMSIS/Include/cmsis_gcc.h **** accepted by assembler. So has to use following less efficient pattern. 1055:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 1056:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); 1057:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 1058:Drivers/CMSIS/Include/cmsis_gcc.h **** return ((uint16_t) result); /* Add explicit type cast here */ 1059:Drivers/CMSIS/Include/cmsis_gcc.h **** } 1060:Drivers/CMSIS/Include/cmsis_gcc.h **** 1061:Drivers/CMSIS/Include/cmsis_gcc.h **** 1062:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 1063:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief LDR Exclusive (32 bit) 1064:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Executes a exclusive LDR instruction for 32 bit values. 1065:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ptr Pointer to data 1066:Drivers/CMSIS/Include/cmsis_gcc.h **** \return value of type uint32_t at (*ptr) 1067:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 1068:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr) 7089 .loc 8 1068 31 view .LVU2203 7090 .LBB593: 1069:Drivers/CMSIS/Include/cmsis_gcc.h **** { 1070:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 7091 .loc 8 1070 5 view .LVU2204 1071:Drivers/CMSIS/Include/cmsis_gcc.h **** 1072:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 7092 .loc 8 1072 4 view .LVU2205 7093 00e8 7D4A ldr r2, .L390+76 7094 00ea 02F10803 add r3, r2, #8 7095 .syntax unified ARM GAS /tmp/ccLSPxIe.s page 509 7096 @ 1072 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 7097 00ee 53E8003F ldrex r3, [r3] 7098 @ 0 "" 2 7099 .LVL637: 1073:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 7100 .loc 8 1073 4 view .LVU2206 7101 .loc 8 1073 4 is_stmt 0 view .LVU2207 7102 .thumb 7103 .syntax unified 7104 .LBE593: 7105 .LBE592: 7106 .loc 7 3558 3 discriminator 1 view .LVU2208 7107 00f2 43F08003 orr r3, r3, #128 7108 .LVL638: 7109 .loc 7 3558 3 is_stmt 1 discriminator 1 view .LVU2209 7110 .LBB594: 7111 .LBI594: 1074:Drivers/CMSIS/Include/cmsis_gcc.h **** } 1075:Drivers/CMSIS/Include/cmsis_gcc.h **** 1076:Drivers/CMSIS/Include/cmsis_gcc.h **** 1077:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 1078:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief STR Exclusive (8 bit) 1079:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Executes a exclusive STR instruction for 8 bit values. 1080:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to store 1081:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ptr Pointer to location 1082:Drivers/CMSIS/Include/cmsis_gcc.h **** \return 0 Function succeeded 1083:Drivers/CMSIS/Include/cmsis_gcc.h **** \return 1 Function failed 1084:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 1085:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) 1086:Drivers/CMSIS/Include/cmsis_gcc.h **** { 1087:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 1088:Drivers/CMSIS/Include/cmsis_gcc.h **** 1089:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); 1090:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 1091:Drivers/CMSIS/Include/cmsis_gcc.h **** } 1092:Drivers/CMSIS/Include/cmsis_gcc.h **** 1093:Drivers/CMSIS/Include/cmsis_gcc.h **** 1094:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 1095:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief STR Exclusive (16 bit) 1096:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Executes a exclusive STR instruction for 16 bit values. 1097:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to store 1098:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ptr Pointer to location 1099:Drivers/CMSIS/Include/cmsis_gcc.h **** \return 0 Function succeeded 1100:Drivers/CMSIS/Include/cmsis_gcc.h **** \return 1 Function failed 1101:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 1102:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) 1103:Drivers/CMSIS/Include/cmsis_gcc.h **** { 1104:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 1105:Drivers/CMSIS/Include/cmsis_gcc.h **** 1106:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); 1107:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 1108:Drivers/CMSIS/Include/cmsis_gcc.h **** } 1109:Drivers/CMSIS/Include/cmsis_gcc.h **** 1110:Drivers/CMSIS/Include/cmsis_gcc.h **** 1111:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 1112:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief STR Exclusive (32 bit) 1113:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Executes a exclusive STR instruction for 32 bit values. ARM GAS /tmp/ccLSPxIe.s page 510 1114:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to store 1115:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ptr Pointer to location 1116:Drivers/CMSIS/Include/cmsis_gcc.h **** \return 0 Function succeeded 1117:Drivers/CMSIS/Include/cmsis_gcc.h **** \return 1 Function failed 1118:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 1119:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) 7112 .loc 8 1119 31 view .LVU2210 7113 .LBB595: 1120:Drivers/CMSIS/Include/cmsis_gcc.h **** { 1121:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 7114 .loc 8 1121 4 view .LVU2211 1122:Drivers/CMSIS/Include/cmsis_gcc.h **** 1123:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 7115 .loc 8 1123 4 view .LVU2212 7116 00f6 0832 adds r2, r2, #8 7117 .syntax unified 7118 @ 1123 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 7119 00f8 42E80031 strex r1, r3, [r2] 7120 @ 0 "" 2 7121 .LVL639: 1124:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 7122 .loc 8 1124 4 view .LVU2213 7123 .loc 8 1124 4 is_stmt 0 view .LVU2214 7124 .thumb 7125 .syntax unified 7126 .LBE595: 7127 .LBE594: 7128 .loc 7 3558 3 discriminator 1 view .LVU2215 7129 00fc 0029 cmp r1, #0 7130 00fe F3D1 bne .L381 7131 .LBE591: 7132 .loc 7 3558 3 is_stmt 1 discriminator 2 view .LVU2216 7133 .LVL640: 7134 .loc 7 3558 3 is_stmt 0 discriminator 2 view .LVU2217 7135 .LBE590: 2408:Src/main.c **** LL_DMA_EnableIT_TE(DMA2, LL_DMA_STREAM_7); 7136 .loc 1 2408 3 is_stmt 1 view .LVU2218 7137 .LBB596: 7138 .LBI596: 2368:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 2369:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 2370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 2371:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Clear Stream 0 direct mode error flag. 2372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LIFCR CDMEIF0 LL_DMA_ClearFlag_DME0 2373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 2374:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 2375:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 2376:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_DME0(DMA_TypeDef *DMAx) 2377:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 2378:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CDMEIF0); 2379:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 2380:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 2381:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 2382:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Clear Stream 1 direct mode error flag. 2383:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LIFCR CDMEIF1 LL_DMA_ClearFlag_DME1 2384:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 2385:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None ARM GAS /tmp/ccLSPxIe.s page 511 2386:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 2387:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_DME1(DMA_TypeDef *DMAx) 2388:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 2389:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CDMEIF1); 2390:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 2391:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 2392:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 2393:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Clear Stream 2 direct mode error flag. 2394:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LIFCR CDMEIF2 LL_DMA_ClearFlag_DME2 2395:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 2396:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 2397:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 2398:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_DME2(DMA_TypeDef *DMAx) 2399:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 2400:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CDMEIF2); 2401:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 2402:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 2403:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 2404:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Clear Stream 3 direct mode error flag. 2405:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LIFCR CDMEIF3 LL_DMA_ClearFlag_DME3 2406:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 2407:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 2408:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 2409:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_DME3(DMA_TypeDef *DMAx) 2410:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 2411:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CDMEIF3); 2412:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 2413:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 2414:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 2415:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Clear Stream 4 direct mode error flag. 2416:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HIFCR CDMEIF4 LL_DMA_ClearFlag_DME4 2417:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 2418:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 2419:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 2420:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_DME4(DMA_TypeDef *DMAx) 2421:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 2422:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CDMEIF4); 2423:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 2424:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 2425:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 2426:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Clear Stream 5 direct mode error flag. 2427:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HIFCR CDMEIF5 LL_DMA_ClearFlag_DME5 2428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 2429:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 2430:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 2431:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_DME5(DMA_TypeDef *DMAx) 2432:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 2433:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CDMEIF5); 2434:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 2435:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 2436:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 2437:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Clear Stream 6 direct mode error flag. 2438:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HIFCR CDMEIF6 LL_DMA_ClearFlag_DME6 2439:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 2440:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 2441:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 2442:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_DME6(DMA_TypeDef *DMAx) ARM GAS /tmp/ccLSPxIe.s page 512 2443:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 2444:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CDMEIF6); 2445:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 2446:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 2447:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 2448:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Clear Stream 7 direct mode error flag. 2449:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HIFCR CDMEIF7 LL_DMA_ClearFlag_DME7 2450:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 2451:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 2452:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 2453:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_DME7(DMA_TypeDef *DMAx) 2454:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 2455:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CDMEIF7); 2456:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 2457:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 2458:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 2459:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Clear Stream 0 FIFO error flag. 2460:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LIFCR CFEIF0 LL_DMA_ClearFlag_FE0 2461:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 2462:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 2463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 2464:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_FE0(DMA_TypeDef *DMAx) 2465:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 2466:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CFEIF0); 2467:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 2468:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 2469:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 2470:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Clear Stream 1 FIFO error flag. 2471:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LIFCR CFEIF1 LL_DMA_ClearFlag_FE1 2472:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 2473:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 2474:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 2475:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_FE1(DMA_TypeDef *DMAx) 2476:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 2477:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CFEIF1); 2478:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 2479:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 2480:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 2481:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Clear Stream 2 FIFO error flag. 2482:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LIFCR CFEIF2 LL_DMA_ClearFlag_FE2 2483:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 2484:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 2485:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 2486:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_FE2(DMA_TypeDef *DMAx) 2487:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 2488:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CFEIF2); 2489:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 2490:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 2491:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 2492:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Clear Stream 3 FIFO error flag. 2493:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LIFCR CFEIF3 LL_DMA_ClearFlag_FE3 2494:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 2495:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 2496:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 2497:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_FE3(DMA_TypeDef *DMAx) 2498:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 2499:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CFEIF3); ARM GAS /tmp/ccLSPxIe.s page 513 2500:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 2501:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 2502:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 2503:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Clear Stream 4 FIFO error flag. 2504:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HIFCR CFEIF4 LL_DMA_ClearFlag_FE4 2505:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 2506:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 2507:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 2508:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_FE4(DMA_TypeDef *DMAx) 2509:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 2510:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CFEIF4); 2511:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 2512:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 2513:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 2514:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Clear Stream 5 FIFO error flag. 2515:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HIFCR CFEIF5 LL_DMA_ClearFlag_FE5 2516:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 2517:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 2518:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 2519:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_FE5(DMA_TypeDef *DMAx) 2520:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 2521:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CFEIF5); 2522:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 2523:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 2524:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 2525:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Clear Stream 6 FIFO error flag. 2526:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HIFCR CFEIF6 LL_DMA_ClearFlag_FE6 2527:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 2528:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 2529:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 2530:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_FE6(DMA_TypeDef *DMAx) 2531:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 2532:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CFEIF6); 2533:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 2534:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 2535:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 2536:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Clear Stream 7 FIFO error flag. 2537:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HIFCR CFEIF7 LL_DMA_ClearFlag_FE7 2538:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 2539:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 2540:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 2541:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_FE7(DMA_TypeDef *DMAx) 2542:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 2543:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CFEIF7); 2544:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 2545:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 2546:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 2547:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @} 2548:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 2549:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 2550:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_EF_IT_Management IT_Management 2551:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @{ 2552:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 2553:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 2554:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 2555:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Enable Half transfer interrupt. 2556:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR HTIE LL_DMA_EnableIT_HT ARM GAS /tmp/ccLSPxIe.s page 514 2557:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 2558:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: 2559:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 2560:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 2561:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 2562:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 2563:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 2564:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 2565:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 2566:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 2567:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 2568:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 2569:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_EnableIT_HT(DMA_TypeDef *DMAx, uint32_t Stream) 2570:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 2571:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA 2572:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 2573:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 2574:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 2575:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Enable Transfer error interrupt. 2576:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR TEIE LL_DMA_EnableIT_TE 2577:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 2578:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: 2579:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 2580:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 2581:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 2582:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 2583:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 2584:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 2585:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 2586:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 2587:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 2588:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 2589:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_EnableIT_TE(DMA_TypeDef *DMAx, uint32_t Stream) 2590:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 2591:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA 2592:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 2593:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** 2594:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** 2595:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Enable Transfer complete interrupt. 2596:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR TCIE LL_DMA_EnableIT_TC 2597:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance 2598:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: 2599:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 2600:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 2601:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 2602:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 2603:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 2604:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 2605:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 2606:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 2607:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None 2608:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ 2609:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_EnableIT_TC(DMA_TypeDef *DMAx, uint32_t Stream) 7139 .loc 6 2609 22 view .LVU2219 7140 .LBB597: 2610:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 2611:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA ARM GAS /tmp/ccLSPxIe.s page 515 7141 .loc 6 2611 3 view .LVU2220 7142 0100 784B ldr r3, .L390+80 7143 0102 D3F8B820 ldr r2, [r3, #184] 7144 0106 42F01002 orr r2, r2, #16 7145 010a C3F8B820 str r2, [r3, #184] 7146 .LVL641: 7147 .loc 6 2611 3 is_stmt 0 view .LVU2221 7148 .LBE597: 7149 .LBE596: 2409:Src/main.c **** LL_DMA_ClearFlag_TC7(DMA2); 7150 .loc 1 2409 3 is_stmt 1 view .LVU2222 7151 .LBB598: 7152 .LBI598: 2589:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 7153 .loc 6 2589 22 view .LVU2223 7154 .LBB599: 2591:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 7155 .loc 6 2591 3 view .LVU2224 7156 010e D3F8B820 ldr r2, [r3, #184] 7157 0112 42F00402 orr r2, r2, #4 7158 0116 C3F8B820 str r2, [r3, #184] 7159 .LVL642: 2591:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 7160 .loc 6 2591 3 is_stmt 0 view .LVU2225 7161 .LBE599: 7162 .LBE598: 2410:Src/main.c **** LL_DMA_ClearFlag_TE7(DMA2); 7163 .loc 1 2410 3 is_stmt 1 view .LVU2226 7164 .LBB600: 7165 .LBI600: 2277:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 7166 .loc 6 2277 22 view .LVU2227 7167 .LBB601: 2279:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 7168 .loc 6 2279 3 view .LVU2228 7169 011a 4FF00062 mov r2, #134217728 7170 011e DA60 str r2, [r3, #12] 7171 .LVL643: 2279:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 7172 .loc 6 2279 3 is_stmt 0 view .LVU2229 7173 .LBE601: 7174 .LBE600: 2411:Src/main.c **** LL_DMA_ConfigAddresses(DMA2, LL_DMA_STREAM_7, (uint32_t)&UART_DATA, LL_USART_DMA_GetRegAddr(USART 7175 .loc 1 2411 3 is_stmt 1 view .LVU2230 7176 .LBB602: 7177 .LBI602: 2365:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 7178 .loc 6 2365 22 view .LVU2231 7179 .LBB603: 2367:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 7180 .loc 6 2367 3 view .LVU2232 7181 0120 4FF00072 mov r2, #33554432 7182 0124 DA60 str r2, [r3, #12] 7183 .LVL644: 2367:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 7184 .loc 6 2367 3 is_stmt 0 view .LVU2233 7185 .LBE603: ARM GAS /tmp/ccLSPxIe.s page 516 7186 .LBE602: 2412:Src/main.c **** 7187 .loc 1 2412 3 is_stmt 1 view .LVU2234 7188 0126 704A ldr r2, .L390+84 7189 .LVL645: 7190 .LBB604: 7191 .LBI604: 621:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 7192 .loc 6 621 26 view .LVU2235 7193 .LBB605: 623:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 7194 .loc 6 623 3 view .LVU2236 623:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 7195 .loc 6 623 11 is_stmt 0 view .LVU2237 7196 0128 D3F8B830 ldr r3, [r3, #184] 7197 012c 03F0C003 and r3, r3, #192 7198 .LVL646: 623:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 7199 .loc 6 623 11 view .LVU2238 7200 .LBE605: 7201 .LBE604: 7202 .LBB606: 7203 .LBI606: 1425:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 7204 .loc 6 1425 22 is_stmt 1 view .LVU2239 7205 .LBB607: 1428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 7206 .loc 6 1428 3 view .LVU2240 1428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 7207 .loc 6 1428 6 is_stmt 0 view .LVU2241 7208 0130 402B cmp r3, #64 7209 0132 00F08480 beq .L387 1436:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR 7210 .loc 6 1436 5 is_stmt 1 view .LVU2242 7211 0136 6B4B ldr r3, .L390+80 7212 .LVL647: 1436:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR 7213 .loc 6 1436 5 is_stmt 0 view .LVU2243 7214 0138 C3F8C020 str r2, [r3, #192] 1437:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 7215 .loc 6 1437 5 is_stmt 1 view .LVU2244 7216 013c 6B4A ldr r2, .L390+88 7217 013e C3F8C420 str r2, [r3, #196] 7218 .L383: 7219 .LVL648: 1437:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 7220 .loc 6 1437 5 is_stmt 0 view .LVU2245 7221 .LBE607: 7222 .LBE606: 2417:Src/main.c **** SD_SLIDE = 0; 7223 .loc 1 2417 2 is_stmt 1 view .LVU2246 2417:Src/main.c **** SD_SLIDE = 0; 7224 .loc 1 2417 10 is_stmt 0 view .LVU2247 7225 0142 0024 movs r4, #0 7226 0144 6A4B ldr r3, .L390+92 7227 0146 1C60 str r4, [r3] 2418:Src/main.c **** //Reset all periphery ARM GAS /tmp/ccLSPxIe.s page 517 7228 .loc 1 2418 2 is_stmt 1 view .LVU2248 2418:Src/main.c **** //Reset all periphery 7229 .loc 1 2418 11 is_stmt 0 view .LVU2249 7230 0148 6A4B ldr r3, .L390+96 7231 014a 1C60 str r4, [r3] 2420:Src/main.c **** HAL_GPIO_WritePin(EN_5V2_GPIO_Port, EN_5V2_Pin, GPIO_PIN_RESET); 7232 .loc 1 2420 2 is_stmt 1 view .LVU2250 7233 014c 6A4E ldr r6, .L390+100 7234 014e 2246 mov r2, r4 7235 0150 0821 movs r1, #8 7236 0152 3046 mov r0, r6 7237 0154 FFF7FEFF bl HAL_GPIO_WritePin 7238 .LVL649: 2421:Src/main.c **** HAL_GPIO_WritePin(LD1_EN_GPIO_Port, LD1_EN_Pin, GPIO_PIN_RESET); 7239 .loc 1 2421 2 view .LVU2251 7240 0158 2246 mov r2, r4 7241 015a 8021 movs r1, #128 7242 015c 3046 mov r0, r6 7243 015e FFF7FEFF bl HAL_GPIO_WritePin 7244 .LVL650: 2422:Src/main.c **** HAL_GPIO_WritePin(LD2_EN_GPIO_Port, LD2_EN_Pin, GPIO_PIN_RESET); 7245 .loc 1 2422 2 view .LVU2252 7246 0162 664F ldr r7, .L390+104 7247 0164 2246 mov r2, r4 7248 0166 4FF48071 mov r1, #256 7249 016a 3846 mov r0, r7 7250 016c FFF7FEFF bl HAL_GPIO_WritePin 7251 .LVL651: 2423:Src/main.c **** HAL_GPIO_WritePin(REF0_EN_GPIO_Port, REF0_EN_Pin, GPIO_PIN_RESET); 7252 .loc 1 2423 2 view .LVU2253 7253 0170 2246 mov r2, r4 7254 0172 1021 movs r1, #16 7255 0174 3046 mov r0, r6 7256 0176 FFF7FEFF bl HAL_GPIO_WritePin 7257 .LVL652: 2424:Src/main.c **** HAL_GPIO_WritePin(REF2_ON_GPIO_Port, REF2_ON_Pin, GPIO_PIN_RESET); 7258 .loc 1 2424 2 view .LVU2254 7259 017a DFF89C81 ldr r8, .L390+132 7260 017e 2246 mov r2, r4 7261 0180 4FF48061 mov r1, #1024 7262 0184 4046 mov r0, r8 7263 0186 FFF7FEFF bl HAL_GPIO_WritePin 7264 .LVL653: 2425:Src/main.c **** HAL_GPIO_WritePin(TECEN1_GPIO_Port, TECEN1_Pin, GPIO_PIN_RESET); 7265 .loc 1 2425 2 view .LVU2255 7266 018a 5D4D ldr r5, .L390+108 7267 018c 2246 mov r2, r4 7268 018e 0821 movs r1, #8 7269 0190 2846 mov r0, r5 7270 0192 FFF7FEFF bl HAL_GPIO_WritePin 7271 .LVL654: 2426:Src/main.c **** HAL_GPIO_WritePin(TECEN2_GPIO_Port, TECEN2_Pin, GPIO_PIN_RESET); 7272 .loc 1 2426 2 view .LVU2256 7273 0196 2246 mov r2, r4 7274 0198 0121 movs r1, #1 7275 019a 2846 mov r0, r5 7276 019c FFF7FEFF bl HAL_GPIO_WritePin ARM GAS /tmp/ccLSPxIe.s page 518 7277 .LVL655: 2427:Src/main.c **** HAL_GPIO_WritePin(TEC1_PD_GPIO_Port, TEC1_PD_Pin, GPIO_PIN_RESET); 7278 .loc 1 2427 2 view .LVU2257 7279 01a0 2246 mov r2, r4 7280 01a2 0221 movs r1, #2 7281 01a4 2846 mov r0, r5 7282 01a6 FFF7FEFF bl HAL_GPIO_WritePin 7283 .LVL656: 2428:Src/main.c **** HAL_GPIO_WritePin(TEC2_PD_GPIO_Port, TEC2_PD_Pin, GPIO_PIN_RESET); 7284 .loc 1 2428 2 view .LVU2258 7285 01aa 2246 mov r2, r4 7286 01ac 4FF40061 mov r1, #2048 7287 01b0 4046 mov r0, r8 7288 01b2 FFF7FEFF bl HAL_GPIO_WritePin 7289 .LVL657: 2429:Src/main.c **** // for (uint16_t i = 0; i < SD_Length; i++) 7290 .loc 1 2429 2 view .LVU2259 7291 01b6 2246 mov r2, r4 7292 01b8 2021 movs r1, #32 7293 01ba 3046 mov r0, r6 7294 01bc FFF7FEFF bl HAL_GPIO_WritePin 7295 .LVL658: 2439:Src/main.c **** HAL_GPIO_WritePin(ADC_MPD2_CS_GPIO_Port, ADC_MPD2_CS_Pin, GPIO_PIN_SET);//Enable SPI for MPhD2 ADC 7296 .loc 1 2439 2 view .LVU2260 7297 01c0 06F50066 add r6, r6, #2048 7298 01c4 0122 movs r2, #1 7299 01c6 4FF48061 mov r1, #1024 7300 01ca 3046 mov r0, r6 7301 01cc FFF7FEFF bl HAL_GPIO_WritePin 7302 .LVL659: 2440:Src/main.c **** HAL_GPIO_WritePin(SPI4_CNV_GPIO_Port, SPI4_CNV_Pin, GPIO_PIN_SET); 7303 .loc 1 2440 2 view .LVU2261 7304 01d0 DFF84891 ldr r9, .L390+136 7305 01d4 0122 movs r2, #1 7306 01d6 4021 movs r1, #64 7307 01d8 4846 mov r0, r9 7308 01da FFF7FEFF bl HAL_GPIO_WritePin 7309 .LVL660: 2441:Src/main.c **** HAL_GPIO_WritePin(SPI5_CNV_GPIO_Port, SPI4_CNV_Pin, GPIO_PIN_SET); 7310 .loc 1 2441 2 view .LVU2262 7311 01de 0122 movs r2, #1 7312 01e0 4FF48041 mov r1, #16384 7313 01e4 3046 mov r0, r6 7314 01e6 FFF7FEFF bl HAL_GPIO_WritePin 7315 .LVL661: 2442:Src/main.c **** HAL_GPIO_WritePin(DAC_LD1_CS_GPIO_Port, DAC_LD1_CS_Pin, GPIO_PIN_SET);//End operation with LDAC1 7316 .loc 1 2442 2 view .LVU2263 7317 01ea 0122 movs r2, #1 7318 01ec 4FF48041 mov r1, #16384 7319 01f0 4846 mov r0, r9 7320 01f2 FFF7FEFF bl HAL_GPIO_WritePin 7321 .LVL662: 2443:Src/main.c **** HAL_GPIO_WritePin(DAC_LD2_CS_GPIO_Port, DAC_LD2_CS_Pin, GPIO_PIN_SET);//End operation with LDAC2 7322 .loc 1 2443 2 view .LVU2264 7323 01f6 0122 movs r2, #1 7324 01f8 4FF48041 mov r1, #16384 7325 01fc 4046 mov r0, r8 ARM GAS /tmp/ccLSPxIe.s page 519 7326 01fe FFF7FEFF bl HAL_GPIO_WritePin 7327 .LVL663: 2444:Src/main.c **** HAL_GPIO_WritePin(DAC_TEC1_CS_GPIO_Port, DAC_TEC1_CS_Pin, GPIO_PIN_SET);//End operation with TEC1 7328 .loc 1 2444 2 view .LVU2265 7329 0202 0122 movs r2, #1 7330 0204 4021 movs r1, #64 7331 0206 2846 mov r0, r5 7332 0208 FFF7FEFF bl HAL_GPIO_WritePin 7333 .LVL664: 2445:Src/main.c **** HAL_GPIO_WritePin(DAC_TEC2_CS_GPIO_Port, DAC_TEC2_CS_Pin, GPIO_PIN_SET);//End operation with TEC2 7334 .loc 1 2445 2 view .LVU2266 7335 020c 0122 movs r2, #1 7336 020e 4FF48051 mov r1, #4096 7337 0212 3846 mov r0, r7 7338 0214 FFF7FEFF bl HAL_GPIO_WritePin 7339 .LVL665: 2446:Src/main.c **** PA4_DAC_Set(0u, 0u); 7340 .loc 1 2446 2 view .LVU2267 7341 0218 0122 movs r2, #1 7342 021a 4FF48071 mov r1, #256 7343 021e 3046 mov r0, r6 7344 0220 FFF7FEFF bl HAL_GPIO_WritePin 7345 .LVL666: 2447:Src/main.c **** 7346 .loc 1 2447 2 view .LVU2268 7347 0224 2146 mov r1, r4 7348 0226 2046 mov r0, r4 7349 0228 FFF7FEFF bl PA4_DAC_Set 7350 .LVL667: 2451:Src/main.c **** { 7351 .loc 1 2451 2 view .LVU2269 2451:Src/main.c **** { 7352 .loc 1 2451 6 is_stmt 0 view .LVU2270 7353 022c 0121 movs r1, #1 7354 022e 3846 mov r0, r7 7355 0230 FFF7FEFF bl HAL_GPIO_ReadPin 7356 .LVL668: 2451:Src/main.c **** { 7357 .loc 1 2451 5 discriminator 1 view .LVU2271 7358 0234 50B1 cbz r0, .L388 7359 .L384: 2482:Src/main.c **** } 7360 .loc 1 2482 2 is_stmt 1 view .LVU2272 7361 0236 FFF7FEFF bl AD9102_Init 7362 .LVL669: 2483:Src/main.c **** static void Decode_uart(uint16_t *Command, LDx_SetupTypeDef *LD1_curr_setup, LDx_SetupTypeDef *LD2_ 7363 .loc 1 2483 1 is_stmt 0 view .LVU2273 7364 023a BDE8F883 pop {r3, r4, r5, r6, r7, r8, r9, pc} 7365 .LVL670: 7366 .L387: 7367 .LBB609: 7368 .LBB608: 1430:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR, 7369 .loc 6 1430 5 is_stmt 1 view .LVU2274 7370 023e 294B ldr r3, .L390+80 7371 .LVL671: 1430:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR, ARM GAS /tmp/ccLSPxIe.s page 520 7372 .loc 6 1430 5 is_stmt 0 view .LVU2275 7373 0240 C3F8C420 str r2, [r3, #196] 1431:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 7374 .loc 6 1431 5 is_stmt 1 view .LVU2276 7375 0244 294A ldr r2, .L390+88 7376 0246 C3F8C020 str r2, [r3, #192] 7377 024a 7AE7 b .L383 7378 .LVL672: 7379 .L388: 1431:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 7380 .loc 6 1431 5 is_stmt 0 view .LVU2277 7381 .LBE608: 7382 .LBE609: 2454:Src/main.c **** { 7383 .loc 1 2454 3 is_stmt 1 view .LVU2278 2454:Src/main.c **** { 7384 .loc 1 2454 7 is_stmt 0 view .LVU2279 7385 024c 4FF48071 mov r1, #256 7386 0250 2846 mov r0, r5 7387 0252 FFF7FEFF bl HAL_GPIO_ReadPin 7388 .LVL673: 2454:Src/main.c **** { 7389 .loc 1 2454 6 discriminator 1 view .LVU2280 7390 0256 0028 cmp r0, #0 7391 0258 EDD1 bne .L384 2457:Src/main.c **** if (test == 0) //0 - suc 7392 .loc 1 2457 4 is_stmt 1 view .LVU2281 2457:Src/main.c **** if (test == 0) //0 - suc 7393 .loc 1 2457 11 is_stmt 0 view .LVU2282 7394 025a 2A48 ldr r0, .L390+112 7395 025c FFF7FEFF bl Mount_SD 7396 .LVL674: 2457:Src/main.c **** if (test == 0) //0 - suc 7397 .loc 1 2457 9 discriminator 1 view .LVU2283 7398 0260 294B ldr r3, .L390+116 7399 0262 1860 str r0, [r3] 2458:Src/main.c **** { 7400 .loc 1 2458 4 is_stmt 1 view .LVU2284 2458:Src/main.c **** { 7401 .loc 1 2458 7 is_stmt 0 view .LVU2285 7402 0264 18B1 cbz r0, .L389 7403 .L385: 2470:Src/main.c **** } 7404 .loc 1 2470 4 is_stmt 1 view .LVU2286 2470:Src/main.c **** } 7405 .loc 1 2470 14 is_stmt 0 view .LVU2287 7406 0266 294B ldr r3, .L390+120 7407 0268 0122 movs r2, #1 7408 026a 1A70 strb r2, [r3] 7409 026c E3E7 b .L384 7410 .L389: 2461:Src/main.c **** test = Unmount_SD("/"); // 0 - succ 7411 .loc 1 2461 5 is_stmt 1 view .LVU2288 2461:Src/main.c **** test = Unmount_SD("/"); // 0 - succ 7412 .loc 1 2461 12 is_stmt 0 view .LVU2289 7413 026e 1E23 movs r3, #30 7414 0270 1A46 mov r2, r3 ARM GAS /tmp/ccLSPxIe.s page 521 7415 0272 2749 ldr r1, .L390+124 7416 0274 2748 ldr r0, .L390+128 7417 0276 FFF7FEFF bl Seek_Read_File 7418 .LVL675: 2461:Src/main.c **** test = Unmount_SD("/"); // 0 - succ 7419 .loc 1 2461 10 discriminator 1 view .LVU2290 7420 027a 234C ldr r4, .L390+116 7421 027c 2060 str r0, [r4] 2462:Src/main.c **** UART_rec_incr = 0; 7422 .loc 1 2462 5 is_stmt 1 view .LVU2291 2462:Src/main.c **** UART_rec_incr = 0; 7423 .loc 1 2462 12 is_stmt 0 view .LVU2292 7424 027e 2148 ldr r0, .L390+112 7425 0280 FFF7FEFF bl Unmount_SD 7426 .LVL676: 2462:Src/main.c **** UART_rec_incr = 0; 7427 .loc 1 2462 10 discriminator 1 view .LVU2293 7428 0284 2060 str r0, [r4] 2463:Src/main.c **** flg_tmt = 0;//Reset the timeout flag 7429 .loc 1 2463 5 is_stmt 1 view .LVU2294 2463:Src/main.c **** flg_tmt = 0;//Reset the timeout flag 7430 .loc 1 2463 19 is_stmt 0 view .LVU2295 7431 0286 0023 movs r3, #0 7432 0288 084A ldr r2, .L390+24 7433 028a 1380 strh r3, [r2] @ movhi 2464:Src/main.c **** } 7434 .loc 1 2464 5 is_stmt 1 view .LVU2296 2464:Src/main.c **** } 7435 .loc 1 2464 13 is_stmt 0 view .LVU2297 7436 028c 064A ldr r2, .L390+20 7437 028e 1370 strb r3, [r2] 7438 0290 E9E7 b .L385 7439 .L391: 7440 0292 00BF .align 2 7441 .L390: 7442 0294 00000000 .word TO6 7443 0298 00000000 .word TO7 7444 029c 00000000 .word TO7_before 7445 02a0 00000000 .word TO6_before 7446 02a4 00000000 .word TO6_uart 7447 02a8 00000000 .word flg_tmt 7448 02ac 00000000 .word UART_rec_incr 7449 02b0 00000000 .word fgoto 7450 02b4 00000000 .word sizeoffile 7451 02b8 00000000 .word u_tx_flg 7452 02bc 00000000 .word u_rx_flg 7453 02c0 00000000 .word Long_Data 7454 02c4 00000000 .word Def_setup 7455 02c8 00000000 .word LD1_def_setup 7456 02cc 00000000 .word LD2_def_setup 7457 02d0 00000000 .word Curr_setup 7458 02d4 00000000 .word LD1_curr_setup 7459 02d8 00000000 .word LD2_curr_setup 7460 02dc 00100040 .word 1073745920 7461 02e0 00100140 .word 1073811456 7462 02e4 00640240 .word 1073898496 7463 02e8 00000000 .word UART_DATA ARM GAS /tmp/ccLSPxIe.s page 522 7464 02ec 28100140 .word 1073811496 7465 02f0 00000000 .word SD_SEEK 7466 02f4 00000000 .word SD_SLIDE 7467 02f8 00080240 .word 1073874944 7468 02fc 000C0240 .word 1073875968 7469 0300 00000240 .word 1073872896 7470 0304 00000000 .word .LC0 7471 0308 00000000 .word test 7472 030c 00000000 .word CPU_state 7473 0310 00000000 .word COMMAND 7474 0314 04000000 .word .LC1 7475 0318 00040240 .word 1073873920 7476 031c 00140240 .word 1073878016 7477 .cfi_endproc 7478 .LFE1208: 7480 .section .text.DS1809_Pulse,"ax",%progbits 7481 .align 1 7482 .syntax unified 7483 .thumb 7484 .thumb_func 7486 DS1809_Pulse: 7487 .LVL677: 7488 .LFB1218: 2849:Src/main.c **** for (uint16_t i = 0; i < count; i++) 7489 .loc 1 2849 1 is_stmt 1 view -0 7490 .cfi_startproc 7491 @ args = 0, pretend = 0, frame = 0 7492 @ frame_needed = 0, uses_anonymous_args = 0 2849:Src/main.c **** for (uint16_t i = 0; i < count; i++) 7493 .loc 1 2849 1 is_stmt 0 view .LVU2299 7494 0000 2DE9F041 push {r4, r5, r6, r7, r8, lr} 7495 .LCFI71: 7496 .cfi_def_cfa_offset 24 7497 .cfi_offset 4, -24 7498 .cfi_offset 5, -20 7499 .cfi_offset 6, -16 7500 .cfi_offset 7, -12 7501 .cfi_offset 8, -8 7502 .cfi_offset 14, -4 7503 0004 0746 mov r7, r0 7504 0006 0E46 mov r6, r1 7505 0008 9046 mov r8, r2 7506 000a 1D46 mov r5, r3 2850:Src/main.c **** { 7507 .loc 1 2850 2 is_stmt 1 view .LVU2300 7508 .LBB610: 2850:Src/main.c **** { 7509 .loc 1 2850 7 view .LVU2301 7510 .LVL678: 2850:Src/main.c **** { 7511 .loc 1 2850 16 is_stmt 0 view .LVU2302 7512 000c 0024 movs r4, #0 2850:Src/main.c **** { 7513 .loc 1 2850 2 view .LVU2303 7514 000e 16E0 b .L393 7515 .LVL679: 7516 .L401: ARM GAS /tmp/ccLSPxIe.s page 523 2854:Src/main.c **** } 7517 .loc 1 2854 4 is_stmt 1 view .LVU2304 7518 0010 0022 movs r2, #0 7519 0012 0421 movs r1, #4 7520 0014 1448 ldr r0, .L404 7521 0016 FFF7FEFF bl HAL_GPIO_WritePin 7522 .LVL680: 7523 001a 14E0 b .L394 7524 .L402: 2858:Src/main.c **** } 7525 .loc 1 2858 4 view .LVU2305 7526 001c 0022 movs r2, #0 7527 001e 0821 movs r1, #8 7528 0020 1148 ldr r0, .L404 7529 0022 FFF7FEFF bl HAL_GPIO_WritePin 7530 .LVL681: 7531 0026 10E0 b .L395 7532 .L403: 2863:Src/main.c **** } 7533 .loc 1 2863 4 view .LVU2306 7534 0028 0122 movs r2, #1 7535 002a 0421 movs r1, #4 7536 002c 0E48 ldr r0, .L404 7537 002e FFF7FEFF bl HAL_GPIO_WritePin 7538 .LVL682: 7539 0032 0FE0 b .L396 7540 .L397: 2869:Src/main.c **** } 7541 .loc 1 2869 3 view .LVU2307 7542 0034 2846 mov r0, r5 7543 0036 FFF7FEFF bl HAL_Delay 7544 .LVL683: 2850:Src/main.c **** { 7545 .loc 1 2850 35 discriminator 2 view .LVU2308 7546 003a 0134 adds r4, r4, #1 7547 .LVL684: 2850:Src/main.c **** { 7548 .loc 1 2850 35 is_stmt 0 discriminator 2 view .LVU2309 7549 003c A4B2 uxth r4, r4 7550 .LVL685: 7551 .L393: 2850:Src/main.c **** { 7552 .loc 1 2850 25 is_stmt 1 discriminator 1 view .LVU2310 7553 003e 4445 cmp r4, r8 7554 0040 10D2 bcs .L400 2852:Src/main.c **** { 7555 .loc 1 2852 3 view .LVU2311 2852:Src/main.c **** { 7556 .loc 1 2852 6 is_stmt 0 view .LVU2312 7557 0042 002F cmp r7, #0 7558 0044 E4D1 bne .L401 7559 .L394: 2856:Src/main.c **** { 7560 .loc 1 2856 3 is_stmt 1 view .LVU2313 2856:Src/main.c **** { 7561 .loc 1 2856 6 is_stmt 0 view .LVU2314 7562 0046 002E cmp r6, #0 ARM GAS /tmp/ccLSPxIe.s page 524 7563 0048 E8D1 bne .L402 7564 .L395: 2860:Src/main.c **** if (uc) 7565 .loc 1 2860 3 is_stmt 1 view .LVU2315 7566 004a 2846 mov r0, r5 7567 004c FFF7FEFF bl HAL_Delay 7568 .LVL686: 2861:Src/main.c **** { 7569 .loc 1 2861 3 view .LVU2316 2861:Src/main.c **** { 7570 .loc 1 2861 6 is_stmt 0 view .LVU2317 7571 0050 002F cmp r7, #0 7572 0052 E9D1 bne .L403 7573 .L396: 2865:Src/main.c **** { 7574 .loc 1 2865 3 is_stmt 1 view .LVU2318 2865:Src/main.c **** { 7575 .loc 1 2865 6 is_stmt 0 view .LVU2319 7576 0054 002E cmp r6, #0 7577 0056 EDD0 beq .L397 2867:Src/main.c **** } 7578 .loc 1 2867 4 is_stmt 1 view .LVU2320 7579 0058 0122 movs r2, #1 7580 005a 0821 movs r1, #8 7581 005c 0248 ldr r0, .L404 7582 005e FFF7FEFF bl HAL_GPIO_WritePin 7583 .LVL687: 7584 0062 E7E7 b .L397 7585 .L400: 2867:Src/main.c **** } 7586 .loc 1 2867 4 is_stmt 0 view .LVU2321 7587 .LBE610: 2871:Src/main.c **** 7588 .loc 1 2871 1 view .LVU2322 7589 0064 BDE8F081 pop {r4, r5, r6, r7, r8, pc} 7590 .LVL688: 7591 .L405: 2871:Src/main.c **** 7592 .loc 1 2871 1 view .LVU2323 7593 .align 2 7594 .L404: 7595 0068 00100240 .word 1073876992 7596 .cfi_endproc 7597 .LFE1218: 7599 .section .text.Get_ADC,"ax",%progbits 7600 .align 1 7601 .syntax unified 7602 .thumb 7603 .thumb_func 7605 Get_ADC: 7606 .LVL689: 7607 .LFB1237: 3644:Src/main.c **** uint16_t OUT; 7608 .loc 1 3644 1 is_stmt 1 view -0 7609 .cfi_startproc 7610 @ args = 0, pretend = 0, frame = 0 7611 @ frame_needed = 0, uses_anonymous_args = 0 ARM GAS /tmp/ccLSPxIe.s page 525 3644:Src/main.c **** uint16_t OUT; 7612 .loc 1 3644 1 is_stmt 0 view .LVU2325 7613 0000 10B5 push {r4, lr} 7614 .LCFI72: 7615 .cfi_def_cfa_offset 8 7616 .cfi_offset 4, -8 7617 .cfi_offset 14, -4 7618 0002 0024 movs r4, #0 3645:Src/main.c **** switch (num) 7619 .loc 1 3645 2 is_stmt 1 view .LVU2326 3646:Src/main.c **** { 7620 .loc 1 3646 2 view .LVU2327 7621 0004 0528 cmp r0, #5 7622 0006 2CD8 bhi .L415 7623 0008 DFE800F0 tbb [pc, r0] 7624 .L409: 7625 000c 03 .byte (.L414-.L409)/2 7626 000d 08 .byte (.L413-.L409)/2 7627 000e 12 .byte (.L412-.L409)/2 7628 000f 17 .byte (.L411-.L409)/2 7629 0010 1C .byte (.L410-.L409)/2 7630 0011 26 .byte (.L408-.L409)/2 7631 .p2align 1 7632 .L414: 3649:Src/main.c **** break; 7633 .loc 1 3649 5 view .LVU2328 7634 0012 1548 ldr r0, .L417 7635 .LVL690: 3649:Src/main.c **** break; 7636 .loc 1 3649 5 is_stmt 0 view .LVU2329 7637 0014 FFF7FEFF bl HAL_ADC_Start 7638 .LVL691: 3650:Src/main.c **** case 1: 7639 .loc 1 3650 4 is_stmt 1 view .LVU2330 7640 0018 2046 mov r0, r4 7641 .L407: 7642 .LVL692: 3669:Src/main.c **** } 7643 .loc 1 3669 2 view .LVU2331 3670:Src/main.c **** 7644 .loc 1 3670 1 is_stmt 0 view .LVU2332 7645 001a 10BD pop {r4, pc} 7646 .LVL693: 7647 .L413: 3652:Src/main.c **** OUT = HAL_ADC_GetValue(&hadc1); // Get value adc 7648 .loc 1 3652 5 is_stmt 1 view .LVU2333 7649 001c 124C ldr r4, .L417 7650 001e 6421 movs r1, #100 7651 0020 2046 mov r0, r4 7652 .LVL694: 3652:Src/main.c **** OUT = HAL_ADC_GetValue(&hadc1); // Get value adc 7653 .loc 1 3652 5 is_stmt 0 view .LVU2334 7654 0022 FFF7FEFF bl HAL_ADC_PollForConversion 7655 .LVL695: 3653:Src/main.c **** break; 7656 .loc 1 3653 9 is_stmt 1 view .LVU2335 3653:Src/main.c **** break; ARM GAS /tmp/ccLSPxIe.s page 526 7657 .loc 1 3653 15 is_stmt 0 view .LVU2336 7658 0026 2046 mov r0, r4 7659 0028 FFF7FEFF bl HAL_ADC_GetValue 7660 .LVL696: 3653:Src/main.c **** break; 7661 .loc 1 3653 13 discriminator 1 view .LVU2337 7662 002c 80B2 uxth r0, r0 7663 .LVL697: 3654:Src/main.c **** case 2: 7664 .loc 1 3654 4 is_stmt 1 view .LVU2338 7665 002e F4E7 b .L407 7666 .LVL698: 7667 .L412: 3656:Src/main.c **** break; 7668 .loc 1 3656 5 view .LVU2339 7669 0030 0D48 ldr r0, .L417 7670 .LVL699: 3656:Src/main.c **** break; 7671 .loc 1 3656 5 is_stmt 0 view .LVU2340 7672 0032 FFF7FEFF bl HAL_ADC_Stop 7673 .LVL700: 3657:Src/main.c **** case 3: 7674 .loc 1 3657 4 is_stmt 1 view .LVU2341 7675 0036 2046 mov r0, r4 7676 0038 EFE7 b .L407 7677 .LVL701: 7678 .L411: 3659:Src/main.c **** break; 7679 .loc 1 3659 5 view .LVU2342 7680 003a 0C48 ldr r0, .L417+4 7681 .LVL702: 3659:Src/main.c **** break; 7682 .loc 1 3659 5 is_stmt 0 view .LVU2343 7683 003c FFF7FEFF bl HAL_ADC_Start 7684 .LVL703: 3660:Src/main.c **** case 4: 7685 .loc 1 3660 4 is_stmt 1 view .LVU2344 7686 0040 2046 mov r0, r4 7687 0042 EAE7 b .L407 7688 .LVL704: 7689 .L410: 3662:Src/main.c **** OUT = HAL_ADC_GetValue(&hadc3); // Get value adc 7690 .loc 1 3662 5 view .LVU2345 7691 0044 094C ldr r4, .L417+4 7692 0046 6421 movs r1, #100 7693 0048 2046 mov r0, r4 7694 .LVL705: 3662:Src/main.c **** OUT = HAL_ADC_GetValue(&hadc3); // Get value adc 7695 .loc 1 3662 5 is_stmt 0 view .LVU2346 7696 004a FFF7FEFF bl HAL_ADC_PollForConversion 7697 .LVL706: 3663:Src/main.c **** break; 7698 .loc 1 3663 9 is_stmt 1 view .LVU2347 3663:Src/main.c **** break; 7699 .loc 1 3663 15 is_stmt 0 view .LVU2348 7700 004e 2046 mov r0, r4 7701 0050 FFF7FEFF bl HAL_ADC_GetValue ARM GAS /tmp/ccLSPxIe.s page 527 7702 .LVL707: 3663:Src/main.c **** break; 7703 .loc 1 3663 13 discriminator 1 view .LVU2349 7704 0054 80B2 uxth r0, r0 7705 .LVL708: 3664:Src/main.c **** case 5: 7706 .loc 1 3664 4 is_stmt 1 view .LVU2350 7707 0056 E0E7 b .L407 7708 .LVL709: 7709 .L408: 3666:Src/main.c **** break; 7710 .loc 1 3666 9 view .LVU2351 7711 0058 0448 ldr r0, .L417+4 7712 .LVL710: 3666:Src/main.c **** break; 7713 .loc 1 3666 9 is_stmt 0 view .LVU2352 7714 005a FFF7FEFF bl HAL_ADC_Stop 7715 .LVL711: 3667:Src/main.c **** } 7716 .loc 1 3667 4 is_stmt 1 view .LVU2353 7717 005e 2046 mov r0, r4 7718 0060 DBE7 b .L407 7719 .LVL712: 7720 .L415: 3646:Src/main.c **** { 7721 .loc 1 3646 2 is_stmt 0 view .LVU2354 7722 0062 2046 mov r0, r4 7723 .LVL713: 3646:Src/main.c **** { 7724 .loc 1 3646 2 view .LVU2355 7725 0064 D9E7 b .L407 7726 .L418: 7727 0066 00BF .align 2 7728 .L417: 7729 0068 00000000 .word hadc1 7730 006c 00000000 .word hadc3 7731 .cfi_endproc 7732 .LFE1237: 7734 .section .text.Set_LTEC,"ax",%progbits 7735 .align 1 7736 .global Set_LTEC 7737 .syntax unified 7738 .thumb 7739 .thumb_func 7741 Set_LTEC: 7742 .LVL714: 7743 .LFB1235: 3466:Src/main.c **** uint32_t tmp32; 7744 .loc 1 3466 1 is_stmt 1 view -0 7745 .cfi_startproc 7746 @ args = 0, pretend = 0, frame = 0 7747 @ frame_needed = 0, uses_anonymous_args = 0 3466:Src/main.c **** uint32_t tmp32; 7748 .loc 1 3466 1 is_stmt 0 view .LVU2357 7749 0000 38B5 push {r3, r4, r5, lr} 7750 .LCFI73: 7751 .cfi_def_cfa_offset 16 ARM GAS /tmp/ccLSPxIe.s page 528 7752 .cfi_offset 3, -16 7753 .cfi_offset 4, -12 7754 .cfi_offset 5, -8 7755 .cfi_offset 14, -4 7756 0002 0446 mov r4, r0 7757 0004 0D46 mov r5, r1 3467:Src/main.c **** 7758 .loc 1 3467 2 is_stmt 1 view .LVU2358 3469:Src/main.c **** { 7759 .loc 1 3469 2 view .LVU2359 3469:Src/main.c **** { 7760 .loc 1 3469 5 is_stmt 0 view .LVU2360 7761 0006 0328 cmp r0, #3 7762 0008 18BF it ne 7763 000a 0128 cmpne r0, #1 7764 000c 06D0 beq .L453 7765 .LVL715: 7766 .L420: 3475:Src/main.c **** { 7767 .loc 1 3475 2 is_stmt 1 view .LVU2361 7768 000e 013C subs r4, r4, #1 7769 .LVL716: 3475:Src/main.c **** { 7770 .loc 1 3475 2 is_stmt 0 view .LVU2362 7771 0010 032C cmp r4, #3 7772 0012 2ED8 bhi .L421 7773 0014 DFE804F0 tbb [pc, r4] 7774 .L423: 7775 0018 0D .byte (.L426-.L423)/2 7776 0019 45 .byte (.L425-.L423)/2 7777 001a 65 .byte (.L424-.L423)/2 7778 001b 86 .byte (.L422-.L423)/2 7779 .LVL717: 7780 .p2align 1 7781 .L453: 3471:Src/main.c **** HAL_GPIO_WritePin(AD9102_CS_GPIO_Port, AD9102_CS_Pin, GPIO_PIN_SET); 7782 .loc 1 3471 3 is_stmt 1 view .LVU2363 7783 001c 0121 movs r1, #1 7784 .LVL718: 3471:Src/main.c **** HAL_GPIO_WritePin(AD9102_CS_GPIO_Port, AD9102_CS_Pin, GPIO_PIN_SET); 7785 .loc 1 3471 3 is_stmt 0 view .LVU2364 7786 001e 0220 movs r0, #2 7787 .LVL719: 3471:Src/main.c **** HAL_GPIO_WritePin(AD9102_CS_GPIO_Port, AD9102_CS_Pin, GPIO_PIN_SET); 7788 .loc 1 3471 3 view .LVU2365 7789 0020 FFF7FEFF bl SPI2_SetMode 7790 .LVL720: 3472:Src/main.c **** } 7791 .loc 1 3472 3 is_stmt 1 view .LVU2366 7792 0024 0122 movs r2, #1 7793 0026 4FF48051 mov r1, #4096 7794 002a 4F48 ldr r0, .L454 7795 002c FFF7FEFF bl HAL_GPIO_WritePin 7796 .LVL721: 7797 0030 EDE7 b .L420 7798 .LVL722: 7799 .L426: ARM GAS /tmp/ccLSPxIe.s page 529 3478:Src/main.c **** //tmp32=0; 7800 .loc 1 3478 4 view .LVU2367 7801 0032 0022 movs r2, #0 7802 0034 4FF48041 mov r1, #16384 7803 0038 4B48 ldr r0, .L454 7804 003a FFF7FEFF bl HAL_GPIO_WritePin 7805 .LVL723: 3481:Src/main.c **** while((!LL_SPI_IsActiveFlag_TXE(SPI2))&&(tmp32<=500)) {tmp32++;}//When trans. last data cycle wi 7806 .loc 1 3481 4 view .LVU2368 3482:Src/main.c **** LL_SPI_TransmitData16(SPI2, DATA);//Transmit word to Laser1 DAC 7807 .loc 1 3482 4 view .LVU2369 3481:Src/main.c **** while((!LL_SPI_IsActiveFlag_TXE(SPI2))&&(tmp32<=500)) {tmp32++;}//When trans. last data cycle wi 7808 .loc 1 3481 10 is_stmt 0 view .LVU2370 7809 003e 0022 movs r2, #0 7810 .LVL724: 7811 .L427: 3482:Src/main.c **** LL_SPI_TransmitData16(SPI2, DATA);//Transmit word to Laser1 DAC 7812 .loc 1 3482 42 is_stmt 1 discriminator 1 view .LVU2371 7813 .LBB611: 7814 .LBI611: 916:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 7815 .loc 4 916 26 view .LVU2372 7816 .LBB612: 918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 7817 .loc 4 918 3 view .LVU2373 918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 7818 .loc 4 918 12 is_stmt 0 view .LVU2374 7819 0040 4A4B ldr r3, .L454+4 7820 0042 9B68 ldr r3, [r3, #8] 918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 7821 .loc 4 918 66 view .LVU2375 7822 0044 13F0020F tst r3, #2 7823 0048 04D1 bne .L428 7824 .LVL725: 918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 7825 .loc 4 918 66 view .LVU2376 7826 .LBE612: 7827 .LBE611: 3482:Src/main.c **** LL_SPI_TransmitData16(SPI2, DATA);//Transmit word to Laser1 DAC 7828 .loc 1 3482 42 discriminator 2 view .LVU2377 7829 004a B2F5FA7F cmp r2, #500 7830 004e 01D8 bhi .L428 3482:Src/main.c **** LL_SPI_TransmitData16(SPI2, DATA);//Transmit word to Laser1 DAC 7831 .loc 1 3482 59 is_stmt 1 discriminator 3 view .LVU2378 3482:Src/main.c **** LL_SPI_TransmitData16(SPI2, DATA);//Transmit word to Laser1 DAC 7832 .loc 1 3482 64 is_stmt 0 discriminator 3 view .LVU2379 7833 0050 0132 adds r2, r2, #1 7834 .LVL726: 3482:Src/main.c **** LL_SPI_TransmitData16(SPI2, DATA);//Transmit word to Laser1 DAC 7835 .loc 1 3482 64 discriminator 3 view .LVU2380 7836 0052 F5E7 b .L427 7837 .L428: 3483:Src/main.c **** tmp32 = 0; 7838 .loc 1 3483 4 is_stmt 1 view .LVU2381 7839 .LVL727: 7840 .LBB613: 7841 .LBI613: ARM GAS /tmp/ccLSPxIe.s page 530 1373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 7842 .loc 4 1373 22 view .LVU2382 7843 .LBB614: 1376:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** *spidr = TxData; 7844 .loc 4 1376 3 view .LVU2383 7845 .loc 4 1377 3 view .LVU2384 7846 .loc 4 1377 10 is_stmt 0 view .LVU2385 7847 0054 454B ldr r3, .L454+4 7848 0056 9D81 strh r5, [r3, #12] @ movhi 7849 .LVL728: 7850 .loc 4 1377 10 view .LVU2386 7851 .LBE614: 7852 .LBE613: 3484:Src/main.c **** while((!LL_SPI_IsActiveFlag_RXNE(SPI2))&&(tmp32<=500)) {tmp32++;}//When trans. last data cycle w 7853 .loc 1 3484 4 is_stmt 1 view .LVU2387 3485:Src/main.c **** (void) SPI2->DR; 7854 .loc 1 3485 4 view .LVU2388 3484:Src/main.c **** while((!LL_SPI_IsActiveFlag_RXNE(SPI2))&&(tmp32<=500)) {tmp32++;}//When trans. last data cycle w 7855 .loc 1 3484 10 is_stmt 0 view .LVU2389 7856 0058 0022 movs r2, #0 7857 .LVL729: 7858 .L430: 3485:Src/main.c **** (void) SPI2->DR; 7859 .loc 1 3485 43 is_stmt 1 discriminator 1 view .LVU2390 7860 .LBB615: 7861 .LBI615: 905:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 7862 .loc 4 905 26 view .LVU2391 7863 .LBB616: 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 7864 .loc 4 907 3 view .LVU2392 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 7865 .loc 4 907 12 is_stmt 0 view .LVU2393 7866 005a 444B ldr r3, .L454+4 7867 005c 9B68 ldr r3, [r3, #8] 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 7868 .loc 4 907 68 view .LVU2394 7869 005e 13F0010F tst r3, #1 7870 0062 04D1 bne .L431 7871 .LVL730: 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 7872 .loc 4 907 68 view .LVU2395 7873 .LBE616: 7874 .LBE615: 3485:Src/main.c **** (void) SPI2->DR; 7875 .loc 1 3485 43 discriminator 2 view .LVU2396 7876 0064 B2F5FA7F cmp r2, #500 7877 0068 01D8 bhi .L431 3485:Src/main.c **** (void) SPI2->DR; 7878 .loc 1 3485 60 is_stmt 1 discriminator 3 view .LVU2397 3485:Src/main.c **** (void) SPI2->DR; 7879 .loc 1 3485 65 is_stmt 0 discriminator 3 view .LVU2398 7880 006a 0132 adds r2, r2, #1 7881 .LVL731: 3485:Src/main.c **** (void) SPI2->DR; 7882 .loc 1 3485 65 discriminator 3 view .LVU2399 7883 006c F5E7 b .L430 ARM GAS /tmp/ccLSPxIe.s page 531 7884 .L431: 3486:Src/main.c **** break; 7885 .loc 1 3486 4 is_stmt 1 view .LVU2400 7886 006e 3F4B ldr r3, .L454+4 7887 0070 DB68 ldr r3, [r3, #12] 3487:Src/main.c **** case 2: 7888 .loc 1 3487 3 view .LVU2401 7889 .LVL732: 7890 .L421: 3523:Src/main.c **** HAL_GPIO_WritePin(DAC_LD2_CS_GPIO_Port, DAC_LD2_CS_Pin, GPIO_PIN_SET);//End operation with LDAC2 7891 .loc 1 3523 2 view .LVU2402 7892 0072 0122 movs r2, #1 7893 0074 4FF48041 mov r1, #16384 7894 0078 3B48 ldr r0, .L454 7895 007a FFF7FEFF bl HAL_GPIO_WritePin 7896 .LVL733: 3524:Src/main.c **** HAL_GPIO_WritePin(DAC_TEC1_CS_GPIO_Port, DAC_TEC1_CS_Pin, GPIO_PIN_SET);//End operation with TEC1 7897 .loc 1 3524 2 view .LVU2403 7898 007e 0122 movs r2, #1 7899 0080 4021 movs r1, #64 7900 0082 3B48 ldr r0, .L454+8 7901 0084 FFF7FEFF bl HAL_GPIO_WritePin 7902 .LVL734: 3525:Src/main.c **** HAL_GPIO_WritePin(DAC_TEC2_CS_GPIO_Port, DAC_TEC2_CS_Pin, GPIO_PIN_SET);//End operation with TEC2 7903 .loc 1 3525 2 view .LVU2404 7904 0088 0122 movs r2, #1 7905 008a 4FF48051 mov r1, #4096 7906 008e 3948 ldr r0, .L454+12 7907 0090 FFF7FEFF bl HAL_GPIO_WritePin 7908 .LVL735: 3526:Src/main.c **** } 7909 .loc 1 3526 2 view .LVU2405 7910 0094 0122 movs r2, #1 7911 0096 4FF48071 mov r1, #256 7912 009a 3748 ldr r0, .L454+16 7913 009c FFF7FEFF bl HAL_GPIO_WritePin 7914 .LVL736: 3527:Src/main.c **** static uint16_t MPhD_T(uint8_t num) 7915 .loc 1 3527 1 is_stmt 0 view .LVU2406 7916 00a0 38BD pop {r3, r4, r5, pc} 7917 .LVL737: 7918 .L425: 3490:Src/main.c **** //tmp32=0; 7919 .loc 1 3490 4 is_stmt 1 view .LVU2407 7920 00a2 0022 movs r2, #0 7921 00a4 4021 movs r1, #64 7922 00a6 3248 ldr r0, .L454+8 7923 00a8 FFF7FEFF bl HAL_GPIO_WritePin 7924 .LVL738: 3493:Src/main.c **** while((!LL_SPI_IsActiveFlag_TXE(SPI6))&&(tmp32<=500)) {tmp32++;}//When trans. last data cycle wi 7925 .loc 1 3493 4 view .LVU2408 3494:Src/main.c **** LL_SPI_TransmitData16(SPI6, DATA);//Transmit word to Laser1 DAC 7926 .loc 1 3494 4 view .LVU2409 3493:Src/main.c **** while((!LL_SPI_IsActiveFlag_TXE(SPI6))&&(tmp32<=500)) {tmp32++;}//When trans. last data cycle wi 7927 .loc 1 3493 10 is_stmt 0 view .LVU2410 7928 00ac 0022 movs r2, #0 7929 .LVL739: ARM GAS /tmp/ccLSPxIe.s page 532 7930 .L433: 3494:Src/main.c **** LL_SPI_TransmitData16(SPI6, DATA);//Transmit word to Laser1 DAC 7931 .loc 1 3494 42 is_stmt 1 discriminator 1 view .LVU2411 7932 .LBB617: 7933 .LBI617: 916:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 7934 .loc 4 916 26 view .LVU2412 7935 .LBB618: 918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 7936 .loc 4 918 3 view .LVU2413 918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 7937 .loc 4 918 12 is_stmt 0 view .LVU2414 7938 00ae 334B ldr r3, .L454+20 7939 00b0 9B68 ldr r3, [r3, #8] 918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 7940 .loc 4 918 66 view .LVU2415 7941 00b2 13F0020F tst r3, #2 7942 00b6 04D1 bne .L434 7943 .LVL740: 918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 7944 .loc 4 918 66 view .LVU2416 7945 .LBE618: 7946 .LBE617: 3494:Src/main.c **** LL_SPI_TransmitData16(SPI6, DATA);//Transmit word to Laser1 DAC 7947 .loc 1 3494 42 discriminator 2 view .LVU2417 7948 00b8 B2F5FA7F cmp r2, #500 7949 00bc 01D8 bhi .L434 3494:Src/main.c **** LL_SPI_TransmitData16(SPI6, DATA);//Transmit word to Laser1 DAC 7950 .loc 1 3494 59 is_stmt 1 discriminator 3 view .LVU2418 3494:Src/main.c **** LL_SPI_TransmitData16(SPI6, DATA);//Transmit word to Laser1 DAC 7951 .loc 1 3494 64 is_stmt 0 discriminator 3 view .LVU2419 7952 00be 0132 adds r2, r2, #1 7953 .LVL741: 3494:Src/main.c **** LL_SPI_TransmitData16(SPI6, DATA);//Transmit word to Laser1 DAC 7954 .loc 1 3494 64 discriminator 3 view .LVU2420 7955 00c0 F5E7 b .L433 7956 .L434: 3495:Src/main.c **** tmp32 = 0; 7957 .loc 1 3495 4 is_stmt 1 view .LVU2421 7958 .LVL742: 7959 .LBB619: 7960 .LBI619: 1373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 7961 .loc 4 1373 22 view .LVU2422 7962 .LBB620: 1376:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** *spidr = TxData; 7963 .loc 4 1376 3 view .LVU2423 7964 .loc 4 1377 3 view .LVU2424 7965 .loc 4 1377 10 is_stmt 0 view .LVU2425 7966 00c2 2E4B ldr r3, .L454+20 7967 00c4 9D81 strh r5, [r3, #12] @ movhi 7968 .LVL743: 7969 .loc 4 1377 10 view .LVU2426 7970 .LBE620: 7971 .LBE619: 3496:Src/main.c **** while((!LL_SPI_IsActiveFlag_RXNE(SPI6))&&(tmp32<=500)) {tmp32++;}//When trans. last data cycle w 7972 .loc 1 3496 4 is_stmt 1 view .LVU2427 ARM GAS /tmp/ccLSPxIe.s page 533 3497:Src/main.c **** (void) SPI6->DR; 7973 .loc 1 3497 4 view .LVU2428 3496:Src/main.c **** while((!LL_SPI_IsActiveFlag_RXNE(SPI6))&&(tmp32<=500)) {tmp32++;}//When trans. last data cycle w 7974 .loc 1 3496 10 is_stmt 0 view .LVU2429 7975 00c6 0022 movs r2, #0 7976 .LVL744: 7977 .L436: 3497:Src/main.c **** (void) SPI6->DR; 7978 .loc 1 3497 43 is_stmt 1 discriminator 1 view .LVU2430 7979 .LBB621: 7980 .LBI621: 905:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 7981 .loc 4 905 26 view .LVU2431 7982 .LBB622: 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 7983 .loc 4 907 3 view .LVU2432 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 7984 .loc 4 907 12 is_stmt 0 view .LVU2433 7985 00c8 2C4B ldr r3, .L454+20 7986 00ca 9B68 ldr r3, [r3, #8] 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 7987 .loc 4 907 68 view .LVU2434 7988 00cc 13F0010F tst r3, #1 7989 00d0 04D1 bne .L437 7990 .LVL745: 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 7991 .loc 4 907 68 view .LVU2435 7992 .LBE622: 7993 .LBE621: 3497:Src/main.c **** (void) SPI6->DR; 7994 .loc 1 3497 43 discriminator 2 view .LVU2436 7995 00d2 B2F5FA7F cmp r2, #500 7996 00d6 01D8 bhi .L437 3497:Src/main.c **** (void) SPI6->DR; 7997 .loc 1 3497 60 is_stmt 1 discriminator 3 view .LVU2437 3497:Src/main.c **** (void) SPI6->DR; 7998 .loc 1 3497 65 is_stmt 0 discriminator 3 view .LVU2438 7999 00d8 0132 adds r2, r2, #1 8000 .LVL746: 3497:Src/main.c **** (void) SPI6->DR; 8001 .loc 1 3497 65 discriminator 3 view .LVU2439 8002 00da F5E7 b .L436 8003 .L437: 3498:Src/main.c **** break; 8004 .loc 1 3498 4 is_stmt 1 view .LVU2440 8005 00dc 274B ldr r3, .L454+20 8006 00de DB68 ldr r3, [r3, #12] 3499:Src/main.c **** case 3: 8007 .loc 1 3499 3 view .LVU2441 8008 00e0 C7E7 b .L421 8009 .LVL747: 8010 .L424: 3501:Src/main.c **** //tmp32=0; 8011 .loc 1 3501 4 view .LVU2442 8012 00e2 0022 movs r2, #0 8013 00e4 4FF48051 mov r1, #4096 8014 00e8 2248 ldr r0, .L454+12 ARM GAS /tmp/ccLSPxIe.s page 534 8015 00ea FFF7FEFF bl HAL_GPIO_WritePin 8016 .LVL748: 3504:Src/main.c **** while((!LL_SPI_IsActiveFlag_TXE(SPI2))&&(tmp32<=500)) {tmp32++;}//When trans. last data cycle wi 8017 .loc 1 3504 4 view .LVU2443 3505:Src/main.c **** LL_SPI_TransmitData16(SPI2, DATA);//Transmit word to Laser1 DAC 8018 .loc 1 3505 4 view .LVU2444 3504:Src/main.c **** while((!LL_SPI_IsActiveFlag_TXE(SPI2))&&(tmp32<=500)) {tmp32++;}//When trans. last data cycle wi 8019 .loc 1 3504 10 is_stmt 0 view .LVU2445 8020 00ee 0022 movs r2, #0 8021 .LVL749: 8022 .L439: 3505:Src/main.c **** LL_SPI_TransmitData16(SPI2, DATA);//Transmit word to Laser1 DAC 8023 .loc 1 3505 42 is_stmt 1 discriminator 1 view .LVU2446 8024 .LBB623: 8025 .LBI623: 916:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 8026 .loc 4 916 26 view .LVU2447 8027 .LBB624: 918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 8028 .loc 4 918 3 view .LVU2448 918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 8029 .loc 4 918 12 is_stmt 0 view .LVU2449 8030 00f0 1E4B ldr r3, .L454+4 8031 00f2 9B68 ldr r3, [r3, #8] 918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 8032 .loc 4 918 66 view .LVU2450 8033 00f4 13F0020F tst r3, #2 8034 00f8 04D1 bne .L440 8035 .LVL750: 918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 8036 .loc 4 918 66 view .LVU2451 8037 .LBE624: 8038 .LBE623: 3505:Src/main.c **** LL_SPI_TransmitData16(SPI2, DATA);//Transmit word to Laser1 DAC 8039 .loc 1 3505 42 discriminator 2 view .LVU2452 8040 00fa B2F5FA7F cmp r2, #500 8041 00fe 01D8 bhi .L440 3505:Src/main.c **** LL_SPI_TransmitData16(SPI2, DATA);//Transmit word to Laser1 DAC 8042 .loc 1 3505 59 is_stmt 1 discriminator 3 view .LVU2453 3505:Src/main.c **** LL_SPI_TransmitData16(SPI2, DATA);//Transmit word to Laser1 DAC 8043 .loc 1 3505 64 is_stmt 0 discriminator 3 view .LVU2454 8044 0100 0132 adds r2, r2, #1 8045 .LVL751: 3505:Src/main.c **** LL_SPI_TransmitData16(SPI2, DATA);//Transmit word to Laser1 DAC 8046 .loc 1 3505 64 discriminator 3 view .LVU2455 8047 0102 F5E7 b .L439 8048 .L440: 3506:Src/main.c **** tmp32 = 0; 8049 .loc 1 3506 4 is_stmt 1 view .LVU2456 8050 .LVL752: 8051 .LBB625: 8052 .LBI625: 1373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 8053 .loc 4 1373 22 view .LVU2457 8054 .LBB626: 1376:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** *spidr = TxData; 8055 .loc 4 1376 3 view .LVU2458 ARM GAS /tmp/ccLSPxIe.s page 535 8056 .loc 4 1377 3 view .LVU2459 8057 .loc 4 1377 10 is_stmt 0 view .LVU2460 8058 0104 194B ldr r3, .L454+4 8059 0106 9D81 strh r5, [r3, #12] @ movhi 8060 .LVL753: 8061 .loc 4 1377 10 view .LVU2461 8062 .LBE626: 8063 .LBE625: 3507:Src/main.c **** while((!LL_SPI_IsActiveFlag_RXNE(SPI2))&&(tmp32<=500)) {tmp32++;}//When trans. last data cycle w 8064 .loc 1 3507 4 is_stmt 1 view .LVU2462 3508:Src/main.c **** (void) SPI2->DR; 8065 .loc 1 3508 4 view .LVU2463 3507:Src/main.c **** while((!LL_SPI_IsActiveFlag_RXNE(SPI2))&&(tmp32<=500)) {tmp32++;}//When trans. last data cycle w 8066 .loc 1 3507 10 is_stmt 0 view .LVU2464 8067 0108 0022 movs r2, #0 8068 .LVL754: 8069 .L442: 3508:Src/main.c **** (void) SPI2->DR; 8070 .loc 1 3508 43 is_stmt 1 discriminator 1 view .LVU2465 8071 .LBB627: 8072 .LBI627: 905:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 8073 .loc 4 905 26 view .LVU2466 8074 .LBB628: 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 8075 .loc 4 907 3 view .LVU2467 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 8076 .loc 4 907 12 is_stmt 0 view .LVU2468 8077 010a 184B ldr r3, .L454+4 8078 010c 9B68 ldr r3, [r3, #8] 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 8079 .loc 4 907 68 view .LVU2469 8080 010e 13F0010F tst r3, #1 8081 0112 04D1 bne .L443 8082 .LVL755: 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 8083 .loc 4 907 68 view .LVU2470 8084 .LBE628: 8085 .LBE627: 3508:Src/main.c **** (void) SPI2->DR; 8086 .loc 1 3508 43 discriminator 2 view .LVU2471 8087 0114 B2F5FA7F cmp r2, #500 8088 0118 01D8 bhi .L443 3508:Src/main.c **** (void) SPI2->DR; 8089 .loc 1 3508 60 is_stmt 1 discriminator 3 view .LVU2472 3508:Src/main.c **** (void) SPI2->DR; 8090 .loc 1 3508 65 is_stmt 0 discriminator 3 view .LVU2473 8091 011a 0132 adds r2, r2, #1 8092 .LVL756: 3508:Src/main.c **** (void) SPI2->DR; 8093 .loc 1 3508 65 discriminator 3 view .LVU2474 8094 011c F5E7 b .L442 8095 .L443: 3509:Src/main.c **** break; 8096 .loc 1 3509 4 is_stmt 1 view .LVU2475 8097 011e 134B ldr r3, .L454+4 8098 0120 DB68 ldr r3, [r3, #12] ARM GAS /tmp/ccLSPxIe.s page 536 3510:Src/main.c **** case 4: 8099 .loc 1 3510 3 view .LVU2476 8100 0122 A6E7 b .L421 8101 .LVL757: 8102 .L422: 3512:Src/main.c **** //tmp32=0; 8103 .loc 1 3512 4 view .LVU2477 8104 0124 0022 movs r2, #0 8105 0126 4FF48071 mov r1, #256 8106 012a 1348 ldr r0, .L454+16 8107 012c FFF7FEFF bl HAL_GPIO_WritePin 8108 .LVL758: 3515:Src/main.c **** while((!LL_SPI_IsActiveFlag_TXE(SPI6))&&(tmp32<=500)) {tmp32++;}//When trans. last data cycle wi 8109 .loc 1 3515 4 view .LVU2478 3516:Src/main.c **** LL_SPI_TransmitData16(SPI6, DATA);//Transmit word to Laser1 DAC 8110 .loc 1 3516 4 view .LVU2479 3515:Src/main.c **** while((!LL_SPI_IsActiveFlag_TXE(SPI6))&&(tmp32<=500)) {tmp32++;}//When trans. last data cycle wi 8111 .loc 1 3515 10 is_stmt 0 view .LVU2480 8112 0130 0022 movs r2, #0 8113 .LVL759: 8114 .L445: 3516:Src/main.c **** LL_SPI_TransmitData16(SPI6, DATA);//Transmit word to Laser1 DAC 8115 .loc 1 3516 42 is_stmt 1 discriminator 1 view .LVU2481 8116 .LBB629: 8117 .LBI629: 916:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 8118 .loc 4 916 26 view .LVU2482 8119 .LBB630: 918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 8120 .loc 4 918 3 view .LVU2483 918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 8121 .loc 4 918 12 is_stmt 0 view .LVU2484 8122 0132 124B ldr r3, .L454+20 8123 0134 9B68 ldr r3, [r3, #8] 918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 8124 .loc 4 918 66 view .LVU2485 8125 0136 13F0020F tst r3, #2 8126 013a 04D1 bne .L446 8127 .LVL760: 918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 8128 .loc 4 918 66 view .LVU2486 8129 .LBE630: 8130 .LBE629: 3516:Src/main.c **** LL_SPI_TransmitData16(SPI6, DATA);//Transmit word to Laser1 DAC 8131 .loc 1 3516 42 discriminator 2 view .LVU2487 8132 013c B2F5FA7F cmp r2, #500 8133 0140 01D8 bhi .L446 3516:Src/main.c **** LL_SPI_TransmitData16(SPI6, DATA);//Transmit word to Laser1 DAC 8134 .loc 1 3516 59 is_stmt 1 discriminator 3 view .LVU2488 3516:Src/main.c **** LL_SPI_TransmitData16(SPI6, DATA);//Transmit word to Laser1 DAC 8135 .loc 1 3516 64 is_stmt 0 discriminator 3 view .LVU2489 8136 0142 0132 adds r2, r2, #1 8137 .LVL761: 3516:Src/main.c **** LL_SPI_TransmitData16(SPI6, DATA);//Transmit word to Laser1 DAC 8138 .loc 1 3516 64 discriminator 3 view .LVU2490 8139 0144 F5E7 b .L445 8140 .L446: ARM GAS /tmp/ccLSPxIe.s page 537 3517:Src/main.c **** tmp32 = 0; 8141 .loc 1 3517 4 is_stmt 1 view .LVU2491 8142 .LVL762: 8143 .LBB631: 8144 .LBI631: 1373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 8145 .loc 4 1373 22 view .LVU2492 8146 .LBB632: 1376:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** *spidr = TxData; 8147 .loc 4 1376 3 view .LVU2493 8148 .loc 4 1377 3 view .LVU2494 8149 .loc 4 1377 10 is_stmt 0 view .LVU2495 8150 0146 0D4B ldr r3, .L454+20 8151 0148 9D81 strh r5, [r3, #12] @ movhi 8152 .LVL763: 8153 .loc 4 1377 10 view .LVU2496 8154 .LBE632: 8155 .LBE631: 3518:Src/main.c **** while((!LL_SPI_IsActiveFlag_RXNE(SPI6))&&(tmp32<=500)) {tmp32++;}//When trans. last data cycle w 8156 .loc 1 3518 4 is_stmt 1 view .LVU2497 3519:Src/main.c **** (void) SPI6->DR; 8157 .loc 1 3519 4 view .LVU2498 3518:Src/main.c **** while((!LL_SPI_IsActiveFlag_RXNE(SPI6))&&(tmp32<=500)) {tmp32++;}//When trans. last data cycle w 8158 .loc 1 3518 10 is_stmt 0 view .LVU2499 8159 014a 0022 movs r2, #0 8160 .LVL764: 8161 .L448: 3519:Src/main.c **** (void) SPI6->DR; 8162 .loc 1 3519 43 is_stmt 1 discriminator 1 view .LVU2500 8163 .LBB633: 8164 .LBI633: 905:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 8165 .loc 4 905 26 view .LVU2501 8166 .LBB634: 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 8167 .loc 4 907 3 view .LVU2502 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 8168 .loc 4 907 12 is_stmt 0 view .LVU2503 8169 014c 0B4B ldr r3, .L454+20 8170 014e 9B68 ldr r3, [r3, #8] 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 8171 .loc 4 907 68 view .LVU2504 8172 0150 13F0010F tst r3, #1 8173 0154 04D1 bne .L449 8174 .LVL765: 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 8175 .loc 4 907 68 view .LVU2505 8176 .LBE634: 8177 .LBE633: 3519:Src/main.c **** (void) SPI6->DR; 8178 .loc 1 3519 43 discriminator 2 view .LVU2506 8179 0156 B2F5FA7F cmp r2, #500 8180 015a 01D8 bhi .L449 3519:Src/main.c **** (void) SPI6->DR; 8181 .loc 1 3519 60 is_stmt 1 discriminator 3 view .LVU2507 3519:Src/main.c **** (void) SPI6->DR; 8182 .loc 1 3519 65 is_stmt 0 discriminator 3 view .LVU2508 ARM GAS /tmp/ccLSPxIe.s page 538 8183 015c 0132 adds r2, r2, #1 8184 .LVL766: 3519:Src/main.c **** (void) SPI6->DR; 8185 .loc 1 3519 65 discriminator 3 view .LVU2509 8186 015e F5E7 b .L448 8187 .L449: 3520:Src/main.c **** break; 8188 .loc 1 3520 4 is_stmt 1 view .LVU2510 8189 0160 064B ldr r3, .L454+20 8190 0162 DB68 ldr r3, [r3, #12] 3521:Src/main.c **** } 8191 .loc 1 3521 3 view .LVU2511 8192 0164 85E7 b .L421 8193 .L455: 8194 0166 00BF .align 2 8195 .L454: 8196 0168 00040240 .word 1073873920 8197 016c 00380040 .word 1073756160 8198 0170 00000240 .word 1073872896 8199 0174 000C0240 .word 1073875968 8200 0178 00100240 .word 1073876992 8201 017c 00540140 .word 1073828864 8202 .cfi_endproc 8203 .LFE1235: 8205 .section .text.Decode_uart,"ax",%progbits 8206 .align 1 8207 .syntax unified 8208 .thumb 8209 .thumb_func 8211 Decode_uart: 8212 .LVL767: 8213 .LFB1209: 2485:Src/main.c **** // uint8_t *temp1; 8214 .loc 1 2485 1 view -0 8215 .cfi_startproc 8216 @ args = 0, pretend = 0, frame = 0 8217 @ frame_needed = 0, uses_anonymous_args = 0 2485:Src/main.c **** // uint8_t *temp1; 8218 .loc 1 2485 1 is_stmt 0 view .LVU2513 8219 0000 2DE9F843 push {r3, r4, r5, r6, r7, r8, r9, lr} 8220 .LCFI74: 8221 .cfi_def_cfa_offset 32 8222 .cfi_offset 3, -32 8223 .cfi_offset 4, -28 8224 .cfi_offset 5, -24 8225 .cfi_offset 6, -20 8226 .cfi_offset 7, -16 8227 .cfi_offset 8, -12 8228 .cfi_offset 9, -8 8229 .cfi_offset 14, -4 8230 0004 0546 mov r5, r0 8231 0006 0F46 mov r7, r1 8232 0008 1646 mov r6, r2 8233 000a 1C46 mov r4, r3 2487:Src/main.c **** 8234 .loc 1 2487 2 is_stmt 1 view .LVU2514 2492:Src/main.c **** if ((HAL_GPIO_ReadPin(SDMMC1_EN_GPIO_Port, SDMMC1_EN_Pin) == GPIO_PIN_RESET)&& ARM GAS /tmp/ccLSPxIe.s page 539 8235 .loc 1 2492 2 view .LVU2515 2492:Src/main.c **** if ((HAL_GPIO_ReadPin(SDMMC1_EN_GPIO_Port, SDMMC1_EN_Pin) == GPIO_PIN_RESET)&& 8236 .loc 1 2492 6 is_stmt 0 view .LVU2516 8237 000c AF4B ldr r3, .L480 8238 .LVL768: 2492:Src/main.c **** if ((HAL_GPIO_ReadPin(SDMMC1_EN_GPIO_Port, SDMMC1_EN_Pin) == GPIO_PIN_RESET)&& 8239 .loc 1 2492 6 view .LVU2517 8240 000e 0022 movs r2, #0 8241 .LVL769: 2492:Src/main.c **** if ((HAL_GPIO_ReadPin(SDMMC1_EN_GPIO_Port, SDMMC1_EN_Pin) == GPIO_PIN_RESET)&& 8242 .loc 1 2492 6 view .LVU2518 8243 0010 1A60 str r2, [r3] 2493:Src/main.c **** (HAL_GPIO_ReadPin(USB_FLAG_GPIO_Port, USB_FLAG_Pin) == GPIO_PIN_SET))//if exist sd && connect u 8244 .loc 1 2493 2 is_stmt 1 view .LVU2519 2493:Src/main.c **** (HAL_GPIO_ReadPin(USB_FLAG_GPIO_Port, USB_FLAG_Pin) == GPIO_PIN_SET))//if exist sd && connect u 8245 .loc 1 2493 7 is_stmt 0 view .LVU2520 8246 0012 0121 movs r1, #1 8247 .LVL770: 2493:Src/main.c **** (HAL_GPIO_ReadPin(USB_FLAG_GPIO_Port, USB_FLAG_Pin) == GPIO_PIN_SET))//if exist sd && connect u 8248 .loc 1 2493 7 view .LVU2521 8249 0014 AE48 ldr r0, .L480+4 8250 .LVL771: 2493:Src/main.c **** (HAL_GPIO_ReadPin(USB_FLAG_GPIO_Port, USB_FLAG_Pin) == GPIO_PIN_SET))//if exist sd && connect u 8251 .loc 1 2493 7 view .LVU2522 8252 0016 FFF7FEFF bl HAL_GPIO_ReadPin 8253 .LVL772: 2493:Src/main.c **** (HAL_GPIO_ReadPin(USB_FLAG_GPIO_Port, USB_FLAG_Pin) == GPIO_PIN_SET))//if exist sd && connect u 8254 .loc 1 2493 5 discriminator 1 view .LVU2523 8255 001a 0028 cmp r0, #0 8256 001c 00F0D280 beq .L477 8257 .L457: 2508:Src/main.c **** Curr_setup->WORK_EN = ((uint8_t)((*temp2)>>0))&0x01; 8258 .loc 1 2508 2 is_stmt 1 view .LVU2524 8259 .LVL773: 2509:Src/main.c **** Curr_setup->U5V1_EN = ((uint8_t)((*temp2)>>1))&0x01; 8260 .loc 1 2509 2 view .LVU2525 2509:Src/main.c **** Curr_setup->U5V1_EN = ((uint8_t)((*temp2)>>1))&0x01; 8261 .loc 1 2509 36 is_stmt 0 view .LVU2526 8262 0020 2B88 ldrh r3, [r5] 2509:Src/main.c **** Curr_setup->U5V1_EN = ((uint8_t)((*temp2)>>1))&0x01; 8263 .loc 1 2509 48 view .LVU2527 8264 0022 03F00103 and r3, r3, #1 2509:Src/main.c **** Curr_setup->U5V1_EN = ((uint8_t)((*temp2)>>1))&0x01; 8265 .loc 1 2509 22 view .LVU2528 8266 0026 2370 strb r3, [r4] 2510:Src/main.c **** Curr_setup->U5V2_EN = ((uint8_t)((*temp2)>>2))&0x01; 8267 .loc 1 2510 2 is_stmt 1 view .LVU2529 2510:Src/main.c **** Curr_setup->U5V2_EN = ((uint8_t)((*temp2)>>2))&0x01; 8268 .loc 1 2510 36 is_stmt 0 view .LVU2530 8269 0028 2B88 ldrh r3, [r5] 2510:Src/main.c **** Curr_setup->U5V2_EN = ((uint8_t)((*temp2)>>2))&0x01; 8270 .loc 1 2510 48 view .LVU2531 8271 002a C3F34003 ubfx r3, r3, #1, #1 2510:Src/main.c **** Curr_setup->U5V2_EN = ((uint8_t)((*temp2)>>2))&0x01; 8272 .loc 1 2510 22 view .LVU2532 8273 002e 6370 strb r3, [r4, #1] 2511:Src/main.c **** Curr_setup->LD1_EN = ((uint8_t)((*temp2)>>3))&0x01; ARM GAS /tmp/ccLSPxIe.s page 540 8274 .loc 1 2511 2 is_stmt 1 view .LVU2533 2511:Src/main.c **** Curr_setup->LD1_EN = ((uint8_t)((*temp2)>>3))&0x01; 8275 .loc 1 2511 36 is_stmt 0 view .LVU2534 8276 0030 2B88 ldrh r3, [r5] 2511:Src/main.c **** Curr_setup->LD1_EN = ((uint8_t)((*temp2)>>3))&0x01; 8277 .loc 1 2511 48 view .LVU2535 8278 0032 C3F38003 ubfx r3, r3, #2, #1 2511:Src/main.c **** Curr_setup->LD1_EN = ((uint8_t)((*temp2)>>3))&0x01; 8279 .loc 1 2511 22 view .LVU2536 8280 0036 A370 strb r3, [r4, #2] 2512:Src/main.c **** Curr_setup->LD2_EN = ((uint8_t)((*temp2)>>4))&0x01; 8281 .loc 1 2512 2 is_stmt 1 view .LVU2537 2512:Src/main.c **** Curr_setup->LD2_EN = ((uint8_t)((*temp2)>>4))&0x01; 8282 .loc 1 2512 35 is_stmt 0 view .LVU2538 8283 0038 2B88 ldrh r3, [r5] 2512:Src/main.c **** Curr_setup->LD2_EN = ((uint8_t)((*temp2)>>4))&0x01; 8284 .loc 1 2512 47 view .LVU2539 8285 003a C3F3C003 ubfx r3, r3, #3, #1 2512:Src/main.c **** Curr_setup->LD2_EN = ((uint8_t)((*temp2)>>4))&0x01; 8286 .loc 1 2512 21 view .LVU2540 8287 003e E370 strb r3, [r4, #3] 2513:Src/main.c **** Curr_setup->REF1_EN = ((uint8_t)((*temp2)>>5))&0x01; 8288 .loc 1 2513 2 is_stmt 1 view .LVU2541 2513:Src/main.c **** Curr_setup->REF1_EN = ((uint8_t)((*temp2)>>5))&0x01; 8289 .loc 1 2513 35 is_stmt 0 view .LVU2542 8290 0040 2B88 ldrh r3, [r5] 2513:Src/main.c **** Curr_setup->REF1_EN = ((uint8_t)((*temp2)>>5))&0x01; 8291 .loc 1 2513 47 view .LVU2543 8292 0042 C3F30013 ubfx r3, r3, #4, #1 2513:Src/main.c **** Curr_setup->REF1_EN = ((uint8_t)((*temp2)>>5))&0x01; 8293 .loc 1 2513 21 view .LVU2544 8294 0046 2371 strb r3, [r4, #4] 2514:Src/main.c **** Curr_setup->REF2_EN = ((uint8_t)((*temp2)>>6))&0x01; 8295 .loc 1 2514 2 is_stmt 1 view .LVU2545 2514:Src/main.c **** Curr_setup->REF2_EN = ((uint8_t)((*temp2)>>6))&0x01; 8296 .loc 1 2514 36 is_stmt 0 view .LVU2546 8297 0048 2B88 ldrh r3, [r5] 2514:Src/main.c **** Curr_setup->REF2_EN = ((uint8_t)((*temp2)>>6))&0x01; 8298 .loc 1 2514 48 view .LVU2547 8299 004a C3F34013 ubfx r3, r3, #5, #1 2514:Src/main.c **** Curr_setup->REF2_EN = ((uint8_t)((*temp2)>>6))&0x01; 8300 .loc 1 2514 22 view .LVU2548 8301 004e 6371 strb r3, [r4, #5] 2515:Src/main.c **** Curr_setup->TEC1_EN = ((uint8_t)((*temp2)>>7))&0x01; 8302 .loc 1 2515 2 is_stmt 1 view .LVU2549 2515:Src/main.c **** Curr_setup->TEC1_EN = ((uint8_t)((*temp2)>>7))&0x01; 8303 .loc 1 2515 36 is_stmt 0 view .LVU2550 8304 0050 2B88 ldrh r3, [r5] 2515:Src/main.c **** Curr_setup->TEC1_EN = ((uint8_t)((*temp2)>>7))&0x01; 8305 .loc 1 2515 48 view .LVU2551 8306 0052 C3F38013 ubfx r3, r3, #6, #1 2515:Src/main.c **** Curr_setup->TEC1_EN = ((uint8_t)((*temp2)>>7))&0x01; 8307 .loc 1 2515 22 view .LVU2552 8308 0056 A371 strb r3, [r4, #6] 2516:Src/main.c **** Curr_setup->TEC2_EN = ((uint8_t)((*temp2)>>8))&0x01; 8309 .loc 1 2516 2 is_stmt 1 view .LVU2553 2516:Src/main.c **** Curr_setup->TEC2_EN = ((uint8_t)((*temp2)>>8))&0x01; ARM GAS /tmp/ccLSPxIe.s page 541 8310 .loc 1 2516 36 is_stmt 0 view .LVU2554 8311 0058 2B88 ldrh r3, [r5] 2516:Src/main.c **** Curr_setup->TEC2_EN = ((uint8_t)((*temp2)>>8))&0x01; 8312 .loc 1 2516 48 view .LVU2555 8313 005a C3F3C013 ubfx r3, r3, #7, #1 2516:Src/main.c **** Curr_setup->TEC2_EN = ((uint8_t)((*temp2)>>8))&0x01; 8314 .loc 1 2516 22 view .LVU2556 8315 005e E371 strb r3, [r4, #7] 2517:Src/main.c **** Curr_setup->TS1_EN = ((uint8_t)((*temp2)>>9))&0x01; 8316 .loc 1 2517 2 is_stmt 1 view .LVU2557 2517:Src/main.c **** Curr_setup->TS1_EN = ((uint8_t)((*temp2)>>9))&0x01; 8317 .loc 1 2517 36 is_stmt 0 view .LVU2558 8318 0060 2B88 ldrh r3, [r5] 2517:Src/main.c **** Curr_setup->TS1_EN = ((uint8_t)((*temp2)>>9))&0x01; 8319 .loc 1 2517 48 view .LVU2559 8320 0062 C3F30023 ubfx r3, r3, #8, #1 2517:Src/main.c **** Curr_setup->TS1_EN = ((uint8_t)((*temp2)>>9))&0x01; 8321 .loc 1 2517 22 view .LVU2560 8322 0066 2372 strb r3, [r4, #8] 2518:Src/main.c **** Curr_setup->TS2_EN = ((uint8_t)((*temp2)>>10))&0x01; 8323 .loc 1 2518 2 is_stmt 1 view .LVU2561 2518:Src/main.c **** Curr_setup->TS2_EN = ((uint8_t)((*temp2)>>10))&0x01; 8324 .loc 1 2518 35 is_stmt 0 view .LVU2562 8325 0068 2B88 ldrh r3, [r5] 2518:Src/main.c **** Curr_setup->TS2_EN = ((uint8_t)((*temp2)>>10))&0x01; 8326 .loc 1 2518 47 view .LVU2563 8327 006a C3F34023 ubfx r3, r3, #9, #1 2518:Src/main.c **** Curr_setup->TS2_EN = ((uint8_t)((*temp2)>>10))&0x01; 8328 .loc 1 2518 21 view .LVU2564 8329 006e 6372 strb r3, [r4, #9] 2519:Src/main.c **** Curr_setup->SD_EN = ((uint8_t)((*temp2)>>11))&0x01; 8330 .loc 1 2519 2 is_stmt 1 view .LVU2565 2519:Src/main.c **** Curr_setup->SD_EN = ((uint8_t)((*temp2)>>11))&0x01; 8331 .loc 1 2519 35 is_stmt 0 view .LVU2566 8332 0070 2B88 ldrh r3, [r5] 2519:Src/main.c **** Curr_setup->SD_EN = ((uint8_t)((*temp2)>>11))&0x01; 8333 .loc 1 2519 48 view .LVU2567 8334 0072 C3F38023 ubfx r3, r3, #10, #1 2519:Src/main.c **** Curr_setup->SD_EN = ((uint8_t)((*temp2)>>11))&0x01; 8335 .loc 1 2519 21 view .LVU2568 8336 0076 A372 strb r3, [r4, #10] 2520:Src/main.c **** Curr_setup->PI1_RD = ((uint8_t)((*temp2)>>12))&0x01; 8337 .loc 1 2520 2 is_stmt 1 view .LVU2569 2520:Src/main.c **** Curr_setup->PI1_RD = ((uint8_t)((*temp2)>>12))&0x01; 8338 .loc 1 2520 34 is_stmt 0 view .LVU2570 8339 0078 2B88 ldrh r3, [r5] 2520:Src/main.c **** Curr_setup->PI1_RD = ((uint8_t)((*temp2)>>12))&0x01; 8340 .loc 1 2520 47 view .LVU2571 8341 007a C3F3C023 ubfx r3, r3, #11, #1 2520:Src/main.c **** Curr_setup->PI1_RD = ((uint8_t)((*temp2)>>12))&0x01; 8342 .loc 1 2520 20 view .LVU2572 8343 007e E372 strb r3, [r4, #11] 2521:Src/main.c **** Curr_setup->PI2_RD = ((uint8_t)((*temp2)>>13))&0x01; 8344 .loc 1 2521 2 is_stmt 1 view .LVU2573 2521:Src/main.c **** Curr_setup->PI2_RD = ((uint8_t)((*temp2)>>13))&0x01; 8345 .loc 1 2521 35 is_stmt 0 view .LVU2574 8346 0080 2B88 ldrh r3, [r5] ARM GAS /tmp/ccLSPxIe.s page 542 2521:Src/main.c **** Curr_setup->PI2_RD = ((uint8_t)((*temp2)>>13))&0x01; 8347 .loc 1 2521 48 view .LVU2575 8348 0082 C3F30033 ubfx r3, r3, #12, #1 2521:Src/main.c **** Curr_setup->PI2_RD = ((uint8_t)((*temp2)>>13))&0x01; 8349 .loc 1 2521 21 view .LVU2576 8350 0086 2373 strb r3, [r4, #12] 2522:Src/main.c **** 8351 .loc 1 2522 2 is_stmt 1 view .LVU2577 2522:Src/main.c **** 8352 .loc 1 2522 35 is_stmt 0 view .LVU2578 8353 0088 2B88 ldrh r3, [r5] 2522:Src/main.c **** 8354 .loc 1 2522 48 view .LVU2579 8355 008a C3F34033 ubfx r3, r3, #13, #1 2522:Src/main.c **** 8356 .loc 1 2522 21 view .LVU2580 8357 008e 6373 strb r3, [r4, #13] 2524:Src/main.c **** LD1_curr_setup->LD_TEMP = (uint16_t)(*temp2); 8358 .loc 1 2524 2 is_stmt 1 view .LVU2581 8359 .LVL774: 2525:Src/main.c **** temp2++; 8360 .loc 1 2525 2 view .LVU2582 2525:Src/main.c **** temp2++; 8361 .loc 1 2525 28 is_stmt 0 view .LVU2583 8362 0090 6B88 ldrh r3, [r5, #2] 2525:Src/main.c **** temp2++; 8363 .loc 1 2525 26 view .LVU2584 8364 0092 3B80 strh r3, [r7] @ movhi 2526:Src/main.c **** LD2_curr_setup->LD_TEMP = (uint16_t)(*temp2); 8365 .loc 1 2526 2 is_stmt 1 view .LVU2585 8366 .LVL775: 2527:Src/main.c **** temp2++; 8367 .loc 1 2527 2 view .LVU2586 2527:Src/main.c **** temp2++; 8368 .loc 1 2527 28 is_stmt 0 view .LVU2587 8369 0094 AB88 ldrh r3, [r5, #4] 2527:Src/main.c **** temp2++; 8370 .loc 1 2527 26 view .LVU2588 8371 0096 3380 strh r3, [r6] @ movhi 2528:Src/main.c **** temp2++; 8372 .loc 1 2528 2 is_stmt 1 view .LVU2589 8373 .LVL776: 2529:Src/main.c **** temp2++; 8374 .loc 1 2529 2 view .LVU2590 2530:Src/main.c **** Curr_setup->AVERAGES = (uint16_t)(*temp2); 8375 .loc 1 2530 2 view .LVU2591 2531:Src/main.c **** temp2++; 8376 .loc 1 2531 2 view .LVU2592 2531:Src/main.c **** temp2++; 8377 .loc 1 2531 25 is_stmt 0 view .LVU2593 8378 0098 6B89 ldrh r3, [r5, #10] 2531:Src/main.c **** temp2++; 8379 .loc 1 2531 23 view .LVU2594 8380 009a E381 strh r3, [r4, #14] @ movhi 2532:Src/main.c **** LD1_curr_setup->P_coef_temp = (float)((uint16_t)(*temp2))/((float)(256));//(float)(1/(float)((uint 8381 .loc 1 2532 2 is_stmt 1 view .LVU2595 8382 .LVL777: ARM GAS /tmp/ccLSPxIe.s page 543 2533:Src/main.c **** temp2++; 8383 .loc 1 2533 2 view .LVU2596 2533:Src/main.c **** temp2++; 8384 .loc 1 2533 51 is_stmt 0 view .LVU2597 8385 009c AB89 ldrh r3, [r5, #12] 8386 009e 07EE903A vmov s15, r3 @ int 2533:Src/main.c **** temp2++; 8387 .loc 1 2533 32 view .LVU2598 8388 00a2 F8EE677A vcvt.f32.u32 s15, s15 2533:Src/main.c **** temp2++; 8389 .loc 1 2533 59 view .LVU2599 8390 00a6 9FED8B7A vldr.32 s14, .L480+8 8391 00aa 67EE877A vmul.f32 s15, s15, s14 2533:Src/main.c **** temp2++; 8392 .loc 1 2533 30 view .LVU2600 8393 00ae C7ED017A vstr.32 s15, [r7, #4] 2534:Src/main.c **** LD1_curr_setup->I_coef_temp = (float)((uint16_t)(*temp2))/((float)(256));//(float)(1/(float)((uint 8394 .loc 1 2534 2 is_stmt 1 view .LVU2601 8395 .LVL778: 2535:Src/main.c **** temp2++; 8396 .loc 1 2535 2 view .LVU2602 2535:Src/main.c **** temp2++; 8397 .loc 1 2535 51 is_stmt 0 view .LVU2603 8398 00b2 EB89 ldrh r3, [r5, #14] 8399 00b4 07EE903A vmov s15, r3 @ int 2535:Src/main.c **** temp2++; 8400 .loc 1 2535 32 view .LVU2604 8401 00b8 F8EE677A vcvt.f32.u32 s15, s15 2535:Src/main.c **** temp2++; 8402 .loc 1 2535 59 view .LVU2605 8403 00bc 67EE877A vmul.f32 s15, s15, s14 2535:Src/main.c **** temp2++; 8404 .loc 1 2535 30 view .LVU2606 8405 00c0 C7ED027A vstr.32 s15, [r7, #8] 2536:Src/main.c **** LD2_curr_setup->P_coef_temp = (float)((uint16_t)(*temp2))/((float)(256));//(float)(1/(float)((uint 8406 .loc 1 2536 2 is_stmt 1 view .LVU2607 8407 .LVL779: 2537:Src/main.c **** temp2++; 8408 .loc 1 2537 2 view .LVU2608 2537:Src/main.c **** temp2++; 8409 .loc 1 2537 51 is_stmt 0 view .LVU2609 8410 00c4 2B8A ldrh r3, [r5, #16] 8411 00c6 07EE903A vmov s15, r3 @ int 2537:Src/main.c **** temp2++; 8412 .loc 1 2537 32 view .LVU2610 8413 00ca F8EE677A vcvt.f32.u32 s15, s15 2537:Src/main.c **** temp2++; 8414 .loc 1 2537 59 view .LVU2611 8415 00ce 67EE877A vmul.f32 s15, s15, s14 2537:Src/main.c **** temp2++; 8416 .loc 1 2537 30 view .LVU2612 8417 00d2 C6ED017A vstr.32 s15, [r6, #4] 2538:Src/main.c **** LD2_curr_setup->I_coef_temp = (float)((uint16_t)(*temp2))/((float)(256));//(float)(1/(float)((uint 8418 .loc 1 2538 2 is_stmt 1 view .LVU2613 8419 .LVL780: 2539:Src/main.c **** temp2++; 8420 .loc 1 2539 2 view .LVU2614 ARM GAS /tmp/ccLSPxIe.s page 544 2539:Src/main.c **** temp2++; 8421 .loc 1 2539 51 is_stmt 0 view .LVU2615 8422 00d6 6B8A ldrh r3, [r5, #18] 8423 00d8 07EE903A vmov s15, r3 @ int 2539:Src/main.c **** temp2++; 8424 .loc 1 2539 32 view .LVU2616 8425 00dc F8EE677A vcvt.f32.u32 s15, s15 2539:Src/main.c **** temp2++; 8426 .loc 1 2539 59 view .LVU2617 8427 00e0 67EE877A vmul.f32 s15, s15, s14 2539:Src/main.c **** temp2++; 8428 .loc 1 2539 30 view .LVU2618 8429 00e4 C6ED027A vstr.32 s15, [r6, #8] 2540:Src/main.c **** Long_Data[13] = (uint16_t)(*temp2);//Message ID 8430 .loc 1 2540 2 is_stmt 1 view .LVU2619 8431 .LVL781: 2541:Src/main.c **** temp2++; 8432 .loc 1 2541 2 view .LVU2620 2541:Src/main.c **** temp2++; 8433 .loc 1 2541 18 is_stmt 0 view .LVU2621 8434 00e8 AA8A ldrh r2, [r5, #20] 2541:Src/main.c **** temp2++; 8435 .loc 1 2541 16 view .LVU2622 8436 00ea 7B4B ldr r3, .L480+12 8437 00ec 5A83 strh r2, [r3, #26] @ movhi 2542:Src/main.c **** LD1_curr_setup->CURRENT = (uint16_t)(*temp2); 8438 .loc 1 2542 2 is_stmt 1 view .LVU2623 8439 .LVL782: 2543:Src/main.c **** temp2++; 8440 .loc 1 2543 2 view .LVU2624 2543:Src/main.c **** temp2++; 8441 .loc 1 2543 28 is_stmt 0 view .LVU2625 8442 00ee EB8A ldrh r3, [r5, #22] 2543:Src/main.c **** temp2++; 8443 .loc 1 2543 26 view .LVU2626 8444 00f0 BB81 strh r3, [r7, #12] @ movhi 2544:Src/main.c **** LD2_curr_setup->CURRENT = (uint16_t)(*temp2); 8445 .loc 1 2544 2 is_stmt 1 view .LVU2627 8446 .LVL783: 2545:Src/main.c **** temp2++; 8447 .loc 1 2545 2 view .LVU2628 2545:Src/main.c **** temp2++; 8448 .loc 1 2545 28 is_stmt 0 view .LVU2629 8449 00f2 2B8B ldrh r3, [r5, #24] 2545:Src/main.c **** temp2++; 8450 .loc 1 2545 26 view .LVU2630 8451 00f4 B381 strh r3, [r6, #12] @ movhi 2546:Src/main.c **** 8452 .loc 1 2546 2 is_stmt 1 view .LVU2631 8453 .LVL784: 2548:Src/main.c **** { 8454 .loc 1 2548 2 view .LVU2632 2548:Src/main.c **** { 8455 .loc 1 2548 16 is_stmt 0 view .LVU2633 8456 00f6 6378 ldrb r3, [r4, #1] @ zero_extendqisi2 2548:Src/main.c **** { 8457 .loc 1 2548 5 view .LVU2634 ARM GAS /tmp/ccLSPxIe.s page 545 8458 00f8 002B cmp r3, #0 8459 00fa 00F09580 beq .L458 2550:Src/main.c **** } 8460 .loc 1 2550 3 is_stmt 1 view .LVU2635 8461 00fe 0122 movs r2, #1 8462 0100 0821 movs r1, #8 8463 0102 7648 ldr r0, .L480+16 8464 0104 FFF7FEFF bl HAL_GPIO_WritePin 8465 .LVL785: 8466 .L459: 2557:Src/main.c **** { 8467 .loc 1 2557 2 view .LVU2636 2557:Src/main.c **** { 8468 .loc 1 2557 16 is_stmt 0 view .LVU2637 8469 0108 A378 ldrb r3, [r4, #2] @ zero_extendqisi2 2557:Src/main.c **** { 8470 .loc 1 2557 5 view .LVU2638 8471 010a 002B cmp r3, #0 8472 010c 00F09280 beq .L460 2559:Src/main.c **** } 8473 .loc 1 2559 3 is_stmt 1 view .LVU2639 8474 0110 0122 movs r2, #1 8475 0112 8021 movs r1, #128 8476 0114 7148 ldr r0, .L480+16 8477 0116 FFF7FEFF bl HAL_GPIO_WritePin 8478 .LVL786: 8479 .L461: 2566:Src/main.c **** { 8480 .loc 1 2566 2 view .LVU2640 2566:Src/main.c **** { 8481 .loc 1 2566 16 is_stmt 0 view .LVU2641 8482 011a E378 ldrb r3, [r4, #3] @ zero_extendqisi2 2566:Src/main.c **** { 8483 .loc 1 2566 5 view .LVU2642 8484 011c 002B cmp r3, #0 8485 011e 00F08F80 beq .L462 2568:Src/main.c **** //LL_SPI_Enable(SPI2);//Enable SPI for Laser1 DAC 8486 .loc 1 2568 3 is_stmt 1 view .LVU2643 8487 0122 0122 movs r2, #1 8488 0124 4FF48071 mov r1, #256 8489 0128 6948 ldr r0, .L480+4 8490 012a FFF7FEFF bl HAL_GPIO_WritePin 8491 .LVL787: 8492 .L463: 2577:Src/main.c **** { 8493 .loc 1 2577 2 view .LVU2644 2577:Src/main.c **** { 8494 .loc 1 2577 16 is_stmt 0 view .LVU2645 8495 012e 2379 ldrb r3, [r4, #4] @ zero_extendqisi2 2577:Src/main.c **** { 8496 .loc 1 2577 5 view .LVU2646 8497 0130 002B cmp r3, #0 8498 0132 00F08C80 beq .L464 2579:Src/main.c **** //LL_SPI_Enable(SPI6);//Enable SPI for Laser2 DAC 8499 .loc 1 2579 3 is_stmt 1 view .LVU2647 8500 0136 0122 movs r2, #1 8501 0138 1021 movs r1, #16 ARM GAS /tmp/ccLSPxIe.s page 546 8502 013a 6848 ldr r0, .L480+16 8503 013c FFF7FEFF bl HAL_GPIO_WritePin 8504 .LVL788: 8505 .L465: 2588:Src/main.c **** { 8506 .loc 1 2588 2 view .LVU2648 2588:Src/main.c **** { 8507 .loc 1 2588 16 is_stmt 0 view .LVU2649 8508 0140 6379 ldrb r3, [r4, #5] @ zero_extendqisi2 2588:Src/main.c **** { 8509 .loc 1 2588 5 view .LVU2650 8510 0142 002B cmp r3, #0 8511 0144 00F08980 beq .L466 2590:Src/main.c **** } 8512 .loc 1 2590 3 is_stmt 1 view .LVU2651 8513 0148 0122 movs r2, #1 8514 014a 4FF48061 mov r1, #1024 8515 014e 6448 ldr r0, .L480+20 8516 0150 FFF7FEFF bl HAL_GPIO_WritePin 8517 .LVL789: 8518 .L467: 2597:Src/main.c **** { 8519 .loc 1 2597 2 view .LVU2652 2597:Src/main.c **** { 8520 .loc 1 2597 16 is_stmt 0 view .LVU2653 8521 0154 A379 ldrb r3, [r4, #6] @ zero_extendqisi2 2597:Src/main.c **** { 8522 .loc 1 2597 5 view .LVU2654 8523 0156 002B cmp r3, #0 8524 0158 00F08680 beq .L468 2599:Src/main.c **** } 8525 .loc 1 2599 3 is_stmt 1 view .LVU2655 8526 015c 0122 movs r2, #1 8527 015e 0821 movs r1, #8 8528 0160 6048 ldr r0, .L480+24 8529 0162 FFF7FEFF bl HAL_GPIO_WritePin 8530 .LVL790: 8531 .L469: 2606:Src/main.c **** { 8532 .loc 1 2606 2 view .LVU2656 2606:Src/main.c **** { 8533 .loc 1 2606 17 is_stmt 0 view .LVU2657 8534 0166 637A ldrb r3, [r4, #9] @ zero_extendqisi2 2606:Src/main.c **** { 8535 .loc 1 2606 5 view .LVU2658 8536 0168 1BB1 cbz r3, .L470 2606:Src/main.c **** { 8537 .loc 1 2606 39 discriminator 1 view .LVU2659 8538 016a E379 ldrb r3, [r4, #7] @ zero_extendqisi2 2606:Src/main.c **** { 8539 .loc 1 2606 26 discriminator 1 view .LVU2660 8540 016c 002B cmp r3, #0 8541 016e 40F08180 bne .L478 8542 .L470: 2615:Src/main.c **** HAL_GPIO_WritePin(TEC1_PD_GPIO_Port, TEC1_PD_Pin, GPIO_PIN_RESET); 8543 .loc 1 2615 3 is_stmt 1 view .LVU2661 8544 0172 0022 movs r2, #0 ARM GAS /tmp/ccLSPxIe.s page 547 8545 0174 0121 movs r1, #1 8546 0176 5B48 ldr r0, .L480+24 8547 0178 FFF7FEFF bl HAL_GPIO_WritePin 8548 .LVL791: 2616:Src/main.c **** } 8549 .loc 1 2616 3 view .LVU2662 8550 017c 0022 movs r2, #0 8551 017e 4FF40061 mov r1, #2048 8552 0182 5748 ldr r0, .L480+20 8553 0184 FFF7FEFF bl HAL_GPIO_WritePin 8554 .LVL792: 8555 .L471: 2619:Src/main.c **** { 8556 .loc 1 2619 2 view .LVU2663 2619:Src/main.c **** { 8557 .loc 1 2619 17 is_stmt 0 view .LVU2664 8558 0188 A37A ldrb r3, [r4, #10] @ zero_extendqisi2 2619:Src/main.c **** { 8559 .loc 1 2619 5 view .LVU2665 8560 018a 1BB1 cbz r3, .L472 2619:Src/main.c **** { 8561 .loc 1 2619 39 discriminator 1 view .LVU2666 8562 018c 237A ldrb r3, [r4, #8] @ zero_extendqisi2 2619:Src/main.c **** { 8563 .loc 1 2619 26 discriminator 1 view .LVU2667 8564 018e 002B cmp r3, #0 8565 0190 40F08680 bne .L479 8566 .L472: 2628:Src/main.c **** HAL_GPIO_WritePin(TEC2_PD_GPIO_Port, TEC2_PD_Pin, GPIO_PIN_RESET); 8567 .loc 1 2628 3 is_stmt 1 view .LVU2668 8568 0194 0022 movs r2, #0 8569 0196 0221 movs r1, #2 8570 0198 5248 ldr r0, .L480+24 8571 019a FFF7FEFF bl HAL_GPIO_WritePin 8572 .LVL793: 2629:Src/main.c **** } 8573 .loc 1 2629 3 view .LVU2669 8574 019e 0022 movs r2, #0 8575 01a0 2021 movs r1, #32 8576 01a2 4E48 ldr r0, .L480+16 8577 01a4 FFF7FEFF bl HAL_GPIO_WritePin 8578 .LVL794: 8579 .L473: 2632:Src/main.c **** { 8580 .loc 1 2632 2 view .LVU2670 2632:Src/main.c **** { 8581 .loc 1 2632 16 is_stmt 0 view .LVU2671 8582 01a8 237B ldrb r3, [r4, #12] @ zero_extendqisi2 2632:Src/main.c **** { 8583 .loc 1 2632 5 view .LVU2672 8584 01aa 1BB9 cbnz r3, .L474 2634:Src/main.c **** LD1_curr_setup->I_coef_temp = 0.01; 8585 .loc 1 2634 3 is_stmt 1 view .LVU2673 2634:Src/main.c **** LD1_curr_setup->I_coef_temp = 0.01; 8586 .loc 1 2634 31 is_stmt 0 view .LVU2674 8587 01ac 4E4B ldr r3, .L480+28 8588 01ae 7B60 str r3, [r7, #4] @ float ARM GAS /tmp/ccLSPxIe.s page 548 2635:Src/main.c **** } 8589 .loc 1 2635 3 is_stmt 1 view .LVU2675 2635:Src/main.c **** } 8590 .loc 1 2635 31 is_stmt 0 view .LVU2676 8591 01b0 4E4B ldr r3, .L480+32 8592 01b2 BB60 str r3, [r7, #8] @ float 8593 .L474: 2638:Src/main.c **** { 8594 .loc 1 2638 2 is_stmt 1 view .LVU2677 2638:Src/main.c **** { 8595 .loc 1 2638 16 is_stmt 0 view .LVU2678 8596 01b4 637B ldrb r3, [r4, #13] @ zero_extendqisi2 2638:Src/main.c **** { 8597 .loc 1 2638 5 view .LVU2679 8598 01b6 1BB9 cbnz r3, .L456 2640:Src/main.c **** LD2_curr_setup->I_coef_temp = 0.01; 8599 .loc 1 2640 3 is_stmt 1 view .LVU2680 2640:Src/main.c **** LD2_curr_setup->I_coef_temp = 0.01; 8600 .loc 1 2640 31 is_stmt 0 view .LVU2681 8601 01b8 4B4B ldr r3, .L480+28 8602 01ba 7360 str r3, [r6, #4] @ float 2641:Src/main.c **** } 8603 .loc 1 2641 3 is_stmt 1 view .LVU2682 2641:Src/main.c **** } 8604 .loc 1 2641 31 is_stmt 0 view .LVU2683 8605 01bc 4B4B ldr r3, .L480+32 8606 01be B360 str r3, [r6, #8] @ float 8607 .L456: 2643:Src/main.c **** 8608 .loc 1 2643 1 view .LVU2684 8609 01c0 BDE8F883 pop {r3, r4, r5, r6, r7, r8, r9, pc} 8610 .LVL795: 8611 .L477: 2494:Src/main.c **** { 8612 .loc 1 2494 6 view .LVU2685 8613 01c4 4FF48071 mov r1, #256 8614 01c8 4648 ldr r0, .L480+24 8615 01ca FFF7FEFF bl HAL_GPIO_ReadPin 8616 .LVL796: 2493:Src/main.c **** (HAL_GPIO_ReadPin(USB_FLAG_GPIO_Port, USB_FLAG_Pin) == GPIO_PIN_SET))//if exist sd && connect u 8617 .loc 1 2493 78 discriminator 1 view .LVU2686 8618 01ce 0128 cmp r0, #1 8619 01d0 7FF426AF bne .L457 2496:Src/main.c **** if (test == 0) //0 - suc 8620 .loc 1 2496 3 is_stmt 1 view .LVU2687 2496:Src/main.c **** if (test == 0) //0 - suc 8621 .loc 1 2496 10 is_stmt 0 view .LVU2688 8622 01d4 4648 ldr r0, .L480+36 8623 01d6 FFF7FEFF bl Mount_SD 8624 .LVL797: 2496:Src/main.c **** if (test == 0) //0 - suc 8625 .loc 1 2496 8 discriminator 1 view .LVU2689 8626 01da 3C4B ldr r3, .L480 8627 01dc 1860 str r0, [r3] 2497:Src/main.c **** { 8628 .loc 1 2497 3 is_stmt 1 view .LVU2690 2497:Src/main.c **** { ARM GAS /tmp/ccLSPxIe.s page 549 8629 .loc 1 2497 6 is_stmt 0 view .LVU2691 8630 01de 0028 cmp r0, #0 8631 01e0 7FF41EAF bne .L457 2500:Src/main.c **** test = Create_File("COMMAND.TXT"); // 0 -succ 8632 .loc 1 2500 4 is_stmt 1 view .LVU2692 2500:Src/main.c **** test = Create_File("COMMAND.TXT"); // 0 -succ 8633 .loc 1 2500 11 is_stmt 0 view .LVU2693 8634 01e4 DFF80C91 ldr r9, .L480+40 8635 01e8 4846 mov r0, r9 8636 01ea FFF7FEFF bl Remove_File 8637 .LVL798: 2500:Src/main.c **** test = Create_File("COMMAND.TXT"); // 0 -succ 8638 .loc 1 2500 9 discriminator 1 view .LVU2694 8639 01ee DFF8DC80 ldr r8, .L480 8640 01f2 C8F80000 str r0, [r8] 2501:Src/main.c **** test = Write_File_byte("COMMAND.TXT", (uint8_t *)Command, CL_8); 8641 .loc 1 2501 4 is_stmt 1 view .LVU2695 2501:Src/main.c **** test = Write_File_byte("COMMAND.TXT", (uint8_t *)Command, CL_8); 8642 .loc 1 2501 11 is_stmt 0 view .LVU2696 8643 01f6 4846 mov r0, r9 8644 01f8 FFF7FEFF bl Create_File 8645 .LVL799: 2501:Src/main.c **** test = Write_File_byte("COMMAND.TXT", (uint8_t *)Command, CL_8); 8646 .loc 1 2501 9 discriminator 1 view .LVU2697 8647 01fc C8F80000 str r0, [r8] 2502:Src/main.c **** test = Update_File_byte("COMMAND.TXT", (uint8_t *)Command, CL_8); 8648 .loc 1 2502 4 is_stmt 1 view .LVU2698 2502:Src/main.c **** test = Update_File_byte("COMMAND.TXT", (uint8_t *)Command, CL_8); 8649 .loc 1 2502 11 is_stmt 0 view .LVU2699 8650 0200 1E22 movs r2, #30 8651 0202 2946 mov r1, r5 8652 0204 4846 mov r0, r9 8653 0206 FFF7FEFF bl Write_File_byte 8654 .LVL800: 2502:Src/main.c **** test = Update_File_byte("COMMAND.TXT", (uint8_t *)Command, CL_8); 8655 .loc 1 2502 9 discriminator 1 view .LVU2700 8656 020a C8F80000 str r0, [r8] 2503:Src/main.c **** test = Unmount_SD("/"); // 0 - succ 8657 .loc 1 2503 4 is_stmt 1 view .LVU2701 2503:Src/main.c **** test = Unmount_SD("/"); // 0 - succ 8658 .loc 1 2503 11 is_stmt 0 view .LVU2702 8659 020e 1E22 movs r2, #30 8660 0210 2946 mov r1, r5 8661 0212 4846 mov r0, r9 8662 0214 FFF7FEFF bl Update_File_byte 8663 .LVL801: 2503:Src/main.c **** test = Unmount_SD("/"); // 0 - succ 8664 .loc 1 2503 9 discriminator 1 view .LVU2703 8665 0218 C8F80000 str r0, [r8] 2504:Src/main.c **** } 8666 .loc 1 2504 4 is_stmt 1 view .LVU2704 2504:Src/main.c **** } 8667 .loc 1 2504 11 is_stmt 0 view .LVU2705 8668 021c 3448 ldr r0, .L480+36 8669 021e FFF7FEFF bl Unmount_SD 8670 .LVL802: 2504:Src/main.c **** } ARM GAS /tmp/ccLSPxIe.s page 550 8671 .loc 1 2504 9 discriminator 1 view .LVU2706 8672 0222 C8F80000 str r0, [r8] 8673 0226 FBE6 b .L457 8674 .LVL803: 8675 .L458: 2554:Src/main.c **** } 8676 .loc 1 2554 3 is_stmt 1 view .LVU2707 8677 0228 0022 movs r2, #0 8678 022a 0821 movs r1, #8 8679 022c 2B48 ldr r0, .L480+16 8680 022e FFF7FEFF bl HAL_GPIO_WritePin 8681 .LVL804: 8682 0232 69E7 b .L459 8683 .L460: 2563:Src/main.c **** } 8684 .loc 1 2563 3 view .LVU2708 8685 0234 0022 movs r2, #0 8686 0236 8021 movs r1, #128 8687 0238 2848 ldr r0, .L480+16 8688 023a FFF7FEFF bl HAL_GPIO_WritePin 8689 .LVL805: 8690 023e 6CE7 b .L461 8691 .L462: 2573:Src/main.c **** //LL_SPI_Disable(SPI2);//Disable SPI for Laser1 DAC 8692 .loc 1 2573 3 view .LVU2709 8693 0240 0022 movs r2, #0 8694 0242 4FF48071 mov r1, #256 8695 0246 2248 ldr r0, .L480+4 8696 0248 FFF7FEFF bl HAL_GPIO_WritePin 8697 .LVL806: 8698 024c 6FE7 b .L463 8699 .L464: 2584:Src/main.c **** //LL_SPI_Disable(SPI6);//Disable SPI for Laser2 DAC 8700 .loc 1 2584 3 view .LVU2710 8701 024e 0022 movs r2, #0 8702 0250 1021 movs r1, #16 8703 0252 2248 ldr r0, .L480+16 8704 0254 FFF7FEFF bl HAL_GPIO_WritePin 8705 .LVL807: 8706 0258 72E7 b .L465 8707 .L466: 2594:Src/main.c **** } 8708 .loc 1 2594 3 view .LVU2711 8709 025a 0022 movs r2, #0 8710 025c 4FF48061 mov r1, #1024 8711 0260 1F48 ldr r0, .L480+20 8712 0262 FFF7FEFF bl HAL_GPIO_WritePin 8713 .LVL808: 8714 0266 75E7 b .L467 8715 .L468: 2603:Src/main.c **** } 8716 .loc 1 2603 3 view .LVU2712 8717 0268 0022 movs r2, #0 8718 026a 0821 movs r1, #8 8719 026c 1D48 ldr r0, .L480+24 8720 026e FFF7FEFF bl HAL_GPIO_WritePin 8721 .LVL809: ARM GAS /tmp/ccLSPxIe.s page 551 8722 0272 78E7 b .L469 8723 .L478: 2608:Src/main.c **** Set_LTEC(3,32767); 8724 .loc 1 2608 3 view .LVU2713 8725 0274 47F6FF71 movw r1, #32767 8726 0278 0320 movs r0, #3 8727 027a FFF7FEFF bl Set_LTEC 8728 .LVL810: 2609:Src/main.c **** HAL_GPIO_WritePin(TEC1_PD_GPIO_Port, TEC1_PD_Pin, GPIO_PIN_SET); 8729 .loc 1 2609 3 view .LVU2714 8730 027e 47F6FF71 movw r1, #32767 8731 0282 0320 movs r0, #3 8732 0284 FFF7FEFF bl Set_LTEC 8733 .LVL811: 2610:Src/main.c **** HAL_GPIO_WritePin(TECEN1_GPIO_Port, TECEN1_Pin, GPIO_PIN_SET); 8734 .loc 1 2610 3 view .LVU2715 8735 0288 0122 movs r2, #1 8736 028a 4FF40061 mov r1, #2048 8737 028e 1448 ldr r0, .L480+20 8738 0290 FFF7FEFF bl HAL_GPIO_WritePin 8739 .LVL812: 2611:Src/main.c **** } 8740 .loc 1 2611 3 view .LVU2716 8741 0294 0122 movs r2, #1 8742 0296 1146 mov r1, r2 8743 0298 1248 ldr r0, .L480+24 8744 029a FFF7FEFF bl HAL_GPIO_WritePin 8745 .LVL813: 8746 029e 73E7 b .L471 8747 .L479: 2621:Src/main.c **** Set_LTEC(4,32767); 8748 .loc 1 2621 3 view .LVU2717 8749 02a0 47F6FF71 movw r1, #32767 8750 02a4 0420 movs r0, #4 8751 02a6 FFF7FEFF bl Set_LTEC 8752 .LVL814: 2622:Src/main.c **** HAL_GPIO_WritePin(TEC2_PD_GPIO_Port, TEC2_PD_Pin, GPIO_PIN_SET); 8753 .loc 1 2622 3 view .LVU2718 8754 02aa 47F6FF71 movw r1, #32767 8755 02ae 0420 movs r0, #4 8756 02b0 FFF7FEFF bl Set_LTEC 8757 .LVL815: 2623:Src/main.c **** HAL_GPIO_WritePin(TECEN2_GPIO_Port, TECEN2_Pin, GPIO_PIN_SET); 8758 .loc 1 2623 3 view .LVU2719 8759 02b4 0122 movs r2, #1 8760 02b6 2021 movs r1, #32 8761 02b8 0848 ldr r0, .L480+16 8762 02ba FFF7FEFF bl HAL_GPIO_WritePin 8763 .LVL816: 2624:Src/main.c **** } 8764 .loc 1 2624 3 view .LVU2720 8765 02be 0122 movs r2, #1 8766 02c0 0221 movs r1, #2 8767 02c2 0848 ldr r0, .L480+24 8768 02c4 FFF7FEFF bl HAL_GPIO_WritePin 8769 .LVL817: 8770 02c8 6EE7 b .L473 ARM GAS /tmp/ccLSPxIe.s page 552 8771 .L481: 8772 02ca 00BF .align 2 8773 .L480: 8774 02cc 00000000 .word test 8775 02d0 000C0240 .word 1073875968 8776 02d4 0000803B .word 998244352 8777 02d8 00000000 .word Long_Data 8778 02dc 00080240 .word 1073874944 8779 02e0 00040240 .word 1073873920 8780 02e4 00000240 .word 1073872896 8781 02e8 00002041 .word 1092616192 8782 02ec 0AD7233C .word 1008981770 8783 02f0 00000000 .word .LC0 8784 02f4 04000000 .word .LC1 8785 .cfi_endproc 8786 .LFE1209: 8788 .section .text.Advanced_Controller_Temp,"ax",%progbits 8789 .align 1 8790 .global Advanced_Controller_Temp 8791 .syntax unified 8792 .thumb 8793 .thumb_func 8795 Advanced_Controller_Temp: 8796 .LVL818: 8797 .LFB1238: 3673:Src/main.c **** // Main idea: 8798 .loc 1 3673 1 view -0 8799 .cfi_startproc 8800 @ args = 0, pretend = 0, frame = 0 8801 @ frame_needed = 0, uses_anonymous_args = 0 8802 @ link register save eliminated. 3673:Src/main.c **** // Main idea: 8803 .loc 1 3673 1 is_stmt 0 view .LVU2722 8804 0000 30B4 push {r4, r5} 8805 .LCFI75: 8806 .cfi_def_cfa_offset 8 8807 .cfi_offset 4, -8 8808 .cfi_offset 5, -4 3691:Src/main.c **** float P_coef_current;//, I_coef_current; 8809 .loc 1 3691 2 is_stmt 1 view .LVU2723 3692:Src/main.c **** float e_integral; 8810 .loc 1 3692 2 view .LVU2724 3693:Src/main.c **** int x_output; 8811 .loc 1 3693 2 view .LVU2725 3694:Src/main.c **** 8812 .loc 1 3694 2 view .LVU2726 3696:Src/main.c **** 8813 .loc 1 3696 2 view .LVU2727 3696:Src/main.c **** 8814 .loc 1 3696 28 is_stmt 0 view .LVU2728 8815 0002 0B88 ldrh r3, [r1] 3696:Src/main.c **** 8816 .loc 1 3696 65 view .LVU2729 8817 0004 0488 ldrh r4, [r0] 3696:Src/main.c **** 8818 .loc 1 3696 8 view .LVU2730 8819 0006 1B1B subs r3, r3, r4 ARM GAS /tmp/ccLSPxIe.s page 553 8820 .LVL819: 3698:Src/main.c **** 8821 .loc 1 3698 2 is_stmt 1 view .LVU2731 3698:Src/main.c **** 8822 .loc 1 3698 13 is_stmt 0 view .LVU2732 8823 0008 D1ED017A vldr.32 s15, [r1, #4] 8824 .LVL820: 3700:Src/main.c **** e_integral += LDx_curr_setup->I_coef_temp * (float)(e_pid) * (float)(TO7 - TO7_PID) / (float) 100 8825 .loc 1 3700 2 is_stmt 1 view .LVU2733 3700:Src/main.c **** e_integral += LDx_curr_setup->I_coef_temp * (float)(e_pid) * (float)(TO7 - TO7_PID) / (float) 100 8826 .loc 1 3700 20 is_stmt 0 view .LVU2734 8827 000c 03F6B73C addw ip, r3, #2999 3700:Src/main.c **** e_integral += LDx_curr_setup->I_coef_temp * (float)(e_pid) * (float)(TO7 - TO7_PID) / (float) 100 8828 .loc 1 3700 4 view .LVU2735 8829 0010 41F26E74 movw r4, #5998 8830 0014 A445 cmp ip, r4 8831 0016 18D8 bhi .L483 3701:Src/main.c **** } 8832 .loc 1 3701 3 is_stmt 1 view .LVU2736 3701:Src/main.c **** } 8833 .loc 1 3701 31 is_stmt 0 view .LVU2737 8834 0018 90ED027A vldr.32 s14, [r0, #8] 3701:Src/main.c **** } 8835 .loc 1 3701 47 view .LVU2738 8836 001c 06EE903A vmov s13, r3 @ int 8837 0020 F8EEE66A vcvt.f32.s32 s13, s13 3701:Src/main.c **** } 8838 .loc 1 3701 45 view .LVU2739 8839 0024 27EE267A vmul.f32 s14, s14, s13 3701:Src/main.c **** } 8840 .loc 1 3701 76 view .LVU2740 8841 0028 284C ldr r4, .L493 8842 002a 2468 ldr r4, [r4] 8843 002c 284D ldr r5, .L493+4 8844 002e 2D68 ldr r5, [r5] 8845 0030 641B subs r4, r4, r5 3701:Src/main.c **** } 8846 .loc 1 3701 64 view .LVU2741 8847 0032 06EE904A vmov s13, r4 @ int 8848 0036 F8EE666A vcvt.f32.u32 s13, s13 3701:Src/main.c **** } 8849 .loc 1 3701 62 view .LVU2742 8850 003a 27EE267A vmul.f32 s14, s14, s13 3701:Src/main.c **** } 8851 .loc 1 3701 87 view .LVU2743 8852 003e 9FED256A vldr.32 s12, .L493+8 8853 0042 C7EE066A vdiv.f32 s13, s14, s12 3701:Src/main.c **** } 8854 .loc 1 3701 14 view .LVU2744 8855 0046 77EEA67A vadd.f32 s15, s15, s13 8856 .LVL821: 8857 .L483: 3703:Src/main.c **** 8858 .loc 1 3703 2 is_stmt 1 view .LVU2745 3703:Src/main.c **** 8859 .loc 1 3703 17 is_stmt 0 view .LVU2746 8860 004a D0ED016A vldr.32 s13, [r0, #4] ARM GAS /tmp/ccLSPxIe.s page 554 8861 .LVL822: 3705:Src/main.c **** e_integral = 32000; 8862 .loc 1 3705 2 is_stmt 1 view .LVU2747 3705:Src/main.c **** e_integral = 32000; 8863 .loc 1 3705 5 is_stmt 0 view .LVU2748 8864 004e 9FED227A vldr.32 s14, .L493+12 8865 0052 F4EEC77A vcmpe.f32 s15, s14 8866 0056 F1EE10FA vmrs APSR_nzcv, FPSCR 8867 005a 09DC bgt .L487 3708:Src/main.c **** e_integral = -32000; 8868 .loc 1 3708 7 is_stmt 1 view .LVU2749 3708:Src/main.c **** e_integral = -32000; 8869 .loc 1 3708 10 is_stmt 0 view .LVU2750 8870 005c 9FED1F7A vldr.32 s14, .L493+16 8871 0060 F4EEC77A vcmpe.f32 s15, s14 8872 0064 F1EE10FA vmrs APSR_nzcv, FPSCR 8873 0068 04D5 bpl .L484 3709:Src/main.c **** } 8874 .loc 1 3709 15 view .LVU2751 8875 006a DFED1C7A vldr.32 s15, .L493+16 8876 .LVL823: 3709:Src/main.c **** } 8877 .loc 1 3709 15 view .LVU2752 8878 006e 01E0 b .L484 8879 .LVL824: 8880 .L487: 3706:Src/main.c **** } 8881 .loc 1 3706 15 view .LVU2753 8882 0070 DFED197A vldr.32 s15, .L493+12 8883 .LVL825: 8884 .L484: 3711:Src/main.c **** 8885 .loc 1 3711 2 is_stmt 1 view .LVU2754 3711:Src/main.c **** 8886 .loc 1 3711 26 is_stmt 0 view .LVU2755 8887 0074 C1ED017A vstr.32 s15, [r1, #4] 3713:Src/main.c **** 8888 .loc 1 3713 2 is_stmt 1 view .LVU2756 3713:Src/main.c **** 8889 .loc 1 3713 36 is_stmt 0 view .LVU2757 8890 0078 07EE103A vmov s14, r3 @ int 8891 007c B8EEC77A vcvt.f32.s32 s14, s14 8892 0080 27EE267A vmul.f32 s14, s14, s13 3713:Src/main.c **** 8893 .loc 1 3713 19 view .LVU2758 8894 0084 DFED166A vldr.32 s13, .L493+20 8895 .LVL826: 3713:Src/main.c **** 8896 .loc 1 3713 19 view .LVU2759 8897 0088 37EE267A vadd.f32 s14, s14, s13 3713:Src/main.c **** 8898 .loc 1 3713 46 view .LVU2760 8899 008c FDEEE77A vcvt.s32.f32 s15, s15 8900 .LVL827: 3713:Src/main.c **** 8901 .loc 1 3713 44 view .LVU2761 8902 0090 F8EEE77A vcvt.f32.s32 s15, s15 ARM GAS /tmp/ccLSPxIe.s page 555 8903 0094 77EE877A vadd.f32 s15, s15, s14 3713:Src/main.c **** 8904 .loc 1 3713 11 view .LVU2762 8905 0098 FDEEE77A vcvt.s32.f32 s15, s15 8906 009c 17EE900A vmov r0, s15 @ int 8907 .LVL828: 3715:Src/main.c **** x_output = 8800; 8908 .loc 1 3715 2 is_stmt 1 view .LVU2763 3715:Src/main.c **** x_output = 8800; 8909 .loc 1 3715 4 is_stmt 0 view .LVU2764 8910 00a0 B0F57A7F cmp r0, #1000 8911 00a4 06DB blt .L489 3718:Src/main.c **** x_output = 56800; 8912 .loc 1 3718 7 is_stmt 1 view .LVU2765 3718:Src/main.c **** x_output = 56800; 8913 .loc 1 3718 9 is_stmt 0 view .LVU2766 8914 00a6 4DF6E053 movw r3, #56800 8915 .LVL829: 3718:Src/main.c **** x_output = 56800; 8916 .loc 1 3718 9 view .LVU2767 8917 00aa 9842 cmp r0, r3 8918 00ac 04DD ble .L485 3719:Src/main.c **** } 8919 .loc 1 3719 12 view .LVU2768 8920 00ae 4DF6E050 movw r0, #56800 8921 .LVL830: 3719:Src/main.c **** } 8922 .loc 1 3719 12 view .LVU2769 8923 00b2 01E0 b .L485 8924 .LVL831: 8925 .L489: 3716:Src/main.c **** } 8926 .loc 1 3716 12 view .LVU2770 8927 00b4 42F26020 movw r0, #8800 8928 .LVL832: 8929 .L485: 3722:Src/main.c **** TO7_PID = TO7;//Save current time only on 2nd laser 8930 .loc 1 3722 2 is_stmt 1 view .LVU2771 3722:Src/main.c **** TO7_PID = TO7;//Save current time only on 2nd laser 8931 .loc 1 3722 5 is_stmt 0 view .LVU2772 8932 00b8 022A cmp r2, #2 8933 00ba 02D0 beq .L492 8934 .LVL833: 8935 .L486: 3725:Src/main.c **** } 8936 .loc 1 3725 2 is_stmt 1 view .LVU2773 3726:Src/main.c **** 8937 .loc 1 3726 1 is_stmt 0 view .LVU2774 8938 00bc 80B2 uxth r0, r0 8939 .LVL834: 3726:Src/main.c **** 8940 .loc 1 3726 1 view .LVU2775 8941 00be 30BC pop {r4, r5} 8942 .LCFI76: 8943 .cfi_remember_state 8944 .cfi_restore 5 8945 .cfi_restore 4 ARM GAS /tmp/ccLSPxIe.s page 556 8946 .cfi_def_cfa_offset 0 8947 00c0 7047 bx lr 8948 .LVL835: 8949 .L492: 8950 .LCFI77: 8951 .cfi_restore_state 3723:Src/main.c **** 8952 .loc 1 3723 3 is_stmt 1 view .LVU2776 3723:Src/main.c **** 8953 .loc 1 3723 11 is_stmt 0 view .LVU2777 8954 00c2 024B ldr r3, .L493 8955 00c4 1A68 ldr r2, [r3] 8956 .LVL836: 3723:Src/main.c **** 8957 .loc 1 3723 11 view .LVU2778 8958 00c6 024B ldr r3, .L493+4 8959 00c8 1A60 str r2, [r3] 8960 00ca F7E7 b .L486 8961 .L494: 8962 .align 2 8963 .L493: 8964 00cc 00000000 .word TO7 8965 00d0 00000000 .word TO7_PID 8966 00d4 0000C842 .word 1120403456 8967 00d8 0000FA46 .word 1190789120 8968 00dc 0000FAC6 .word -956694528 8969 00e0 00000047 .word 1191182336 8970 .cfi_endproc 8971 .LFE1238: 8973 .section .text.CalculateChecksum,"ax",%progbits 8974 .align 1 8975 .global CalculateChecksum 8976 .syntax unified 8977 .thumb 8978 .thumb_func 8980 CalculateChecksum: 8981 .LVL837: 8982 .LFB1241: 3789:Src/main.c **** short i; 8983 .loc 1 3789 1 is_stmt 1 view -0 8984 .cfi_startproc 8985 @ args = 0, pretend = 0, frame = 0 8986 @ frame_needed = 0, uses_anonymous_args = 0 8987 @ link register save eliminated. 3789:Src/main.c **** short i; 8988 .loc 1 3789 1 is_stmt 0 view .LVU2780 8989 0000 8446 mov ip, r0 3790:Src/main.c **** uint16_t cs = *pbuff; 8990 .loc 1 3790 2 is_stmt 1 view .LVU2781 3791:Src/main.c **** 8991 .loc 1 3791 2 view .LVU2782 3791:Src/main.c **** 8992 .loc 1 3791 11 is_stmt 0 view .LVU2783 8993 0002 0088 ldrh r0, [r0] 8994 .LVL838: 3793:Src/main.c **** { 8995 .loc 1 3793 3 is_stmt 1 view .LVU2784 ARM GAS /tmp/ccLSPxIe.s page 557 3793:Src/main.c **** { 8996 .loc 1 3793 9 is_stmt 0 view .LVU2785 8997 0004 0123 movs r3, #1 3793:Src/main.c **** { 8998 .loc 1 3793 3 view .LVU2786 8999 0006 04E0 b .L496 9000 .LVL839: 9001 .L497: 3795:Src/main.c **** } 9002 .loc 1 3795 3 is_stmt 1 view .LVU2787 3795:Src/main.c **** } 9003 .loc 1 3795 9 is_stmt 0 view .LVU2788 9004 0008 3CF81320 ldrh r2, [ip, r3, lsl #1] 3795:Src/main.c **** } 9005 .loc 1 3795 6 view .LVU2789 9006 000c 5040 eors r0, r0, r2 9007 .LVL840: 3793:Src/main.c **** { 9008 .loc 1 3793 24 is_stmt 1 discriminator 3 view .LVU2790 9009 000e 0133 adds r3, r3, #1 9010 .LVL841: 3793:Src/main.c **** { 9011 .loc 1 3793 24 is_stmt 0 discriminator 3 view .LVU2791 9012 0010 1BB2 sxth r3, r3 9013 .LVL842: 9014 .L496: 3793:Src/main.c **** { 9015 .loc 1 3793 16 is_stmt 1 discriminator 1 view .LVU2792 9016 0012 8B42 cmp r3, r1 9017 0014 F8DB blt .L497 3797:Src/main.c **** } 9018 .loc 1 3797 2 view .LVU2793 3798:Src/main.c **** 9019 .loc 1 3798 1 is_stmt 0 view .LVU2794 9020 0016 7047 bx lr 9021 .cfi_endproc 9022 .LFE1241: 9024 .section .text.CheckChecksum,"ax",%progbits 9025 .align 1 9026 .global CheckChecksum 9027 .syntax unified 9028 .thumb 9029 .thumb_func 9031 CheckChecksum: 9032 .LVL843: 9033 .LFB1240: 3768:Src/main.c **** uint16_t cl_ind; 9034 .loc 1 3768 1 is_stmt 1 view -0 9035 .cfi_startproc 9036 @ args = 0, pretend = 0, frame = 0 9037 @ frame_needed = 0, uses_anonymous_args = 0 3768:Src/main.c **** uint16_t cl_ind; 9038 .loc 1 3768 1 is_stmt 0 view .LVU2796 9039 0000 10B5 push {r4, lr} 9040 .LCFI78: 9041 .cfi_def_cfa_offset 8 9042 .cfi_offset 4, -8 ARM GAS /tmp/ccLSPxIe.s page 558 9043 .cfi_offset 14, -4 3769:Src/main.c **** 9044 .loc 1 3769 3 is_stmt 1 view .LVU2797 3771:Src/main.c **** { 9045 .loc 1 3771 3 view .LVU2798 9046 0002 0E4B ldr r3, .L504 9047 0004 1B88 ldrh r3, [r3] 9048 0006 41F21112 movw r2, #4369 9049 000a 9342 cmp r3, r2 9050 000c 05D0 beq .L501 9051 000e 47F27772 movw r2, #30583 9052 0012 9342 cmp r3, r2 9053 0014 0FD1 bne .L502 9054 0016 0E24 movs r4, #14 9055 0018 00E0 b .L499 9056 .L501: 3777:Src/main.c **** break; 9057 .loc 1 3777 14 is_stmt 0 view .LVU2799 9058 001a 0D24 movs r4, #13 9059 .L499: 9060 .LVL844: 3781:Src/main.c **** } 9061 .loc 1 3781 5 is_stmt 1 view .LVU2800 3784:Src/main.c **** 9062 .loc 1 3784 3 view .LVU2801 3784:Src/main.c **** 9063 .loc 1 3784 15 is_stmt 0 view .LVU2802 9064 001c 2146 mov r1, r4 9065 001e FFF7FEFF bl CalculateChecksum 9066 .LVL845: 3784:Src/main.c **** 9067 .loc 1 3784 13 discriminator 1 view .LVU2803 9068 0022 074B ldr r3, .L504+4 9069 0024 1880 strh r0, [r3] @ movhi 3786:Src/main.c **** } 9070 .loc 1 3786 3 is_stmt 1 view .LVU2804 3786:Src/main.c **** } 9071 .loc 1 3786 32 is_stmt 0 view .LVU2805 9072 0026 074B ldr r3, .L504+8 9073 0028 33F81430 ldrh r3, [r3, r4, lsl #1] 3786:Src/main.c **** } 9074 .loc 1 3786 46 view .LVU2806 9075 002c 9842 cmp r0, r3 9076 002e 14BF ite ne 9077 0030 0020 movne r0, #0 9078 0032 0120 moveq r0, #1 9079 .LVL846: 9080 .L500: 3787:Src/main.c **** uint16_t CalculateChecksum(uint16_t *pbuff, uint16_t len) 9081 .loc 1 3787 1 view .LVU2807 9082 0034 10BD pop {r4, pc} 9083 .LVL847: 9084 .L502: 3771:Src/main.c **** { 9085 .loc 1 3771 3 view .LVU2808 9086 0036 0020 movs r0, #0 9087 .LVL848: ARM GAS /tmp/ccLSPxIe.s page 559 3771:Src/main.c **** { 9088 .loc 1 3771 3 view .LVU2809 9089 0038 FCE7 b .L500 9090 .L505: 9091 003a 00BF .align 2 9092 .L504: 9093 003c 00000000 .word UART_header 9094 0040 00000000 .word CS_result 9095 0044 00000000 .word COMMAND 9096 .cfi_endproc 9097 .LFE1240: 9099 .section .rodata.SD_SAVE.str1.4,"aMS",%progbits,1 9100 .align 2 9101 .LC2: 9102 0000 46494C45 .ascii "FILE1.TXT\000" 9102 312E5458 9102 5400 9103 .section .text.SD_SAVE,"ax",%progbits 9104 .align 1 9105 .global SD_SAVE 9106 .syntax unified 9107 .thumb 9108 .thumb_func 9110 SD_SAVE: 9111 .LVL849: 9112 .LFB1242: 3827:Src/main.c **** int test=0; 9113 .loc 1 3827 1 is_stmt 1 view -0 9114 .cfi_startproc 9115 @ args = 0, pretend = 0, frame = 0 9116 @ frame_needed = 0, uses_anonymous_args = 0 3827:Src/main.c **** int test=0; 9117 .loc 1 3827 1 is_stmt 0 view .LVU2811 9118 0000 10B5 push {r4, lr} 9119 .LCFI79: 9120 .cfi_def_cfa_offset 8 9121 .cfi_offset 4, -8 9122 .cfi_offset 14, -4 9123 0002 0446 mov r4, r0 3828:Src/main.c **** if (HAL_GPIO_ReadPin(SDMMC1_EN_GPIO_Port, SDMMC1_EN_Pin)==GPIO_PIN_RESET) 9124 .loc 1 3828 2 is_stmt 1 view .LVU2812 9125 .LVL850: 3829:Src/main.c **** { 9126 .loc 1 3829 2 view .LVU2813 3829:Src/main.c **** { 9127 .loc 1 3829 6 is_stmt 0 view .LVU2814 9128 0004 0121 movs r1, #1 9129 0006 0A48 ldr r0, .L513 9130 .LVL851: 3829:Src/main.c **** { 9131 .loc 1 3829 6 view .LVU2815 9132 0008 FFF7FEFF bl HAL_GPIO_ReadPin 9133 .LVL852: 3829:Src/main.c **** { 9134 .loc 1 3829 5 discriminator 1 view .LVU2816 9135 000c 08B1 cbz r0, .L511 3846:Src/main.c **** } ARM GAS /tmp/ccLSPxIe.s page 560 9136 .loc 1 3846 10 view .LVU2817 9137 000e 0120 movs r0, #1 9138 .LVL853: 9139 .L506: 3848:Src/main.c **** 9140 .loc 1 3848 1 view .LVU2818 9141 0010 10BD pop {r4, pc} 9142 .LVL854: 9143 .L511: 3831:Src/main.c **** if (test == 0) //0 - suc 9144 .loc 1 3831 3 is_stmt 1 view .LVU2819 3831:Src/main.c **** if (test == 0) //0 - suc 9145 .loc 1 3831 10 is_stmt 0 view .LVU2820 9146 0012 0848 ldr r0, .L513+4 9147 0014 FFF7FEFF bl Mount_SD 9148 .LVL855: 3832:Src/main.c **** { 9149 .loc 1 3832 3 is_stmt 1 view .LVU2821 3832:Src/main.c **** { 9150 .loc 1 3832 6 is_stmt 0 view .LVU2822 9151 0018 08B1 cbz r0, .L512 3841:Src/main.c **** } 9152 .loc 1 3841 11 view .LVU2823 9153 001a 0120 movs r0, #1 9154 .LVL856: 3841:Src/main.c **** } 9155 .loc 1 3841 11 view .LVU2824 9156 001c F8E7 b .L506 9157 .LVL857: 9158 .L512: 3835:Src/main.c **** test = Unmount_SD("/"); // 0 - succ 9159 .loc 1 3835 4 is_stmt 1 view .LVU2825 3835:Src/main.c **** test = Unmount_SD("/"); // 0 - succ 9160 .loc 1 3835 11 is_stmt 0 view .LVU2826 9161 001e 1E22 movs r2, #30 9162 0020 2146 mov r1, r4 9163 0022 0548 ldr r0, .L513+8 9164 .LVL858: 3835:Src/main.c **** test = Unmount_SD("/"); // 0 - succ 9165 .loc 1 3835 11 view .LVU2827 9166 0024 FFF7FEFF bl Update_File_byte 9167 .LVL859: 3836:Src/main.c **** return test; 9168 .loc 1 3836 4 is_stmt 1 view .LVU2828 3836:Src/main.c **** return test; 9169 .loc 1 3836 11 is_stmt 0 view .LVU2829 9170 0028 0248 ldr r0, .L513+4 9171 002a FFF7FEFF bl Unmount_SD 9172 .LVL860: 3837:Src/main.c **** } 9173 .loc 1 3837 4 is_stmt 1 view .LVU2830 3837:Src/main.c **** } 9174 .loc 1 3837 11 is_stmt 0 view .LVU2831 9175 002e EFE7 b .L506 9176 .L514: 9177 .align 2 9178 .L513: ARM GAS /tmp/ccLSPxIe.s page 561 9179 0030 000C0240 .word 1073875968 9180 0034 00000000 .word .LC0 9181 0038 00000000 .word .LC2 9182 .cfi_endproc 9183 .LFE1242: 9185 .section .text.SD_READ,"ax",%progbits 9186 .align 1 9187 .global SD_READ 9188 .syntax unified 9189 .thumb 9190 .thumb_func 9192 SD_READ: 9193 .LVL861: 9194 .LFB1243: 3858:Src/main.c **** int test=0; 9195 .loc 1 3858 1 is_stmt 1 view -0 9196 .cfi_startproc 9197 @ args = 0, pretend = 0, frame = 0 9198 @ frame_needed = 0, uses_anonymous_args = 0 3858:Src/main.c **** int test=0; 9199 .loc 1 3858 1 is_stmt 0 view .LVU2833 9200 0000 38B5 push {r3, r4, r5, lr} 9201 .LCFI80: 9202 .cfi_def_cfa_offset 16 9203 .cfi_offset 3, -16 9204 .cfi_offset 4, -12 9205 .cfi_offset 5, -8 9206 .cfi_offset 14, -4 9207 0002 0446 mov r4, r0 3859:Src/main.c **** if (HAL_GPIO_ReadPin(SDMMC1_EN_GPIO_Port, SDMMC1_EN_Pin)==GPIO_PIN_RESET) 9208 .loc 1 3859 2 is_stmt 1 view .LVU2834 9209 .LVL862: 3860:Src/main.c **** { 9210 .loc 1 3860 2 view .LVU2835 3860:Src/main.c **** { 9211 .loc 1 3860 6 is_stmt 0 view .LVU2836 9212 0004 0121 movs r1, #1 9213 0006 0D48 ldr r0, .L522 9214 .LVL863: 3860:Src/main.c **** { 9215 .loc 1 3860 6 view .LVU2837 9216 0008 FFF7FEFF bl HAL_GPIO_ReadPin 9217 .LVL864: 3860:Src/main.c **** { 9218 .loc 1 3860 5 discriminator 1 view .LVU2838 9219 000c 08B1 cbz r0, .L520 3878:Src/main.c **** } 9220 .loc 1 3878 10 view .LVU2839 9221 000e 0120 movs r0, #1 9222 .LVL865: 9223 .L515: 3894:Src/main.c **** 9224 .loc 1 3894 1 view .LVU2840 9225 0010 38BD pop {r3, r4, r5, pc} 9226 .LVL866: 9227 .L520: 3862:Src/main.c **** if (test == 0) //0 - suc ARM GAS /tmp/ccLSPxIe.s page 562 9228 .loc 1 3862 3 is_stmt 1 view .LVU2841 3862:Src/main.c **** if (test == 0) //0 - suc 9229 .loc 1 3862 10 is_stmt 0 view .LVU2842 9230 0012 0B48 ldr r0, .L522+4 9231 0014 FFF7FEFF bl Mount_SD 9232 .LVL867: 3863:Src/main.c **** { 9233 .loc 1 3863 3 is_stmt 1 view .LVU2843 3863:Src/main.c **** { 9234 .loc 1 3863 6 is_stmt 0 view .LVU2844 9235 0018 08B1 cbz r0, .L521 3873:Src/main.c **** } 9236 .loc 1 3873 11 view .LVU2845 9237 001a 0120 movs r0, #1 9238 .LVL868: 3873:Src/main.c **** } 9239 .loc 1 3873 11 view .LVU2846 9240 001c F8E7 b .L515 9241 .LVL869: 9242 .L521: 3866:Src/main.c **** fgoto+=DL_8; 9243 .loc 1 3866 4 is_stmt 1 view .LVU2847 3866:Src/main.c **** fgoto+=DL_8; 9244 .loc 1 3866 11 is_stmt 0 view .LVU2848 9245 001e 094D ldr r5, .L522+8 9246 0020 2B68 ldr r3, [r5] 9247 0022 1E22 movs r2, #30 9248 0024 2146 mov r1, r4 9249 0026 0848 ldr r0, .L522+12 9250 .LVL870: 3866:Src/main.c **** fgoto+=DL_8; 9251 .loc 1 3866 11 view .LVU2849 9252 0028 FFF7FEFF bl Seek_Read_File 9253 .LVL871: 3867:Src/main.c **** test = Unmount_SD("/"); // 0 - succ 9254 .loc 1 3867 4 is_stmt 1 view .LVU2850 3867:Src/main.c **** test = Unmount_SD("/"); // 0 - succ 9255 .loc 1 3867 9 is_stmt 0 view .LVU2851 9256 002c 2B68 ldr r3, [r5] 9257 002e 1E33 adds r3, r3, #30 9258 0030 2B60 str r3, [r5] 3868:Src/main.c **** return test; 9259 .loc 1 3868 4 is_stmt 1 view .LVU2852 3868:Src/main.c **** return test; 9260 .loc 1 3868 11 is_stmt 0 view .LVU2853 9261 0032 0348 ldr r0, .L522+4 9262 0034 FFF7FEFF bl Unmount_SD 9263 .LVL872: 3869:Src/main.c **** } 9264 .loc 1 3869 4 is_stmt 1 view .LVU2854 3869:Src/main.c **** } 9265 .loc 1 3869 11 is_stmt 0 view .LVU2855 9266 0038 EAE7 b .L515 9267 .L523: 9268 003a 00BF .align 2 9269 .L522: 9270 003c 000C0240 .word 1073875968 ARM GAS /tmp/ccLSPxIe.s page 563 9271 0040 00000000 .word .LC0 9272 0044 00000000 .word fgoto 9273 0048 00000000 .word .LC2 9274 .cfi_endproc 9275 .LFE1243: 9277 .section .text.SD_REMOVE,"ax",%progbits 9278 .align 1 9279 .global SD_REMOVE 9280 .syntax unified 9281 .thumb 9282 .thumb_func 9284 SD_REMOVE: 9285 .LFB1244: 3897:Src/main.c **** int test=0; 9286 .loc 1 3897 1 is_stmt 1 view -0 9287 .cfi_startproc 9288 @ args = 0, pretend = 0, frame = 0 9289 @ frame_needed = 0, uses_anonymous_args = 0 9290 0000 10B5 push {r4, lr} 9291 .LCFI81: 9292 .cfi_def_cfa_offset 8 9293 .cfi_offset 4, -8 9294 .cfi_offset 14, -4 3898:Src/main.c **** if (HAL_GPIO_ReadPin(SDMMC1_EN_GPIO_Port, SDMMC1_EN_Pin)==GPIO_PIN_RESET) 9295 .loc 1 3898 2 view .LVU2857 9296 .LVL873: 3899:Src/main.c **** { 9297 .loc 1 3899 2 view .LVU2858 3899:Src/main.c **** { 9298 .loc 1 3899 6 is_stmt 0 view .LVU2859 9299 0002 0121 movs r1, #1 9300 0004 0B48 ldr r0, .L531 9301 0006 FFF7FEFF bl HAL_GPIO_ReadPin 9302 .LVL874: 3899:Src/main.c **** { 9303 .loc 1 3899 5 discriminator 1 view .LVU2860 9304 000a 08B1 cbz r0, .L529 3917:Src/main.c **** } 9305 .loc 1 3917 10 view .LVU2861 9306 000c 0120 movs r0, #1 9307 .LVL875: 9308 .L524: 3919:Src/main.c **** 9309 .loc 1 3919 1 view .LVU2862 9310 000e 10BD pop {r4, pc} 9311 .LVL876: 9312 .L529: 3901:Src/main.c **** if (test==FR_OK) 9313 .loc 1 3901 3 is_stmt 1 view .LVU2863 3901:Src/main.c **** if (test==FR_OK) 9314 .loc 1 3901 10 is_stmt 0 view .LVU2864 9315 0010 0948 ldr r0, .L531+4 9316 0012 FFF7FEFF bl Mount_SD 9317 .LVL877: 3902:Src/main.c **** { 9318 .loc 1 3902 3 is_stmt 1 view .LVU2865 3902:Src/main.c **** { ARM GAS /tmp/ccLSPxIe.s page 564 9319 .loc 1 3902 6 is_stmt 0 view .LVU2866 9320 0016 08B1 cbz r0, .L530 3912:Src/main.c **** } 9321 .loc 1 3912 11 view .LVU2867 9322 0018 0120 movs r0, #1 9323 .LVL878: 3912:Src/main.c **** } 9324 .loc 1 3912 11 view .LVU2868 9325 001a F8E7 b .L524 9326 .LVL879: 9327 .L530: 3904:Src/main.c **** test = Create_File("FILE1.TXT"); // 0 -suc 9328 .loc 1 3904 4 is_stmt 1 view .LVU2869 3904:Src/main.c **** test = Create_File("FILE1.TXT"); // 0 -suc 9329 .loc 1 3904 11 is_stmt 0 view .LVU2870 9330 001c 074C ldr r4, .L531+8 9331 001e 2046 mov r0, r4 9332 .LVL880: 3904:Src/main.c **** test = Create_File("FILE1.TXT"); // 0 -suc 9333 .loc 1 3904 11 view .LVU2871 9334 0020 FFF7FEFF bl Remove_File 9335 .LVL881: 3905:Src/main.c **** //test = Write_File ("FILE1.TXT", "____OSGG main borad information. Program made by Kazakov Vikt 9336 .loc 1 3905 4 is_stmt 1 view .LVU2872 3905:Src/main.c **** //test = Write_File ("FILE1.TXT", "____OSGG main borad information. Program made by Kazakov Vikt 9337 .loc 1 3905 11 is_stmt 0 view .LVU2873 9338 0024 2046 mov r0, r4 9339 0026 FFF7FEFF bl Create_File 9340 .LVL882: 3907:Src/main.c **** return test; 9341 .loc 1 3907 4 is_stmt 1 view .LVU2874 3907:Src/main.c **** return test; 9342 .loc 1 3907 11 is_stmt 0 view .LVU2875 9343 002a 0348 ldr r0, .L531+4 9344 002c FFF7FEFF bl Unmount_SD 9345 .LVL883: 3908:Src/main.c **** } 9346 .loc 1 3908 4 is_stmt 1 view .LVU2876 3908:Src/main.c **** } 9347 .loc 1 3908 11 is_stmt 0 view .LVU2877 9348 0030 EDE7 b .L524 9349 .L532: 9350 0032 00BF .align 2 9351 .L531: 9352 0034 000C0240 .word 1073875968 9353 0038 00000000 .word .LC0 9354 003c 00000000 .word .LC2 9355 .cfi_endproc 9356 .LFE1244: 9358 .section .text.USART_TX,"ax",%progbits 9359 .align 1 9360 .global USART_TX 9361 .syntax unified 9362 .thumb 9363 .thumb_func 9365 USART_TX: 9366 .LVL884: ARM GAS /tmp/ccLSPxIe.s page 565 9367 .LFB1245: 3923:Src/main.c **** uint16_t ind = 0; 9368 .loc 1 3923 1 is_stmt 1 view -0 9369 .cfi_startproc 9370 @ args = 0, pretend = 0, frame = 0 9371 @ frame_needed = 0, uses_anonymous_args = 0 9372 @ link register save eliminated. 3923:Src/main.c **** uint16_t ind = 0; 9373 .loc 1 3923 1 is_stmt 0 view .LVU2879 9374 0000 8C46 mov ip, r1 3924:Src/main.c **** while (indCR3, USART_CR3_DMAT); 3570:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 3571:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3572:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 3573:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if DMA Mode is enabled for transmission 3574:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 DMAT LL_USART_IsEnabledDMAReq_TX 3575:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 3576:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). 3577:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3578:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_TX(const USART_TypeDef *USARTx) 3579:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 3580:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->CR3, USART_CR3_DMAT) == (USART_CR3_DMAT)) ? 1UL : 0UL); 3581:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 3582:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3583:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 3584:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Enable DMA Disabling on Reception Error 3585:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 DDRE LL_USART_EnableDMADeactOnRxErr 3586:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 3587:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 3588:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3589:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableDMADeactOnRxErr(USART_TypeDef *USARTx) 3590:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 3591:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** SET_BIT(USARTx->CR3, USART_CR3_DDRE); 3592:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 3593:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3594:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 3595:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Disable DMA Disabling on Reception Error 3596:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 DDRE LL_USART_DisableDMADeactOnRxErr 3597:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 3598:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 3599:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3600:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableDMADeactOnRxErr(USART_TypeDef *USARTx) 3601:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 3602:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** CLEAR_BIT(USARTx->CR3, USART_CR3_DDRE); 3603:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 3604:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3605:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 3606:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Indicate if DMA Disabling on Reception Error is disabled 3607:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 DDRE LL_USART_IsEnabledDMADeactOnRxErr 3608:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 3609:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). ARM GAS /tmp/ccLSPxIe.s page 567 3610:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3611:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledDMADeactOnRxErr(const USART_TypeDef *USARTx) 3612:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 3613:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->CR3, USART_CR3_DDRE) == (USART_CR3_DDRE)) ? 1UL : 0UL); 3614:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 3615:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3616:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 3617:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Get the data register address used for DMA transfer 3618:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll RDR RDR LL_USART_DMA_GetRegAddr\n 3619:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll TDR TDR LL_USART_DMA_GetRegAddr 3620:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 3621:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param Direction This parameter can be one of the following values: 3622:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_DMA_REG_DATA_TRANSMIT 3623:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_DMA_REG_DATA_RECEIVE 3624:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Address of data register 3625:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3626:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_DMA_GetRegAddr(const USART_TypeDef *USARTx, uint32_t Direction) 3627:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 3628:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** uint32_t data_reg_addr; 3629:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3630:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** if (Direction == LL_USART_DMA_REG_DATA_TRANSMIT) 3631:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 3632:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* return address of TDR register */ 3633:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** data_reg_addr = (uint32_t) &(USARTx->TDR); 3634:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 3635:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** else 3636:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 3637:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* return address of RDR register */ 3638:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** data_reg_addr = (uint32_t) &(USARTx->RDR); 3639:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 3640:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3641:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return data_reg_addr; 3642:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 3643:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3644:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 3645:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} 3646:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3647:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3648:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EF_Data_Management Data_Management 3649:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ 3650:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3651:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3652:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 3653:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Read Receiver Data register (Receive Data value, 8 bits) 3654:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll RDR RDR LL_USART_ReceiveData8 3655:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 3656:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Value between Min_Data=0x00 and Max_Data=0xFF 3657:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3658:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint8_t LL_USART_ReceiveData8(const USART_TypeDef *USARTx) 3659:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 3660:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return (uint8_t)(READ_BIT(USARTx->RDR, USART_RDR_RDR) & 0xFFU); 3661:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 3662:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3663:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 3664:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Read Receiver Data register (Receive Data value, 9 bits) 3665:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll RDR RDR LL_USART_ReceiveData9 3666:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance ARM GAS /tmp/ccLSPxIe.s page 568 3667:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Value between Min_Data=0x00 and Max_Data=0x1FF 3668:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3669:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint16_t LL_USART_ReceiveData9(const USART_TypeDef *USARTx) 3670:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 3671:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return (uint16_t)(READ_BIT(USARTx->RDR, USART_RDR_RDR)); 3672:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 3673:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** 3674:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** 3675:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Write in Transmitter Data Register (Transmit Data value, 8 bits) 3676:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll TDR TDR LL_USART_TransmitData8 3677:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance 3678:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param Value between Min_Data=0x00 and Max_Data=0xFF 3679:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None 3680:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ 3681:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_TransmitData8(USART_TypeDef *USARTx, uint8_t Value) 9414 .loc 7 3681 22 view .LVU2894 9415 .LBB638: 3682:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 3683:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** USARTx->TDR = Value; 9416 .loc 7 3683 3 view .LVU2895 9417 .loc 7 3683 15 is_stmt 0 view .LVU2896 9418 0018 034B ldr r3, .L538 9419 001a 9962 str r1, [r3, #40] 9420 .LVL890: 9421 .loc 7 3683 15 view .LVU2897 9422 .LBE638: 9423 .LBE637: 3929:Src/main.c **** } 9424 .loc 1 3929 5 is_stmt 1 view .LVU2898 3929:Src/main.c **** } 9425 .loc 1 3929 8 is_stmt 0 view .LVU2899 9426 001c 0132 adds r2, r2, #1 9427 .LVL891: 3929:Src/main.c **** } 9428 .loc 1 3929 8 view .LVU2900 9429 001e 92B2 uxth r2, r2 9430 .LVL892: 9431 .L534: 3925:Src/main.c **** { 9432 .loc 1 3925 13 is_stmt 1 view .LVU2901 9433 0020 6245 cmp r2, ip 9434 0022 F1D3 bcc .L536 3931:Src/main.c **** 9435 .loc 1 3931 1 is_stmt 0 view .LVU2902 9436 0024 7047 bx lr 9437 .L539: 9438 0026 00BF .align 2 9439 .L538: 9440 0028 00100140 .word 1073811456 9441 .cfi_endproc 9442 .LFE1245: 9444 .section .text.USART_TX_DMA,"ax",%progbits 9445 .align 1 9446 .global USART_TX_DMA 9447 .syntax unified 9448 .thumb 9449 .thumb_func ARM GAS /tmp/ccLSPxIe.s page 569 9451 USART_TX_DMA: 9452 .LFB1246: 3934:Src/main.c **** while (u_tx_flg) {}//Wait until previous transfer not complete. u_tx_flg is resetting in DMA inter 9453 .loc 1 3934 1 is_stmt 1 view -0 9454 .cfi_startproc 9455 @ args = 0, pretend = 0, frame = 0 9456 @ frame_needed = 0, uses_anonymous_args = 0 9457 @ link register save eliminated. 9458 .LVL893: 9459 .L541: 3935:Src/main.c **** LL_DMA_DisableStream(DMA2, LL_DMA_STREAM_7); 9460 .loc 1 3935 20 discriminator 1 view .LVU2904 3935:Src/main.c **** LL_DMA_DisableStream(DMA2, LL_DMA_STREAM_7); 9461 .loc 1 3935 9 discriminator 1 view .LVU2905 9462 0000 0D4B ldr r3, .L542 9463 0002 1B78 ldrb r3, [r3] @ zero_extendqisi2 9464 0004 002B cmp r3, #0 9465 0006 FBD1 bne .L541 3936:Src/main.c **** LL_DMA_SetDataLength(DMA2, LL_DMA_STREAM_7, sz); 9466 .loc 1 3936 2 view .LVU2906 9467 .LVL894: 9468 .LBB639: 9469 .LBI639: 517:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 9470 .loc 6 517 22 view .LVU2907 9471 .LBB640: 519:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 9472 .loc 6 519 3 view .LVU2908 9473 0008 0C4B ldr r3, .L542+4 9474 000a D3F8B820 ldr r2, [r3, #184] 9475 000e 22F00102 bic r2, r2, #1 9476 0012 C3F8B820 str r2, [r3, #184] 9477 .LVL895: 519:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 9478 .loc 6 519 3 is_stmt 0 view .LVU2909 9479 .LBE640: 9480 .LBE639: 3937:Src/main.c **** LL_DMA_EnableStream(DMA2, LL_DMA_STREAM_7); 9481 .loc 1 3937 3 is_stmt 1 view .LVU2910 9482 .LBB641: 9483 .LBI641: 971:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 9484 .loc 6 971 22 view .LVU2911 9485 .LBB642: 973:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 9486 .loc 6 973 3 view .LVU2912 9487 0016 D3F8BC20 ldr r2, [r3, #188] 9488 001a 6FF30F02 bfc r2, #0, #16 9489 001e 1043 orrs r0, r0, r2 9490 .LVL896: 973:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 9491 .loc 6 973 3 is_stmt 0 view .LVU2913 9492 0020 C3F8BC00 str r0, [r3, #188] 9493 .LVL897: 973:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 9494 .loc 6 973 3 view .LVU2914 9495 .LBE642: ARM GAS /tmp/ccLSPxIe.s page 570 9496 .LBE641: 3938:Src/main.c **** u_tx_flg = 1;//indicate that transfer begin 9497 .loc 1 3938 3 is_stmt 1 view .LVU2915 9498 .LBB643: 9499 .LBI643: 497:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 9500 .loc 6 497 22 view .LVU2916 9501 .LBB644: 499:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 9502 .loc 6 499 3 view .LVU2917 9503 0024 D3F8B820 ldr r2, [r3, #184] 9504 0028 42F00102 orr r2, r2, #1 9505 002c C3F8B820 str r2, [r3, #184] 9506 .LVL898: 499:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 9507 .loc 6 499 3 is_stmt 0 view .LVU2918 9508 .LBE644: 9509 .LBE643: 3939:Src/main.c **** } 9510 .loc 1 3939 2 is_stmt 1 view .LVU2919 3939:Src/main.c **** } 9511 .loc 1 3939 11 is_stmt 0 view .LVU2920 9512 0030 014B ldr r3, .L542 9513 0032 0122 movs r2, #1 9514 0034 1A70 strb r2, [r3] 3940:Src/main.c **** 9515 .loc 1 3940 1 view .LVU2921 9516 0036 7047 bx lr 9517 .L543: 9518 .align 2 9519 .L542: 9520 0038 00000000 .word u_tx_flg 9521 003c 00640240 .word 1073898496 9522 .cfi_endproc 9523 .LFE1246: 9525 .section .text.Error_Handler,"ax",%progbits 9526 .align 1 9527 .global Error_Handler 9528 .syntax unified 9529 .thumb 9530 .thumb_func 9532 Error_Handler: 9533 .LFB1248: 3948:Src/main.c **** //------------------------------------------------------- 3949:Src/main.c **** /* USER CODE END 4 */ 3950:Src/main.c **** 3951:Src/main.c **** /** 3952:Src/main.c **** * @brief This function is executed in case of error occurrence. 3953:Src/main.c **** * @retval None 3954:Src/main.c **** */ 3955:Src/main.c **** void Error_Handler(void) 3956:Src/main.c **** { 9534 .loc 1 3956 1 is_stmt 1 view -0 9535 .cfi_startproc 9536 @ Volatile: function does not return. 9537 @ args = 0, pretend = 0, frame = 0 9538 @ frame_needed = 0, uses_anonymous_args = 0 ARM GAS /tmp/ccLSPxIe.s page 571 9539 @ link register save eliminated. 3957:Src/main.c **** /* USER CODE BEGIN Error_Handler_Debug */ 3958:Src/main.c **** /* User can add his own implementation to report the HAL error return state */ 3959:Src/main.c **** __disable_irq(); 9540 .loc 1 3959 3 view .LVU2923 9541 .LBB645: 9542 .LBI645: 140:Drivers/CMSIS/Include/cmsis_gcc.h **** { 9543 .loc 8 140 27 view .LVU2924 9544 .LBB646: 142:Drivers/CMSIS/Include/cmsis_gcc.h **** } 9545 .loc 8 142 3 view .LVU2925 9546 .syntax unified 9547 @ 142 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 9548 0000 72B6 cpsid i 9549 @ 0 "" 2 9550 .thumb 9551 .syntax unified 9552 .L545: 9553 .LBE646: 9554 .LBE645: 3960:Src/main.c **** while (1) 9555 .loc 1 3960 3 view .LVU2926 3961:Src/main.c **** { 3962:Src/main.c **** } 9556 .loc 1 3962 3 view .LVU2927 3960:Src/main.c **** while (1) 9557 .loc 1 3960 9 view .LVU2928 9558 0002 FEE7 b .L545 9559 .cfi_endproc 9560 .LFE1248: 9562 .section .text.MX_ADC1_Init,"ax",%progbits 9563 .align 1 9564 .syntax unified 9565 .thumb 9566 .thumb_func 9568 MX_ADC1_Init: 9569 .LFB1188: 1199:Src/main.c **** 9570 .loc 1 1199 1 view -0 9571 .cfi_startproc 9572 @ args = 0, pretend = 0, frame = 16 9573 @ frame_needed = 0, uses_anonymous_args = 0 9574 0000 00B5 push {lr} 9575 .LCFI82: 9576 .cfi_def_cfa_offset 4 9577 .cfi_offset 14, -4 9578 0002 85B0 sub sp, sp, #20 9579 .LCFI83: 9580 .cfi_def_cfa_offset 24 1205:Src/main.c **** 9581 .loc 1 1205 3 view .LVU2930 1205:Src/main.c **** 9582 .loc 1 1205 26 is_stmt 0 view .LVU2931 9583 0004 0023 movs r3, #0 9584 0006 0093 str r3, [sp] 9585 0008 0193 str r3, [sp, #4] ARM GAS /tmp/ccLSPxIe.s page 572 9586 000a 0293 str r3, [sp, #8] 9587 000c 0393 str r3, [sp, #12] 1213:Src/main.c **** hadc1.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV8; 9588 .loc 1 1213 3 is_stmt 1 view .LVU2932 1213:Src/main.c **** hadc1.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV8; 9589 .loc 1 1213 18 is_stmt 0 view .LVU2933 9590 000e 2B48 ldr r0, .L560 9591 0010 2B4A ldr r2, .L560+4 9592 0012 0260 str r2, [r0] 1214:Src/main.c **** hadc1.Init.Resolution = ADC_RESOLUTION_12B; 9593 .loc 1 1214 3 is_stmt 1 view .LVU2934 1214:Src/main.c **** hadc1.Init.Resolution = ADC_RESOLUTION_12B; 9594 .loc 1 1214 29 is_stmt 0 view .LVU2935 9595 0014 4FF44032 mov r2, #196608 9596 0018 4260 str r2, [r0, #4] 1215:Src/main.c **** hadc1.Init.ScanConvMode = ADC_SCAN_ENABLE; 9597 .loc 1 1215 3 is_stmt 1 view .LVU2936 1215:Src/main.c **** hadc1.Init.ScanConvMode = ADC_SCAN_ENABLE; 9598 .loc 1 1215 25 is_stmt 0 view .LVU2937 9599 001a 8360 str r3, [r0, #8] 1216:Src/main.c **** hadc1.Init.ContinuousConvMode = DISABLE; 9600 .loc 1 1216 3 is_stmt 1 view .LVU2938 1216:Src/main.c **** hadc1.Init.ContinuousConvMode = DISABLE; 9601 .loc 1 1216 27 is_stmt 0 view .LVU2939 9602 001c 0122 movs r2, #1 9603 001e 0261 str r2, [r0, #16] 1217:Src/main.c **** hadc1.Init.DiscontinuousConvMode = DISABLE; 9604 .loc 1 1217 3 is_stmt 1 view .LVU2940 1217:Src/main.c **** hadc1.Init.DiscontinuousConvMode = DISABLE; 9605 .loc 1 1217 33 is_stmt 0 view .LVU2941 9606 0020 8361 str r3, [r0, #24] 1218:Src/main.c **** hadc1.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE; 9607 .loc 1 1218 3 is_stmt 1 view .LVU2942 1218:Src/main.c **** hadc1.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE; 9608 .loc 1 1218 36 is_stmt 0 view .LVU2943 9609 0022 80F82030 strb r3, [r0, #32] 1219:Src/main.c **** hadc1.Init.ExternalTrigConv = ADC_SOFTWARE_START; 9610 .loc 1 1219 3 is_stmt 1 view .LVU2944 1219:Src/main.c **** hadc1.Init.ExternalTrigConv = ADC_SOFTWARE_START; 9611 .loc 1 1219 35 is_stmt 0 view .LVU2945 9612 0026 C362 str r3, [r0, #44] 1220:Src/main.c **** hadc1.Init.DataAlign = ADC_DATAALIGN_RIGHT; 9613 .loc 1 1220 3 is_stmt 1 view .LVU2946 1220:Src/main.c **** hadc1.Init.DataAlign = ADC_DATAALIGN_RIGHT; 9614 .loc 1 1220 31 is_stmt 0 view .LVU2947 9615 0028 2649 ldr r1, .L560+8 9616 002a 8162 str r1, [r0, #40] 1221:Src/main.c **** hadc1.Init.NbrOfConversion = 5; 9617 .loc 1 1221 3 is_stmt 1 view .LVU2948 1221:Src/main.c **** hadc1.Init.NbrOfConversion = 5; 9618 .loc 1 1221 24 is_stmt 0 view .LVU2949 9619 002c C360 str r3, [r0, #12] 1222:Src/main.c **** hadc1.Init.DMAContinuousRequests = DISABLE; 9620 .loc 1 1222 3 is_stmt 1 view .LVU2950 1222:Src/main.c **** hadc1.Init.DMAContinuousRequests = DISABLE; 9621 .loc 1 1222 30 is_stmt 0 view .LVU2951 9622 002e 0521 movs r1, #5 ARM GAS /tmp/ccLSPxIe.s page 573 9623 0030 C161 str r1, [r0, #28] 1223:Src/main.c **** hadc1.Init.EOCSelection = ADC_EOC_SINGLE_CONV; 9624 .loc 1 1223 3 is_stmt 1 view .LVU2952 1223:Src/main.c **** hadc1.Init.EOCSelection = ADC_EOC_SINGLE_CONV; 9625 .loc 1 1223 36 is_stmt 0 view .LVU2953 9626 0032 80F83030 strb r3, [r0, #48] 1224:Src/main.c **** if (HAL_ADC_Init(&hadc1) != HAL_OK) 9627 .loc 1 1224 3 is_stmt 1 view .LVU2954 1224:Src/main.c **** if (HAL_ADC_Init(&hadc1) != HAL_OK) 9628 .loc 1 1224 27 is_stmt 0 view .LVU2955 9629 0036 4261 str r2, [r0, #20] 1225:Src/main.c **** { 9630 .loc 1 1225 3 is_stmt 1 view .LVU2956 1225:Src/main.c **** { 9631 .loc 1 1225 7 is_stmt 0 view .LVU2957 9632 0038 FFF7FEFF bl HAL_ADC_Init 9633 .LVL899: 1225:Src/main.c **** { 9634 .loc 1 1225 6 discriminator 1 view .LVU2958 9635 003c 0028 cmp r0, #0 9636 003e 31D1 bne .L554 1232:Src/main.c **** sConfig.Rank = ADC_REGULAR_RANK_1; 9637 .loc 1 1232 3 is_stmt 1 view .LVU2959 1232:Src/main.c **** sConfig.Rank = ADC_REGULAR_RANK_1; 9638 .loc 1 1232 19 is_stmt 0 view .LVU2960 9639 0040 0923 movs r3, #9 9640 0042 0093 str r3, [sp] 1233:Src/main.c **** sConfig.SamplingTime = ADC_SAMPLETIME_480CYCLES; 9641 .loc 1 1233 3 is_stmt 1 view .LVU2961 1233:Src/main.c **** sConfig.SamplingTime = ADC_SAMPLETIME_480CYCLES; 9642 .loc 1 1233 16 is_stmt 0 view .LVU2962 9643 0044 0123 movs r3, #1 9644 0046 0193 str r3, [sp, #4] 1234:Src/main.c **** if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 9645 .loc 1 1234 3 is_stmt 1 view .LVU2963 1234:Src/main.c **** if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 9646 .loc 1 1234 24 is_stmt 0 view .LVU2964 9647 0048 0723 movs r3, #7 9648 004a 0293 str r3, [sp, #8] 1235:Src/main.c **** { 9649 .loc 1 1235 3 is_stmt 1 view .LVU2965 1235:Src/main.c **** { 9650 .loc 1 1235 7 is_stmt 0 view .LVU2966 9651 004c 6946 mov r1, sp 9652 004e 1B48 ldr r0, .L560 9653 0050 FFF7FEFF bl HAL_ADC_ConfigChannel 9654 .LVL900: 1235:Src/main.c **** { 9655 .loc 1 1235 6 discriminator 1 view .LVU2967 9656 0054 40BB cbnz r0, .L555 1242:Src/main.c **** sConfig.Rank = ADC_REGULAR_RANK_2; 9657 .loc 1 1242 3 is_stmt 1 view .LVU2968 1242:Src/main.c **** sConfig.Rank = ADC_REGULAR_RANK_2; 9658 .loc 1 1242 19 is_stmt 0 view .LVU2969 9659 0056 0823 movs r3, #8 9660 0058 0093 str r3, [sp] 1243:Src/main.c **** if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) ARM GAS /tmp/ccLSPxIe.s page 574 9661 .loc 1 1243 3 is_stmt 1 view .LVU2970 1243:Src/main.c **** if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 9662 .loc 1 1243 16 is_stmt 0 view .LVU2971 9663 005a 0223 movs r3, #2 9664 005c 0193 str r3, [sp, #4] 1244:Src/main.c **** { 9665 .loc 1 1244 3 is_stmt 1 view .LVU2972 1244:Src/main.c **** { 9666 .loc 1 1244 7 is_stmt 0 view .LVU2973 9667 005e 6946 mov r1, sp 9668 0060 1648 ldr r0, .L560 9669 0062 FFF7FEFF bl HAL_ADC_ConfigChannel 9670 .LVL901: 1244:Src/main.c **** { 9671 .loc 1 1244 6 discriminator 1 view .LVU2974 9672 0066 08BB cbnz r0, .L556 1251:Src/main.c **** sConfig.Rank = ADC_REGULAR_RANK_3; 9673 .loc 1 1251 3 is_stmt 1 view .LVU2975 1251:Src/main.c **** sConfig.Rank = ADC_REGULAR_RANK_3; 9674 .loc 1 1251 19 is_stmt 0 view .LVU2976 9675 0068 0223 movs r3, #2 9676 006a 0093 str r3, [sp] 1252:Src/main.c **** if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 9677 .loc 1 1252 3 is_stmt 1 view .LVU2977 1252:Src/main.c **** if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 9678 .loc 1 1252 16 is_stmt 0 view .LVU2978 9679 006c 0323 movs r3, #3 9680 006e 0193 str r3, [sp, #4] 1253:Src/main.c **** { 9681 .loc 1 1253 3 is_stmt 1 view .LVU2979 1253:Src/main.c **** { 9682 .loc 1 1253 7 is_stmt 0 view .LVU2980 9683 0070 6946 mov r1, sp 9684 0072 1248 ldr r0, .L560 9685 0074 FFF7FEFF bl HAL_ADC_ConfigChannel 9686 .LVL902: 1253:Src/main.c **** { 9687 .loc 1 1253 6 discriminator 1 view .LVU2981 9688 0078 D0B9 cbnz r0, .L557 1260:Src/main.c **** sConfig.Rank = ADC_REGULAR_RANK_4; 9689 .loc 1 1260 3 is_stmt 1 view .LVU2982 1260:Src/main.c **** sConfig.Rank = ADC_REGULAR_RANK_4; 9690 .loc 1 1260 19 is_stmt 0 view .LVU2983 9691 007a 0A23 movs r3, #10 9692 007c 0093 str r3, [sp] 1261:Src/main.c **** if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 9693 .loc 1 1261 3 is_stmt 1 view .LVU2984 1261:Src/main.c **** if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 9694 .loc 1 1261 16 is_stmt 0 view .LVU2985 9695 007e 0423 movs r3, #4 9696 0080 0193 str r3, [sp, #4] 1262:Src/main.c **** { 9697 .loc 1 1262 3 is_stmt 1 view .LVU2986 1262:Src/main.c **** { 9698 .loc 1 1262 7 is_stmt 0 view .LVU2987 9699 0082 6946 mov r1, sp 9700 0084 0D48 ldr r0, .L560 ARM GAS /tmp/ccLSPxIe.s page 575 9701 0086 FFF7FEFF bl HAL_ADC_ConfigChannel 9702 .LVL903: 1262:Src/main.c **** { 9703 .loc 1 1262 6 discriminator 1 view .LVU2988 9704 008a 98B9 cbnz r0, .L558 1269:Src/main.c **** sConfig.Rank = ADC_REGULAR_RANK_5; 9705 .loc 1 1269 3 is_stmt 1 view .LVU2989 1269:Src/main.c **** sConfig.Rank = ADC_REGULAR_RANK_5; 9706 .loc 1 1269 19 is_stmt 0 view .LVU2990 9707 008c 0B23 movs r3, #11 9708 008e 0093 str r3, [sp] 1270:Src/main.c **** if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 9709 .loc 1 1270 3 is_stmt 1 view .LVU2991 1270:Src/main.c **** if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 9710 .loc 1 1270 16 is_stmt 0 view .LVU2992 9711 0090 0523 movs r3, #5 9712 0092 0193 str r3, [sp, #4] 1271:Src/main.c **** { 9713 .loc 1 1271 3 is_stmt 1 view .LVU2993 1271:Src/main.c **** { 9714 .loc 1 1271 7 is_stmt 0 view .LVU2994 9715 0094 6946 mov r1, sp 9716 0096 0948 ldr r0, .L560 9717 0098 FFF7FEFF bl HAL_ADC_ConfigChannel 9718 .LVL904: 1271:Src/main.c **** { 9719 .loc 1 1271 6 discriminator 1 view .LVU2995 9720 009c 60B9 cbnz r0, .L559 1279:Src/main.c **** 9721 .loc 1 1279 1 view .LVU2996 9722 009e 05B0 add sp, sp, #20 9723 .LCFI84: 9724 .cfi_remember_state 9725 .cfi_def_cfa_offset 4 9726 @ sp needed 9727 00a0 5DF804FB ldr pc, [sp], #4 9728 .L554: 9729 .LCFI85: 9730 .cfi_restore_state 1227:Src/main.c **** } 9731 .loc 1 1227 5 is_stmt 1 view .LVU2997 9732 00a4 FFF7FEFF bl Error_Handler 9733 .LVL905: 9734 .L555: 1237:Src/main.c **** } 9735 .loc 1 1237 5 view .LVU2998 9736 00a8 FFF7FEFF bl Error_Handler 9737 .LVL906: 9738 .L556: 1246:Src/main.c **** } 9739 .loc 1 1246 5 view .LVU2999 9740 00ac FFF7FEFF bl Error_Handler 9741 .LVL907: 9742 .L557: 1255:Src/main.c **** } 9743 .loc 1 1255 5 view .LVU3000 9744 00b0 FFF7FEFF bl Error_Handler ARM GAS /tmp/ccLSPxIe.s page 576 9745 .LVL908: 9746 .L558: 1264:Src/main.c **** } 9747 .loc 1 1264 5 view .LVU3001 9748 00b4 FFF7FEFF bl Error_Handler 9749 .LVL909: 9750 .L559: 1273:Src/main.c **** } 9751 .loc 1 1273 5 view .LVU3002 9752 00b8 FFF7FEFF bl Error_Handler 9753 .LVL910: 9754 .L561: 9755 .align 2 9756 .L560: 9757 00bc 00000000 .word hadc1 9758 00c0 00200140 .word 1073815552 9759 00c4 0100000F .word 251658241 9760 .cfi_endproc 9761 .LFE1188: 9763 .section .text.MX_ADC3_Init,"ax",%progbits 9764 .align 1 9765 .syntax unified 9766 .thumb 9767 .thumb_func 9769 MX_ADC3_Init: 9770 .LFB1189: 1287:Src/main.c **** 9771 .loc 1 1287 1 view -0 9772 .cfi_startproc 9773 @ args = 0, pretend = 0, frame = 16 9774 @ frame_needed = 0, uses_anonymous_args = 0 9775 0000 00B5 push {lr} 9776 .LCFI86: 9777 .cfi_def_cfa_offset 4 9778 .cfi_offset 14, -4 9779 0002 85B0 sub sp, sp, #20 9780 .LCFI87: 9781 .cfi_def_cfa_offset 24 1293:Src/main.c **** 9782 .loc 1 1293 3 view .LVU3004 1293:Src/main.c **** 9783 .loc 1 1293 26 is_stmt 0 view .LVU3005 9784 0004 0023 movs r3, #0 9785 0006 0093 str r3, [sp] 9786 0008 0193 str r3, [sp, #4] 9787 000a 0293 str r3, [sp, #8] 9788 000c 0393 str r3, [sp, #12] 1301:Src/main.c **** hadc3.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV8; 9789 .loc 1 1301 3 is_stmt 1 view .LVU3006 1301:Src/main.c **** hadc3.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV8; 9790 .loc 1 1301 18 is_stmt 0 view .LVU3007 9791 000e 1448 ldr r0, .L568 9792 0010 144A ldr r2, .L568+4 9793 0012 0260 str r2, [r0] 1302:Src/main.c **** hadc3.Init.Resolution = ADC_RESOLUTION_12B; 9794 .loc 1 1302 3 is_stmt 1 view .LVU3008 1302:Src/main.c **** hadc3.Init.Resolution = ADC_RESOLUTION_12B; ARM GAS /tmp/ccLSPxIe.s page 577 9795 .loc 1 1302 29 is_stmt 0 view .LVU3009 9796 0014 4FF44032 mov r2, #196608 9797 0018 4260 str r2, [r0, #4] 1303:Src/main.c **** hadc3.Init.ScanConvMode = ADC_SCAN_DISABLE; 9798 .loc 1 1303 3 is_stmt 1 view .LVU3010 1303:Src/main.c **** hadc3.Init.ScanConvMode = ADC_SCAN_DISABLE; 9799 .loc 1 1303 25 is_stmt 0 view .LVU3011 9800 001a 8360 str r3, [r0, #8] 1304:Src/main.c **** hadc3.Init.ContinuousConvMode = DISABLE; 9801 .loc 1 1304 3 is_stmt 1 view .LVU3012 1304:Src/main.c **** hadc3.Init.ContinuousConvMode = DISABLE; 9802 .loc 1 1304 27 is_stmt 0 view .LVU3013 9803 001c 0361 str r3, [r0, #16] 1305:Src/main.c **** hadc3.Init.DiscontinuousConvMode = DISABLE; 9804 .loc 1 1305 3 is_stmt 1 view .LVU3014 1305:Src/main.c **** hadc3.Init.DiscontinuousConvMode = DISABLE; 9805 .loc 1 1305 33 is_stmt 0 view .LVU3015 9806 001e 8361 str r3, [r0, #24] 1306:Src/main.c **** hadc3.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE; 9807 .loc 1 1306 3 is_stmt 1 view .LVU3016 1306:Src/main.c **** hadc3.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE; 9808 .loc 1 1306 36 is_stmt 0 view .LVU3017 9809 0020 80F82030 strb r3, [r0, #32] 1307:Src/main.c **** hadc3.Init.ExternalTrigConv = ADC_SOFTWARE_START; 9810 .loc 1 1307 3 is_stmt 1 view .LVU3018 1307:Src/main.c **** hadc3.Init.ExternalTrigConv = ADC_SOFTWARE_START; 9811 .loc 1 1307 35 is_stmt 0 view .LVU3019 9812 0024 C362 str r3, [r0, #44] 1308:Src/main.c **** hadc3.Init.DataAlign = ADC_DATAALIGN_RIGHT; 9813 .loc 1 1308 3 is_stmt 1 view .LVU3020 1308:Src/main.c **** hadc3.Init.DataAlign = ADC_DATAALIGN_RIGHT; 9814 .loc 1 1308 31 is_stmt 0 view .LVU3021 9815 0026 104A ldr r2, .L568+8 9816 0028 8262 str r2, [r0, #40] 1309:Src/main.c **** hadc3.Init.NbrOfConversion = 1; 9817 .loc 1 1309 3 is_stmt 1 view .LVU3022 1309:Src/main.c **** hadc3.Init.NbrOfConversion = 1; 9818 .loc 1 1309 24 is_stmt 0 view .LVU3023 9819 002a C360 str r3, [r0, #12] 1310:Src/main.c **** hadc3.Init.DMAContinuousRequests = DISABLE; 9820 .loc 1 1310 3 is_stmt 1 view .LVU3024 1310:Src/main.c **** hadc3.Init.DMAContinuousRequests = DISABLE; 9821 .loc 1 1310 30 is_stmt 0 view .LVU3025 9822 002c 0122 movs r2, #1 9823 002e C261 str r2, [r0, #28] 1311:Src/main.c **** hadc3.Init.EOCSelection = ADC_EOC_SINGLE_CONV; 9824 .loc 1 1311 3 is_stmt 1 view .LVU3026 1311:Src/main.c **** hadc3.Init.EOCSelection = ADC_EOC_SINGLE_CONV; 9825 .loc 1 1311 36 is_stmt 0 view .LVU3027 9826 0030 80F83030 strb r3, [r0, #48] 1312:Src/main.c **** if (HAL_ADC_Init(&hadc3) != HAL_OK) 9827 .loc 1 1312 3 is_stmt 1 view .LVU3028 1312:Src/main.c **** if (HAL_ADC_Init(&hadc3) != HAL_OK) 9828 .loc 1 1312 27 is_stmt 0 view .LVU3029 9829 0034 4261 str r2, [r0, #20] 1313:Src/main.c **** { 9830 .loc 1 1313 3 is_stmt 1 view .LVU3030 ARM GAS /tmp/ccLSPxIe.s page 578 1313:Src/main.c **** { 9831 .loc 1 1313 7 is_stmt 0 view .LVU3031 9832 0036 FFF7FEFF bl HAL_ADC_Init 9833 .LVL911: 1313:Src/main.c **** { 9834 .loc 1 1313 6 discriminator 1 view .LVU3032 9835 003a 68B9 cbnz r0, .L566 1320:Src/main.c **** sConfig.Rank = ADC_REGULAR_RANK_1; 9836 .loc 1 1320 3 is_stmt 1 view .LVU3033 1320:Src/main.c **** sConfig.Rank = ADC_REGULAR_RANK_1; 9837 .loc 1 1320 19 is_stmt 0 view .LVU3034 9838 003c 0F23 movs r3, #15 9839 003e 0093 str r3, [sp] 1321:Src/main.c **** sConfig.SamplingTime = ADC_SAMPLETIME_480CYCLES; 9840 .loc 1 1321 3 is_stmt 1 view .LVU3035 1321:Src/main.c **** sConfig.SamplingTime = ADC_SAMPLETIME_480CYCLES; 9841 .loc 1 1321 16 is_stmt 0 view .LVU3036 9842 0040 0123 movs r3, #1 9843 0042 0193 str r3, [sp, #4] 1322:Src/main.c **** if (HAL_ADC_ConfigChannel(&hadc3, &sConfig) != HAL_OK) 9844 .loc 1 1322 3 is_stmt 1 view .LVU3037 1322:Src/main.c **** if (HAL_ADC_ConfigChannel(&hadc3, &sConfig) != HAL_OK) 9845 .loc 1 1322 24 is_stmt 0 view .LVU3038 9846 0044 0723 movs r3, #7 9847 0046 0293 str r3, [sp, #8] 1323:Src/main.c **** { 9848 .loc 1 1323 3 is_stmt 1 view .LVU3039 1323:Src/main.c **** { 9849 .loc 1 1323 7 is_stmt 0 view .LVU3040 9850 0048 6946 mov r1, sp 9851 004a 0548 ldr r0, .L568 9852 004c FFF7FEFF bl HAL_ADC_ConfigChannel 9853 .LVL912: 1323:Src/main.c **** { 9854 .loc 1 1323 6 discriminator 1 view .LVU3041 9855 0050 20B9 cbnz r0, .L567 1331:Src/main.c **** 9856 .loc 1 1331 1 view .LVU3042 9857 0052 05B0 add sp, sp, #20 9858 .LCFI88: 9859 .cfi_remember_state 9860 .cfi_def_cfa_offset 4 9861 @ sp needed 9862 0054 5DF804FB ldr pc, [sp], #4 9863 .L566: 9864 .LCFI89: 9865 .cfi_restore_state 1315:Src/main.c **** } 9866 .loc 1 1315 5 is_stmt 1 view .LVU3043 9867 0058 FFF7FEFF bl Error_Handler 9868 .LVL913: 9869 .L567: 1325:Src/main.c **** } 9870 .loc 1 1325 5 view .LVU3044 9871 005c FFF7FEFF bl Error_Handler 9872 .LVL914: 9873 .L569: ARM GAS /tmp/ccLSPxIe.s page 579 9874 .align 2 9875 .L568: 9876 0060 00000000 .word hadc3 9877 0064 00220140 .word 1073816064 9878 0068 0100000F .word 251658241 9879 .cfi_endproc 9880 .LFE1189: 9882 .section .text.MX_USART1_UART_Init,"ax",%progbits 9883 .align 1 9884 .syntax unified 9885 .thumb 9886 .thumb_func 9888 MX_USART1_UART_Init: 9889 .LFB1205: 2067:Src/main.c **** 9890 .loc 1 2067 1 view -0 9891 .cfi_startproc 9892 @ args = 0, pretend = 0, frame = 208 9893 @ frame_needed = 0, uses_anonymous_args = 0 9894 0000 2DE9F041 push {r4, r5, r6, r7, r8, lr} 9895 .LCFI90: 9896 .cfi_def_cfa_offset 24 9897 .cfi_offset 4, -24 9898 .cfi_offset 5, -20 9899 .cfi_offset 6, -16 9900 .cfi_offset 7, -12 9901 .cfi_offset 8, -8 9902 .cfi_offset 14, -4 9903 0004 B4B0 sub sp, sp, #208 9904 .LCFI91: 9905 .cfi_def_cfa_offset 232 2073:Src/main.c **** 9906 .loc 1 2073 3 view .LVU3046 2073:Src/main.c **** 9907 .loc 1 2073 24 is_stmt 0 view .LVU3047 9908 0006 0021 movs r1, #0 9909 0008 2D91 str r1, [sp, #180] 9910 000a 2E91 str r1, [sp, #184] 9911 000c 2F91 str r1, [sp, #188] 9912 000e 3091 str r1, [sp, #192] 9913 0010 3191 str r1, [sp, #196] 9914 0012 3291 str r1, [sp, #200] 9915 0014 3391 str r1, [sp, #204] 2075:Src/main.c **** RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; 9916 .loc 1 2075 3 is_stmt 1 view .LVU3048 2075:Src/main.c **** RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; 9917 .loc 1 2075 23 is_stmt 0 view .LVU3049 9918 0016 2791 str r1, [sp, #156] 9919 0018 2891 str r1, [sp, #160] 9920 001a 2991 str r1, [sp, #164] 9921 001c 2A91 str r1, [sp, #168] 9922 001e 2B91 str r1, [sp, #172] 9923 0020 2C91 str r1, [sp, #176] 2076:Src/main.c **** 9924 .loc 1 2076 3 is_stmt 1 view .LVU3050 2076:Src/main.c **** 9925 .loc 1 2076 28 is_stmt 0 view .LVU3051 ARM GAS /tmp/ccLSPxIe.s page 580 9926 0022 9022 movs r2, #144 9927 0024 03A8 add r0, sp, #12 9928 0026 FFF7FEFF bl memset 9929 .LVL915: 2080:Src/main.c **** PeriphClkInitStruct.Usart1ClockSelection = RCC_USART1CLKSOURCE_PCLK2; 9930 .loc 1 2080 3 is_stmt 1 view .LVU3052 2080:Src/main.c **** PeriphClkInitStruct.Usart1ClockSelection = RCC_USART1CLKSOURCE_PCLK2; 9931 .loc 1 2080 44 is_stmt 0 view .LVU3053 9932 002a 4023 movs r3, #64 9933 002c 0393 str r3, [sp, #12] 2081:Src/main.c **** if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) 9934 .loc 1 2081 3 is_stmt 1 view .LVU3054 2082:Src/main.c **** { 9935 .loc 1 2082 3 view .LVU3055 2082:Src/main.c **** { 9936 .loc 1 2082 7 is_stmt 0 view .LVU3056 9937 002e 03A8 add r0, sp, #12 9938 0030 FFF7FEFF bl HAL_RCCEx_PeriphCLKConfig 9939 .LVL916: 2082:Src/main.c **** { 9940 .loc 1 2082 6 discriminator 1 view .LVU3057 9941 0034 0028 cmp r0, #0 9942 0036 40F09E80 bne .L573 2088:Src/main.c **** 9943 .loc 1 2088 3 is_stmt 1 view .LVU3058 9944 .LVL917: 9945 .LBB647: 9946 .LBI647: 1587:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { 9947 .loc 3 1587 22 view .LVU3059 9948 .LBB648: 1589:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** SET_BIT(RCC->APB2ENR, Periphs); 9949 .loc 3 1589 3 view .LVU3060 1590:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Delay after an RCC peripheral clock enabling */ 9950 .loc 3 1590 3 view .LVU3061 9951 003a 504B ldr r3, .L574 9952 003c 5A6C ldr r2, [r3, #68] 9953 003e 42F01002 orr r2, r2, #16 9954 0042 5A64 str r2, [r3, #68] 1592:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; 9955 .loc 3 1592 3 view .LVU3062 1592:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; 9956 .loc 3 1592 12 is_stmt 0 view .LVU3063 9957 0044 5A6C ldr r2, [r3, #68] 9958 0046 02F01002 and r2, r2, #16 1592:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; 9959 .loc 3 1592 10 view .LVU3064 9960 004a 0292 str r2, [sp, #8] 9961 .loc 3 1593 3 is_stmt 1 view .LVU3065 9962 004c 029A ldr r2, [sp, #8] 9963 .LVL918: 9964 .loc 3 1593 3 is_stmt 0 view .LVU3066 9965 .LBE648: 9966 .LBE647: 2090:Src/main.c **** /**USART1 GPIO Configuration 9967 .loc 1 2090 3 is_stmt 1 view .LVU3067 9968 .LBB649: ARM GAS /tmp/ccLSPxIe.s page 581 9969 .LBI649: 309:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { 9970 .loc 3 309 22 view .LVU3068 9971 .LBB650: 311:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** SET_BIT(RCC->AHB1ENR, Periphs); 9972 .loc 3 311 3 view .LVU3069 312:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Delay after an RCC peripheral clock enabling */ 9973 .loc 3 312 3 view .LVU3070 9974 004e 1A6B ldr r2, [r3, #48] 9975 0050 42F00102 orr r2, r2, #1 9976 0054 1A63 str r2, [r3, #48] 314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; 9977 .loc 3 314 3 view .LVU3071 314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; 9978 .loc 3 314 12 is_stmt 0 view .LVU3072 9979 0056 1B6B ldr r3, [r3, #48] 9980 0058 03F00103 and r3, r3, #1 314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; 9981 .loc 3 314 10 view .LVU3073 9982 005c 0193 str r3, [sp, #4] 315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } 9983 .loc 3 315 3 is_stmt 1 view .LVU3074 9984 005e 019B ldr r3, [sp, #4] 9985 .LVL919: 315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } 9986 .loc 3 315 3 is_stmt 0 view .LVU3075 9987 .LBE650: 9988 .LBE649: 2095:Src/main.c **** GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE; 9989 .loc 1 2095 3 is_stmt 1 view .LVU3076 2095:Src/main.c **** GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE; 9990 .loc 1 2095 23 is_stmt 0 view .LVU3077 9991 0060 4FF40073 mov r3, #512 9992 0064 2793 str r3, [sp, #156] 2096:Src/main.c **** GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH; 9993 .loc 1 2096 3 is_stmt 1 view .LVU3078 2096:Src/main.c **** GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH; 9994 .loc 1 2096 24 is_stmt 0 view .LVU3079 9995 0066 4FF00208 mov r8, #2 9996 006a CDF8A080 str r8, [sp, #160] 2097:Src/main.c **** GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; 9997 .loc 1 2097 3 is_stmt 1 view .LVU3080 2097:Src/main.c **** GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; 9998 .loc 1 2097 25 is_stmt 0 view .LVU3081 9999 006e 0327 movs r7, #3 10000 0070 2997 str r7, [sp, #164] 2098:Src/main.c **** GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; 10001 .loc 1 2098 3 is_stmt 1 view .LVU3082 2098:Src/main.c **** GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; 10002 .loc 1 2098 30 is_stmt 0 view .LVU3083 10003 0072 0024 movs r4, #0 10004 0074 2A94 str r4, [sp, #168] 2099:Src/main.c **** GPIO_InitStruct.Alternate = LL_GPIO_AF_7; 10005 .loc 1 2099 3 is_stmt 1 view .LVU3084 2099:Src/main.c **** GPIO_InitStruct.Alternate = LL_GPIO_AF_7; 10006 .loc 1 2099 24 is_stmt 0 view .LVU3085 10007 0076 2B94 str r4, [sp, #172] ARM GAS /tmp/ccLSPxIe.s page 582 2100:Src/main.c **** LL_GPIO_Init(GPIOA, &GPIO_InitStruct); 10008 .loc 1 2100 3 is_stmt 1 view .LVU3086 2100:Src/main.c **** LL_GPIO_Init(GPIOA, &GPIO_InitStruct); 10009 .loc 1 2100 29 is_stmt 0 view .LVU3087 10010 0078 0726 movs r6, #7 10011 007a 2C96 str r6, [sp, #176] 2101:Src/main.c **** 10012 .loc 1 2101 3 is_stmt 1 view .LVU3088 10013 007c 404D ldr r5, .L574+4 10014 007e 27A9 add r1, sp, #156 10015 0080 2846 mov r0, r5 10016 0082 FFF7FEFF bl LL_GPIO_Init 10017 .LVL920: 2103:Src/main.c **** GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE; 10018 .loc 1 2103 3 view .LVU3089 2103:Src/main.c **** GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE; 10019 .loc 1 2103 23 is_stmt 0 view .LVU3090 10020 0086 4FF48063 mov r3, #1024 10021 008a 2793 str r3, [sp, #156] 2104:Src/main.c **** GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH; 10022 .loc 1 2104 3 is_stmt 1 view .LVU3091 2104:Src/main.c **** GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH; 10023 .loc 1 2104 24 is_stmt 0 view .LVU3092 10024 008c CDF8A080 str r8, [sp, #160] 2105:Src/main.c **** GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; 10025 .loc 1 2105 3 is_stmt 1 view .LVU3093 2105:Src/main.c **** GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; 10026 .loc 1 2105 25 is_stmt 0 view .LVU3094 10027 0090 2997 str r7, [sp, #164] 2106:Src/main.c **** GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; 10028 .loc 1 2106 3 is_stmt 1 view .LVU3095 2106:Src/main.c **** GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; 10029 .loc 1 2106 30 is_stmt 0 view .LVU3096 10030 0092 2A94 str r4, [sp, #168] 2107:Src/main.c **** GPIO_InitStruct.Alternate = LL_GPIO_AF_7; 10031 .loc 1 2107 3 is_stmt 1 view .LVU3097 2107:Src/main.c **** GPIO_InitStruct.Alternate = LL_GPIO_AF_7; 10032 .loc 1 2107 24 is_stmt 0 view .LVU3098 10033 0094 2B94 str r4, [sp, #172] 2108:Src/main.c **** LL_GPIO_Init(GPIOA, &GPIO_InitStruct); 10034 .loc 1 2108 3 is_stmt 1 view .LVU3099 2108:Src/main.c **** LL_GPIO_Init(GPIOA, &GPIO_InitStruct); 10035 .loc 1 2108 29 is_stmt 0 view .LVU3100 10036 0096 2C96 str r6, [sp, #176] 2109:Src/main.c **** 10037 .loc 1 2109 3 is_stmt 1 view .LVU3101 10038 0098 27A9 add r1, sp, #156 10039 009a 2846 mov r0, r5 10040 009c FFF7FEFF bl LL_GPIO_Init 10041 .LVL921: 2114:Src/main.c **** 10042 .loc 1 2114 3 view .LVU3102 10043 .LBB651: 10044 .LBI651: 1032:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 10045 .loc 6 1032 22 view .LVU3103 10046 .LBB652: ARM GAS /tmp/ccLSPxIe.s page 583 1034:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 10047 .loc 6 1034 3 view .LVU3104 10048 00a0 384B ldr r3, .L574+8 10049 00a2 D3F8B820 ldr r2, [r3, #184] 10050 00a6 22F0F052 bic r2, r2, #503316480 10051 00aa 42F00062 orr r2, r2, #134217728 10052 00ae C3F8B820 str r2, [r3, #184] 10053 .LVL922: 1034:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 10054 .loc 6 1034 3 is_stmt 0 view .LVU3105 10055 .LBE652: 10056 .LBE651: 2116:Src/main.c **** 10057 .loc 1 2116 3 is_stmt 1 view .LVU3106 10058 .LBB653: 10059 .LBI653: 598:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 10060 .loc 6 598 22 view .LVU3107 10061 .LBB654: 600:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 10062 .loc 6 600 3 view .LVU3108 10063 00b2 D3F8B820 ldr r2, [r3, #184] 10064 00b6 22F0C002 bic r2, r2, #192 10065 00ba 42F04002 orr r2, r2, #64 10066 00be C3F8B820 str r2, [r3, #184] 10067 .LVL923: 600:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 10068 .loc 6 600 3 is_stmt 0 view .LVU3109 10069 .LBE654: 10070 .LBE653: 2118:Src/main.c **** 10071 .loc 1 2118 3 is_stmt 1 view .LVU3110 10072 .LBB655: 10073 .LBI655: 924:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 10074 .loc 6 924 22 view .LVU3111 10075 .LBB656: 926:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 10076 .loc 6 926 3 view .LVU3112 10077 00c2 D3F8B820 ldr r2, [r3, #184] 10078 00c6 42F44032 orr r2, r2, #196608 10079 00ca C3F8B820 str r2, [r3, #184] 10080 .LVL924: 926:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 10081 .loc 6 926 3 is_stmt 0 view .LVU3113 10082 .LBE656: 10083 .LBE655: 2120:Src/main.c **** 10084 .loc 1 2120 3 is_stmt 1 view .LVU3114 10085 .LBB657: 10086 .LBI657: 646:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 10087 .loc 6 646 22 view .LVU3115 10088 .LBB658: 648:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 10089 .loc 6 648 3 view .LVU3116 10090 00ce D3F8B820 ldr r2, [r3, #184] ARM GAS /tmp/ccLSPxIe.s page 584 10091 00d2 22F49072 bic r2, r2, #288 10092 00d6 C3F8B820 str r2, [r3, #184] 10093 .LVL925: 648:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 10094 .loc 6 648 3 is_stmt 0 view .LVU3117 10095 .LBE658: 10096 .LBE657: 2122:Src/main.c **** 10097 .loc 1 2122 3 is_stmt 1 view .LVU3118 10098 .LBB659: 10099 .LBI659: 693:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 10100 .loc 6 693 22 view .LVU3119 10101 .LBB660: 695:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 10102 .loc 6 695 3 view .LVU3120 10103 00da D3F8B820 ldr r2, [r3, #184] 10104 00de 22F40072 bic r2, r2, #512 10105 00e2 C3F8B820 str r2, [r3, #184] 10106 .LVL926: 695:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 10107 .loc 6 695 3 is_stmt 0 view .LVU3121 10108 .LBE660: 10109 .LBE659: 2124:Src/main.c **** 10110 .loc 1 2124 3 is_stmt 1 view .LVU3122 10111 .LBB661: 10112 .LBI661: 738:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 10113 .loc 6 738 22 view .LVU3123 10114 .LBB662: 740:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 10115 .loc 6 740 3 view .LVU3124 10116 00e6 D3F8B820 ldr r2, [r3, #184] 10117 00ea 42F48062 orr r2, r2, #1024 10118 00ee C3F8B820 str r2, [r3, #184] 10119 .LVL927: 740:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 10120 .loc 6 740 3 is_stmt 0 view .LVU3125 10121 .LBE662: 10122 .LBE661: 2126:Src/main.c **** 10123 .loc 1 2126 3 is_stmt 1 view .LVU3126 10124 .LBB663: 10125 .LBI663: 784:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 10126 .loc 6 784 22 view .LVU3127 10127 .LBB664: 786:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 10128 .loc 6 786 3 view .LVU3128 10129 00f2 D3F8B820 ldr r2, [r3, #184] 10130 00f6 22F4C052 bic r2, r2, #6144 10131 00fa C3F8B820 str r2, [r3, #184] 10132 .LVL928: 786:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 10133 .loc 6 786 3 is_stmt 0 view .LVU3129 10134 .LBE664: ARM GAS /tmp/ccLSPxIe.s page 585 10135 .LBE663: 2128:Src/main.c **** 10136 .loc 1 2128 3 is_stmt 1 view .LVU3130 10137 .LBB665: 10138 .LBI665: 831:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 10139 .loc 6 831 22 view .LVU3131 10140 .LBB666: 833:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 10141 .loc 6 833 3 view .LVU3132 10142 00fe D3F8B820 ldr r2, [r3, #184] 10143 0102 22F4C042 bic r2, r2, #24576 10144 0106 C3F8B820 str r2, [r3, #184] 10145 .LVL929: 833:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 10146 .loc 6 833 3 is_stmt 0 view .LVU3133 10147 .LBE666: 10148 .LBE665: 2130:Src/main.c **** 10149 .loc 1 2130 3 is_stmt 1 view .LVU3134 10150 .LBB667: 10151 .LBI667: 1299:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { 10152 .loc 6 1299 22 view .LVU3135 10153 .LBB668: 1301:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 10154 .loc 6 1301 3 view .LVU3136 10155 010a D3F8CC20 ldr r2, [r3, #204] 10156 010e 22F00402 bic r2, r2, #4 10157 0112 C3F8CC20 str r2, [r3, #204] 10158 .LVL930: 1301:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } 10159 .loc 6 1301 3 is_stmt 0 view .LVU3137 10160 .LBE668: 10161 .LBE667: 2133:Src/main.c **** NVIC_EnableIRQ(USART1_IRQn); 10162 .loc 1 2133 3 is_stmt 1 view .LVU3138 10163 .LBB669: 10164 .LBI669: 1884:Drivers/CMSIS/Include/core_cm7.h **** { 10165 .loc 2 1884 26 view .LVU3139 10166 .LBB670: 1886:Drivers/CMSIS/Include/core_cm7.h **** } 10167 .loc 2 1886 3 view .LVU3140 1886:Drivers/CMSIS/Include/core_cm7.h **** } 10168 .loc 2 1886 26 is_stmt 0 view .LVU3141 10169 0116 1C4B ldr r3, .L574+12 10170 0118 D868 ldr r0, [r3, #12] 10171 .LBE670: 10172 .LBE669: 2133:Src/main.c **** NVIC_EnableIRQ(USART1_IRQn); 10173 .loc 1 2133 3 discriminator 1 view .LVU3142 10174 011a 2246 mov r2, r4 10175 011c 2146 mov r1, r4 10176 011e C0F30220 ubfx r0, r0, #8, #3 10177 0122 FFF7FEFF bl NVIC_EncodePriority 10178 .LVL931: ARM GAS /tmp/ccLSPxIe.s page 586 10179 .LBB671: 10180 .LBI671: 2024:Drivers/CMSIS/Include/core_cm7.h **** { 10181 .loc 2 2024 22 is_stmt 1 view .LVU3143 10182 .LBB672: 2026:Drivers/CMSIS/Include/core_cm7.h **** { 10183 .loc 2 2026 3 view .LVU3144 2028:Drivers/CMSIS/Include/core_cm7.h **** } 10184 .loc 2 2028 5 view .LVU3145 2028:Drivers/CMSIS/Include/core_cm7.h **** } 10185 .loc 2 2028 49 is_stmt 0 view .LVU3146 10186 0126 0001 lsls r0, r0, #4 10187 .LVL932: 2028:Drivers/CMSIS/Include/core_cm7.h **** } 10188 .loc 2 2028 49 view .LVU3147 10189 0128 C0B2 uxtb r0, r0 2028:Drivers/CMSIS/Include/core_cm7.h **** } 10190 .loc 2 2028 47 view .LVU3148 10191 012a 184B ldr r3, .L574+16 10192 012c 83F82503 strb r0, [r3, #805] 10193 .LVL933: 2028:Drivers/CMSIS/Include/core_cm7.h **** } 10194 .loc 2 2028 47 view .LVU3149 10195 .LBE672: 10196 .LBE671: 2134:Src/main.c **** 10197 .loc 1 2134 3 is_stmt 1 view .LVU3150 10198 .LBB673: 10199 .LBI673: 1896:Drivers/CMSIS/Include/core_cm7.h **** { 10200 .loc 2 1896 22 view .LVU3151 10201 .LBB674: 1898:Drivers/CMSIS/Include/core_cm7.h **** { 10202 .loc 2 1898 3 view .LVU3152 1900:Drivers/CMSIS/Include/core_cm7.h **** } 10203 .loc 2 1900 5 view .LVU3153 1900:Drivers/CMSIS/Include/core_cm7.h **** } 10204 .loc 2 1900 43 is_stmt 0 view .LVU3154 10205 0130 2022 movs r2, #32 10206 0132 5A60 str r2, [r3, #4] 10207 .LVL934: 1900:Drivers/CMSIS/Include/core_cm7.h **** } 10208 .loc 2 1900 43 view .LVU3155 10209 .LBE674: 10210 .LBE673: 2139:Src/main.c **** USART_InitStruct.DataWidth = LL_USART_DATAWIDTH_8B; 10211 .loc 1 2139 3 is_stmt 1 view .LVU3156 2139:Src/main.c **** USART_InitStruct.DataWidth = LL_USART_DATAWIDTH_8B; 10212 .loc 1 2139 29 is_stmt 0 view .LVU3157 10213 0134 4FF4E133 mov r3, #115200 10214 0138 2D93 str r3, [sp, #180] 2140:Src/main.c **** USART_InitStruct.StopBits = LL_USART_STOPBITS_1; 10215 .loc 1 2140 3 is_stmt 1 view .LVU3158 2140:Src/main.c **** USART_InitStruct.StopBits = LL_USART_STOPBITS_1; 10216 .loc 1 2140 30 is_stmt 0 view .LVU3159 10217 013a 2E94 str r4, [sp, #184] 2141:Src/main.c **** USART_InitStruct.Parity = LL_USART_PARITY_NONE; ARM GAS /tmp/ccLSPxIe.s page 587 10218 .loc 1 2141 3 is_stmt 1 view .LVU3160 2141:Src/main.c **** USART_InitStruct.Parity = LL_USART_PARITY_NONE; 10219 .loc 1 2141 29 is_stmt 0 view .LVU3161 10220 013c 2F94 str r4, [sp, #188] 2142:Src/main.c **** USART_InitStruct.TransferDirection = LL_USART_DIRECTION_TX_RX; 10221 .loc 1 2142 3 is_stmt 1 view .LVU3162 2142:Src/main.c **** USART_InitStruct.TransferDirection = LL_USART_DIRECTION_TX_RX; 10222 .loc 1 2142 27 is_stmt 0 view .LVU3163 10223 013e 3094 str r4, [sp, #192] 2143:Src/main.c **** USART_InitStruct.HardwareFlowControl = LL_USART_HWCONTROL_NONE; 10224 .loc 1 2143 3 is_stmt 1 view .LVU3164 2143:Src/main.c **** USART_InitStruct.HardwareFlowControl = LL_USART_HWCONTROL_NONE; 10225 .loc 1 2143 38 is_stmt 0 view .LVU3165 10226 0140 0C23 movs r3, #12 10227 0142 3193 str r3, [sp, #196] 2144:Src/main.c **** USART_InitStruct.OverSampling = LL_USART_OVERSAMPLING_16; 10228 .loc 1 2144 3 is_stmt 1 view .LVU3166 2144:Src/main.c **** USART_InitStruct.OverSampling = LL_USART_OVERSAMPLING_16; 10229 .loc 1 2144 40 is_stmt 0 view .LVU3167 10230 0144 3294 str r4, [sp, #200] 2145:Src/main.c **** LL_USART_Init(USART1, &USART_InitStruct); 10231 .loc 1 2145 3 is_stmt 1 view .LVU3168 2145:Src/main.c **** LL_USART_Init(USART1, &USART_InitStruct); 10232 .loc 1 2145 33 is_stmt 0 view .LVU3169 10233 0146 3394 str r4, [sp, #204] 2146:Src/main.c **** LL_USART_ConfigAsyncMode(USART1); 10234 .loc 1 2146 3 is_stmt 1 view .LVU3170 10235 0148 04F18044 add r4, r4, #1073741824 10236 014c 04F58834 add r4, r4, #69632 10237 0150 2DA9 add r1, sp, #180 10238 0152 2046 mov r0, r4 10239 0154 FFF7FEFF bl LL_USART_Init 10240 .LVL935: 2147:Src/main.c **** LL_USART_Enable(USART1); 10241 .loc 1 2147 3 view .LVU3171 10242 .LBB675: 10243 .LBI675: 2320:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 10244 .loc 7 2320 22 view .LVU3172 10245 .LBB676: 2326:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN | USART_CR3_HDSEL)); 10246 .loc 7 2326 3 view .LVU3173 10247 0158 6368 ldr r3, [r4, #4] 10248 015a 23F49043 bic r3, r3, #18432 10249 015e 6360 str r3, [r4, #4] 2327:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 10250 .loc 7 2327 3 view .LVU3174 10251 0160 A368 ldr r3, [r4, #8] 10252 0162 23F02A03 bic r3, r3, #42 10253 0166 A360 str r3, [r4, #8] 10254 .LVL936: 2327:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 10255 .loc 7 2327 3 is_stmt 0 view .LVU3175 10256 .LBE676: 10257 .LBE675: 2148:Src/main.c **** /* USER CODE BEGIN USART1_Init 2 */ 10258 .loc 1 2148 3 is_stmt 1 view .LVU3176 ARM GAS /tmp/ccLSPxIe.s page 588 10259 .LBB677: 10260 .LBI677: 560:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { 10261 .loc 7 560 22 view .LVU3177 10262 .LBB678: 562:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 10263 .loc 7 562 3 view .LVU3178 10264 0168 2368 ldr r3, [r4] 10265 016a 43F00103 orr r3, r3, #1 10266 016e 2360 str r3, [r4] 10267 .LVL937: 562:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 10268 .loc 7 562 3 is_stmt 0 view .LVU3179 10269 .LBE678: 10270 .LBE677: 2153:Src/main.c **** 10271 .loc 1 2153 1 view .LVU3180 10272 0170 34B0 add sp, sp, #208 10273 .LCFI92: 10274 .cfi_remember_state 10275 .cfi_def_cfa_offset 24 10276 @ sp needed 10277 0172 BDE8F081 pop {r4, r5, r6, r7, r8, pc} 10278 .L573: 10279 .LCFI93: 10280 .cfi_restore_state 2084:Src/main.c **** } 10281 .loc 1 2084 5 is_stmt 1 view .LVU3181 10282 0176 FFF7FEFF bl Error_Handler 10283 .LVL938: 10284 .L575: 10285 017a 00BF .align 2 10286 .L574: 10287 017c 00380240 .word 1073887232 10288 0180 00000240 .word 1073872896 10289 0184 00640240 .word 1073898496 10290 0188 00ED00E0 .word -536810240 10291 018c 00E100E0 .word -536813312 10292 .cfi_endproc 10293 .LFE1205: 10295 .section .text.MX_TIM10_Init,"ax",%progbits 10296 .align 1 10297 .syntax unified 10298 .thumb 10299 .thumb_func 10301 MX_TIM10_Init: 10302 .LFB1201: 1886:Src/main.c **** 10303 .loc 1 1886 1 view -0 10304 .cfi_startproc 10305 @ args = 0, pretend = 0, frame = 0 10306 @ frame_needed = 0, uses_anonymous_args = 0 10307 0000 08B5 push {r3, lr} 10308 .LCFI94: 10309 .cfi_def_cfa_offset 8 10310 .cfi_offset 3, -8 10311 .cfi_offset 14, -4 ARM GAS /tmp/ccLSPxIe.s page 589 1895:Src/main.c **** htim10.Init.Prescaler = 183; 10312 .loc 1 1895 3 view .LVU3183 1895:Src/main.c **** htim10.Init.Prescaler = 183; 10313 .loc 1 1895 19 is_stmt 0 view .LVU3184 10314 0002 0848 ldr r0, .L580 10315 0004 084B ldr r3, .L580+4 10316 0006 0360 str r3, [r0] 1896:Src/main.c **** htim10.Init.CounterMode = TIM_COUNTERMODE_UP; 10317 .loc 1 1896 3 is_stmt 1 view .LVU3185 1896:Src/main.c **** htim10.Init.CounterMode = TIM_COUNTERMODE_UP; 10318 .loc 1 1896 25 is_stmt 0 view .LVU3186 10319 0008 B723 movs r3, #183 10320 000a 4360 str r3, [r0, #4] 1897:Src/main.c **** htim10.Init.Period = 9; 10321 .loc 1 1897 3 is_stmt 1 view .LVU3187 1897:Src/main.c **** htim10.Init.Period = 9; 10322 .loc 1 1897 27 is_stmt 0 view .LVU3188 10323 000c 0023 movs r3, #0 10324 000e 8360 str r3, [r0, #8] 1898:Src/main.c **** htim10.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; 10325 .loc 1 1898 3 is_stmt 1 view .LVU3189 1898:Src/main.c **** htim10.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; 10326 .loc 1 1898 22 is_stmt 0 view .LVU3190 10327 0010 0922 movs r2, #9 10328 0012 C260 str r2, [r0, #12] 1899:Src/main.c **** htim10.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; 10329 .loc 1 1899 3 is_stmt 1 view .LVU3191 1899:Src/main.c **** htim10.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; 10330 .loc 1 1899 29 is_stmt 0 view .LVU3192 10331 0014 0361 str r3, [r0, #16] 1900:Src/main.c **** if (HAL_TIM_Base_Init(&htim10) != HAL_OK) 10332 .loc 1 1900 3 is_stmt 1 view .LVU3193 1900:Src/main.c **** if (HAL_TIM_Base_Init(&htim10) != HAL_OK) 10333 .loc 1 1900 33 is_stmt 0 view .LVU3194 10334 0016 8361 str r3, [r0, #24] 1901:Src/main.c **** { 10335 .loc 1 1901 3 is_stmt 1 view .LVU3195 1901:Src/main.c **** { 10336 .loc 1 1901 7 is_stmt 0 view .LVU3196 10337 0018 FFF7FEFF bl HAL_TIM_Base_Init 10338 .LVL939: 1901:Src/main.c **** { 10339 .loc 1 1901 6 discriminator 1 view .LVU3197 10340 001c 00B9 cbnz r0, .L579 1909:Src/main.c **** 10341 .loc 1 1909 1 view .LVU3198 10342 001e 08BD pop {r3, pc} 10343 .L579: 1903:Src/main.c **** } 10344 .loc 1 1903 5 is_stmt 1 view .LVU3199 10345 0020 FFF7FEFF bl Error_Handler 10346 .LVL940: 10347 .L581: 10348 .align 2 10349 .L580: 10350 0024 00000000 .word htim10 10351 0028 00440140 .word 1073824768 ARM GAS /tmp/ccLSPxIe.s page 590 10352 .cfi_endproc 10353 .LFE1201: 10355 .section .text.MX_UART8_Init,"ax",%progbits 10356 .align 1 10357 .syntax unified 10358 .thumb 10359 .thumb_func 10361 MX_UART8_Init: 10362 .LFB1204: 2032:Src/main.c **** 10363 .loc 1 2032 1 view -0 10364 .cfi_startproc 10365 @ args = 0, pretend = 0, frame = 0 10366 @ frame_needed = 0, uses_anonymous_args = 0 10367 0000 08B5 push {r3, lr} 10368 .LCFI95: 10369 .cfi_def_cfa_offset 8 10370 .cfi_offset 3, -8 10371 .cfi_offset 14, -4 2041:Src/main.c **** huart8.Init.BaudRate = 115200; 10372 .loc 1 2041 3 view .LVU3201 2041:Src/main.c **** huart8.Init.BaudRate = 115200; 10373 .loc 1 2041 19 is_stmt 0 view .LVU3202 10374 0002 0B48 ldr r0, .L586 10375 0004 0B4B ldr r3, .L586+4 10376 0006 0360 str r3, [r0] 2042:Src/main.c **** huart8.Init.WordLength = UART_WORDLENGTH_8B; 10377 .loc 1 2042 3 is_stmt 1 view .LVU3203 2042:Src/main.c **** huart8.Init.WordLength = UART_WORDLENGTH_8B; 10378 .loc 1 2042 24 is_stmt 0 view .LVU3204 10379 0008 4FF4E133 mov r3, #115200 10380 000c 4360 str r3, [r0, #4] 2043:Src/main.c **** huart8.Init.StopBits = UART_STOPBITS_1; 10381 .loc 1 2043 3 is_stmt 1 view .LVU3205 2043:Src/main.c **** huart8.Init.StopBits = UART_STOPBITS_1; 10382 .loc 1 2043 26 is_stmt 0 view .LVU3206 10383 000e 0023 movs r3, #0 10384 0010 8360 str r3, [r0, #8] 2044:Src/main.c **** huart8.Init.Parity = UART_PARITY_NONE; 10385 .loc 1 2044 3 is_stmt 1 view .LVU3207 2044:Src/main.c **** huart8.Init.Parity = UART_PARITY_NONE; 10386 .loc 1 2044 24 is_stmt 0 view .LVU3208 10387 0012 C360 str r3, [r0, #12] 2045:Src/main.c **** huart8.Init.Mode = UART_MODE_TX_RX; 10388 .loc 1 2045 3 is_stmt 1 view .LVU3209 2045:Src/main.c **** huart8.Init.Mode = UART_MODE_TX_RX; 10389 .loc 1 2045 22 is_stmt 0 view .LVU3210 10390 0014 0361 str r3, [r0, #16] 2046:Src/main.c **** huart8.Init.HwFlowCtl = UART_HWCONTROL_NONE; 10391 .loc 1 2046 3 is_stmt 1 view .LVU3211 2046:Src/main.c **** huart8.Init.HwFlowCtl = UART_HWCONTROL_NONE; 10392 .loc 1 2046 20 is_stmt 0 view .LVU3212 10393 0016 0C22 movs r2, #12 10394 0018 4261 str r2, [r0, #20] 2047:Src/main.c **** huart8.Init.OverSampling = UART_OVERSAMPLING_16; 10395 .loc 1 2047 3 is_stmt 1 view .LVU3213 2047:Src/main.c **** huart8.Init.OverSampling = UART_OVERSAMPLING_16; ARM GAS /tmp/ccLSPxIe.s page 591 10396 .loc 1 2047 25 is_stmt 0 view .LVU3214 10397 001a 8361 str r3, [r0, #24] 2048:Src/main.c **** huart8.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE; 10398 .loc 1 2048 3 is_stmt 1 view .LVU3215 2048:Src/main.c **** huart8.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE; 10399 .loc 1 2048 28 is_stmt 0 view .LVU3216 10400 001c C361 str r3, [r0, #28] 2049:Src/main.c **** huart8.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT; 10401 .loc 1 2049 3 is_stmt 1 view .LVU3217 2049:Src/main.c **** huart8.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT; 10402 .loc 1 2049 30 is_stmt 0 view .LVU3218 10403 001e 0362 str r3, [r0, #32] 2050:Src/main.c **** if (HAL_UART_Init(&huart8) != HAL_OK) 10404 .loc 1 2050 3 is_stmt 1 view .LVU3219 2050:Src/main.c **** if (HAL_UART_Init(&huart8) != HAL_OK) 10405 .loc 1 2050 38 is_stmt 0 view .LVU3220 10406 0020 4362 str r3, [r0, #36] 2051:Src/main.c **** { 10407 .loc 1 2051 3 is_stmt 1 view .LVU3221 2051:Src/main.c **** { 10408 .loc 1 2051 7 is_stmt 0 view .LVU3222 10409 0022 FFF7FEFF bl HAL_UART_Init 10410 .LVL941: 2051:Src/main.c **** { 10411 .loc 1 2051 6 discriminator 1 view .LVU3223 10412 0026 00B9 cbnz r0, .L585 2059:Src/main.c **** 10413 .loc 1 2059 1 view .LVU3224 10414 0028 08BD pop {r3, pc} 10415 .L585: 2053:Src/main.c **** } 10416 .loc 1 2053 5 is_stmt 1 view .LVU3225 10417 002a FFF7FEFF bl Error_Handler 10418 .LVL942: 10419 .L587: 10420 002e 00BF .align 2 10421 .L586: 10422 0030 00000000 .word huart8 10423 0034 007C0040 .word 1073773568 10424 .cfi_endproc 10425 .LFE1204: 10427 .section .text.MX_TIM8_Init,"ax",%progbits 10428 .align 1 10429 .syntax unified 10430 .thumb 10431 .thumb_func 10433 MX_TIM8_Init: 10434 .LFB1200: 1839:Src/main.c **** 10435 .loc 1 1839 1 view -0 10436 .cfi_startproc 10437 @ args = 0, pretend = 0, frame = 32 10438 @ frame_needed = 0, uses_anonymous_args = 0 10439 0000 00B5 push {lr} 10440 .LCFI96: 10441 .cfi_def_cfa_offset 4 10442 .cfi_offset 14, -4 ARM GAS /tmp/ccLSPxIe.s page 592 10443 0002 89B0 sub sp, sp, #36 10444 .LCFI97: 10445 .cfi_def_cfa_offset 40 1845:Src/main.c **** TIM_MasterConfigTypeDef sMasterConfig = {0}; 10446 .loc 1 1845 3 view .LVU3227 1845:Src/main.c **** TIM_MasterConfigTypeDef sMasterConfig = {0}; 10447 .loc 1 1845 26 is_stmt 0 view .LVU3228 10448 0004 0023 movs r3, #0 10449 0006 0493 str r3, [sp, #16] 10450 0008 0593 str r3, [sp, #20] 10451 000a 0693 str r3, [sp, #24] 10452 000c 0793 str r3, [sp, #28] 1846:Src/main.c **** 10453 .loc 1 1846 3 is_stmt 1 view .LVU3229 1846:Src/main.c **** 10454 .loc 1 1846 27 is_stmt 0 view .LVU3230 10455 000e 0193 str r3, [sp, #4] 10456 0010 0293 str r3, [sp, #8] 10457 0012 0393 str r3, [sp, #12] 1851:Src/main.c **** htim8.Init.Prescaler = 0; 10458 .loc 1 1851 3 is_stmt 1 view .LVU3231 1851:Src/main.c **** htim8.Init.Prescaler = 0; 10459 .loc 1 1851 18 is_stmt 0 view .LVU3232 10460 0014 1348 ldr r0, .L596 10461 0016 144A ldr r2, .L596+4 10462 0018 0260 str r2, [r0] 1852:Src/main.c **** htim8.Init.CounterMode = TIM_COUNTERMODE_UP; 10463 .loc 1 1852 3 is_stmt 1 view .LVU3233 1852:Src/main.c **** htim8.Init.CounterMode = TIM_COUNTERMODE_UP; 10464 .loc 1 1852 24 is_stmt 0 view .LVU3234 10465 001a 4360 str r3, [r0, #4] 1853:Src/main.c **** htim8.Init.Period = 91; 10466 .loc 1 1853 3 is_stmt 1 view .LVU3235 1853:Src/main.c **** htim8.Init.Period = 91; 10467 .loc 1 1853 26 is_stmt 0 view .LVU3236 10468 001c 8360 str r3, [r0, #8] 1854:Src/main.c **** htim8.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; 10469 .loc 1 1854 3 is_stmt 1 view .LVU3237 1854:Src/main.c **** htim8.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; 10470 .loc 1 1854 21 is_stmt 0 view .LVU3238 10471 001e 5B22 movs r2, #91 10472 0020 C260 str r2, [r0, #12] 1855:Src/main.c **** htim8.Init.RepetitionCounter = 0; 10473 .loc 1 1855 3 is_stmt 1 view .LVU3239 1855:Src/main.c **** htim8.Init.RepetitionCounter = 0; 10474 .loc 1 1855 28 is_stmt 0 view .LVU3240 10475 0022 0361 str r3, [r0, #16] 1856:Src/main.c **** htim8.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; 10476 .loc 1 1856 3 is_stmt 1 view .LVU3241 1856:Src/main.c **** htim8.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; 10477 .loc 1 1856 32 is_stmt 0 view .LVU3242 10478 0024 4361 str r3, [r0, #20] 1857:Src/main.c **** if (HAL_TIM_Base_Init(&htim8) != HAL_OK) 10479 .loc 1 1857 3 is_stmt 1 view .LVU3243 1857:Src/main.c **** if (HAL_TIM_Base_Init(&htim8) != HAL_OK) 10480 .loc 1 1857 32 is_stmt 0 view .LVU3244 10481 0026 8361 str r3, [r0, #24] ARM GAS /tmp/ccLSPxIe.s page 593 1858:Src/main.c **** { 10482 .loc 1 1858 3 is_stmt 1 view .LVU3245 1858:Src/main.c **** { 10483 .loc 1 1858 7 is_stmt 0 view .LVU3246 10484 0028 FFF7FEFF bl HAL_TIM_Base_Init 10485 .LVL943: 1858:Src/main.c **** { 10486 .loc 1 1858 6 discriminator 1 view .LVU3247 10487 002c 98B9 cbnz r0, .L593 1862:Src/main.c **** if (HAL_TIM_ConfigClockSource(&htim8, &sClockSourceConfig) != HAL_OK) 10488 .loc 1 1862 3 is_stmt 1 view .LVU3248 1862:Src/main.c **** if (HAL_TIM_ConfigClockSource(&htim8, &sClockSourceConfig) != HAL_OK) 10489 .loc 1 1862 34 is_stmt 0 view .LVU3249 10490 002e 4FF48053 mov r3, #4096 10491 0032 0493 str r3, [sp, #16] 1863:Src/main.c **** { 10492 .loc 1 1863 3 is_stmt 1 view .LVU3250 1863:Src/main.c **** { 10493 .loc 1 1863 7 is_stmt 0 view .LVU3251 10494 0034 04A9 add r1, sp, #16 10495 0036 0B48 ldr r0, .L596 10496 0038 FFF7FEFF bl HAL_TIM_ConfigClockSource 10497 .LVL944: 1863:Src/main.c **** { 10498 .loc 1 1863 6 discriminator 1 view .LVU3252 10499 003c 68B9 cbnz r0, .L594 1867:Src/main.c **** sMasterConfig.MasterOutputTrigger2 = TIM_TRGO2_RESET; 10500 .loc 1 1867 3 is_stmt 1 view .LVU3253 1867:Src/main.c **** sMasterConfig.MasterOutputTrigger2 = TIM_TRGO2_RESET; 10501 .loc 1 1867 37 is_stmt 0 view .LVU3254 10502 003e 0023 movs r3, #0 10503 0040 0193 str r3, [sp, #4] 1868:Src/main.c **** sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; 10504 .loc 1 1868 3 is_stmt 1 view .LVU3255 1868:Src/main.c **** sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; 10505 .loc 1 1868 38 is_stmt 0 view .LVU3256 10506 0042 0293 str r3, [sp, #8] 1869:Src/main.c **** if (HAL_TIMEx_MasterConfigSynchronization(&htim8, &sMasterConfig) != HAL_OK) 10507 .loc 1 1869 3 is_stmt 1 view .LVU3257 1869:Src/main.c **** if (HAL_TIMEx_MasterConfigSynchronization(&htim8, &sMasterConfig) != HAL_OK) 10508 .loc 1 1869 33 is_stmt 0 view .LVU3258 10509 0044 0393 str r3, [sp, #12] 1870:Src/main.c **** { 10510 .loc 1 1870 3 is_stmt 1 view .LVU3259 1870:Src/main.c **** { 10511 .loc 1 1870 7 is_stmt 0 view .LVU3260 10512 0046 01A9 add r1, sp, #4 10513 0048 0648 ldr r0, .L596 10514 004a FFF7FEFF bl HAL_TIMEx_MasterConfigSynchronization 10515 .LVL945: 1870:Src/main.c **** { 10516 .loc 1 1870 6 discriminator 1 view .LVU3261 10517 004e 30B9 cbnz r0, .L595 1878:Src/main.c **** 10518 .loc 1 1878 1 view .LVU3262 10519 0050 09B0 add sp, sp, #36 10520 .LCFI98: ARM GAS /tmp/ccLSPxIe.s page 594 10521 .cfi_remember_state 10522 .cfi_def_cfa_offset 4 10523 @ sp needed 10524 0052 5DF804FB ldr pc, [sp], #4 10525 .L593: 10526 .LCFI99: 10527 .cfi_restore_state 1860:Src/main.c **** } 10528 .loc 1 1860 5 is_stmt 1 view .LVU3263 10529 0056 FFF7FEFF bl Error_Handler 10530 .LVL946: 10531 .L594: 1865:Src/main.c **** } 10532 .loc 1 1865 5 view .LVU3264 10533 005a FFF7FEFF bl Error_Handler 10534 .LVL947: 10535 .L595: 1872:Src/main.c **** } 10536 .loc 1 1872 5 view .LVU3265 10537 005e FFF7FEFF bl Error_Handler 10538 .LVL948: 10539 .L597: 10540 0062 00BF .align 2 10541 .L596: 10542 0064 00000000 .word htim8 10543 0068 00040140 .word 1073808384 10544 .cfi_endproc 10545 .LFE1200: 10547 .section .text.MX_TIM11_Init,"ax",%progbits 10548 .align 1 10549 .syntax unified 10550 .thumb 10551 .thumb_func 10553 MX_TIM11_Init: 10554 .LFB1202: 1917:Src/main.c **** 10555 .loc 1 1917 1 view -0 10556 .cfi_startproc 10557 @ args = 0, pretend = 0, frame = 32 10558 @ frame_needed = 0, uses_anonymous_args = 0 10559 0000 00B5 push {lr} 10560 .LCFI100: 10561 .cfi_def_cfa_offset 4 10562 .cfi_offset 14, -4 10563 0002 89B0 sub sp, sp, #36 10564 .LCFI101: 10565 .cfi_def_cfa_offset 40 1923:Src/main.c **** 10566 .loc 1 1923 3 view .LVU3267 1923:Src/main.c **** 10567 .loc 1 1923 22 is_stmt 0 view .LVU3268 10568 0004 0023 movs r3, #0 10569 0006 0193 str r3, [sp, #4] 10570 0008 0293 str r3, [sp, #8] 10571 000a 0393 str r3, [sp, #12] 10572 000c 0493 str r3, [sp, #16] 10573 000e 0593 str r3, [sp, #20] ARM GAS /tmp/ccLSPxIe.s page 595 10574 0010 0693 str r3, [sp, #24] 10575 0012 0793 str r3, [sp, #28] 1928:Src/main.c **** htim11.Init.Prescaler = 1; 10576 .loc 1 1928 3 is_stmt 1 view .LVU3269 1928:Src/main.c **** htim11.Init.Prescaler = 1; 10577 .loc 1 1928 19 is_stmt 0 view .LVU3270 10578 0014 1448 ldr r0, .L606 10579 0016 154A ldr r2, .L606+4 10580 0018 0260 str r2, [r0] 1929:Src/main.c **** htim11.Init.CounterMode = TIM_COUNTERMODE_UP; 10581 .loc 1 1929 3 is_stmt 1 view .LVU3271 1929:Src/main.c **** htim11.Init.CounterMode = TIM_COUNTERMODE_UP; 10582 .loc 1 1929 25 is_stmt 0 view .LVU3272 10583 001a 0122 movs r2, #1 10584 001c 4260 str r2, [r0, #4] 1930:Src/main.c **** htim11.Init.Period = 91; 10585 .loc 1 1930 3 is_stmt 1 view .LVU3273 1930:Src/main.c **** htim11.Init.Period = 91; 10586 .loc 1 1930 27 is_stmt 0 view .LVU3274 10587 001e 8360 str r3, [r0, #8] 1931:Src/main.c **** htim11.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; 10588 .loc 1 1931 3 is_stmt 1 view .LVU3275 1931:Src/main.c **** htim11.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; 10589 .loc 1 1931 22 is_stmt 0 view .LVU3276 10590 0020 5B22 movs r2, #91 10591 0022 C260 str r2, [r0, #12] 1932:Src/main.c **** htim11.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_ENABLE; 10592 .loc 1 1932 3 is_stmt 1 view .LVU3277 1932:Src/main.c **** htim11.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_ENABLE; 10593 .loc 1 1932 29 is_stmt 0 view .LVU3278 10594 0024 0361 str r3, [r0, #16] 1933:Src/main.c **** if (HAL_TIM_Base_Init(&htim11) != HAL_OK) 10595 .loc 1 1933 3 is_stmt 1 view .LVU3279 1933:Src/main.c **** if (HAL_TIM_Base_Init(&htim11) != HAL_OK) 10596 .loc 1 1933 33 is_stmt 0 view .LVU3280 10597 0026 8023 movs r3, #128 10598 0028 8361 str r3, [r0, #24] 1934:Src/main.c **** { 10599 .loc 1 1934 3 is_stmt 1 view .LVU3281 1934:Src/main.c **** { 10600 .loc 1 1934 7 is_stmt 0 view .LVU3282 10601 002a FFF7FEFF bl HAL_TIM_Base_Init 10602 .LVL949: 1934:Src/main.c **** { 10603 .loc 1 1934 6 discriminator 1 view .LVU3283 10604 002e A8B9 cbnz r0, .L603 1938:Src/main.c **** { 10605 .loc 1 1938 3 is_stmt 1 view .LVU3284 1938:Src/main.c **** { 10606 .loc 1 1938 7 is_stmt 0 view .LVU3285 10607 0030 0D48 ldr r0, .L606 10608 0032 FFF7FEFF bl HAL_TIM_PWM_Init 10609 .LVL950: 1938:Src/main.c **** { 10610 .loc 1 1938 6 discriminator 1 view .LVU3286 10611 0036 98B9 cbnz r0, .L604 1942:Src/main.c **** sConfigOC.Pulse = 91; ARM GAS /tmp/ccLSPxIe.s page 596 10612 .loc 1 1942 3 is_stmt 1 view .LVU3287 1942:Src/main.c **** sConfigOC.Pulse = 91; 10613 .loc 1 1942 20 is_stmt 0 view .LVU3288 10614 0038 6023 movs r3, #96 10615 003a 0193 str r3, [sp, #4] 1943:Src/main.c **** sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH; 10616 .loc 1 1943 3 is_stmt 1 view .LVU3289 1943:Src/main.c **** sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH; 10617 .loc 1 1943 19 is_stmt 0 view .LVU3290 10618 003c 5B23 movs r3, #91 10619 003e 0293 str r3, [sp, #8] 1944:Src/main.c **** sConfigOC.OCFastMode = TIM_OCFAST_DISABLE; 10620 .loc 1 1944 3 is_stmt 1 view .LVU3291 1944:Src/main.c **** sConfigOC.OCFastMode = TIM_OCFAST_DISABLE; 10621 .loc 1 1944 24 is_stmt 0 view .LVU3292 10622 0040 0022 movs r2, #0 10623 0042 0392 str r2, [sp, #12] 1945:Src/main.c **** if (HAL_TIM_PWM_ConfigChannel(&htim11, &sConfigOC, TIM_CHANNEL_1) != HAL_OK) 10624 .loc 1 1945 3 is_stmt 1 view .LVU3293 1945:Src/main.c **** if (HAL_TIM_PWM_ConfigChannel(&htim11, &sConfigOC, TIM_CHANNEL_1) != HAL_OK) 10625 .loc 1 1945 24 is_stmt 0 view .LVU3294 10626 0044 0592 str r2, [sp, #20] 1946:Src/main.c **** { 10627 .loc 1 1946 3 is_stmt 1 view .LVU3295 1946:Src/main.c **** { 10628 .loc 1 1946 7 is_stmt 0 view .LVU3296 10629 0046 01A9 add r1, sp, #4 10630 0048 0748 ldr r0, .L606 10631 004a FFF7FEFF bl HAL_TIM_PWM_ConfigChannel 10632 .LVL951: 1946:Src/main.c **** { 10633 .loc 1 1946 6 discriminator 1 view .LVU3297 10634 004e 48B9 cbnz r0, .L605 1953:Src/main.c **** 10635 .loc 1 1953 3 is_stmt 1 view .LVU3298 10636 0050 0548 ldr r0, .L606 10637 0052 FFF7FEFF bl HAL_TIM_MspPostInit 10638 .LVL952: 1955:Src/main.c **** 10639 .loc 1 1955 1 is_stmt 0 view .LVU3299 10640 0056 09B0 add sp, sp, #36 10641 .LCFI102: 10642 .cfi_remember_state 10643 .cfi_def_cfa_offset 4 10644 @ sp needed 10645 0058 5DF804FB ldr pc, [sp], #4 10646 .L603: 10647 .LCFI103: 10648 .cfi_restore_state 1936:Src/main.c **** } 10649 .loc 1 1936 5 is_stmt 1 view .LVU3300 10650 005c FFF7FEFF bl Error_Handler 10651 .LVL953: 10652 .L604: 1940:Src/main.c **** } 10653 .loc 1 1940 5 view .LVU3301 10654 0060 FFF7FEFF bl Error_Handler ARM GAS /tmp/ccLSPxIe.s page 597 10655 .LVL954: 10656 .L605: 1948:Src/main.c **** } 10657 .loc 1 1948 5 view .LVU3302 10658 0064 FFF7FEFF bl Error_Handler 10659 .LVL955: 10660 .L607: 10661 .align 2 10662 .L606: 10663 0068 00000000 .word htim11 10664 006c 00480140 .word 1073825792 10665 .cfi_endproc 10666 .LFE1202: 10668 .section .text.MX_TIM4_Init,"ax",%progbits 10669 .align 1 10670 .syntax unified 10671 .thumb 10672 .thumb_func 10674 MX_TIM4_Init: 10675 .LFB1196: 1667:Src/main.c **** 10676 .loc 1 1667 1 view -0 10677 .cfi_startproc 10678 @ args = 0, pretend = 0, frame = 56 10679 @ frame_needed = 0, uses_anonymous_args = 0 10680 0000 00B5 push {lr} 10681 .LCFI104: 10682 .cfi_def_cfa_offset 4 10683 .cfi_offset 14, -4 10684 0002 8FB0 sub sp, sp, #60 10685 .LCFI105: 10686 .cfi_def_cfa_offset 64 1673:Src/main.c **** TIM_MasterConfigTypeDef sMasterConfig = {0}; 10687 .loc 1 1673 3 view .LVU3304 1673:Src/main.c **** TIM_MasterConfigTypeDef sMasterConfig = {0}; 10688 .loc 1 1673 26 is_stmt 0 view .LVU3305 10689 0004 0023 movs r3, #0 10690 0006 0A93 str r3, [sp, #40] 10691 0008 0B93 str r3, [sp, #44] 10692 000a 0C93 str r3, [sp, #48] 10693 000c 0D93 str r3, [sp, #52] 1674:Src/main.c **** TIM_OC_InitTypeDef sConfigOC = {0}; 10694 .loc 1 1674 3 is_stmt 1 view .LVU3306 1674:Src/main.c **** TIM_OC_InitTypeDef sConfigOC = {0}; 10695 .loc 1 1674 27 is_stmt 0 view .LVU3307 10696 000e 0793 str r3, [sp, #28] 10697 0010 0893 str r3, [sp, #32] 10698 0012 0993 str r3, [sp, #36] 1675:Src/main.c **** 10699 .loc 1 1675 3 is_stmt 1 view .LVU3308 1675:Src/main.c **** 10700 .loc 1 1675 22 is_stmt 0 view .LVU3309 10701 0014 0093 str r3, [sp] 10702 0016 0193 str r3, [sp, #4] 10703 0018 0293 str r3, [sp, #8] 10704 001a 0393 str r3, [sp, #12] 10705 001c 0493 str r3, [sp, #16] ARM GAS /tmp/ccLSPxIe.s page 598 10706 001e 0593 str r3, [sp, #20] 10707 0020 0693 str r3, [sp, #24] 1680:Src/main.c **** htim4.Init.Prescaler = 0; 10708 .loc 1 1680 3 is_stmt 1 view .LVU3310 1680:Src/main.c **** htim4.Init.Prescaler = 0; 10709 .loc 1 1680 18 is_stmt 0 view .LVU3311 10710 0022 1E48 ldr r0, .L620 10711 0024 1E4A ldr r2, .L620+4 10712 0026 0260 str r2, [r0] 1681:Src/main.c **** htim4.Init.CounterMode = TIM_COUNTERMODE_UP; 10713 .loc 1 1681 3 is_stmt 1 view .LVU3312 1681:Src/main.c **** htim4.Init.CounterMode = TIM_COUNTERMODE_UP; 10714 .loc 1 1681 24 is_stmt 0 view .LVU3313 10715 0028 4360 str r3, [r0, #4] 1682:Src/main.c **** htim4.Init.Period = 45; 10716 .loc 1 1682 3 is_stmt 1 view .LVU3314 1682:Src/main.c **** htim4.Init.Period = 45; 10717 .loc 1 1682 26 is_stmt 0 view .LVU3315 10718 002a 8360 str r3, [r0, #8] 1683:Src/main.c **** htim4.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; 10719 .loc 1 1683 3 is_stmt 1 view .LVU3316 1683:Src/main.c **** htim4.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; 10720 .loc 1 1683 21 is_stmt 0 view .LVU3317 10721 002c 2D22 movs r2, #45 10722 002e C260 str r2, [r0, #12] 1684:Src/main.c **** htim4.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; 10723 .loc 1 1684 3 is_stmt 1 view .LVU3318 1684:Src/main.c **** htim4.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; 10724 .loc 1 1684 28 is_stmt 0 view .LVU3319 10725 0030 0361 str r3, [r0, #16] 1685:Src/main.c **** if (HAL_TIM_Base_Init(&htim4) != HAL_OK) 10726 .loc 1 1685 3 is_stmt 1 view .LVU3320 1685:Src/main.c **** if (HAL_TIM_Base_Init(&htim4) != HAL_OK) 10727 .loc 1 1685 32 is_stmt 0 view .LVU3321 10728 0032 8361 str r3, [r0, #24] 1686:Src/main.c **** { 10729 .loc 1 1686 3 is_stmt 1 view .LVU3322 1686:Src/main.c **** { 10730 .loc 1 1686 7 is_stmt 0 view .LVU3323 10731 0034 FFF7FEFF bl HAL_TIM_Base_Init 10732 .LVL956: 1686:Src/main.c **** { 10733 .loc 1 1686 6 discriminator 1 view .LVU3324 10734 0038 30BB cbnz r0, .L615 1690:Src/main.c **** if (HAL_TIM_ConfigClockSource(&htim4, &sClockSourceConfig) != HAL_OK) 10735 .loc 1 1690 3 is_stmt 1 view .LVU3325 1690:Src/main.c **** if (HAL_TIM_ConfigClockSource(&htim4, &sClockSourceConfig) != HAL_OK) 10736 .loc 1 1690 34 is_stmt 0 view .LVU3326 10737 003a 4FF48053 mov r3, #4096 10738 003e 0A93 str r3, [sp, #40] 1691:Src/main.c **** { 10739 .loc 1 1691 3 is_stmt 1 view .LVU3327 1691:Src/main.c **** { 10740 .loc 1 1691 7 is_stmt 0 view .LVU3328 10741 0040 0AA9 add r1, sp, #40 10742 0042 1648 ldr r0, .L620 10743 0044 FFF7FEFF bl HAL_TIM_ConfigClockSource ARM GAS /tmp/ccLSPxIe.s page 599 10744 .LVL957: 1691:Src/main.c **** { 10745 .loc 1 1691 6 discriminator 1 view .LVU3329 10746 0048 00BB cbnz r0, .L616 1695:Src/main.c **** { 10747 .loc 1 1695 3 is_stmt 1 view .LVU3330 1695:Src/main.c **** { 10748 .loc 1 1695 7 is_stmt 0 view .LVU3331 10749 004a 1448 ldr r0, .L620 10750 004c FFF7FEFF bl HAL_TIM_PWM_Init 10751 .LVL958: 1695:Src/main.c **** { 10752 .loc 1 1695 6 discriminator 1 view .LVU3332 10753 0050 F0B9 cbnz r0, .L617 1699:Src/main.c **** sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; 10754 .loc 1 1699 3 is_stmt 1 view .LVU3333 1699:Src/main.c **** sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; 10755 .loc 1 1699 37 is_stmt 0 view .LVU3334 10756 0052 0023 movs r3, #0 10757 0054 0793 str r3, [sp, #28] 1700:Src/main.c **** if (HAL_TIMEx_MasterConfigSynchronization(&htim4, &sMasterConfig) != HAL_OK) 10758 .loc 1 1700 3 is_stmt 1 view .LVU3335 1700:Src/main.c **** if (HAL_TIMEx_MasterConfigSynchronization(&htim4, &sMasterConfig) != HAL_OK) 10759 .loc 1 1700 33 is_stmt 0 view .LVU3336 10760 0056 0993 str r3, [sp, #36] 1701:Src/main.c **** { 10761 .loc 1 1701 3 is_stmt 1 view .LVU3337 1701:Src/main.c **** { 10762 .loc 1 1701 7 is_stmt 0 view .LVU3338 10763 0058 07A9 add r1, sp, #28 10764 005a 1048 ldr r0, .L620 10765 005c FFF7FEFF bl HAL_TIMEx_MasterConfigSynchronization 10766 .LVL959: 1701:Src/main.c **** { 10767 .loc 1 1701 6 discriminator 1 view .LVU3339 10768 0060 C0B9 cbnz r0, .L618 1705:Src/main.c **** sConfigOC.Pulse = 22; 10769 .loc 1 1705 3 is_stmt 1 view .LVU3340 1705:Src/main.c **** sConfigOC.Pulse = 22; 10770 .loc 1 1705 20 is_stmt 0 view .LVU3341 10771 0062 6023 movs r3, #96 10772 0064 0093 str r3, [sp] 1706:Src/main.c **** sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH; 10773 .loc 1 1706 3 is_stmt 1 view .LVU3342 1706:Src/main.c **** sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH; 10774 .loc 1 1706 19 is_stmt 0 view .LVU3343 10775 0066 1623 movs r3, #22 10776 0068 0193 str r3, [sp, #4] 1707:Src/main.c **** sConfigOC.OCFastMode = TIM_OCFAST_DISABLE; 10777 .loc 1 1707 3 is_stmt 1 view .LVU3344 1707:Src/main.c **** sConfigOC.OCFastMode = TIM_OCFAST_DISABLE; 10778 .loc 1 1707 24 is_stmt 0 view .LVU3345 10779 006a 0023 movs r3, #0 10780 006c 0293 str r3, [sp, #8] 1708:Src/main.c **** if (HAL_TIM_PWM_ConfigChannel(&htim4, &sConfigOC, TIM_CHANNEL_3) != HAL_OK) 10781 .loc 1 1708 3 is_stmt 1 view .LVU3346 1708:Src/main.c **** if (HAL_TIM_PWM_ConfigChannel(&htim4, &sConfigOC, TIM_CHANNEL_3) != HAL_OK) ARM GAS /tmp/ccLSPxIe.s page 600 10782 .loc 1 1708 24 is_stmt 0 view .LVU3347 10783 006e 0493 str r3, [sp, #16] 1709:Src/main.c **** { 10784 .loc 1 1709 3 is_stmt 1 view .LVU3348 1709:Src/main.c **** { 10785 .loc 1 1709 7 is_stmt 0 view .LVU3349 10786 0070 0822 movs r2, #8 10787 0072 6946 mov r1, sp 10788 0074 0948 ldr r0, .L620 10789 0076 FFF7FEFF bl HAL_TIM_PWM_ConfigChannel 10790 .LVL960: 1709:Src/main.c **** { 10791 .loc 1 1709 6 discriminator 1 view .LVU3350 10792 007a 68B9 cbnz r0, .L619 1716:Src/main.c **** 10793 .loc 1 1716 3 is_stmt 1 view .LVU3351 10794 007c 0748 ldr r0, .L620 10795 007e FFF7FEFF bl HAL_TIM_MspPostInit 10796 .LVL961: 1718:Src/main.c **** 10797 .loc 1 1718 1 is_stmt 0 view .LVU3352 10798 0082 0FB0 add sp, sp, #60 10799 .LCFI106: 10800 .cfi_remember_state 10801 .cfi_def_cfa_offset 4 10802 @ sp needed 10803 0084 5DF804FB ldr pc, [sp], #4 10804 .L615: 10805 .LCFI107: 10806 .cfi_restore_state 1688:Src/main.c **** } 10807 .loc 1 1688 5 is_stmt 1 view .LVU3353 10808 0088 FFF7FEFF bl Error_Handler 10809 .LVL962: 10810 .L616: 1693:Src/main.c **** } 10811 .loc 1 1693 5 view .LVU3354 10812 008c FFF7FEFF bl Error_Handler 10813 .LVL963: 10814 .L617: 1697:Src/main.c **** } 10815 .loc 1 1697 5 view .LVU3355 10816 0090 FFF7FEFF bl Error_Handler 10817 .LVL964: 10818 .L618: 1703:Src/main.c **** } 10819 .loc 1 1703 5 view .LVU3356 10820 0094 FFF7FEFF bl Error_Handler 10821 .LVL965: 10822 .L619: 1711:Src/main.c **** } 10823 .loc 1 1711 5 view .LVU3357 10824 0098 FFF7FEFF bl Error_Handler 10825 .LVL966: 10826 .L621: 10827 .align 2 10828 .L620: ARM GAS /tmp/ccLSPxIe.s page 601 10829 009c 00000000 .word htim4 10830 00a0 00080040 .word 1073743872 10831 .cfi_endproc 10832 .LFE1196: 10834 .section .text.MX_TIM1_Init,"ax",%progbits 10835 .align 1 10836 .syntax unified 10837 .thumb 10838 .thumb_func 10840 MX_TIM1_Init: 10841 .LFB1203: 1963:Src/main.c **** 10842 .loc 1 1963 1 view -0 10843 .cfi_startproc 10844 @ args = 0, pretend = 0, frame = 88 10845 @ frame_needed = 0, uses_anonymous_args = 0 10846 0000 10B5 push {r4, lr} 10847 .LCFI108: 10848 .cfi_def_cfa_offset 8 10849 .cfi_offset 4, -8 10850 .cfi_offset 14, -4 10851 0002 96B0 sub sp, sp, #88 10852 .LCFI109: 10853 .cfi_def_cfa_offset 96 1969:Src/main.c **** TIM_OC_InitTypeDef sConfigOC = {0}; 10854 .loc 1 1969 3 view .LVU3359 1969:Src/main.c **** TIM_OC_InitTypeDef sConfigOC = {0}; 10855 .loc 1 1969 26 is_stmt 0 view .LVU3360 10856 0004 0024 movs r4, #0 10857 0006 1294 str r4, [sp, #72] 10858 0008 1394 str r4, [sp, #76] 10859 000a 1494 str r4, [sp, #80] 10860 000c 1594 str r4, [sp, #84] 1970:Src/main.c **** TIM_BreakDeadTimeConfigTypeDef sBreakDeadTimeConfig = {0}; 10861 .loc 1 1970 3 is_stmt 1 view .LVU3361 1970:Src/main.c **** TIM_BreakDeadTimeConfigTypeDef sBreakDeadTimeConfig = {0}; 10862 .loc 1 1970 22 is_stmt 0 view .LVU3362 10863 000e 0B94 str r4, [sp, #44] 10864 0010 0C94 str r4, [sp, #48] 10865 0012 0D94 str r4, [sp, #52] 10866 0014 0E94 str r4, [sp, #56] 10867 0016 0F94 str r4, [sp, #60] 10868 0018 1094 str r4, [sp, #64] 10869 001a 1194 str r4, [sp, #68] 1971:Src/main.c **** 10870 .loc 1 1971 3 is_stmt 1 view .LVU3363 1971:Src/main.c **** 10871 .loc 1 1971 34 is_stmt 0 view .LVU3364 10872 001c 2C22 movs r2, #44 10873 001e 2146 mov r1, r4 10874 0020 6846 mov r0, sp 10875 0022 FFF7FEFF bl memset 10876 .LVL967: 1976:Src/main.c **** htim1.Init.Prescaler = 0; 10877 .loc 1 1976 3 is_stmt 1 view .LVU3365 1976:Src/main.c **** htim1.Init.Prescaler = 0; 10878 .loc 1 1976 18 is_stmt 0 view .LVU3366 ARM GAS /tmp/ccLSPxIe.s page 602 10879 0026 2548 ldr r0, .L634 10880 0028 254B ldr r3, .L634+4 10881 002a 0360 str r3, [r0] 1977:Src/main.c **** htim1.Init.CounterMode = TIM_COUNTERMODE_UP; 10882 .loc 1 1977 3 is_stmt 1 view .LVU3367 1977:Src/main.c **** htim1.Init.CounterMode = TIM_COUNTERMODE_UP; 10883 .loc 1 1977 24 is_stmt 0 view .LVU3368 10884 002c 4460 str r4, [r0, #4] 1978:Src/main.c **** htim1.Init.Period = 8; 10885 .loc 1 1978 3 is_stmt 1 view .LVU3369 1978:Src/main.c **** htim1.Init.Period = 8; 10886 .loc 1 1978 26 is_stmt 0 view .LVU3370 10887 002e 8460 str r4, [r0, #8] 1979:Src/main.c **** htim1.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; 10888 .loc 1 1979 3 is_stmt 1 view .LVU3371 1979:Src/main.c **** htim1.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; 10889 .loc 1 1979 21 is_stmt 0 view .LVU3372 10890 0030 0823 movs r3, #8 10891 0032 C360 str r3, [r0, #12] 1980:Src/main.c **** htim1.Init.RepetitionCounter = 0; 10892 .loc 1 1980 3 is_stmt 1 view .LVU3373 1980:Src/main.c **** htim1.Init.RepetitionCounter = 0; 10893 .loc 1 1980 28 is_stmt 0 view .LVU3374 10894 0034 0461 str r4, [r0, #16] 1981:Src/main.c **** htim1.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; 10895 .loc 1 1981 3 is_stmt 1 view .LVU3375 1981:Src/main.c **** htim1.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; 10896 .loc 1 1981 32 is_stmt 0 view .LVU3376 10897 0036 4461 str r4, [r0, #20] 1982:Src/main.c **** if (HAL_TIM_Base_Init(&htim1) != HAL_OK) 10898 .loc 1 1982 3 is_stmt 1 view .LVU3377 1982:Src/main.c **** if (HAL_TIM_Base_Init(&htim1) != HAL_OK) 10899 .loc 1 1982 32 is_stmt 0 view .LVU3378 10900 0038 8461 str r4, [r0, #24] 1983:Src/main.c **** { 10901 .loc 1 1983 3 is_stmt 1 view .LVU3379 1983:Src/main.c **** { 10902 .loc 1 1983 7 is_stmt 0 view .LVU3380 10903 003a FFF7FEFF bl HAL_TIM_Base_Init 10904 .LVL968: 1983:Src/main.c **** { 10905 .loc 1 1983 6 discriminator 1 view .LVU3381 10906 003e 0028 cmp r0, #0 10907 0040 32D1 bne .L629 1987:Src/main.c **** if (HAL_TIM_ConfigClockSource(&htim1, &sClockSourceConfig) != HAL_OK) 10908 .loc 1 1987 3 is_stmt 1 view .LVU3382 1987:Src/main.c **** if (HAL_TIM_ConfigClockSource(&htim1, &sClockSourceConfig) != HAL_OK) 10909 .loc 1 1987 34 is_stmt 0 view .LVU3383 10910 0042 4FF48053 mov r3, #4096 10911 0046 1293 str r3, [sp, #72] 1988:Src/main.c **** { 10912 .loc 1 1988 3 is_stmt 1 view .LVU3384 1988:Src/main.c **** { 10913 .loc 1 1988 7 is_stmt 0 view .LVU3385 10914 0048 12A9 add r1, sp, #72 10915 004a 1C48 ldr r0, .L634 10916 004c FFF7FEFF bl HAL_TIM_ConfigClockSource ARM GAS /tmp/ccLSPxIe.s page 603 10917 .LVL969: 1988:Src/main.c **** { 10918 .loc 1 1988 6 discriminator 1 view .LVU3386 10919 0050 0028 cmp r0, #0 10920 0052 2BD1 bne .L630 1992:Src/main.c **** { 10921 .loc 1 1992 3 is_stmt 1 view .LVU3387 1992:Src/main.c **** { 10922 .loc 1 1992 7 is_stmt 0 view .LVU3388 10923 0054 1948 ldr r0, .L634 10924 0056 FFF7FEFF bl HAL_TIM_PWM_Init 10925 .LVL970: 1992:Src/main.c **** { 10926 .loc 1 1992 6 discriminator 1 view .LVU3389 10927 005a 48BB cbnz r0, .L631 1996:Src/main.c **** sConfigOC.Pulse = 4; 10928 .loc 1 1996 3 is_stmt 1 view .LVU3390 1996:Src/main.c **** sConfigOC.Pulse = 4; 10929 .loc 1 1996 20 is_stmt 0 view .LVU3391 10930 005c 6023 movs r3, #96 10931 005e 0B93 str r3, [sp, #44] 1997:Src/main.c **** sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH; 10932 .loc 1 1997 3 is_stmt 1 view .LVU3392 1997:Src/main.c **** sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH; 10933 .loc 1 1997 19 is_stmt 0 view .LVU3393 10934 0060 0423 movs r3, #4 10935 0062 0C93 str r3, [sp, #48] 1998:Src/main.c **** sConfigOC.OCFastMode = TIM_OCFAST_DISABLE; 10936 .loc 1 1998 3 is_stmt 1 view .LVU3394 1998:Src/main.c **** sConfigOC.OCFastMode = TIM_OCFAST_DISABLE; 10937 .loc 1 1998 24 is_stmt 0 view .LVU3395 10938 0064 0022 movs r2, #0 10939 0066 0D92 str r2, [sp, #52] 1999:Src/main.c **** if (HAL_TIM_PWM_ConfigChannel(&htim1, &sConfigOC, TIM_CHANNEL_1) != HAL_OK) 10940 .loc 1 1999 3 is_stmt 1 view .LVU3396 1999:Src/main.c **** if (HAL_TIM_PWM_ConfigChannel(&htim1, &sConfigOC, TIM_CHANNEL_1) != HAL_OK) 10941 .loc 1 1999 24 is_stmt 0 view .LVU3397 10942 0068 0F92 str r2, [sp, #60] 2000:Src/main.c **** { 10943 .loc 1 2000 3 is_stmt 1 view .LVU3398 2000:Src/main.c **** { 10944 .loc 1 2000 7 is_stmt 0 view .LVU3399 10945 006a 0BA9 add r1, sp, #44 10946 006c 1348 ldr r0, .L634 10947 006e FFF7FEFF bl HAL_TIM_PWM_ConfigChannel 10948 .LVL971: 2000:Src/main.c **** { 10949 .loc 1 2000 6 discriminator 1 view .LVU3400 10950 0072 F8B9 cbnz r0, .L632 2004:Src/main.c **** sBreakDeadTimeConfig.OffStateIDLEMode = TIM_OSSI_DISABLE; 10951 .loc 1 2004 3 is_stmt 1 view .LVU3401 2004:Src/main.c **** sBreakDeadTimeConfig.OffStateIDLEMode = TIM_OSSI_DISABLE; 10952 .loc 1 2004 40 is_stmt 0 view .LVU3402 10953 0074 0023 movs r3, #0 10954 0076 0093 str r3, [sp] 2005:Src/main.c **** sBreakDeadTimeConfig.LockLevel = TIM_LOCKLEVEL_OFF; 10955 .loc 1 2005 3 is_stmt 1 view .LVU3403 ARM GAS /tmp/ccLSPxIe.s page 604 2005:Src/main.c **** sBreakDeadTimeConfig.LockLevel = TIM_LOCKLEVEL_OFF; 10956 .loc 1 2005 41 is_stmt 0 view .LVU3404 10957 0078 0193 str r3, [sp, #4] 2006:Src/main.c **** sBreakDeadTimeConfig.DeadTime = 0; 10958 .loc 1 2006 3 is_stmt 1 view .LVU3405 2006:Src/main.c **** sBreakDeadTimeConfig.DeadTime = 0; 10959 .loc 1 2006 34 is_stmt 0 view .LVU3406 10960 007a 0293 str r3, [sp, #8] 2007:Src/main.c **** sBreakDeadTimeConfig.BreakState = TIM_BREAK_DISABLE; 10961 .loc 1 2007 3 is_stmt 1 view .LVU3407 2007:Src/main.c **** sBreakDeadTimeConfig.BreakState = TIM_BREAK_DISABLE; 10962 .loc 1 2007 33 is_stmt 0 view .LVU3408 10963 007c 0393 str r3, [sp, #12] 2008:Src/main.c **** sBreakDeadTimeConfig.BreakPolarity = TIM_BREAKPOLARITY_HIGH; 10964 .loc 1 2008 3 is_stmt 1 view .LVU3409 2008:Src/main.c **** sBreakDeadTimeConfig.BreakPolarity = TIM_BREAKPOLARITY_HIGH; 10965 .loc 1 2008 35 is_stmt 0 view .LVU3410 10966 007e 0493 str r3, [sp, #16] 2009:Src/main.c **** sBreakDeadTimeConfig.BreakFilter = 0; 10967 .loc 1 2009 3 is_stmt 1 view .LVU3411 2009:Src/main.c **** sBreakDeadTimeConfig.BreakFilter = 0; 10968 .loc 1 2009 38 is_stmt 0 view .LVU3412 10969 0080 4FF40052 mov r2, #8192 10970 0084 0592 str r2, [sp, #20] 2010:Src/main.c **** sBreakDeadTimeConfig.Break2State = TIM_BREAK2_DISABLE; 10971 .loc 1 2010 3 is_stmt 1 view .LVU3413 2010:Src/main.c **** sBreakDeadTimeConfig.Break2State = TIM_BREAK2_DISABLE; 10972 .loc 1 2010 36 is_stmt 0 view .LVU3414 10973 0086 0693 str r3, [sp, #24] 2011:Src/main.c **** sBreakDeadTimeConfig.Break2Polarity = TIM_BREAK2POLARITY_HIGH; 10974 .loc 1 2011 3 is_stmt 1 view .LVU3415 2011:Src/main.c **** sBreakDeadTimeConfig.Break2Polarity = TIM_BREAK2POLARITY_HIGH; 10975 .loc 1 2011 36 is_stmt 0 view .LVU3416 10976 0088 0793 str r3, [sp, #28] 2012:Src/main.c **** sBreakDeadTimeConfig.Break2Filter = 0; 10977 .loc 1 2012 3 is_stmt 1 view .LVU3417 2012:Src/main.c **** sBreakDeadTimeConfig.Break2Filter = 0; 10978 .loc 1 2012 39 is_stmt 0 view .LVU3418 10979 008a 4FF00072 mov r2, #33554432 10980 008e 0892 str r2, [sp, #32] 2013:Src/main.c **** sBreakDeadTimeConfig.AutomaticOutput = TIM_AUTOMATICOUTPUT_DISABLE; 10981 .loc 1 2013 3 is_stmt 1 view .LVU3419 2013:Src/main.c **** sBreakDeadTimeConfig.AutomaticOutput = TIM_AUTOMATICOUTPUT_DISABLE; 10982 .loc 1 2013 37 is_stmt 0 view .LVU3420 10983 0090 0993 str r3, [sp, #36] 2014:Src/main.c **** if (HAL_TIMEx_ConfigBreakDeadTime(&htim1, &sBreakDeadTimeConfig) != HAL_OK) 10984 .loc 1 2014 3 is_stmt 1 view .LVU3421 2014:Src/main.c **** if (HAL_TIMEx_ConfigBreakDeadTime(&htim1, &sBreakDeadTimeConfig) != HAL_OK) 10985 .loc 1 2014 40 is_stmt 0 view .LVU3422 10986 0092 0A93 str r3, [sp, #40] 2015:Src/main.c **** { 10987 .loc 1 2015 3 is_stmt 1 view .LVU3423 2015:Src/main.c **** { 10988 .loc 1 2015 7 is_stmt 0 view .LVU3424 10989 0094 6946 mov r1, sp 10990 0096 0948 ldr r0, .L634 10991 0098 FFF7FEFF bl HAL_TIMEx_ConfigBreakDeadTime ARM GAS /tmp/ccLSPxIe.s page 605 10992 .LVL972: 2015:Src/main.c **** { 10993 .loc 1 2015 6 discriminator 1 view .LVU3425 10994 009c 60B9 cbnz r0, .L633 2022:Src/main.c **** 10995 .loc 1 2022 3 is_stmt 1 view .LVU3426 10996 009e 0748 ldr r0, .L634 10997 00a0 FFF7FEFF bl HAL_TIM_MspPostInit 10998 .LVL973: 2024:Src/main.c **** 10999 .loc 1 2024 1 is_stmt 0 view .LVU3427 11000 00a4 16B0 add sp, sp, #88 11001 .LCFI110: 11002 .cfi_remember_state 11003 .cfi_def_cfa_offset 8 11004 @ sp needed 11005 00a6 10BD pop {r4, pc} 11006 .L629: 11007 .LCFI111: 11008 .cfi_restore_state 1985:Src/main.c **** } 11009 .loc 1 1985 5 is_stmt 1 view .LVU3428 11010 00a8 FFF7FEFF bl Error_Handler 11011 .LVL974: 11012 .L630: 1990:Src/main.c **** } 11013 .loc 1 1990 5 view .LVU3429 11014 00ac FFF7FEFF bl Error_Handler 11015 .LVL975: 11016 .L631: 1994:Src/main.c **** } 11017 .loc 1 1994 5 view .LVU3430 11018 00b0 FFF7FEFF bl Error_Handler 11019 .LVL976: 11020 .L632: 2002:Src/main.c **** } 11021 .loc 1 2002 5 view .LVU3431 11022 00b4 FFF7FEFF bl Error_Handler 11023 .LVL977: 11024 .L633: 2017:Src/main.c **** } 11025 .loc 1 2017 5 view .LVU3432 11026 00b8 FFF7FEFF bl Error_Handler 11027 .LVL978: 11028 .L635: 11029 .align 2 11030 .L634: 11031 00bc 00000000 .word htim1 11032 00c0 00000140 .word 1073807360 11033 .cfi_endproc 11034 .LFE1203: 11036 .section .text.SystemClock_Config,"ax",%progbits 11037 .align 1 11038 .global SystemClock_Config 11039 .syntax unified 11040 .thumb 11041 .thumb_func ARM GAS /tmp/ccLSPxIe.s page 606 11043 SystemClock_Config: 11044 .LFB1187: 1145:Src/main.c **** RCC_OscInitTypeDef RCC_OscInitStruct = {0}; 11045 .loc 1 1145 1 view -0 11046 .cfi_startproc 11047 @ args = 0, pretend = 0, frame = 80 11048 @ frame_needed = 0, uses_anonymous_args = 0 11049 0000 00B5 push {lr} 11050 .LCFI112: 11051 .cfi_def_cfa_offset 4 11052 .cfi_offset 14, -4 11053 0002 95B0 sub sp, sp, #84 11054 .LCFI113: 11055 .cfi_def_cfa_offset 88 1146:Src/main.c **** RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; 11056 .loc 1 1146 3 view .LVU3434 1146:Src/main.c **** RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; 11057 .loc 1 1146 22 is_stmt 0 view .LVU3435 11058 0004 3422 movs r2, #52 11059 0006 0021 movs r1, #0 11060 0008 07A8 add r0, sp, #28 11061 000a FFF7FEFF bl memset 11062 .LVL979: 1147:Src/main.c **** 11063 .loc 1 1147 3 is_stmt 1 view .LVU3436 1147:Src/main.c **** 11064 .loc 1 1147 22 is_stmt 0 view .LVU3437 11065 000e 0023 movs r3, #0 11066 0010 0293 str r3, [sp, #8] 11067 0012 0393 str r3, [sp, #12] 11068 0014 0493 str r3, [sp, #16] 11069 0016 0593 str r3, [sp, #20] 11070 0018 0693 str r3, [sp, #24] 1151:Src/main.c **** __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); 11071 .loc 1 1151 3 is_stmt 1 view .LVU3438 11072 .LBB679: 1151:Src/main.c **** __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); 11073 .loc 1 1151 3 view .LVU3439 1151:Src/main.c **** __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); 11074 .loc 1 1151 3 view .LVU3440 11075 001a 244B ldr r3, .L644 11076 001c 1A6C ldr r2, [r3, #64] 11077 001e 42F08052 orr r2, r2, #268435456 11078 0022 1A64 str r2, [r3, #64] 1151:Src/main.c **** __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); 11079 .loc 1 1151 3 view .LVU3441 11080 0024 1B6C ldr r3, [r3, #64] 11081 0026 03F08053 and r3, r3, #268435456 11082 002a 0093 str r3, [sp] 1151:Src/main.c **** __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); 11083 .loc 1 1151 3 view .LVU3442 11084 002c 009B ldr r3, [sp] 11085 .LBE679: 1151:Src/main.c **** __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); 11086 .loc 1 1151 3 view .LVU3443 1152:Src/main.c **** 11087 .loc 1 1152 3 view .LVU3444 ARM GAS /tmp/ccLSPxIe.s page 607 11088 .LBB680: 1152:Src/main.c **** 11089 .loc 1 1152 3 view .LVU3445 1152:Src/main.c **** 11090 .loc 1 1152 3 view .LVU3446 11091 002e 204B ldr r3, .L644+4 11092 0030 1A68 ldr r2, [r3] 11093 0032 42F44042 orr r2, r2, #49152 11094 0036 1A60 str r2, [r3] 1152:Src/main.c **** 11095 .loc 1 1152 3 view .LVU3447 11096 0038 1B68 ldr r3, [r3] 11097 003a 03F44043 and r3, r3, #49152 11098 003e 0193 str r3, [sp, #4] 1152:Src/main.c **** 11099 .loc 1 1152 3 view .LVU3448 11100 0040 019B ldr r3, [sp, #4] 11101 .LBE680: 1152:Src/main.c **** 11102 .loc 1 1152 3 view .LVU3449 1157:Src/main.c **** RCC_OscInitStruct.HSEState = RCC_HSE_ON; 11103 .loc 1 1157 3 view .LVU3450 1157:Src/main.c **** RCC_OscInitStruct.HSEState = RCC_HSE_ON; 11104 .loc 1 1157 36 is_stmt 0 view .LVU3451 11105 0042 0123 movs r3, #1 11106 0044 0793 str r3, [sp, #28] 1158:Src/main.c **** RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; 11107 .loc 1 1158 3 is_stmt 1 view .LVU3452 1158:Src/main.c **** RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; 11108 .loc 1 1158 30 is_stmt 0 view .LVU3453 11109 0046 4FF48033 mov r3, #65536 11110 004a 0893 str r3, [sp, #32] 1159:Src/main.c **** RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; 11111 .loc 1 1159 3 is_stmt 1 view .LVU3454 1159:Src/main.c **** RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; 11112 .loc 1 1159 34 is_stmt 0 view .LVU3455 11113 004c 0223 movs r3, #2 11114 004e 0D93 str r3, [sp, #52] 1160:Src/main.c **** RCC_OscInitStruct.PLL.PLLM = 25; 11115 .loc 1 1160 3 is_stmt 1 view .LVU3456 1160:Src/main.c **** RCC_OscInitStruct.PLL.PLLM = 25; 11116 .loc 1 1160 35 is_stmt 0 view .LVU3457 11117 0050 4FF48002 mov r2, #4194304 11118 0054 0E92 str r2, [sp, #56] 1161:Src/main.c **** RCC_OscInitStruct.PLL.PLLN = 368; 11119 .loc 1 1161 3 is_stmt 1 view .LVU3458 1161:Src/main.c **** RCC_OscInitStruct.PLL.PLLN = 368; 11120 .loc 1 1161 30 is_stmt 0 view .LVU3459 11121 0056 1922 movs r2, #25 11122 0058 0F92 str r2, [sp, #60] 1162:Src/main.c **** RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; 11123 .loc 1 1162 3 is_stmt 1 view .LVU3460 1162:Src/main.c **** RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; 11124 .loc 1 1162 30 is_stmt 0 view .LVU3461 11125 005a 4FF4B872 mov r2, #368 11126 005e 1092 str r2, [sp, #64] 1163:Src/main.c **** RCC_OscInitStruct.PLL.PLLQ = 8; ARM GAS /tmp/ccLSPxIe.s page 608 11127 .loc 1 1163 3 is_stmt 1 view .LVU3462 1163:Src/main.c **** RCC_OscInitStruct.PLL.PLLQ = 8; 11128 .loc 1 1163 30 is_stmt 0 view .LVU3463 11129 0060 1193 str r3, [sp, #68] 1164:Src/main.c **** RCC_OscInitStruct.PLL.PLLR = 2; 11130 .loc 1 1164 3 is_stmt 1 view .LVU3464 1164:Src/main.c **** RCC_OscInitStruct.PLL.PLLR = 2; 11131 .loc 1 1164 30 is_stmt 0 view .LVU3465 11132 0062 0822 movs r2, #8 11133 0064 1292 str r2, [sp, #72] 1165:Src/main.c **** if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) 11134 .loc 1 1165 3 is_stmt 1 view .LVU3466 1165:Src/main.c **** if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) 11135 .loc 1 1165 30 is_stmt 0 view .LVU3467 11136 0066 1393 str r3, [sp, #76] 1166:Src/main.c **** { 11137 .loc 1 1166 3 is_stmt 1 view .LVU3468 1166:Src/main.c **** { 11138 .loc 1 1166 7 is_stmt 0 view .LVU3469 11139 0068 07A8 add r0, sp, #28 11140 006a FFF7FEFF bl HAL_RCC_OscConfig 11141 .LVL980: 1166:Src/main.c **** { 11142 .loc 1 1166 6 discriminator 1 view .LVU3470 11143 006e B0B9 cbnz r0, .L641 1173:Src/main.c **** { 11144 .loc 1 1173 3 is_stmt 1 view .LVU3471 1173:Src/main.c **** { 11145 .loc 1 1173 7 is_stmt 0 view .LVU3472 11146 0070 FFF7FEFF bl HAL_PWREx_EnableOverDrive 11147 .LVL981: 1173:Src/main.c **** { 11148 .loc 1 1173 6 discriminator 1 view .LVU3473 11149 0074 A8B9 cbnz r0, .L642 1180:Src/main.c **** |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; 11150 .loc 1 1180 3 is_stmt 1 view .LVU3474 1180:Src/main.c **** |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; 11151 .loc 1 1180 31 is_stmt 0 view .LVU3475 11152 0076 0F23 movs r3, #15 11153 0078 0293 str r3, [sp, #8] 1182:Src/main.c **** RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; 11154 .loc 1 1182 3 is_stmt 1 view .LVU3476 1182:Src/main.c **** RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; 11155 .loc 1 1182 34 is_stmt 0 view .LVU3477 11156 007a 0223 movs r3, #2 11157 007c 0393 str r3, [sp, #12] 1183:Src/main.c **** RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4; 11158 .loc 1 1183 3 is_stmt 1 view .LVU3478 1183:Src/main.c **** RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4; 11159 .loc 1 1183 35 is_stmt 0 view .LVU3479 11160 007e 0023 movs r3, #0 11161 0080 0493 str r3, [sp, #16] 1184:Src/main.c **** RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; 11162 .loc 1 1184 3 is_stmt 1 view .LVU3480 1184:Src/main.c **** RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; 11163 .loc 1 1184 36 is_stmt 0 view .LVU3481 11164 0082 4FF4A053 mov r3, #5120 ARM GAS /tmp/ccLSPxIe.s page 609 11165 0086 0593 str r3, [sp, #20] 1185:Src/main.c **** 11166 .loc 1 1185 3 is_stmt 1 view .LVU3482 1185:Src/main.c **** 11167 .loc 1 1185 36 is_stmt 0 view .LVU3483 11168 0088 4FF48053 mov r3, #4096 11169 008c 0693 str r3, [sp, #24] 1187:Src/main.c **** { 11170 .loc 1 1187 3 is_stmt 1 view .LVU3484 1187:Src/main.c **** { 11171 .loc 1 1187 7 is_stmt 0 view .LVU3485 11172 008e 0621 movs r1, #6 11173 0090 02A8 add r0, sp, #8 11174 0092 FFF7FEFF bl HAL_RCC_ClockConfig 11175 .LVL982: 1187:Src/main.c **** { 11176 .loc 1 1187 6 discriminator 1 view .LVU3486 11177 0096 30B9 cbnz r0, .L643 1191:Src/main.c **** 11178 .loc 1 1191 1 view .LVU3487 11179 0098 15B0 add sp, sp, #84 11180 .LCFI114: 11181 .cfi_remember_state 11182 .cfi_def_cfa_offset 4 11183 @ sp needed 11184 009a 5DF804FB ldr pc, [sp], #4 11185 .L641: 11186 .LCFI115: 11187 .cfi_restore_state 1168:Src/main.c **** } 11188 .loc 1 1168 5 is_stmt 1 view .LVU3488 11189 009e FFF7FEFF bl Error_Handler 11190 .LVL983: 11191 .L642: 1175:Src/main.c **** } 11192 .loc 1 1175 5 view .LVU3489 11193 00a2 FFF7FEFF bl Error_Handler 11194 .LVL984: 11195 .L643: 1189:Src/main.c **** } 11196 .loc 1 1189 5 view .LVU3490 11197 00a6 FFF7FEFF bl Error_Handler 11198 .LVL985: 11199 .L645: 11200 00aa 00BF .align 2 11201 .L644: 11202 00ac 00380240 .word 1073887232 11203 00b0 00700040 .word 1073770496 11204 .cfi_endproc 11205 .LFE1187: 11207 .section .text.main,"ax",%progbits 11208 .align 1 11209 .global main 11210 .syntax unified 11211 .thumb 11212 .thumb_func 11214 main: ARM GAS /tmp/ccLSPxIe.s page 610 11215 .LFB1186: 270:Src/main.c **** 11216 .loc 1 270 1 view -0 11217 .cfi_startproc 11218 @ args = 0, pretend = 0, frame = 16 11219 @ frame_needed = 0, uses_anonymous_args = 0 11220 0000 2DE9F043 push {r4, r5, r6, r7, r8, r9, lr} 11221 .LCFI116: 11222 .cfi_def_cfa_offset 28 11223 .cfi_offset 4, -28 11224 .cfi_offset 5, -24 11225 .cfi_offset 6, -20 11226 .cfi_offset 7, -16 11227 .cfi_offset 8, -12 11228 .cfi_offset 9, -8 11229 .cfi_offset 14, -4 11230 0004 87B0 sub sp, sp, #28 11231 .LCFI117: 11232 .cfi_def_cfa_offset 56 273:Src/main.c **** /* USER CODE END 1 */ 11233 .loc 1 273 2 view .LVU3492 279:Src/main.c **** 11234 .loc 1 279 3 view .LVU3493 11235 0006 FFF7FEFF bl HAL_Init 11236 .LVL986: 286:Src/main.c **** 11237 .loc 1 286 3 view .LVU3494 11238 000a FFF7FEFF bl SystemClock_Config 11239 .LVL987: 293:Src/main.c **** MX_DMA_Init(); 11240 .loc 1 293 3 view .LVU3495 11241 000e FFF7FEFF bl MX_GPIO_Init 11242 .LVL988: 294:Src/main.c **** MX_SPI4_Init(); 11243 .loc 1 294 3 view .LVU3496 11244 0012 FFF7FEFF bl MX_DMA_Init 11245 .LVL989: 295:Src/main.c **** MX_FATFS_Init(); 11246 .loc 1 295 3 view .LVU3497 11247 0016 FFF7FEFF bl MX_SPI4_Init 11248 .LVL990: 296:Src/main.c **** MX_TIM2_Init(); 11249 .loc 1 296 3 view .LVU3498 11250 001a FFF7FEFF bl MX_FATFS_Init 11251 .LVL991: 297:Src/main.c **** MX_TIM5_Init(); 11252 .loc 1 297 3 view .LVU3499 11253 001e FFF7FEFF bl MX_TIM2_Init 11254 .LVL992: 298:Src/main.c **** MX_ADC1_Init(); 11255 .loc 1 298 3 view .LVU3500 11256 0022 FFF7FEFF bl MX_TIM5_Init 11257 .LVL993: 299:Src/main.c **** MX_ADC3_Init(); 11258 .loc 1 299 3 view .LVU3501 11259 0026 FFF7FEFF bl MX_ADC1_Init 11260 .LVL994: ARM GAS /tmp/ccLSPxIe.s page 611 300:Src/main.c **** MX_SPI2_Init(); 11261 .loc 1 300 3 view .LVU3502 11262 002a FFF7FEFF bl MX_ADC3_Init 11263 .LVL995: 301:Src/main.c **** MX_SPI5_Init(); 11264 .loc 1 301 3 view .LVU3503 11265 002e FFF7FEFF bl MX_SPI2_Init 11266 .LVL996: 302:Src/main.c **** MX_SPI6_Init(); 11267 .loc 1 302 3 view .LVU3504 11268 0032 FFF7FEFF bl MX_SPI5_Init 11269 .LVL997: 303:Src/main.c **** MX_USART1_UART_Init(); 11270 .loc 1 303 3 view .LVU3505 11271 0036 FFF7FEFF bl MX_SPI6_Init 11272 .LVL998: 304:Src/main.c **** MX_SDMMC1_SD_Init(); 11273 .loc 1 304 3 view .LVU3506 11274 003a FFF7FEFF bl MX_USART1_UART_Init 11275 .LVL999: 305:Src/main.c **** MX_TIM7_Init(); 11276 .loc 1 305 3 view .LVU3507 11277 003e FFF7FEFF bl MX_SDMMC1_SD_Init 11278 .LVL1000: 306:Src/main.c **** MX_TIM6_Init(); 11279 .loc 1 306 3 view .LVU3508 11280 0042 FFF7FEFF bl MX_TIM7_Init 11281 .LVL1001: 307:Src/main.c **** MX_TIM10_Init(); 11282 .loc 1 307 3 view .LVU3509 11283 0046 FFF7FEFF bl MX_TIM6_Init 11284 .LVL1002: 308:Src/main.c **** MX_UART8_Init(); 11285 .loc 1 308 3 view .LVU3510 11286 004a FFF7FEFF bl MX_TIM10_Init 11287 .LVL1003: 309:Src/main.c **** MX_TIM8_Init(); 11288 .loc 1 309 3 view .LVU3511 11289 004e FFF7FEFF bl MX_UART8_Init 11290 .LVL1004: 310:Src/main.c **** MX_TIM11_Init(); 11291 .loc 1 310 3 view .LVU3512 11292 0052 FFF7FEFF bl MX_TIM8_Init 11293 .LVL1005: 311:Src/main.c **** MX_TIM4_Init(); 11294 .loc 1 311 3 view .LVU3513 11295 0056 FFF7FEFF bl MX_TIM11_Init 11296 .LVL1006: 312:Src/main.c **** MX_TIM1_Init(); 11297 .loc 1 312 3 view .LVU3514 11298 005a FFF7FEFF bl MX_TIM4_Init 11299 .LVL1007: 313:Src/main.c **** PA4_DAC_Init(); 11300 .loc 1 313 3 view .LVU3515 11301 005e FFF7FEFF bl MX_TIM1_Init 11302 .LVL1008: 314:Src/main.c **** /* USER CODE BEGIN 2 */ ARM GAS /tmp/ccLSPxIe.s page 612 11303 .loc 1 314 3 view .LVU3516 11304 0062 FFF7FEFF bl PA4_DAC_Init 11305 .LVL1009: 316:Src/main.c **** //HAL_TIM_Base_Start(&htim11); 11306 .loc 1 316 2 view .LVU3517 11307 0066 FFF7FEFF bl Init_params 11308 .LVL1010: 327:Src/main.c **** 11309 .loc 1 327 2 view .LVU3518 327:Src/main.c **** 11310 .loc 1 327 14 is_stmt 0 view .LVU3519 11311 006a 8D4A ldr r2, .L761 11312 006c 3523 movs r3, #53 11313 006e D362 str r3, [r2, #44] 329:Src/main.c **** 11314 .loc 1 329 2 is_stmt 1 view .LVU3520 329:Src/main.c **** 11315 .loc 1 329 23 is_stmt 0 view .LVU3521 11316 0070 D36A ldr r3, [r2, #44] 329:Src/main.c **** 11317 .loc 1 329 30 view .LVU3522 11318 0072 0133 adds r3, r3, #1 329:Src/main.c **** 11319 .loc 1 329 33 view .LVU3523 11320 0074 5B08 lsrs r3, r3, #1 329:Src/main.c **** 11321 .loc 1 329 36 view .LVU3524 11322 0076 013B subs r3, r3, #1 329:Src/main.c **** 11323 .loc 1 329 15 view .LVU3525 11324 0078 D363 str r3, [r2, #60] 334:Src/main.c **** TIM11 -> CCR1 = (TIM11 -> ARR +1)/2 - 1; 11325 .loc 1 334 2 is_stmt 1 view .LVU3526 334:Src/main.c **** TIM11 -> CCR1 = (TIM11 -> ARR +1)/2 - 1; 11326 .loc 1 334 23 is_stmt 0 view .LVU3527 11327 007a D36A ldr r3, [r2, #44] 334:Src/main.c **** TIM11 -> CCR1 = (TIM11 -> ARR +1)/2 - 1; 11328 .loc 1 334 36 view .LVU3528 11329 007c 9B00 lsls r3, r3, #2 11330 007e 0333 adds r3, r3, #3 334:Src/main.c **** TIM11 -> CCR1 = (TIM11 -> ARR +1)/2 - 1; 11331 .loc 1 334 15 view .LVU3529 11332 0080 02F5A032 add r2, r2, #81920 11333 0084 D362 str r3, [r2, #44] 335:Src/main.c **** 11334 .loc 1 335 2 is_stmt 1 view .LVU3530 335:Src/main.c **** 11335 .loc 1 335 25 is_stmt 0 view .LVU3531 11336 0086 D36A ldr r3, [r2, #44] 335:Src/main.c **** 11337 .loc 1 335 32 view .LVU3532 11338 0088 0133 adds r3, r3, #1 335:Src/main.c **** 11339 .loc 1 335 35 view .LVU3533 11340 008a 5B08 lsrs r3, r3, #1 335:Src/main.c **** 11341 .loc 1 335 38 view .LVU3534 ARM GAS /tmp/ccLSPxIe.s page 613 11342 008c 013B subs r3, r3, #1 335:Src/main.c **** 11343 .loc 1 335 16 view .LVU3535 11344 008e 5363 str r3, [r2, #52] 339:Src/main.c **** 11345 .loc 1 339 2 is_stmt 1 view .LVU3536 11346 0090 0021 movs r1, #0 11347 0092 8448 ldr r0, .L761+4 11348 0094 FFF7FEFF bl HAL_TIM_PWM_Start 11349 .LVL1011: 11350 0098 4CE0 b .L647 11351 .L746: 353:Src/main.c **** { 11352 .loc 1 353 85 is_stmt 0 discriminator 1 view .LVU3537 11353 009a 834B ldr r3, .L761+8 11354 009c 1B78 ldrb r3, [r3] @ zero_extendqisi2 353:Src/main.c **** { 11355 .loc 1 353 73 discriminator 1 view .LVU3538 11356 009e 002B cmp r3, #0 11357 00a0 4FD1 bne .L648 11358 .L649: 11359 .LBB681: 3073:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 11360 .loc 7 3073 3 is_stmt 1 discriminator 1 view .LVU3539 11361 .LBB682: 3073:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 11362 .loc 7 3073 3 discriminator 1 view .LVU3540 3073:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 11363 .loc 7 3073 3 discriminator 1 view .LVU3541 3073:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 11364 .loc 7 3073 3 discriminator 1 view .LVU3542 11365 .LVL1012: 11366 .LBB683: 11367 .LBI683: 1068:Drivers/CMSIS/Include/cmsis_gcc.h **** { 11368 .loc 8 1068 31 view .LVU3543 11369 .LBB684: 1070:Drivers/CMSIS/Include/cmsis_gcc.h **** 11370 .loc 8 1070 5 view .LVU3544 1072:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 11371 .loc 8 1072 4 view .LVU3545 11372 00a2 824A ldr r2, .L761+12 11373 .syntax unified 11374 @ 1072 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 11375 00a4 52E8003F ldrex r3, [r2] 11376 @ 0 "" 2 11377 .LVL1013: 1073:Drivers/CMSIS/Include/cmsis_gcc.h **** } 11378 .loc 8 1073 4 view .LVU3546 1073:Drivers/CMSIS/Include/cmsis_gcc.h **** } 11379 .loc 8 1073 4 is_stmt 0 view .LVU3547 11380 .thumb 11381 .syntax unified 11382 .LBE684: 11383 .LBE683: 3073:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 11384 .loc 7 3073 3 discriminator 1 view .LVU3548 ARM GAS /tmp/ccLSPxIe.s page 614 11385 00a8 43F48073 orr r3, r3, #256 11386 .LVL1014: 3073:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 11387 .loc 7 3073 3 is_stmt 1 discriminator 1 view .LVU3549 11388 .LBB685: 11389 .LBI685: 1119:Drivers/CMSIS/Include/cmsis_gcc.h **** { 11390 .loc 8 1119 31 view .LVU3550 11391 .LBB686: 1121:Drivers/CMSIS/Include/cmsis_gcc.h **** 11392 .loc 8 1121 4 view .LVU3551 1123:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 11393 .loc 8 1123 4 view .LVU3552 11394 .syntax unified 11395 @ 1123 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 11396 00ac 42E80031 strex r1, r3, [r2] 11397 @ 0 "" 2 11398 .LVL1015: 11399 .loc 8 1124 4 view .LVU3553 11400 .loc 8 1124 4 is_stmt 0 view .LVU3554 11401 .thumb 11402 .syntax unified 11403 .LBE686: 11404 .LBE685: 3073:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 11405 .loc 7 3073 3 discriminator 1 view .LVU3555 11406 00b0 0029 cmp r1, #0 11407 00b2 F6D1 bne .L649 11408 .LVL1016: 11409 .L650: 3073:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 11410 .loc 7 3073 3 discriminator 1 view .LVU3556 11411 .LBE682: 11412 .LBE681: 11413 .LBB687: 3040:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 11414 .loc 7 3040 3 is_stmt 1 discriminator 1 view .LVU3557 11415 .LBB688: 3040:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 11416 .loc 7 3040 3 discriminator 1 view .LVU3558 3040:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 11417 .loc 7 3040 3 discriminator 1 view .LVU3559 3040:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 11418 .loc 7 3040 3 discriminator 1 view .LVU3560 11419 .LBB689: 11420 .LBI689: 1068:Drivers/CMSIS/Include/cmsis_gcc.h **** { 11421 .loc 8 1068 31 view .LVU3561 11422 .LBB690: 1070:Drivers/CMSIS/Include/cmsis_gcc.h **** 11423 .loc 8 1070 5 view .LVU3562 1072:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 11424 .loc 8 1072 4 view .LVU3563 11425 00b4 7D4A ldr r2, .L761+12 11426 .syntax unified 11427 @ 1072 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 11428 00b6 52E8003F ldrex r3, [r2] ARM GAS /tmp/ccLSPxIe.s page 615 11429 @ 0 "" 2 11430 .LVL1017: 1073:Drivers/CMSIS/Include/cmsis_gcc.h **** } 11431 .loc 8 1073 4 view .LVU3564 1073:Drivers/CMSIS/Include/cmsis_gcc.h **** } 11432 .loc 8 1073 4 is_stmt 0 view .LVU3565 11433 .thumb 11434 .syntax unified 11435 .LBE690: 11436 .LBE689: 3040:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 11437 .loc 7 3040 3 discriminator 1 view .LVU3566 11438 00ba 43F02003 orr r3, r3, #32 11439 .LVL1018: 3040:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 11440 .loc 7 3040 3 is_stmt 1 discriminator 1 view .LVU3567 11441 .LBB691: 11442 .LBI691: 1119:Drivers/CMSIS/Include/cmsis_gcc.h **** { 11443 .loc 8 1119 31 view .LVU3568 11444 .LBB692: 1121:Drivers/CMSIS/Include/cmsis_gcc.h **** 11445 .loc 8 1121 4 view .LVU3569 1123:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 11446 .loc 8 1123 4 view .LVU3570 11447 .syntax unified 11448 @ 1123 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 11449 00be 42E80031 strex r1, r3, [r2] 11450 @ 0 "" 2 11451 .LVL1019: 11452 .loc 8 1124 4 view .LVU3571 11453 .loc 8 1124 4 is_stmt 0 view .LVU3572 11454 .thumb 11455 .syntax unified 11456 .LBE692: 11457 .LBE691: 3040:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 11458 .loc 7 3040 3 discriminator 1 view .LVU3573 11459 00c2 0029 cmp r1, #0 11460 00c4 F6D1 bne .L650 11461 .LVL1020: 11462 .L651: 3040:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 11463 .loc 7 3040 3 discriminator 1 view .LVU3574 11464 .LBE688: 11465 .LBE687: 11466 .LBB693: 3136:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 11467 .loc 7 3136 3 is_stmt 1 discriminator 1 view .LVU3575 11468 .LBB694: 3136:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 11469 .loc 7 3136 3 discriminator 1 view .LVU3576 3136:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 11470 .loc 7 3136 3 discriminator 1 view .LVU3577 3136:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 11471 .loc 7 3136 3 discriminator 1 view .LVU3578 11472 .LBB695: ARM GAS /tmp/ccLSPxIe.s page 616 11473 .LBI695: 1068:Drivers/CMSIS/Include/cmsis_gcc.h **** { 11474 .loc 8 1068 31 view .LVU3579 11475 .LBB696: 1070:Drivers/CMSIS/Include/cmsis_gcc.h **** 11476 .loc 8 1070 5 view .LVU3580 1072:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 11477 .loc 8 1072 4 view .LVU3581 11478 00c6 794A ldr r2, .L761+12 11479 00c8 02F10803 add r3, r2, #8 11480 .syntax unified 11481 @ 1072 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 11482 00cc 53E8003F ldrex r3, [r3] 11483 @ 0 "" 2 11484 .LVL1021: 1073:Drivers/CMSIS/Include/cmsis_gcc.h **** } 11485 .loc 8 1073 4 view .LVU3582 1073:Drivers/CMSIS/Include/cmsis_gcc.h **** } 11486 .loc 8 1073 4 is_stmt 0 view .LVU3583 11487 .thumb 11488 .syntax unified 11489 .LBE696: 11490 .LBE695: 3136:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 11491 .loc 7 3136 3 discriminator 1 view .LVU3584 11492 00d0 43F00103 orr r3, r3, #1 11493 .LVL1022: 3136:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 11494 .loc 7 3136 3 is_stmt 1 discriminator 1 view .LVU3585 11495 .LBB697: 11496 .LBI697: 1119:Drivers/CMSIS/Include/cmsis_gcc.h **** { 11497 .loc 8 1119 31 view .LVU3586 11498 .LBB698: 1121:Drivers/CMSIS/Include/cmsis_gcc.h **** 11499 .loc 8 1121 4 view .LVU3587 1123:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 11500 .loc 8 1123 4 view .LVU3588 11501 00d4 0832 adds r2, r2, #8 11502 .syntax unified 11503 @ 1123 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 11504 00d6 42E80031 strex r1, r3, [r2] 11505 @ 0 "" 2 11506 .LVL1023: 11507 .loc 8 1124 4 view .LVU3589 11508 .loc 8 1124 4 is_stmt 0 view .LVU3590 11509 .thumb 11510 .syntax unified 11511 .LBE698: 11512 .LBE697: 3136:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 11513 .loc 7 3136 3 discriminator 1 view .LVU3591 11514 00da 0029 cmp r1, #0 11515 00dc F3D1 bne .L651 11516 .LBE694: 3136:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 11517 .loc 7 3136 3 is_stmt 1 discriminator 2 view .LVU3592 ARM GAS /tmp/ccLSPxIe.s page 617 11518 .LVL1024: 3136:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } 11519 .loc 7 3136 3 is_stmt 0 discriminator 2 view .LVU3593 11520 .LBE693: 359:Src/main.c **** NVIC_EnableIRQ(USART1_IRQn);//In other case you have FE error flag... 11521 .loc 1 359 4 is_stmt 1 view .LVU3594 11522 .LBB699: 11523 .LBI699: 2024:Drivers/CMSIS/Include/core_cm7.h **** { 11524 .loc 2 2024 22 view .LVU3595 11525 .LBB700: 2026:Drivers/CMSIS/Include/core_cm7.h **** { 11526 .loc 2 2026 3 view .LVU3596 2028:Drivers/CMSIS/Include/core_cm7.h **** } 11527 .loc 2 2028 5 view .LVU3597 2028:Drivers/CMSIS/Include/core_cm7.h **** } 11528 .loc 2 2028 47 is_stmt 0 view .LVU3598 11529 00de 744B ldr r3, .L761+16 11530 00e0 0022 movs r2, #0 11531 00e2 83F82523 strb r2, [r3, #805] 11532 .LVL1025: 2028:Drivers/CMSIS/Include/core_cm7.h **** } 11533 .loc 2 2028 47 view .LVU3599 11534 .LBE700: 11535 .LBE699: 360:Src/main.c **** u_rx_flg = 1; 11536 .loc 1 360 4 is_stmt 1 view .LVU3600 11537 .LBB701: 11538 .LBI701: 1896:Drivers/CMSIS/Include/core_cm7.h **** { 11539 .loc 2 1896 22 view .LVU3601 11540 .LBB702: 1898:Drivers/CMSIS/Include/core_cm7.h **** { 11541 .loc 2 1898 3 view .LVU3602 1900:Drivers/CMSIS/Include/core_cm7.h **** } 11542 .loc 2 1900 5 view .LVU3603 1900:Drivers/CMSIS/Include/core_cm7.h **** } 11543 .loc 2 1900 43 is_stmt 0 view .LVU3604 11544 00e6 2022 movs r2, #32 11545 00e8 5A60 str r2, [r3, #4] 11546 .LVL1026: 1900:Drivers/CMSIS/Include/core_cm7.h **** } 11547 .loc 2 1900 43 view .LVU3605 11548 .LBE702: 11549 .LBE701: 361:Src/main.c **** } 11550 .loc 1 361 4 is_stmt 1 view .LVU3606 361:Src/main.c **** } 11551 .loc 1 361 13 is_stmt 0 view .LVU3607 11552 00ea 6F4B ldr r3, .L761+8 11553 00ec 0122 movs r2, #1 11554 00ee 1A70 strb r2, [r3] 11555 00f0 27E0 b .L648 11556 .L669: 371:Src/main.c **** task.current_param = task.min_param; 11557 .loc 1 371 6 is_stmt 1 view .LVU3608 371:Src/main.c **** task.current_param = task.min_param; ARM GAS /tmp/ccLSPxIe.s page 618 11558 .loc 1 371 20 is_stmt 0 view .LVU3609 11559 00f2 704B ldr r3, .L761+20 11560 00f4 0022 movs r2, #0 11561 00f6 1A70 strb r2, [r3] 372:Src/main.c **** Stop_TIM10(); 11562 .loc 1 372 6 is_stmt 1 view .LVU3610 372:Src/main.c **** Stop_TIM10(); 11563 .loc 1 372 31 is_stmt 0 view .LVU3611 11564 00f8 6F4B ldr r3, .L761+24 11565 00fa 5A68 ldr r2, [r3, #4] @ float 372:Src/main.c **** Stop_TIM10(); 11566 .loc 1 372 25 view .LVU3612 11567 00fc 1A61 str r2, [r3, #16] @ float 373:Src/main.c **** break; 11568 .loc 1 373 6 is_stmt 1 view .LVU3613 11569 00fe FFF7FEFF bl Stop_TIM10 11570 .LVL1027: 374:Src/main.c **** case DECODE_ENABLE://1 - Decode rec. message 11571 .loc 1 374 5 view .LVU3614 11572 .L652: 1084:Src/main.c **** { 11573 .loc 1 1084 3 view .LVU3615 11574 0102 6E4B ldr r3, .L761+28 11575 0104 1B78 ldrb r3, [r3] @ zero_extendqisi2 11576 0106 022B cmp r3, #2 11577 0108 00F0C085 beq .L726 11578 010c 032B cmp r3, #3 11579 010e 00F0F385 beq .L742 11580 0112 012B cmp r3, #1 11581 0114 09D1 bne .L728 1087:Src/main.c **** //HAL_UART_Transmit(&huart1, State_Data, 2, 10); 11582 .loc 1 1087 5 view .LVU3616 11583 0116 6A4C ldr r4, .L761+32 11584 0118 0221 movs r1, #2 11585 011a 2046 mov r0, r4 11586 011c FFF7FEFF bl USART_TX 11587 .LVL1028: 1089:Src/main.c **** State_Data[1]=0;//All OK! 11588 .loc 1 1089 5 view .LVU3617 1089:Src/main.c **** State_Data[1]=0;//All OK! 11589 .loc 1 1089 18 is_stmt 0 view .LVU3618 11590 0120 0023 movs r3, #0 11591 0122 2370 strb r3, [r4] 1090:Src/main.c **** UART_transmission_request = NO_MESS; 11592 .loc 1 1090 5 is_stmt 1 view .LVU3619 1090:Src/main.c **** UART_transmission_request = NO_MESS; 11593 .loc 1 1090 18 is_stmt 0 view .LVU3620 11594 0124 6370 strb r3, [r4, #1] 1091:Src/main.c **** break; 11595 .loc 1 1091 5 is_stmt 1 view .LVU3621 1091:Src/main.c **** break; 11596 .loc 1 1091 31 is_stmt 0 view .LVU3622 11597 0126 654A ldr r2, .L761+28 11598 0128 1370 strb r3, [r2] 1092:Src/main.c **** case MESS_02://Transmith packet 11599 .loc 1 1092 4 is_stmt 1 view .LVU3623 11600 .L728: ARM GAS /tmp/ccLSPxIe.s page 619 1126:Src/main.c **** { 11601 .loc 1 1126 5 view .LVU3624 1126:Src/main.c **** { 11602 .loc 1 1126 17 is_stmt 0 view .LVU3625 11603 012a 664B ldr r3, .L761+36 11604 012c 1B78 ldrb r3, [r3] @ zero_extendqisi2 1126:Src/main.c **** { 11605 .loc 1 1126 8 view .LVU3626 11606 012e 012B cmp r3, #1 11607 0130 00F0E485 beq .L745 11608 .L647: 351:Src/main.c **** { 11609 .loc 1 351 3 is_stmt 1 view .LVU3627 353:Src/main.c **** { 11610 .loc 1 353 3 view .LVU3628 353:Src/main.c **** { 11611 .loc 1 353 8 is_stmt 0 view .LVU3629 11612 0134 4FF48071 mov r1, #256 11613 0138 6348 ldr r0, .L761+40 11614 013a FFF7FEFF bl HAL_GPIO_ReadPin 11615 .LVL1029: 353:Src/main.c **** { 11616 .loc 1 353 6 discriminator 1 view .LVU3630 11617 013e 0128 cmp r0, #1 11618 0140 ABD0 beq .L746 11619 .L648: 368:Src/main.c **** { 11620 .loc 1 368 4 is_stmt 1 view .LVU3631 11621 0142 624B ldr r3, .L761+44 11622 0144 1B78 ldrb r3, [r3] @ zero_extendqisi2 11623 0146 0F2B cmp r3, #15 11624 0148 DBD8 bhi .L652 11625 014a 01A2 adr r2, .L654 11626 014c 52F823F0 ldr pc, [r2, r3, lsl #2] 11627 .p2align 2 11628 .L654: 11629 0150 F3000000 .word .L669+1 11630 0154 91010000 .word .L668+1 11631 0158 FB010000 .word .L667+1 11632 015c 35020000 .word .L666+1 11633 0160 65020000 .word .L665+1 11634 0164 75020000 .word .L664+1 11635 0168 91020000 .word .L663+1 11636 016c F9020000 .word .L662+1 11637 0170 89070000 .word .L661+1 11638 0174 CF070000 .word .L660+1 11639 0178 4D040000 .word .L659+1 11640 017c 29050000 .word .L658+1 11641 0180 79050000 .word .L657+1 11642 0184 2F060000 .word .L656+1 11643 0188 6B060000 .word .L655+1 11644 018c 37070000 .word .L653+1 11645 .p2align 1 11646 .L668: 376:Src/main.c **** if (CheckChecksum(COMMAND)) 11647 .loc 1 376 6 view .LVU3632 376:Src/main.c **** if (CheckChecksum(COMMAND)) ARM GAS /tmp/ccLSPxIe.s page 620 11648 .loc 1 376 18 is_stmt 0 view .LVU3633 11649 0190 4F4C ldr r4, .L761+48 11650 0192 0D21 movs r1, #13 11651 0194 2046 mov r0, r4 11652 0196 FFF7FEFF bl CalculateChecksum 11653 .LVL1030: 376:Src/main.c **** if (CheckChecksum(COMMAND)) 11654 .loc 1 376 16 discriminator 1 view .LVU3634 11655 019a 4E4B ldr r3, .L761+52 11656 019c 1880 strh r0, [r3] @ movhi 377:Src/main.c **** { 11657 .loc 1 377 6 is_stmt 1 view .LVU3635 377:Src/main.c **** { 11658 .loc 1 377 10 is_stmt 0 view .LVU3636 11659 019e 2046 mov r0, r4 11660 01a0 FFF7FEFF bl CheckChecksum 11661 .LVL1031: 377:Src/main.c **** { 11662 .loc 1 377 9 discriminator 1 view .LVU3637 11663 01a4 70B9 cbnz r0, .L747 390:Src/main.c **** CPU_state = DEFAULT_ENABLE; 11664 .loc 1 390 7 is_stmt 1 view .LVU3638 390:Src/main.c **** CPU_state = DEFAULT_ENABLE; 11665 .loc 1 390 17 is_stmt 0 view .LVU3639 11666 01a6 464A ldr r2, .L761+32 11667 01a8 1378 ldrb r3, [r2] @ zero_extendqisi2 390:Src/main.c **** CPU_state = DEFAULT_ENABLE; 11668 .loc 1 390 21 view .LVU3640 11669 01aa 43F00403 orr r3, r3, #4 11670 01ae 1370 strb r3, [r2] 391:Src/main.c **** CPU_state_old = HALT;//Save main current cycle 11671 .loc 1 391 7 is_stmt 1 view .LVU3641 391:Src/main.c **** CPU_state_old = HALT;//Save main current cycle 11672 .loc 1 391 17 is_stmt 0 view .LVU3642 11673 01b0 464B ldr r3, .L761+44 11674 01b2 0222 movs r2, #2 11675 01b4 1A70 strb r2, [r3] 392:Src/main.c **** } 11676 .loc 1 392 7 is_stmt 1 view .LVU3643 392:Src/main.c **** } 11677 .loc 1 392 21 is_stmt 0 view .LVU3644 11678 01b6 3F4B ldr r3, .L761+20 11679 01b8 0022 movs r2, #0 11680 01ba 1A70 strb r2, [r3] 11681 .L671: 394:Src/main.c **** break; 11682 .loc 1 394 6 is_stmt 1 view .LVU3645 394:Src/main.c **** break; 11683 .loc 1 394 32 is_stmt 0 view .LVU3646 11684 01bc 3F4B ldr r3, .L761+28 11685 01be 0122 movs r2, #1 11686 01c0 1A70 strb r2, [r3] 395:Src/main.c **** case DEFAULT_ENABLE://2 - Go to HALT 11687 .loc 1 395 5 is_stmt 1 view .LVU3647 11688 01c2 9EE7 b .L652 11689 .L747: 379:Src/main.c **** LL_SPI_Enable(SPI6);//Enable SPI for Laser2 DAC & TEC2 ARM GAS /tmp/ccLSPxIe.s page 621 11690 .loc 1 379 7 view .LVU3648 11691 .LVL1032: 11692 .LBB703: 11693 .LBI703: 358:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 11694 .loc 4 358 22 view .LVU3649 11695 .LBB704: 360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 11696 .loc 4 360 3 view .LVU3650 11697 01c4 444A ldr r2, .L761+56 11698 01c6 1368 ldr r3, [r2] 11699 01c8 43F04003 orr r3, r3, #64 11700 01cc 1360 str r3, [r2] 11701 .LVL1033: 360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 11702 .loc 4 360 3 is_stmt 0 view .LVU3651 11703 .LBE704: 11704 .LBE703: 380:Src/main.c **** Decode_uart(COMMAND, &LD1_curr_setup, &LD2_curr_setup, &Curr_setup); 11705 .loc 1 380 7 is_stmt 1 view .LVU3652 11706 .LBB705: 11707 .LBI705: 358:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 11708 .loc 4 358 22 view .LVU3653 11709 .LBB706: 360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 11710 .loc 4 360 3 view .LVU3654 11711 01ce 02F58E32 add r2, r2, #72704 11712 01d2 1368 ldr r3, [r2] 11713 01d4 43F04003 orr r3, r3, #64 11714 01d8 1360 str r3, [r2] 11715 .LVL1034: 360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 11716 .loc 4 360 3 is_stmt 0 view .LVU3655 11717 .LBE706: 11718 .LBE705: 381:Src/main.c **** TO6_before = TO6; 11719 .loc 1 381 7 is_stmt 1 view .LVU3656 11720 01da 404B ldr r3, .L761+60 11721 01dc 404A ldr r2, .L761+64 11722 01de 4149 ldr r1, .L761+68 11723 01e0 2046 mov r0, r4 11724 01e2 FFF7FEFF bl Decode_uart 11725 .LVL1035: 382:Src/main.c **** //LD1_param.LD_TEMP_Before = LD1_param.LD_TEMP; 11726 .loc 1 382 7 view .LVU3657 382:Src/main.c **** //LD1_param.LD_TEMP_Before = LD1_param.LD_TEMP; 11727 .loc 1 382 18 is_stmt 0 view .LVU3658 11728 01e6 404B ldr r3, .L761+72 11729 01e8 1A68 ldr r2, [r3] 11730 01ea 404B ldr r3, .L761+76 11731 01ec 1A60 str r2, [r3] 385:Src/main.c **** CPU_state_old = WORK_ENABLE;//Save main current cycle 11732 .loc 1 385 7 is_stmt 1 view .LVU3659 385:Src/main.c **** CPU_state_old = WORK_ENABLE;//Save main current cycle 11733 .loc 1 385 17 is_stmt 0 view .LVU3660 11734 01ee 0723 movs r3, #7 ARM GAS /tmp/ccLSPxIe.s page 622 11735 01f0 364A ldr r2, .L761+44 11736 01f2 1370 strb r3, [r2] 386:Src/main.c **** } 11737 .loc 1 386 7 is_stmt 1 view .LVU3661 386:Src/main.c **** } 11738 .loc 1 386 21 is_stmt 0 view .LVU3662 11739 01f4 2F4A ldr r2, .L761+20 11740 01f6 1370 strb r3, [r2] 11741 01f8 E0E7 b .L671 11742 .L667: 398:Src/main.c **** Stop_TIM10(); 11743 .loc 1 398 6 is_stmt 1 view .LVU3663 398:Src/main.c **** Stop_TIM10(); 11744 .loc 1 398 31 is_stmt 0 view .LVU3664 11745 01fa 2F4B ldr r3, .L761+24 11746 01fc 5A68 ldr r2, [r3, #4] @ float 398:Src/main.c **** Stop_TIM10(); 11747 .loc 1 398 25 view .LVU3665 11748 01fe 1A61 str r2, [r3, #16] @ float 399:Src/main.c **** Init_params(); 11749 .loc 1 399 6 is_stmt 1 view .LVU3666 11750 0200 FFF7FEFF bl Stop_TIM10 11751 .LVL1036: 400:Src/main.c **** AD9102_CancelWaveUpload(); 11752 .loc 1 400 6 view .LVU3667 11753 0204 FFF7FEFF bl Init_params 11754 .LVL1037: 401:Src/main.c **** LL_SPI_Disable(SPI2);//Disable SPI for Laser1 DAC & TEC1 11755 .loc 1 401 6 view .LVU3668 11756 0208 FFF7FEFF bl AD9102_CancelWaveUpload 11757 .LVL1038: 402:Src/main.c **** LL_SPI_Disable(SPI6);//Disable SPI for Laser2 DAC & TEC2 11758 .loc 1 402 6 view .LVU3669 11759 .LBB707: 11760 .LBI707: 370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 11761 .loc 4 370 22 view .LVU3670 11762 .LBB708: 372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 11763 .loc 4 372 3 view .LVU3671 11764 020c 324A ldr r2, .L761+56 11765 020e 1368 ldr r3, [r2] 11766 0210 23F04003 bic r3, r3, #64 11767 0214 1360 str r3, [r2] 11768 .LVL1039: 372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 11769 .loc 4 372 3 is_stmt 0 view .LVU3672 11770 .LBE708: 11771 .LBE707: 403:Src/main.c **** CPU_state = HALT; 11772 .loc 1 403 6 is_stmt 1 view .LVU3673 11773 .LBB709: 11774 .LBI709: 370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { 11775 .loc 4 370 22 view .LVU3674 11776 .LBB710: 372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } ARM GAS /tmp/ccLSPxIe.s page 623 11777 .loc 4 372 3 view .LVU3675 11778 0216 02F58E32 add r2, r2, #72704 11779 021a 1368 ldr r3, [r2] 11780 021c 23F04003 bic r3, r3, #64 11781 0220 1360 str r3, [r2] 11782 .LVL1040: 372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } 11783 .loc 4 372 3 is_stmt 0 view .LVU3676 11784 .LBE710: 11785 .LBE709: 404:Src/main.c **** CPU_state_old = HALT;//Save main current cycle 11786 .loc 1 404 6 is_stmt 1 view .LVU3677 404:Src/main.c **** CPU_state_old = HALT;//Save main current cycle 11787 .loc 1 404 16 is_stmt 0 view .LVU3678 11788 0222 0023 movs r3, #0 11789 0224 294A ldr r2, .L761+44 11790 0226 1370 strb r3, [r2] 405:Src/main.c **** UART_transmission_request = MESS_01; 11791 .loc 1 405 6 is_stmt 1 view .LVU3679 405:Src/main.c **** UART_transmission_request = MESS_01; 11792 .loc 1 405 20 is_stmt 0 view .LVU3680 11793 0228 224A ldr r2, .L761+20 11794 022a 1370 strb r3, [r2] 406:Src/main.c **** break; 11795 .loc 1 406 6 is_stmt 1 view .LVU3681 406:Src/main.c **** break; 11796 .loc 1 406 32 is_stmt 0 view .LVU3682 11797 022c 234B ldr r3, .L761+28 11798 022e 0122 movs r2, #1 11799 0230 1A70 strb r2, [r3] 407:Src/main.c **** case TRANS_S_ENABLE://3 - Transmith saved packet Before this operation must to be defaulting! 11800 .loc 1 407 5 is_stmt 1 view .LVU3683 11801 0232 66E7 b .L652 11802 .L666: 409:Src/main.c **** State_Data[0]|=temp16&0xff; 11803 .loc 1 409 6 view .LVU3684 409:Src/main.c **** State_Data[0]|=temp16&0xff; 11804 .loc 1 409 15 is_stmt 0 view .LVU3685 11805 0234 2E48 ldr r0, .L761+80 11806 0236 FFF7FEFF bl SD_READ 11807 .LVL1041: 409:Src/main.c **** State_Data[0]|=temp16&0xff; 11808 .loc 1 409 13 discriminator 1 view .LVU3686 11809 023a 82B2 uxth r2, r0 11810 023c 2D4B ldr r3, .L761+84 11811 023e 1A80 strh r2, [r3] @ movhi 410:Src/main.c **** if (temp16==0) 11812 .loc 1 410 6 is_stmt 1 view .LVU3687 410:Src/main.c **** if (temp16==0) 11813 .loc 1 410 16 is_stmt 0 view .LVU3688 11814 0240 1F49 ldr r1, .L761+32 11815 0242 0B78 ldrb r3, [r1] @ zero_extendqisi2 410:Src/main.c **** if (temp16==0) 11816 .loc 1 410 19 view .LVU3689 11817 0244 0343 orrs r3, r3, r0 11818 0246 0B70 strb r3, [r1] 411:Src/main.c **** { ARM GAS /tmp/ccLSPxIe.s page 624 11819 .loc 1 411 6 is_stmt 1 view .LVU3690 411:Src/main.c **** { 11820 .loc 1 411 9 is_stmt 0 view .LVU3691 11821 0248 42B9 cbnz r2, .L672 413:Src/main.c **** } 11822 .loc 1 413 7 is_stmt 1 view .LVU3692 413:Src/main.c **** } 11823 .loc 1 413 33 is_stmt 0 view .LVU3693 11824 024a 1C4B ldr r3, .L761+28 11825 024c 0322 movs r2, #3 11826 024e 1A70 strb r2, [r3] 11827 .L673: 419:Src/main.c **** CPU_state = CPU_state_old;//Return to main current cycle 11828 .loc 1 419 6 is_stmt 1 view .LVU3694 419:Src/main.c **** CPU_state = CPU_state_old;//Return to main current cycle 11829 .loc 1 419 20 is_stmt 0 view .LVU3695 11830 0250 0023 movs r3, #0 11831 0252 184A ldr r2, .L761+20 11832 0254 1370 strb r3, [r2] 420:Src/main.c **** break; 11833 .loc 1 420 6 is_stmt 1 view .LVU3696 420:Src/main.c **** break; 11834 .loc 1 420 16 is_stmt 0 view .LVU3697 11835 0256 1D4A ldr r2, .L761+44 11836 0258 1370 strb r3, [r2] 421:Src/main.c **** case TRANS_ENABLE://4 - Transmith current packet 11837 .loc 1 421 5 is_stmt 1 view .LVU3698 11838 025a 52E7 b .L652 11839 .L672: 417:Src/main.c **** } 11840 .loc 1 417 7 view .LVU3699 417:Src/main.c **** } 11841 .loc 1 417 33 is_stmt 0 view .LVU3700 11842 025c 174B ldr r3, .L761+28 11843 025e 0122 movs r2, #1 11844 0260 1A70 strb r2, [r3] 11845 0262 F5E7 b .L673 11846 .L665: 423:Src/main.c **** CPU_state = CPU_state_old;//Return to main current cycle 11847 .loc 1 423 6 is_stmt 1 view .LVU3701 423:Src/main.c **** CPU_state = CPU_state_old;//Return to main current cycle 11848 .loc 1 423 32 is_stmt 0 view .LVU3702 11849 0264 154B ldr r3, .L761+28 11850 0266 0222 movs r2, #2 11851 0268 1A70 strb r2, [r3] 424:Src/main.c **** break; 11852 .loc 1 424 6 is_stmt 1 view .LVU3703 424:Src/main.c **** break; 11853 .loc 1 424 16 is_stmt 0 view .LVU3704 11854 026a 124B ldr r3, .L761+20 11855 026c 1A78 ldrb r2, [r3] @ zero_extendqisi2 11856 026e 174B ldr r3, .L761+44 11857 0270 1A70 strb r2, [r3] 425:Src/main.c **** case REMOVE_FILE://5 - Remove file from SD 11858 .loc 1 425 5 is_stmt 1 view .LVU3705 11859 0272 46E7 b .L652 11860 .L664: ARM GAS /tmp/ccLSPxIe.s page 625 427:Src/main.c **** UART_transmission_request = MESS_01; 11861 .loc 1 427 6 view .LVU3706 427:Src/main.c **** UART_transmission_request = MESS_01; 11862 .loc 1 427 21 is_stmt 0 view .LVU3707 11863 0274 FFF7FEFF bl SD_REMOVE 11864 .LVL1042: 427:Src/main.c **** UART_transmission_request = MESS_01; 11865 .loc 1 427 16 discriminator 1 view .LVU3708 11866 0278 114A ldr r2, .L761+32 11867 027a 1378 ldrb r3, [r2] @ zero_extendqisi2 427:Src/main.c **** UART_transmission_request = MESS_01; 11868 .loc 1 427 19 discriminator 1 view .LVU3709 11869 027c 0343 orrs r3, r3, r0 11870 027e 1370 strb r3, [r2] 428:Src/main.c **** CPU_state = CPU_state_old; 11871 .loc 1 428 6 is_stmt 1 view .LVU3710 428:Src/main.c **** CPU_state = CPU_state_old; 11872 .loc 1 428 32 is_stmt 0 view .LVU3711 11873 0280 0E4B ldr r3, .L761+28 11874 0282 0122 movs r2, #1 11875 0284 1A70 strb r2, [r3] 429:Src/main.c **** break; 11876 .loc 1 429 6 is_stmt 1 view .LVU3712 429:Src/main.c **** break; 11877 .loc 1 429 16 is_stmt 0 view .LVU3713 11878 0286 0B4B ldr r3, .L761+20 11879 0288 1A78 ldrb r2, [r3] @ zero_extendqisi2 11880 028a 104B ldr r3, .L761+44 11881 028c 1A70 strb r2, [r3] 430:Src/main.c **** case STATE://6 - Transmith state message 11882 .loc 1 430 5 is_stmt 1 view .LVU3714 11883 028e 38E7 b .L652 11884 .L663: 432:Src/main.c **** CPU_state = CPU_state_old;//Return to main current cycle 11885 .loc 1 432 6 view .LVU3715 432:Src/main.c **** CPU_state = CPU_state_old;//Return to main current cycle 11886 .loc 1 432 32 is_stmt 0 view .LVU3716 11887 0290 0A4B ldr r3, .L761+28 11888 0292 0122 movs r2, #1 11889 0294 1A70 strb r2, [r3] 433:Src/main.c **** break; 11890 .loc 1 433 6 is_stmt 1 view .LVU3717 433:Src/main.c **** break; 11891 .loc 1 433 16 is_stmt 0 view .LVU3718 11892 0296 074B ldr r3, .L761+20 11893 0298 1A78 ldrb r2, [r3] @ zero_extendqisi2 11894 029a 0C4B ldr r3, .L761+44 11895 029c 1A70 strb r2, [r3] 434:Src/main.c **** case WORK_ENABLE://7 - Main work cycle 11896 .loc 1 434 5 is_stmt 1 view .LVU3719 11897 029e 30E7 b .L652 11898 .L762: 11899 .align 2 11900 .L761: 11901 02a0 00080040 .word 1073743872 11902 02a4 00000000 .word htim1 11903 02a8 00000000 .word u_rx_flg ARM GAS /tmp/ccLSPxIe.s page 626 11904 02ac 00100140 .word 1073811456 11905 02b0 00E100E0 .word -536813312 11906 02b4 00000000 .word CPU_state_old 11907 02b8 00000000 .word task 11908 02bc 00000000 .word UART_transmission_request 11909 02c0 00000000 .word State_Data 11910 02c4 00000000 .word flg_tmt 11911 02c8 00000240 .word 1073872896 11912 02cc 00000000 .word CPU_state 11913 02d0 00000000 .word COMMAND 11914 02d4 00000000 .word CS_result 11915 02d8 00380040 .word 1073756160 11916 02dc 00000000 .word Curr_setup 11917 02e0 00000000 .word LD2_curr_setup 11918 02e4 00000000 .word LD1_curr_setup 11919 02e8 00000000 .word TO6 11920 02ec 00000000 .word TO6_before 11921 02f0 00000000 .word Long_Data 11922 02f4 00000000 .word temp16 11923 .L662: 436:Src/main.c **** Stop_TIM10(); 11924 .loc 1 436 6 view .LVU3720 436:Src/main.c **** Stop_TIM10(); 11925 .loc 1 436 31 is_stmt 0 view .LVU3721 11926 02f8 B24B ldr r3, .L763 11927 02fa 5A68 ldr r2, [r3, #4] @ float 436:Src/main.c **** Stop_TIM10(); 11928 .loc 1 436 25 view .LVU3722 11929 02fc 1A61 str r2, [r3, #16] @ float 437:Src/main.c **** if (TO7>TO7_before)//Main work cycle go with the timer 7 (1000 us or 1 kHz) 11930 .loc 1 437 6 is_stmt 1 view .LVU3723 11931 02fe FFF7FEFF bl Stop_TIM10 11932 .LVL1043: 438:Src/main.c **** { 11933 .loc 1 438 6 view .LVU3724 438:Src/main.c **** { 11934 .loc 1 438 13 is_stmt 0 view .LVU3725 11935 0302 B14B ldr r3, .L763+4 11936 0304 1B68 ldr r3, [r3] 11937 0306 B14A ldr r2, .L763+8 11938 0308 1268 ldr r2, [r2] 438:Src/main.c **** { 11939 .loc 1 438 9 view .LVU3726 11940 030a 9342 cmp r3, r2 11941 030c 7FF6F9AE bls .L652 440:Src/main.c **** LD1_param.POWER = MPhD_T(1);//Get Data from monitor photodiode of LD1 11942 .loc 1 440 7 is_stmt 1 view .LVU3727 440:Src/main.c **** LD1_param.POWER = MPhD_T(1);//Get Data from monitor photodiode of LD1 11943 .loc 1 440 18 is_stmt 0 view .LVU3728 11944 0310 AE4A ldr r2, .L763+8 11945 0312 1360 str r3, [r2] 441:Src/main.c **** LD1_param.POWER = MPhD_T(1);//Get Data from monitor photodiode of LD1 11946 .loc 1 441 7 is_stmt 1 view .LVU3729 441:Src/main.c **** LD1_param.POWER = MPhD_T(1);//Get Data from monitor photodiode of LD1 11947 .loc 1 441 25 is_stmt 0 view .LVU3730 11948 0314 0120 movs r0, #1 11949 0316 FFF7FEFF bl MPhD_T ARM GAS /tmp/ccLSPxIe.s page 627 11950 .LVL1044: 441:Src/main.c **** LD1_param.POWER = MPhD_T(1);//Get Data from monitor photodiode of LD1 11951 .loc 1 441 23 discriminator 1 view .LVU3731 11952 031a AD4F ldr r7, .L763+12 11953 031c 3881 strh r0, [r7, #8] @ movhi 442:Src/main.c **** LD2_param.POWER = MPhD_T(2);//Get Data from monitor photodiode of LD2 11954 .loc 1 442 7 is_stmt 1 view .LVU3732 442:Src/main.c **** LD2_param.POWER = MPhD_T(2);//Get Data from monitor photodiode of LD2 11955 .loc 1 442 25 is_stmt 0 view .LVU3733 11956 031e 0120 movs r0, #1 11957 0320 FFF7FEFF bl MPhD_T 11958 .LVL1045: 442:Src/main.c **** LD2_param.POWER = MPhD_T(2);//Get Data from monitor photodiode of LD2 11959 .loc 1 442 23 discriminator 1 view .LVU3734 11960 0324 3881 strh r0, [r7, #8] @ movhi 443:Src/main.c **** LD2_param.POWER = MPhD_T(2);//Get Data from monitor photodiode of LD2 11961 .loc 1 443 7 is_stmt 1 view .LVU3735 443:Src/main.c **** LD2_param.POWER = MPhD_T(2);//Get Data from monitor photodiode of LD2 11962 .loc 1 443 25 is_stmt 0 view .LVU3736 11963 0326 0220 movs r0, #2 11964 0328 FFF7FEFF bl MPhD_T 11965 .LVL1046: 443:Src/main.c **** LD2_param.POWER = MPhD_T(2);//Get Data from monitor photodiode of LD2 11966 .loc 1 443 23 discriminator 1 view .LVU3737 11967 032c A94E ldr r6, .L763+16 11968 032e 3081 strh r0, [r6, #8] @ movhi 444:Src/main.c **** 11969 .loc 1 444 7 is_stmt 1 view .LVU3738 444:Src/main.c **** 11970 .loc 1 444 25 is_stmt 0 view .LVU3739 11971 0330 0220 movs r0, #2 11972 0332 FFF7FEFF bl MPhD_T 11973 .LVL1047: 444:Src/main.c **** 11974 .loc 1 444 23 discriminator 1 view .LVU3740 11975 0336 3081 strh r0, [r6, #8] @ movhi 447:Src/main.c **** LD1_param.LD_CURR_TEMP = MPhD_T(3); 11976 .loc 1 447 7 is_stmt 1 view .LVU3741 447:Src/main.c **** LD1_param.LD_CURR_TEMP = MPhD_T(3); 11977 .loc 1 447 14 is_stmt 0 view .LVU3742 11978 0338 0320 movs r0, #3 11979 033a FFF7FEFF bl MPhD_T 11980 .LVL1048: 448:Src/main.c **** (void) MPhD_T(4); 11981 .loc 1 448 7 is_stmt 1 view .LVU3743 448:Src/main.c **** (void) MPhD_T(4); 11982 .loc 1 448 32 is_stmt 0 view .LVU3744 11983 033e 0320 movs r0, #3 11984 0340 FFF7FEFF bl MPhD_T 11985 .LVL1049: 448:Src/main.c **** (void) MPhD_T(4); 11986 .loc 1 448 30 discriminator 1 view .LVU3745 11987 0344 3880 strh r0, [r7] @ movhi 449:Src/main.c **** LD2_param.LD_CURR_TEMP = MPhD_T(4); 11988 .loc 1 449 7 is_stmt 1 view .LVU3746 449:Src/main.c **** LD2_param.LD_CURR_TEMP = MPhD_T(4); 11989 .loc 1 449 14 is_stmt 0 view .LVU3747 ARM GAS /tmp/ccLSPxIe.s page 628 11990 0346 0420 movs r0, #4 11991 0348 FFF7FEFF bl MPhD_T 11992 .LVL1050: 450:Src/main.c **** temp16=PID_Controller_Temp(&LD1_curr_setup, &LD1_param, 1); 11993 .loc 1 450 7 is_stmt 1 view .LVU3748 450:Src/main.c **** temp16=PID_Controller_Temp(&LD1_curr_setup, &LD1_param, 1); 11994 .loc 1 450 32 is_stmt 0 view .LVU3749 11995 034c 0420 movs r0, #4 11996 034e FFF7FEFF bl MPhD_T 11997 .LVL1051: 450:Src/main.c **** temp16=PID_Controller_Temp(&LD1_curr_setup, &LD1_param, 1); 11998 .loc 1 450 30 discriminator 1 view .LVU3750 11999 0352 3080 strh r0, [r6] @ movhi 451:Src/main.c **** Set_LTEC(3, temp16);//Drive Laser TEC 1 12000 .loc 1 451 7 is_stmt 1 view .LVU3751 451:Src/main.c **** Set_LTEC(3, temp16);//Drive Laser TEC 1 12001 .loc 1 451 14 is_stmt 0 view .LVU3752 12002 0354 DFF8AC82 ldr r8, .L763+64 12003 0358 0122 movs r2, #1 12004 035a 3946 mov r1, r7 12005 035c 4046 mov r0, r8 12006 035e FFF7FEFF bl PID_Controller_Temp 12007 .LVL1052: 12008 0362 0146 mov r1, r0 451:Src/main.c **** Set_LTEC(3, temp16);//Drive Laser TEC 1 12009 .loc 1 451 13 discriminator 1 view .LVU3753 12010 0364 9C4D ldr r5, .L763+20 12011 0366 2880 strh r0, [r5] @ movhi 452:Src/main.c **** temp16=PID_Controller_Temp(&LD2_curr_setup, &LD2_param, 2); 12012 .loc 1 452 7 is_stmt 1 view .LVU3754 12013 0368 0320 movs r0, #3 12014 036a FFF7FEFF bl Set_LTEC 12015 .LVL1053: 453:Src/main.c **** Set_LTEC(4, temp16);//Drive Laser TEC 2 12016 .loc 1 453 7 view .LVU3755 453:Src/main.c **** Set_LTEC(4, temp16);//Drive Laser TEC 2 12017 .loc 1 453 14 is_stmt 0 view .LVU3756 12018 036e DFF89892 ldr r9, .L763+68 12019 0372 0222 movs r2, #2 12020 0374 3146 mov r1, r6 12021 0376 4846 mov r0, r9 12022 0378 FFF7FEFF bl PID_Controller_Temp 12023 .LVL1054: 12024 037c 0146 mov r1, r0 453:Src/main.c **** Set_LTEC(4, temp16);//Drive Laser TEC 2 12025 .loc 1 453 13 discriminator 1 view .LVU3757 12026 037e 2880 strh r0, [r5] @ movhi 454:Src/main.c **** 12027 .loc 1 454 7 is_stmt 1 view .LVU3758 12028 0380 0420 movs r0, #4 12029 0382 FFF7FEFF bl Set_LTEC 12030 .LVL1055: 456:Src/main.c **** Long_Data[2] = LD2_param.POWER;//Translate Data from monitor photodiode of LD2 to Long_Data 12031 .loc 1 456 7 view .LVU3759 456:Src/main.c **** Long_Data[2] = LD2_param.POWER;//Translate Data from monitor photodiode of LD2 to Long_Data 12032 .loc 1 456 31 is_stmt 0 view .LVU3760 12033 0386 3B89 ldrh r3, [r7, #8] ARM GAS /tmp/ccLSPxIe.s page 629 456:Src/main.c **** Long_Data[2] = LD2_param.POWER;//Translate Data from monitor photodiode of LD2 to Long_Data 12034 .loc 1 456 20 view .LVU3761 12035 0388 944C ldr r4, .L763+24 12036 038a 6380 strh r3, [r4, #2] @ movhi 457:Src/main.c **** 12037 .loc 1 457 7 is_stmt 1 view .LVU3762 457:Src/main.c **** 12038 .loc 1 457 31 is_stmt 0 view .LVU3763 12039 038c 3389 ldrh r3, [r6, #8] 457:Src/main.c **** 12040 .loc 1 457 20 view .LVU3764 12041 038e A380 strh r3, [r4, #4] @ movhi 459:Src/main.c **** Set_LTEC(2,LD2_curr_setup.CURRENT);//Drive Laser diode 2 12042 .loc 1 459 7 is_stmt 1 view .LVU3765 12043 0390 B8F80C10 ldrh r1, [r8, #12] 12044 0394 0120 movs r0, #1 12045 0396 FFF7FEFF bl Set_LTEC 12046 .LVL1056: 460:Src/main.c **** 12047 .loc 1 460 7 view .LVU3766 12048 039a B9F80C10 ldrh r1, [r9, #12] 12049 039e 0220 movs r0, #2 12050 03a0 FFF7FEFF bl Set_LTEC 12051 .LVL1057: 464:Src/main.c **** temp16 = Get_ADC(1); 12052 .loc 1 464 7 view .LVU3767 464:Src/main.c **** temp16 = Get_ADC(1); 12053 .loc 1 464 16 is_stmt 0 view .LVU3768 12054 03a4 0020 movs r0, #0 12055 03a6 FFF7FEFF bl Get_ADC 12056 .LVL1058: 464:Src/main.c **** temp16 = Get_ADC(1); 12057 .loc 1 464 14 discriminator 1 view .LVU3769 12058 03aa 2880 strh r0, [r5] @ movhi 465:Src/main.c **** Long_Data[7] = temp16; // PA2 -- 3V_monitor // PB1 -- U_Rt1_ext_Gain 12059 .loc 1 465 7 is_stmt 1 view .LVU3770 465:Src/main.c **** Long_Data[7] = temp16; // PA2 -- 3V_monitor // PB1 -- U_Rt1_ext_Gain 12060 .loc 1 465 16 is_stmt 0 view .LVU3771 12061 03ac 0120 movs r0, #1 12062 03ae FFF7FEFF bl Get_ADC 12063 .LVL1059: 465:Src/main.c **** Long_Data[7] = temp16; // PA2 -- 3V_monitor // PB1 -- U_Rt1_ext_Gain 12064 .loc 1 465 14 discriminator 1 view .LVU3772 12065 03b2 2880 strh r0, [r5] @ movhi 466:Src/main.c **** 12066 .loc 1 466 7 is_stmt 1 view .LVU3773 466:Src/main.c **** 12067 .loc 1 466 20 is_stmt 0 view .LVU3774 12068 03b4 E081 strh r0, [r4, #14] @ movhi 469:Src/main.c **** Long_Data[8] = temp16; // PB0 -- U_Rt2_ext_Gain // PB0 -- U_Rt2_ext_Gain 12069 .loc 1 469 7 is_stmt 1 view .LVU3775 469:Src/main.c **** Long_Data[8] = temp16; // PB0 -- U_Rt2_ext_Gain // PB0 -- U_Rt2_ext_Gain 12070 .loc 1 469 16 is_stmt 0 view .LVU3776 12071 03b6 0120 movs r0, #1 12072 03b8 FFF7FEFF bl Get_ADC 12073 .LVL1060: 469:Src/main.c **** Long_Data[8] = temp16; // PB0 -- U_Rt2_ext_Gain // PB0 -- U_Rt2_ext_Gain ARM GAS /tmp/ccLSPxIe.s page 630 12074 .loc 1 469 14 discriminator 1 view .LVU3777 12075 03bc 2880 strh r0, [r5] @ movhi 470:Src/main.c **** 12076 .loc 1 470 7 is_stmt 1 view .LVU3778 470:Src/main.c **** 12077 .loc 1 470 20 is_stmt 0 view .LVU3779 12078 03be 2082 strh r0, [r4, #16] @ movhi 473:Src/main.c **** Long_Data[9] = temp16; // PB1 -- U_Rt1_ext_Gain // PA2 -- 3V_monitor 12079 .loc 1 473 7 is_stmt 1 view .LVU3780 473:Src/main.c **** Long_Data[9] = temp16; // PB1 -- U_Rt1_ext_Gain // PA2 -- 3V_monitor 12080 .loc 1 473 16 is_stmt 0 view .LVU3781 12081 03c0 0120 movs r0, #1 12082 03c2 FFF7FEFF bl Get_ADC 12083 .LVL1061: 473:Src/main.c **** Long_Data[9] = temp16; // PB1 -- U_Rt1_ext_Gain // PA2 -- 3V_monitor 12084 .loc 1 473 14 discriminator 1 view .LVU3782 12085 03c6 2880 strh r0, [r5] @ movhi 474:Src/main.c **** 12086 .loc 1 474 7 is_stmt 1 view .LVU3783 474:Src/main.c **** 12087 .loc 1 474 20 is_stmt 0 view .LVU3784 12088 03c8 6082 strh r0, [r4, #18] @ movhi 477:Src/main.c **** Long_Data[10] = temp16; // PC0 -- 5V1_monitor // PC0 -- 5V1_monitor 12089 .loc 1 477 7 is_stmt 1 view .LVU3785 477:Src/main.c **** Long_Data[10] = temp16; // PC0 -- 5V1_monitor // PC0 -- 5V1_monitor 12090 .loc 1 477 16 is_stmt 0 view .LVU3786 12091 03ca 0120 movs r0, #1 12092 03cc FFF7FEFF bl Get_ADC 12093 .LVL1062: 477:Src/main.c **** Long_Data[10] = temp16; // PC0 -- 5V1_monitor // PC0 -- 5V1_monitor 12094 .loc 1 477 14 discriminator 1 view .LVU3787 12095 03d0 2880 strh r0, [r5] @ movhi 478:Src/main.c **** 12096 .loc 1 478 7 is_stmt 1 view .LVU3788 478:Src/main.c **** 12097 .loc 1 478 21 is_stmt 0 view .LVU3789 12098 03d2 A082 strh r0, [r4, #20] @ movhi 481:Src/main.c **** Long_Data[11] = temp16; // PC1 -- 5V2_monitor // PC1 -- 5V2_monitor 12099 .loc 1 481 7 is_stmt 1 view .LVU3790 481:Src/main.c **** Long_Data[11] = temp16; // PC1 -- 5V2_monitor // PC1 -- 5V2_monitor 12100 .loc 1 481 16 is_stmt 0 view .LVU3791 12101 03d4 0120 movs r0, #1 12102 03d6 FFF7FEFF bl Get_ADC 12103 .LVL1063: 481:Src/main.c **** Long_Data[11] = temp16; // PC1 -- 5V2_monitor // PC1 -- 5V2_monitor 12104 .loc 1 481 14 discriminator 1 view .LVU3792 12105 03da 2880 strh r0, [r5] @ movhi 482:Src/main.c **** temp16 = Get_ADC(2); 12106 .loc 1 482 7 is_stmt 1 view .LVU3793 482:Src/main.c **** temp16 = Get_ADC(2); 12107 .loc 1 482 21 is_stmt 0 view .LVU3794 12108 03dc E082 strh r0, [r4, #22] @ movhi 483:Src/main.c **** 12109 .loc 1 483 7 is_stmt 1 view .LVU3795 483:Src/main.c **** 12110 .loc 1 483 16 is_stmt 0 view .LVU3796 12111 03de 0220 movs r0, #2 ARM GAS /tmp/ccLSPxIe.s page 631 12112 03e0 FFF7FEFF bl Get_ADC 12113 .LVL1064: 483:Src/main.c **** 12114 .loc 1 483 14 discriminator 1 view .LVU3797 12115 03e4 2880 strh r0, [r5] @ movhi 486:Src/main.c **** temp16 = Get_ADC(4); 12116 .loc 1 486 7 is_stmt 1 view .LVU3798 486:Src/main.c **** temp16 = Get_ADC(4); 12117 .loc 1 486 16 is_stmt 0 view .LVU3799 12118 03e6 0320 movs r0, #3 12119 03e8 FFF7FEFF bl Get_ADC 12120 .LVL1065: 486:Src/main.c **** temp16 = Get_ADC(4); 12121 .loc 1 486 14 discriminator 1 view .LVU3800 12122 03ec 2880 strh r0, [r5] @ movhi 487:Src/main.c **** Long_Data[12] = temp16; 12123 .loc 1 487 7 is_stmt 1 view .LVU3801 487:Src/main.c **** Long_Data[12] = temp16; 12124 .loc 1 487 16 is_stmt 0 view .LVU3802 12125 03ee 0420 movs r0, #4 12126 03f0 FFF7FEFF bl Get_ADC 12127 .LVL1066: 487:Src/main.c **** Long_Data[12] = temp16; 12128 .loc 1 487 14 discriminator 1 view .LVU3803 12129 03f4 2880 strh r0, [r5] @ movhi 488:Src/main.c **** temp16 = Get_ADC(5); 12130 .loc 1 488 7 is_stmt 1 view .LVU3804 488:Src/main.c **** temp16 = Get_ADC(5); 12131 .loc 1 488 21 is_stmt 0 view .LVU3805 12132 03f6 2083 strh r0, [r4, #24] @ movhi 489:Src/main.c **** 12133 .loc 1 489 7 is_stmt 1 view .LVU3806 489:Src/main.c **** 12134 .loc 1 489 16 is_stmt 0 view .LVU3807 12135 03f8 0520 movs r0, #5 12136 03fa FFF7FEFF bl Get_ADC 12137 .LVL1067: 489:Src/main.c **** 12138 .loc 1 489 14 discriminator 1 view .LVU3808 12139 03fe 2880 strh r0, [r5] @ movhi 492:Src/main.c **** Long_Data[3] = (TO6_stop)&0xffff; 12140 .loc 1 492 7 is_stmt 1 view .LVU3809 492:Src/main.c **** Long_Data[3] = (TO6_stop)&0xffff; 12141 .loc 1 492 16 is_stmt 0 view .LVU3810 12142 0400 774B ldr r3, .L763+28 12143 0402 1B68 ldr r3, [r3] 12144 0404 774A ldr r2, .L763+32 12145 0406 1360 str r3, [r2] 493:Src/main.c **** Long_Data[4] = (TO6_stop>>16)&0xffff; 12146 .loc 1 493 7 is_stmt 1 view .LVU3811 493:Src/main.c **** Long_Data[4] = (TO6_stop>>16)&0xffff; 12147 .loc 1 493 20 is_stmt 0 view .LVU3812 12148 0408 E380 strh r3, [r4, #6] @ movhi 494:Src/main.c **** 12149 .loc 1 494 7 is_stmt 1 view .LVU3813 494:Src/main.c **** 12150 .loc 1 494 31 is_stmt 0 view .LVU3814 ARM GAS /tmp/ccLSPxIe.s page 632 12151 040a 1B0C lsrs r3, r3, #16 494:Src/main.c **** 12152 .loc 1 494 20 view .LVU3815 12153 040c 2381 strh r3, [r4, #8] @ movhi 497:Src/main.c **** 12154 .loc 1 497 7 is_stmt 1 view .LVU3816 497:Src/main.c **** 12155 .loc 1 497 31 is_stmt 0 view .LVU3817 12156 040e 3B88 ldrh r3, [r7] 497:Src/main.c **** 12157 .loc 1 497 20 view .LVU3818 12158 0410 6381 strh r3, [r4, #10] @ movhi 500:Src/main.c **** 12159 .loc 1 500 7 is_stmt 1 view .LVU3819 500:Src/main.c **** 12160 .loc 1 500 31 is_stmt 0 view .LVU3820 12161 0412 3388 ldrh r3, [r6] 500:Src/main.c **** 12162 .loc 1 500 20 view .LVU3821 12163 0414 A381 strh r3, [r4, #12] @ movhi 502:Src/main.c **** { 12164 .loc 1 502 7 is_stmt 1 view .LVU3822 502:Src/main.c **** { 12165 .loc 1 502 21 is_stmt 0 view .LVU3823 12166 0416 744B ldr r3, .L763+36 12167 0418 DB7A ldrb r3, [r3, #11] @ zero_extendqisi2 502:Src/main.c **** { 12168 .loc 1 502 10 view .LVU3824 12169 041a 012B cmp r3, #1 12170 041c 03D0 beq .L748 12171 .L674: 509:Src/main.c **** } 12172 .loc 1 509 7 is_stmt 1 view .LVU3825 509:Src/main.c **** } 12173 .loc 1 509 21 is_stmt 0 view .LVU3826 12174 041e 734B ldr r3, .L763+40 12175 0420 0722 movs r2, #7 12176 0422 1A70 strb r2, [r3] 12177 0424 6DE6 b .L652 12178 .L748: 504:Src/main.c **** Long_Data[DL_16-1] = CS_result; 12179 .loc 1 504 8 is_stmt 1 view .LVU3827 504:Src/main.c **** Long_Data[DL_16-1] = CS_result; 12180 .loc 1 504 20 is_stmt 0 view .LVU3828 12181 0426 0234 adds r4, r4, #2 12182 0428 0D21 movs r1, #13 12183 042a 2046 mov r0, r4 12184 042c FFF7FEFF bl CalculateChecksum 12185 .LVL1068: 12186 0430 0346 mov r3, r0 504:Src/main.c **** Long_Data[DL_16-1] = CS_result; 12187 .loc 1 504 18 discriminator 1 view .LVU3829 12188 0432 6F4A ldr r2, .L763+44 12189 0434 1080 strh r0, [r2] @ movhi 505:Src/main.c **** temp16 = SD_SAVE(&Long_Data[0]); 12190 .loc 1 505 8 is_stmt 1 view .LVU3830 505:Src/main.c **** temp16 = SD_SAVE(&Long_Data[0]); ARM GAS /tmp/ccLSPxIe.s page 633 12191 .loc 1 505 27 is_stmt 0 view .LVU3831 12192 0436 A01E subs r0, r4, #2 12193 0438 8383 strh r3, [r0, #28] @ movhi 506:Src/main.c **** State_Data[0]|=temp16&0xff; 12194 .loc 1 506 8 is_stmt 1 view .LVU3832 506:Src/main.c **** State_Data[0]|=temp16&0xff; 12195 .loc 1 506 17 is_stmt 0 view .LVU3833 12196 043a FFF7FEFF bl SD_SAVE 12197 .LVL1069: 12198 043e 0346 mov r3, r0 506:Src/main.c **** State_Data[0]|=temp16&0xff; 12199 .loc 1 506 15 discriminator 1 view .LVU3834 12200 0440 2880 strh r0, [r5] @ movhi 507:Src/main.c **** } 12201 .loc 1 507 8 is_stmt 1 view .LVU3835 507:Src/main.c **** } 12202 .loc 1 507 18 is_stmt 0 view .LVU3836 12203 0442 6C49 ldr r1, .L763+48 12204 0444 0A78 ldrb r2, [r1] @ zero_extendqisi2 507:Src/main.c **** } 12205 .loc 1 507 21 view .LVU3837 12206 0446 1343 orrs r3, r3, r2 12207 0448 0B70 strb r3, [r1] 12208 044a E8E7 b .L674 12209 .L659: 513:Src/main.c **** { 12210 .loc 1 513 6 is_stmt 1 view .LVU3838 513:Src/main.c **** { 12211 .loc 1 513 10 is_stmt 0 view .LVU3839 12212 044c 6A4C ldr r4, .L763+52 12213 044e 0321 movs r1, #3 12214 0450 2046 mov r0, r4 12215 0452 FFF7FEFF bl CalculateChecksum 12216 .LVL1070: 513:Src/main.c **** { 12217 .loc 1 513 69 discriminator 1 view .LVU3840 12218 0456 E388 ldrh r3, [r4, #6] 513:Src/main.c **** { 12219 .loc 1 513 9 discriminator 1 view .LVU3841 12220 0458 9842 cmp r0, r3 12221 045a 0CD0 beq .L749 588:Src/main.c **** } 12222 .loc 1 588 7 is_stmt 1 view .LVU3842 588:Src/main.c **** } 12223 .loc 1 588 17 is_stmt 0 view .LVU3843 12224 045c 654A ldr r2, .L763+48 12225 045e 1378 ldrb r3, [r2] @ zero_extendqisi2 588:Src/main.c **** } 12226 .loc 1 588 21 view .LVU3844 12227 0460 43F00403 orr r3, r3, #4 12228 0464 1370 strb r3, [r2] 12229 .L678: 590:Src/main.c **** CPU_state = CPU_state_old; 12230 .loc 1 590 6 is_stmt 1 view .LVU3845 590:Src/main.c **** CPU_state = CPU_state_old; 12231 .loc 1 590 32 is_stmt 0 view .LVU3846 12232 0466 654B ldr r3, .L763+56 ARM GAS /tmp/ccLSPxIe.s page 634 12233 0468 0122 movs r2, #1 12234 046a 1A70 strb r2, [r3] 591:Src/main.c **** break; 12235 .loc 1 591 6 is_stmt 1 view .LVU3847 591:Src/main.c **** break; 12236 .loc 1 591 16 is_stmt 0 view .LVU3848 12237 046c 5F4B ldr r3, .L763+40 12238 046e 1A78 ldrb r2, [r3] @ zero_extendqisi2 12239 0470 634B ldr r3, .L763+60 12240 0472 1A70 strb r2, [r3] 592:Src/main.c **** case AD9833_CMD://11 - Configure AD9833 triangle output 12241 .loc 1 592 5 is_stmt 1 view .LVU3849 12242 0474 45E6 b .L652 12243 .L749: 12244 .LBB711: 515:Src/main.c **** uint16_t param0 = COMMAND[1]; 12245 .loc 1 515 7 view .LVU3850 515:Src/main.c **** uint16_t param0 = COMMAND[1]; 12246 .loc 1 515 16 is_stmt 0 view .LVU3851 12247 0476 2388 ldrh r3, [r4] 12248 .LVL1071: 516:Src/main.c **** uint16_t param1 = COMMAND[2]; 12249 .loc 1 516 7 is_stmt 1 view .LVU3852 516:Src/main.c **** uint16_t param1 = COMMAND[2]; 12250 .loc 1 516 16 is_stmt 0 view .LVU3853 12251 0478 6188 ldrh r1, [r4, #2] 12252 .LVL1072: 517:Src/main.c **** uint8_t enable = (flags & AD9102_FLAG_ENABLE) ? 1u : 0u; 12253 .loc 1 517 7 is_stmt 1 view .LVU3854 517:Src/main.c **** uint8_t enable = (flags & AD9102_FLAG_ENABLE) ? 1u : 0u; 12254 .loc 1 517 16 is_stmt 0 view .LVU3855 12255 047a A488 ldrh r4, [r4, #4] 12256 .LVL1073: 518:Src/main.c **** uint8_t triangle = (flags & AD9102_FLAG_TRIANGLE) ? 1u : 0u; 12257 .loc 1 518 7 is_stmt 1 view .LVU3856 518:Src/main.c **** uint8_t triangle = (flags & AD9102_FLAG_TRIANGLE) ? 1u : 0u; 12258 .loc 1 518 15 is_stmt 0 view .LVU3857 12259 047c 03F00106 and r6, r3, #1 12260 .LVL1074: 519:Src/main.c **** uint8_t sram_mode = (flags & AD9102_FLAG_SRAM) ? 1u : 0u; 12261 .loc 1 519 7 is_stmt 1 view .LVU3858 519:Src/main.c **** uint8_t sram_mode = (flags & AD9102_FLAG_SRAM) ? 1u : 0u; 12262 .loc 1 519 15 is_stmt 0 view .LVU3859 12263 0480 C3F34005 ubfx r5, r3, #1, #1 12264 .LVL1075: 520:Src/main.c **** 12265 .loc 1 520 7 is_stmt 1 view .LVU3860 522:Src/main.c **** { 12266 .loc 1 522 7 view .LVU3861 522:Src/main.c **** { 12267 .loc 1 522 10 is_stmt 0 view .LVU3862 12268 0484 13F0040F tst r3, #4 12269 0488 1FD0 beq .L676 12270 .LBB712: 524:Src/main.c **** uint16_t samples; 12271 .loc 1 524 8 is_stmt 1 view .LVU3863 12272 .LVL1076: ARM GAS /tmp/ccLSPxIe.s page 635 525:Src/main.c **** uint8_t hold; 12273 .loc 1 525 8 view .LVU3864 526:Src/main.c **** uint16_t amplitude; 12274 .loc 1 526 8 view .LVU3865 527:Src/main.c **** 12275 .loc 1 527 8 view .LVU3866 529:Src/main.c **** { 12276 .loc 1 529 8 view .LVU3867 529:Src/main.c **** { 12277 .loc 1 529 11 is_stmt 0 view .LVU3868 12278 048a 13F0080F tst r3, #8 12279 048e 1AD1 bne .L733 537:Src/main.c **** hold = (uint8_t)(param1 & 0x0Fu); 12280 .loc 1 537 9 is_stmt 1 view .LVU3869 12281 .LVL1077: 538:Src/main.c **** amplitude = AD9102_SRAM_AMP_DEFAULT; 12282 .loc 1 538 9 view .LVU3870 538:Src/main.c **** amplitude = AD9102_SRAM_AMP_DEFAULT; 12283 .loc 1 538 14 is_stmt 0 view .LVU3871 12284 0490 04F00F07 and r7, r4, #15 12285 .LVL1078: 539:Src/main.c **** } 12286 .loc 1 539 9 is_stmt 1 view .LVU3872 537:Src/main.c **** hold = (uint8_t)(param1 & 0x0Fu); 12287 .loc 1 537 17 is_stmt 0 view .LVU3873 12288 0494 0C46 mov r4, r1 12289 .LVL1079: 539:Src/main.c **** } 12290 .loc 1 539 19 view .LVU3874 12291 0496 41F6FF71 movw r1, #8191 12292 .LVL1080: 12293 .L677: 542:Src/main.c **** State_Data[1] = (uint8_t)(pat_status & 0x00FFu); 12294 .loc 1 542 8 is_stmt 1 view .LVU3875 542:Src/main.c **** State_Data[1] = (uint8_t)(pat_status & 0x00FFu); 12295 .loc 1 542 30 is_stmt 0 view .LVU3876 12296 049a 0091 str r1, [sp] 12297 049c 2B46 mov r3, r5 12298 .LVL1081: 542:Src/main.c **** State_Data[1] = (uint8_t)(pat_status & 0x00FFu); 12299 .loc 1 542 30 view .LVU3877 12300 049e 3A46 mov r2, r7 12301 04a0 2146 mov r1, r4 12302 .LVL1082: 542:Src/main.c **** State_Data[1] = (uint8_t)(pat_status & 0x00FFu); 12303 .loc 1 542 30 view .LVU3878 12304 04a2 3046 mov r0, r6 12305 04a4 FFF7FEFF bl AD9102_ApplySram 12306 .LVL1083: 543:Src/main.c **** if (AD9102_CheckFlagsSram(pat_status, enable, samples, hold)) 12307 .loc 1 543 8 is_stmt 1 view .LVU3879 543:Src/main.c **** if (AD9102_CheckFlagsSram(pat_status, enable, samples, hold)) 12308 .loc 1 543 22 is_stmt 0 view .LVU3880 12309 04a8 524B ldr r3, .L763+48 12310 04aa 5870 strb r0, [r3, #1] 544:Src/main.c **** { 12311 .loc 1 544 8 is_stmt 1 view .LVU3881 ARM GAS /tmp/ccLSPxIe.s page 636 544:Src/main.c **** { 12312 .loc 1 544 12 is_stmt 0 view .LVU3882 12313 04ac 3B46 mov r3, r7 12314 04ae 2246 mov r2, r4 12315 04b0 3146 mov r1, r6 12316 04b2 FFF7FEFF bl AD9102_CheckFlagsSram 12317 .LVL1084: 544:Src/main.c **** { 12318 .loc 1 544 11 discriminator 1 view .LVU3883 12319 04b6 0028 cmp r0, #0 12320 04b8 D5D0 beq .L678 546:Src/main.c **** } 12321 .loc 1 546 9 is_stmt 1 view .LVU3884 546:Src/main.c **** } 12322 .loc 1 546 19 is_stmt 0 view .LVU3885 12323 04ba 4E4A ldr r2, .L763+48 12324 04bc 1378 ldrb r3, [r2] @ zero_extendqisi2 546:Src/main.c **** } 12325 .loc 1 546 23 view .LVU3886 12326 04be 63F07F03 orn r3, r3, #127 12327 04c2 1370 strb r3, [r2] 12328 04c4 CFE7 b .L678 12329 .LVL1085: 12330 .L733: 533:Src/main.c **** } 12331 .loc 1 533 14 view .LVU3887 12332 04c6 0127 movs r7, #1 12333 04c8 E7E7 b .L677 12334 .LVL1086: 12335 .L676: 533:Src/main.c **** } 12336 .loc 1 533 14 view .LVU3888 12337 .LBE712: 12338 .LBB713: 551:Src/main.c **** uint8_t saw_step = (uint8_t)(param0 & 0x00FFu); 12339 .loc 1 551 8 is_stmt 1 view .LVU3889 551:Src/main.c **** uint8_t saw_step = (uint8_t)(param0 & 0x00FFu); 12340 .loc 1 551 16 is_stmt 0 view .LVU3890 12341 04ca 05B1 cbz r5, .L679 551:Src/main.c **** uint8_t saw_step = (uint8_t)(param0 & 0x00FFu); 12342 .loc 1 551 16 discriminator 1 view .LVU3891 12343 04cc 0225 movs r5, #2 12344 .LVL1087: 12345 .L679: 552:Src/main.c **** uint8_t pat_base = (uint8_t)((param0 >> 8) & 0x0Fu); 12346 .loc 1 552 8 is_stmt 1 view .LVU3892 552:Src/main.c **** uint8_t pat_base = (uint8_t)((param0 >> 8) & 0x0Fu); 12347 .loc 1 552 16 is_stmt 0 view .LVU3893 12348 04ce CFB2 uxtb r7, r1 12349 .LVL1088: 553:Src/main.c **** uint16_t pat_period = param1; 12350 .loc 1 553 8 is_stmt 1 view .LVU3894 553:Src/main.c **** uint16_t pat_period = param1; 12351 .loc 1 553 16 is_stmt 0 view .LVU3895 12352 04d0 C1F30328 ubfx r8, r1, #8, #4 12353 .LVL1089: 554:Src/main.c **** ARM GAS /tmp/ccLSPxIe.s page 637 12354 .loc 1 554 8 is_stmt 1 view .LVU3896 556:Src/main.c **** { 12355 .loc 1 556 8 view .LVU3897 556:Src/main.c **** { 12356 .loc 1 556 11 is_stmt 0 view .LVU3898 12357 04d4 2143 orrs r1, r1, r4 12358 .LVL1090: 556:Src/main.c **** { 12359 .loc 1 556 11 view .LVU3899 12360 04d6 09D0 beq .L734 564:Src/main.c **** { 12361 .loc 1 564 9 is_stmt 1 view .LVU3900 564:Src/main.c **** { 12362 .loc 1 564 12 is_stmt 0 view .LVU3901 12363 04d8 1FB1 cbz r7, .L735 568:Src/main.c **** { 12364 .loc 1 568 14 is_stmt 1 view .LVU3902 568:Src/main.c **** { 12365 .loc 1 568 17 is_stmt 0 view .LVU3903 12366 04da 3F2F cmp r7, #63 12367 04dc 02D9 bls .L681 570:Src/main.c **** } 12368 .loc 1 570 19 view .LVU3904 12369 04de 3F27 movs r7, #63 12370 .LVL1091: 570:Src/main.c **** } 12371 .loc 1 570 19 view .LVU3905 12372 04e0 00E0 b .L681 12373 .LVL1092: 12374 .L735: 566:Src/main.c **** } 12375 .loc 1 566 19 view .LVU3906 12376 04e2 0127 movs r7, #1 12377 .LVL1093: 12378 .L681: 572:Src/main.c **** { 12379 .loc 1 572 9 is_stmt 1 view .LVU3907 572:Src/main.c **** { 12380 .loc 1 572 12 is_stmt 0 view .LVU3908 12381 04e4 3CB9 cbnz r4, .L680 574:Src/main.c **** } 12382 .loc 1 574 21 view .LVU3909 12383 04e6 4FF6FF74 movw r4, #65535 12384 .LVL1094: 574:Src/main.c **** } 12385 .loc 1 574 21 view .LVU3910 12386 04ea 04E0 b .L680 12387 .LVL1095: 12388 .L734: 560:Src/main.c **** } 12389 .loc 1 560 20 view .LVU3911 12390 04ec 4FF6FF74 movw r4, #65535 12391 .LVL1096: 559:Src/main.c **** pat_period = AD9102_PAT_PERIOD_DEFAULT; 12392 .loc 1 559 18 view .LVU3912 12393 04f0 4FF00208 mov r8, #2 12394 .LVL1097: ARM GAS /tmp/ccLSPxIe.s page 638 558:Src/main.c **** pat_base = AD9102_PAT_PERIOD_BASE_DEFAULT; 12395 .loc 1 558 18 view .LVU3913 12396 04f4 0127 movs r7, #1 12397 .LVL1098: 12398 .L680: 578:Src/main.c **** State_Data[1] = (uint8_t)(pat_status & 0x00FFu); 12399 .loc 1 578 8 is_stmt 1 view .LVU3914 578:Src/main.c **** State_Data[1] = (uint8_t)(pat_status & 0x00FFu); 12400 .loc 1 578 30 is_stmt 0 view .LVU3915 12401 04f6 0094 str r4, [sp] 12402 04f8 4346 mov r3, r8 12403 .LVL1099: 578:Src/main.c **** State_Data[1] = (uint8_t)(pat_status & 0x00FFu); 12404 .loc 1 578 30 view .LVU3916 12405 04fa 3A46 mov r2, r7 12406 04fc 3146 mov r1, r6 12407 04fe 2846 mov r0, r5 12408 0500 FFF7FEFF bl AD9102_Apply 12409 .LVL1100: 579:Src/main.c **** if (AD9102_CheckFlags(pat_status, enable, saw_type, saw_step, pat_base, pat_period)) 12410 .loc 1 579 8 is_stmt 1 view .LVU3917 579:Src/main.c **** if (AD9102_CheckFlags(pat_status, enable, saw_type, saw_step, pat_base, pat_period)) 12411 .loc 1 579 22 is_stmt 0 view .LVU3918 12412 0504 3B4B ldr r3, .L763+48 12413 0506 5870 strb r0, [r3, #1] 580:Src/main.c **** { 12414 .loc 1 580 8 is_stmt 1 view .LVU3919 580:Src/main.c **** { 12415 .loc 1 580 12 is_stmt 0 view .LVU3920 12416 0508 0194 str r4, [sp, #4] 12417 050a CDF80080 str r8, [sp] 12418 050e 3B46 mov r3, r7 12419 0510 2A46 mov r2, r5 12420 0512 3146 mov r1, r6 12421 0514 FFF7FEFF bl AD9102_CheckFlags 12422 .LVL1101: 580:Src/main.c **** { 12423 .loc 1 580 11 discriminator 1 view .LVU3921 12424 0518 0028 cmp r0, #0 12425 051a A4D0 beq .L678 582:Src/main.c **** } 12426 .loc 1 582 9 is_stmt 1 view .LVU3922 582:Src/main.c **** } 12427 .loc 1 582 19 is_stmt 0 view .LVU3923 12428 051c 354A ldr r2, .L763+48 12429 051e 1378 ldrb r3, [r2] @ zero_extendqisi2 582:Src/main.c **** } 12430 .loc 1 582 23 view .LVU3924 12431 0520 63F07F03 orn r3, r3, #127 12432 0524 1370 strb r3, [r2] 12433 0526 9EE7 b .L678 12434 .LVL1102: 12435 .L658: 582:Src/main.c **** } 12436 .loc 1 582 23 view .LVU3925 12437 .LBE713: 12438 .LBE711: ARM GAS /tmp/ccLSPxIe.s page 639 594:Src/main.c **** if (CalculateChecksum(COMMAND, AD9833_CMD_WORDS - 1) == COMMAND[AD9833_CMD_WORDS - 1]) 12439 .loc 1 594 6 is_stmt 1 view .LVU3926 594:Src/main.c **** if (CalculateChecksum(COMMAND, AD9833_CMD_WORDS - 1) == COMMAND[AD9833_CMD_WORDS - 1]) 12440 .loc 1 594 20 is_stmt 0 view .LVU3927 12441 0528 324B ldr r3, .L763+48 12442 052a 0022 movs r2, #0 12443 052c 5A70 strb r2, [r3, #1] 595:Src/main.c **** { 12444 .loc 1 595 6 is_stmt 1 view .LVU3928 595:Src/main.c **** { 12445 .loc 1 595 10 is_stmt 0 view .LVU3929 12446 052e 324C ldr r4, .L763+52 12447 0530 0321 movs r1, #3 12448 0532 2046 mov r0, r4 12449 0534 FFF7FEFF bl CalculateChecksum 12450 .LVL1103: 595:Src/main.c **** { 12451 .loc 1 595 69 discriminator 1 view .LVU3930 12452 0538 E388 ldrh r3, [r4, #6] 595:Src/main.c **** { 12453 .loc 1 595 9 discriminator 1 view .LVU3931 12454 053a 9842 cmp r0, r3 12455 053c 0CD0 beq .L750 608:Src/main.c **** } 12456 .loc 1 608 7 is_stmt 1 view .LVU3932 608:Src/main.c **** } 12457 .loc 1 608 17 is_stmt 0 view .LVU3933 12458 053e 2D4A ldr r2, .L763+48 12459 0540 1378 ldrb r3, [r2] @ zero_extendqisi2 608:Src/main.c **** } 12460 .loc 1 608 21 view .LVU3934 12461 0542 43F00403 orr r3, r3, #4 12462 0546 1370 strb r3, [r2] 12463 .L683: 610:Src/main.c **** CPU_state = CPU_state_old; 12464 .loc 1 610 6 is_stmt 1 view .LVU3935 610:Src/main.c **** CPU_state = CPU_state_old; 12465 .loc 1 610 32 is_stmt 0 view .LVU3936 12466 0548 2C4B ldr r3, .L763+56 12467 054a 0122 movs r2, #1 12468 054c 1A70 strb r2, [r3] 611:Src/main.c **** break; 12469 .loc 1 611 6 is_stmt 1 view .LVU3937 611:Src/main.c **** break; 12470 .loc 1 611 16 is_stmt 0 view .LVU3938 12471 054e 274B ldr r3, .L763+40 12472 0550 1A78 ldrb r2, [r3] @ zero_extendqisi2 12473 0552 2B4B ldr r3, .L763+60 12474 0554 1A70 strb r2, [r3] 612:Src/main.c **** case DS1809_CMD://12 - Pulse DS1809 UC/DC controls 12475 .loc 1 612 5 is_stmt 1 view .LVU3939 12476 0556 D4E5 b .L652 12477 .L750: 12478 .LBB714: 597:Src/main.c **** uint16_t lsw = (uint16_t)(COMMAND[1] & 0x3FFFu); 12479 .loc 1 597 7 view .LVU3940 597:Src/main.c **** uint16_t lsw = (uint16_t)(COMMAND[1] & 0x3FFFu); ARM GAS /tmp/ccLSPxIe.s page 640 12480 .loc 1 597 16 is_stmt 0 view .LVU3941 12481 0558 2088 ldrh r0, [r4] 12482 .LVL1104: 598:Src/main.c **** uint16_t msw = (uint16_t)(COMMAND[2] & 0x3FFFu); 12483 .loc 1 598 7 is_stmt 1 view .LVU3942 598:Src/main.c **** uint16_t msw = (uint16_t)(COMMAND[2] & 0x3FFFu); 12484 .loc 1 598 40 is_stmt 0 view .LVU3943 12485 055a 6388 ldrh r3, [r4, #2] 598:Src/main.c **** uint16_t msw = (uint16_t)(COMMAND[2] & 0x3FFFu); 12486 .loc 1 598 16 view .LVU3944 12487 055c C3F30D03 ubfx r3, r3, #0, #14 12488 .LVL1105: 599:Src/main.c **** uint8_t enable = (flags & AD9833_FLAG_ENABLE) ? 1u : 0u; 12489 .loc 1 599 7 is_stmt 1 view .LVU3945 599:Src/main.c **** uint8_t enable = (flags & AD9833_FLAG_ENABLE) ? 1u : 0u; 12490 .loc 1 599 40 is_stmt 0 view .LVU3946 12491 0560 A288 ldrh r2, [r4, #4] 599:Src/main.c **** uint8_t enable = (flags & AD9833_FLAG_ENABLE) ? 1u : 0u; 12492 .loc 1 599 16 view .LVU3947 12493 0562 C2F30D02 ubfx r2, r2, #0, #14 12494 .LVL1106: 600:Src/main.c **** uint8_t triangle = (flags & AD9833_FLAG_TRIANGLE) ? 1u : 0u; 12495 .loc 1 600 7 is_stmt 1 view .LVU3948 601:Src/main.c **** uint32_t freq_word = ((uint32_t)msw << 14) | (uint32_t)lsw; 12496 .loc 1 601 7 view .LVU3949 602:Src/main.c **** 12497 .loc 1 602 7 view .LVU3950 604:Src/main.c **** } 12498 .loc 1 604 7 view .LVU3951 12499 0566 43EA8232 orr r2, r3, r2, lsl #14 12500 .LVL1107: 604:Src/main.c **** } 12501 .loc 1 604 7 is_stmt 0 view .LVU3952 12502 056a C0F34001 ubfx r1, r0, #1, #1 12503 056e 00F00100 and r0, r0, #1 12504 .LVL1108: 604:Src/main.c **** } 12505 .loc 1 604 7 view .LVU3953 12506 0572 FFF7FEFF bl AD9833_Apply 12507 .LVL1109: 604:Src/main.c **** } 12508 .loc 1 604 7 view .LVU3954 12509 .LBE714: 12510 0576 E7E7 b .L683 12511 .LVL1110: 12512 .L657: 614:Src/main.c **** { 12513 .loc 1 614 6 is_stmt 1 view .LVU3955 614:Src/main.c **** { 12514 .loc 1 614 10 is_stmt 0 view .LVU3956 12515 0578 1F4C ldr r4, .L763+52 12516 057a 0321 movs r1, #3 12517 057c 2046 mov r0, r4 12518 057e FFF7FEFF bl CalculateChecksum 12519 .LVL1111: 614:Src/main.c **** { 12520 .loc 1 614 69 discriminator 1 view .LVU3957 ARM GAS /tmp/ccLSPxIe.s page 641 12521 0582 E388 ldrh r3, [r4, #6] 614:Src/main.c **** { 12522 .loc 1 614 9 discriminator 1 view .LVU3958 12523 0584 9842 cmp r0, r3 12524 0586 0CD0 beq .L751 649:Src/main.c **** } 12525 .loc 1 649 7 is_stmt 1 view .LVU3959 649:Src/main.c **** } 12526 .loc 1 649 17 is_stmt 0 view .LVU3960 12527 0588 1A4A ldr r2, .L763+48 12528 058a 1378 ldrb r3, [r2] @ zero_extendqisi2 649:Src/main.c **** } 12529 .loc 1 649 21 view .LVU3961 12530 058c 43F00403 orr r3, r3, #4 12531 0590 1370 strb r3, [r2] 12532 .L686: 651:Src/main.c **** CPU_state = CPU_state_old; 12533 .loc 1 651 6 is_stmt 1 view .LVU3962 651:Src/main.c **** CPU_state = CPU_state_old; 12534 .loc 1 651 32 is_stmt 0 view .LVU3963 12535 0592 1A4B ldr r3, .L763+56 12536 0594 0122 movs r2, #1 12537 0596 1A70 strb r2, [r3] 652:Src/main.c **** break; 12538 .loc 1 652 6 is_stmt 1 view .LVU3964 652:Src/main.c **** break; 12539 .loc 1 652 16 is_stmt 0 view .LVU3965 12540 0598 144B ldr r3, .L763+40 12541 059a 1A78 ldrb r2, [r3] @ zero_extendqisi2 12542 059c 184B ldr r3, .L763+60 12543 059e 1A70 strb r2, [r3] 653:Src/main.c **** case STM32_DAC_CMD://13 - Set STM32 internal DAC (PA4) 12544 .loc 1 653 5 is_stmt 1 view .LVU3966 12545 05a0 AFE5 b .L652 12546 .L751: 12547 .LBB715: 616:Src/main.c **** uint16_t count = COMMAND[1]; 12548 .loc 1 616 7 view .LVU3967 616:Src/main.c **** uint16_t count = COMMAND[1]; 12549 .loc 1 616 16 is_stmt 0 view .LVU3968 12550 05a2 2346 mov r3, r4 12551 05a4 2488 ldrh r4, [r4] 12552 .LVL1112: 617:Src/main.c **** uint16_t pulse_ms = COMMAND[2]; 12553 .loc 1 617 7 is_stmt 1 view .LVU3969 617:Src/main.c **** uint16_t pulse_ms = COMMAND[2]; 12554 .loc 1 617 16 is_stmt 0 view .LVU3970 12555 05a6 5A88 ldrh r2, [r3, #2] 12556 .LVL1113: 618:Src/main.c **** uint8_t uc = (flags & DS1809_FLAG_UC) ? 1u : 0u; 12557 .loc 1 618 7 is_stmt 1 view .LVU3971 618:Src/main.c **** uint8_t uc = (flags & DS1809_FLAG_UC) ? 1u : 0u; 12558 .loc 1 618 16 is_stmt 0 view .LVU3972 12559 05a8 9B88 ldrh r3, [r3, #4] 12560 .LVL1114: 619:Src/main.c **** uint8_t dc = (flags & DS1809_FLAG_DC) ? 1u : 0u; 12561 .loc 1 619 7 is_stmt 1 view .LVU3973 ARM GAS /tmp/ccLSPxIe.s page 642 620:Src/main.c **** 12562 .loc 1 620 7 view .LVU3974 620:Src/main.c **** 12563 .loc 1 620 15 is_stmt 0 view .LVU3975 12564 05aa C4F34001 ubfx r1, r4, #1, #1 12565 .LVL1115: 622:Src/main.c **** { 12566 .loc 1 622 7 is_stmt 1 view .LVU3976 622:Src/main.c **** { 12567 .loc 1 622 11 is_stmt 0 view .LVU3977 12568 05ae 04F00100 and r0, r4, #1 622:Src/main.c **** { 12569 .loc 1 622 10 view .LVU3978 12570 05b2 0C42 tst r4, r1 12571 05b4 2AD0 beq .L685 624:Src/main.c **** } 12572 .loc 1 624 8 is_stmt 1 view .LVU3979 624:Src/main.c **** } 12573 .loc 1 624 18 is_stmt 0 view .LVU3980 12574 05b6 0F4A ldr r2, .L763+48 12575 .LVL1116: 624:Src/main.c **** } 12576 .loc 1 624 18 view .LVU3981 12577 05b8 1378 ldrb r3, [r2] @ zero_extendqisi2 12578 .LVL1117: 624:Src/main.c **** } 12579 .loc 1 624 22 view .LVU3982 12580 05ba 43F00403 orr r3, r3, #4 12581 05be 1370 strb r3, [r2] 12582 05c0 E7E7 b .L686 12583 .L764: 12584 05c2 00BF .align 2 12585 .L763: 12586 05c4 00000000 .word task 12587 05c8 00000000 .word TO7 12588 05cc 00000000 .word TO7_before 12589 05d0 00000000 .word LD1_param 12590 05d4 00000000 .word LD2_param 12591 05d8 00000000 .word temp16 12592 05dc 00000000 .word Long_Data 12593 05e0 00000000 .word TO6 12594 05e4 00000000 .word TO6_stop 12595 05e8 00000000 .word Curr_setup 12596 05ec 00000000 .word CPU_state_old 12597 05f0 00000000 .word CS_result 12598 05f4 00000000 .word State_Data 12599 05f8 00000000 .word COMMAND 12600 05fc 00000000 .word UART_transmission_request 12601 0600 00000000 .word CPU_state 12602 0604 00000000 .word LD1_curr_setup 12603 0608 00000000 .word LD2_curr_setup 12604 .LVL1118: 12605 .L685: 628:Src/main.c **** { 12606 .loc 1 628 8 is_stmt 1 view .LVU3983 628:Src/main.c **** { 12607 .loc 1 628 11 is_stmt 0 view .LVU3984 ARM GAS /tmp/ccLSPxIe.s page 643 12608 060c 1AB1 cbz r2, .L738 632:Src/main.c **** { 12609 .loc 1 632 8 is_stmt 1 view .LVU3985 632:Src/main.c **** { 12610 .loc 1 632 11 is_stmt 0 view .LVU3986 12611 060e 402A cmp r2, #64 12612 0610 02D9 bls .L687 634:Src/main.c **** } 12613 .loc 1 634 15 view .LVU3987 12614 0612 4022 movs r2, #64 12615 .LVL1119: 634:Src/main.c **** } 12616 .loc 1 634 15 view .LVU3988 12617 0614 00E0 b .L687 12618 .LVL1120: 12619 .L738: 630:Src/main.c **** } 12620 .loc 1 630 15 view .LVU3989 12621 0616 0122 movs r2, #1 12622 .LVL1121: 12623 .L687: 636:Src/main.c **** { 12624 .loc 1 636 8 is_stmt 1 view .LVU3990 636:Src/main.c **** { 12625 .loc 1 636 11 is_stmt 0 view .LVU3991 12626 0618 2BB1 cbz r3, .L740 640:Src/main.c **** { 12627 .loc 1 640 8 is_stmt 1 view .LVU3992 640:Src/main.c **** { 12628 .loc 1 640 11 is_stmt 0 view .LVU3993 12629 061a B3F5FA7F cmp r3, #500 12630 061e 03D9 bls .L688 642:Src/main.c **** } 12631 .loc 1 642 18 view .LVU3994 12632 0620 4FF4FA73 mov r3, #500 12633 .LVL1122: 642:Src/main.c **** } 12634 .loc 1 642 18 view .LVU3995 12635 0624 00E0 b .L688 12636 .LVL1123: 12637 .L740: 638:Src/main.c **** } 12638 .loc 1 638 18 view .LVU3996 12639 0626 0223 movs r3, #2 12640 .LVL1124: 12641 .L688: 644:Src/main.c **** } 12642 .loc 1 644 8 is_stmt 1 view .LVU3997 12643 0628 FFF7FEFF bl DS1809_Pulse 12644 .LVL1125: 644:Src/main.c **** } 12645 .loc 1 644 8 is_stmt 0 view .LVU3998 12646 062c B1E7 b .L686 12647 .LVL1126: 12648 .L656: 644:Src/main.c **** } 12649 .loc 1 644 8 view .LVU3999 ARM GAS /tmp/ccLSPxIe.s page 644 12650 .LBE715: 655:Src/main.c **** { 12651 .loc 1 655 6 is_stmt 1 view .LVU4000 655:Src/main.c **** { 12652 .loc 1 655 10 is_stmt 0 view .LVU4001 12653 062e 7C4C ldr r4, .L765 12654 0630 0321 movs r1, #3 12655 0632 2046 mov r0, r4 12656 0634 FFF7FEFF bl CalculateChecksum 12657 .LVL1127: 655:Src/main.c **** { 12658 .loc 1 655 72 discriminator 1 view .LVU4002 12659 0638 E388 ldrh r3, [r4, #6] 655:Src/main.c **** { 12660 .loc 1 655 9 discriminator 1 view .LVU4003 12661 063a 9842 cmp r0, r3 12662 063c 0CD0 beq .L752 664:Src/main.c **** } 12663 .loc 1 664 7 is_stmt 1 view .LVU4004 664:Src/main.c **** } 12664 .loc 1 664 17 is_stmt 0 view .LVU4005 12665 063e 794A ldr r2, .L765+4 12666 0640 1378 ldrb r3, [r2] @ zero_extendqisi2 664:Src/main.c **** } 12667 .loc 1 664 21 view .LVU4006 12668 0642 43F00403 orr r3, r3, #4 12669 0646 1370 strb r3, [r2] 12670 .L690: 666:Src/main.c **** CPU_state = CPU_state_old; 12671 .loc 1 666 6 is_stmt 1 view .LVU4007 666:Src/main.c **** CPU_state = CPU_state_old; 12672 .loc 1 666 32 is_stmt 0 view .LVU4008 12673 0648 774B ldr r3, .L765+8 12674 064a 0122 movs r2, #1 12675 064c 1A70 strb r2, [r3] 667:Src/main.c **** break; 12676 .loc 1 667 6 is_stmt 1 view .LVU4009 667:Src/main.c **** break; 12677 .loc 1 667 16 is_stmt 0 view .LVU4010 12678 064e 774B ldr r3, .L765+12 12679 0650 1A78 ldrb r2, [r3] @ zero_extendqisi2 12680 0652 774B ldr r3, .L765+16 12681 0654 1A70 strb r2, [r3] 668:Src/main.c **** case AD9102_WAVE_CTRL_CMD://14 - Control custom AD9102 SRAM upload 12682 .loc 1 668 5 is_stmt 1 view .LVU4011 12683 0656 54E5 b .L652 12684 .L752: 12685 .LBB716: 657:Src/main.c **** uint16_t dac_code = (uint16_t)(COMMAND[1] & 0x0FFFu); 12686 .loc 1 657 7 view .LVU4012 12687 .LVL1128: 658:Src/main.c **** uint8_t enable = (flags & STM32_DAC_FLAG_ENABLE) ? 1u : 0u; 12688 .loc 1 658 7 view .LVU4013 658:Src/main.c **** uint8_t enable = (flags & STM32_DAC_FLAG_ENABLE) ? 1u : 0u; 12689 .loc 1 658 45 is_stmt 0 view .LVU4014 12690 0658 6088 ldrh r0, [r4, #2] 12691 .LVL1129: ARM GAS /tmp/ccLSPxIe.s page 645 659:Src/main.c **** PA4_DAC_Set(dac_code, enable); 12692 .loc 1 659 7 is_stmt 1 view .LVU4015 659:Src/main.c **** PA4_DAC_Set(dac_code, enable); 12693 .loc 1 659 61 is_stmt 0 view .LVU4016 12694 065a 2178 ldrb r1, [r4] @ zero_extendqisi2 12695 .LVL1130: 660:Src/main.c **** } 12696 .loc 1 660 7 is_stmt 1 view .LVU4017 12697 065c 01F00101 and r1, r1, #1 12698 .LVL1131: 660:Src/main.c **** } 12699 .loc 1 660 7 is_stmt 0 view .LVU4018 12700 0660 C0F30B00 ubfx r0, r0, #0, #12 12701 .LVL1132: 660:Src/main.c **** } 12702 .loc 1 660 7 view .LVU4019 12703 0664 FFF7FEFF bl PA4_DAC_Set 12704 .LVL1133: 660:Src/main.c **** } 12705 .loc 1 660 7 view .LVU4020 12706 .LBE716: 12707 0668 EEE7 b .L690 12708 .LVL1134: 12709 .L655: 670:Src/main.c **** if (CalculateChecksum(COMMAND, AD9102_WAVE_CTRL_WORDS - 1) == COMMAND[AD9102_WAVE_CTRL_WORDS - 12710 .loc 1 670 6 is_stmt 1 view .LVU4021 670:Src/main.c **** if (CalculateChecksum(COMMAND, AD9102_WAVE_CTRL_WORDS - 1) == COMMAND[AD9102_WAVE_CTRL_WORDS - 12711 .loc 1 670 20 is_stmt 0 view .LVU4022 12712 066a 6E4B ldr r3, .L765+4 12713 066c 0022 movs r2, #0 12714 066e 5A70 strb r2, [r3, #1] 671:Src/main.c **** { 12715 .loc 1 671 6 is_stmt 1 view .LVU4023 671:Src/main.c **** { 12716 .loc 1 671 10 is_stmt 0 view .LVU4024 12717 0670 6B4C ldr r4, .L765 12718 0672 0321 movs r1, #3 12719 0674 2046 mov r0, r4 12720 0676 FFF7FEFF bl CalculateChecksum 12721 .LVL1135: 671:Src/main.c **** { 12722 .loc 1 671 75 discriminator 1 view .LVU4025 12723 067a E388 ldrh r3, [r4, #6] 671:Src/main.c **** { 12724 .loc 1 671 9 discriminator 1 view .LVU4026 12725 067c 9842 cmp r0, r3 12726 067e 0CD0 beq .L753 722:Src/main.c **** } 12727 .loc 1 722 7 is_stmt 1 view .LVU4027 722:Src/main.c **** } 12728 .loc 1 722 17 is_stmt 0 view .LVU4028 12729 0680 684A ldr r2, .L765+4 12730 0682 1378 ldrb r3, [r2] @ zero_extendqisi2 722:Src/main.c **** } 12731 .loc 1 722 21 view .LVU4029 12732 0684 43F00403 orr r3, r3, #4 12733 0688 1370 strb r3, [r2] ARM GAS /tmp/ccLSPxIe.s page 646 12734 .L696: 724:Src/main.c **** CPU_state = CPU_state_old; 12735 .loc 1 724 6 is_stmt 1 view .LVU4030 724:Src/main.c **** CPU_state = CPU_state_old; 12736 .loc 1 724 32 is_stmt 0 view .LVU4031 12737 068a 674B ldr r3, .L765+8 12738 068c 0122 movs r2, #1 12739 068e 1A70 strb r2, [r3] 725:Src/main.c **** break; 12740 .loc 1 725 6 is_stmt 1 view .LVU4032 725:Src/main.c **** break; 12741 .loc 1 725 16 is_stmt 0 view .LVU4033 12742 0690 664B ldr r3, .L765+12 12743 0692 1A78 ldrb r2, [r3] @ zero_extendqisi2 12744 0694 664B ldr r3, .L765+16 12745 0696 1A70 strb r2, [r3] 726:Src/main.c **** case AD9102_WAVE_DATA_CMD://15 - Write custom AD9102 SRAM samples 12746 .loc 1 726 5 is_stmt 1 view .LVU4034 12747 0698 33E5 b .L652 12748 .L753: 12749 .LBB717: 673:Src/main.c **** uint16_t param0 = COMMAND[1]; 12750 .loc 1 673 7 view .LVU4035 673:Src/main.c **** uint16_t param0 = COMMAND[1]; 12751 .loc 1 673 16 is_stmt 0 view .LVU4036 12752 069a 2288 ldrh r2, [r4] 12753 .LVL1136: 674:Src/main.c **** uint16_t param1 = COMMAND[2]; 12754 .loc 1 674 7 is_stmt 1 view .LVU4037 674:Src/main.c **** uint16_t param1 = COMMAND[2]; 12755 .loc 1 674 16 is_stmt 0 view .LVU4038 12756 069c 6088 ldrh r0, [r4, #2] 12757 .LVL1137: 675:Src/main.c **** 12758 .loc 1 675 7 is_stmt 1 view .LVU4039 675:Src/main.c **** 12759 .loc 1 675 16 is_stmt 0 view .LVU4040 12760 069e A388 ldrh r3, [r4, #4] 12761 .LVL1138: 677:Src/main.c **** { 12762 .loc 1 677 7 is_stmt 1 view .LVU4041 12763 06a0 022A cmp r2, #2 12764 06a2 10D0 beq .L692 12765 06a4 032A cmp r2, #3 12766 06a6 34D0 beq .L693 12767 06a8 012A cmp r2, #1 12768 06aa 3CD1 bne .L694 680:Src/main.c **** { 12769 .loc 1 680 9 view .LVU4042 680:Src/main.c **** { 12770 .loc 1 680 12 is_stmt 0 view .LVU4043 12771 06ac 1BB9 cbnz r3, .L695 680:Src/main.c **** { 12772 .loc 1 680 32 discriminator 1 view .LVU4044 12773 06ae FFF7FEFF bl AD9102_BeginWaveUpload 12774 .LVL1139: 680:Src/main.c **** { ARM GAS /tmp/ccLSPxIe.s page 647 12775 .loc 1 680 28 discriminator 1 view .LVU4045 12776 06b2 0028 cmp r0, #0 12777 06b4 E9D1 bne .L696 12778 .L695: 682:Src/main.c **** State_Data[0] |= AD9102_ERR; 12779 .loc 1 682 10 is_stmt 1 view .LVU4046 12780 06b6 FFF7FEFF bl AD9102_CancelWaveUpload 12781 .LVL1140: 683:Src/main.c **** } 12782 .loc 1 683 10 view .LVU4047 683:Src/main.c **** } 12783 .loc 1 683 20 is_stmt 0 view .LVU4048 12784 06ba 5A4A ldr r2, .L765+4 12785 06bc 1378 ldrb r3, [r2] @ zero_extendqisi2 683:Src/main.c **** } 12786 .loc 1 683 24 view .LVU4049 12787 06be 63F07F03 orn r3, r3, #127 12788 06c2 1370 strb r3, [r2] 12789 06c4 E1E7 b .L696 12790 .LVL1141: 12791 .L692: 12792 .LBB718: 688:Src/main.c **** uint8_t ok = 0u; 12793 .loc 1 688 9 is_stmt 1 view .LVU4050 688:Src/main.c **** uint8_t ok = 0u; 12794 .loc 1 688 18 is_stmt 0 view .LVU4051 12795 06c6 5B4A ldr r2, .L765+20 12796 .LVL1142: 688:Src/main.c **** uint8_t ok = 0u; 12797 .loc 1 688 18 view .LVU4052 12798 06c8 1488 ldrh r4, [r2] 12799 .LVL1143: 689:Src/main.c **** uint16_t pat_status; 12800 .loc 1 689 9 is_stmt 1 view .LVU4053 689:Src/main.c **** uint16_t pat_status; 12801 .loc 1 689 17 is_stmt 0 view .LVU4054 12802 06ca 0022 movs r2, #0 12803 06cc 8DF81720 strb r2, [sp, #23] 690:Src/main.c **** 12804 .loc 1 690 9 is_stmt 1 view .LVU4055 692:Src/main.c **** { 12805 .loc 1 692 9 view .LVU4056 692:Src/main.c **** { 12806 .loc 1 692 12 is_stmt 0 view .LVU4057 12807 06d0 1843 orrs r0, r0, r3 12808 .LVL1144: 692:Src/main.c **** { 12809 .loc 1 692 12 view .LVU4058 12810 06d2 07D0 beq .L697 694:Src/main.c **** State_Data[0] |= AD9102_ERR; 12811 .loc 1 694 10 is_stmt 1 view .LVU4059 12812 06d4 FFF7FEFF bl AD9102_CancelWaveUpload 12813 .LVL1145: 695:Src/main.c **** break; 12814 .loc 1 695 10 view .LVU4060 695:Src/main.c **** break; 12815 .loc 1 695 20 is_stmt 0 view .LVU4061 ARM GAS /tmp/ccLSPxIe.s page 648 12816 06d8 524A ldr r2, .L765+4 12817 06da 1378 ldrb r3, [r2] @ zero_extendqisi2 695:Src/main.c **** break; 12818 .loc 1 695 24 view .LVU4062 12819 06dc 63F07F03 orn r3, r3, #127 12820 06e0 1370 strb r3, [r2] 696:Src/main.c **** } 12821 .loc 1 696 10 is_stmt 1 view .LVU4063 12822 06e2 D2E7 b .L696 12823 .LVL1146: 12824 .L697: 699:Src/main.c **** State_Data[1] = (uint8_t)(pat_status & 0x00FFu); 12825 .loc 1 699 9 view .LVU4064 699:Src/main.c **** State_Data[1] = (uint8_t)(pat_status & 0x00FFu); 12826 .loc 1 699 22 is_stmt 0 view .LVU4065 12827 06e4 0DF11700 add r0, sp, #23 12828 06e8 FFF7FEFF bl AD9102_CommitWaveUpload 12829 .LVL1147: 700:Src/main.c **** if ((!ok) || AD9102_CheckFlagsSram(pat_status, 1u, samples, AD9102_SRAM_HOLD_DEFAULT)) 12830 .loc 1 700 9 is_stmt 1 view .LVU4066 700:Src/main.c **** if ((!ok) || AD9102_CheckFlagsSram(pat_status, 1u, samples, AD9102_SRAM_HOLD_DEFAULT)) 12831 .loc 1 700 23 is_stmt 0 view .LVU4067 12832 06ec 4D4B ldr r3, .L765+4 12833 06ee 5870 strb r0, [r3, #1] 701:Src/main.c **** { 12834 .loc 1 701 9 is_stmt 1 view .LVU4068 701:Src/main.c **** { 12835 .loc 1 701 14 is_stmt 0 view .LVU4069 12836 06f0 9DF81730 ldrb r3, [sp, #23] @ zero_extendqisi2 701:Src/main.c **** { 12837 .loc 1 701 12 view .LVU4070 12838 06f4 2BB9 cbnz r3, .L754 12839 .LVL1148: 12840 .L698: 703:Src/main.c **** } 12841 .loc 1 703 10 is_stmt 1 view .LVU4071 703:Src/main.c **** } 12842 .loc 1 703 20 is_stmt 0 view .LVU4072 12843 06f6 4B4A ldr r2, .L765+4 12844 06f8 1378 ldrb r3, [r2] @ zero_extendqisi2 703:Src/main.c **** } 12845 .loc 1 703 24 view .LVU4073 12846 06fa 63F07F03 orn r3, r3, #127 12847 06fe 1370 strb r3, [r2] 12848 .LBE718: 706:Src/main.c **** case AD9102_WAVE_OPCODE_CANCEL: 12849 .loc 1 706 8 is_stmt 1 view .LVU4074 12850 0700 C3E7 b .L696 12851 .LVL1149: 12852 .L754: 12853 .LBB719: 701:Src/main.c **** { 12854 .loc 1 701 22 is_stmt 0 discriminator 1 view .LVU4075 12855 0702 0123 movs r3, #1 12856 0704 2246 mov r2, r4 12857 0706 1946 mov r1, r3 12858 0708 FFF7FEFF bl AD9102_CheckFlagsSram ARM GAS /tmp/ccLSPxIe.s page 649 12859 .LVL1150: 701:Src/main.c **** { 12860 .loc 1 701 19 discriminator 1 view .LVU4076 12861 070c 0028 cmp r0, #0 12862 070e BCD0 beq .L696 12863 0710 F1E7 b .L698 12864 .LVL1151: 12865 .L693: 701:Src/main.c **** { 12866 .loc 1 701 19 discriminator 1 view .LVU4077 12867 .LBE719: 708:Src/main.c **** { 12868 .loc 1 708 9 is_stmt 1 view .LVU4078 708:Src/main.c **** { 12869 .loc 1 708 12 is_stmt 0 view .LVU4079 12870 0712 1843 orrs r0, r0, r3 12871 .LVL1152: 708:Src/main.c **** { 12872 .loc 1 708 12 view .LVU4080 12873 0714 04D0 beq .L700 710:Src/main.c **** } 12874 .loc 1 710 10 is_stmt 1 view .LVU4081 710:Src/main.c **** } 12875 .loc 1 710 20 is_stmt 0 view .LVU4082 12876 0716 434A ldr r2, .L765+4 12877 .LVL1153: 710:Src/main.c **** } 12878 .loc 1 710 20 view .LVU4083 12879 0718 1378 ldrb r3, [r2] @ zero_extendqisi2 12880 .LVL1154: 710:Src/main.c **** } 12881 .loc 1 710 24 view .LVU4084 12882 071a 63F07F03 orn r3, r3, #127 12883 071e 1370 strb r3, [r2] 12884 .L700: 712:Src/main.c **** break; 12885 .loc 1 712 9 is_stmt 1 view .LVU4085 12886 0720 FFF7FEFF bl AD9102_CancelWaveUpload 12887 .LVL1155: 713:Src/main.c **** default: 12888 .loc 1 713 8 view .LVU4086 12889 0724 B1E7 b .L696 12890 .LVL1156: 12891 .L694: 715:Src/main.c **** State_Data[0] |= AD9102_ERR; 12892 .loc 1 715 9 view .LVU4087 12893 0726 FFF7FEFF bl AD9102_CancelWaveUpload 12894 .LVL1157: 716:Src/main.c **** break; 12895 .loc 1 716 9 view .LVU4088 716:Src/main.c **** break; 12896 .loc 1 716 19 is_stmt 0 view .LVU4089 12897 072a 3E4A ldr r2, .L765+4 12898 072c 1378 ldrb r3, [r2] @ zero_extendqisi2 716:Src/main.c **** break; 12899 .loc 1 716 23 view .LVU4090 12900 072e 63F07F03 orn r3, r3, #127 ARM GAS /tmp/ccLSPxIe.s page 650 12901 0732 1370 strb r3, [r2] 717:Src/main.c **** } 12902 .loc 1 717 8 is_stmt 1 view .LVU4091 12903 0734 A9E7 b .L696 12904 .LVL1158: 12905 .L653: 717:Src/main.c **** } 12906 .loc 1 717 8 is_stmt 0 view .LVU4092 12907 .LBE717: 728:Src/main.c **** if (CalculateChecksum(COMMAND, AD9102_WAVE_DATA_WORDS - 1) == COMMAND[AD9102_WAVE_DATA_WORDS - 12908 .loc 1 728 6 is_stmt 1 view .LVU4093 728:Src/main.c **** if (CalculateChecksum(COMMAND, AD9102_WAVE_DATA_WORDS - 1) == COMMAND[AD9102_WAVE_DATA_WORDS - 12909 .loc 1 728 20 is_stmt 0 view .LVU4094 12910 0736 3B4B ldr r3, .L765+4 12911 0738 0022 movs r2, #0 12912 073a 5A70 strb r2, [r3, #1] 729:Src/main.c **** { 12913 .loc 1 729 6 is_stmt 1 view .LVU4095 729:Src/main.c **** { 12914 .loc 1 729 10 is_stmt 0 view .LVU4096 12915 073c 384C ldr r4, .L765 12916 073e 0D21 movs r1, #13 12917 0740 2046 mov r0, r4 12918 0742 FFF7FEFF bl CalculateChecksum 12919 .LVL1159: 729:Src/main.c **** { 12920 .loc 1 729 75 discriminator 1 view .LVU4097 12921 0746 638B ldrh r3, [r4, #26] 729:Src/main.c **** { 12922 .loc 1 729 9 discriminator 1 view .LVU4098 12923 0748 9842 cmp r0, r3 12924 074a 0ED0 beq .L755 740:Src/main.c **** State_Data[0] |= UART_DECODE_ERR; 12925 .loc 1 740 7 is_stmt 1 view .LVU4099 12926 074c FFF7FEFF bl AD9102_CancelWaveUpload 12927 .LVL1160: 741:Src/main.c **** } 12928 .loc 1 741 7 view .LVU4100 741:Src/main.c **** } 12929 .loc 1 741 17 is_stmt 0 view .LVU4101 12930 0750 344A ldr r2, .L765+4 12931 0752 1378 ldrb r3, [r2] @ zero_extendqisi2 741:Src/main.c **** } 12932 .loc 1 741 21 view .LVU4102 12933 0754 43F00403 orr r3, r3, #4 12934 0758 1370 strb r3, [r2] 12935 .L702: 743:Src/main.c **** CPU_state = CPU_state_old; 12936 .loc 1 743 6 is_stmt 1 view .LVU4103 743:Src/main.c **** CPU_state = CPU_state_old; 12937 .loc 1 743 32 is_stmt 0 view .LVU4104 12938 075a 334B ldr r3, .L765+8 12939 075c 0122 movs r2, #1 12940 075e 1A70 strb r2, [r3] 744:Src/main.c **** break; 12941 .loc 1 744 6 is_stmt 1 view .LVU4105 744:Src/main.c **** break; ARM GAS /tmp/ccLSPxIe.s page 651 12942 .loc 1 744 16 is_stmt 0 view .LVU4106 12943 0760 324B ldr r3, .L765+12 12944 0762 1A78 ldrb r2, [r3] @ zero_extendqisi2 12945 0764 324B ldr r3, .L765+16 12946 0766 1A70 strb r2, [r3] 745:Src/main.c **** case DECODE_TASK: 12947 .loc 1 745 5 is_stmt 1 view .LVU4107 12948 0768 CBE4 b .L652 12949 .L755: 12950 .LBB720: 731:Src/main.c **** if (!AD9102_WriteWaveUploadChunk(&COMMAND[1], chunk_count)) 12951 .loc 1 731 7 view .LVU4108 731:Src/main.c **** if (!AD9102_WriteWaveUploadChunk(&COMMAND[1], chunk_count)) 12952 .loc 1 731 16 is_stmt 0 view .LVU4109 12953 076a 2046 mov r0, r4 12954 .LVL1161: 732:Src/main.c **** { 12955 .loc 1 732 7 is_stmt 1 view .LVU4110 732:Src/main.c **** { 12956 .loc 1 732 12 is_stmt 0 view .LVU4111 12957 076c 30F8021B ldrh r1, [r0], #2 12958 0770 FFF7FEFF bl AD9102_WriteWaveUploadChunk 12959 .LVL1162: 732:Src/main.c **** { 12960 .loc 1 732 10 discriminator 1 view .LVU4112 12961 0774 0028 cmp r0, #0 12962 0776 F0D1 bne .L702 734:Src/main.c **** State_Data[0] |= AD9102_ERR; 12963 .loc 1 734 8 is_stmt 1 view .LVU4113 12964 0778 FFF7FEFF bl AD9102_CancelWaveUpload 12965 .LVL1163: 735:Src/main.c **** } 12966 .loc 1 735 8 view .LVU4114 735:Src/main.c **** } 12967 .loc 1 735 18 is_stmt 0 view .LVU4115 12968 077c 294A ldr r2, .L765+4 12969 077e 1378 ldrb r3, [r2] @ zero_extendqisi2 735:Src/main.c **** } 12970 .loc 1 735 22 view .LVU4116 12971 0780 63F07F03 orn r3, r3, #127 12972 0784 1370 strb r3, [r2] 12973 0786 E8E7 b .L702 12974 .LVL1164: 12975 .L661: 735:Src/main.c **** } 12976 .loc 1 735 22 view .LVU4117 12977 .LBE720: 747:Src/main.c **** { 12978 .loc 1 747 6 is_stmt 1 view .LVU4118 747:Src/main.c **** { 12979 .loc 1 747 10 is_stmt 0 view .LVU4119 12980 0788 2548 ldr r0, .L765 12981 078a FFF7FEFF bl CheckChecksum 12982 .LVL1165: 747:Src/main.c **** { 12983 .loc 1 747 9 discriminator 1 view .LVU4120 12984 078e 70B9 cbnz r0, .L756 ARM GAS /tmp/ccLSPxIe.s page 652 756:Src/main.c **** CPU_state = DEFAULT_ENABLE; 12985 .loc 1 756 7 is_stmt 1 view .LVU4121 756:Src/main.c **** CPU_state = DEFAULT_ENABLE; 12986 .loc 1 756 17 is_stmt 0 view .LVU4122 12987 0790 244A ldr r2, .L765+4 12988 0792 1378 ldrb r3, [r2] @ zero_extendqisi2 756:Src/main.c **** CPU_state = DEFAULT_ENABLE; 12989 .loc 1 756 21 view .LVU4123 12990 0794 43F00403 orr r3, r3, #4 12991 0798 1370 strb r3, [r2] 757:Src/main.c **** CPU_state_old = HALT;//Save main current cycle 12992 .loc 1 757 7 is_stmt 1 view .LVU4124 757:Src/main.c **** CPU_state_old = HALT;//Save main current cycle 12993 .loc 1 757 17 is_stmt 0 view .LVU4125 12994 079a 254B ldr r3, .L765+16 12995 079c 0222 movs r2, #2 12996 079e 1A70 strb r2, [r3] 758:Src/main.c **** } 12997 .loc 1 758 7 is_stmt 1 view .LVU4126 758:Src/main.c **** } 12998 .loc 1 758 21 is_stmt 0 view .LVU4127 12999 07a0 224B ldr r3, .L765+12 13000 07a2 0022 movs r2, #0 13001 07a4 1A70 strb r2, [r3] 13002 .L704: 760:Src/main.c **** break; 13003 .loc 1 760 6 is_stmt 1 view .LVU4128 760:Src/main.c **** break; 13004 .loc 1 760 32 is_stmt 0 view .LVU4129 13005 07a6 204B ldr r3, .L765+8 13006 07a8 0122 movs r2, #1 13007 07aa 1A70 strb r2, [r3] 761:Src/main.c **** case RUN_TASK: 13008 .loc 1 761 5 is_stmt 1 view .LVU4130 13009 07ac A9E4 b .L652 13010 .L756: 749:Src/main.c **** TO6_before = TO6; 13011 .loc 1 749 7 view .LVU4131 13012 07ae 224B ldr r3, .L765+24 13013 07b0 224A ldr r2, .L765+28 13014 07b2 2349 ldr r1, .L765+32 13015 07b4 1A48 ldr r0, .L765 13016 07b6 FFF7FEFF bl Decode_task 13017 .LVL1166: 750:Src/main.c **** CPU_state = RUN_TASK; 13018 .loc 1 750 7 view .LVU4132 750:Src/main.c **** CPU_state = RUN_TASK; 13019 .loc 1 750 18 is_stmt 0 view .LVU4133 13020 07ba 224B ldr r3, .L765+36 13021 07bc 1A68 ldr r2, [r3] 13022 07be 224B ldr r3, .L765+40 13023 07c0 1A60 str r2, [r3] 751:Src/main.c **** CPU_state_old = RUN_TASK;//Save main current cycle 13024 .loc 1 751 7 is_stmt 1 view .LVU4134 751:Src/main.c **** CPU_state_old = RUN_TASK;//Save main current cycle 13025 .loc 1 751 17 is_stmt 0 view .LVU4135 13026 07c2 0923 movs r3, #9 ARM GAS /tmp/ccLSPxIe.s page 653 13027 07c4 1A4A ldr r2, .L765+16 13028 07c6 1370 strb r3, [r2] 752:Src/main.c **** } 13029 .loc 1 752 7 is_stmt 1 view .LVU4136 752:Src/main.c **** } 13030 .loc 1 752 21 is_stmt 0 view .LVU4137 13031 07c8 184A ldr r2, .L765+12 13032 07ca 1370 strb r3, [r2] 13033 07cc EBE7 b .L704 13034 .L660: 763:Src/main.c **** { 13035 .loc 1 763 6 is_stmt 1 view .LVU4138 763:Src/main.c **** { 13036 .loc 1 763 18 is_stmt 0 view .LVU4139 13037 07ce 1F4B ldr r3, .L765+44 13038 07d0 1B78 ldrb r3, [r3] @ zero_extendqisi2 13039 07d2 012B cmp r3, #1 13040 07d4 4AD0 beq .L705 13041 07d6 022B cmp r3, #2 13042 07d8 00F02D81 beq .L706 13043 .L707: 1018:Src/main.c **** { 13044 .loc 1 1018 6 is_stmt 1 view .LVU4140 1018:Src/main.c **** { 13045 .loc 1 1018 13 is_stmt 0 view .LVU4141 13046 07dc 1C4B ldr r3, .L765+48 13047 07de 1B68 ldr r3, [r3] 13048 07e0 1C4A ldr r2, .L765+52 13049 07e2 1268 ldr r2, [r2] 1018:Src/main.c **** { 13050 .loc 1 1018 9 view .LVU4142 13051 07e4 9342 cmp r3, r2 13052 07e6 00F2FE81 bhi .L757 13053 .L724: 1070:Src/main.c **** 13054 .loc 1 1070 13 is_stmt 1 discriminator 1 view .LVU4143 13055 07ea 1B4B ldr r3, .L765+56 13056 07ec 1B78 ldrb r3, [r3] @ zero_extendqisi2 13057 07ee 002B cmp r3, #0 13058 07f0 FBD0 beq .L724 1072:Src/main.c **** 13059 .loc 1 1072 6 view .LVU4144 13060 07f2 FFF7FEFF bl Stop_TIM10 13061 .LVL1167: 1074:Src/main.c **** { 13062 .loc 1 1074 6 view .LVU4145 1074:Src/main.c **** { 13063 .loc 1 1074 14 is_stmt 0 view .LVU4146 13064 07f6 154B ldr r3, .L765+44 13065 07f8 DB8A ldrh r3, [r3, #22] 1074:Src/main.c **** { 13066 .loc 1 1074 9 view .LVU4147 13067 07fa 032B cmp r3, #3 13068 07fc 0BD9 bls .L725 1076:Src/main.c **** TO10_counter = task.dt / 10; 13069 .loc 1 1076 7 is_stmt 1 view .LVU4148 1076:Src/main.c **** TO10_counter = task.dt / 10; ARM GAS /tmp/ccLSPxIe.s page 654 13070 .loc 1 1076 26 is_stmt 0 view .LVU4149 13071 07fe 174B ldr r3, .L765+60 13072 0800 1A68 ldr r2, [r3] 13073 0802 174B ldr r3, .L765+64 13074 0804 DA60 str r2, [r3, #12] 1077:Src/main.c **** } 13075 .loc 1 1077 7 is_stmt 1 view .LVU4150 1077:Src/main.c **** } 13076 .loc 1 1077 26 is_stmt 0 view .LVU4151 13077 0806 114B ldr r3, .L765+44 13078 0808 1B7D ldrb r3, [r3, #20] @ zero_extendqisi2 1077:Src/main.c **** } 13079 .loc 1 1077 30 view .LVU4152 13080 080a 164A ldr r2, .L765+68 13081 080c A2FB0323 umull r2, r3, r2, r3 13082 0810 DB08 lsrs r3, r3, #3 1077:Src/main.c **** } 13083 .loc 1 1077 20 view .LVU4153 13084 0812 154A ldr r2, .L765+72 13085 0814 1360 str r3, [r2] 13086 .L725: 1080:Src/main.c **** break; 13087 .loc 1 1080 6 is_stmt 1 view .LVU4154 1080:Src/main.c **** break; 13088 .loc 1 1080 20 is_stmt 0 view .LVU4155 13089 0816 054B ldr r3, .L765+12 13090 0818 0922 movs r2, #9 13091 081a 1A70 strb r2, [r3] 1081:Src/main.c **** } 13092 .loc 1 1081 9 is_stmt 1 view .LVU4156 13093 081c 71E4 b .L652 13094 .L766: 13095 081e 00BF .align 2 13096 .L765: 13097 0820 00000000 .word COMMAND 13098 0824 00000000 .word State_Data 13099 0828 00000000 .word UART_transmission_request 13100 082c 00000000 .word CPU_state_old 13101 0830 00000000 .word CPU_state 13102 0834 00000000 .word ad9102_wave_expected_samples 13103 0838 00000000 .word Curr_setup 13104 083c 00000000 .word LD2_curr_setup 13105 0840 00000000 .word LD1_curr_setup 13106 0844 00000000 .word TO6 13107 0848 00000000 .word TO6_before 13108 084c 00000000 .word task 13109 0850 00000000 .word TO7 13110 0854 00000000 .word TO7_before 13111 0858 00000000 .word TIM10_coflag 13112 085c 00000000 .word TIM10_period 13113 0860 00000000 .word htim10 13114 0864 CDCCCCCC .word -858993459 13115 0868 00000000 .word TO10_counter 13116 .L705: 13117 .LBB721: 785:Src/main.c **** (void) MPhD_T(TT_CHANGE_TEMP_1); 13118 .loc 1 785 7 view .LVU4157 ARM GAS /tmp/ccLSPxIe.s page 655 785:Src/main.c **** (void) MPhD_T(TT_CHANGE_TEMP_1); 13119 .loc 1 785 38 is_stmt 0 view .LVU4158 13120 086c AD4B ldr r3, .L767 13121 086e D3ED077A vldr.32 s15, [r3, #28] 785:Src/main.c **** (void) MPhD_T(TT_CHANGE_TEMP_1); 13122 .loc 1 785 7 view .LVU4159 13123 0872 FCEEE77A vcvt.u32.f32 s15, s15 13124 0876 17EE903A vmov r3, s15 @ int 13125 087a 99B2 uxth r1, r3 13126 087c 0220 movs r0, #2 13127 087e FFF7FEFF bl Set_LTEC 13128 .LVL1168: 786:Src/main.c **** LD1_param.LD_CURR_TEMP = MPhD_T(TT_CHANGE_TEMP_1); 13129 .loc 1 786 7 is_stmt 1 view .LVU4160 786:Src/main.c **** LD1_param.LD_CURR_TEMP = MPhD_T(TT_CHANGE_TEMP_1); 13130 .loc 1 786 14 is_stmt 0 view .LVU4161 13131 0882 0320 movs r0, #3 13132 0884 FFF7FEFF bl MPhD_T 13133 .LVL1169: 787:Src/main.c **** (void) MPhD_T(TT_CHANGE_TEMP_2); 13134 .loc 1 787 7 is_stmt 1 view .LVU4162 787:Src/main.c **** (void) MPhD_T(TT_CHANGE_TEMP_2); 13135 .loc 1 787 32 is_stmt 0 view .LVU4163 13136 0888 0320 movs r0, #3 13137 088a FFF7FEFF bl MPhD_T 13138 .LVL1170: 787:Src/main.c **** (void) MPhD_T(TT_CHANGE_TEMP_2); 13139 .loc 1 787 30 discriminator 1 view .LVU4164 13140 088e A64C ldr r4, .L767+4 13141 0890 2080 strh r0, [r4] @ movhi 788:Src/main.c **** LD2_param.LD_CURR_TEMP = MPhD_T(TT_CHANGE_TEMP_2); 13142 .loc 1 788 7 is_stmt 1 view .LVU4165 788:Src/main.c **** LD2_param.LD_CURR_TEMP = MPhD_T(TT_CHANGE_TEMP_2); 13143 .loc 1 788 14 is_stmt 0 view .LVU4166 13144 0892 0420 movs r0, #4 13145 0894 FFF7FEFF bl MPhD_T 13146 .LVL1171: 789:Src/main.c **** temp16=PID_Controller_Temp(&LD1_curr_setup, &LD1_param, 1); 13147 .loc 1 789 7 is_stmt 1 view .LVU4167 789:Src/main.c **** temp16=PID_Controller_Temp(&LD1_curr_setup, &LD1_param, 1); 13148 .loc 1 789 32 is_stmt 0 view .LVU4168 13149 0898 0420 movs r0, #4 13150 089a FFF7FEFF bl MPhD_T 13151 .LVL1172: 789:Src/main.c **** temp16=PID_Controller_Temp(&LD1_curr_setup, &LD1_param, 1); 13152 .loc 1 789 30 discriminator 1 view .LVU4169 13153 089e A34D ldr r5, .L767+8 13154 08a0 2880 strh r0, [r5] @ movhi 790:Src/main.c **** Set_LTEC(TT_CHANGE_TEMP_1, temp16);//Drive Laser TEC 1 13155 .loc 1 790 7 is_stmt 1 view .LVU4170 790:Src/main.c **** Set_LTEC(TT_CHANGE_TEMP_1, temp16);//Drive Laser TEC 1 13156 .loc 1 790 14 is_stmt 0 view .LVU4171 13157 08a2 0122 movs r2, #1 13158 08a4 2146 mov r1, r4 13159 08a6 A248 ldr r0, .L767+12 13160 08a8 FFF7FEFF bl PID_Controller_Temp 13161 .LVL1173: ARM GAS /tmp/ccLSPxIe.s page 656 13162 08ac 0146 mov r1, r0 790:Src/main.c **** Set_LTEC(TT_CHANGE_TEMP_1, temp16);//Drive Laser TEC 1 13163 .loc 1 790 13 discriminator 1 view .LVU4172 13164 08ae A14C ldr r4, .L767+16 13165 08b0 2080 strh r0, [r4] @ movhi 791:Src/main.c **** temp16=PID_Controller_Temp(&LD2_curr_setup, &LD2_param, 2); 13166 .loc 1 791 7 is_stmt 1 view .LVU4173 13167 08b2 0320 movs r0, #3 13168 08b4 FFF7FEFF bl Set_LTEC 13169 .LVL1174: 792:Src/main.c **** Set_LTEC(TT_CHANGE_TEMP_2, temp16);//Drive Laser TEC 2 13170 .loc 1 792 7 view .LVU4174 792:Src/main.c **** Set_LTEC(TT_CHANGE_TEMP_2, temp16);//Drive Laser TEC 2 13171 .loc 1 792 14 is_stmt 0 view .LVU4175 13172 08b8 0222 movs r2, #2 13173 08ba 2946 mov r1, r5 13174 08bc 9E48 ldr r0, .L767+20 13175 08be FFF7FEFF bl PID_Controller_Temp 13176 .LVL1175: 13177 08c2 0146 mov r1, r0 792:Src/main.c **** Set_LTEC(TT_CHANGE_TEMP_2, temp16);//Drive Laser TEC 2 13178 .loc 1 792 13 discriminator 1 view .LVU4176 13179 08c4 2080 strh r0, [r4] @ movhi 793:Src/main.c **** 13180 .loc 1 793 7 is_stmt 1 view .LVU4177 13181 08c6 0420 movs r0, #4 13182 08c8 FFF7FEFF bl Set_LTEC 13183 .LVL1176: 796:Src/main.c **** HAL_GPIO_WritePin(GPIOD, GPIO_PIN_7, GPIO_PIN_RESET); 13184 .loc 1 796 7 view .LVU4178 13185 08cc 9B4C ldr r4, .L767+24 13186 08ce 0122 movs r2, #1 13187 08d0 8021 movs r1, #128 13188 08d2 2046 mov r0, r4 13189 08d4 FFF7FEFF bl HAL_GPIO_WritePin 13190 .LVL1177: 797:Src/main.c **** 13191 .loc 1 797 7 view .LVU4179 13192 08d8 0022 movs r2, #0 13193 08da 8021 movs r1, #128 13194 08dc 2046 mov r0, r4 13195 08de FFF7FEFF bl HAL_GPIO_WritePin 13196 .LVL1178: 799:Src/main.c **** if (st != HAL_OK) 13197 .loc 1 799 7 view .LVU4180 799:Src/main.c **** if (st != HAL_OK) 13198 .loc 1 799 12 is_stmt 0 view .LVU4181 13199 08e2 9748 ldr r0, .L767+28 13200 08e4 FFF7FEFF bl HAL_TIM_Base_Start_IT 13201 .LVL1179: 800:Src/main.c **** while(1); 13202 .loc 1 800 7 is_stmt 1 view .LVU4182 800:Src/main.c **** while(1); 13203 .loc 1 800 10 is_stmt 0 view .LVU4183 13204 08e8 0028 cmp r0, #0 13205 08ea 75D1 bne .L709 803:Src/main.c **** uint16_t trigger_counter = 0; ARM GAS /tmp/ccLSPxIe.s page 657 13206 .loc 1 803 7 is_stmt 1 view .LVU4184 13207 .LVL1180: 804:Src/main.c **** uint16_t trigger_step = (uint8_t )((task.max_param - task.current_param)/task.delta_param * 1 13208 .loc 1 804 7 view .LVU4185 805:Src/main.c **** uint16_t task_sheduler = 0; 13209 .loc 1 805 7 view .LVU4186 805:Src/main.c **** uint16_t task_sheduler = 0; 13210 .loc 1 805 47 is_stmt 0 view .LVU4187 13211 08ec 8D4B ldr r3, .L767 13212 08ee 93ED027A vldr.32 s14, [r3, #8] 805:Src/main.c **** uint16_t task_sheduler = 0; 13213 .loc 1 805 64 view .LVU4188 13214 08f2 D3ED047A vldr.32 s15, [r3, #16] 805:Src/main.c **** uint16_t task_sheduler = 0; 13215 .loc 1 805 58 view .LVU4189 13216 08f6 37EE677A vsub.f32 s14, s14, s15 805:Src/main.c **** uint16_t task_sheduler = 0; 13217 .loc 1 805 84 view .LVU4190 13218 08fa D3ED036A vldr.32 s13, [r3, #12] 805:Src/main.c **** uint16_t task_sheduler = 0; 13219 .loc 1 805 79 view .LVU4191 13220 08fe C7EE267A vdiv.f32 s15, s14, s13 805:Src/main.c **** uint16_t task_sheduler = 0; 13221 .loc 1 805 97 view .LVU4192 13222 0902 B2EE047A vmov.f32 s14, #1.0e+1 13223 0906 67EE877A vmul.f32 s15, s15, s14 805:Src/main.c **** uint16_t task_sheduler = 0; 13224 .loc 1 805 31 view .LVU4193 13225 090a FCEEE77A vcvt.u32.f32 s15, s15 13226 090e CDED037A vstr.32 s15, [sp, #12] @ int 13227 0912 9DF80C60 ldrb r6, [sp, #12] @ zero_extendqisi2 13228 .LVL1181: 806:Src/main.c **** 13229 .loc 1 806 7 is_stmt 1 view .LVU4194 810:Src/main.c **** HAL_TIM_PWM_Stop(&htim4, TIM_CHANNEL_3); //start ADC clock 13230 .loc 1 810 7 view .LVU4195 13231 0916 DFF85492 ldr r9, .L767+72 13232 091a 0021 movs r1, #0 13233 091c 4846 mov r0, r9 13234 .LVL1182: 810:Src/main.c **** HAL_TIM_PWM_Stop(&htim4, TIM_CHANNEL_3); //start ADC clock 13235 .loc 1 810 7 is_stmt 0 view .LVU4196 13236 091e FFF7FEFF bl HAL_TIM_PWM_Stop 13237 .LVL1183: 811:Src/main.c **** TIM11 -> CR1 &= ~(1 << 3); //disables one-pulse mode 13238 .loc 1 811 7 is_stmt 1 view .LVU4197 13239 0922 DFF84C82 ldr r8, .L767+76 13240 0926 0821 movs r1, #8 13241 0928 4046 mov r0, r8 13242 092a FFF7FEFF bl HAL_TIM_PWM_Stop 13243 .LVL1184: 812:Src/main.c **** TIM4 -> CR1 &= ~(1 << 3); //disables one-pulse mode 13244 .loc 1 812 7 view .LVU4198 812:Src/main.c **** TIM4 -> CR1 &= ~(1 << 3); //disables one-pulse mode 13245 .loc 1 812 13 is_stmt 0 view .LVU4199 13246 092e 854F ldr r7, .L767+32 13247 0930 3B68 ldr r3, [r7] ARM GAS /tmp/ccLSPxIe.s page 658 812:Src/main.c **** TIM4 -> CR1 &= ~(1 << 3); //disables one-pulse mode 13248 .loc 1 812 20 view .LVU4200 13249 0932 23F00803 bic r3, r3, #8 13250 0936 3B60 str r3, [r7] 813:Src/main.c **** 13251 .loc 1 813 7 is_stmt 1 view .LVU4201 813:Src/main.c **** 13252 .loc 1 813 12 is_stmt 0 view .LVU4202 13253 0938 834D ldr r5, .L767+36 13254 093a 2B68 ldr r3, [r5] 813:Src/main.c **** 13255 .loc 1 813 19 view .LVU4203 13256 093c 23F00803 bic r3, r3, #8 13257 0940 2B60 str r3, [r5] 817:Src/main.c **** TIM4 -> CNT = 0; 13258 .loc 1 817 7 is_stmt 1 view .LVU4204 817:Src/main.c **** TIM4 -> CNT = 0; 13259 .loc 1 817 20 is_stmt 0 view .LVU4205 13260 0942 0024 movs r4, #0 13261 0944 7C62 str r4, [r7, #36] 818:Src/main.c **** 13262 .loc 1 818 7 is_stmt 1 view .LVU4206 818:Src/main.c **** 13263 .loc 1 818 19 is_stmt 0 view .LVU4207 13264 0946 6C62 str r4, [r5, #36] 820:Src/main.c **** HAL_TIM_PWM_Start(&htim4, TIM_CHANNEL_3); //start ADC clock 13265 .loc 1 820 7 is_stmt 1 view .LVU4208 13266 0948 2146 mov r1, r4 13267 094a 4846 mov r0, r9 13268 094c FFF7FEFF bl HAL_TIM_PWM_Start 13269 .LVL1185: 821:Src/main.c **** //TIM4 -> CNT = 0; 13270 .loc 1 821 7 view .LVU4209 13271 0950 0821 movs r1, #8 13272 0952 4046 mov r0, r8 13273 0954 FFF7FEFF bl HAL_TIM_PWM_Start 13274 .LVL1186: 824:Src/main.c **** TIM11 -> CNT = 0; 13275 .loc 1 824 7 view .LVU4210 824:Src/main.c **** TIM11 -> CNT = 0; 13276 .loc 1 824 26 is_stmt 0 view .LVU4211 13277 0958 EB6A ldr r3, [r5, #44] 824:Src/main.c **** TIM11 -> CNT = 0; 13278 .loc 1 824 33 view .LVU4212 13279 095a 143B subs r3, r3, #20 824:Src/main.c **** TIM11 -> CNT = 0; 13280 .loc 1 824 19 view .LVU4213 13281 095c 6B62 str r3, [r5, #36] 825:Src/main.c **** 13282 .loc 1 825 7 is_stmt 1 view .LVU4214 825:Src/main.c **** 13283 .loc 1 825 20 is_stmt 0 view .LVU4215 13284 095e 7C62 str r4, [r7, #36] 828:Src/main.c **** { 13285 .loc 1 828 7 is_stmt 1 view .LVU4216 804:Src/main.c **** uint16_t trigger_step = (uint8_t )((task.max_param - task.current_param)/task.delta_param * 1 13286 .loc 1 804 16 is_stmt 0 view .LVU4217 ARM GAS /tmp/ccLSPxIe.s page 659 13287 0960 2546 mov r5, r4 13288 .LVL1187: 13289 .L711: 828:Src/main.c **** { 13290 .loc 1 828 33 is_stmt 1 view .LVU4218 828:Src/main.c **** { 13291 .loc 1 828 18 is_stmt 0 view .LVU4219 13292 0962 704B ldr r3, .L767 13293 0964 D3ED047A vldr.32 s15, [r3, #16] 828:Src/main.c **** { 13294 .loc 1 828 39 view .LVU4220 13295 0968 93ED027A vldr.32 s14, [r3, #8] 828:Src/main.c **** { 13296 .loc 1 828 33 view .LVU4221 13297 096c F4EEC77A vcmpe.f32 s15, s14 13298 0970 F1EE10FA vmrs APSR_nzcv, FPSCR 13299 0974 37D5 bpl .L758 830:Src/main.c **** { 13300 .loc 1 830 8 is_stmt 1 view .LVU4222 830:Src/main.c **** { 13301 .loc 1 830 12 is_stmt 0 view .LVU4223 13302 0976 754B ldr r3, .L767+40 13303 0978 1B78 ldrb r3, [r3] @ zero_extendqisi2 830:Src/main.c **** { 13304 .loc 1 830 11 view .LVU4224 13305 097a 002B cmp r3, #0 13306 097c F1D0 beq .L711 832:Src/main.c **** //TIM11 -> CNT = 0; // to link modulator phase 13307 .loc 1 832 9 is_stmt 1 view .LVU4225 13308 097e FCEEE77A vcvt.u32.f32 s15, s15 13309 0982 17EE903A vmov r3, s15 @ int 13310 0986 99B2 uxth r1, r3 13311 0988 0120 movs r0, #1 13312 098a FFF7FEFF bl Set_LTEC 13313 .LVL1188: 835:Src/main.c **** TO10 = 0; 13314 .loc 1 835 9 view .LVU4226 835:Src/main.c **** TO10 = 0; 13315 .loc 1 835 13 is_stmt 0 view .LVU4227 13316 098e 654B ldr r3, .L767 13317 0990 D3ED047A vldr.32 s15, [r3, #16] 835:Src/main.c **** TO10 = 0; 13318 .loc 1 835 35 view .LVU4228 13319 0994 93ED037A vldr.32 s14, [r3, #12] 835:Src/main.c **** TO10 = 0; 13320 .loc 1 835 28 view .LVU4229 13321 0998 77EE877A vadd.f32 s15, s15, s14 13322 099c C3ED047A vstr.32 s15, [r3, #16] 836:Src/main.c **** TIM10_coflag = 0; 13323 .loc 1 836 9 is_stmt 1 view .LVU4230 836:Src/main.c **** TIM10_coflag = 0; 13324 .loc 1 836 14 is_stmt 0 view .LVU4231 13325 09a0 0027 movs r7, #0 13326 09a2 6B4B ldr r3, .L767+44 13327 09a4 1F60 str r7, [r3] 837:Src/main.c **** 13328 .loc 1 837 9 is_stmt 1 view .LVU4232 ARM GAS /tmp/ccLSPxIe.s page 660 837:Src/main.c **** 13329 .loc 1 837 22 is_stmt 0 view .LVU4233 13330 09a6 694B ldr r3, .L767+40 13331 09a8 1F70 strb r7, [r3] 839:Src/main.c **** HAL_GPIO_WritePin(GPIOG, GPIO_PIN_9, GPIO_PIN_RESET); 13332 .loc 1 839 9 is_stmt 1 view .LVU4234 13333 09aa DFF8C881 ldr r8, .L767+80 13334 09ae 0122 movs r2, #1 13335 09b0 4FF40071 mov r1, #512 13336 09b4 4046 mov r0, r8 13337 09b6 FFF7FEFF bl HAL_GPIO_WritePin 13338 .LVL1189: 840:Src/main.c **** //* 13339 .loc 1 840 9 view .LVU4235 13340 09ba 3A46 mov r2, r7 13341 09bc 4FF40071 mov r1, #512 13342 09c0 4046 mov r0, r8 13343 09c2 FFF7FEFF bl HAL_GPIO_WritePin 13344 .LVL1190: 842:Src/main.c **** OUT_trigger(trigger_counter); 13345 .loc 1 842 9 view .LVU4236 842:Src/main.c **** OUT_trigger(trigger_counter); 13346 .loc 1 842 41 is_stmt 0 view .LVU4237 13347 09c6 B4FBF6F3 udiv r3, r4, r6 13348 09ca 06FB1343 mls r3, r6, r3, r4 13349 09ce 9BB2 uxth r3, r3 842:Src/main.c **** OUT_trigger(trigger_counter); 13350 .loc 1 842 12 view .LVU4238 13351 09d0 1BB1 cbz r3, .L759 13352 .L712: 846:Src/main.c **** //*/ 13353 .loc 1 846 9 is_stmt 1 view .LVU4239 13354 09d2 0134 adds r4, r4, #1 13355 .LVL1191: 846:Src/main.c **** //*/ 13356 .loc 1 846 9 is_stmt 0 view .LVU4240 13357 09d4 A4B2 uxth r4, r4 13358 .LVL1192: 846:Src/main.c **** //*/ 13359 .loc 1 846 9 view .LVU4241 13360 09d6 C4E7 b .L711 13361 .LVL1193: 13362 .L709: 801:Src/main.c **** 13363 .loc 1 801 8 is_stmt 1 view .LVU4242 801:Src/main.c **** 13364 .loc 1 801 13 view .LVU4243 13365 09d8 FEE7 b .L709 13366 .LVL1194: 13367 .L759: 843:Src/main.c **** ++trigger_counter; 13368 .loc 1 843 10 view .LVU4244 13369 09da E8B2 uxtb r0, r5 13370 09dc FFF7FEFF bl OUT_trigger 13371 .LVL1195: 844:Src/main.c **** } 13372 .loc 1 844 10 view .LVU4245 ARM GAS /tmp/ccLSPxIe.s page 661 13373 09e0 0135 adds r5, r5, #1 13374 .LVL1196: 844:Src/main.c **** } 13375 .loc 1 844 10 is_stmt 0 view .LVU4246 13376 09e2 ADB2 uxth r5, r5 13377 .LVL1197: 844:Src/main.c **** } 13378 .loc 1 844 10 view .LVU4247 13379 09e4 F5E7 b .L712 13380 .L758: 871:Src/main.c **** //TIM11 -> CR1 |= 1 << 3; //sets timer to one-pulse mode. So it will turn off at the next Upd 13381 .loc 1 871 7 is_stmt 1 view .LVU4248 871:Src/main.c **** //TIM11 -> CR1 |= 1 << 3; //sets timer to one-pulse mode. So it will turn off at the next Upd 13382 .loc 1 871 13 is_stmt 0 view .LVU4249 13383 09e6 574A ldr r2, .L767+32 13384 09e8 D368 ldr r3, [r2, #12] 871:Src/main.c **** //TIM11 -> CR1 |= 1 << 3; //sets timer to one-pulse mode. So it will turn off at the next Upd 13385 .loc 1 871 21 view .LVU4250 13386 09ea 43F00103 orr r3, r3, #1 13387 09ee D360 str r3, [r2, #12] 881:Src/main.c **** 13388 .loc 1 881 7 is_stmt 1 view .LVU4251 13389 09f0 FFF7FEFF bl Stop_TIM10 13390 .LVL1198: 883:Src/main.c **** Set_LTEC(TT_CHANGE_CURR_1, task.current_param); 13391 .loc 1 883 7 view .LVU4252 883:Src/main.c **** Set_LTEC(TT_CHANGE_CURR_1, task.current_param); 13392 .loc 1 883 32 is_stmt 0 view .LVU4253 13393 09f4 4B4C ldr r4, .L767 13394 .LVL1199: 883:Src/main.c **** Set_LTEC(TT_CHANGE_CURR_1, task.current_param); 13395 .loc 1 883 32 view .LVU4254 13396 09f6 D4ED017A vldr.32 s15, [r4, #4] 883:Src/main.c **** Set_LTEC(TT_CHANGE_CURR_1, task.current_param); 13397 .loc 1 883 26 view .LVU4255 13398 09fa C4ED047A vstr.32 s15, [r4, #16] 884:Src/main.c **** if (task.tau > 3) 13399 .loc 1 884 7 is_stmt 1 view .LVU4256 13400 09fe FCEEE77A vcvt.u32.f32 s15, s15 13401 0a02 17EE903A vmov r3, s15 @ int 13402 0a06 99B2 uxth r1, r3 13403 0a08 0120 movs r0, #1 13404 0a0a FFF7FEFF bl Set_LTEC 13405 .LVL1200: 885:Src/main.c **** { 13406 .loc 1 885 7 view .LVU4257 885:Src/main.c **** { 13407 .loc 1 885 15 is_stmt 0 view .LVU4258 13408 0a0e E38A ldrh r3, [r4, #22] 885:Src/main.c **** { 13409 .loc 1 885 10 view .LVU4259 13410 0a10 032B cmp r3, #3 13411 0a12 0CD9 bls .L714 887:Src/main.c **** htim10.Init.Period = 9999; 13412 .loc 1 887 8 is_stmt 1 view .LVU4260 887:Src/main.c **** htim10.Init.Period = 9999; 13413 .loc 1 887 34 is_stmt 0 view .LVU4261 ARM GAS /tmp/ccLSPxIe.s page 662 13414 0a14 4A4A ldr r2, .L767+28 13415 0a16 D068 ldr r0, [r2, #12] 887:Src/main.c **** htim10.Init.Period = 9999; 13416 .loc 1 887 21 view .LVU4262 13417 0a18 4E49 ldr r1, .L767+48 13418 0a1a 0860 str r0, [r1] 888:Src/main.c **** TO10_counter = (task.tau - 1) * 100; 13419 .loc 1 888 8 is_stmt 1 view .LVU4263 888:Src/main.c **** TO10_counter = (task.tau - 1) * 100; 13420 .loc 1 888 27 is_stmt 0 view .LVU4264 13421 0a1c 42F20F71 movw r1, #9999 13422 0a20 D160 str r1, [r2, #12] 889:Src/main.c **** } 13423 .loc 1 889 8 is_stmt 1 view .LVU4265 889:Src/main.c **** } 13424 .loc 1 889 33 is_stmt 0 view .LVU4266 13425 0a22 013B subs r3, r3, #1 889:Src/main.c **** } 13426 .loc 1 889 38 view .LVU4267 13427 0a24 6422 movs r2, #100 13428 0a26 02FB03F3 mul r3, r2, r3 889:Src/main.c **** } 13429 .loc 1 889 21 view .LVU4268 13430 0a2a 4B4A ldr r2, .L767+52 13431 0a2c 1360 str r3, [r2] 13432 .L714: 891:Src/main.c **** break; 13433 .loc 1 891 7 is_stmt 1 view .LVU4269 13434 0a2e 4448 ldr r0, .L767+28 13435 0a30 FFF7FEFF bl HAL_TIM_Base_Start_IT 13436 .LVL1201: 892:Src/main.c **** case TT_CHANGE_CURR_2: 13437 .loc 1 892 6 view .LVU4270 13438 0a34 D2E6 b .L707 13439 .LVL1202: 13440 .L706: 896:Src/main.c **** (void) MPhD_T(TT_CHANGE_TEMP_1); 13441 .loc 1 896 7 view .LVU4271 896:Src/main.c **** (void) MPhD_T(TT_CHANGE_TEMP_1); 13442 .loc 1 896 38 is_stmt 0 view .LVU4272 13443 0a36 3B4B ldr r3, .L767 13444 0a38 D3ED077A vldr.32 s15, [r3, #28] 896:Src/main.c **** (void) MPhD_T(TT_CHANGE_TEMP_1); 13445 .loc 1 896 7 view .LVU4273 13446 0a3c FCEEE77A vcvt.u32.f32 s15, s15 13447 0a40 17EE903A vmov r3, s15 @ int 13448 0a44 99B2 uxth r1, r3 13449 0a46 0120 movs r0, #1 13450 0a48 FFF7FEFF bl Set_LTEC 13451 .LVL1203: 897:Src/main.c **** LD1_param.LD_CURR_TEMP = MPhD_T(TT_CHANGE_TEMP_1); 13452 .loc 1 897 7 is_stmt 1 view .LVU4274 897:Src/main.c **** LD1_param.LD_CURR_TEMP = MPhD_T(TT_CHANGE_TEMP_1); 13453 .loc 1 897 14 is_stmt 0 view .LVU4275 13454 0a4c 0320 movs r0, #3 13455 0a4e FFF7FEFF bl MPhD_T 13456 .LVL1204: ARM GAS /tmp/ccLSPxIe.s page 663 898:Src/main.c **** (void) MPhD_T(TT_CHANGE_TEMP_2); 13457 .loc 1 898 7 is_stmt 1 view .LVU4276 898:Src/main.c **** (void) MPhD_T(TT_CHANGE_TEMP_2); 13458 .loc 1 898 32 is_stmt 0 view .LVU4277 13459 0a52 0320 movs r0, #3 13460 0a54 FFF7FEFF bl MPhD_T 13461 .LVL1205: 898:Src/main.c **** (void) MPhD_T(TT_CHANGE_TEMP_2); 13462 .loc 1 898 30 discriminator 1 view .LVU4278 13463 0a58 334C ldr r4, .L767+4 13464 0a5a 2080 strh r0, [r4] @ movhi 899:Src/main.c **** LD2_param.LD_CURR_TEMP = MPhD_T(TT_CHANGE_TEMP_2); 13465 .loc 1 899 7 is_stmt 1 view .LVU4279 899:Src/main.c **** LD2_param.LD_CURR_TEMP = MPhD_T(TT_CHANGE_TEMP_2); 13466 .loc 1 899 14 is_stmt 0 view .LVU4280 13467 0a5c 0420 movs r0, #4 13468 0a5e FFF7FEFF bl MPhD_T 13469 .LVL1206: 900:Src/main.c **** temp16=PID_Controller_Temp(&LD1_curr_setup, &LD1_param, 1); 13470 .loc 1 900 7 is_stmt 1 view .LVU4281 900:Src/main.c **** temp16=PID_Controller_Temp(&LD1_curr_setup, &LD1_param, 1); 13471 .loc 1 900 32 is_stmt 0 view .LVU4282 13472 0a62 0420 movs r0, #4 13473 0a64 FFF7FEFF bl MPhD_T 13474 .LVL1207: 900:Src/main.c **** temp16=PID_Controller_Temp(&LD1_curr_setup, &LD1_param, 1); 13475 .loc 1 900 30 discriminator 1 view .LVU4283 13476 0a68 304D ldr r5, .L767+8 13477 0a6a 2880 strh r0, [r5] @ movhi 901:Src/main.c **** Set_LTEC(TT_CHANGE_TEMP_1, temp16);//Drive Laser TEC 1 13478 .loc 1 901 7 is_stmt 1 view .LVU4284 901:Src/main.c **** Set_LTEC(TT_CHANGE_TEMP_1, temp16);//Drive Laser TEC 1 13479 .loc 1 901 14 is_stmt 0 view .LVU4285 13480 0a6c 0122 movs r2, #1 13481 0a6e 2146 mov r1, r4 13482 0a70 2F48 ldr r0, .L767+12 13483 0a72 FFF7FEFF bl PID_Controller_Temp 13484 .LVL1208: 13485 0a76 0146 mov r1, r0 901:Src/main.c **** Set_LTEC(TT_CHANGE_TEMP_1, temp16);//Drive Laser TEC 1 13486 .loc 1 901 13 discriminator 1 view .LVU4286 13487 0a78 2E4C ldr r4, .L767+16 13488 0a7a 2080 strh r0, [r4] @ movhi 902:Src/main.c **** temp16=PID_Controller_Temp(&LD2_curr_setup, &LD2_param, 2); 13489 .loc 1 902 7 is_stmt 1 view .LVU4287 13490 0a7c 0320 movs r0, #3 13491 0a7e FFF7FEFF bl Set_LTEC 13492 .LVL1209: 903:Src/main.c **** Set_LTEC(TT_CHANGE_TEMP_2, temp16);//Drive Laser TEC 2 13493 .loc 1 903 7 view .LVU4288 903:Src/main.c **** Set_LTEC(TT_CHANGE_TEMP_2, temp16);//Drive Laser TEC 2 13494 .loc 1 903 14 is_stmt 0 view .LVU4289 13495 0a82 0222 movs r2, #2 13496 0a84 2946 mov r1, r5 13497 0a86 2C48 ldr r0, .L767+20 13498 0a88 FFF7FEFF bl PID_Controller_Temp 13499 .LVL1210: ARM GAS /tmp/ccLSPxIe.s page 664 13500 0a8c 0146 mov r1, r0 903:Src/main.c **** Set_LTEC(TT_CHANGE_TEMP_2, temp16);//Drive Laser TEC 2 13501 .loc 1 903 13 discriminator 1 view .LVU4290 13502 0a8e 2080 strh r0, [r4] @ movhi 904:Src/main.c **** 13503 .loc 1 904 7 is_stmt 1 view .LVU4291 13504 0a90 0420 movs r0, #4 13505 0a92 FFF7FEFF bl Set_LTEC 13506 .LVL1211: 906:Src/main.c **** LD_blinker.state = 0; // 0 -- disabled (do nothing); 1 -- update LD current; 2 -- blinking, L 13507 .loc 1 906 7 view .LVU4292 906:Src/main.c **** LD_blinker.state = 0; // 0 -- disabled (do nothing); 1 -- update LD current; 2 -- blinking, L 13508 .loc 1 906 28 is_stmt 0 view .LVU4293 13509 0a96 314B ldr r3, .L767+56 13510 0a98 0222 movs r2, #2 13511 0a9a 1A70 strb r2, [r3] 907:Src/main.c **** //LD_blinker.param = task.current_param; 13512 .loc 1 907 7 is_stmt 1 view .LVU4294 907:Src/main.c **** //LD_blinker.param = task.current_param; 13513 .loc 1 907 24 is_stmt 0 view .LVU4295 13514 0a9c 0022 movs r2, #0 13515 0a9e 9A72 strb r2, [r3, #10] 909:Src/main.c **** LD_blinker.param = 1000; // LD2 current (in unspecified units) 13516 .loc 1 909 7 is_stmt 1 view .LVU4296 909:Src/main.c **** LD_blinker.param = 1000; // LD2 current (in unspecified units) 13517 .loc 1 909 24 is_stmt 0 view .LVU4297 13518 0aa0 1A81 strh r2, [r3, #8] @ movhi 910:Src/main.c **** LD_blinker.signal_port = OUT_9_GPIO_Port; 13519 .loc 1 910 7 is_stmt 1 view .LVU4298 910:Src/main.c **** LD_blinker.signal_port = OUT_9_GPIO_Port; 13520 .loc 1 910 24 is_stmt 0 view .LVU4299 13521 0aa2 4FF47A72 mov r2, #1000 13522 0aa6 1A81 strh r2, [r3, #8] @ movhi 911:Src/main.c **** LD_blinker.signal_pin = OUT_9_Pin; 13523 .loc 1 911 7 is_stmt 1 view .LVU4300 911:Src/main.c **** LD_blinker.signal_pin = OUT_9_Pin; 13524 .loc 1 911 30 is_stmt 0 view .LVU4301 13525 0aa8 2D4A ldr r2, .L767+60 13526 0aaa 5A60 str r2, [r3, #4] 912:Src/main.c **** 13527 .loc 1 912 7 is_stmt 1 view .LVU4302 912:Src/main.c **** 13528 .loc 1 912 29 is_stmt 0 view .LVU4303 13529 0aac 8022 movs r2, #128 13530 0aae 5A80 strh r2, [r3, #2] @ movhi 914:Src/main.c **** //When it is too low -- Desktop app crashes (there is not so much compute sources on MCU 13531 .loc 1 914 7 is_stmt 1 view .LVU4304 914:Src/main.c **** //When it is too low -- Desktop app crashes (there is not so much compute sources on MCU 13532 .loc 1 914 17 is_stmt 0 view .LVU4305 13533 0ab0 2C4B ldr r3, .L767+64 13534 0ab2 42F21072 movw r2, #10000 13535 0ab6 DA62 str r2, [r3, #44] 916:Src/main.c **** if (st != HAL_OK) 13536 .loc 1 916 7 is_stmt 1 view .LVU4306 916:Src/main.c **** if (st != HAL_OK) 13537 .loc 1 916 12 is_stmt 0 view .LVU4307 13538 0ab8 2B48 ldr r0, .L767+68 ARM GAS /tmp/ccLSPxIe.s page 665 13539 0aba FFF7FEFF bl HAL_TIM_Base_Start_IT 13540 .LVL1212: 917:Src/main.c **** while(1); 13541 .loc 1 917 7 is_stmt 1 view .LVU4308 917:Src/main.c **** while(1); 13542 .loc 1 917 10 is_stmt 0 view .LVU4309 13543 0abe 78BB cbnz r0, .L716 922:Src/main.c **** uint32_t i = 10000; while (--i){} 13544 .loc 1 922 7 is_stmt 1 view .LVU4310 13545 0ac0 0122 movs r2, #1 13546 0ac2 8021 movs r1, #128 13547 0ac4 1D48 ldr r0, .L767+24 13548 .LVL1213: 922:Src/main.c **** uint32_t i = 10000; while (--i){} 13549 .loc 1 922 7 is_stmt 0 view .LVU4311 13550 0ac6 FFF7FEFF bl HAL_GPIO_WritePin 13551 .LVL1214: 923:Src/main.c **** HAL_GPIO_WritePin(GPIOD, GPIO_PIN_7, GPIO_PIN_RESET); 13552 .loc 1 923 7 is_stmt 1 view .LVU4312 923:Src/main.c **** HAL_GPIO_WritePin(GPIOD, GPIO_PIN_7, GPIO_PIN_RESET); 13553 .loc 1 923 27 view .LVU4313 923:Src/main.c **** HAL_GPIO_WritePin(GPIOD, GPIO_PIN_7, GPIO_PIN_RESET); 13554 .loc 1 923 16 is_stmt 0 view .LVU4314 13555 0aca 42F21073 movw r3, #10000 13556 .LVL1215: 13557 .L717: 923:Src/main.c **** HAL_GPIO_WritePin(GPIOD, GPIO_PIN_7, GPIO_PIN_RESET); 13558 .loc 1 923 39 is_stmt 1 discriminator 2 view .LVU4315 923:Src/main.c **** HAL_GPIO_WritePin(GPIOD, GPIO_PIN_7, GPIO_PIN_RESET); 13559 .loc 1 923 34 discriminator 2 view .LVU4316 923:Src/main.c **** HAL_GPIO_WritePin(GPIOD, GPIO_PIN_7, GPIO_PIN_RESET); 13560 .loc 1 923 34 is_stmt 0 discriminator 2 view .LVU4317 13561 0ace 013B subs r3, r3, #1 13562 .LVL1216: 923:Src/main.c **** HAL_GPIO_WritePin(GPIOD, GPIO_PIN_7, GPIO_PIN_RESET); 13563 .loc 1 923 34 discriminator 2 view .LVU4318 13564 0ad0 FDD1 bne .L717 924:Src/main.c **** LD_blinker.state = 2; 13565 .loc 1 924 7 is_stmt 1 view .LVU4319 13566 0ad2 0022 movs r2, #0 13567 0ad4 8021 movs r1, #128 13568 0ad6 1948 ldr r0, .L767+24 13569 0ad8 FFF7FEFF bl HAL_GPIO_WritePin 13570 .LVL1217: 925:Src/main.c **** 13571 .loc 1 925 7 view .LVU4320 925:Src/main.c **** 13572 .loc 1 925 24 is_stmt 0 view .LVU4321 13573 0adc 1F4B ldr r3, .L767+56 13574 0ade 0222 movs r2, #2 13575 0ae0 9A72 strb r2, [r3, #10] 927:Src/main.c **** if (st != HAL_OK) 13576 .loc 1 927 7 is_stmt 1 view .LVU4322 927:Src/main.c **** if (st != HAL_OK) 13577 .loc 1 927 12 is_stmt 0 view .LVU4323 13578 0ae2 1748 ldr r0, .L767+28 13579 0ae4 FFF7FEFF bl HAL_TIM_Base_Start_IT ARM GAS /tmp/ccLSPxIe.s page 666 13580 .LVL1218: 928:Src/main.c **** while(1); 13581 .loc 1 928 7 is_stmt 1 view .LVU4324 928:Src/main.c **** while(1); 13582 .loc 1 928 10 is_stmt 0 view .LVU4325 13583 0ae8 D8B9 cbnz r0, .L719 13584 .L720: 930:Src/main.c **** { 13585 .loc 1 930 33 is_stmt 1 view .LVU4326 930:Src/main.c **** { 13586 .loc 1 930 18 is_stmt 0 view .LVU4327 13587 0aea 0E4B ldr r3, .L767 13588 0aec D3ED047A vldr.32 s15, [r3, #16] 930:Src/main.c **** { 13589 .loc 1 930 39 view .LVU4328 13590 0af0 93ED027A vldr.32 s14, [r3, #8] 930:Src/main.c **** { 13591 .loc 1 930 33 view .LVU4329 13592 0af4 F4EEC77A vcmpe.f32 s15, s14 13593 0af8 F1EE10FA vmrs APSR_nzcv, FPSCR 13594 0afc 3CD5 bpl .L760 932:Src/main.c **** { 13595 .loc 1 932 8 is_stmt 1 view .LVU4330 932:Src/main.c **** { 13596 .loc 1 932 12 is_stmt 0 view .LVU4331 13597 0afe 134B ldr r3, .L767+40 13598 0b00 1B78 ldrb r3, [r3] @ zero_extendqisi2 932:Src/main.c **** { 13599 .loc 1 932 11 view .LVU4332 13600 0b02 002B cmp r3, #0 13601 0b04 F1D0 beq .L720 937:Src/main.c **** TO10 = 0; 13602 .loc 1 937 9 is_stmt 1 view .LVU4333 937:Src/main.c **** TO10 = 0; 13603 .loc 1 937 35 is_stmt 0 view .LVU4334 13604 0b06 074B ldr r3, .L767 13605 0b08 93ED037A vldr.32 s14, [r3, #12] 937:Src/main.c **** TO10 = 0; 13606 .loc 1 937 28 view .LVU4335 13607 0b0c 77EE277A vadd.f32 s15, s14, s15 13608 0b10 C3ED047A vstr.32 s15, [r3, #16] 938:Src/main.c **** TIM10_coflag = 0; 13609 .loc 1 938 9 is_stmt 1 view .LVU4336 938:Src/main.c **** TIM10_coflag = 0; 13610 .loc 1 938 14 is_stmt 0 view .LVU4337 13611 0b14 0023 movs r3, #0 13612 0b16 0E4A ldr r2, .L767+44 13613 0b18 1360 str r3, [r2] 939:Src/main.c **** 13614 .loc 1 939 9 is_stmt 1 view .LVU4338 939:Src/main.c **** 13615 .loc 1 939 22 is_stmt 0 view .LVU4339 13616 0b1a 0C4A ldr r2, .L767+40 13617 0b1c 1370 strb r3, [r2] 13618 0b1e E4E7 b .L720 13619 .LVL1219: 13620 .L716: ARM GAS /tmp/ccLSPxIe.s page 667 918:Src/main.c **** // */ 13621 .loc 1 918 8 is_stmt 1 view .LVU4340 918:Src/main.c **** // */ 13622 .loc 1 918 13 view .LVU4341 13623 0b20 FEE7 b .L716 13624 .LVL1220: 13625 .L719: 929:Src/main.c **** while (task.current_param < task.max_param) 13626 .loc 1 929 8 view .LVU4342 929:Src/main.c **** while (task.current_param < task.max_param) 13627 .loc 1 929 13 view .LVU4343 13628 0b22 FEE7 b .L719 13629 .L768: 13630 .align 2 13631 .L767: 13632 0b24 00000000 .word task 13633 0b28 00000000 .word LD1_param 13634 0b2c 00000000 .word LD2_param 13635 0b30 00000000 .word LD1_curr_setup 13636 0b34 00000000 .word temp16 13637 0b38 00000000 .word LD2_curr_setup 13638 0b3c 000C0240 .word 1073875968 13639 0b40 00000000 .word htim10 13640 0b44 00480140 .word 1073825792 13641 0b48 00080040 .word 1073743872 13642 0b4c 00000000 .word TIM10_coflag 13643 0b50 00000000 .word TO10 13644 0b54 00000000 .word TIM10_period 13645 0b58 00000000 .word TO10_counter 13646 0b5c 00000000 .word LD_blinker 13647 0b60 00040240 .word 1073873920 13648 0b64 00040140 .word 1073808384 13649 0b68 00000000 .word htim8 13650 0b6c 00000000 .word htim11 13651 0b70 00000000 .word htim4 13652 0b74 00180240 .word 1073879040 13653 .L760: 944:Src/main.c **** HAL_GPIO_WritePin(GPIOD, GPIO_PIN_7, GPIO_PIN_SET); 13654 .loc 1 944 7 view .LVU4344 13655 0b78 6C48 ldr r0, .L769 13656 .LVL1221: 944:Src/main.c **** HAL_GPIO_WritePin(GPIOD, GPIO_PIN_7, GPIO_PIN_SET); 13657 .loc 1 944 7 is_stmt 0 view .LVU4345 13658 0b7a FFF7FEFF bl HAL_TIM_Base_Stop 13659 .LVL1222: 945:Src/main.c **** 13660 .loc 1 945 7 is_stmt 1 view .LVU4346 13661 0b7e 6C4C ldr r4, .L769+4 13662 0b80 0122 movs r2, #1 13663 0b82 8021 movs r1, #128 13664 0b84 2046 mov r0, r4 13665 0b86 FFF7FEFF bl HAL_GPIO_WritePin 13666 .LVL1223: 947:Src/main.c **** 13667 .loc 1 947 7 view .LVU4347 13668 0b8a 0022 movs r2, #0 13669 0b8c 8021 movs r1, #128 ARM GAS /tmp/ccLSPxIe.s page 668 13670 0b8e 2046 mov r0, r4 13671 0b90 FFF7FEFF bl HAL_GPIO_WritePin 13672 .LVL1224: 949:Src/main.c **** TIM8->CNT = 0; 13673 .loc 1 949 7 view .LVU4348 13674 0b94 6748 ldr r0, .L769+8 13675 0b96 FFF7FEFF bl HAL_TIM_Base_Stop_IT 13676 .LVL1225: 950:Src/main.c **** 13677 .loc 1 950 7 view .LVU4349 950:Src/main.c **** 13678 .loc 1 950 17 is_stmt 0 view .LVU4350 13679 0b9a 674B ldr r3, .L769+12 13680 0b9c 0022 movs r2, #0 13681 0b9e 5A62 str r2, [r3, #36] 952:Src/main.c **** task.current_param = task.min_param; 13682 .loc 1 952 7 is_stmt 1 view .LVU4351 13683 0ba0 FFF7FEFF bl Stop_TIM10 13684 .LVL1226: 953:Src/main.c **** Set_LTEC(TT_CHANGE_CURR_2, task.current_param); 13685 .loc 1 953 7 view .LVU4352 953:Src/main.c **** Set_LTEC(TT_CHANGE_CURR_2, task.current_param); 13686 .loc 1 953 32 is_stmt 0 view .LVU4353 13687 0ba4 654C ldr r4, .L769+16 13688 0ba6 D4ED017A vldr.32 s15, [r4, #4] 953:Src/main.c **** Set_LTEC(TT_CHANGE_CURR_2, task.current_param); 13689 .loc 1 953 26 view .LVU4354 13690 0baa C4ED047A vstr.32 s15, [r4, #16] 954:Src/main.c **** if (task.tau > 3) 13691 .loc 1 954 7 is_stmt 1 view .LVU4355 13692 0bae FCEEE77A vcvt.u32.f32 s15, s15 13693 0bb2 17EE903A vmov r3, s15 @ int 13694 0bb6 99B2 uxth r1, r3 13695 0bb8 0220 movs r0, #2 13696 0bba FFF7FEFF bl Set_LTEC 13697 .LVL1227: 955:Src/main.c **** { 13698 .loc 1 955 7 view .LVU4356 955:Src/main.c **** { 13699 .loc 1 955 15 is_stmt 0 view .LVU4357 13700 0bbe E38A ldrh r3, [r4, #22] 955:Src/main.c **** { 13701 .loc 1 955 10 view .LVU4358 13702 0bc0 032B cmp r3, #3 13703 0bc2 0CD9 bls .L722 957:Src/main.c **** htim10.Init.Period = 9999; 13704 .loc 1 957 8 is_stmt 1 view .LVU4359 957:Src/main.c **** htim10.Init.Period = 9999; 13705 .loc 1 957 34 is_stmt 0 view .LVU4360 13706 0bc4 594A ldr r2, .L769 13707 0bc6 D068 ldr r0, [r2, #12] 957:Src/main.c **** htim10.Init.Period = 9999; 13708 .loc 1 957 21 view .LVU4361 13709 0bc8 5D49 ldr r1, .L769+20 13710 0bca 0860 str r0, [r1] 958:Src/main.c **** TO10_counter = (task.tau - 1) * 100; 13711 .loc 1 958 8 is_stmt 1 view .LVU4362 ARM GAS /tmp/ccLSPxIe.s page 669 958:Src/main.c **** TO10_counter = (task.tau - 1) * 100; 13712 .loc 1 958 27 is_stmt 0 view .LVU4363 13713 0bcc 42F20F71 movw r1, #9999 13714 0bd0 D160 str r1, [r2, #12] 959:Src/main.c **** } 13715 .loc 1 959 8 is_stmt 1 view .LVU4364 959:Src/main.c **** } 13716 .loc 1 959 33 is_stmt 0 view .LVU4365 13717 0bd2 013B subs r3, r3, #1 959:Src/main.c **** } 13718 .loc 1 959 38 view .LVU4366 13719 0bd4 6422 movs r2, #100 13720 0bd6 02FB03F3 mul r3, r2, r3 959:Src/main.c **** } 13721 .loc 1 959 21 view .LVU4367 13722 0bda 5A4A ldr r2, .L769+24 13723 0bdc 1360 str r3, [r2] 13724 .L722: 961:Src/main.c **** 13725 .loc 1 961 7 is_stmt 1 view .LVU4368 13726 0bde 5348 ldr r0, .L769 13727 0be0 FFF7FEFF bl HAL_TIM_Base_Start_IT 13728 .LVL1228: 1009:Src/main.c **** case TT_CHANGE_TEMP_1: 13729 .loc 1 1009 6 view .LVU4369 13730 0be4 FAE5 b .L707 13731 .LVL1229: 13732 .L757: 1009:Src/main.c **** case TT_CHANGE_TEMP_1: 13733 .loc 1 1009 6 is_stmt 0 view .LVU4370 13734 .LBE721: 1020:Src/main.c **** 13735 .loc 1 1020 7 is_stmt 1 view .LVU4371 1020:Src/main.c **** 13736 .loc 1 1020 18 is_stmt 0 view .LVU4372 13737 0be6 584A ldr r2, .L769+28 13738 0be8 1360 str r3, [r2] 1022:Src/main.c **** LD1_param.POWER = MPhD_T(1);//Get Data from monitor photodiode of LD1 13739 .loc 1 1022 7 is_stmt 1 view .LVU4373 1022:Src/main.c **** LD1_param.POWER = MPhD_T(1);//Get Data from monitor photodiode of LD1 13740 .loc 1 1022 25 is_stmt 0 view .LVU4374 13741 0bea 0120 movs r0, #1 13742 0bec FFF7FEFF bl MPhD_T 13743 .LVL1230: 1022:Src/main.c **** LD1_param.POWER = MPhD_T(1);//Get Data from monitor photodiode of LD1 13744 .loc 1 1022 23 discriminator 1 view .LVU4375 13745 0bf0 564E ldr r6, .L769+32 13746 0bf2 3081 strh r0, [r6, #8] @ movhi 1023:Src/main.c **** LD2_param.POWER = MPhD_T(2);//Get Data from monitor photodiode of LD2 13747 .loc 1 1023 7 is_stmt 1 view .LVU4376 1023:Src/main.c **** LD2_param.POWER = MPhD_T(2);//Get Data from monitor photodiode of LD2 13748 .loc 1 1023 25 is_stmt 0 view .LVU4377 13749 0bf4 0120 movs r0, #1 13750 0bf6 FFF7FEFF bl MPhD_T 13751 .LVL1231: 1023:Src/main.c **** LD2_param.POWER = MPhD_T(2);//Get Data from monitor photodiode of LD2 13752 .loc 1 1023 23 discriminator 1 view .LVU4378 ARM GAS /tmp/ccLSPxIe.s page 670 13753 0bfa 3081 strh r0, [r6, #8] @ movhi 1024:Src/main.c **** LD2_param.POWER = MPhD_T(2);//Get Data from monitor photodiode of LD2 13754 .loc 1 1024 7 is_stmt 1 view .LVU4379 1024:Src/main.c **** LD2_param.POWER = MPhD_T(2);//Get Data from monitor photodiode of LD2 13755 .loc 1 1024 25 is_stmt 0 view .LVU4380 13756 0bfc 0220 movs r0, #2 13757 0bfe FFF7FEFF bl MPhD_T 13758 .LVL1232: 1024:Src/main.c **** LD2_param.POWER = MPhD_T(2);//Get Data from monitor photodiode of LD2 13759 .loc 1 1024 23 discriminator 1 view .LVU4381 13760 0c02 534F ldr r7, .L769+36 13761 0c04 3881 strh r0, [r7, #8] @ movhi 1025:Src/main.c **** 13762 .loc 1 1025 7 is_stmt 1 view .LVU4382 1025:Src/main.c **** 13763 .loc 1 1025 25 is_stmt 0 view .LVU4383 13764 0c06 0220 movs r0, #2 13765 0c08 FFF7FEFF bl MPhD_T 13766 .LVL1233: 1025:Src/main.c **** 13767 .loc 1 1025 23 discriminator 1 view .LVU4384 13768 0c0c 3881 strh r0, [r7, #8] @ movhi 1027:Src/main.c **** Long_Data[2] = LD2_param.POWER;//Translate Data from monitor photodiode of LD2 to Long_Data 13769 .loc 1 1027 7 is_stmt 1 view .LVU4385 1027:Src/main.c **** Long_Data[2] = LD2_param.POWER;//Translate Data from monitor photodiode of LD2 to Long_Data 13770 .loc 1 1027 31 is_stmt 0 view .LVU4386 13771 0c0e 3389 ldrh r3, [r6, #8] 1027:Src/main.c **** Long_Data[2] = LD2_param.POWER;//Translate Data from monitor photodiode of LD2 to Long_Data 13772 .loc 1 1027 20 view .LVU4387 13773 0c10 504C ldr r4, .L769+40 13774 0c12 6380 strh r3, [r4, #2] @ movhi 1028:Src/main.c **** 13775 .loc 1 1028 7 is_stmt 1 view .LVU4388 1028:Src/main.c **** 13776 .loc 1 1028 20 is_stmt 0 view .LVU4389 13777 0c14 A080 strh r0, [r4, #4] @ movhi 1032:Src/main.c **** temp16 = Get_ADC(1); 13778 .loc 1 1032 7 is_stmt 1 view .LVU4390 1032:Src/main.c **** temp16 = Get_ADC(1); 13779 .loc 1 1032 16 is_stmt 0 view .LVU4391 13780 0c16 0020 movs r0, #0 13781 0c18 FFF7FEFF bl Get_ADC 13782 .LVL1234: 1032:Src/main.c **** temp16 = Get_ADC(1); 13783 .loc 1 1032 14 discriminator 1 view .LVU4392 13784 0c1c 4E4D ldr r5, .L769+44 13785 0c1e 2880 strh r0, [r5] @ movhi 1033:Src/main.c **** Long_Data[7] = temp16; 13786 .loc 1 1033 7 is_stmt 1 view .LVU4393 1033:Src/main.c **** Long_Data[7] = temp16; 13787 .loc 1 1033 16 is_stmt 0 view .LVU4394 13788 0c20 0120 movs r0, #1 13789 0c22 FFF7FEFF bl Get_ADC 13790 .LVL1235: 1033:Src/main.c **** Long_Data[7] = temp16; 13791 .loc 1 1033 14 discriminator 1 view .LVU4395 13792 0c26 2880 strh r0, [r5] @ movhi ARM GAS /tmp/ccLSPxIe.s page 671 1034:Src/main.c **** 13793 .loc 1 1034 7 is_stmt 1 view .LVU4396 1034:Src/main.c **** 13794 .loc 1 1034 20 is_stmt 0 view .LVU4397 13795 0c28 E081 strh r0, [r4, #14] @ movhi 1037:Src/main.c **** Long_Data[8] = temp16; 13796 .loc 1 1037 7 is_stmt 1 view .LVU4398 1037:Src/main.c **** Long_Data[8] = temp16; 13797 .loc 1 1037 16 is_stmt 0 view .LVU4399 13798 0c2a 0120 movs r0, #1 13799 0c2c FFF7FEFF bl Get_ADC 13800 .LVL1236: 1037:Src/main.c **** Long_Data[8] = temp16; 13801 .loc 1 1037 14 discriminator 1 view .LVU4400 13802 0c30 2880 strh r0, [r5] @ movhi 1038:Src/main.c **** 13803 .loc 1 1038 7 is_stmt 1 view .LVU4401 1038:Src/main.c **** 13804 .loc 1 1038 20 is_stmt 0 view .LVU4402 13805 0c32 2082 strh r0, [r4, #16] @ movhi 1041:Src/main.c **** Long_Data[9] = temp16; 13806 .loc 1 1041 7 is_stmt 1 view .LVU4403 1041:Src/main.c **** Long_Data[9] = temp16; 13807 .loc 1 1041 16 is_stmt 0 view .LVU4404 13808 0c34 0120 movs r0, #1 13809 0c36 FFF7FEFF bl Get_ADC 13810 .LVL1237: 1041:Src/main.c **** Long_Data[9] = temp16; 13811 .loc 1 1041 14 discriminator 1 view .LVU4405 13812 0c3a 2880 strh r0, [r5] @ movhi 1042:Src/main.c **** 13813 .loc 1 1042 7 is_stmt 1 view .LVU4406 1042:Src/main.c **** 13814 .loc 1 1042 20 is_stmt 0 view .LVU4407 13815 0c3c 6082 strh r0, [r4, #18] @ movhi 1045:Src/main.c **** Long_Data[10] = temp16; 13816 .loc 1 1045 7 is_stmt 1 view .LVU4408 1045:Src/main.c **** Long_Data[10] = temp16; 13817 .loc 1 1045 16 is_stmt 0 view .LVU4409 13818 0c3e 0120 movs r0, #1 13819 0c40 FFF7FEFF bl Get_ADC 13820 .LVL1238: 1045:Src/main.c **** Long_Data[10] = temp16; 13821 .loc 1 1045 14 discriminator 1 view .LVU4410 13822 0c44 2880 strh r0, [r5] @ movhi 1046:Src/main.c **** 13823 .loc 1 1046 7 is_stmt 1 view .LVU4411 1046:Src/main.c **** 13824 .loc 1 1046 21 is_stmt 0 view .LVU4412 13825 0c46 A082 strh r0, [r4, #20] @ movhi 1049:Src/main.c **** Long_Data[11] = temp16; 13826 .loc 1 1049 7 is_stmt 1 view .LVU4413 1049:Src/main.c **** Long_Data[11] = temp16; 13827 .loc 1 1049 16 is_stmt 0 view .LVU4414 13828 0c48 0120 movs r0, #1 13829 0c4a FFF7FEFF bl Get_ADC 13830 .LVL1239: ARM GAS /tmp/ccLSPxIe.s page 672 1049:Src/main.c **** Long_Data[11] = temp16; 13831 .loc 1 1049 14 discriminator 1 view .LVU4415 13832 0c4e 2880 strh r0, [r5] @ movhi 1050:Src/main.c **** temp16 = Get_ADC(2); 13833 .loc 1 1050 7 is_stmt 1 view .LVU4416 1050:Src/main.c **** temp16 = Get_ADC(2); 13834 .loc 1 1050 21 is_stmt 0 view .LVU4417 13835 0c50 E082 strh r0, [r4, #22] @ movhi 1051:Src/main.c **** 13836 .loc 1 1051 7 is_stmt 1 view .LVU4418 1051:Src/main.c **** 13837 .loc 1 1051 16 is_stmt 0 view .LVU4419 13838 0c52 0220 movs r0, #2 13839 0c54 FFF7FEFF bl Get_ADC 13840 .LVL1240: 1051:Src/main.c **** 13841 .loc 1 1051 14 discriminator 1 view .LVU4420 13842 0c58 2880 strh r0, [r5] @ movhi 1054:Src/main.c **** temp16 = Get_ADC(4); 13843 .loc 1 1054 7 is_stmt 1 view .LVU4421 1054:Src/main.c **** temp16 = Get_ADC(4); 13844 .loc 1 1054 16 is_stmt 0 view .LVU4422 13845 0c5a 0320 movs r0, #3 13846 0c5c FFF7FEFF bl Get_ADC 13847 .LVL1241: 1054:Src/main.c **** temp16 = Get_ADC(4); 13848 .loc 1 1054 14 discriminator 1 view .LVU4423 13849 0c60 2880 strh r0, [r5] @ movhi 1055:Src/main.c **** Long_Data[12] = temp16; 13850 .loc 1 1055 7 is_stmt 1 view .LVU4424 1055:Src/main.c **** Long_Data[12] = temp16; 13851 .loc 1 1055 16 is_stmt 0 view .LVU4425 13852 0c62 0420 movs r0, #4 13853 0c64 FFF7FEFF bl Get_ADC 13854 .LVL1242: 1055:Src/main.c **** Long_Data[12] = temp16; 13855 .loc 1 1055 14 discriminator 1 view .LVU4426 13856 0c68 2880 strh r0, [r5] @ movhi 1056:Src/main.c **** temp16 = Get_ADC(5); 13857 .loc 1 1056 7 is_stmt 1 view .LVU4427 1056:Src/main.c **** temp16 = Get_ADC(5); 13858 .loc 1 1056 21 is_stmt 0 view .LVU4428 13859 0c6a 2083 strh r0, [r4, #24] @ movhi 1057:Src/main.c **** 13860 .loc 1 1057 7 is_stmt 1 view .LVU4429 1057:Src/main.c **** 13861 .loc 1 1057 16 is_stmt 0 view .LVU4430 13862 0c6c 0520 movs r0, #5 13863 0c6e FFF7FEFF bl Get_ADC 13864 .LVL1243: 1057:Src/main.c **** 13865 .loc 1 1057 14 discriminator 1 view .LVU4431 13866 0c72 2880 strh r0, [r5] @ movhi 1060:Src/main.c **** Long_Data[3] = (TO6_stop)&0xffff; 13867 .loc 1 1060 7 is_stmt 1 view .LVU4432 1060:Src/main.c **** Long_Data[3] = (TO6_stop)&0xffff; 13868 .loc 1 1060 16 is_stmt 0 view .LVU4433 ARM GAS /tmp/ccLSPxIe.s page 673 13869 0c74 394B ldr r3, .L769+48 13870 0c76 1B68 ldr r3, [r3] 13871 0c78 394A ldr r2, .L769+52 13872 0c7a 1360 str r3, [r2] 1061:Src/main.c **** Long_Data[4] = (TO6_stop>>16)&0xffff; 13873 .loc 1 1061 7 is_stmt 1 view .LVU4434 1061:Src/main.c **** Long_Data[4] = (TO6_stop>>16)&0xffff; 13874 .loc 1 1061 20 is_stmt 0 view .LVU4435 13875 0c7c E380 strh r3, [r4, #6] @ movhi 1062:Src/main.c **** 13876 .loc 1 1062 7 is_stmt 1 view .LVU4436 1062:Src/main.c **** 13877 .loc 1 1062 31 is_stmt 0 view .LVU4437 13878 0c7e 1B0C lsrs r3, r3, #16 1062:Src/main.c **** 13879 .loc 1 1062 20 view .LVU4438 13880 0c80 2381 strh r3, [r4, #8] @ movhi 1065:Src/main.c **** 13881 .loc 1 1065 7 is_stmt 1 view .LVU4439 1065:Src/main.c **** 13882 .loc 1 1065 31 is_stmt 0 view .LVU4440 13883 0c82 3388 ldrh r3, [r6] 1065:Src/main.c **** 13884 .loc 1 1065 20 view .LVU4441 13885 0c84 6381 strh r3, [r4, #10] @ movhi 1068:Src/main.c **** } 13886 .loc 1 1068 7 is_stmt 1 view .LVU4442 1068:Src/main.c **** } 13887 .loc 1 1068 31 is_stmt 0 view .LVU4443 13888 0c86 3B88 ldrh r3, [r7] 1068:Src/main.c **** } 13889 .loc 1 1068 20 view .LVU4444 13890 0c88 A381 strh r3, [r4, #12] @ movhi 13891 0c8a AEE5 b .L724 13892 .L726: 1096:Src/main.c **** Long_Data[DL_16-1] = CS_result; 13893 .loc 1 1096 5 is_stmt 1 view .LVU4445 1096:Src/main.c **** Long_Data[DL_16-1] = CS_result; 13894 .loc 1 1096 17 is_stmt 0 view .LVU4446 13895 0c8c 354C ldr r4, .L769+56 13896 0c8e 0D21 movs r1, #13 13897 0c90 2046 mov r0, r4 13898 0c92 FFF7FEFF bl CalculateChecksum 13899 .LVL1244: 1096:Src/main.c **** Long_Data[DL_16-1] = CS_result; 13900 .loc 1 1096 15 discriminator 1 view .LVU4447 13901 0c96 344B ldr r3, .L769+60 13902 0c98 1880 strh r0, [r3] @ movhi 1097:Src/main.c **** 13903 .loc 1 1097 5 is_stmt 1 view .LVU4448 1097:Src/main.c **** 13904 .loc 1 1097 24 is_stmt 0 view .LVU4449 13905 0c9a 6083 strh r0, [r4, #26] @ movhi 1099:Src/main.c **** { 13906 .loc 1 1099 5 is_stmt 1 view .LVU4450 13907 .LBB722: 1099:Src/main.c **** { ARM GAS /tmp/ccLSPxIe.s page 674 13908 .loc 1 1099 10 view .LVU4451 13909 .LVL1245: 1099:Src/main.c **** { 13910 .loc 1 1099 19 is_stmt 0 view .LVU4452 13911 0c9c 0023 movs r3, #0 1099:Src/main.c **** { 13912 .loc 1 1099 5 view .LVU4453 13913 0c9e 0BE0 b .L729 13914 .LVL1246: 13915 .L730: 1101:Src/main.c **** UART_DATA[i*2+1] = (Long_Data[i]>>8)&0xff; 13916 .loc 1 1101 6 is_stmt 1 view .LVU4454 1101:Src/main.c **** UART_DATA[i*2+1] = (Long_Data[i]>>8)&0xff; 13917 .loc 1 1101 33 is_stmt 0 view .LVU4455 13918 0ca0 2C4A ldr r2, .L769+40 13919 0ca2 32F81320 ldrh r2, [r2, r3, lsl #1] 1101:Src/main.c **** UART_DATA[i*2+1] = (Long_Data[i]>>8)&0xff; 13920 .loc 1 1101 17 view .LVU4456 13921 0ca6 5900 lsls r1, r3, #1 1101:Src/main.c **** UART_DATA[i*2+1] = (Long_Data[i]>>8)&0xff; 13922 .loc 1 1101 21 view .LVU4457 13923 0ca8 3048 ldr r0, .L769+64 13924 0caa 00F81320 strb r2, [r0, r3, lsl #1] 1102:Src/main.c **** } 13925 .loc 1 1102 6 is_stmt 1 view .LVU4458 1102:Src/main.c **** } 13926 .loc 1 1102 19 is_stmt 0 view .LVU4459 13927 0cae 0131 adds r1, r1, #1 1102:Src/main.c **** } 13928 .loc 1 1102 23 view .LVU4460 13929 0cb0 120A lsrs r2, r2, #8 13930 0cb2 4254 strb r2, [r0, r1] 1099:Src/main.c **** { 13931 .loc 1 1099 38 is_stmt 1 discriminator 3 view .LVU4461 13932 0cb4 0133 adds r3, r3, #1 13933 .LVL1247: 1099:Src/main.c **** { 13934 .loc 1 1099 38 is_stmt 0 discriminator 3 view .LVU4462 13935 0cb6 9BB2 uxth r3, r3 13936 .LVL1248: 13937 .L729: 1099:Src/main.c **** { 13938 .loc 1 1099 28 is_stmt 1 discriminator 1 view .LVU4463 13939 0cb8 0E2B cmp r3, #14 13940 0cba F1D9 bls .L730 13941 .LBE722: 1109:Src/main.c **** UART_transmission_request = NO_MESS; 13942 .loc 1 1109 5 view .LVU4464 13943 0cbc 1E20 movs r0, #30 13944 0cbe FFF7FEFF bl USART_TX_DMA 13945 .LVL1249: 1110:Src/main.c **** break; 13946 .loc 1 1110 5 view .LVU4465 1110:Src/main.c **** break; 13947 .loc 1 1110 31 is_stmt 0 view .LVU4466 13948 0cc2 2B4B ldr r3, .L769+68 13949 0cc4 0022 movs r2, #0 ARM GAS /tmp/ccLSPxIe.s page 675 13950 0cc6 1A70 strb r2, [r3] 1111:Src/main.c **** case MESS_03://Transmith saved packet 13951 .loc 1 1111 4 is_stmt 1 view .LVU4467 13952 0cc8 FFF72FBA b .L728 13953 .LVL1250: 13954 .L731: 13955 .LBB723: 1115:Src/main.c **** UART_DATA[i*2+1] = (Long_Data[i]>>8)&0xff; 13956 .loc 1 1115 6 view .LVU4468 1115:Src/main.c **** UART_DATA[i*2+1] = (Long_Data[i]>>8)&0xff; 13957 .loc 1 1115 33 is_stmt 0 view .LVU4469 13958 0ccc 214A ldr r2, .L769+40 13959 0cce 32F81320 ldrh r2, [r2, r3, lsl #1] 1115:Src/main.c **** UART_DATA[i*2+1] = (Long_Data[i]>>8)&0xff; 13960 .loc 1 1115 17 view .LVU4470 13961 0cd2 5900 lsls r1, r3, #1 1115:Src/main.c **** UART_DATA[i*2+1] = (Long_Data[i]>>8)&0xff; 13962 .loc 1 1115 21 view .LVU4471 13963 0cd4 2548 ldr r0, .L769+64 13964 0cd6 00F81320 strb r2, [r0, r3, lsl #1] 1116:Src/main.c **** } 13965 .loc 1 1116 6 is_stmt 1 view .LVU4472 1116:Src/main.c **** } 13966 .loc 1 1116 19 is_stmt 0 view .LVU4473 13967 0cda 0131 adds r1, r1, #1 1116:Src/main.c **** } 13968 .loc 1 1116 23 view .LVU4474 13969 0cdc 120A lsrs r2, r2, #8 13970 0cde 4254 strb r2, [r0, r1] 1113:Src/main.c **** { 13971 .loc 1 1113 38 is_stmt 1 discriminator 3 view .LVU4475 13972 0ce0 0133 adds r3, r3, #1 13973 .LVL1251: 1113:Src/main.c **** { 13974 .loc 1 1113 38 is_stmt 0 discriminator 3 view .LVU4476 13975 0ce2 9BB2 uxth r3, r3 13976 .LVL1252: 13977 .L727: 1113:Src/main.c **** { 13978 .loc 1 1113 28 is_stmt 1 discriminator 1 view .LVU4477 13979 0ce4 0E2B cmp r3, #14 13980 0ce6 F1D9 bls .L731 13981 .LBE723: 1122:Src/main.c **** UART_transmission_request = NO_MESS; 13982 .loc 1 1122 5 view .LVU4478 13983 0ce8 1E20 movs r0, #30 13984 0cea FFF7FEFF bl USART_TX_DMA 13985 .LVL1253: 1123:Src/main.c **** break; 13986 .loc 1 1123 5 view .LVU4479 1123:Src/main.c **** break; 13987 .loc 1 1123 31 is_stmt 0 view .LVU4480 13988 0cee 204B ldr r3, .L769+68 13989 0cf0 0022 movs r2, #0 13990 0cf2 1A70 strb r2, [r3] 1124:Src/main.c **** } 13991 .loc 1 1124 4 is_stmt 1 view .LVU4481 ARM GAS /tmp/ccLSPxIe.s page 676 13992 0cf4 FFF719BA b .L728 13993 .LVL1254: 13994 .L742: 1084:Src/main.c **** { 13995 .loc 1 1084 3 is_stmt 0 view .LVU4482 13996 0cf8 0023 movs r3, #0 13997 0cfa F3E7 b .L727 13998 .L745: 1126:Src/main.c **** { 13999 .loc 1 1126 28 discriminator 1 view .LVU4483 14000 0cfc 174B ldr r3, .L769+48 14001 0cfe 1B68 ldr r3, [r3] 14002 0d00 1C4A ldr r2, .L769+72 14003 0d02 1268 ldr r2, [r2] 14004 0d04 9B1A subs r3, r3, r2 1126:Src/main.c **** { 14005 .loc 1 1126 21 discriminator 1 view .LVU4484 14006 0d06 642B cmp r3, #100 14007 0d08 7FF614AA bls .L647 1128:Src/main.c **** State_Data[0] |= UART_ERR;//timeout error! 14008 .loc 1 1128 4 is_stmt 1 view .LVU4485 1128:Src/main.c **** State_Data[0] |= UART_ERR;//timeout error! 14009 .loc 1 1128 18 is_stmt 0 view .LVU4486 14010 0d0c 0022 movs r2, #0 14011 0d0e 1A4B ldr r3, .L769+76 14012 0d10 1A80 strh r2, [r3] @ movhi 1129:Src/main.c **** UART_transmission_request = MESS_01;//Send status 14013 .loc 1 1129 4 is_stmt 1 view .LVU4487 1129:Src/main.c **** UART_transmission_request = MESS_01;//Send status 14014 .loc 1 1129 14 is_stmt 0 view .LVU4488 14015 0d12 1A49 ldr r1, .L769+80 14016 0d14 0B78 ldrb r3, [r1] @ zero_extendqisi2 1129:Src/main.c **** UART_transmission_request = MESS_01;//Send status 14017 .loc 1 1129 18 view .LVU4489 14018 0d16 43F00203 orr r3, r3, #2 14019 0d1a 0B70 strb r3, [r1] 1130:Src/main.c **** flg_tmt = 0;//Reset timeout flag 14020 .loc 1 1130 4 is_stmt 1 view .LVU4490 1130:Src/main.c **** flg_tmt = 0;//Reset timeout flag 14021 .loc 1 1130 30 is_stmt 0 view .LVU4491 14022 0d1c 144B ldr r3, .L769+68 14023 0d1e 0121 movs r1, #1 14024 0d20 1970 strb r1, [r3] 1131:Src/main.c **** } 14025 .loc 1 1131 4 is_stmt 1 view .LVU4492 1131:Src/main.c **** } 14026 .loc 1 1131 12 is_stmt 0 view .LVU4493 14027 0d22 174B ldr r3, .L769+84 14028 0d24 1A70 strb r2, [r3] 14029 0d26 FFF705BA b .L647 14030 .L770: 14031 0d2a 00BF .align 2 14032 .L769: 14033 0d2c 00000000 .word htim10 14034 0d30 000C0240 .word 1073875968 14035 0d34 00000000 .word htim8 14036 0d38 00040140 .word 1073808384 ARM GAS /tmp/ccLSPxIe.s page 677 14037 0d3c 00000000 .word task 14038 0d40 00000000 .word TIM10_period 14039 0d44 00000000 .word TO10_counter 14040 0d48 00000000 .word TO7_before 14041 0d4c 00000000 .word LD1_param 14042 0d50 00000000 .word LD2_param 14043 0d54 00000000 .word Long_Data 14044 0d58 00000000 .word temp16 14045 0d5c 00000000 .word TO6 14046 0d60 00000000 .word TO6_stop 14047 0d64 02000000 .word Long_Data+2 14048 0d68 00000000 .word CS_result 14049 0d6c 00000000 .word UART_DATA 14050 0d70 00000000 .word UART_transmission_request 14051 0d74 00000000 .word TO6_uart 14052 0d78 00000000 .word UART_rec_incr 14053 0d7c 00000000 .word State_Data 14054 0d80 00000000 .word flg_tmt 14055 .cfi_endproc 14056 .LFE1186: 14058 .section .bss.ad9102_wave_written_samples,"aw",%nobits 14059 .align 1 14062 ad9102_wave_written_samples: 14063 0000 0000 .space 2 14064 .section .bss.ad9102_wave_expected_samples,"aw",%nobits 14065 .align 1 14068 ad9102_wave_expected_samples: 14069 0000 0000 .space 2 14070 .section .bss.ad9102_wave_upload_active,"aw",%nobits 14073 ad9102_wave_upload_active: 14074 0000 00 .space 1 14075 .section .rodata.ad9102_example2_regval,"a" 14076 .align 2 14079 ad9102_example2_regval: 14080 0000 0000 .short 0 14081 0002 000E .short 3584 14082 0004 0000 .short 0 14083 0006 0000 .short 0 14084 0008 0000 .short 0 14085 000a 0000 .short 0 14086 000c 0000 .short 0 14087 000e 0040 .short 16384 14088 0010 0000 .short 0 14089 0012 0000 .short 0 14090 0014 0000 .short 0 14091 0016 0000 .short 0 14092 0018 001F .short 7936 14093 001a 0000 .short 0 14094 001c 0000 .short 0 14095 001e 0000 .short 0 14096 0020 0E00 .short 14 14097 0022 0000 .short 0 14098 0024 0000 .short 0 14099 0026 0000 .short 0 14100 0028 0000 .short 0 14101 002a 0000 .short 0 14102 002c 3030 .short 12336 ARM GAS /tmp/ccLSPxIe.s page 678 14103 002e 1101 .short 273 14104 0030 FFFF .short -1 14105 0032 0000 .short 0 14106 0034 0101 .short 257 14107 0036 0300 .short 3 14108 0038 0000 .short 0 14109 003a 0000 .short 0 14110 003c 0000 .short 0 14111 003e 0000 .short 0 14112 0040 0000 .short 0 14113 0042 0000 .short 0 14114 0044 0000 .short 0 14115 0046 0000 .short 0 14116 0048 0040 .short 16384 14117 004a 0000 .short 0 14118 004c 0002 .short 512 14119 004e 0000 .short 0 14120 0050 0000 .short 0 14121 0052 0000 .short 0 14122 0054 0000 .short 0 14123 0056 0000 .short 0 14124 0058 0000 .short 0 14125 005a 0000 .short 0 14126 005c 0000 .short 0 14127 005e 0000 .short 0 14128 0060 0000 .short 0 14129 0062 0000 .short 0 14130 0064 0000 .short 0 14131 0066 0000 .short 0 14132 0068 0000 .short 0 14133 006a 0000 .short 0 14134 006c 0000 .short 0 14135 006e 0000 .short 0 14136 0070 0000 .short 0 14137 0072 0000 .short 0 14138 0074 0000 .short 0 14139 0076 0000 .short 0 14140 0078 A00F .short 4000 14141 007a 0000 .short 0 14142 007c F03F .short 16368 14143 007e 0001 .short 256 14144 0080 0100 .short 1 14145 0082 0100 .short 1 14146 .section .rodata.ad9102_example4_regval,"a" 14147 .align 2 14150 ad9102_example4_regval: 14151 0000 0000 .short 0 14152 0002 0000 .short 0 14153 0004 0000 .short 0 14154 0006 0000 .short 0 14155 0008 0000 .short 0 14156 000a 0000 .short 0 14157 000c 0000 .short 0 14158 000e 0040 .short 16384 14159 0010 0000 .short 0 14160 0012 0000 .short 0 14161 0014 0000 .short 0 ARM GAS /tmp/ccLSPxIe.s page 679 14162 0016 0000 .short 0 14163 0018 001F .short 7936 14164 001a 0000 .short 0 14165 001c 0000 .short 0 14166 001e 0000 .short 0 14167 0020 0E00 .short 14 14168 0022 0000 .short 0 14169 0024 0000 .short 0 14170 0026 0000 .short 0 14171 0028 0000 .short 0 14172 002a 0000 .short 0 14173 002c 1232 .short 12818 14174 002e 2101 .short 289 14175 0030 FFFF .short -1 14176 0032 0000 .short 0 14177 0034 0101 .short 257 14178 0036 0300 .short 3 14179 0038 0000 .short 0 14180 003a 0000 .short 0 14181 003c 0000 .short 0 14182 003e 0000 .short 0 14183 0040 0000 .short 0 14184 0042 0000 .short 0 14185 0044 0000 .short 0 14186 0046 0000 .short 0 14187 0048 0040 .short 16384 14188 004a 0000 .short 0 14189 004c 0606 .short 1542 14190 004e 9919 .short 6553 14191 0050 009A .short -26112 14192 0052 0000 .short 0 14193 0054 0000 .short 0 14194 0056 0000 .short 0 14195 0058 0000 .short 0 14196 005a 0000 .short 0 14197 005c 0000 .short 0 14198 005e 0000 .short 0 14199 0060 A00F .short 4000 14200 0062 0000 .short 0 14201 0064 0000 .short 0 14202 0066 0000 .short 0 14203 0068 0000 .short 0 14204 006a 0000 .short 0 14205 006c 0000 .short 0 14206 006e 0000 .short 0 14207 0070 0000 .short 0 14208 0072 0000 .short 0 14209 0074 0000 .short 0 14210 0076 0000 .short 0 14211 0078 0000 .short 0 14212 007a 0000 .short 0 14213 007c 0000 .short 0 14214 007e FF16 .short 5887 14215 0080 0100 .short 1 14216 0082 0100 .short 1 14217 .section .rodata.ad9102_reg_addr,"a" 14218 .align 2 ARM GAS /tmp/ccLSPxIe.s page 680 14221 ad9102_reg_addr: 14222 0000 0000 .short 0 14223 0002 0100 .short 1 14224 0004 0200 .short 2 14225 0006 0300 .short 3 14226 0008 0400 .short 4 14227 000a 0500 .short 5 14228 000c 0600 .short 6 14229 000e 0700 .short 7 14230 0010 0800 .short 8 14231 0012 0900 .short 9 14232 0014 0A00 .short 10 14233 0016 0B00 .short 11 14234 0018 0C00 .short 12 14235 001a 0D00 .short 13 14236 001c 0E00 .short 14 14237 001e 1F00 .short 31 14238 0020 2000 .short 32 14239 0022 2200 .short 34 14240 0024 2300 .short 35 14241 0026 2400 .short 36 14242 0028 2500 .short 37 14243 002a 2600 .short 38 14244 002c 2700 .short 39 14245 002e 2800 .short 40 14246 0030 2900 .short 41 14247 0032 2A00 .short 42 14248 0034 2B00 .short 43 14249 0036 2C00 .short 44 14250 0038 2D00 .short 45 14251 003a 2E00 .short 46 14252 003c 2F00 .short 47 14253 003e 3000 .short 48 14254 0040 3100 .short 49 14255 0042 3200 .short 50 14256 0044 3300 .short 51 14257 0046 3400 .short 52 14258 0048 3500 .short 53 14259 004a 3600 .short 54 14260 004c 3700 .short 55 14261 004e 3E00 .short 62 14262 0050 3F00 .short 63 14263 0052 4000 .short 64 14264 0054 4100 .short 65 14265 0056 4200 .short 66 14266 0058 4300 .short 67 14267 005a 4400 .short 68 14268 005c 4500 .short 69 14269 005e 4700 .short 71 14270 0060 5000 .short 80 14271 0062 5100 .short 81 14272 0064 5200 .short 82 14273 0066 5300 .short 83 14274 0068 5400 .short 84 14275 006a 5500 .short 85 14276 006c 5600 .short 86 14277 006e 5700 .short 87 ARM GAS /tmp/ccLSPxIe.s page 681 14278 0070 5800 .short 88 14279 0072 5900 .short 89 14280 0074 5A00 .short 90 14281 0076 5B00 .short 91 14282 0078 5C00 .short 92 14283 007a 5D00 .short 93 14284 007c 5E00 .short 94 14285 007e 5F00 .short 95 14286 0080 1E00 .short 30 14287 0082 1D00 .short 29 14288 .global task 14289 .section .bss.task,"aw",%nobits 14290 .align 2 14293 task: 14294 0000 00000000 .space 52 14294 00000000 14294 00000000 14294 00000000 14294 00000000 14295 .global LD_blinker 14296 .section .bss.LD_blinker,"aw",%nobits 14297 .align 2 14300 LD_blinker: 14301 0000 00000000 .space 12 14301 00000000 14301 00000000 14302 .global LD2_param 14303 .section .bss.LD2_param,"aw",%nobits 14304 .align 2 14307 LD2_param: 14308 0000 00000000 .space 12 14308 00000000 14308 00000000 14309 .global LD1_param 14310 .section .bss.LD1_param,"aw",%nobits 14311 .align 2 14314 LD1_param: 14315 0000 00000000 .space 12 14315 00000000 14315 00000000 14316 .global Def_setup 14317 .section .bss.Def_setup,"aw",%nobits 14318 .align 2 14321 Def_setup: 14322 0000 00000000 .space 18 14322 00000000 14322 00000000 14322 00000000 14322 0000 14323 .global Curr_setup 14324 .section .bss.Curr_setup,"aw",%nobits 14325 .align 2 14328 Curr_setup: 14329 0000 00000000 .space 18 14329 00000000 14329 00000000 14329 00000000 ARM GAS /tmp/ccLSPxIe.s page 682 14329 0000 14330 .global LD2_def_setup 14331 .section .bss.LD2_def_setup,"aw",%nobits 14332 .align 2 14335 LD2_def_setup: 14336 0000 00000000 .space 16 14336 00000000 14336 00000000 14336 00000000 14337 .global LD1_def_setup 14338 .section .bss.LD1_def_setup,"aw",%nobits 14339 .align 2 14342 LD1_def_setup: 14343 0000 00000000 .space 16 14343 00000000 14343 00000000 14343 00000000 14344 .global LD2_curr_setup 14345 .section .bss.LD2_curr_setup,"aw",%nobits 14346 .align 2 14349 LD2_curr_setup: 14350 0000 00000000 .space 16 14350 00000000 14350 00000000 14350 00000000 14351 .global LD1_curr_setup 14352 .section .bss.LD1_curr_setup,"aw",%nobits 14353 .align 2 14356 LD1_curr_setup: 14357 0000 00000000 .space 16 14357 00000000 14357 00000000 14357 00000000 14358 .global sizeoffile 14359 .section .bss.sizeoffile,"aw",%nobits 14360 .align 2 14363 sizeoffile: 14364 0000 00000000 .space 4 14365 .global fgoto 14366 .section .bss.fgoto,"aw",%nobits 14367 .align 2 14370 fgoto: 14371 0000 00000000 .space 4 14372 .global test 14373 .section .bss.test,"aw",%nobits 14374 .align 2 14377 test: 14378 0000 00000000 .space 4 14379 .global fresult 14380 .section .bss.fresult,"aw",%nobits 14383 fresult: 14384 0000 00 .space 1 14385 .global COMMAND 14386 .section .bss.COMMAND,"aw",%nobits 14387 .align 2 14390 COMMAND: 14391 0000 00000000 .space 30 ARM GAS /tmp/ccLSPxIe.s page 683 14391 00000000 14391 00000000 14391 00000000 14391 00000000 14392 .global Long_Data 14393 .section .bss.Long_Data,"aw",%nobits 14394 .align 2 14397 Long_Data: 14398 0000 00000000 .space 30 14398 00000000 14398 00000000 14398 00000000 14398 00000000 14399 .global temp16 14400 .section .bss.temp16,"aw",%nobits 14401 .align 1 14404 temp16: 14405 0000 0000 .space 2 14406 .global CS_result 14407 .section .bss.CS_result,"aw",%nobits 14408 .align 1 14411 CS_result: 14412 0000 0000 .space 2 14413 .global UART_header 14414 .section .bss.UART_header,"aw",%nobits 14415 .align 1 14418 UART_header: 14419 0000 0000 .space 2 14420 .global UART_rec_incr 14421 .section .bss.UART_rec_incr,"aw",%nobits 14422 .align 1 14425 UART_rec_incr: 14426 0000 0000 .space 2 14427 .global TIM10_coflag 14428 .section .bss.TIM10_coflag,"aw",%nobits 14431 TIM10_coflag: 14432 0000 00 .space 1 14433 .global u_rx_flg 14434 .section .bss.u_rx_flg,"aw",%nobits 14437 u_rx_flg: 14438 0000 00 .space 1 14439 .global u_tx_flg 14440 .section .bss.u_tx_flg,"aw",%nobits 14443 u_tx_flg: 14444 0000 00 .space 1 14445 .global flg_tmt 14446 .section .bss.flg_tmt,"aw",%nobits 14449 flg_tmt: 14450 0000 00 .space 1 14451 .global UART_DATA 14452 .section .bss.UART_DATA,"aw",%nobits 14453 .align 2 14456 UART_DATA: 14457 0000 00000000 .space 30 14457 00000000 14457 00000000 14457 00000000 ARM GAS /tmp/ccLSPxIe.s page 684 14457 00000000 14458 .global State_Data 14459 .section .bss.State_Data,"aw",%nobits 14460 .align 2 14463 State_Data: 14464 0000 0000 .space 2 14465 .global UART_transmission_request 14466 .section .bss.UART_transmission_request,"aw",%nobits 14469 UART_transmission_request: 14470 0000 00 .space 1 14471 .global CPU_state_old 14472 .section .bss.CPU_state_old,"aw",%nobits 14475 CPU_state_old: 14476 0000 00 .space 1 14477 .global CPU_state 14478 .section .bss.CPU_state,"aw",%nobits 14481 CPU_state: 14482 0000 00 .space 1 14483 .global uart_buf 14484 .section .bss.uart_buf,"aw",%nobits 14487 uart_buf: 14488 0000 00 .space 1 14489 .global TIM10_period 14490 .section .bss.TIM10_period,"aw",%nobits 14491 .align 2 14494 TIM10_period: 14495 0000 00000000 .space 4 14496 .global TO10_counter 14497 .section .bss.TO10_counter,"aw",%nobits 14498 .align 2 14501 TO10_counter: 14502 0000 00000000 .space 4 14503 .global TO10 14504 .section .bss.TO10,"aw",%nobits 14505 .align 2 14508 TO10: 14509 0000 00000000 .space 4 14510 .global TO7_PID 14511 .section .bss.TO7_PID,"aw",%nobits 14512 .align 2 14515 TO7_PID: 14516 0000 00000000 .space 4 14517 .global TO7_before 14518 .section .bss.TO7_before,"aw",%nobits 14519 .align 2 14522 TO7_before: 14523 0000 00000000 .space 4 14524 .global TO7 14525 .section .bss.TO7,"aw",%nobits 14526 .align 2 14529 TO7: 14530 0000 00000000 .space 4 14531 .global temp32 14532 .section .bss.temp32,"aw",%nobits 14533 .align 2 14536 temp32: 14537 0000 00000000 .space 4 ARM GAS /tmp/ccLSPxIe.s page 685 14538 .global SD_SLIDE 14539 .section .bss.SD_SLIDE,"aw",%nobits 14540 .align 2 14543 SD_SLIDE: 14544 0000 00000000 .space 4 14545 .global SD_SEEK 14546 .section .bss.SD_SEEK,"aw",%nobits 14547 .align 2 14550 SD_SEEK: 14551 0000 00000000 .space 4 14552 .global TO6_uart 14553 .section .bss.TO6_uart,"aw",%nobits 14554 .align 2 14557 TO6_uart: 14558 0000 00000000 .space 4 14559 .global TO6_stop 14560 .section .bss.TO6_stop,"aw",%nobits 14561 .align 2 14564 TO6_stop: 14565 0000 00000000 .space 4 14566 .global TO6_before 14567 .section .bss.TO6_before,"aw",%nobits 14568 .align 2 14571 TO6_before: 14572 0000 00000000 .space 4 14573 .global TO6 14574 .section .bss.TO6,"aw",%nobits 14575 .align 2 14578 TO6: 14579 0000 00000000 .space 4 14580 .global huart8 14581 .section .bss.huart8,"aw",%nobits 14582 .align 2 14585 huart8: 14586 0000 00000000 .space 136 14586 00000000 14586 00000000 14586 00000000 14586 00000000 14587 .global htim11 14588 .section .bss.htim11,"aw",%nobits 14589 .align 2 14592 htim11: 14593 0000 00000000 .space 76 14593 00000000 14593 00000000 14593 00000000 14593 00000000 14594 .global htim10 14595 .section .bss.htim10,"aw",%nobits 14596 .align 2 14599 htim10: 14600 0000 00000000 .space 76 14600 00000000 14600 00000000 14600 00000000 14600 00000000 ARM GAS /tmp/ccLSPxIe.s page 686 14601 .global htim1 14602 .section .bss.htim1,"aw",%nobits 14603 .align 2 14606 htim1: 14607 0000 00000000 .space 76 14607 00000000 14607 00000000 14607 00000000 14607 00000000 14608 .global htim8 14609 .section .bss.htim8,"aw",%nobits 14610 .align 2 14613 htim8: 14614 0000 00000000 .space 76 14614 00000000 14614 00000000 14614 00000000 14614 00000000 14615 .global htim4 14616 .section .bss.htim4,"aw",%nobits 14617 .align 2 14620 htim4: 14621 0000 00000000 .space 76 14621 00000000 14621 00000000 14621 00000000 14621 00000000 14622 .global hsd1 14623 .section .bss.hsd1,"aw",%nobits 14624 .align 2 14627 hsd1: 14628 0000 00000000 .space 132 14628 00000000 14628 00000000 14628 00000000 14628 00000000 14629 .global hadc3 14630 .section .bss.hadc3,"aw",%nobits 14631 .align 2 14634 hadc3: 14635 0000 00000000 .space 72 14635 00000000 14635 00000000 14635 00000000 14635 00000000 14636 .global hadc1 14637 .section .bss.hadc1,"aw",%nobits 14638 .align 2 14641 hadc1: 14642 0000 00000000 .space 72 14642 00000000 14642 00000000 14642 00000000 14642 00000000 14643 .text 14644 .Letext0: 14645 .file 9 "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h" ARM GAS /tmp/ccLSPxIe.s page 687 14646 .file 10 "/usr/lib/gcc/arm-none-eabi/13.2.1/include/stdint.h" 14647 .file 11 "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h" 14648 .file 12 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h" 14649 .file 13 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h" 14650 .file 14 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h" 14651 .file 15 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h" 14652 .file 16 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h" 14653 .file 17 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h" 14654 .file 18 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_sdmmc.h" 14655 .file 19 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sd.h" 14656 .file 20 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h" 14657 .file 21 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h" 14658 .file 22 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h" 14659 .file 23 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h" 14660 .file 24 "Inc/main.h" 14661 .file 25 "Middlewares/Third_Party/FatFs/src/ff.h" 14662 .file 26 "Inc/File_Handling.h" 14663 .file 27 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h" 14664 .file 28 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h" 14665 .file 29 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h" 14666 .file 30 "Inc/fatfs.h" 14667 .file 31 "" ARM GAS /tmp/ccLSPxIe.s page 688 DEFINED SYMBOLS *ABS*:00000000 main.c /tmp/ccLSPxIe.s:20 .text.NVIC_EncodePriority:00000000 $t /tmp/ccLSPxIe.s:25 .text.NVIC_EncodePriority:00000000 NVIC_EncodePriority /tmp/ccLSPxIe.s:88 .text.MX_SDMMC1_SD_Init:00000000 $t /tmp/ccLSPxIe.s:93 .text.MX_SDMMC1_SD_Init:00000000 MX_SDMMC1_SD_Init /tmp/ccLSPxIe.s:131 .text.MX_SDMMC1_SD_Init:0000001c $d /tmp/ccLSPxIe.s:14627 .bss.hsd1:00000000 hsd1 /tmp/ccLSPxIe.s:137 .text.MX_DMA_Init:00000000 $t /tmp/ccLSPxIe.s:142 .text.MX_DMA_Init:00000000 MX_DMA_Init /tmp/ccLSPxIe.s:238 .text.MX_DMA_Init:0000003c $d /tmp/ccLSPxIe.s:245 .text.Decode_task:00000000 $t /tmp/ccLSPxIe.s:250 .text.Decode_task:00000000 Decode_task /tmp/ccLSPxIe.s:527 .text.Decode_task:00000150 $d /tmp/ccLSPxIe.s:14293 .bss.task:00000000 task /tmp/ccLSPxIe.s:14501 .bss.TO10_counter:00000000 TO10_counter /tmp/ccLSPxIe.s:537 .text.SPI2_SetMode:00000000 $t /tmp/ccLSPxIe.s:542 .text.SPI2_SetMode:00000000 SPI2_SetMode /tmp/ccLSPxIe.s:650 .text.SPI2_SetMode:00000040 $d /tmp/ccLSPxIe.s:655 .text.PA4_DAC_Set:00000000 $t /tmp/ccLSPxIe.s:660 .text.PA4_DAC_Set:00000000 PA4_DAC_Set /tmp/ccLSPxIe.s:704 .text.PA4_DAC_Set:00000028 $d /tmp/ccLSPxIe.s:709 .text.AD9102_ResetWaveUploadState:00000000 $t /tmp/ccLSPxIe.s:714 .text.AD9102_ResetWaveUploadState:00000000 AD9102_ResetWaveUploadState /tmp/ccLSPxIe.s:739 .text.AD9102_ResetWaveUploadState:00000010 $d /tmp/ccLSPxIe.s:14073 .bss.ad9102_wave_upload_active:00000000 ad9102_wave_upload_active /tmp/ccLSPxIe.s:14068 .bss.ad9102_wave_expected_samples:00000000 ad9102_wave_expected_samples /tmp/ccLSPxIe.s:14062 .bss.ad9102_wave_written_samples:00000000 ad9102_wave_written_samples /tmp/ccLSPxIe.s:746 .text.PID_Controller_Temp:00000000 $t /tmp/ccLSPxIe.s:751 .text.PID_Controller_Temp:00000000 PID_Controller_Temp /tmp/ccLSPxIe.s:920 .text.PID_Controller_Temp:000000cc $d /tmp/ccLSPxIe.s:14529 .bss.TO7:00000000 TO7 /tmp/ccLSPxIe.s:14515 .bss.TO7_PID:00000000 TO7_PID /tmp/ccLSPxIe.s:930 .text.AD9102_WriteReg:00000000 $t /tmp/ccLSPxIe.s:935 .text.AD9102_WriteReg:00000000 AD9102_WriteReg /tmp/ccLSPxIe.s:1198 .text.AD9102_WriteReg:000000c8 $d /tmp/ccLSPxIe.s:1205 .text.AD9102_WriteRegTable:00000000 $t /tmp/ccLSPxIe.s:1210 .text.AD9102_WriteRegTable:00000000 AD9102_WriteRegTable /tmp/ccLSPxIe.s:1261 .text.AD9102_WriteRegTable:00000024 $d /tmp/ccLSPxIe.s:14221 .rodata.ad9102_reg_addr:00000000 ad9102_reg_addr /tmp/ccLSPxIe.s:1266 .text.AD9102_LoadSramRamp:00000000 $t /tmp/ccLSPxIe.s:1271 .text.AD9102_LoadSramRamp:00000000 AD9102_LoadSramRamp /tmp/ccLSPxIe.s:1555 .text.AD9102_LoadSramRamp:000000d4 $d /tmp/ccLSPxIe.s:1560 .text.AD9102_WriteWaveUploadChunk:00000000 $t /tmp/ccLSPxIe.s:1565 .text.AD9102_WriteWaveUploadChunk:00000000 AD9102_WriteWaveUploadChunk /tmp/ccLSPxIe.s:1695 .text.AD9102_WriteWaveUploadChunk:0000006c $d /tmp/ccLSPxIe.s:1704 .text.AD9102_Init:00000000 $t /tmp/ccLSPxIe.s:1709 .text.AD9102_Init:00000000 AD9102_Init /tmp/ccLSPxIe.s:1790 .text.AD9102_Init:00000064 $d /tmp/ccLSPxIe.s:14150 .rodata.ad9102_example4_regval:00000000 ad9102_example4_regval /tmp/ccLSPxIe.s:1798 .text.AD9102_StartOutput:00000000 $t /tmp/ccLSPxIe.s:1803 .text.AD9102_StartOutput:00000000 AD9102_StartOutput /tmp/ccLSPxIe.s:1867 .text.AD9102_StartOutput:00000048 $d /tmp/ccLSPxIe.s:1872 .text.AD9102_StopOutput:00000000 $t /tmp/ccLSPxIe.s:1877 .text.AD9102_StopOutput:00000000 AD9102_StopOutput /tmp/ccLSPxIe.s:1904 .text.AD9102_StopOutput:00000018 $d /tmp/ccLSPxIe.s:1909 .text.AD9102_ConfigureSramPlayback:00000000 $t ARM GAS /tmp/ccLSPxIe.s page 689 /tmp/ccLSPxIe.s:1914 .text.AD9102_ConfigureSramPlayback:00000000 AD9102_ConfigureSramPlayback /tmp/ccLSPxIe.s:2065 .text.AD9102_ConfigureSramPlayback:000000b0 $d /tmp/ccLSPxIe.s:14079 .rodata.ad9102_example2_regval:00000000 ad9102_example2_regval /tmp/ccLSPxIe.s:2070 .text.AD9102_BeginWaveUpload:00000000 $t /tmp/ccLSPxIe.s:2075 .text.AD9102_BeginWaveUpload:00000000 AD9102_BeginWaveUpload /tmp/ccLSPxIe.s:2140 .text.AD9102_BeginWaveUpload:00000040 $d /tmp/ccLSPxIe.s:2147 .text.AD9102_CancelWaveUpload:00000000 $t /tmp/ccLSPxIe.s:2152 .text.AD9102_CancelWaveUpload:00000000 AD9102_CancelWaveUpload /tmp/ccLSPxIe.s:2183 .text.AD9102_CancelWaveUpload:00000014 $d /tmp/ccLSPxIe.s:2188 .text.AD9102_ReadReg:00000000 $t /tmp/ccLSPxIe.s:2193 .text.AD9102_ReadReg:00000000 AD9102_ReadReg /tmp/ccLSPxIe.s:2465 .text.AD9102_ReadReg:000000c8 $d /tmp/ccLSPxIe.s:2472 .text.AD9102_ApplySram:00000000 $t /tmp/ccLSPxIe.s:2477 .text.AD9102_ApplySram:00000000 AD9102_ApplySram /tmp/ccLSPxIe.s:2594 .text.AD9102_Apply:00000000 $t /tmp/ccLSPxIe.s:2599 .text.AD9102_Apply:00000000 AD9102_Apply /tmp/ccLSPxIe.s:2715 .text.AD9102_CheckFlags:00000000 $t /tmp/ccLSPxIe.s:2720 .text.AD9102_CheckFlags:00000000 AD9102_CheckFlags /tmp/ccLSPxIe.s:2950 .text.AD9102_CommitWaveUpload:00000000 $t /tmp/ccLSPxIe.s:2955 .text.AD9102_CommitWaveUpload:00000000 AD9102_CommitWaveUpload /tmp/ccLSPxIe.s:3068 .text.AD9102_CommitWaveUpload:00000074 $d /tmp/ccLSPxIe.s:3075 .text.AD9102_CheckFlagsSram:00000000 $t /tmp/ccLSPxIe.s:3080 .text.AD9102_CheckFlagsSram:00000000 AD9102_CheckFlagsSram /tmp/ccLSPxIe.s:3378 .text.AD9833_WriteWord:00000000 $t /tmp/ccLSPxIe.s:3383 .text.AD9833_WriteWord:00000000 AD9833_WriteWord /tmp/ccLSPxIe.s:3531 .text.AD9833_WriteWord:00000088 $d /tmp/ccLSPxIe.s:3538 .text.AD9833_Apply:00000000 $t /tmp/ccLSPxIe.s:3543 .text.AD9833_Apply:00000000 AD9833_Apply /tmp/ccLSPxIe.s:3628 .text.OUT_trigger:00000000 $t /tmp/ccLSPxIe.s:3633 .text.OUT_trigger:00000000 OUT_trigger /tmp/ccLSPxIe.s:3651 .text.OUT_trigger:0000000a $d /tmp/ccLSPxIe.s:3661 .text.OUT_trigger:00000014 $t /tmp/ccLSPxIe.s:3857 .text.OUT_trigger:0000011c $d /tmp/ccLSPxIe.s:3863 .text.MPhD_T:00000000 $t /tmp/ccLSPxIe.s:3868 .text.MPhD_T:00000000 MPhD_T /tmp/ccLSPxIe.s:3952 .text.MPhD_T:00000056 $d /tmp/ccLSPxIe.s:3956 .text.MPhD_T:0000005a $t /tmp/ccLSPxIe.s:4499 .text.MPhD_T:00000210 $d /tmp/ccLSPxIe.s:4509 .text.Stop_TIM10:00000000 $t /tmp/ccLSPxIe.s:4514 .text.Stop_TIM10:00000000 Stop_TIM10 /tmp/ccLSPxIe.s:4543 .text.Stop_TIM10:00000014 $d /tmp/ccLSPxIe.s:14599 .bss.htim10:00000000 htim10 /tmp/ccLSPxIe.s:14431 .bss.TIM10_coflag:00000000 TIM10_coflag /tmp/ccLSPxIe.s:14508 .bss.TO10:00000000 TO10 /tmp/ccLSPxIe.s:4550 .text.MX_GPIO_Init:00000000 $t /tmp/ccLSPxIe.s:4555 .text.MX_GPIO_Init:00000000 MX_GPIO_Init /tmp/ccLSPxIe.s:5053 .text.MX_GPIO_Init:00000274 $d /tmp/ccLSPxIe.s:5065 .text.PA4_DAC_Init:00000000 $t /tmp/ccLSPxIe.s:5070 .text.PA4_DAC_Init:00000000 PA4_DAC_Init /tmp/ccLSPxIe.s:5157 .text.PA4_DAC_Init:00000058 $d /tmp/ccLSPxIe.s:5165 .text.MX_SPI4_Init:00000000 $t /tmp/ccLSPxIe.s:5170 .text.MX_SPI4_Init:00000000 MX_SPI4_Init /tmp/ccLSPxIe.s:5375 .text.MX_SPI4_Init:000000c8 $d /tmp/ccLSPxIe.s:5382 .text.MX_SPI2_Init:00000000 $t /tmp/ccLSPxIe.s:5387 .text.MX_SPI2_Init:00000000 MX_SPI2_Init /tmp/ccLSPxIe.s:5615 .text.MX_SPI2_Init:000000dc $d /tmp/ccLSPxIe.s:5622 .text.MX_SPI5_Init:00000000 $t ARM GAS /tmp/ccLSPxIe.s page 690 /tmp/ccLSPxIe.s:5627 .text.MX_SPI5_Init:00000000 MX_SPI5_Init /tmp/ccLSPxIe.s:5832 .text.MX_SPI5_Init:000000c4 $d /tmp/ccLSPxIe.s:5839 .text.MX_SPI6_Init:00000000 $t /tmp/ccLSPxIe.s:5844 .text.MX_SPI6_Init:00000000 MX_SPI6_Init /tmp/ccLSPxIe.s:6049 .text.MX_SPI6_Init:000000c4 $d /tmp/ccLSPxIe.s:6056 .text.MX_TIM2_Init:00000000 $t /tmp/ccLSPxIe.s:6061 .text.MX_TIM2_Init:00000000 MX_TIM2_Init /tmp/ccLSPxIe.s:6239 .text.MX_TIM2_Init:00000088 $d /tmp/ccLSPxIe.s:6248 .text.MX_TIM5_Init:00000000 $t /tmp/ccLSPxIe.s:6253 .text.MX_TIM5_Init:00000000 MX_TIM5_Init /tmp/ccLSPxIe.s:6430 .text.MX_TIM5_Init:00000084 $d /tmp/ccLSPxIe.s:6439 .text.MX_TIM7_Init:00000000 $t /tmp/ccLSPxIe.s:6444 .text.MX_TIM7_Init:00000000 MX_TIM7_Init /tmp/ccLSPxIe.s:6605 .text.MX_TIM7_Init:0000007c $d /tmp/ccLSPxIe.s:6613 .text.MX_TIM6_Init:00000000 $t /tmp/ccLSPxIe.s:6618 .text.MX_TIM6_Init:00000000 MX_TIM6_Init /tmp/ccLSPxIe.s:6779 .text.MX_TIM6_Init:0000007c $d /tmp/ccLSPxIe.s:6787 .rodata.Init_params.str1.4:00000000 $d /tmp/ccLSPxIe.s:6794 .text.Init_params:00000000 $t /tmp/ccLSPxIe.s:6799 .text.Init_params:00000000 Init_params /tmp/ccLSPxIe.s:7442 .text.Init_params:00000294 $d /tmp/ccLSPxIe.s:14578 .bss.TO6:00000000 TO6 /tmp/ccLSPxIe.s:14522 .bss.TO7_before:00000000 TO7_before /tmp/ccLSPxIe.s:14571 .bss.TO6_before:00000000 TO6_before /tmp/ccLSPxIe.s:14557 .bss.TO6_uart:00000000 TO6_uart /tmp/ccLSPxIe.s:14449 .bss.flg_tmt:00000000 flg_tmt /tmp/ccLSPxIe.s:14425 .bss.UART_rec_incr:00000000 UART_rec_incr /tmp/ccLSPxIe.s:14370 .bss.fgoto:00000000 fgoto /tmp/ccLSPxIe.s:14363 .bss.sizeoffile:00000000 sizeoffile /tmp/ccLSPxIe.s:14443 .bss.u_tx_flg:00000000 u_tx_flg /tmp/ccLSPxIe.s:14437 .bss.u_rx_flg:00000000 u_rx_flg /tmp/ccLSPxIe.s:14397 .bss.Long_Data:00000000 Long_Data /tmp/ccLSPxIe.s:14321 .bss.Def_setup:00000000 Def_setup /tmp/ccLSPxIe.s:14342 .bss.LD1_def_setup:00000000 LD1_def_setup /tmp/ccLSPxIe.s:14335 .bss.LD2_def_setup:00000000 LD2_def_setup /tmp/ccLSPxIe.s:14328 .bss.Curr_setup:00000000 Curr_setup /tmp/ccLSPxIe.s:14356 .bss.LD1_curr_setup:00000000 LD1_curr_setup /tmp/ccLSPxIe.s:14349 .bss.LD2_curr_setup:00000000 LD2_curr_setup /tmp/ccLSPxIe.s:14456 .bss.UART_DATA:00000000 UART_DATA /tmp/ccLSPxIe.s:14550 .bss.SD_SEEK:00000000 SD_SEEK /tmp/ccLSPxIe.s:14543 .bss.SD_SLIDE:00000000 SD_SLIDE /tmp/ccLSPxIe.s:14377 .bss.test:00000000 test /tmp/ccLSPxIe.s:14481 .bss.CPU_state:00000000 CPU_state /tmp/ccLSPxIe.s:14390 .bss.COMMAND:00000000 COMMAND /tmp/ccLSPxIe.s:7481 .text.DS1809_Pulse:00000000 $t /tmp/ccLSPxIe.s:7486 .text.DS1809_Pulse:00000000 DS1809_Pulse /tmp/ccLSPxIe.s:7595 .text.DS1809_Pulse:00000068 $d /tmp/ccLSPxIe.s:7600 .text.Get_ADC:00000000 $t /tmp/ccLSPxIe.s:7605 .text.Get_ADC:00000000 Get_ADC /tmp/ccLSPxIe.s:7625 .text.Get_ADC:0000000c $d /tmp/ccLSPxIe.s:7631 .text.Get_ADC:00000012 $t /tmp/ccLSPxIe.s:7729 .text.Get_ADC:00000068 $d /tmp/ccLSPxIe.s:14641 .bss.hadc1:00000000 hadc1 /tmp/ccLSPxIe.s:14634 .bss.hadc3:00000000 hadc3 /tmp/ccLSPxIe.s:7735 .text.Set_LTEC:00000000 $t /tmp/ccLSPxIe.s:7741 .text.Set_LTEC:00000000 Set_LTEC /tmp/ccLSPxIe.s:7775 .text.Set_LTEC:00000018 $d ARM GAS /tmp/ccLSPxIe.s page 691 /tmp/ccLSPxIe.s:7780 .text.Set_LTEC:0000001c $t /tmp/ccLSPxIe.s:8196 .text.Set_LTEC:00000168 $d /tmp/ccLSPxIe.s:8206 .text.Decode_uart:00000000 $t /tmp/ccLSPxIe.s:8211 .text.Decode_uart:00000000 Decode_uart /tmp/ccLSPxIe.s:8774 .text.Decode_uart:000002cc $d /tmp/ccLSPxIe.s:8789 .text.Advanced_Controller_Temp:00000000 $t /tmp/ccLSPxIe.s:8795 .text.Advanced_Controller_Temp:00000000 Advanced_Controller_Temp /tmp/ccLSPxIe.s:8964 .text.Advanced_Controller_Temp:000000cc $d /tmp/ccLSPxIe.s:8974 .text.CalculateChecksum:00000000 $t /tmp/ccLSPxIe.s:8980 .text.CalculateChecksum:00000000 CalculateChecksum /tmp/ccLSPxIe.s:9025 .text.CheckChecksum:00000000 $t /tmp/ccLSPxIe.s:9031 .text.CheckChecksum:00000000 CheckChecksum /tmp/ccLSPxIe.s:9093 .text.CheckChecksum:0000003c $d /tmp/ccLSPxIe.s:14418 .bss.UART_header:00000000 UART_header /tmp/ccLSPxIe.s:14411 .bss.CS_result:00000000 CS_result /tmp/ccLSPxIe.s:9100 .rodata.SD_SAVE.str1.4:00000000 $d /tmp/ccLSPxIe.s:9104 .text.SD_SAVE:00000000 $t /tmp/ccLSPxIe.s:9110 .text.SD_SAVE:00000000 SD_SAVE /tmp/ccLSPxIe.s:9179 .text.SD_SAVE:00000030 $d /tmp/ccLSPxIe.s:9186 .text.SD_READ:00000000 $t /tmp/ccLSPxIe.s:9192 .text.SD_READ:00000000 SD_READ /tmp/ccLSPxIe.s:9270 .text.SD_READ:0000003c $d /tmp/ccLSPxIe.s:9278 .text.SD_REMOVE:00000000 $t /tmp/ccLSPxIe.s:9284 .text.SD_REMOVE:00000000 SD_REMOVE /tmp/ccLSPxIe.s:9352 .text.SD_REMOVE:00000034 $d /tmp/ccLSPxIe.s:9359 .text.USART_TX:00000000 $t /tmp/ccLSPxIe.s:9365 .text.USART_TX:00000000 USART_TX /tmp/ccLSPxIe.s:9440 .text.USART_TX:00000028 $d /tmp/ccLSPxIe.s:9445 .text.USART_TX_DMA:00000000 $t /tmp/ccLSPxIe.s:9451 .text.USART_TX_DMA:00000000 USART_TX_DMA /tmp/ccLSPxIe.s:9520 .text.USART_TX_DMA:00000038 $d /tmp/ccLSPxIe.s:9526 .text.Error_Handler:00000000 $t /tmp/ccLSPxIe.s:9532 .text.Error_Handler:00000000 Error_Handler /tmp/ccLSPxIe.s:9563 .text.MX_ADC1_Init:00000000 $t /tmp/ccLSPxIe.s:9568 .text.MX_ADC1_Init:00000000 MX_ADC1_Init /tmp/ccLSPxIe.s:9757 .text.MX_ADC1_Init:000000bc $d /tmp/ccLSPxIe.s:9764 .text.MX_ADC3_Init:00000000 $t /tmp/ccLSPxIe.s:9769 .text.MX_ADC3_Init:00000000 MX_ADC3_Init /tmp/ccLSPxIe.s:9876 .text.MX_ADC3_Init:00000060 $d /tmp/ccLSPxIe.s:9883 .text.MX_USART1_UART_Init:00000000 $t /tmp/ccLSPxIe.s:9888 .text.MX_USART1_UART_Init:00000000 MX_USART1_UART_Init /tmp/ccLSPxIe.s:10287 .text.MX_USART1_UART_Init:0000017c $d /tmp/ccLSPxIe.s:10296 .text.MX_TIM10_Init:00000000 $t /tmp/ccLSPxIe.s:10301 .text.MX_TIM10_Init:00000000 MX_TIM10_Init /tmp/ccLSPxIe.s:10350 .text.MX_TIM10_Init:00000024 $d /tmp/ccLSPxIe.s:10356 .text.MX_UART8_Init:00000000 $t /tmp/ccLSPxIe.s:10361 .text.MX_UART8_Init:00000000 MX_UART8_Init /tmp/ccLSPxIe.s:10422 .text.MX_UART8_Init:00000030 $d /tmp/ccLSPxIe.s:14585 .bss.huart8:00000000 huart8 /tmp/ccLSPxIe.s:10428 .text.MX_TIM8_Init:00000000 $t /tmp/ccLSPxIe.s:10433 .text.MX_TIM8_Init:00000000 MX_TIM8_Init /tmp/ccLSPxIe.s:10542 .text.MX_TIM8_Init:00000064 $d /tmp/ccLSPxIe.s:14613 .bss.htim8:00000000 htim8 /tmp/ccLSPxIe.s:10548 .text.MX_TIM11_Init:00000000 $t /tmp/ccLSPxIe.s:10553 .text.MX_TIM11_Init:00000000 MX_TIM11_Init /tmp/ccLSPxIe.s:10663 .text.MX_TIM11_Init:00000068 $d /tmp/ccLSPxIe.s:14592 .bss.htim11:00000000 htim11 ARM GAS /tmp/ccLSPxIe.s page 692 /tmp/ccLSPxIe.s:10669 .text.MX_TIM4_Init:00000000 $t /tmp/ccLSPxIe.s:10674 .text.MX_TIM4_Init:00000000 MX_TIM4_Init /tmp/ccLSPxIe.s:10829 .text.MX_TIM4_Init:0000009c $d /tmp/ccLSPxIe.s:14620 .bss.htim4:00000000 htim4 /tmp/ccLSPxIe.s:10835 .text.MX_TIM1_Init:00000000 $t /tmp/ccLSPxIe.s:10840 .text.MX_TIM1_Init:00000000 MX_TIM1_Init /tmp/ccLSPxIe.s:11031 .text.MX_TIM1_Init:000000bc $d /tmp/ccLSPxIe.s:14606 .bss.htim1:00000000 htim1 /tmp/ccLSPxIe.s:11037 .text.SystemClock_Config:00000000 $t /tmp/ccLSPxIe.s:11043 .text.SystemClock_Config:00000000 SystemClock_Config /tmp/ccLSPxIe.s:11202 .text.SystemClock_Config:000000ac $d /tmp/ccLSPxIe.s:11208 .text.main:00000000 $t /tmp/ccLSPxIe.s:11214 .text.main:00000000 main /tmp/ccLSPxIe.s:11629 .text.main:00000150 $d /tmp/ccLSPxIe.s:11645 .text.main:00000190 $t /tmp/ccLSPxIe.s:11901 .text.main:000002a0 $d /tmp/ccLSPxIe.s:14475 .bss.CPU_state_old:00000000 CPU_state_old /tmp/ccLSPxIe.s:14469 .bss.UART_transmission_request:00000000 UART_transmission_request /tmp/ccLSPxIe.s:14463 .bss.State_Data:00000000 State_Data /tmp/ccLSPxIe.s:14404 .bss.temp16:00000000 temp16 /tmp/ccLSPxIe.s:11926 .text.main:000002f8 $t /tmp/ccLSPxIe.s:12586 .text.main:000005c4 $d /tmp/ccLSPxIe.s:14314 .bss.LD1_param:00000000 LD1_param /tmp/ccLSPxIe.s:14307 .bss.LD2_param:00000000 LD2_param /tmp/ccLSPxIe.s:14564 .bss.TO6_stop:00000000 TO6_stop /tmp/ccLSPxIe.s:12608 .text.main:0000060c $t /tmp/ccLSPxIe.s:13097 .text.main:00000820 $d /tmp/ccLSPxIe.s:14494 .bss.TIM10_period:00000000 TIM10_period /tmp/ccLSPxIe.s:13120 .text.main:0000086c $t /tmp/ccLSPxIe.s:13632 .text.main:00000b24 $d /tmp/ccLSPxIe.s:14300 .bss.LD_blinker:00000000 LD_blinker /tmp/ccLSPxIe.s:13655 .text.main:00000b78 $t /tmp/ccLSPxIe.s:14033 .text.main:00000d2c $d /tmp/ccLSPxIe.s:14059 .bss.ad9102_wave_written_samples:00000000 $d /tmp/ccLSPxIe.s:14065 .bss.ad9102_wave_expected_samples:00000000 $d /tmp/ccLSPxIe.s:14074 .bss.ad9102_wave_upload_active:00000000 $d /tmp/ccLSPxIe.s:14076 .rodata.ad9102_example2_regval:00000000 $d /tmp/ccLSPxIe.s:14147 .rodata.ad9102_example4_regval:00000000 $d /tmp/ccLSPxIe.s:14218 .rodata.ad9102_reg_addr:00000000 $d /tmp/ccLSPxIe.s:14290 .bss.task:00000000 $d /tmp/ccLSPxIe.s:14297 .bss.LD_blinker:00000000 $d /tmp/ccLSPxIe.s:14304 .bss.LD2_param:00000000 $d /tmp/ccLSPxIe.s:14311 .bss.LD1_param:00000000 $d /tmp/ccLSPxIe.s:14318 .bss.Def_setup:00000000 $d /tmp/ccLSPxIe.s:14325 .bss.Curr_setup:00000000 $d /tmp/ccLSPxIe.s:14332 .bss.LD2_def_setup:00000000 $d /tmp/ccLSPxIe.s:14339 .bss.LD1_def_setup:00000000 $d /tmp/ccLSPxIe.s:14346 .bss.LD2_curr_setup:00000000 $d /tmp/ccLSPxIe.s:14353 .bss.LD1_curr_setup:00000000 $d /tmp/ccLSPxIe.s:14360 .bss.sizeoffile:00000000 $d /tmp/ccLSPxIe.s:14367 .bss.fgoto:00000000 $d /tmp/ccLSPxIe.s:14374 .bss.test:00000000 $d /tmp/ccLSPxIe.s:14383 .bss.fresult:00000000 fresult /tmp/ccLSPxIe.s:14384 .bss.fresult:00000000 $d /tmp/ccLSPxIe.s:14387 .bss.COMMAND:00000000 $d /tmp/ccLSPxIe.s:14394 .bss.Long_Data:00000000 $d /tmp/ccLSPxIe.s:14401 .bss.temp16:00000000 $d ARM GAS /tmp/ccLSPxIe.s page 693 /tmp/ccLSPxIe.s:14408 .bss.CS_result:00000000 $d /tmp/ccLSPxIe.s:14415 .bss.UART_header:00000000 $d /tmp/ccLSPxIe.s:14422 .bss.UART_rec_incr:00000000 $d /tmp/ccLSPxIe.s:14432 .bss.TIM10_coflag:00000000 $d /tmp/ccLSPxIe.s:14438 .bss.u_rx_flg:00000000 $d /tmp/ccLSPxIe.s:14444 .bss.u_tx_flg:00000000 $d /tmp/ccLSPxIe.s:14450 .bss.flg_tmt:00000000 $d /tmp/ccLSPxIe.s:14453 .bss.UART_DATA:00000000 $d /tmp/ccLSPxIe.s:14460 .bss.State_Data:00000000 $d /tmp/ccLSPxIe.s:14470 .bss.UART_transmission_request:00000000 $d /tmp/ccLSPxIe.s:14476 .bss.CPU_state_old:00000000 $d /tmp/ccLSPxIe.s:14482 .bss.CPU_state:00000000 $d /tmp/ccLSPxIe.s:14487 .bss.uart_buf:00000000 uart_buf /tmp/ccLSPxIe.s:14488 .bss.uart_buf:00000000 $d /tmp/ccLSPxIe.s:14491 .bss.TIM10_period:00000000 $d /tmp/ccLSPxIe.s:14498 .bss.TO10_counter:00000000 $d /tmp/ccLSPxIe.s:14505 .bss.TO10:00000000 $d /tmp/ccLSPxIe.s:14512 .bss.TO7_PID:00000000 $d /tmp/ccLSPxIe.s:14519 .bss.TO7_before:00000000 $d /tmp/ccLSPxIe.s:14526 .bss.TO7:00000000 $d /tmp/ccLSPxIe.s:14536 .bss.temp32:00000000 temp32 /tmp/ccLSPxIe.s:14533 .bss.temp32:00000000 $d /tmp/ccLSPxIe.s:14540 .bss.SD_SLIDE:00000000 $d /tmp/ccLSPxIe.s:14547 .bss.SD_SEEK:00000000 $d /tmp/ccLSPxIe.s:14554 .bss.TO6_uart:00000000 $d /tmp/ccLSPxIe.s:14561 .bss.TO6_stop:00000000 $d /tmp/ccLSPxIe.s:14568 .bss.TO6_before:00000000 $d /tmp/ccLSPxIe.s:14575 .bss.TO6:00000000 $d /tmp/ccLSPxIe.s:14582 .bss.huart8:00000000 $d /tmp/ccLSPxIe.s:14589 .bss.htim11:00000000 $d /tmp/ccLSPxIe.s:14596 .bss.htim10:00000000 $d /tmp/ccLSPxIe.s:14603 .bss.htim1:00000000 $d /tmp/ccLSPxIe.s:14610 .bss.htim8:00000000 $d /tmp/ccLSPxIe.s:14617 .bss.htim4:00000000 $d /tmp/ccLSPxIe.s:14624 .bss.hsd1:00000000 $d /tmp/ccLSPxIe.s:14631 .bss.hadc3:00000000 $d /tmp/ccLSPxIe.s:14638 .bss.hadc1:00000000 $d UNDEFINED SYMBOLS HAL_GPIO_WritePin HAL_TIM_Base_Stop_IT HAL_GPIO_Init memset LL_GPIO_Init LL_SPI_Init LL_TIM_Init HAL_GPIO_ReadPin Mount_SD Seek_Read_File Unmount_SD HAL_Delay HAL_ADC_Start HAL_ADC_PollForConversion HAL_ADC_GetValue HAL_ADC_Stop Remove_File Create_File ARM GAS /tmp/ccLSPxIe.s page 694 Write_File_byte Update_File_byte HAL_ADC_Init HAL_ADC_ConfigChannel HAL_RCCEx_PeriphCLKConfig LL_USART_Init HAL_TIM_Base_Init HAL_UART_Init HAL_TIM_ConfigClockSource HAL_TIMEx_MasterConfigSynchronization HAL_TIM_PWM_Init HAL_TIM_PWM_ConfigChannel HAL_TIM_MspPostInit HAL_TIMEx_ConfigBreakDeadTime HAL_RCC_OscConfig HAL_PWREx_EnableOverDrive HAL_RCC_ClockConfig HAL_Init MX_FATFS_Init HAL_TIM_PWM_Start HAL_TIM_Base_Start_IT HAL_TIM_PWM_Stop HAL_TIM_Base_Stop