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pulse modulation added

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This commit is contained in:
Ayzen
2026-09-01 18:08:35 +03:00
parent 42795eb899
commit fd95fe3c56
6 changed files with 179 additions and 13 deletions
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App/Devices/ad9102_device.c
+41 -7
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@@ -44,6 +44,9 @@
#define AD9102_EX2_SAW_CONFIG 0x0200u
#define AD9102_SRAM_PAT_PERIOD_BASE_DEFAULT 0x1u
#define AD9102_SRAM_START_DELAY_BASE_DEFAULT 0x1u
/* Board-level oscillator on the AD9102 CLKIN pin. */
#define AD9102_DAC_CLOCK_MHZ 150u
#define AD9102_SRAM_START_DLY_DEFAULT 0x0000u
#define AD9102_SRAM_RAMP_MIN (-8192)
#define AD9102_SRAM_RAMP_MAX (8191)
@@ -207,10 +210,13 @@ static void ad9102_start_output(void)
HAL_GPIO_WritePin(AD9102_TRIG_GPIO_Port, AD9102_TRIG_Pin, GPIO_PIN_RESET);
}
static void ad9102_configure_sram_playback(uint16_t sample_count, uint8_t hold_cycles)
static void ad9102_configure_sram_playback(uint16_t sample_count,
uint8_t hold_cycles,
uint16_t pat_period_us)
{
uint16_t pat_timebase;
uint32_t pat_period;
uint32_t pat_period_base = AD9102_SRAM_PAT_PERIOD_BASE_DEFAULT;
if (sample_count < 2u)
{
@@ -229,9 +235,6 @@ static void ad9102_configure_sram_playback(uint16_t sample_count, uint8_t hold_c
hold_cycles = 0x0Fu;
}
pat_timebase = (uint16_t)(((uint16_t)(hold_cycles & 0x0Fu) << 8) |
((AD9102_SRAM_PAT_PERIOD_BASE_DEFAULT & 0x0Fu) << 4) |
(AD9102_SRAM_START_DELAY_BASE_DEFAULT & 0x0Fu));
pat_period = (uint32_t)sample_count * (uint32_t)(hold_cycles & 0x0Fu);
if (pat_period == 0u)
{
@@ -242,6 +245,37 @@ static void ad9102_configure_sram_playback(uint16_t sample_count, uint8_t hold_c
pat_period = 0xFFFFu;
}
if (pat_period_us != 0u)
{
/* Repetition period requested in microseconds (0 = back-to-back).
* PAT_PERIOD counts in units of PATTERN_PERIOD_BASE DAC clocks, so
* spread the tick count over the smallest base that fits 16 bits. */
uint32_t period_clocks = (uint32_t)pat_period_us * AD9102_DAC_CLOCK_MHZ;
uint32_t pattern_clocks = (uint32_t)sample_count * (uint32_t)(hold_cycles & 0x0Fu);
if (period_clocks < pattern_clocks)
{
/* Shorter than the pattern itself would truncate it and raise a
* configuration error; fall back to back-to-back playback. */
period_clocks = pattern_clocks;
}
pat_period_base = 1u + ((period_clocks - 1u) / 0xFFFFu);
if (pat_period_base > 0x0Fu)
{
pat_period_base = 0x0Fu;
}
pat_period = (period_clocks + (pat_period_base / 2u)) / pat_period_base;
if (pat_period > 0xFFFFu)
{
pat_period = 0xFFFFu;
}
}
pat_timebase = (uint16_t)(((uint16_t)(hold_cycles & 0x0Fu) << 8) |
((uint16_t)(pat_period_base & 0x0Fu) << 4) |
(AD9102_SRAM_START_DELAY_BASE_DEFAULT & 0x0Fu));
ad9102_write_reg_table(g_ad9102_example2_regval, AD9102_REG_COUNT);
ad9102_stop_output();
ad9102_write_reg(AD9102_REG_WAV_CONFIG, AD9102_EX2_WAV_CONFIG);
@@ -426,7 +460,7 @@ uint16_t ad9102_apply_generated_sram(uint8_t enabled,
amplitude = AD9102_SRAM_DEFAULT_AMPLITUDE;
}
ad9102_configure_sram_playback(sample_count, hold_cycles);
ad9102_configure_sram_playback(sample_count, hold_cycles, 0u);
ad9102_load_sram_ramp(sample_count, triangle_mode, amplitude);
if (enabled != 0u)
@@ -441,7 +475,7 @@ uint16_t ad9102_apply_generated_sram(uint8_t enabled,
return ad9102_read_reg(AD9102_REG_PAT_STATUS);
}
bool ad9102_begin_custom_upload(uint16_t sample_count)
bool ad9102_begin_custom_upload(uint16_t sample_count, uint16_t pat_period_us)
{
if ((sample_count < 2u) || (sample_count > AD9102_SRAM_MAX_SAMPLE_COUNT))
{
@@ -450,7 +484,7 @@ bool ad9102_begin_custom_upload(uint16_t sample_count)
ad9102_stop_output();
ad9102_reset_upload_state();
ad9102_configure_sram_playback(sample_count, AD9102_SRAM_DEFAULT_HOLD);
ad9102_configure_sram_playback(sample_count, AD9102_SRAM_DEFAULT_HOLD, pat_period_us);
ad9102_write_reg(AD9102_REG_PAT_STATUS, 0x0004u);
g_upload_state.expected_samples = sample_count;